Patent ID: 9734921
Date: 2017-08-15
CPC Classifications: G06F,G11C

Claim:
1. A memory integrated circuit, comprising: a memory array having a plurality of columns and a plurality of rows, the memory array comprising at least one repair column comprising at least one repair element, each of the at least one repair elements comprising at least one repair cell; an external command/address interface to receive a command, a row address, and a column address from a source external to the memory integrated circuit, the row address to select a row of the plurality of rows to output a row of data, the column address to select a subset of the row of data; and, an external repair address interface to receive a repair enable indicator and a repair address from the source external to the memory integrated circuit, the repair address corresponding to a column of a subset of the plurality of rows, the memory integrated circuit to determine, based on the command and the repair enable indicator, whether data from the repair column is to be output by the memory.