Patent ID: 9721967
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method of manufacturing a nonvolatile memory device comprising: stacking first insulating layers and second insulating layers, alternately, on a semiconductor substrate; penetrating the first insulating layers and the second insulating layers to form a semiconductor pattern disposed on the semiconductor substrate; forming a trench which is spaced apart from the semiconductor pattern and penetrates the first insulating layers and the second insulating layers; removing the second insulating layers exposed to the trench to form extension portions exposing portions of sidewall of the semiconductor pattern between vertically adjacent ones of the first insulating layers; forming a charge storage layer including a charge blocking layer comprising Al forming a metal liner pattern along the charge storage layer; removing the metal liner pattern disposed on the exposed sidewall of the first insulating layers while the charge blocking layer disposed on the exposed sidewall remains; and forming gate electrodes filling the extension portions in which the metal liner pattern is formed.