Patent ID: 9589806
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method of forming a replacement gate stack for a p-type field-effect transistor (pFET) and an n-type field-effect transistor (nFET), the method comprising: forming an interfacial layer in a first opening over a pFET region and a second opening over a nFET region, each of the first and second openings being positioned in a dielectric layer over the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each opening; forming a pFET work function metal layer over the high-k layer in each opening; forming a first gate electrode layer over the pFET work function metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack for the pFET; removing the first gate electrode layer from the second opening; forming an nFET work function metal layer in the second opening after the removing of the first gate electrode from the second opening; and forming a second gate electrode layer over the nFET work function metal layer, thereby forming a second replacement gate stack for the nFET.