Patent ID: 9613901
Date: 2017-04-04
CPC Classifications: G06F,G11C,H01L

Claim:
1. An electronic device comprising a semiconductor memory unit, wherein the semiconductor memory unit comprises: first lines which extend in a first direction and located at a first level over a substrate, wherein two first lines of the first lines which are adjacent in the first direction are spaced apart by a first gap; second lines which extend in a second direction crossing the first direction and are located at a second level higher than the first level; first memory cells disposed between the first lines and the second lines and disposed in intersection regions between the first lines and the second lines; third lines which extend in the first direction and are located at a third level higher than the second level, wherein one of the third lines overlaps with portions of the two first lines and the first gap between the two first lines; second memory cells disposed between the second lines and the third lines and disposed in intersection regions between the second lines and the third lines; and a third contact which couples the one of the third lines to the substrate, wherein the third contact passes through the first gap.