Patent ID: 9614006
Date: 2017-04-04
CPC Classifications: G11C,H01L

Claim:
1. A method of forming a cross-point memory array, comprising: forming a first level of wordlines over a semiconductor substrate, the wordlines of the first level of wordlines having non-planar upper and lower surfaces; forming a first level of diode dielectric stacks over the first level of wordlines, each of the diode dielectric stacks comprising at least two different dielectric materials in a vertical stack comprising at least three dielectric layers, each of the two different dielectric layers having a different barrier height and being selected from the group consisting of aluminum oxide, silicon oxide, silicon nitride, hafnium oxide and zirconium oxide, a dielectric material nearest the first level of wordlines having the highest barrier height relative to remaining dielectric materials comprised by the diode dielectric stack; forming a conductive material over the first level of diode dielectric stacks; forming a first level of memory elements over the conductive material the conductive material contacting dielectric material of the first level of dielectric stacks and a memory element material of the first level of memory elements; forming a first level of bitlines over the first level of memory elements, the first level of bitlines, first level of memory elements and first level of conductive material forming a first level array of memory components; forming a second level of wordlines over the first level of bitlines; forming a second level of diode dielectric stacks over the second level of wordlines; forming a second level of memory elements over the second level of diode dielectric stacks; and forming a second level of bitlines over the second level of memory elements.