Patent ID: 9641311
Date: 2017-05-02
CPC Classifications: H04B,H04L,H04W

Claim:
1. An integrated circuit (IC) for a backplane serializer/deserializer (SerDes) system, comprising: a first transmitter in a first IC configured to send first data at a data rate on a first channel to a second receiver in a second IC via a first bidirectional link; a first receiver in the first IC configured to receive second data at the data rate on a second channel from a second transmitter in the second IC via a second bidirectional link; a third transmitter in the first IC configured to send third data at the data rate to a fourth receiver in the second IC via a third bidirectional link; and a third receiver in the first IC configured to receive fourth data at the data rate from a fourth transmitter in the second IC via a fourth bidirectional link, wherein the third bidirectional link and the fourth bidirectional link are each configured to transfer the third data and transfer the fourth data at the data rate, wherein the IC is configured to transfer the first data and the second data in full duplex mode by employing four-level pulse-amplitude modulation (PAM-4) to reduce signaling speed of the first bidirectional link and the second bidirectional link without reducing throughput of a lane pair comprising the first bidirectional link and the second bidirectional link, and wherein the first data simultaneously traverses the first channel while the second data traverses the second channel.