Patent ID: 9659895
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A semiconductor package structure, comprising: a body enclosing a semiconductor chip and having a bottom surface; a plurality of first-layer electrical contacts disposed on the bottom surface and electrically connected to the semiconductor chip; a plurality of second-layer electrical contacts disposed on the bottom surface and electrically connected to the semiconductor chip; a plurality of third-layer electrical contacts disposed on the bottom surface and electrically connected to the semiconductor chip; and a plurality of fourth-layer electrical contacts disposed on the bottom surface and electrically connected to the semiconductor chip, the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts being arranged sequentially from outside to inside on the bottom surface in a matrix manner, wherein adjacent ones of the first-layer electrical contacts have two different spacings therebetween, and adjacent ones of the third-layer electrical contacts have the two different spacings therebetween, wherein said two different spacing comprise a first spacing and a second spacing greater than the first spacing.