Patent ID: 9600278
Date: 2017-03-21
CPC Classifications: G06F,H03K

Claim:
1. First, second, and third specialized processing blocks on a programmable integrated circuit device, each of said first, second and third specialized processing blocks comprising: a floating-point arithmetic operator stage; a floating-point adder stage comprising at least one floating-point binary adder; a plurality of block inputs; at least one block output; a direct-connect input; and configurable interconnect that comprises selectable routing connections at least between said direct-connect input and said floating-point adder stage, a first block input of said plurality of block inputs and said floating-point adder stage, a second block input of said plurality of block inputs and said floating-point arithmetic operator stage, said floating-point arithmetic operator stage and said direct-connect output, and said floating-point adder stage and said at least one block output; whereby: said direct-connect input of said first specialized processing block is coupled to said direct-connect output of said second specialized processing block; said direct-connect output of said first specialized processing block is coupled to said direct-connect input of said third specialized processing block; and said first, second, and third specialized processing blocks are together configurable to form at least a portion of a recursive adder tree.