Patent ID: 9535833
Date: 2017-01-03
CPC Classifications: G06F,H03M

Claim:
1. A method of optimizing use of a configuration memory of a reconfigurable processor, the method comprising: analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and details of the configuration memory; scheduling groups of function units (FUs), which will be activated in each cycle of the loop, according to the analyzed parallelism to generate configuration data of each cycle; and sequentially mapping classification letters for classifying the generated configuration data and the groups with respect to the scheduled groups in adjacent cycles in at least one row of the configuration memory, wherein the classification letters are mapped according to a determination of whether regular encoding of the configuration data is possible, based on the architecture and the details of the configuration memory, wherein if the regular encoding is possible, the classification letters are mapped according to a determination of whether the groups are the same in the adjacent cycles, wherein the configuration data is encoded regularly when the configuration data is mapped uniformly on fields of the configuration memory.