Patent ID: 9570579
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of fabricating a gate stack of a semiconductor device, the method comprising: forming a channel that has a channel surface extending in a lateral direction; forming first and second spacers that (i) are parallel, (ii) project upward perpendicularly from the channel surface to first and second top ends of the first and second spacers, and (iii) define a first empty space that is bounded by the first and second spacers and by the channel surface; partially filling the first empty space with a gate insulator that (i) is laterally bounded by the first and second spacers, (ii) extends upward from the channel surface, (iii) has a top surface that is lower than first and second top ends, and (iv) leaves a second empty space that is bounded by the first and second spacers and the gate insulator's top surface; depositing a dummy gate layer in the second empty space, wherein the dummy gate layer includes first and second end sections respectively adjacent the first and second spacers and a middle section laterally between the first and second end sections; and removing the middle section to leave a third empty space bounded by the first and second end sections and the gate insulator's top surface; substantially filling the third empty space with a second metal gate layer; removing the first and second end sections to yield fourth and fifth empty spaces in place of the first and second end sections; and substantially filling the fourth and fifth empty spaces with a first metal gate layer that has a workfunction different from a workfunction of the second metal gate layer.