Patent ID: 9535120
Date: 2017-01-03
CPC Classifications: G01R,G06F

Claim:
1. A method for establishing scan test architecture in an integrated circuit, wherein the integrated circuit comprises a plurality of circuit modules, comprising: performing a scan test architecture establishing process on one of the circuit modules, wherein the step of performing the scan test architecture establishing process further comprises: performing a synthesis process on the circuit module, to obtain a first netlist of the circuit module, wherein the first netlist comprises a circuit under test and a test circuit of the circuit module, wherein the circuit under test comprises a plurality of scan chain circuits, and the test circuit comprises a first pipeline unit, a second pipeline unit, a third pipeline unit coupled between the scan chain circuits and the first pipeline unit, and a fourth pipeline unit coupled between the scan chain circuits and the second pipeline unit; performing an automatic place and route (APR) process on the first netlist, to generate a second netlist, wherein the second netlist does not comprise the first pipeline unit and the second pipeline unit; generating a test netlist according to the second netlist and a clock controller; and performing a design rules check (DRC) process on the test netlist.