Patent ID: 9536839
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: (a) a semiconductor substrate including an alignment mark formation region and an integrated circuit formation region; (b) a MISFET formed over the semiconductor substrate, the MISFET being formed in the integrated circuit formation region; (c) a first wiring layer formed over the MISFET, the first wiring layer formed in the integrated circuit formation region; (d) a plurality of first patterns formed over the semiconductor substrate and in the same layer as the first wiring layer, the plurality of first patterns being formed in the alignment mark formation region; (e) a first interlayer insulating film formed over the semiconductor substrate to cover the first wiring layer and the plurality of first patterns; (f) a second wiring layer formed over the first interlayer insulating film, the second wiring layer being formed in the integrated circuit formation region; and (g) an alignment mark formed over the first interlayer insulating film and in the same layer as the second wiring layer, the alignment mark being formed in the alignment mark formation region, wherein the second wiring layer and the alignment mark are formed of an uppermost layer wiring, wherein the alignment mark formation region has a mark region where the alignment mark is disposed and a background region surrounding the mark region, wherein the plurality of first patterns are disposed under the alignment mark so as to arrange in both of the background region and the mark region in plan view, and wherein the plurality of the first patterns are not connected to any of other wiring layers respectively.