Patent ID: 9691856
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A transistor, comprising: a doped silicon semi-insulating substrate; a buffer layer disposed above the doped silicon semi-insulating substrate; a bottom barrier layer disposed above the buffer layer wherein the bottom barrier layer comprises a material different than the buffer layer; a group III-V material quantum well layer disposed above the bottom barrier layer; a top barrier layer disposed above the group III-V material quantum well layer; a gate stack disposed above the top barrier layer, the gate stack having a bottommost surface, and the gate stack comprising: raised source and drain regions disposed above an etch stop layer disposed above the top barrier layer, the raised source and drain regions disposed on either side of the gate stack, and the raised source and drain regions having a bottommost surface above the bottommost surface of the gate stack; and a metal source contact on the raised source region and a metal drain contact on the raised drain region wherein a top surface of the metal source contact and a top surface of the metal drain contact are coplanar with a top surface of the metal gate electrode and wherein a bottom surface of the metal source contact and a bottom surface of the metal drain contact are above the bottommost surface of the gate stack.