Patent ID: 9705516
Date: 2017-07-11
CPC Classifications: H03B,H03L

Claim:
1. A reconfigurable phase-locked loop integrated circuit coupleable to a reference frequency generator and further coupleable to an inductor, the reconfigurable phase-locked loop integrated circuit comprising: a memory storing a plurality of configuration parameters, at least one configuration parameter of the plurality of configuration parameters specifying a selected output frequency; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the plurality of configuration parameters to configure as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller coupled to the reconfigurable frequency and delay generator and to the plurality of capacitive tuning circuits, the first digital controller further coupleable to receive an input signal from the reference frequency generator having a reference frequency, the first digital controller adapted to access the memory and retrieve the plurality of configuration parameters; when the reconfigurable frequency and delay generator is configured as the ring oscillator, to generate a first plurality of control signals to the reconfigurable frequency and delay generator both to generate the second output signal having the second output frequency in response to the plurality of configuration parameters, and to match a phase of the second output signal to an input signal phase; and when the reconfigurable frequency and delay generator is configured as the delay line circuit, to generate a second plurality of control signals to the plurality of capacitive tuning circuits both to generate the first output signal having the first output frequency in response to the plurality of configuration parameters, and to match a phase of the first output signal to the input signal phase.