Patent ID: 9565762
Date: 2017-02-07
CPC Classifications: H01L,H05K

Claim:
1. A printed circuit board (PCB) structure, comprising: a plurality of dielectric layers including an outer layer, a second layer disposed immediately below the outer layer, and a plurality of internal layers; at least one first power plane disposed on at least one first internal layer; at least one first ground plane disposed on at least one second internal layer; an array of buried vias passing through at least the second layer and configured to respectively connect power pads disposed on the second layer to the at least one first power plane and to connect ground pads disposed on the second layer to the at least one first ground plane, wherein the array of buried vias is defined by columns of pads in which a respective column includes either power pads or ground pads, columns of power pads alternate with columns of ground pads, pads of at least one of a column of power pads and a column of ground pads are staggered with respect to other pads of the at least one of the column of power pads and the column of ground pads on a plane parallel to the plurality of dielectric layers, and the array of buried vias includes: an array of outer layer vias passing through the outer layer and configured to provide an electrical connection between one or more circuit components disposed on the outer layer and the second layer.