Patent ID: 9652243
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A method of predicting out-of-order instruction-level parallelism of threads being executed in a multi-threaded processor, comprising: for each thread, assigning to an instruction a priority to be dispatched to an issue queue for a processor cycle; said assigning comprising determining, using a predictor value in a predictor array, if the instruction is associated with a position in a global completion table having a head segment and a tail segment; wherein instructions associated with the tail segment are prioritized for entry into the issue queue; issuing an instruction; updating a predictor value of the issued instruction, wherein the updating comprises updating the predictor value based on the issued instruction being associated with either the head segment or the tail segment; and thereafter prioritizing, based on the updated prediction value for an instruction, scheduling for future occurrences of the instruction.