Patent ID: 9640663
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A high-voltage FinFET device having LDMOS structure, comprising: a fin structure, having a first-type well region, a second-type well region adjacent to the first-type well region; a trench, formed in the first-type well region of the fin structure and separating the fin structure into a first part and a second part; a drain doped layer, formed in the first part of the fin structure; a source doped layer, formed in the second part of the fin structure and in the second-type well region; a working gate, located on the fin structure across the first-type well region and the second-type well region; a shallow trench isolation structure, located in the trench, and a first dummy gate, located in the trench and on the shallow trench isolation structure.