Patent ID: 9584345
Date: 2017-02-28
CPC Classifications: H04L,H04Q

Claim:
1. A clock recovery system, comprising: an ADC (analog-to-digital converter) circuit configured to sample an analog signal in response to sample a clock signal and generate a digital signal comprising sequence of digital data samples, wherein the analog signal comprises a stream of data symbols, wherein each data symbol comprises a plurality n of symbol components, including at least a first symbol component and a second symbol component, wherein n is an integer equal to or greater than 2, and wherein each digital data sample corresponds to one data symbol in the analog signal; a FFE (feed forward equalizer) circuit configured to remove precursor ISI (intersymbol interference) from the digital data samples and at least partially remove postcursor ISI from the digital data samples, and output FFE equalized data samples; a multi-stage postcursor ISI equalizer circuit configured to remove postcursor ISI from a current FFE equalized data sample, the multi-stage postcursor ISI equalizer circuit comprising: control circuitry configured to process the equalized 2-level digital signal to determine an amount of residual postcursor and precursor ISI of the equalized 2-level digital signal, and to adjust a phase of the sample clock signal that is applied to the ADC circuitry to minimize the residual postcursor and precursor ISI of the equalized 2-level digital signal.