Patent ID: 9672897
Date: 2017-06-06
CPC Classifications: G06F,G11C,H03K

Claim:
1. An integrated circuit, comprising: a memory array defined by a plurality of memory cells arranged in rows and columns to form the memory array, each column including a first group of transistors and a second group of transistors; a plurality of gate terminals shared between adjacent columns of the memory cells; a plurality of inversion stages formed of memory cells modified from the memory cells only in a single one of the columns, the single one of the columns being a middle column among the adjacent columns of the memory cells, gate terminals of the first group of transistors of the middle column being directly coupled only with corresponding gate terminals of the second group of transistors of an adjacent column within the same row, the inversion stages being connected in a loop to form a ring oscillator; and a speed determination circuit configured to determine a speed of the memory cells based on a frequency of the ring oscillator.