Patent ID: 9577960
Date: 2017-02-21
CPC Classifications: G06F,H03K,H03M,H04L

Claim:
1. A universal error-correction circuit with fault-tolerant nature, comprising: an error-correction unit with fault-tolerant nature implemented by a logic gate, wherein digital input signals of the error-correction unit with fault-tolerant nature are separately I wherein a number of the digital input signals that exist in the universal error-correction circuit with fault-tolerant nature is 2k+1, wherein digital output signals of the error-correction unit with fault-tolerant nature are separately O wherein a number of the digital output signals that exist in the universal error-correction circuit with fault-tolerant nature is k, wherein the digital input signals and the digital output signals belong to a set {0,1}, wherein k is a positive integer, wherein the error-correction unit with fault-tolerant nature is configured to: wherein when k=3 in the error-correction unit with fault-tolerant nature, seven corresponding digital input signals are separately I wherein the error-correction unit with fault-tolerant nature comprises three error-correction subunits with fault-tolerant nature, which are separately a first error-correction subunit with fault-tolerant nature, a second error-correction subunit with fault-tolerant nature, and a third error-correction subunit with fault-tolerant nature, each error-correction subunit with fault-tolerant nature is corresponding to three digital input signals and one digital output signal, and each error-correction subunit with fault-tolerant nature comprises a first AND gate, a first OR gate, a second AND gate, and a second OR gate, wherein two input signals of both the first AND gate and the first OR gate are a first digital input signal and a second digital input signal, one input signal of the second AND gate is a third digital input signal, the other input signal of the second AND gate is an output signal of the first OR gate, and an output signal of the second AND gate and an output signal of the first AND gate serve as two input signals of the second OR gate, wherein a first digital input signal, a second digital input signal, and a third digital input signal of the first error-correction subunit with fault-tolerant nature are I wherein a first digital input signal, a second digital input signal, and a third digital input signal of the second error-correction subunit with fault-tolerant nature are I wherein a first digital input signal, a second digital input signal, and a third digital input signal of the third error-correction subunit with fault-tolerant nature are I