Patent ID: 9633960
Date: 2017-04-25
CPC Classifications: G06K,H01L

Claim:
1. A chip with input-output (I/O) pads on the peripheries, comprising: a substrate; a first metal layer, formed above the substrate; an inter-metal dielectric layer, formed above the first metal layer, having a plurality of concave portions formed along the peripheries of the chip so that a portion of the first metal layer is exposed to form an I/O pad in each of the plurality of concave portions, wherein the plurality of concave portions are spaced apart from each other, and the I/O pads have a top surface lower than a top surface of the inter-metal dielectric layer; a second metal layer, formed above the inter-metal dielectric layer; a passivation layer, formed above the second metal layer without covering the plurality of concave portions; wherein the first metal layer and the second metal layer each contains a specific circuit, and wherein the second metal layer extends along the plurality of concave portions and covers the exposed portion of the first metal layer, and together with the first metal layer form the plurality of I/O pads.