Patent ID: 9740491
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A method of processing instructions for execution by a processor, comprising: determining, using grouping logic, whether a first property of a first instruction and a second property of a second instruction in an instruction stream are compatible, wherein the first instruction is a last instruction before a cache boundary and the second instruction is an initial instruction after the cache boundary; grouping, using the grouping logic, the first instruction and the second instruction in a same decode-time instruction optimization group in response to the first and second properties being compatible and a feedback value generated by a feedback function indicating the same decode-time instruction optimization group has been historically beneficial with respect to a benefit metric of the processor; and group, using the grouping logic, the first and second instructions in different decode-time instruction optimization groups, in response to the first and second properties being compatible and the feedback value indicating the grouping of the first and second instructions in the same decode-time instruction optimization group has not been historically beneficial.