Patent ID: 9672872
Date: 2017-06-06
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a multiport memory including: a single port memory including: wherein the plurality of first memory cells each includes: wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter has a second driver transistor and a second load transistor, wherein the respective first word line of the word line groups are electrically coupled to the first and third access transistors of the first memory cells, and the respective second word line of the respective word line groups are electrically coupled to the second and fourth access transistors of the first memory cells, wherein the first and third access transistors and the first driver transistor of each of the first memory cells are disposed in a first well of a first conductive type, wherein the first and the second load transistors of the first memory cells are disposed in a second well of a second conductive type, wherein the second and fourth access transistors and the second driver transistor of each of the first memory cells are disposed in a third well of the first conductive type, and wherein the second well is disposed between the first and the third wells.