Patent ID: 9575900
Date: 2017-02-21
CPC Classifications: G06F

Claim:
1. A digital signal processing system, comprising: a memory device; a memory access controller providing a plurality of channels for accessing the memory device; a plurality of fixed function accelerators, each arranged to only perform a predefined specialised signal processing task and not being capable of changing the task performed, each connected to the memory access controller and each configured to read data from the memory device via one of the channels, perform one or more operations on the data, and write data to the memory device via one of the channels; and a multi-threaded processor coupled to the memory access controller and configured to execute a plurality of threads, each thread arranged to control one of the channels, wherein at least one of the threads is configured to detect an occurrence of an event and, responsive thereto, control provision of data from the memory device to a selected fixed function accelerator using the thread's associated channel.