Patent ID: 9634619
Date: 2017-04-25
CPC Classifications: H01L,H03F,H04B

Claim:
1. A bias circuit for a power amplifier (PA), the bias circuit comprising: a first bias path implemented to couple a base node of an amplifying transistor and a supply node, the first bias path configured to provide a base bias current to the base node, the first bias path including a field-effect transistor (FET) having a source, a drain, and a gate, the source coupled to the supply node, the drain coupled to the base node; and a second bias path implemented to be electrically parallel with the first bias path between the base node and the supply node, the second bias path configured to provide an additional base bias current to the base node under a selected condition, the second bias path including an emitter follower having a collector, an emitter, and a base, the collector coupled to the supply node, the emitter coupled to the base node.