Patent ID: 9548298
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A process of forming an integrated circuit, comprising the steps: providing a substrate comprising a silicon-based semiconductor material; implanting p-type dopants into the substrate to form a first p-type well in an area for an NMOS transistor; implanting n-type dopants into the substrate to form a first n-type well in an area for a PMOS transistor; implanting dopants of a first conductivity type into the substrate to form a collector well of the first conductivity type in an area for a vertical bipolar transistor; implanting dopants of a second, opposite, conductivity type into the substrate to form an extrinsic base of the second conductivity type of the vertical bipolar transistor, and to form an intrinsic base of the second conductivity type of the vertical bipolar transistor, the extrinsic base contacting and laterally surrounding the collector well, the intrinsic base being formed by the dopants of the second type counterdoping an upper portion of the collector well, the extrinsic base having a net average dopant density at least 3 times a net average dopant density of the intrinsic base, a remaining portion of the collector well which has the first conductivity type, below the intrinsic base, providing a collector of the vertical bipolar transistor; forming a gate dielectric layer at a top surface of the substrate over the intrinsic base and extending onto the extrinsic base; forming a gate on the gate dielectric layer, the gate surrounding an area for an emitter of the vertical bipolar transistor, the area for the emitter being laterally separated from the extrinsic base by the intrinsic base around the area for the emitter; and implanting dopants of the first conductivity type into the substrate in the area for the emitter to form the emitter, the emitter having the first conductivity type, the emitter being substantially aligned with the gate and being above a portion of the intrinsic base.