Patent ID: 9612612
Date: 2017-04-04
CPC Classifications: G06F,Y02D

Claim:
1. A wide bandwidth resonant clock distribution comprising: a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit; and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, wherein the tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode, wherein the tunable sector buffer receives an enable signal and the clock signal, wherein the tunable sector buffer comprises a NOR gate that receives the clock signal and an inverted enable signal and provides output to a first inverter, wherein the tunable sector buffer further comprises a NAND gate that receives the clock signal and the enable signal and provides output to a second inverter, wherein the tunable sector buffer comprises a plurality of NOR gate fingers connectable to the clock signal in parallel with the NOR gate, a plurality of first inverter fingers connectable to an output of the NOR gate in parallel with the first inverter, a plurality of NAND gate fingers connectable to the clock signal in parallel with the NAND gate, and a plurality of second inverter fingers connectable to an output of the NAND gate in parallel with the NAND gate.