Patent ID: 9589617
Date: 2017-03-07
CPC Classifications: G06F,G11C,H01L

Claim:
1. An electronic device comprising semiconductor memory, wherein the semiconductor memory includes: a substrate; a dielectric layer formed over the substrate; an array of contact plugs formed in the dielectric layer over a substrate, each contact plug being configured to extend in the dielectric layer along a direction perpendicular to the substrate; an array of variable resistance elements formed over the contact plugs, respectively, each variable resistant element being coupled to a corresponding contact plug and including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer; and an array of third magnetic layer structures formed in the dielectric layer and corresponding to the array of contact plugs, respectively, so that one third magnetic layer structure is formed around a corresponding contact plug and is located outside of a respective variable resistance element coupled to the corresponding contact plug as a separate structure from the respective variable resistance element, wherein each third magnetic layer structure produces a magnetic field in the first magnetic layer of the respective that offsets an influence of a bias magnetic field in the first magnetic layer that is generated by the second magnetic layer.