Patent ID: 9589084
Date: 2017-03-07
CPC Classifications: G06F

Claim:
1. A method for verifying a circuit design, the method comprising: providing first and second prototypes of the circuit; applying a plurality of input signals to the second prototype of the circuit at a first point in time; configuring the second prototype of the circuit to detect a condition; applying the plurality of input signals to the first prototype of the circuit at a second point in time occurring after the first point in time by a predetermined number of cycles of a clock; capturing a design state of the first prototype when the condition is met; capturing at least a first subset of the plurality of input signals during a period defined by the first and second points in time; configuring a hardware emulator to represent the circuit design; loading the captured design state to the hardware emulator; and applying the captured at least first subset of the plurality of input signals to the hardware emulator to verify the circuit design.