Patent ID: 9639649
Date: 2017-05-02
CPC Classifications: G06F,G11C

Claim:
1. A semiconductor memory device comprising: a core section comprising a memory cell array, a sense amplifier adjacent to the memory cell array in a first direction, and a row decoder adjacent to the memory cell array in a second direction; a corner area adjacent section arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder, the corner area adjacent section being arranged opposite to the row decoder across the corner area; a first circuit block and a second circuit block provided in the corner area adjacent section to control the core section; and multiple wiring layers provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.