Patent ID: 9576664
Date: 2017-02-21
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device, comprising: a first connection element; a first channel layer protruding from the first connection element in a first direction; first memory cells surrounding the first channel layer, the first memory cells being stacked along the first channel layer; at least one drain select transistor stacked on the first memory cells and surrounding the first channel layer; a second channel layer protruding from the first connection element in the first direction; second memory cells surrounding the second channel layer, the second memory cells being stacked along the second channel layer; a second connection element connected to the second channel layer; a third channel layer protruding from the second connection element in a second direction that is substantially opposite to the first direction; third memory cells surrounding the third channel layer, the third memory cells being stacked along the third channel layer; and at least one source select transistor surrounding the third channel layer, the at least one source select transistor being stacked at lower portions of the third memory cells.