Patent ID: 9583589
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A method for fabricating a double-recess gate structure for a field effect transistor (FET) device, said method comprising: providing a semiconductor wafer having a plurality of semiconductor layers including a substrate, a channel deposited on the substrate, a barrier layer deposited on the channel and a doped cap layer deposited on the barrier layer; depositing at least one electron-beam lithography (EBL) resist layer on the semiconductor wafer; patterning the at least one EBL resist layer using an electron-beam lithography process to form a wide upper opening in the at least one EBL resist layer and a narrow lower opening in the at least one EBL resist layer, the wide upper opening in the at least one EBL resist layer being wider than the narrow lower opening in the at least one EBL resist layer; performing a first wet etch through the wide upper and narrow lower openings in the at least one EBL resist layer and into the semiconductor wafer to form a first recess in the semiconductor wafer; depositing a dielectric layer over the at least one EBL resist layer and into the first recess; performing a dry etch to remove a portion of the dielectric layer in the first recess to form an opening in the dielectric layer, the opening in the dielectric layer aligns with the narrow lower opening in the at least one EBL resist layer in a vertical direction substantially perpendicular to a top surface of the substrate; performing a second wet etch through the opening in the dielectric layer and into the semiconductor wafer to form a second recess in the semiconductor layer, where the second recess is aligned with the first recess in the vertical direction; depositing a gate metal layer on the FET device so that a first portion of the gate metal layer is deposited in the first and second recesses and in the wide upper and narrow lower openings in the at least one EBL resist layer to form a gate terminal having a T-shape including an upper horizontal portion and a lower vertical portion, where a width of the lower vertical portion is in the range of 25-35 nm; and removing the at least one EBL resist layer to remove a second portion of the gate metal layer on top of the at least one EBL resist layer to define the T-shaped gate terminal.