Patent ID: 9552884
Date: 2017-01-24
CPC Classifications: G11C,H01L

Claim:
1. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a string selection transistor, a ground selection transistor, a plurality of nonvolatile memory cells, a first dummy memory cell and a second dummy memory cell, the ground selection transistor being connected to a source line, and the plurality of memory cells stacked on a direction perpendicular to a substrate, the method comprising: generating a first voltage to the substrate connected to the first memory cell string; supplying a second voltage to a ground selection line connected to the ground selection transistor; and supplying a third voltage to a first dummy word line connected to the first dummy memory cell; then floating the ground selection line; floating the first dummy word line after the floating the ground selection line; and floating a second dummy word line connected to the second dummy memory cell before the floating the first dummy word line.