Patent ID: 9748109
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of manufacturing an integrated circuit device, the method comprising: processing a semiconductor substrate through a series of operations to form a plurality of first features which have co-planar upper surfaces, and to form a plurality of second features which are stacked on the plurality of first features, respectively, wherein the plurality of second features have different thicknesses as measured over the co-planar upper surfaces of the first features, thereby establishing a topographically variable surface which varies in height across the semiconductor substrate; providing a polymer coating over the topographically variable surface; performing chemical mechanical polishing (CMP) to remove a first portion of the polymer coating while leaving a second portion of the polymer coating in place; and etching to effectuate a top-down recessing of the second portion of the polymer coating to below an uppermost surface of the upper surfaces of the plurality of second features.