Patent ID: 9606911
Date: 2017-03-28
CPC Classifications: G06F

Claim:
1. A controller for managing a flash memory module, comprising: a processing circuit configured for recording a plurality of address groups into a plurality of addressing blocks, wherein the processing circuit writes each address group into a physical page of one of the plurality of addressing blocks, and each of the plurality of address groups containing a plurality of address mapping information respectively corresponding to a plurality of sequential logical addresses; and a communication interface for coupling with the processing circuit for receiving a write command with respect to a target logical address from a host device; wherein the processing circuit writes the target logical address and associated data into a destination page of a target data block, retrieves the address mapping information for the target logical address from the plurality of address groups, updates the retrieved address mapping information based on physical location information of the destination page of the target data block, and writes a target address group containing updated address mapping information for the target logical address into a target page of a target addressing block, wherein the processing circuit records N group numberings of N address groups stored in a first addressing block in a physical page of the first addressing block, and wherein the processing circuit is further configured for: