Patent ID: 9536908
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A thin-film transistor array panel, comprising: an insulation substrate; a gate line disposed on the insulation substrate; a gate insulating layer disposed on the gate line; a semiconductor layer disposed on the gate insulating layer; a data line disposed on the semiconductor layer and comprising a source electrode; a drain electrode disposed on the semiconductor layer and facing the source electrode; a first electrode disposed on the gate insulating layer; a first passivation layer disposed on the first electrode and comprising silicon nitride; a second passivation layer disposed on the first passivation layer and comprising silicon nitride; and a second electrode disposed on the first and second passivation layers, wherein a first ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the first passivation layer is different from a second ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the second passivation layer.