Patent ID: 9536994
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer over an insulating surface; forming a gate insulating layer over the semiconductor layer; forming a gate electrode layer over the semiconductor layer with the gate insulating layer provided therebetween; forming an insulating layer over the gate electrode layer; forming a first opening reaching the semiconductor layer by etching the insulating layer and the gate insulating layer by a first lithography step; forming a second opening reaching the semiconductor layer so that the gate electrode layer is between the first opening and the second opening by etching the insulating layer and the gate insulating layer by a second lithography step after formation of the first opening; forming a conductive film simultaneously in the first opening, the second opening, and on the insulating layer; forming a source electrode layer and a drain electrode layer from the conductive film, the source electrode layer and the drain electrode layer filling the first opening and the second opening, respectively; and forming a source wiring layer and a drain wiring layer on and in contact with the source electrode layer and the drain electrode layer, respectively, wherein a distance in a channel formation region length direction between the source electrode layer and the drain electrode layer is shorter than a distance in the channel formation region length direction between the source wiring layer and the drain wiring layer.