Patent ID: 9658280
Date: 2017-05-23
CPC Classifications: G01R,H05K

Claim:
1. A method comprising: a) providing primary assembly process specifications for assembling a circuit board, said specifications including the materials and methods to be used to assemble the board; b) providing secondary repair process specifications for reworking and/or repairing a circuit board assembled by the primary assembly process, said specifications including the materials and methods to be used to rework or repair the board; c) building a group of test circuit boards according to the primary assembly process specifications for the materials and methods to be used to assemble the board, wherein each of said test circuit boards includes a first section having components linked together to provide a one or more functional circuits, wherein each of said test circuit boards includes a second section having components daisy-chained together to provide one or more non-functional circuits, wherein each of said first sections and each of said second sections includes one or more surface insulation resistance (SIR) test patterns effective for assessing surface cleanliness, wherein each of said first sections and each of said second sections includes one or more conductive anodic filament (CAF) test patterns effective for assessing inner layer build quality, and wherein each of said first sections is thermally and electrically isolated from each of said second sections; d) reworking or repairing one or more portions of the first section of a sample of the group of test circuit board according to the secondary repair process specifications for the materials and methods to be used to rework or repair the board, and reworking or repairing one or more portions of the second section of a sample of the group of test circuit board using the secondary repair process specifications for the materials and methods to be used to rework or repair the board; e) optionally separating the first section of one or more of the test boards from the second section of that board; f) exposing samples of the first sections of the test boards processed only by the primary assembly process to test conditions comprising thermal cycle test conditions, humidity test conditions, and vibration test conditions; g) exposing samples of the first sections of the test boards processed by both the primary assembly process and the secondary repair process to test conditions comprising thermal cycle test conditions, humidity test conditions, and vibration test conditions; h) exposing samples of the second sections of the test boards processed only by the primary assembly process to test conditions comprising thermal cycle test conditions, humidity test conditions, and vibration test conditions; i) exposing samples of the second sections of the test boards processed by both the primary assembly process and the secondary repair process to test conditions comprising thermal cycle test conditions, humidity test conditions, and vibration test conditions; j) assessing the circuit performance of at least one functional circuit provided in the first section of a board processed only by the primary assembly process after the exposure to test conditions to evaluate the quality of the primary assembly process with respect to circuit quality; k) assessing the circuit performance of at least one functional circuit provided in the first section of a board processed both by the primary assembly process and by the secondary repair process after the exposure to test conditions to evaluate the quality of the primary assembly process and the secondary repair process with respect to circuit quality; l) assessing the solder joint quality of the non-functional components in the second section of a board processed only by the primary assembly process after the exposure to test conditions to evaluate the quality of the primary assembly process with respect to solder joint quality; m) assessing the solder joint quality of the non-functional components in the second section of a board processed both by the primary assembly process and by the secondary repair process after the exposure to test conditions to evaluate the quality of the primary assembly process with respect to solder joint quality; n) assessing the surface cleanliness of the areas of a test board having an SIR test pattern; o) assessing the inner layer build quality of the areas of a test board having a CAF test pattern.