Patent ID: 9542995
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A sense amplifier circuit configuration enabling reliable operation, comprising: a latch comprising first and second latch node, first and second sensing transistor, first and second load transistor, first and second precharge transistor, first and second column multiplexer transistor, first and second auxiliary sensing transistor serially connected to the first and second sensing transistor, first and second internal node, first and second bitline, an activation transistor; and first and second bitline signal amplification and boosting means; and coupling means to selectively couple said first and second latch nodes to said first and second bitlines via said first and second column multiplexer transistor; and one precharge signal to selectively couple the first and second latch nodes to supply voltage via said first and second precharge transistors; and one activation signal; and a signal delay and signal complementing means to delay and complement said activation signal.