Patent ID: 9741438
Date: 2017-08-22
CPC Classifications: G11C

Claim:
1. A nonvolatile memory device comprising: a memory cell array comprising a plurality of cell strings that include a selected cell string and an unselected cell string that are connected to a first bit-line in common, each of the plurality of cell strings including a string selection transistor (SST) and a plurality of serially-connected nonvolatile memory cells that are stacked on or above a substrate in a direction that is perpendicular to the substrate, the SST of the selected cell string being connected to a selected string selection line (SSL), the SST of the unselected cell string being connected to an unselected SSL, a first memory cell among the plurality of serially-connected nonvolatile memory cells of the selected cell string and a second memory cell among the plurality of serially-connected nonvolatile memory cells of the unselected cell string being connected to a first word-line in common; an address decoder configured to apply a program voltage to the first word-line, and configured to apply a selected SSL voltage to the selected SSL and an unselected SSL voltage to the unselected SSL; a control circuit configured to control a plurality of program loops to program the first memory cell, the plurality of program loops including a corresponding program loop, the control circuit being configured to determine whether to perform a pre-charge operation for each of the plurality of program loops based on a loop number of the corresponding program loop or a level of the program voltage corresponding to the corresponding program loop, the level of the program voltage corresponding to the corresponding program loop becoming higher as the loop number of the corresponding program loop becomes greater, and the pre-charge operation for the corresponding program loop is determined to be formed when the loop number of the corresponding program loop is greater than a reference value; and a read and write circuit configured to apply a pre-charge voltage, wherein if the control circuit determines to perform the pre-charge operation for a first program loop among the plurality of program loops, the address decoder applies the unselected SSL voltage to turn-on the SST of the unselected cell string to the unselected SSL during the first program loop, while the read and write circuit applies the pre-charge voltage to the first bit-line before the address decoder applies the program voltage corresponding to the first program loop to the first word-line during the first program loop, the read and write circuit is further configured to apply a program bit-line voltage to the first bit-line while the address decoder applies the program voltage corresponding to the first program loop to the first word-line during the first program loop, and if the control circuit determines not to perform the pre-charge operation for a second program loop among the plurality of program loops, the unselected SSL voltage to turn-on the SST of the unselected cell string is not applied to the unselected SSL until the program voltage corresponding to the second program loop is applied to the first word-line during the second program loop, wherein the control circuit is further configured to compare the loop number of the corresponding program loop with the reference value to determine whether to perform the pre-charge operation.