Patent ID: 9748254
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate; a plurality of first bit lines comprising a plurality of upper surfaces and a plurality of lower surfaces, wherein the plurality of first bit lines are disposed to align the plurality of upper surfaces substantially in a first plane and to align the plurality of lower surfaces substantially in a second plane; an insulating layer that is provided between the plurality of first bit lines, the insulating layer comprising an upper surface and a lower surface, wherein at least a portion of the lower surface of the insulating layer is provided in a groove of the semiconductor device, wherein the groove is disposed substantially in a third plane below the second plane and the upper surface is substantially in a fourth plane above the first plane; and an ONO film comprising an oxide film, a tunnel oxide film, and a plurality of charge storage layers, and a plurality of channel layers provided on opposing third and fourth faces of the insulating layer and coupled to the respective first bit lines of the plurality of first bit lines, wherein at least a portion of the ONO film is formed on a portion of the plurality of channel layers and at least a portion of a first face of the oxide film is in direct contact with a first face of the tunnel oxide film; and wherein a path of a current flowing through the substrate and between the plurality of first bit lines is lengthened by the portion of the insulating layer provided in the groove.