Patent ID: 9576894
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method for fabricating an integrated circuit, the method comprising: depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer; forming a patterned hard mask overlying the OILD layer to form a first target metal line trench pattern and a second target metal line trench pattern; forming a patterned mask overlying the patterned hard mask and the second target metal line trench pattern to form a target via-hole pattern in the first target metal line trench pattern; forming a via-hole extending through the target via-hole pattern and in the OILD layer; removing the patterned mask overlying the second target metal line trench pattern; forming a metal line trench extending through the second target metal line trench pattern and in the OILD layer; depositing a conductive metal fill in the via-hole for forming a via and in the metal line trench for forming a metal line; and planarizing the conductive metal fill to expose an upper surface portion of the OILD layer.