Patent ID: 9589959
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: a p-type substrate; a pwell formed in said p-type substrate where doping of said pwell is higher than doping of said p-type substrate; an NMOS transistor with a NMOS transistor gate and with N+ doped deep source and drain diffusions formed in the pwell on said p-type substrate; a first nwell formed in said p-type substrate; a PMOS transistor with a PMOS transistor gate and with P+ doped deep source and drain diffusions formed in said first nwell; an ESD diode gate overlapping a portion of a N+ deep diffusion and a portion of a P+ deep diffusion where said N+ deep diffusion and said N+ doped deep source and drain diffusion doping concentrations are equal and where said P+ deep diffusion and said P+ doped deep source and drain diffusion doping concentrations are equal; a low capacitance GS ESD diode selected from the group consisting of: where said N+ deep diffusion is a cathode of said low capacitance GS ESD diode; and where said P+ deep diffusion is an anode of said low capacitance GS ESD diode.