Patent ID: 9693078
Date: 2017-06-27
CPC Classifications: H04N

Claim:
1. A processor implemented method for detecting block errors in a video sequence having a plurality of frames, the frame being composed of a plurality of top fields and a plurality of bottom fields, comprising the steps of: a. detecting a scene change and determining a set of frames corresponding to a single scene; b. detecting motion between two consecutive top fields or between two consecutive bottom fields corresponding to the set of frames determined in step a, and determining one or more blocks in the top field or bottom field having motion, wherein each block is a matrix of predetermined size containing pixels; c. determining one or more candidate blocks within the top field or bottom field determined in step b, comprising the steps of: d. verifying the candidate blocks DCT statistics for determining the blocks with grid pattern block error, comprising the steps of: e. verifying for block variation visibility, comprising the steps of: f. validating the candidate block as an erroneous block if the transitions are greater than a predefined threshold.