Patent ID: 9673391
Date: 2017-06-06
CPC Classifications: G11C,H01L

Claim:
1. A method of forming a semiconductor device, comprising: forming a protection material over a conductive structure disposed on a substrate, wherein the protection material is formed in a memory region and a periphery region of the substrate; etching an opening in the protection material exposing a top surface of the conductive structure in the memory region; depositing a first conductive material in the opening; etching back the deposited first conductive material such that a top surface of the deposited first conductive material in the opening is lower than a top surface of the protection material; forming a resistance variable layer and a second conductive material in the opening on the etched back first conductive material; forming a memory structure by patterning the second conductive material, the resistance variable layer and the protective layer such that a sidewall of each of the second conductive material, the resistance variable layer and the protective layer are coplanar; depositing a dielectric layer over the memory structure and the periphery region of the substrate; and forming a first contact plug in the dielectric layer interfacing with the memory structure and a second, coplanar, contact plug in the dielectric layer of the periphery region of the substrate.