Patent ID: 9696746
Date: 2017-07-04
CPC Classifications: G05F

Claim:
1. A method, comprising: receiving a supply voltage at a first source/drain region of a first transistor and a first source/drain region of a second transistor; generating a first voltage at an output of an operational amplifier that is applied to a pate of the first transistor and a pate of the second transistor; responsive to the supply voltage exceeding the first voltage: clamping a current flowing from the first source/drain region of the third transistor to a second source/drain region of the third transistor as a function of the second voltage applied to the gate of the third transistor and the third voltage applied to the first source/drain region of the third transistor to mitigate an impact of a surge in the supply voltage on an output voltage at the second source/drain region of the third transistor.