Patent ID: 9583502
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device having a memory cell of a non-volatile memory formed in a first region of a semiconductor substrate and a MISFET formed in a second region of the semiconductor substrate, in which the memory cell has a first gate electrode and a second gate electrode adjacent to each other formed over the semiconductor substrate, a first gate insulation film formed between the first gate electrode and the semiconductor substrate, and a second gate insulation film formed between the second gate electrode and the semiconductor substrate and having a charge accumulation portion in an interior, and the MISFET has a third gate electrode formed over the semiconductor substrate and a third gate insulation film formed between the third gate electrode and the semiconductor substrate, the method comprising the steps of: (a) providing the semiconductor substrate; (b) forming a first film for the first gate electrode and the third gate electrode over the main surface of the semiconductor substrate; (c) forming a first insulation film over the first film; (d) patterning the first insulation film and the first film, thereby forming a first lamination pattern comprising the first insulation film and the first gate electrode in the first region, forming a second lamination pattern comprising the first insulation film and a first film pattern in the second region, and forming a third lamination pattern comprising the first insulation film and a first dummy gate electrode in a third region of the semiconductor substrate; (e) removing the first insulation film over the first film pattern and the first insulation film over the first dummy gate electrode while leaving the first insulation film over the first gate electrode; (f) forming a second insulation film for the second gate insulation film over the main surface of the semiconductor substrate so as to cover the first lamination pattern, the first film pattern, and the first dummy gate electrode; (g) forming a second film for the second gate electrode over the second insulation film; (h) etching the second film, thereby forming the second gate electrode on the side wall of the first lamination pattern by way of the second insulation film while leaving the second film; (i) patterning the first film pattern, thereby forming the third gate electrode and a second dummy gate electrode in the second region; (j) forming an interlayer insulation film so as to cover the first lamination pattern, the second gate electrode, the third gate electrode, the first dummy gate electrode, and the second dummy gate electrode; and (k) polishing an upper surface of the interlayer insulation film, wherein an upper part of the first gate electrode is lower than an upper part of the second gate electrode, wherein the first dummy gate electrode is separated from the first gate electrode in a plan view, and wherein the second dummy gate electrode is separated from the second gate electrode in a plan view.