Patent ID: 9734276
Date: 2017-08-15
CPC Classifications: G06F,H01L

Claim:
1. A method of designing a layout of an integrated circuit (IC) in an electronic processor, the method comprising: preparing, using a processor, a standard cell library that stores a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including a plurality of conductive lines that extend in a first direction; placing, using the processor, the first standard cell and the second standard cell to be adjacent to each other at a first boundary parallel to the plurality of conductive lines; and generating, using the processor, a decoupling capacitor by using at least one first conductive line of the plurality of conductive lines when a same voltage is to be applied to a first conductive pattern adjacent to the first boundary in the first standard cell and to a second conductive pattern adjacent to the first boundary in the second standard cell, wherein the at least one first conductive line being adjacent to the first boundary.