Patent ID: 9666518
Date: 2017-05-30
CPC Classifications: H01L,H02S,Y02E

Claim:
1. An electronic device comprising: a substrate having a top surface and a bottom surface opposite to the top surface, a shape in a plan view of the top surface being comprised of a rectangle having a first long side, a second long side, a first short side and a second short side, a first metal pattern formed on the top surface of the substrate; a second metal pattern formed on the top surface of the substrate, and spaced apart from the first metal pattern; a third metal pattern formed on the top surface of the substrate, and spaced apart from the first and second metal patterns; a fourth metal pattern formed on the top surface of the substrate, and spaced apart from the first, second and third metal patterns; a first semiconductor chip mounted on a first region in a surface of the first metal pattern via a first bonding material; a second semiconductor chip mounted on a first region in a surface of the second metal pattern via a second bonding material; a first terminal mounted on a first region in a surface of the third metal pattern via a third bonding material, and connected with the third metal pattern via the third bonding material; a second terminal mounted on a first region in a surface of the fourth metal pattern via a fourth bonding material, and connected with the fourth terminal via the fourth bonding material; a cover member adhered to the substrate, and covering a second region in the surface of the first metal pattern, which is not overlapped with the first semiconductor chip and the first bonding material, a second region in the surface of the second metal pattern, which is not overlapped with the second semiconductor chip and the second bonding material, a second region in the surface of the third metal pattern, which is not overlapped with the first terminal and the third bonding material, a second region in the surface of the fourth metal pattern, which is not overlapped with the second terminal and the fourth bonding material, the first semiconductor chip and the second semiconductor chip; and a sealing material sealing the first semiconductor chip, the second semiconductor chip, a part of the first terminal and a part of the second terminal, wherein, in the plan view, the first region the first metal pattern, the first region of the second metal pattern, the first region of the third metal pattern and the first region of the fourth metal pattern are arranged along the short side of the substrate, wherein, in the plan view, the first region of each of the first and second metal patterns is located between the third metal pattern and the fourth metal pattern, wherein, in the plan view, the first region of the first metal pattern is located between the third metal pattern and the first region of the second metal pattern, wherein no pattern is located between the third metal pattern and the first long side of the substrate, and located between the fourth metal pattern and the second long side, and wherein dimples are formed in each of the second region of the third metal pattern and the second region of the fourth metal pattern, but not formed in each of the first region of the first metal pattern, the first region of the second metal pattern, the first region of the third metal pattern and the first region of the fourth metal pattern.