Patent ID: 9583650
Date: 2017-02-28
CPC Classifications: B82Y,G01N,G02B,G02F,H01L,H04B

Claim:
1. An integrated plasmonic circuit comprising: a lower electrode layer extended in a length direction and made of a metal; at least one pair of semiconductor parts disposed on an upper surface of the lower electrode layer and disposed to be spaced apart from each other in the length direction; an upper electrode layer disposed above the lower electrode layer so as to be spaced apart from the lower electrode layer in a vertical direction, having a lower surface contacting the semiconductor parts, having a spacing part formed at a position between the semiconductor parts to thereby be separated into at least one pair, and made of a metal; and a dielectric layer interposed in a space between the lower electrode layer and the upper electrode layer and configured to accommodate the semiconductor parts therein, wherein a plasmonic signal generated in one of one pair of semiconductor parts is guided through the dielectric layer and is transferred to the other semiconductor part.