Patent ID: 9722015
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method for manufacturing a capacitor structure, comprising: forming a conductive region in a substrate; forming a trench with a bottom portion and an inner sidewall portion in the conductive region; conformally depositing a polysilicon layer over the trench; etching the polysilicon layer to form a spacer over the inner sidewall portion of the trench; conformally depositing a first conductive layer over the bottom portion and the spacer; conformally depositing a first dielectric layer over the first conductive layer; conformally depositing a second conductive layer over the first dielectric layer; and conformally depositing a second dielectric layer over the second conductive layer, wherein the spacer is etched to have an angle in a range of from about 85 to about 89 degrees with respect to the bottom portion of the trench and a flared opening opposite to the bottom portion of the trench.