Patent ID: 9685621
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method for manufacturing a thin film transistor (TFT), comprising steps of: forming patterns of a gate electrode, a source electrode and a drain electrode on a base substrate; and forming a pattern of an active layer and a pattern of a passivation layer covering the active layer by a single patterning process, wherein the passivation layer is made of a negative or positive photoresist, and the active layer is insulated from the gate electrode and electrically connected to the source electrode and the drain electrode, wherein the step of forming the patterns of the active layer and the passivation layer covering the active layer by a single patterning process comprises: wherein after forming the pattern of the passivation layer, the base substrate with the passivation layer is subjected to a high-temperature annealing treatment, and wherein an annealing temperature is a temperature that cures the negative or the positive photoresist that forms the passivation layer.