Patent ID: 9684360
Date: 2017-06-20
CPC Classifications: G06F,Y02D

Claim:
1. A processor comprising: at least one core to execute instructions; a memory coupled to the at least one core, the memory to include a plurality of pages to store information; an integrated sensor hub to interface with a plurality of sensors coupled to the processor, the integrated sensor hub including the memory; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database based at least in part on access information of the metadata, the entry of the database associated with the page of the memory, wherein the page manager is to cause at least a portion of the memory to be dynamically powered off based at least in part on the usage information, wherein the memory comprises a plurality of banks, the page manager to cause a first bank including the page to be powered off when at least a threshold number of pages of the memory have corresponding usage counts less than a usage threshold, and responsive to a page fault that results from a memory access request that misses in the memory, to determine whether a time since a prior page fault is less than a threshold time, and if so, to enable the first bank, and otherwise to maintain the first bank powered off.