Patent ID: 9704884
Date: 2017-07-11
CPC Classifications: G02F,H01L

Claim:
1. A method for manufacturing an array substrate, the method comprising: providing a substrate, and forming a transparent conductive layer and a first metallic layer on the substrate in sequence; forming a photoresist layer on the first metallic layer, patterning the photoresist layer by a photomask, so that the patterned photoresist layer comprising two first sections and one second section, wherein a thickness of the two first sections is greater than a thickness of the second section; patterning the transparent conductive layer and the first metallic layer by two etching processes for forming a common electrode and a light shielding layer, wherein the light shielding layer comprises a first light shielding section, a second light shielding section and an edge section, the first light shielding section, the second light shielding section and the edge section are disposed apart by an interval in a same layer, an orthographic projection of the edge section is at the common electrode, an orthographic projection of the second section is at the edge section, and orthographic projections of the two first sections are at the first light shielding section and the second light shielding section; removing the patterned photoresist layer and the edge section on the common electrode by two etching processes; forming an insulating layer on the light shielding layer and the common electrode; forming a poly-silicon layer by patterning on the insulating layer, wherein the poly-silicon layer comprises a first poly-silicon section and a second poly-silicon section, an orthographic projection of the first poly-silicon section is at the first light shielding section, and an orthographic projection of the second poly-silicon layer is at the second light shielding layer; forming a gate insulating layer on the poly-silicon layer and the insulating layer, forming a hole on the gate insulating layer by a photomask and an etching process and defining a first doping section, wherein the hole passes through the gate insulating layer and the insulating layer and the hole exposes the common electrode, and the first doping section is disposed at two lateral sides of the first poly-silicon section; injecting a first type ion to the first doping section; and forming a second metallic layer at the gate insulating layer, patterning the second metallic layer for forming a gate, and the gate connecting with the common electrode through the hole.