Patent ID: 9673131
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. An apparatus comprising: one or more build-up layers having electrical routing features, wherein a first material of the one or more build-up layers has a first coefficient of thermal expansion (CTE); a die coupled with a first side of the one or more build-up layers; a molding compound to at least partially encapsulate the die, wherein a second material of the molding compound has a second CTE; a solder mask layer of a third material that is different from the first material of the one or more build-up layers and the second material of the molding compound and has a third CTE that corresponds to at least one of the first CTE or the second CTE, wherein the solder mask layer of the third material includes a sheet of glass composed of silica or quartz, the sheet of glass being coupled with a second side of the one or more build-up layers and having openings disposed in the sheet of glass layer to allow coupling of package-level interconnect structures with the electrical routing features through the openings, wherein the silica or quartz has a CTE from 3 to 7 and the sheet of glass has a thickness of the silica or quartz ranging from 15 microns to 50 microns, the second side being disposed opposite to the first side; wherein a pitch between two of the openings is less than or equal to 400 microns; and an opening of the openings has a diameter between 100 and 300 microns.