Patent ID: 9697322
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A system to perform physical synthesis using hierarchical wire-pin co-optimization in a chip design process, the system comprising: a memory device storing computer readable instructions; and a processor executing the computer readable instructions to provide boundary conditions corresponding to each of a plurality of macros of the chip design, the plurality of macros being part of a unit and the boundary conditions provided to each of the plurality of macros including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, perform macro-level physical synthesis at each of the plurality of macros of the unit, provide feedback based on the macro-level physical synthesis performed at each of the plurality of macros to a hierarchical level of the unit corresponding with the plurality of macros, the feedback including proposed new locations for the movable pins of each of the plurality of macros, and perform pin placement at the hierarchical level of the unit for all of the plurality of macros of the unit based on the proposed new locations in the feedback to determine locations for the movable pins, wherein the chip design and the pin placement are physically implemented in an integrated circuit.