Patent ID: 9645437
Date: 2017-05-09
CPC Classifications: G02F

Claim:
1. An array substrate, comprising: a plurality of pixel units defined by a plurality of gate lines and a plurality of data lines intersecting each other, wherein the plurality of pixel units are arranged in a matrix of rows and columns; at least one additional functional area located in each row of the matrix and located in a display region of the array substrate, the at least one additional functional area comprising a gate signal detecting transistor; a detection signal output line; and a preset signal line connected with the detection signal output line; wherein the gate signal detecting transistor comprises a gate electrode, a source electrode and a drain electrode, the gate electrode and the source electrode being directly connected to a gate line of the plurality of gate lines associated with a row in which the gate signal detecting transistor is located, and the drain electrode being directly connected to the preset signal line, and the gate signal detecting transistor is connected to the detection signal output line by the preset signal line.