Patent ID: 9741748
Date: 2017-08-22
CPC Classifications: G02F,H01L

Claim:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a pate line and a gate pad on a substrate; forming a gate insulating layer on the gate line and the gate pad; forming a data line and a data pad on the gate insulating layer; forming an organic layer on the data line and the data pad; forming a first field generating electrode on the organic layer; forming a passivation layer on the first field generating electrode; forming a connecting member on one of the gate pad and the data pad; and forming a second field generating electrode on the passivation layer, wherein: the organic layer is formed in a first portion overlapping the connecting member and a second portion not overlapping the connecting member; a thickness of the first portion of the organic layer is greater than a thickness of the second portion of the organic layer; forming the passivation layer comprises removing the passivation layer in a first region comprising the gate pad and the data pad; and forming the organic layer comprises forming the organic layer in the first region.