Patent ID: 9577075
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming a preliminary fin-type active pattern by partially etching a substrate, the preliminary fin-type active pattern extending in a first direction; forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern; forming a gate structure crossing over the preliminary fin-type active pattern, the gate structure extending a second direction and the preliminary fin-type active pattern having an exposed upper portion not covered by the gate structure; forming a fin-type active pattern having a first region and a second region by etching the exposed upper portion of the preliminary fin-type active pattern, the first region being located below the gate structure and the second region being located at both sides of the gate structure, wherein the first region has sidewall surfaces and the second region has upper surfaces; forming an impurity-doped region at the sidewall surfaces of the first region and at the upper surfaces of the second region by using a plasma doping process; and forming an impurity-doped pattern on the second region by using a selective epitaxial-growth process, wherein an upper surface of the first region is at a first level and the upper surfaces of the second region are at a second level lower than the first level.