Patent ID: 9576912
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A wafer level chip scale package (WLCSP) comprising: a semiconductor substrate; a back end of line (BEOL) layer on said semiconductor substrate, said BEOL layer comprising at least one insulating layer and an uppermost passivation layer, and having a peripheral edge recessed inwardly from an adjacent peripheral edge of said semiconductor substrate; a first dielectric layer over said BEOL layer and wrapping around the peripheral edge of said BEOL layer to confine the peripheral edge of the BEOL layer in compressive stress and having a peripheral edge recessed inwardly from an adjacent peripheral edge of the semiconductor substrate; a redistribution layer over said first dielectric layer; and a second dielectric layer over said redistribution layer and having a peripheral edge recessed inwardly from the adjacent peripheral edge of the first dielectric layer.