Patent ID: 9577650
Date: 2017-02-21
CPC Classifications: H03K,H03L

Claim:
1. A Circuit to indicate when a divided down version of an output signal of a Phase Locked Loop (PLL) has a frequency close enough to the frequency of an input reference clock signal, wherein the circuit evaluates the output signals of the PLL Phase Frequency Detector (PFD) to establish a lock-on signal of the PLL with respect to the input reference clock signal, wherein the PFD provides for an up pulse signal, a down pulse signal, a not-up pulse signal and a not-down pulse signal, wherein the not-up pulse signal and the not-down pulse signal are complementary to the up pulse signal and the down pulse signal, respectively, wherein the circuit comprises a first OR gate receiving the up pulse signal and the down pulse signal and generating ORed up- and down-pulse signals, and a second OR gate receiving the not-up pulse signal and the not-down pulse signal and generating ORed not-up- and not-down- pulse signals, wherein the circuit is further configured to compare the duration of the ORed up- and down-pulse signals with the duration of the ORed not-up- and not-down- pulse signals, and wherein the circuit generates the lock-on signal when the duration of the ORed up- and down- pulse signals are smaller than a certain fraction of the duration of the ORed not-up- and not-down- pulse signals.