Patent ID: 9559025
Date: 2017-01-31
CPC Classifications: G01R,H01L

Claim:
1. An integrated circuit comprising: (a) a die having a top surface and a bottom surface; (b) a top contact point on the top surface and a bottom contact point on the bottom surface; (c) a through silicon via in the die having a top end coupled to the top contact point and a bottom end coupled to the bottom contact point; (d) a first switch having a first lead connected to the bottom contact point, a second lead connected to the bottom end of the through silicon via, a stimulus lead, and a control input; and (e) a scan cell having a reference voltage input, a serial data input, a control input, a response input coupled to between the top contact point and the top end of the through silicon via, a stimulus output connected to the stimulus lead, and a serial data output.