Patent ID: 9595531
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A circuit device comprising: a semiconductor substrate with a conductive source layer to provide a source conductor for a channel; a multitier stack of memory cells, each tier of the multitier stack including a memory cell device; a source gate select polycrystalline (SGS poly) layer over the source layer and between the multitier stack and the source layer, the SGS poly layer to provide a gate select signal to selectively conduct charge from the source conductor to the memory cell devices; and an aluminum oxide (AlOx) layer between the source layer and the SGS poly layer, the AlOx layer to provide an etch stop layer to separate the SGS poly layer from the source layer, wherein the AlOx layer to provide both dry etch selectivity and wet etch selectivity, wherein a channel etch is to etch through the multitier stack of memory cells and the SGS poly layer, and stop at the AlOx layer and not expose the source layer, and wherein a selective gate etch is to etch gate contacts in the memory cells and to etch through the AlOx layer to expose the source layer.