Patent ID: 9588176
Date: 2017-03-07
CPC Classifications: G01R,G11C

Claim:
1. An integrated circuit, comprising: first and second user storage circuits that store first and second user signals in response to a first clock signal; a scan chain comprising first and second scan storage circuits; a first multiplexer to provide the first user signal from the first user storage circuit to the first scan storage circuit in a first mode, wherein the first scan storage circuit stores the first user signal in response to a second clock signal that is different from the first clock signal, and wherein the first multiplexer provides a first scan signal to the first scan storage circuit in a second mode; and a second multiplexer to provide the second user signal from the second user storage circuit to the second scan storage circuit in the first mode, wherein the second multiplexer provides a second scan signal from the first scan storage circuit to the second scan storage circuit in the second mode, and wherein the second scan storage circuit stores the second scan signal in response to the second clock signal.