Patent ID: 9698826
Date: 2017-07-04
CPC Classifications: H03M

Claim:
1. A bit group-unit interleaver, comprising: a first memory configured to store a low-density parity check (LDPC) codeword having a length of 16200 bits and a code rate of 4/15; a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to 360 bits; and a second memory storing the interleaved codeword for providing input bits to a modulator, the modulator performing 256-symbol mapping based on the input bits and providing a modulated signal corresponding to the interleaved codeword, wherein the processor reads the LDPC codeword from the first memory and writes the interleaved codeword to the second memory, wherein the interleaving is performed using the following equation using permutation order: where X wherein the permutation order corresponds to an interleaving sequence represented by the following interleaving sequence ={38 20 0 34 33 41 14 30 44 7 37 8 4 9 43 15 19 32 23 5 22 26 10 12 3 31 36 21 24 11 16 18 17 29 35 42 13 40 1 28 2 25 6 39 27}, wherein the LDPC codeword comprises a systematic part corresponding to information bits and having a length of 4320 bits, a first parity part corresponding to a dual diagonal matrix and having a length of 1080 bits, and a second parity part corresponding to an identity matrix and having a length of 10800 bits, and wherein the interleaving sequence is for a case where the 256-symbol mapping is employed and the modulated signal output from the modulator corresponds to a transmission signal, the transmission signal being transmitted to a reception device.