Patent ID: 9741716
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of forming a vertical FET device and a horizontal FINFET device on a common semiconductor substrate, the method comprising: forming, on the semiconductor substrate, vertical device fins for the vertical FET device and the horizontal FINFET device with a sacrificial layer and a hard mask (HM) layer; forming a vertical FET device doped bottom source and drain (S/D) on the semiconductor substrate; forming a shallow trench isolation (STI) and a bottom spacer by forming the bottom spacer proximate to the vertical FET device doped S/D and a bottom spacer proximate to an oxide layer at a base of the horizontal FINFET device fins, wherein the bottom spacer for the vertical FET device is deposited at the same time as the bottom spacer for the horizontal FINFET device; removing the HM layer and the sacrificial layer for horizontal FINFET device; forming a sacrificial gate; forming an oxide inter dielectric (ILD) layer, and opening the sacrificial gate; forming high-k vertical FET device gate and a high-k horizontal FINFET device gate; and forming contacts for the vertical FET device and the horizontal FINFET device.