Patent ID: 9720691
Date: 2017-08-01
CPC Classifications: G06F,Y02D

Claim:
1. A method comprising: receiving, by a first processor, vector code, wherein the vector code includes a plurality of instructions configured to be compiled for execution by a vector processor; determining, by the first processor during compilation of the vector code, whether at least one instruction of the plurality of instructions is a speculatively uniform instruction, wherein the speculatively uniform instruction is an instruction that cannot be determined to be a uniform operation during compilation and cannot be determined to not be a uniform operation during compilation; generating, by the first processor during compilation of the vector code, uniformity detection code for the at least one speculatively uniform instruction, wherein the uniformity detection code, when executed, is configured to determine whether the at least one speculatively uniform instruction is uniform during runtime; generating, by the first processor during compilation of the vector code, scalar code by scalarizing the at least one speculatively uniform instruction, wherein the scalar code is configured to be compiled by the first processor for execution by a scalar processor, a scalar processing unit of the vector processor, or a vector pipeline of the vector processor; and executing, by the vector processor, the generated uniformity detection code during runtime to determine whether the at least one speculatively uniform instruction is uniform during runtime.