Patent ID: 9548251
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: a substrate; a semiconductor interposer having a cavity, said cavity having a height from a first surface of said semiconductor interposer to a second surface of said semiconductor interposer; an intra-interposer die disposed within said cavity of said semiconductor interposer; a thermally conductive adhesive contacting first and second sides of said semiconductor interposer and said intra-interposer die; a die situated over said first surface of said semiconductor interposer; a first interconnect structure coupled to a first surface of said intra-interposer die and said die; and a second interconnect structure coupled to a second surface of said intra-interposer die and said semiconductor interposer, wherein said intra-interposer die is in electrical communication with said substrate situated below said second surface of said semiconductor interposer by a first electrical connection with said die using said first interconnect structure and by a second electrical connection through said semiconductor interposer using said second interconnect structure.