Patent ID: 9613709
Date: 2017-04-04
CPC Classifications: G11C,H01L

Claim:
1. A method, comprising: manufacturing on a semiconductor substrate a memory cell that includes: forming in the substrate isolating trenches delimiting first and second strips of the substrate, making the second strip permanently conductive by doping the second strip, forming a first dielectric layer on the substrate and forming the floating gate of the first floating gate transistor on the first dielectric layer, the floating gate being arranged transversally to the two strips of substrate, forming a second dielectric layer on the floating gate of the first floating gate transistor and forming the control gate of the first floating gate transistor on the floating gate with of the first floating gate transistor, to obtain a gate stack, and doping the first and second strips of substrate on opposite sides of the gate stack, thereby generating drain and source regions of the first floating-gate transistor and a drain region of the second floating-gate transistor, the permanently conducting region opposite the floating gate of the second floating-gate transistor being formed by a region of the second strip, which is doped before forming the gate stack.