Patent ID: 9559000
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method comprising: forming a first opening in a dielectric layer, the first opening is located in an SRAM device region of a semiconductor structure and exposes a portion of an SRAM source drain region and a portion of an SRAM gate cap, the portion of the SRAM source drain region and the portion of the SRAM gate cap are both of an SRAM finFET device located in the SRAM device region; forming a second opening in the dielectric layer, the second opening is located in a logic device region of the semiconductor structure and exposes a portion of a logic source drain region and a portion of a logic gate cap, the portion of the logic source drain region and the portion of the logic gate cap are both of a logic finFET device located in the logic device region; forming a first contact by filling the first opening with a conductive material; forming a second contact by filling the second opening with the conductive material; forming a third opening in the dielectric layer, the third opening is adjacent to the first opening and exposes a portion of a titanium nitride SRAM gate, a portion of an SRAM gate dielectric layer and a portion of an SRAM gate sidewall spacer, all of the SRAM finFET device, wherein a sidewall of the first contact is exposed within the third opening, and wherein a portion of the SRAM gate cap remains directly beneath a portion of the first contact; forming a fourth opening in the dielectric layer, the fourth opening is adjacent to the second opening and exposes a portion of a titanium nitride logic gate, a portion of a logic gate dielectric layer and a portion of a logic gate sidewall spacer, all of the logic finFET device, wherein a sidewall of the second contact is exposed within the fourth opening, and wherein a portion of the logic gate cap remains directly beneath a portion of the second contact; forming a first pair of sidewall spacers on opposite sidewalls of the third opening, wherein one of the first pair of sidewall spacers is in direct contact with the first contact and vertically extends upward from the exposed surface of the SRAM gate to a top surface of the first contact; forming a second pair of sidewall spacers on opposite sidewalls of the fourth opening, wherein one of the second pair of sidewall spacers is in direct contact with the second contact and vertically extends upward from the exposed surface of the logic gate to a top surface of the second contact; depositing a hard mask in the logic device region, wherein the hard mask covers the second pair of sidewall spacers; recessing a portion of each of the first pair of sidewall spacers, wherein the sidewall of the first contact is re-exposed while the second pair of sidewall spacers remain protected by the hard mask; removing the hard mask from the logic device region; forming a third contact by filling the third opening with the conductive material, wherein the third contact is in direct contact with the first contact and forms an electrical connection between the SRAM source drain region and the titanium nitride SRAM gate, wherein the electrical connection is directly above a remaining portion of the first sidewall spacer; and forming a fourth contact by filling the fourth opening with the conductive material, wherein the second sidewall spacer electrically isolates the fourth contact from the second contact such that the logic source drain region remains electrically isolated from the titanium nitride logic gate.