Patent ID: 9576967
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A monolithic three-dimensional memory device comprising: at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor substrate; memory openings extending through the at least one alternating stack, wherein each of the memory openings is filled with an epitaxial channel portion contacting the semiconductor substrate and a memory stack structure; and support openings extending through the at least one alternating stack, wherein each of the support openings is filled with a support pillar structure, wherein: each of the memory stack structures and the support pillar structures comprise an instance of a layer stack including charge storage material portions, a tunneling dielectric layer, and at least one vertical semiconductor layer; each instance of the layer stack in the memory stack structures is vertically spaced from the semiconductor substrate by a respective epitaxial channel portion; and each instance of the layer stack in the support pillar structures is in physical contact with an impurity-doped semiconductor material portion within the semiconductor substrate.