Patent ID: 9742523
Date: 2017-08-22
CPC Classifications: H04L,H04N,Y02D

Claim:
1. A network controller, comprising: physical interface (PHY) circuitry comprising receiver circuitry to receive backchannel information from a link partner in communication with the receiver circuitry over a channel link; link speed cycling circuitry to cause the receiver circuitry to receive the backchannel information from the link partner using at least one high rate link speed, the backchannel information being included in a low rate (LR) bit stream modulated onto at least one first high rate (HR) bit sequence; and demodulation circuitry to demodulate the HR bit sequence to recover the LR bit stream based, at least in part, on detecting an existence of or an absence of a transition between a true HR bit sequence and a complementary HR bit sequence.