Patent ID: 9614143
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A semiconductor device including a magnetic tunnel junction (MTJ) region and a logic region adjacent to the MTJ region, the device comprising: a magnetoresistive random-access memory (MRAM) trench within the MTJ region of the semiconductor device, the MRAM trench comprising a first conductive barrier liner and a second conductive barrier liner, the MRAM trench having a flat portion landing no deeper than an adjoining surface of a hard mask and an encapsulation layer of an MTJ within the MTJ region of the semiconductor device, in which the second conductive barrier liner is on sidewalls and a surface of the MRAM trench, and the first conductive barrier liner is on the second conductive barrier liner; a logic trench comprising the first conductive barrier liner; and a logic via comprising the first conductive barrier liner, the logic via landing on a first portion of a conductive interconnect (Mx) within the logic region of the semiconductor device.