Patent ID: 9659621
Date: 2017-05-23
CPC Classifications: G11C

Claim:
1. A memory system, comprising: first and second semiconductor memories each including a plurality of memory cells disposed along rows and columns, each row in a first plurality of memory cells of the first semiconductor memory having a corresponding row having a same location in a second plurality of memory cells of the second semiconductor memory; and a memory controller coupled to the first and second semiconductor memories and configured to provide a common address, first group scramble information, first chip scramble information, and second chip scramble information to the first and second semiconductor memories, wherein the first semiconductor memory is configured to access a first row of memory cells in the first semiconductor memory based on the common address, the first group scramble information and the first chip scramble information, and the second semiconductor memory is configured to access a second row of memory cells in the second semiconductor memory based on the common address, the first group scramble information and the second chip scramble information, wherein a first location of the first row in the first semiconductor memory is different from a second location of the second row in the second semiconductor memory, wherein row addresses of rows adjacent to the first row of memory cells in the first semiconductor memory are different from row addresses of rows in the first plurality of memory cells of the first semiconductor memory that correspond to rows in the second plurality of memory cells of the second semiconductor memory adjacent to the second row of memory cells of the second semiconductor memory, wherein the memory system further comprises third and fourth semiconductor memories configured to receive a second common address, second group scramble information, the first chip scramble information, and the second chip scramble information from the memory controller, wherein the third semiconductor memory is configured to access a third row based on the second common address, the second group scramble information and the first chip scramble information, and the fourth semiconductor memory is configured to access a fourth row based on the second common address, the second group scramble information and the second chip scramble information, and wherein a third location of the third row is different from the first location when the second common address is identical to the common address, and a fourth location of the fourth row is different from the third location.