Patent ID: 9671685
Date: 2017-06-06
CPC Classifications: G03F

Claim:
1. A method comprising: receiving a mask fabricated according to an integrated circuit (IC) design pattern; extracting a mask pattern from a mask image of the fabricated mask by converting a mask image of the fabricated mask into an IC design format; converting the mask pattern in the IC design format into a rendered mask pattern, wherein the rendered mask pattern simulates the IC design pattern and any defects in the mask, and further wherein the converting includes applying a model to map edge contours of the mask pattern into polygons; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; determining whether any defects in the mask are critical based on the virtual wafer pattern; and repairing any defects in the mask that are determined to be critical based on the virtual wafer pattern and any defects indicated as critical in a repair reference report associated with the fabricated mask.