Patent ID: 9679833
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: a lead frame having a die pad; a semiconductor chip having a top surface and a bottom surface; the bottom surface of the semiconductor chip being directly attached to a top surface of the die pad; the top surface of the semiconductor chip having a gate electrode and a source electrode; and the bottom surface of the semiconductor chip having a drain electrode; a gate lead; a metal gate clip having a first end bottom surface, a mid-range bottom surface and a second end side surface; the first end bottom surface of the metal gate clip being directly attached to the gate electrode of the semiconductor chip; and the mid-range bottom surface of the metal gate clip being directly attached to the gate lead; a molding encapsulation covering a top surface of the lead frame and enclosing the semiconductor chip, at least a majority portion of the gate lead and at least a majority portion of the metal gate clip; wherein the second end side surface of the metal gate clip is exposed from the molding encapsulation; and wherein the mid-range bottom surface of the metal gate clip is located at a height lower than the first end bottom surface and the second end side surface of the metal gate clip.