Patent ID: 9646934
Date: 2017-05-09
CPC Classifications: G03F,H01L

Claim:
1. An integrated circuit comprising: a base dielectric layer; a first dielectric layer overlying the base dielectric layer; a second dielectric layer overlying the first dielectric layer; a first overlay mark pattern positioned within the first dielectric layer; a second overlay mark pattern positioned within the second dielectric layer, wherein the second overlay mark pattern is offset from the first overlay mark pattern; and a first block and a second block positioned within the base dielectric layer, wherein the first overlay mark pattern directly overlays the first block, wherein the first block comprises a first block geographic center, wherein the second overlay mark pattern directly overlays the second block, wherein the first block comprises a first block upper surface that is dished with a trough area and a curved area, wherein the first block geographic center is within the trough area, and wherein the curved area of the first block upper surface is symmetric with the first overlay mark pattern.