Patent ID: 9673286
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A group III-V transistor comprising: a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG); a source electrode, a drain electrode, and a gate situated over said group III-V heterostructure; an insulator layer over said group III-V heterostructure and situated between said gate and said drain electrode, wherein a gate-facing end of said insulator layer is in contact with, and terminates at, a side surface of said gate, wherein a drain electrode-facing end of said insulator layer is in contact with a side surface, and a portion of an upper surface, of said drain electrode; a semiconductor field plate situated between said gate and said drain electrode, over said insulator layer, wherein a gate-facing end of said semiconductor field plate is in contact with said side surface, and a portion of an upper surface, of said gate, wherein a drain electrode-facing end of said semiconductor field plate is in contact with a portion of the upper surface of said drain electrode; wherein said semiconductor field plate adjoins said drain electrode.