Patent ID: 9594117
Date: 2017-03-14
CPC Classifications: G01R,Y10T

Claim:
1. A method comprising: a first test structure comprising at least one first interface section and a second interface section, wherein said second interface section comprises an integrated circuit interface section comprising a plurality of programmable input and output elements, wherein said integrated circuit interface section is adapted to removably and electrically connect or release one or more said input and output elements with one or more input and output elements of a device under test (DUT), receive inputs and outputs from said DUT, process said inputs and outputs, and output processed data; a second test structure comprising: a third interface section adapted to selectively and removably electrically couple with said first interface section of said first structure; a communication protocol section adapted to transmit data from said FPGA through a communication signal data interface adaptor to a computer adapted to analyze said data.