Patent ID: 9665478
Date: 2017-05-30
CPC Classifications: G06F,G11C

Claim:
1. A non-volatile memory system, comprising: a memory circuit, including: a memory controller circuit that controls writing of data into addressed blocks, reading data from addressed blocks and erasing data from one or more of addressed blocks at a time, wherein the one or more physical memory arrays are subdivided by the controller into logical zones each comprised of a plurality of physical blocks by introducing logical boundaries of the one or more physical memory arrays for address translation within which logical to physical block translations are performed for the plurality of physical blocks thereof, and where the logical zones correspond to contiguous physical spaces by introducing beginning and end physical block addresses for the logical zones, wherein the memory controller circuit can adjust said logical boundaries and update said correspondence in response to identifying one or more of said physical blocks as defective based on the distribution of the identified defective physical blocks while maintaining a correspondence of physical blocks to logical zones corresponding to contiguous physical spaces.