Patent ID: 9685221
Date: 2017-06-20
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A memory control circuit unit, configured to control a volatile memory, the memory control circuit unit comprising: a processor core; a memory controller, coupled to the processor core; and a memory interface, coupled to the memory controller and the volatile memory, wherein the memory interface comprises: a first connection interface, configured to couple to the memory controller; a second connection interface, configured to couple to the volatile memory; and a reference voltage generator, coupled to the first connection interface and the second connection interface, wherein the reference voltage generator is configured to detect the first impedance characteristic of the memory controller via the first connection interface, detect the second impedance characteristic of the volatile memory via the second connection interface and generate the internal reference voltage according to the detection result, wherein a voltage value of the internal reference voltage is positively correlated to a voltage value of a supply voltage of the memory controller, and the internal reference voltage is for resolving a data signal received by the memory interface.