Patent ID: 9583570
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first oxide semiconductor layer; a second oxide semiconductor layer over and in contact with the first oxide semiconductor layer; a third oxide semiconductor layer over and in contact with the second oxide semiconductor layer; a pair of electrode layers in contact with the third oxide semiconductor layer; a gate electrode layer, wherein the gate electrode layer, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer overlap each other; and a gate insulating film between the gate electrode layer and the pair of electrode layers, wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium, gallium, and zinc, wherein a conduction band of each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than a conduction band of the second oxide semiconductor layer, wherein the third oxide semiconductor layer covers side surfaces of the second oxide semiconductor layer, wherein one of the pair of electrode layers and the gate electrode layer overlap each other, and wherein the other of the pair of electrode layers and the gate electrode layer overlap each other.