Patent ID: 9711377
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: (a) providing a semiconductor wafer including a main surface, a first electrode pad formed over the main surface, a second electrode pad formed over the main surface and also arranged next to the first electrode pad in plan view, and a first insulating member including a first opening that exposes an upper surface of the first electrode pad and a second opening that exposes an upper surface of the second electrode pad; (b) after (a), forming a second insulating member over the first insulating member of the semiconductor wafer, and forming a third opening that exposes the upper surface of the first electrode pad and a fourth opening that exposes the upper surface of the second electrode pad, in the second insulating member; (c) after (b), bringing probe needles into contact with the first and second electrode pads, respectively, thereby writing data in a memory circuit of the semiconductor wafer; (d) after (c), within the third opening and the fourth opening, covering the upper surface of the first electrode pad and the upper surface of the second electrode pad with a first cover film and a second cover film, respectively; (e) after (d), forming a first wiring and a second wiring over a surface of the first cover film and a surface of the second cover film, respectively; and (f) after (e), covering the surface of the first cover film, the surface of the second cover film, the first wiring and the second wiring with a third insulating member, and forming a fifth opening that exposes a first part of the first wiring and a sixth opening that exposes a first part of the second wiring, in the third insulating member, wherein, in plan view, the first electrode pad and the second electrode pad are arranged along a first direction, wherein each of the first cover film and the second cover film is comprised of a conductive material, wherein the first part of the first wiring is located outside of the third opening in plan view and is formed over the second insulating member, wherein the first wiring has a second part located within the third opening in plan view, wherein the first part of the second wiring is located outside of the fourth opening in plan view and is formed over the second insulating member, wherein the second wiring has a second part located within the fourth opening in plan view, wherein, in plan view, a width of the second part of the first wiring in the first direction is equal to or smaller than a width of the third opening formed in the second insulating member, wherein, in plan view, a width of the second part of the second wiring in the first direction is equal to or smaller than a width of the fourth opening formed in the second insulating member, and wherein in (b) a heat treatment is performed.