Patent ID: 9721668
Date: 2017-08-01
CPC Classifications: G11C,H01L

Claim:
1. A memory device, comprising: a plurality of blocks of memory cells, bit lines, word lines and sub-block reference lines; each block in the plurality being operably coupled to a set of X bit lines BL(x), a set of Z word lines WL(z), and a set of Y sub-block reference lines RL(y), where Y is two or more, and each block including: an array of NAND strings including a plurality of rows and a plurality of columns of NAND strings, each NAND string in the array including memory cells coupled to each word line WL(z) in the set of Z word lines, the NAND strings in the array having respective first select switches and second select switches; a string select line set including N string select lines coupled to gates of the first select switches of NAND strings in corresponding columns of the NAND strings in the array, each string select line SSL(n) in the string select line set configured to control the first switches in one column of the NAND strings in the array for selective connection to corresponding bit lines BL(x) in the set of X bit lines;