Patent ID: 9748145
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device, the method comprising: providing a structure with at least one region and including a dielectric layer disposed over a substrate. wherein the at least one region is present in an opening located in an interlaver dielectric material that is disposed directly on the substrate; forming a multilayer stack structure comprising a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure comprising a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold-voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, wherein a threshold voltage of the first region is independent of the threshold voltage of the second region.