Patent ID: 9672927
Date: 2017-06-06
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor storage device, comprising: a plurality of peripheral circuits on a semiconductor substrate; a memory cell array having a plurality of semiconductor layers above the peripheral circuits, the memory cell array including first to third regions, the first to third regions including a plurality of memory strings, the second region being adjacent to the first region and the third region; a plurality of upper bit lines disposed above the memory cell array and extending in a first direction above the first to third regions, the upper bit lines including a plurality of first bit lines, a plurality of second bit lines, a plurality of third bit lines, each of the second bit lines being adjacent in a second direction to one of the first bit lines and one of the third bit lines, the second direction crossing the first direction, each of the upper bit lines being electrically connected to at least one of the peripheral circuits, a plurality of first contact plugs provided in a first connection part, each of the first bit lines electrically connected to at least one of peripheral circuits via one of the first contact plugs; a plurality of second contact plugs provided in a second connection part, each of the second bit lines electrically connected to at least one of peripheral circuits via one of the second contact plugs; a plurality of third contact plugs provided in a third connection part, each of the third bit lines electrically connected to at least one of peripheral circuits via one of the third contact plugs; wherein the first to third connection parts is provided separately in the first direction.