Patent ID: 9658501
Date: 2017-05-23
CPC Classifications: G02F,H01L

Claim:
1. A method for producing a fringe field switching (FFS) array substrate, comprising steps of: (1) forming a metal layer on an array substrate, and obtaining a gate electrode and a common electrode line by a patterning process; (2) forming a gate electrode insulating layer on the gate electrode and the common electrode line, the gate electrode insulating layer entirely covering the array substrate; (3) forming a layer of pixel electrode ITO on the gate electrode insulating layer between the gate electrode and the common electrode line; (4) forming a semiconductor active layer on a location of the gate electrode insulating layer corresponding to the gate electrode, and a cross-sectional width of the semiconductor active layer being less than a cross-sectional width of the gate electrode; (5) forming a source electrode and a drain electrode on the semiconductor active layer and the gate electrode insulating layer, and the drain electrode overlapping and contacting a portion of the pixel electrode ITO and the drain electrode being on the pixel electrode ITO; (6) forming an insulating protective layer on the source electrode, the drain electrode, the semiconductor active layer, the pixel electrode ITO and the gate electrode insulating layer, and forming a via structure on the gate electrode insulating layer and the insulating protective layer on the common electrode line, and a cross-sectional width of the via structure being less than a cross-sectional width of the common electrode line; (7) forming a common electrode on the insulating protective layer and the via structure corresponding to the pixel electrode ITO.