Patent ID: 9627273
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming a first semiconductor material layer in a first region and a second region of a substrate; forming a second semiconductor material layer on the first semiconductor material layer, the second semiconductor material layer including a material different from the first semiconductor material and having a thickness in the second region greater than a thickness in the first region; patterning the first and second semiconductor material layers to form first and second nanowire structures having a first width in a horizontal region respectively in the first region and the second region; selectively removing the first semiconductor material layer in the first and second nanowire structures to respectively form a first nanowire pattern in the first region of the substrate and to form a second nanowire pattern in the second region of the substrate, the first nanowire pattern having a first width in a horizontal direction of a cross-section of the first nanowire pattern and a first vertical length in a vertical direction of the cross-section of the first nanowire pattern, the second nanowire pattern having a first width in the horizontal direction of a cross-section of the second nanowire pattern and a second vertical length greater than the first vertical length in the vertical direction of the cross-section of the second nanowire pattern; forming a first MOS transistor including a first gate structure and first source/drain regions in the first nanowire pattern; and forming a second MOS transistor including a second gate structure and second source/drain regions in the second nanowire pattern.