Patent ID: 9748173
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising: forming a trench in at least one dielectric layer; conformally depositing a first conductive layer on a top surface of the at least one dielectric layer, and on sidewall and bottom surfaces of the trench; reflowing the first conductive layer to increase an amount of the first conductive layer in the trench, and partially fill the trench with the first conductive layer; conformally depositing a liner layer on the first conductive layer on the top surface of the at least one dielectric layer, and on the sidewall and bottom surfaces of the trench; forming a second conductive layer on the liner layer on the top surface of the at least one dielectric layer, and filling a remaining portion of the trench; removing the first conductive layer, the liner layer and the second conductive layer from the top surface of the at least one dielectric layer; determining a range of an aspect ratio of the second conductive layer in the trench to result in columnar grain boundaries in the second conductive layer; and determining a height of the first conductive layer in the trench needed to yield the determined range of the aspect ratio; wherein the reflowing of the first conductive layer increases the height of the first conductive layer in the trench to at least the height needed to yield the determined range of the aspect ratio; and wherein the first conductive layer comprises aluminum.