Patent ID: 9716117
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A method for producing an array substrate comprising: forming in sequence from bottom to top a metal layer comprising a pattern of a gate line and a gate, a gate insulating layer and an active layer on a substrate base; forming a metal layer comprising a pattern of a source and a drain; forming a protective layer covering the substrate and a first passivation layer comprising a first via located above the drain and exposing the protective layer; forming a first metal layer comprising a pattern of a first electrode; forming a second passivation layer; wherein the method for producing an array substrate further comprises the following steps of: producing a second via located above the drain in the second passivation layer; and forming a second metal layer comprising a pattern of a second electrode to realize electrical connection between corresponding electrode patterns, wherein producing the second via comprises the following steps of: employing a first etching process to partially etch the second passivation layer in an area that needs to form a via above the drain, wherein the vertical etching amount achieved by employing the first etching process is less than the thickness of the second passivation layer; and employing a second etching process for which the vertical etching rate is larger than the lateral etching rate to etch the remaining part in the area that needs to form a via, until the drain is exposed, wherein a material of the second passivation layer is silicon nitride, and wherein each of the first etching process and the second etching process is a fluorine based etching process.