Patent ID: 9553716
Date: 2017-01-24
CPC Classifications: H04L

Claim:
1. A network receiver for a network using distributed clock synchronization, the network receiver comprising: an input for receiving an input signal from the network, the input signal representing a series of bits; an internal clock for generating a clock signal, the internal clock being configured to receive a frequency adjustment signal for adjusting a frequency of the clock signal; a clock bit comparator configured to compare a length of a first time period lapsed while receiving at least five consecutive bits of the input signal with a length of an internal clock time interval being a sub-interval of the clock signal and representing the same number of bits as a number of bits of the first time period and the clock bit comparator being configured to generate a difference signal indicating a difference between the lengths of the first time period and the internal clock time interval; and an adjustment signal generator configured to receive the difference signal and configured to generate the frequency adjustment signal for controlling the frequency of the clock signal towards a frequency which reduces the difference between the lengths of the first time period and the internal clock time interval.