Patent ID: 9620420
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor arrangement comprising: forming a first set of one or more fins and a second set of one or more fins, the first set of one or more fins spaced apart from the second set of one or more fins by a first dielectric; forming a second dielectric over the first set of one or more fins, the second set of one or more fins, and the first dielectric; etching a first opening in the second dielectric, the first opening extending over the first set of one or more fins, the second set of one or more fins, and the first dielectric; and forming a first metal connect in the first opening, the first metal connect extending over the first set of one or more fins, the second set of one or more fins, and the first dielectric to form an electrical connection between the first set of one or more fins and the second set of one or more fins.