Patent ID: 9711462
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A package arrangement, comprising: at least one chip; encapsulation material at least partially encapsulating the chip; a redistribution structure over a first side of the chip; a metal structure over a second side of the chip, wherein the second side is opposite the first side; and a semiconductor structure electrically coupled to the redistribution structure and the metal structure; wherein semiconductor material of the semiconductor structure forms a current path between the redistribution structure and the metal structure; wherein the semiconductor structure comprises at least one block external from the chip, wherein the at least one block comprises the semiconductor material and wherein the at least one block further comprises electrically conductive plastic material; wherein the at least one block is configured to be diced or sawn; and wherein the at least one block is arranged at least partially along the perimeter of the package arrangement.