Patent ID: 9696377
Date: 2017-07-04
CPC Classifications: F16C,G01R

Claim:
1. A broadcaster that accepts a virtual scan pattern via one or more scan inputs for generating a broadcast scan pattern to test a scan-based circuit, the scan-based circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, said broadcaster comprising: a) a virtual scan controller, said virtual scan controller further including one or more shift registers for accepting said virtual scan pattern via at least one said scan input; and b) a solely combinational logic network coupled to one or more outputs of said virtual scan controller for generating said broadcast scan pattern at outputs of said combinational logic network, said combinational logic network comprising one or more multiplexers, wherein application of said virtual scan pattern to said scan-based circuit through said broadcaster decreases a test application time relative to a test application time for a test that does not utilize said broadcaster.