Patent ID: 9738510
Date: 2017-08-22
CPC Classifications: B81B,B81C,G01C,G01L,H01L,H04R

Claim:
1. A package-level chip scale MEMS packaged device comprising: a MEMS chip comprising a CMOS substrate having a top surface having a first portion and a second portion and comprising a cap disposed upon the first portion of the CMOS substrate, wherein the CMOS substrate is associated with a first thickness, wherein the cap is associated with a second thickness, wherein the cap and the first portion of the top surface form an enclosed cavity, wherein at least a MEMS device is formed on the first portion of the top surface and disposed within the enclosed cavity, wherein the second portion of the top surface of the CMOS substrate is substantially free of the cap and includes at least a first bonding region; a packaging substrate having a top surface, the top surface having a first portion and a second portion, wherein the first portion is characterized by a third thickness, wherein the second portion is characterized by a fourth thickness, wherein the third thickness exceeds the fourth thickness by at least the second thickness associated with the cap, wherein the first portion of the top surface of the packaging substrate includes at least a second bonding region; wherein the MEMS chip is oriented relative to the packaging substrate such that the second portion of the top surface of the CMOS substrate is opposed to the first portion of the top surface of the packaging substrate, and such that the cap is disposed above the second portion of the top surface of the packaging substrate; and wherein the first bonding region is bonded to the second bonding region.