Patent ID: 9653447
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: a substrate having a first surface and a second surface; an active region formed within the substrate; a plurality of collector regions each having a first area formed within the active region; a plurality of emitter regions each having a second area smaller than the first area and formed within the active region; a plurality of collector contact regions formed at the first surface of the substrate; a plurality of emitter contact regions formed at the first surface of the substrate; a local interconnect layer (LIL) disposed at a level above the emitter contact regions and collector contact regions directly contacting the plurality of emitter contact regions and the plurality of collector contact regions, the LIL including cooling fin contacts formed at the level on the collector contact regions to enhance the current handling capacity of the collector regions; and an LIL contact formed at the level on the active region on the emitter contact regions, the LIL contact having a length smaller than a length of an LIL cooling fin contact.