Patent ID: 9543937
Date: 2017-01-10
CPC Classifications: G06F,H03K,H03L

Claim:
1. A device, comprising: a first delay line having a plurality of delay elements, the first delay line being configured to receive a first input clock signal and output a first plurality of output clock signals having different phases compared to a phase of the first input clock signal; a second delay line having a plurality of delay elements, the second delay line being configured to receive a second input clock signal and output a second plurality of output clock signals having different phases compared to a phase of the second input clock signal; a control circuit configured to control the first and second delay lines based at least in part upon a rising or falling edge of at least one output clock signal of the first plurality of output clocks signals and at least one output clock signal of the second plurality of output clock signals; and a crossover control module communicatively coupled to the delay line, the crossover control module being configured to receive clock signals from a clock signal source, determine crossover error in the first and second delay lines, and generate the first input clock signal and the second input clock signal based on the crossover error.