Patent ID: 9607884
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising the steps of: forming a first interlayer insulating film over a semiconductor substrate; forming an etching stopper film containing Si and C over the first interlayer insulating film; forming an inorganic insulating film not containing C over the etching stopper film; forming a resist film over the inorganic insulating film; selectively etching the etching stopper film and the inorganic insulating film so as to expose an upper surface of the first interlayer insulating film by using the resist film as a mask to form a first opening in the etching stopper film and to form a second opening that overlaps with the first opening in the inorganic insulating film; removing the resist film by O forming a second interlayer insulating film over the inorganic insulating film and in contact with the upper surface of the first interlayer insulating film; and etching the second interlayer insulating film to form a wiring groove that is coupled to the second opening, and etching a portion located under the first opening of the first interlayer insulating film to form a via hole.