Patent ID: 9685461
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A manufacturing method of an array substrate comprising a first thin film transistor and a pixel electrode, wherein, an active layer and source and drain electrodes in the first thin film transistor as well as the pixel electrode are formed by one patterning process, wherein the array substrate further comprises a second thin film transistor, active layers and source and drain electrodes in the first thin film transistor and the second thin film transistor as well as the pixel electrode are formed by one patterning process, the method comprising: depositing an active layer thin film, a source/drain metal layer and a pixel electrode layer; applying photoresist; conducting exposure and development with a dual-tone masking process, performing etching and ashing, and removing a remaining photoresist layer to form a pattern of the connecting zone of the drain electrode of the first thin film transistor and the gate electrode of the second thin film transistor, a pattern of the zone of the data line and the power supply line, a pattern of the zone of source and drain electrodes of the first thin film transistor and the second thin film transistor, and a pattern of the pixel electrode.