Patent ID: 9559676
Date: 2017-01-31
CPC Classifications: H03K

Claim:
1. An output buffer apparatus, comprising: a clamp circuit outputting a clamp voltage through a transistor pair having a first configuration; a bias circuit outputting a bias voltage through a transistor pair having a second configuration, wherein the bias circuit comprises: a first N-type transistor having a drain coupled to an operation voltage, and a gate and a source of the first N-type transistor are connected to each other; and a first P-type transistor, coupled between the source of the first N-type transistor and a ground voltage, and a gate and a drain of the first P-type transistor are connected to each other, and a common contact point of the first N-type transistor and the first P-type transistor is configured to output the bias voltage; and a rate control circuit for rising/falling edge, coupled to the clamp circuit and the bias circuit, wherein the rate control circuit for rising/falling edge buffers an input signal to generate a buffered signal and controls a rate of rising/falling edge of the buffered signal according to the clamp voltage and the bias voltage.