Patent ID: 9588240
Date: 2017-03-07
CPC Classifications: G01T,H01L,H04N

Claim:
1. An imager tile comprising: an array of sub-imager pixel arrays, the sub-imager pixel arrays arranged in rows and columns; each of the sub-imager pixel arrays including a plurality of four-side buttable imagers distributed on a wafer substrate and an on-chip digitizing electronic readout circuit; each of the four-side buttable imagers including at least one photodiode configured to be exposed to incident photon radiation; a plurality of pixel groupings formed from among the plurality of imagers; the readout electronics including a buffer amplifier for each of the plurality of pixel groupings and connected to respective outputs of each four-side buttable imager of the pixel grouping; a plurality of shared analog front ends, each shared analog front end connected to respective multiple buffer amplifiers from among the plurality of pixel groupings; an analog-to-digital converter located at a common centroid location relative to the plurality of shared analog front ends, the analog-to-digital converter having a selection input/output line to individually select an output from each of the plurality of shared analog front ends; the analog-to-digital converter having a clock input line, and a shared digital output line that is shared among the respective multiple buffer amplifiers; wherein a pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line.