Patent ID: 9685416
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate that includes a first semiconductor chip area formed with a semiconductor element; laminated interlayer insulating films formed on the semiconductor substrate; and a first metal ring formed in the laminated interlayer insulating films, wherein: the first metal ring has a multilayer structure of vertically stacked plural metal layers each of which consists of a uniformly-shaped contact layer or a uniformly-shaped wiring layer and each metal layer is disposed vertically between the semiconductor substrate and a top of the first metal ring; the first metal ring has a closed loop-shape, and surrounds the semiconductor element; the first metal ring has a first side wall; the first metal ring has a second side wall on a side opposite to the first side wall; the first metal ring includes a first lower metal layer and a first upper metal layer formed directly on the first lower metal layer; the first metal ring includes a second lower metal layer formed directly under the first lower metal layer; an end of the first upper metal layer on the first side wall is inwardly retracted from an end of the first lower metal layer on the first side wall near an edge of the first semiconductor chip area; and an end of the first upper metal layer on the second side wall is farther from the edge of the first semiconductor chip area than an end of the second lower metal layer on the second side wall.