Patent ID: 9543228
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate; wherein a heat dissipation structure is provided in the multi-layer wiring structure, an upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and a lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element, wherein the multi-layer wiring structure includes a plurality of interlayer insulating films stacked one over another and a plurality of wiring layers, each of the wiring layers includes both a pad and a plurality of via plugs extending downwards from the wiring layer pad as part of the heat dissipation structure making the contact outside the element forming region, and the plurality of via plugs of each of the wiring layers are arranged in a two-dimensional matrix form in a plan view, and wherein the pad of each of the wiring layers has a plurality of openings formed therethrough, and the openings of the pad in a given one of the wiring layers are situated directly above the openings of the pad in another one of the wiring layers.