Patent ID: 9608080
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A silicon-on-insulator device comprising: a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a set of silicide contacts having a first silicide contact on the raised source, a second silicide contact on the raised drain, and a third silicide contact on the gate; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; a low-k layer covering at least an upper portion of each of the first sidewall and the second sidewall of the gate; and a dielectric layer over the low-k layer, wherein the low-k layer directly covers at least a portion of each of the first silicide contact, the second silicide contact, and the third silicide contact.