Patent ID: 9548210
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A fabrication method of a field-effect transistor, comprising the following consecutive steps: providing a substrate comprising: depositing a metallic material in the access hole of the source and/or drain areas so that the metallic material is in contact with the first semiconductor material, depositing an electrically conducting barrier layer, said barrier layer being non-reactive with the first semiconductor material and non-reactive with the metallic material, depositing an electric conductor on said barrier layer so as to fill said access hole, and performing a heat treatment so that the metallic material react with the semiconductor material to form an alloy between a metallic material and the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas, wherein the metallic material is deposited by means of selective deposition or directional deposition in a direction perpendicular to the surface of the substrate.