Patent ID: 9570360
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor structure comprising: forming a plurality of silicon fins extending upwards from a bulk silicon portion, wherein each silicon fin of said plurality of silicon fins is separated by a trench isolation region; completely removing a predetermined number of silicon fins of said plurality of silicon fins to expose a surface of said bulk silicon substrate in an nFET device region and a pFET device region of the bulk silicon portion; forming a relaxed silicon germanium alloy fin portion on said exposed portion of said bulk silicon substrate; forming, in any order, a compressively strained silicon-containing germanium alloy fin portion on a topmost surface of each relaxed silicon germanium alloy fin portion in said pFET device region and a tensile strained silicon-containing fin portion on a topmost surface of each relaxed silicon germanium alloy fin portion in said nFET device region; and recessing each trench isolation region to provide trench isolation structures and to partially expose sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile stained silicon fin portion.