Patent ID: 9740657
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A memory device for multiple processors, the memory device comprising: a command and control signal port receiving a command and control signal from a memory controller; an address port receiving an address signal from the memory controller; a data port comprising a plurality of data channels being independently driven to simultaneously process a plurality of memory access requests to the memory controller; a mode register changing a number of the plurality of data channels being independently driven by combining or dividing the plurality of data channels; and a plurality of memory banks, wherein each of the plurality of memory banks is divided into a plurality of sub-banks to simultaneously perform operations according to the plurality of memory access requests when the plurality of memory access requests are sequentially transmitted through the command and control signal port and the address port, wherein each of the plurality of sub-banks is divided based on a bit line, wherein the mode register changes at least a part of data widths of the plurality of data channels to be different from one another by combining or dividing the plurality of data channels.