Patent ID: 9613946
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a P-type semiconductor substrate; a first N-well, a second N-well, and a P-well in the semiconductor substrate, the P-well being disposed between the first N-well and the second N-well and having opposite sides abutting the first N-well and the second N-well; a first doped region having a first conductivity type within the first N-well; a second doped region having a second conductivity type formed in a junction region between the first N-well and the P-well and spaced apart from the first doped region; a third N+ doped region formed in a junction region between the second N-well and the P-well and spaced apart from the second doped region; a fourth P+ doped region within the second N-well and spaced apart from the third N+ doped region; and a gate structure formed on the surface of the P-well between the second doped region and the third N+ doped region, wherein the gate structure, the second doped region and the third N+ doped region form an NMOS structure.