Patent ID: 9595308
Date: 2017-03-14
CPC Classifications: G06F,G11C

Claim:
1. A circuit comprising: a first first-in first-out (FIFO) buffer on a first semiconductor die, wherein a write pointer for the first FIFO buffer is clocked by a first write clock signal, and a read pointer for the first FIFO buffer is clocked by a first read clock signal; a first observation circuit that samples the first write clock signal and outputs a first observed clock signal; a second observation circuit that samples the first read clock signal and outputs a second observed clock signal; a second FIFO buffer on a second semiconductor die, wherein a write pointer for the second FIFO buffer is clocked by a second write clock signal, and a read pointer for the second FIFO buffer is clocked by a second read clock signal; a third observation circuit that samples the second write clock signal and outputs a third observed clock signal; and a fourth observation circuit that samples the second read clock signal and outputs a fourth observed clock signal, wherein the first, second, third and fourth observation circuits are clocked by a first sampling clock signal; and a fifth observation circuit clocked by the first sampling clock that samples the first read clock signal and outputs a fifth observed clock signal, wherein the first read clock signal reaches the fifth observation circuit before reaching the second observation circuit.