Patent ID: 9659137
Date: 2017-05-23
CPC Classifications: G06F

Claim:
1. A computer-implemented method of correcting a layout of a mask read only memory (ROM), the method comprising: a processor receiving source ROM code, bitmap data, and layout design data of the mask ROM; the processor generating coordinate data of vias of the layout design data; the processor determining an error cell in the layout design data based on the coordinate data of the vias, the bitmap data, and the source ROM code; and the processor correcting the layout design data using the determined error cell, wherein each via is used to connect a transistor of the mask ROM to a bit line in the mask ROM, and wherein the determining comprises the processor determining a given cell of the mask ROM to be the error cell when a bit, the source ROM code for the given cell is 1 and two of the vias are adjacent in a same direction in the given cell.