Patent ID: 9589960
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor structure, comprising: forming a first doping region, a second doping region and a trench between the first and second doping regions in a semiconductor substrate; forming a gate dielectric layer over a surface of the trench; forming a dielectric liner layer over the gate dielectric layer; forming a sacrificial layer which fills the trench, over the dielectric liner layer; etching the sacrificial layer and the dielectric liner layer, and forming a sacrificial filler and a dielectric liner that are positioned in the trench; removing the sacrificial filler; forming a conductive layer which fills the trench, over the dielectric liner and the gate dielectric layer; and recessing the conductive layer, and forming a gate electrode that is buried in the trench.