Patent ID: 9620512
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A device comprising a field effect transistor and a three-dimensional memory device, wherein the field effect transistor comprises: a first vertical transistor channel portion extending through a first portion of an alternating stack of electrically conductive layers and insulating layers located over a substrate, wherein at least some of the electrically conductive layers are electrically shorted among one another to provide a gate electrode; a first gate dielectric laterally surrounding the first vertical transistor channel portion; a gate electrode contact structure extending through the first portion of the alternating stack and contacting at least some of the electrically conductive layers to electrically short at least some of the electrically conductive layers; a bottom active region located in, or on, the substrate and laterally spaced from the first vertical transistor channel portion; and a first top active region overlying the first vertical transistor channel portion, wherein one of the top and bottom active regions is a source region of the field effect transistor and another of the top and bottom active regions is a drain region of the field effect transistor, and wherein the three-dimensional memory device comprises: a second portion of the alternating stack of insulating layers and electrically conductive layers that are electrically isolated from one another and from the electrically conductive layers of the first portion of the alternating stack; and at least one memory stack structure vertically extending through the second portion of the alternating stack, wherein each of the at least one memory stack structure comprises, from inside to outside, a memory device channel and a memory film.