Patent ID: 9601568
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A transistor device, comprising: a semiconductor substrate; and a plurality of shallow trench isolation (STI) structures disposed in the semiconductor substrate, each STI structure including: a first dielectric layer disposed in a trench in the semiconductor substrate and having a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate; an epitaxial layer disposed on the uncovered sidewall surface of the trench in the semiconductor substrate and on a surface portion of the first dielectric layer, wherein the epitaxial layer has a top surface leveled with the top surface of the semiconductor substrate; and a second dielectric layer disposed on a remaining surface portion of the first dielectric layer, wherein the second dielectric layer has a top surface leveled with the top surface of the semiconductor substrate, wherein: a channel width of the transistor device is a total width including a width of a portion of the semiconductor substrate located between neighboring STI structures plus a total width of the epitaxial layer on both sides of the isolation structure.