Patent ID: 9721890
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A system-on-chip comprising: a substrate comprising a first region and a second region that is disposed laterally relative to the first region; a plurality of unit cells disposed at an upper surface of the substrate, each of the plurality of unit cells having electronic components and a power terminal through which power is supplied to the electronic components of the cell; a first metallization layer comprising a first power rail electrically connected to the power terminal of each of the plurality of unit cells; a second metallization layer comprising a first power strap, wherein one of the first and second metallization layers is stacked on the other of the first and second metallization layers, and the power strap and the power rail are electrically connected to each other, and constitute a first power mesh; a third metallization layer; and a fourth metallization layer, wherein one of the third and fourth metallization layers is stacked on the other of the third and fourth metallization layers, the third and fourth metallization layers are both stacked on the first and second metallization layers, the third and fourth metallization layers comprise a second power mesh disposed above levels of the power strap and power rail of the first power mesh in the device, the first power mesh lies over the first region of the substrate, and the second power mesh lies over the second region of the substrate.