Patent ID: 9563398
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. An integrated circuit, comprising: a first processor; a transmit pin; a GPIO interface configured to receive a transmit set of GPIO signals from the processor and to transmit a first portion of the transmit set over a plurality of GPIO pins to a remote second processor; a finite state machine configured to serialize a remaining second portion of the transmit set of GPIO signals from the GPIO interface into a first virtual GPIO (VGI) frame and a second VGI frame, wherein the first VGI frame and the second VGI frame each ends with a stop bit; a transmit buffer configured to transmit an initial portion of the first VGI frame's stop bit over the transmit pin through a low output impedance responsive to at least one cycle of an oversampling clock signal and to transmit a remaining portion of first VGI frame's stop bit through a high output impedance responsive to a plurality of cycles of the oversampling clock signal; and a transmit control circuit configured to command the transmit buffer to transmit an initial portion of the second VGI frame responsive to a determination that a voltage for the transmit pin was above a threshold voltage during the transmission of the remaining portion of the first VGI frame's stop bit.