Patent ID: 9536906
Date: 2017-01-03
CPC Classifications: G02F,G09G,H01L

Claim:
1. A pixel structure, comprising: a plurality of data lines arranged in a first direction; and a plurality of gate lines arranged in a second direction, wherein the plurality of data lines intersect with the plurality of gate lines near a plurality of sub-pixels, each of the plurality of sub-pixels comprising: a thin film transistor, and a pixel electrode, wherein the plurality of sub-pixels comprises: a plurality of first rows of sub-pixels, and a plurality of second rows of sub-pixels, wherein the first rows of sub-pixels and the second rows of sub-pixels are interleaved, each sub-pixel in the first rows of sub-pixels is provided with a signal over a second-closest data line, each sub-pixel in the second rows of sub-pixels is provided with a signal over a first-closest data line, the first-closest data line is each sub-pixel's closest data line, and the second-closest data line, which is not adjacent to the each sub-pixel is each sub-pixel's next closest data line.