Patent ID: 9583430
Date: 2017-02-28
CPC Classifications: H01L,H05K

Claim:
1. A package-on-package (PoP) device comprising: a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted on the lower package substrate; an upper semiconductor package disposed on the lower semiconductor package, the upper semiconductor package including an upper package substrate and an upper semiconductor chip mounted on the upper package substrate; an interposer substrate disposed between the lower semiconductor package and the upper semiconductor package, the interposer substrate electrically connecting the lower semiconductor package to the upper semiconductor package; and a first thermal boundary material layer disposed between the lower semiconductor package and the interposer substrate, wherein the first thermal boundary material layer and the lower semiconductor chip vertically overlap, and wherein the lower semiconductor chip is electrically connected to the lower package substrate through bumps, wherein the lower semiconductor package further comprises a connecting member spaced apart from the lower semiconductor chip on the lower package substrate, wherein the connecting member electrically connects the lower package substrate to the interposer substrate, wherein the connecting member includes at least one of a conductive bump and a solder ball, wherein the lower semiconductor package further comprises a lower mold layer covering a top surface of the lower package substrate and a sidewall of the lower semiconductor chip, and wherein the lower mold layer includes a hole in which the connecting member is disposed, wherein the lower mold layer extends to cover a top surface of the lower semiconductor chip.