Patent ID: 9627256
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor interconnect structure, comprising: forming a dielectric layer on a substrate; patterning the dielectric layer to form an opening in the dielectric layer; forming a diffusion barrier layer on sidewalls of the opening, the diffusion barrier layer having a first thickness; filling the opening and covering the dielectric layer with a metal layer; planarizing the metal layer so that the metal layer is co-planar with a top of the dielectric layer; etching back the metal layer and the diffusion barrier layer a first distance from the top of the dielectric layer to expose inside sidewalls of the dielectric layer; forming a sidewall barrier layer on the exposed inside sidewalls of the dielectric layer, the sidewall barrier layer having a second thickness, the sidewall barrier layer only partially extending over the metal layer, the second thickness being greater than the first thickness; forming a copper-containing layer over the metal layer, the dielectric layer, and the sidewall barrier layers; and etching the copper-containing layer to form interconnect features, wherein the etching stops at the sidewall barrier layer at approximately a juncture of the inside sidewall of the dielectric layer and the copper-containing layer and does not etch into the metal layer.