Patent ID: 9715386
Date: 2017-07-25
CPC Classifications: G06F

Claim:
1. A processor comprising: an execution core configured to execute a vector instruction comprising: a first vector predicate operand that specifies active elements of a result vector of the vector instruction; the execution core is configured to generate the result vector of the vector instruction identifying which active vector elements are dependent on which other active vector elements in response to the true/false results and the source operand, wherein dependencies are detected only between active vector elements, and wherein a dependency is detected between a first active vector element and a nearest prior active vector element in response to a first combination in the true/false results between the first active vector element and the nearest prior active vector element being specified in the source operand, and wherein no dependency is detected between the first active vector element and the nearest prior active vector element in response to the first combination in the true/false results not being specified in the source operand, and wherein the dependency or no dependency is detected even in the event that one or more inactive elements are included between the first active vector element and the nearest prior active vector element as specified by the first vector predicate operand.