Patent ID: 9543381
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A semiconductor structure, comprising: a substrate having a center portion and an edge portion; a plurality of semiconductor dies over the substrate, the edge portion including a region where at least one side of the semiconductor die being in contact with the circumference of the substrate; an isolation layer over the plurality of semiconductor dies; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer; a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at the edge portion of the substrate; and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at the center portion of the substrate, wherein a lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin.