Patent ID: 9721793
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method for patterning a substrate, the method comprising: forming an array of fin structures on a working surface of a substrate; forming an array of gate structures on the working surface of the substrate, the array of gate structures having gate structures crossing and covering a portion of fin structures of the array of fin structures, the array of gate structures including first dielectric material abutting sidewalls of the gate structures and covering a remaining portion of the fin structures; forming a first etch mask on the substrate that uncovers portions of the gate structures; removing portions of the gate structures that are uncovered by the first etch mask resulting in forming trench segments defined by the first dielectric material with portions of the fin structures being uncovered within the trench segments; removing uncovered fin structures from the trench segments; and filling the trench segments with a second dielectric material.