Patent ID: 9691783
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first stacked structure in which first conductive patterns and first interlayer insulating layers are alternately stacked; a second stacked structure formed on the first stacked structure and including second conductive patterns and second interlayer insulating layers, which are alternately stacked; an interfacial pattern formed between the first stacked structure and the second stacked structure; first through-areas passing through the first stacked structure and the interfacial pattern and including first protrusions protruding toward a sidewall of the interfacial pattern; second through-areas passing through the second stacked structure and connected to the first through-areas; and through-structures formed along sidewalls of the first through-areas and the second through-areas, wherein the first protrusions define depressions on sidewalls of the first through-areas, the depressions more protruding toward a lateral direction than entire sidewalls of the second through-areas, wherein the through-structures are formed such that the first conductive patterns and the first interlayer insulating layers between a lowermost layer and an uppermost layer of the first stacked structure have the same structure as the second conductive patterns and the second interlayer insulating layers between a lowermost layer and an uppermost layer of the second stacked structures, wherein each of the first protrusions and the depressions has a top surface in direct contact with the lowermost layer of the second stacked structure and a bottom surface in direct contact with the uppermost layer of the first stacked structure, wherein the interfacial pattern is formed of a conductive material, or is formed of an insulating material having an etch selectivity different from etch selectivities of the first and second conductive patterns and the first and second interlayer insulating layers; and wherein at least one conductive pattern from an uppermost layer among the second conductive patterns is a drain select line, and at least one conductive pattern from a lowermost layer among the first conductive patterns is a source select line.