Patent ID: 9588933
Date: 2017-03-07
CPC Classifications: G06F,H04L

Claim:
1. A single wire-serial interface_(SSI) master module comprising: a state machine unit; a selector unit; a sampling unit; and a sample delay controlling unit; wherein the sample delay controlling unit is connected to the state machine unit and is configured to send, before the SSI master module sends a last bit of address information in a first read operation each time after being power on or reset, a delay instruction to the state machine unit; wherein the state machine unit is connected to the selector unit and is configured to: wherein the selector unit includes a first end connected to the sampling unit and a second end connected to the SSI slave module through a single wire, and is configured to, after receiving the sample control signal, enable a transmission channel between the selector unit and the sampling unit enable the SSI slave module to input data information corresponding to the address information in the read operation frame into the sampling unit; and wherein the sampling unit is configured to sample the data information from the SSI slave module.