Patent ID: 9628257
Date: 2017-04-18
CPC Classifications: G11C,H04L

Claim:
1. A component, comprising: a receiver to sample arriving read data, retrieved from addressable memory space of a memory device, the read data arriving at the component via a bidirectional link during a normal mode of operation, the sampling performed according to an operational value of a sampling instant defined relative to a reference clock; circuitry to suspend the normal mode of operation to update the operational value of the sampling instant in order to account for timing drift, the circuitry to cause the receiver to, in iterations, use at least two other values of the sampling instant to sample values of a predefined data pattern arriving at the component from the memory device via the bidirectional link; circuitry to, for each value of the at least two other values of the sampling instant, compare the sampled values of the predefined data pattern against expected data, to obtain pass/fail data; and circuitry to update the operational value of the sampling instant in response to the pass/fail data, to obtain an updated value; wherein the component is to sample the arriving read data, retrieved from the addressable memory space of the memory device, following resumption of the normal mode of operation according to the updated value.