Patent ID: 9728561
Date: 2017-08-08
CPC Classifications: G02B,G02F,H01L

Claim:
1. A method for fabricating a portion of a pixel of a display, the method comprising: forming a gate structure for at least two thin film transistors (TFTs) of the pixel; forming an amorphous silicon layer on at least a portion of the gate structure; forming a drain layer over at least a portion of (i) the gate structure and (ii) the amorphous silicon layer, wherein the drain layer includes a central conductive region that is, in a plan view, proximate to a middle of the drain layer; forming an insulating layer to substantially cover the gate structure, the amorphous silicon layer, and the drain layer, wherein the insulating layer includes an opening substantially above the central conductive region; forming a common electrode layer over the insulating layer, wherein the common electrode layer includes an opening substantially above the central conductive region; forming a silicon nitride layer on the common electrode layer, wherein the silicon nitride layer includes an opening substantially above the central conductive region; and forming a pixel electrode on the silicon nitride layer, wherein at least a portion of the pixel electrode is (1) disposed in the opening of the insulating layer, the opening of the common electrode layer, and the opening of the silicon nitride layer, and (ii) in electrical contact with the central conductive region.