Patent ID: 9704856
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices, comprising: forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region; cutting gate structures in the CMOS region and the capacitor region by etching at least one trench across the gate structures and filling the at least one trench with a dielectric material; removing the gate structures and the dielectric material in the at least one trench in the capacitor region to form a position for an insulator and a second electrode; depositing the insulator in the position; and depositing gate metal to form gate conductors in the CMOS region and the second electrode in the capacitor region.