Patent ID: 9705001
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first oxide layer comprising at least one of indium, gallium and zinc; an oxide semiconductor layer including a first channel formation region and a second channel formation region, the oxide semiconductor layer being in contact with a top surface of the first oxide layer; a second oxide layer in contact with a top surface of the oxide semiconductor layer and comprising at least one of indium, gallium and zinc; a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer; a gate electrode layer covering a side surface and a top surface of the first channel formation region and a side surface and a top surface of the second channel formation region; and a gate insulating layer between the oxide semiconductor layer and the gate electrode layer, wherein a portion of the first oxide layer is surrounded by the oxide semiconductor layer when seen from a direction perpendicular to a surface of the first oxide layer, and wherein the second oxide layer is in contact with a top surface of the portion of the first oxide layer.