Patent ID: 9614051
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device, comprising: providing a substrate; forming at least one dummy gate structure on the substrate; forming doping regions in the substrate at both sides of the dummy gate structure; forming an interlayer dielectric film on the substrate, on a side surface of the dummy gate structure, and having a top surface above the dummy gate structure; performing a first step thermal annealing process onto the interlayer dielectric film and the doping regions; after the first step thermal annealing process, removing a portion of the annealed interlayer dielectric film to form an interlayer dielectric layer; removing the dummy gate structure to expose a surface portion of the substrate to form a trench in the interlayer dielectric layer; forming a gate dielectric layer on the surface portion of the substrate and on a bottom of the trench; and performing a second step thermal annealing process onto the gate dielectric layer and the doping regions to further activate doping ions in the doping regions and increase a density of the gate dielectric layer.