Patent ID: 9685609
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A variable resistance memory device comprising: a plurality of first conductive lines on a substrate, each of the first conductive lines extending in a first direction; a plurality of second conductive lines above the first conductive lines, each of the second conductive lines extending in a second direction transverse to the first direction; a plurality of first memory cells at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on substantially a first plane; a plurality of third conductive lines above the second conductive lines, each of the third conductive lines extending in the first direction; a plurality of second memory cells at intersections where the second and the third conductive lines overlap each other, each of the second memory cells including a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on substantially a second plane; and a first capping pattern on first and second sidewalls facing in the first direction of each of the first and second memory cells.