Patent ID: 9564519
Date: 2017-02-07
CPC Classifications: G11C,H01L

Claim:
1. A method of manufacturing a non-volatile memory device, comprising: alternately stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate, wherein the plurality of conductive layers comprise a silicon material; forming an opening that exposes a portion of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; forming a channel region on the tunneling layer; forming a separation opening through the plurality of insulating layers and the plurality of conductive layers; forming a metal layer in the separation opening; performing a heat treatment process on the metal layer and the plurality of conductive layers to generate a metal silicide; and forming a separation layer in the separation opening, wherein the anti-oxidation layer remains between the plurality of conductive layers and the gate dielectric after forming the separation layer in the separation opening.