Patent ID: 9612465
Date: 2017-04-04
CPC Classifications: G02F,G09G

Claim:
1. A source driving circuit, comprising a plurality of output channels, wherein the plurality of the output channels are divided into odd output channels and even output channels alternately arranged with each other, each output channel comprises a first switch element, a second switch element, a first output end, and a second output end, the first switch element is connected to the first output end, the second switch element is connected to the second output end, the first switch element of each odd output channel is controlled by an odd first control signal, the second switch element of each odd output channel is controlled by an odd second control signal, the first switch element of each even output channel is controlled by an even first control signal, and the second switch element of each even output channel is controlled by an even second control signal, when the first switch element is turned on, the output channel outputs a display signal through the first switch element and the first output end, and when the second switch element is turned on, the output channel provides recycled charges through the second switch element and the second output end, and the recycled charges are generated when the display signal outputted by the first output end is changed from a positive voltage to a negative voltage; wherein each of the first switch element and the second switch element includes a first conduction terminal, a second conduction terminal, and a control terminal, the first conduction terminal of the first switch element is used to receive display data, the second conduction terminal of the first switch element is connected to the first output end, the first conduction terminal of the second switch element is connected to the second conduction terminal of the first switch element, the second conduction terminal of the second switch element is connected to the second output end, the control terminal of the first switch element of each odd output channel is connected to the odd first control signal, the control terminal of the second switch element of each odd output channel is connected to the odd second control signal, the control terminal of the first switch element of each even output channel is connected to the even first control signal, and the control terminal of the second switch element of each even output channel is connected to the even second control signal; wherein phase of the odd first control signal and phase of the odd second control signal are opposite, and phase of the even first control signal and phase of the even second control signal are opposite.