Patent ID: 9748368
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A tunnel field-effect transistor (FET) device, comprising: a bulk silicon substrate; a p-i-n tunnel structure formed within the bulk silicon substrate, the p-i-n tunnel structure comprising a source region of a first type, a drain region of a second type, and a channel region of the bulk silicon substrate between the drain region and the source region, wherein the drain region comprises silicon or silicon-germanium doped with dopants of the second type, and wherein the bulk silicon substrate comprises silicon or silicon-germanium doped with dopants of either the first type the second type; a gate electrode separated from the p-i-n tunnel structure through a gate dielectric, wherein the gate dielectric is positioned partially over the source region and partially over the channel region; a source electrode; a drain electrode; a first side-wall spacer material arranged to interface with each of a first portion of the source region and a portion of the source electrode; and a second side-wall spacer material arranged to interface with each of a stepped top portion of the channel region, a portion of the drain region, and a portion of the drain electrode.