Patent ID: 9632942
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A processing unit, comprising: a processor core including: an instruction sequencing unit that orders instructions for execution; and an execution unit that generates a store operation by executing a store instruction in an instruction sequence; a cache memory including a cache array and a store queue for buffering store operations to be serviced with respect to the cache array; and marking logic located within at least one of the processor core or the cache memory, wherein the marking logic selectively marks the store operation as a high priority store operation, wherein the marking logic marks the store operation as a high priority store operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and refrains from marking the store operation as a high priority store operation in response to not detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order; wherein the cache memory expedites handling of the store operation in the store queue in response to the store operation being marked as a high priority store operation and otherwise refrains from expediting handling of the store operation in the store queue; wherein the barrier instruction is an instruction that guarantees completion of all store operations preceding the barrier instruction prior to completing any store operations following the barrier instruction.