Patent ID: 9607717
Date: 2017-03-28
CPC Classifications: G11C

Claim:
1. A method of testing an integrated circuit including ferroelectric memory cells, comprising the steps of: determining a first reference voltage at which fewer than a preselected number of a plurality of ferroelectric memory cells of the integrated circuit that are programmed to a first data state return a second data state when read; determining a second reference voltage corresponding to a selected differential from the first reference voltage; programming the plurality of the ferroelectric memory cells to the first data state; heating the integrated circuit to an elevated temperature; then reading the plurality of ferroelectric memory cells, at the elevated temperature, wherein the reading step comprises, for each of the plurality of ferroelectric memory cells accessing the memory cell and comparing a voltage produced by the memory cell by the accessing step to the second reference voltage; and then comparing a number of the ferroelectric memory cells from which the second data state, opposite from the first data state, was read by the reading step with a pass/fail threshold number.