Patent ID: 9735346
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method for fabricating an electronic device including a semiconductor memory, the method comprising: forming a plurality of buried gates in a substrate including a first region including a cell region that includes storage cells for storing data and a second region including a peripheral region that includes control circuitry to control operations of the storage cells in the cell region, wherein a distance between adjacent buried gates is greater in the second region than in the first region; forming an ion implantation barrier layer over the substrate in the second region; forming a junction by performing ion implantation into the substrate between the adjacent buried gates in the first and second regions; removing the ion implantation barrier layer; forming an interlayer insulating layer over the substrate in the first and second regions; forming a lower electrode contact through the interlayer insulating layer in the first region so as to contact the substrate; and forming a variable resistance element within a storage cell over the interlayer insulating layer in the first region so as to be connected to the lower electrode contact, wherein the variable resistance element exhibits different resistance states for storing data.