Patent ID: 9601505
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first pillar-shaped semiconductor layer; a first selection gate insulating film surrounding the first pillar-shaped semiconductor layer; a first selection gate surrounding the first selection gate insulating film; a first bit line connected to an upper portion of the first pillar-shaped semiconductor layer; a second pillar-shaped semiconductor layer; a layer including a first charge storage layer, surrounding the second pillar-shaped semiconductor layer; a first control gate surrounding the layer including the first charge storage layer; a layer including a second charge storage layer, the layer being disposed above the first control gate and surrounding the second pillar-shaped semiconductor layer; a second control gate surrounding the layer including the second charge storage layer; a first lower-portion internal line connecting a lower portion of the first pillar-shaped semiconductor layer to a lower portion of the second pillar-shaped semiconductor layer, wherein an upper portion of the second pillar-shaped semiconductor layer is connected to a pillar-shaped semiconductor layer next to the second pillar-shaped semiconductor layer and located on a side of the second pillar-shaped semiconductor layer being opposite the first pillar-shaped semiconductor layer, by a first upper-portion internal line, and wherein the upper portion of the second pillar-shaped semiconductor layer is not connected to any pillar-shaped semiconductor layers other than the pillar-shaped semiconductor layer next to the second pillar-shaped semiconductor layer; a third pillar-shaped semiconductor layer; a layer including a third charge storage layer, surrounding the third pillar-shaped semiconductor layer; a third control gate surrounding the layer including the third charge storage layer; a layer including a fourth charge storage layer, the layer being disposed above the third control gate and surrounding the third pillar-shaped semiconductor layer; a fourth control gate surrounding the layer including the fourth charge storage layer; a fourth pillar-shaped semiconductor layer; a second selection gate insulating film surrounding the fourth pillar-shaped semiconductor layer; a second selection gate surrounding the second selection gate insulating film; a first source line connected to an upper portion of the fourth pillar-shaped semiconductor layer; and a second lower-portion internal line connecting a lower portion of the third pillar-shaped semiconductor layer to a lower portion of the fourth pillar-shaped semiconductor layer.