Patent ID: 9621172
Date: 2017-04-11
CPC Classifications: H03L

Claim:
1. A phase-locked loop circuit, comprising: a phase frequency detector receiving a reference signal and a feedback signal, and generating a control signal; a charge pump receiving the control signal, and generating a driving current, wherein the charge pump comprises a first charging path, a first discharging path, a second charging path and a second discharging path, wherein a first charging current is provided by the first charging path, a first discharging current is provided by the first discharging path, a second charging current is provided by the second charging path, and a second discharging current is provided by the second discharging path; a loop filter receiving the driving current, and generating a tuned voltage, wherein the loop filter comprises an RC circuit and a unit gain buffer, wherein the RC circuit is connected with a node, the RC circuit generates the tuned voltage at the node according to the driving current, and an input terminal of the unit gain buffer is connected with the node; a voltage controlled oscillator receiving the tuned voltage, and generating an oscillation signal, wherein the voltage controlled oscillator comprises plural variable capacitance devices, wherein a first variable capacitance device of the plural variable capacitance devices is connected with the node to receive the tuned voltage, and the other variable capacitance devices of the plural variable capacitance devices are connected with an output terminal of the unit gain buffer through a switch so as to receive the tuned voltage; and a feedback circuit comprising a frequency divider and a frequency detector, wherein the frequency divider performs a frequency division on the oscillation signal according to a divisor, so that the feedback signal is outputted from the frequency divider, wherein the frequency detector counts the oscillation signal, wherein during a calibrating process, the switch is in a closed state and the second charging current or the second discharging current is used as the driving current, wherein during a normal operation, the switch is in an open state and the first charging current or the first discharging current is used as the driving current.