Patent ID: 9608602
Date: 2017-03-28
CPC Classifications: G01R,G06F,H01L,H03K

Claim:
1. An apparatus, comprising: a first ring oscillator circuit comprising a first delay stage that includes inverting logic elements coupled by a first interconnect of a first interconnect layer in an integrated circuit (IC); a second ring oscillator circuit comprising a second delay stage that includes inverting logic elements coupled by a second interconnect in the IC, wherein the second interconnect is disposed in proximate alignment with the first interconnect; a processing circuit configured to: a multiplexer that receives a feedback signal corresponding to an output of the second ring oscillator circuit and one or more phase versions of the first oscillating signal, wherein a control signal selects an output of the multiplexer from the feedback signal, the one or more phase versions of the first oscillating signal and one or more fixed-state signals, wherein a current corresponding to the output of the multiplexer and provided in the second interconnect modifies the one or more characteristics of the first interconnect.