Patent ID: 9729148
Date: 2017-08-08
CPC Classifications: H01L,H03K

Claim:
1. A semiconductor device including a plurality of logic cells, the semiconductor device comprising: a first element layer; a second element layer; and first to k-th wiring layers (k is an integer of greater than 3), wherein each of the first element layer and the second element layer is provided with a plurality of transistors, wherein the first to k-th wiring layers are stacked in this order, wherein the first element layer is provided under the first wiring layer, wherein the second element layer is provided between the second wiring layer and the third wiring layer, wherein the transistors of the logic cells are provided in the first element layer, wherein wirings of the logic cells are provided in the first wiring layer or the second wiring layer, wherein an input port and an output port of the logic cell are provided in the third wiring layer, wherein wirings of the first wiring layer and the second wiring layer contain tungsten, and wherein wirings of the third to k-th wiring layers contain copper or aluminum.