Patent ID: 9621430
Date: 2017-04-11
CPC Classifications: H04L

Claim:
1. A design support apparatus comprising: a memory; and a processor coupled to the memory, wherein the processor executes a process including: accepting inputs of a number of nodes to be connected to a network, a number of networks to be connected to each node, and the number of nodes to be connected to a terminating device being a relay device to be connected to the nodes among relay devices relaying communication between nodes; calculating a number of terminating devices included in each network based on the number of nodes, the number of networks, and the number of nodes to be connected to the terminating device, the numbers having been accepted at the accepting; specifying nodes to be connected to each terminating device for each network such that each node is connected to any of the number of terminating devices calculated at the calculating and that individually different combinations of nodes are connected to the terminating devices included in all the networks; and outputting connection information indicating that the nodes specified at the specifying are connected to the terminating devices, wherein the specifying includes calculating a number of ports included in the each terminating device and designing connection relationships between the terminating devices for each network based on the calculated number of ports, the number of terminating devices, and the number of nodes, wherein the specifying further includes accepting designation of a number of levels of switches in each network from a user, and designing a tree network having the accepted number of levels.