Patent ID: 9569272
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A device for processing digital data of a system on electronic chip type, the device comprising: a plurality of different calculation nodes and buffer memory nodes, the device using distributed execution of multiple data processing operations on the calculation nodes using a data-flow processing model in which each data processing operation destined to be carried out on the device is modelled by a directed graph which is made up of the calculation nodes of the device, the buffer memory nodes of the device, and directed links for transfer of data through the calculation nodes and the buffer memory nodes of the device from at least one input buffer memory node to at least one output buffer memory node; and an identification processor configured to, from a valued directed multi-graph, which illustrates a relationship between each of the data processing operations and each of the plurality of different calculation nodes and the buffer memory nodes of the device, including a data processing operation that each different calculation node executes, and which is made up of a union of several distinct processing graphs divided into several valued directed sub-multi-graphs called chunks, input and output nodes of the chunks being buffer memory nodes of the multi-graph, and at least an output buffer memory node of a first chunk of the chunks being an input buffer memory node of a second chunk of the chunks, select a coordination module for each chunk from among the calculation nodes of the respective chunk, such that the coordination module is a calculation node of a sub-set of the respective chunk having the most output links to other first nodes or the most input links from other second nodes, wherein the identification processor determines the other first nodes according to a first criterion, and the other second nodes according to a second criterion, at least one calculation node of the plurality of different calculation nodes that is included in one of the chunks, is configured to perform two different processing operations of the multiple data processing operations, each selected coordination module is configured to synchronise portions of processing operations that are to be executed in the chunk with which the respective coordination module is associated, independently of portions of processing operations that are to be executed in other chunks, and the plurality of different calculation nodes and buffer memory nodes are hardware components.