Patent ID: 9653397
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: a semiconductor chip; a substrate including an accommodating portion configured to accommodate the semiconductor chip and a via hole formed to vertically pass in an outer side of the semiconductor chip; a sealing material configured to mold the semiconductor chip and the substrate to be integrated; a through wiring configured to vertically extend from an inner circumferential surface of the via hole; a through member accommodated inside the through wiring; a wiring portion including a wiring layer configured to electrically connect the semiconductor chip and one side of the through wiring; and an external connection portion electrically connected to the other side of the through wiring and configured to be electrically connectable to the outside, wherein an end portion of the through wiring connected to the wiring layer is coplanar with one surface of the substrate and the through wiring and the wiring layer are in direct contact with each other.