Patent ID: 9746516
Date: 2017-08-29
CPC Classifications: G01R

Claim:
1. A method for identifying related latches for use during testing of a chip having a plurality of latches, the method comprising: selecting a first target latch, from the plurality of latches, for identifying latches related to the first target latch; tracing, based on selecting the first target latch, data input from the first target latch back to a first set of source latches from the plurality of latches, wherein data input into each latch in the first set of source latches propagates to the first target latch; tracing data propagation from the first set of source latches to a set of sink latches from the plurality of latches, each latch in the set of sink latches receiving data propagated from input into at least one latch in the first set of source latches, the set of sink latches consisting of the first target latch and related latches; recording the first target latch and the related latches in a related latches table for the chip, wherein the related latches table lists related latches for each target latch listed in the table, the related latches for each target latch indicating latches for data collection during testing when the associated target latch is failing; identifying the first target latch as failing; determining, in response to identifying the first target latch as failing, a diagnostic set of latches, the diagnostic set of latches comprising the target latch and the related latches, wherein the related latches are identified from the related latches table; performing, after determining the diagnostic set of latches, one or more tests on the chip; collecting test output data from the diagnostic set of latches, the test output data produced during the one or more tests; loading the collected test output data into a diagnostic tool; and determining, by the diagnostic tool, possible faults using the test output data and a fault model.