Patent ID: 9564229
Date: 2017-02-07
CPC Classifications: G11C

Claim:
1. A method of programming a three-dimensional (3D) memory cell array which includes a plurality of memory cell strings, each of the memory cell strings extending in a direction vertical to a substrate, an upper end of the memory cell string being connected with a bit line and a lower end of the memory cell string being connected with a common source line (CSL), and each of the memory cell strings including a plurality of memory cells, each of the plurality of memory cells being programmed by applying a programming voltage to a word line connected with the memory cell, the method comprising: executing a first programming loop, the first programming loop comprising: executing a second programming loop, the second programming loop comprising: wherein the second programming voltage is greater than the first programming voltage and the second common source line voltage is greater than the first common source line voltage respectively.