Patent ID: 9601190
Date: 2017-03-21
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor integrated circuit comprising: N (≧1) input wiring lines, N being an integer number; M (≧1) output wiring lines, M being an integer number; N first wiring lines corresponding to the N input wiring lines, each of the first wiring lines connecting to a corresponding input wiring line; K (>M) second wiring lines crossing the N first wiring lines, K being an integer number; a plurality of first resistive change elements disposed at intersections of the first wiring lines and the second wiring lines, each of the first resistive change elements including a first electrode connecting to a corresponding one of the first wiring lines, a second electrode connecting to a corresponding one of the second wiring lines, and a first resistive change layer disposed between the first electrode and the second electrode; a first controller configured to control a voltage applied to the first wiring lines; a second controller configured to control a voltage applied to the second wiring lines, and the second controller including a current limitation circuit configured to limit a current flowing through the second wiring lines; and a selection circuit disposed between the output wiring lines and the second wiring lines to select M second wiring lines from the K second wiring lines, and to connect the selected M second wiring lines to the output wiring lines.