Patent ID: 9673849
Date: 2017-06-06
CPC Classifications: H04B

Claim:
1. A circuit comprising: a plurality of input ports; and a receiver component; wherein the circuit is configured to: receive a single-ended data signal on a first input port of the plurality of input ports and couple the single-ended data signal to a positive input terminal of the receiver component; receive a differential clock signal on second and third input ports of the plurality of input ports; couple a first signal component of the differential clock signal to a first end of a first resistor; couple a second signal component of the differential clock signal to a first end of a second resistor; couple a second end of the first resistor to a second end of the second resistor; couple a capacitor between the second end of the first resistor and ground; and utilize the second end of the first resistor as an average of the differential clock signal; couple the second end of the first resistor to an input of a unity gain buffer; and couple an output, representing a reference signal, of the unity gain buffer to the negative input terminal of the receiver component.