Patent ID: 9571103
Date: 2017-02-14
CPC Classifications: G11C,H01L,H03K

Claim:
1. A lookup table comprising: a memory including a first memory element and a second memory element; and multiplexers electrically connected to each other in a binary tree with multi levels, the multiplexers including a first multiplexer in the lowermost level of the multi levels, wherein a first input terminal of the first multiplexer is electrically connected to the first memory element, wherein a second input terminal of the first multiplexer is electrically connecter to the second memory element, wherein each of the first memory element and the second memory element comprises: wherein one of a source and a drain of the first transistor is electrically connected to one of electrodes of the capacitor, a gate of the n-channel transistor, and a gate of the p-channel transistor, wherein the other of the electrodes of the capacitor is electrically connected to the terminal, wherein one of a source and a drain of the n-channel transistor is electrically connected to one of a source and a drain of the p-channel transistor, wherein the input terminal is electrically connected to the other of the source and the drain of the p-channel transistor, and wherein the output terminal is electrically connected to the one of the source and the drain of the n-channel transistor and the one of the source and the drain of the p-channel transistor.