Patent ID: 9697909
Date: 2017-07-04
CPC Classifications: G09G,G11C

Claim:
1. A shift register, comprising: a first switch electrically coupled to a control terminal and configured to selectively conduct a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal; a second switch electrically coupled to the first switch and configured to receive a second clock signal different from the first clock signal and a third clock signal phase inverted to the second clock signal and to selectively force a voltage level of the first output signal equal to a voltage level of the second clock signal based on the second clock signal and the third clock signal; a third switch electrically coupled to the first switch and configured to selectively force a voltage level over the control terminal essentially equal to a first voltage based on a first input signal; and a fourth switch electrically coupled to the first switch and configured to receive the second clock signal and the third clock signal and to selectively force the voltage level over the control terminal equal to the voltage level of the second clock signal based on the second clock signal and the third clock signal.