Patent ID: 9680031
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising steps of: (a) forming a first wiring over a semiconductor substrate; (b) forming a first insulating film over the first wiring: (c) forming a semiconductor layer over the first insulating film; (d) forming a first gate insulating film over the semiconductor layer; (e) patterning the first gate insulating film; (f) after the step (e), patterning the semiconductor layer by using the first gate insulating film as a mask; (g) after the step (f), forming a first side wall which is made of a second insulating film, over a side surface of the semiconductor layer so as to surround the semiconductor layer in a plan view; (h) forming a first gate electrode over the first gate insulating film, the first side wall and the first insulating film; (i) patterning the first gate electrode such that the first gate insulating film is exposed from the first gate electrode in a gate length direction; (j) after the step (i), forming a third insulating film over the first gate electrode, the first gate insulating film, the first side wall and the first insulating film; and (k) forming a first contact for a drain electrode and a second contact for a source electrode in the third insulating film and the first gate insulating film in order to be connected to the semiconductor layer, wherein, after the step (i), as considered in a gate width direction, the first gate electrode is located over the first gate insulating film, the first side wall, and parts of the first insulating film disposed to opposite sides of the semiconductor layer in a region surrounding the semiconductor layer and the first sidewall in the plan view, and wherein, in the gate width direction in the plan view, the first side wall has portions located between the side surface of the semiconductor layer and portions of the first gate electrode formed over the parts of the first insulating film.