Patent ID: 9583347
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A manufacturing method for a semiconductor device, the method comprising: forming a first resist pattern on a substrate, the first resist pattern including, in a planar view with respect to an upper surface of the substrate, a plurality of first line patterns each extending continuously along a first direction and a plurality of third line patterns each extending continuously along a second direction intersecting the first direction, such that each first line pattern contacts the plurality of the third line patterns and that each third line pattern contacts the plurality of the first line patterns; injecting a first impurity into the substrate by using the first resist pattern; removing the first resist pattern; forming a second resist pattern on the substrate, the second resist pattern including, in the planar view, a plurality of second line patterns each extending continuously along the first direction and a plurality of fourth line patterns each extending continuously along the second direction, such that each second line pattern contacts the plurality of the fourth line patterns and that each fourth line pattern contacts the plurality of the second line patterns; and injecting a second impurity into the substrate by using the second resist pattern, wherein, in the forming of the second resist pattern, the plurality of the second line patterns are respectively formed between two adjacent patterns of the plurality of the first line patterns, and the plurality of the fourth line patterns are respectively formed between two adjacent patterns of the plurality of the third line patterns.