Patent ID: 9705490
Date: 2017-07-11
CPC Classifications: H03K

Claim:
1. A driver circuit for a single wire protocol slave unit, the driver circuit comprising: at least one current mirror comprising a first transistor and a second transistor, wherein the gate of both transistors is connected to a bias node, and wherein the second transistor is adapted to conduct a mirror current equal to a current conducted by the first transistor multiplied by a predetermined factor, a bias transistor for selectively connecting and disconnecting the bias node to and from a predetermined potential in response to a control signal, a current boosting element for providing a boost current to the bias node for a predetermined period of time when the control signal causes the bias transistor to disconnect the bias node from the predetermined potential, a further current mirror coupled in cascade with the current mirror, the further current mirror comprising a third transistor and a fourth transistor, wherein the gate of both transistors is connected to a further bias node, and wherein the fourth transistor is adapted to conduct a further mirror current equal to a current conducted by the third transistor multiplied by a further predetermined factor, a further bias transistor for selectively connecting and disconnecting the further bias node to and from a further predetermined potential in response to the control signal, a further current boosting element for providing a further boost current to the further bias node for the predetermined period of time when the control signal causes the further bias transistor to disconnect the further bias node from the further predetermined potential, and a yet further current mirror coupled in cascade with the current mirror and the further current mirror, the yet further current mirror comprising a fifth transistor and a sixth transistor, wherein the gate of the fifth transistor is connected to the gate of the sixth transistor, and wherein the sixth transistor is adapted to conduct a yet further mirror current equal to a reference current conducted by and provided to the fifth transistor multiplied by a yet further predetermined factor.