Patent ID: 9646890
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor structure, comprising: an NMOS transistor and a PMOS transistor above a silicon substrate; a first gate stack for the PMOS transistor, the first gate stack comprising a workfunction metal layer; a second gate stack for the NMOS transistor, the second gate stack comprising a layer comprising titanium and aluminum, wherein the workfunction metal layer of the first gate stack is not included in the second gate stack, and wherein the layer comprising titanium and aluminum is over the workfunction metal layer in the first gate stack; a source region and a drain region for the NMOS transistor; a raised source region and a raised drain region for the PMOS transistor, the raised source and drain regions comprising a silicon germanium layer creating a stressed channel for the PMOS device, and the raised source and drain regions extending above a surface of the silicon substrate over which the first gate stack is formed; and a nitride layer over the silicon germanium layer and co-planar with an uppermost surface of the first gate stack.