Patent ID: 9559177
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method comprising: forming a control gate structure over a substrate; depositing a charge storage layer over the control gate structure; depositing a memory gate layer over the charge storage layer; applying a first etching process to the memory gate layer to form a first memory gate structure and a second memory gate structure, wherein the first memory gate structure and the second memory gate structure are formed along opposite sidewalls of the control gate structure; removing the second memory gate structure; applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure; forming a first spacer layer over the substrate; applying a third etching process to the first spacer layer to form a first thin spacer along a sidewall of the first memory gate structure and a second thin spacer along a sidewall of the control gate structure, wherein a top surface of the first memory gate structure is exposed after the step of applying the third etching process to the first spacer layer; forming a top spacer over the first memory gate structure after removing a portion of the first memory gate structure; and forming a first drain/source region adjacent to the first memory gate structure and a second drain/source region adjacent to the control gate structure.