Patent ID: 9600418
Date: 2017-03-21
CPC Classifications: G06F,Y02D

Claim:
1. A method comprising: converting, by a computing device comprising one or more processors, program code into an intermediate representation comprising instructions for execution by a central processing unit (CPU); determining, by the computing device, one or more candidate memory references associated with an L1 data cache for storage in a tagless access buffer (TAB), the determination based at least in part on analysis of the instructions for the program code; executing, by the computing device, a load or store instruction associated with the program code, wherein the program code, when executed, accesses a register to identify a reference to the TAB, wherein the reference to the TAB is identified based at least in part on (i) a base address register comprising at least a portion of the one or more candidate memory references to the TAB and (ii) metadata associated with the base address register; and allocating, by the computing device, at least a portion of the one or more candidate memory references in the TAB; wherein the TAB comprises a first line buffer for storing the one or more candidate memory references, the method further comprising: determining, by the computing device, that a plurality of memory references to a strided access pattern spans two consecutive lines in L1 data cache; allocating, by the computing device, a second line buffer in the TAB for receiving one or more additional candidate memory references; and prefetching, by the computing device, two lines from the L1 data cache for storage in one of the first line buffer or the second line buffer in the TAB.