Patent ID: 9710229
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. A data processing apparatus comprising: processing circuitry configured to perform a floating-point square root operation for determining a square root of a radicand value R having a radicand exponent and a radicand mantissa to generate a result value having a result exponent and a result mantissa; wherein the processing circuitry comprises: first square root processing circuitry configured to perform the floating-point square root operation for radicand values which are not an exact power of two; second square root processing circuitry configured to perform the floating-point square root operation for radicand values which are an exact power of two, wherein the second square root processing circuitry is configured to generate the result value in fewer processing cycles than the first square root processing circuitry; and power-of-two detection circuitry configured to detect whether the radicand value is an exact power of two, to control the processing circuitry to output the result value generated by the first square root processing circuitry if the radicand value is not an exact power of two, and to control the processing circuitry to output the result value generated by the second square root processing circuitry if the radicand value is an exact power of two.