Patent ID: 9704541
Date: 2017-07-11
CPC Classifications: G11C

Claim:
1. A method comprising: receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines, wherein the first bit-vector comprises a first group of data values and the second bit-vector comprises a second group of data values; storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and the third number of sense lines; and performing an operation on the first bit-vector and the second bit-vector.