Patent ID: 9570467
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor structure, the method comprising: forming a plurality of fin active regions above a substrate; forming a plurality of dummy gate structures above the plurality of fin active regions; forming spacers adjacent the sidewalls of each of the plurality of dummy gate structures; removing the dummy gate structures to form a plurality of gate locations defined by the spacers; forming a first conformal dielectric layer to remain in a second of the plurality of gate locations but not in a first of the plurality of gate locations, wherein the first conformal dielectric layer is formed over a top surface of one or more of the plurality of fin active regions and along both sidewalls of each of the one or more of the plurality of fin active regions; and, subsequently, forming a second conformal dielectric layer in the plurality of gate locations and on the first conformal dielectric layer; and, subsequently, forming a low voltage device in the first of the plurality of gate locations and a high voltage device in the second of the plurality of gate locations, wherein the substrate is a bulk single crystalline silicon substrate, and the plurality of fin active regions is formed from and remain continuous with the bulk single crystalline silicon substrate in the low voltage device and in the high voltage device.