Patent ID: 9659799
Date: 2017-05-23
CPC Classifications: G05B,H01L,Y02P

Claim:
1. A method comprising: analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool comprising an expected time to transfer a first wafer from a wafer handling chamber to a first process module, an expected time to transfer the first wafer from the first process module to the wafer handling chamber, an expected time to transfer a second wafer from the wafer handling chamber to a second process module, and an expected time to transfer the second wafer from the second process module to the wafer handling chamber, the semiconductor processing tool including the first process module and the second process module; and automatically generating, by a computer program, a wafer processing plan based on the analysis, wherein the wafer processing plan, when executed by the processing tool, causes the semiconductor processing tool to: wherein execution of the wafer processing plan by the semiconductor processing tool causes an idle time for the wafer handling chamber prior to unloading the first wafer from the first process module to be about equal to an idle time for the wafer handling chamber after loading the third wafer into the first process module, and