Patent ID: 9715923
Date: 2017-07-25
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a first tunnel transistor and a second tunnel transistor whose gates and drains are cross-coupled; a first node connected to the drain of the first tunnel transistor; a second node connected to the drain of the second tunnel transistor; a first access transistor connecting the first node to a first write bit line; a second access transistor connecting the second node to a second write bit line; and a third access transistor that supplies a voltage corresponding to a voltage of the first node to a first read bit line, wherein the first access transistor is constructed of a tunnel transistor connected in such a manner as that current flows from the first node to the first write bit line upon turning-on in a forward biased state, the second access transistor is constructed of a tunnel transistor connected in such a manner as that current flows from the second node to the second write bit line upon turning-on in a forward biased state, and the semiconductor memory device further comprises a voltage supply circuit that supplies a voltage to the first and second write bit lines to apply reverse-bias voltages based on the voltage between sources and drains of the first and second access transistors in response to a refresh control signal upon a refresh operation.