Patent ID: 9576852
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method of producing an integrated circuit comprising: forming an interconnect in a first interlayer dielectric; forming a first cap overlying the first interlayer dielectric adjacent to the interconnect; recessing the interconnect after forming the first cap; forming a second cap overlying the first cap layer and the interconnect after recessing the interconnect; forming a second interlayer dielectric overlying the first interlayer dielectric, the interconnect, the first cap, and the second cap; forming a contact through the second interlayer dielectric, wherein the contact comprises an overlap region and a connection region, wherein the overlap region directly overlies the first interlayer dielectric adjacent to the interconnect and the connection region directly contacts the interconnect, wherein the first cap is positioned between the overlap region of the contact and the first interlayer dielectric, and after forming the contact the second cap layer is directly in contact with a portion of the interconnect surface.