Patent ID: 9711511
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor structure, comprising: horizontally adjacent layers of conductive material; a plurality of transistors in process on the horizontally adjacent layers of conductive material, each transistor comprising a vertical channel and a gate electrode wrapped around the vertical channel, each of the adjacent layers of conductive material being a shared bottom source/drain electrode for some of the plurality of transistors; a cross-coupled contact having at least two portions, each portion on one of the adjacent layers of conductive material; non-shared top source/drain electrodes on top of each vertical channel and associated gate electrode; and wherein the plurality of transistors comprises at least two sets of transistors, each of the at least two sets of transistors having only a pull-up transistor, at least two pulldown transistors and at least two pass gate transistors.