Patent ID: 9559707
Date: 2017-01-31
CPC Classifications: H03L

Claim:
1. A phase-locked loop (PLL) comprising: a loop filter comprising a sampling capacitor and a holding capacitor coupled in parallel via a switching element, the loop filter configured to generate a filter output signal based at least on a charge output signal indicating a first time period during which the sampling capacitor is charged; a voltage controlled oscillator (VCO) coupled to the loop filter and configured to generate an oscillator output signal with a frequency corresponding to the filter output signal; a divider coupled to the VCO to receive the oscillator output signal, the divider configured to perform frequency division on the oscillator output signal to generate a divider clock signal having a same phase as the oscillator output signal but a frequency different than the oscillator output signal; and a phase frequency detector coupled to the divider to receive the divider clock signal, the phase frequency detector configured to generate the charge output signal based on a phase difference between the divider clock signal and a reference clock signal, the phase frequency detector further configured to prevent locking of the PLL at a sub-harmonic of a frequency of the oscillator output signal, the phase frequency detector comprising a gating element configured to generate a clear output signal causing the sampling capacitor to discharge charge stored in the sampling capacitor to a low reference voltage of the loop filter during a second time period defined as a period during which a charge is not transferred between the sampling capacitor and the holding capacitor via the switching element, and during which the divider clock signal and the reference clock signal are inactive.