Patent ID: 9640126
Date: 2017-05-02
CPC Classifications: G09G

Claim:
1. An array substrate, comprising: a plurality of data lines, connected with a source driver integrated circuit (IC); a plurality of gate lines, intercrossed with the plurality of data lines and connected with a gate driver IC; and a plurality of pixel units, arranged in an array and defined by the plurality of data lines and the plurality of gate lines intercrossed with each other, wherein each row of pixel units are connected with a first gate line and a second gate line, the first gate line is configured to receive a gate driving signal outputted by the gate driver IC in a case of displaying an odd frame image, the second gate line is configured to receive a gate driving signal outputted by the gate driver IC in a case of displaying an adjacent even frame image, each pixel unit comprises a first thin-film transistor (TFT) and a second TFT, the first TFT is connected with the first gate line, and the second TFT is connected with the second gate line, wherein each column of pixel units is connected with two data lines, two adjacent columns of pixel units share one data line; as for the same frame image, the source driving signals outputted by the source driver IC and received by two adjacent data lines have opposite polarity; and as for two adjacent frame images, the source driving signals outputted by the source driver IC and received by the same data line have the same polarity, wherein the first gate line is disposed at one side of each row of pixel units, and the second gate line is disposed at the other side of each row of pixel units, wherein four gate lines connected with two adjacent rows of pixel units are combined into a gate line unit, and wherein in a case that the four gate lines are a first gate line, a second gate line, a first gate line, and a second gate line in sequence,