Patent ID: 9564441
Date: 2017-02-07
CPC Classifications: G11C,H01L

Claim:
1. The process for forming a pair of cross-coupled PNP and NPN bipolar transistors in a selected region of a first conductivity type semiconductor substrate of an integrated circuit, the integrated circuit also including field effect transistors outside the selected region, the process comprising: introducing opposite conductivity type dopant into the selected region of the substrate to form a buried layer; introducing first conductivity type dopant into the selected region of the substrate above the buried layer; introducing additional opposite conductivity type dopant into a first portion of the selected region to form a shallow well vertically separated from the buried layer by the first conductivity type dopant; in a same process as used elsewhere on the integrated circuit to form gates of field effect transistors outside the selected region, forming a first field effect transistor gate over only a portion of the shallow well, and a second field effect transistor gate entirely over the shallow well; using the first field effect transistor gate and the second field effect transistor gate to mask underlying portions of the selected region, performing steps of: providing electrical connections to the first doped region, the second doped region, and the third doped region.