Patent ID: 9721653
Date: 2017-08-01
CPC Classifications: B82Y,G11C,H01L

Claim:
1. A data memory, comprising: a plurality of non-volatile re-programmable memory elements arranged in a three dimensional pattern defined by rectangular coordinates along x, y and z directions and with a plurality of parallel planes stacked in the z direction on top of a semiconductor substrate; a plurality of first conductive lines elongated in the z direction through the plurality of planes and arranged in a two dimensional rectangular array of rows in the x direction and columns in the y-direction; a plurality of second conductive lines elongated in the x-direction across each of the planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in each of the planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across each of the planes, the plurality of second conductive lines forming pairs of adjacent second conductive lines, wherein each non-volatile re-programmable memory element is connected between a corresponding first conductive line and a corresponding second conductive line crossing each other at an associated location of the plurality of locations; and a plurality of select devices arranged to individually couple a selected row of first conductive lines to respective sensing circuits via a plurality of third conductive lines, wherein, for each of the pairs of adjacent second conductive lines, each second conductive line is connected to only one corresponding row of first conductive line such that both of the second conductive lines of each pair are connected to the same row of first conductive lines and such that each connection made with each first conductive line of the corresponding row of first conductive lines is via a single corresponding non-volatile re-programmable memory element, wherein each memory element is positioned between a respective first conductive line and a respective second conductive line, and is in the plane of said plurality of planes where said respective second conductive line is placed, to contact the first conductive line in the y-direction, and wherein the individual memory elements are characterized by a level of electrical conductance that changes in response to an electrical stimulus applied thereto through the first and second conductive lines.