Patent ID: 9740255
Date: 2017-08-22
CPC Classifications: G06F,G11C

Claim:
1. A memory cell comprising: a flip-flop comprising a first inverter and a second inverter, the first inverter comprising a first magnetic tunneling junction element and a first field-effect transistor, the second inverter comprising a second magnetic tunneling junction element and a second field-effect transistor, the first inverter and the second inverter being cross coupled to each other; a power gating field-effect transistor; a third field-effect transistor; and a fourth field-effect transistor, wherein: respective pin layers of the first magnetic tunneling junction element and the second magnetic tunneling junction element are connected to a power supply line through the power gating field-effect transistor; a control terminal of the power gating field-effect transistor is connected to a bit select line; an output terminal of the first inverter is a node to which a free layer of the first magnetic tunneling junction element and a control terminal of the second field-effect transistor are connected, is grounded through the first field-effect transistor, and is connected to a bit line through the third field-effect transistor; an output terminal of the second inverter is a node to which a free layer of the second magnetic tunneling junction element and a control terminal of the first field-effect transistor are connected, is grounded through the second field-effect transistor, and is connected to an inverse bit line through the fourth field-effect transistor; and respective control terminals of the third field-effect transistor and the fourth field-effect transistor are connected to a word line.