Patent ID: 9710277
Date: 2017-07-18
CPC Classifications: G06F,Y02D

Claim:
1. A processor, comprising: a prefetch buffer to store a plurality of macro instructions; a clock circuit to provide an oscillating clock signal to be used by one of a plurality of circuits in the processor; macro instruction decode circuitry to determine a class of each macro instruction retrieved from the prefetch buffer and determine whether a macro instruction utilizes a displacement byte field and zero out the displacement byte field in the macro instruction in response to the macro instruction not utilizing the displacement byte field; a first decoder circuit of an instruction decoder circuit of the plurality of circuits to decode a first macro instruction into one or more opcodes; a floating point micro-operation tracker to track a floating point micro-operation, wherein the floating point micro-operation corresponds to a floating point macro instruction of the plurality of macro instructions, from a time when the corresponding floating point macro instruction is retrieved from the prefetch buffer to retirement of the floating point micro-operation and set a floating point pipeline clear flag indicating that, when set, no floating point micro-operations are currently being tracked, wherein an indication of retirement is to be provided by retirement circuitry to the floating point micro-operation tracker; and a clock management circuit to cause an oscillating clock signal entering a floating point circuit of the plurality of circuits to remain in a steady state for at least one clock cycle in response to the floating point pipeline clear flag being set.