Patent ID: 9564880
Date: 2017-02-07
CPC Classifications: H03K

Claim:
1. A circuit system comprising a frequency-multiplication circuit, the frequency-multiplication circuit comprising: a ring of a number (N) of serially connected delay-buffer elements that each provide an equal time delay (D), at least some of the delay-buffer elements having at least one pulse-locking injection port, the pulse-locking injection port being an edge driven pulse-locking injection port, the ring having a ring output port; and an injection-pulse-generation circuit comprising: a clock input port configured to receive a clock signal having a clock-signal frequency (F a pulse-selection input port configured to receive pulse-selection control signals; a plurality of injection-pulse output ports connected to respective pulse-locking injection ports of the delay-buffer elements; and balanced-delay selection-logic circuitry connected to the clock input port, the pulse-selection input port, and the injection-pulse output ports, wherein the injection-pulse generation circuit is configured to: generate balanced-delay injection-pulse signals by applying the balanced-delay selection-logic circuitry to the clock signal according to the pulse-selection control signals by generating one or more falling-edge injection-pulse signals responsive to one or more respective falling edges of the clock signal; and provide an injection-locked, frequency-multiplied ring output signal at the ring output port by transmitting the generated balanced-delay injection-pulse signals via the injection-pulse output ports to the respectively connected pulse-locking injection ports, the ring output signal having an output-signal frequency (F