Patent ID: 9727408
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. An error detection system connected to a memory in which data packets are stored, wherein the error detection system detects errors in the stored data packets, the error detection system comprising: a read signature generation circuit that (i) receives a first read address, a read clock signal, and a read enable signal, (ii) is connected to the memory for receiving a first data packet, (iii) generates a first read signature based on at least one of the first data packet and a read signature of a second data packet, and (iv) stores the first read signature; a write signature generation circuit that (i) receives a first write address, a write clock signal, and a write enable signal, (ii) is connected to the memory for receiving a third data packet, (iii) generates a first write signature based on at least one of the third data packet and a write signature of a fourth data packet, and (iv) stores the first write signature; a trigger generation circuit that generates a first trigger signal; a first latching circuit that (i) receives the first write address, the write enable signal, and the write clock signal, (ii) is connected to the trigger generation circuit for receiving the first trigger signal, and (iii) stores the first write address as a first latch write address when the first trigger signal and the write enable signal are active; a second latching circuit that (i) receives the write enable signal and the write clock signal, (ii) is connected to the trigger generation circuit and the write signature generation circuit for receiving the first trigger signal and the first write signature, respectively, and (iii) stores the first write signature as a first latch write signature when the first trigger signal and the write enable signal are active; a first synchronization and comparison circuit that (i) receives the read and write enable signals, and the first read address, (ii) is connected to the first latching circuit for receiving the first latch write address, and (iii) generates a comparison signal based on a comparison of the first latch write address with the first read address when the read enable signal is active; and a second synchronization and comparison circuit that (i) is connected to the first synchronization and comparison circuit, the second latching circuit, and the read signature generation circuit for receiving the comparison signal, the first latch write signature, and the first read signature, respectively, and (ii) generates a fault signal based on a comparison of the first latch write signature with the first read signature, wherein the fault signal indicates a presence of the errors in the stored data packets.