Patent ID: 9728542
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method for integrating vertical transistor and vertical electric fuses comprising: forming fins through a dielectric layer and a dummy gate stack on a substrate, the dummy gate stack including a bottom spacer, a dummy gate layer and a top spacer layer; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; removing the dummy gate layer and exposing sidewalls of the fins; blocking the fuse region to form a gate structure in the transistor region; blocking the transistor region and exposing the fuse region; conformally depositing a metal on exposed sidewalls of the fins in the fuse region; annealing the metal to form silicided fins to form fuses in the fuse region; and separating portions of the substrate to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.