Patent ID: 9741701
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor package, the method comprising: attaching an array of package substrates to a carrier, where each package substrate of the array of package substrates has passed testing prior to said attaching the array of package substrates; for each package substrate of the array of package substrates: encapsulating the array of package substrates, the semiconductor dies, and the stacking terminals in an encapsulating material; thinning the encapsulating material to expose a respective upper end of each of the stacking terminals; for each package substrate of the array of package substrates, forming a respective interposer on an upper surface of the encapsulating material and electrically connected to the respective stacking terminal attached to said each package substrate; removing the encapsulated array of package substrates, semiconductor dies, and stacking terminals from the carrier; and attaching a respective interconnection structure to each of the encapsulated array of package substrates on a side opposite the respective semiconductor die.