Patent ID: 9697872
Date: 2017-07-04
CPC Classifications: G06F,G11C

Claim:
1. A memory subsystem, comprising: a serial peripheral interface (SPI) double data rate (DDR) volatile memory component; a SPI DDR non-volatile memory component coupled to the SPI DDR volatile memory component; and a SPI DDR interface that accesses the SPI DDR volatile memory component and the SPI DDR non-volatile memory component, wherein the SPI DDR interface includes a plurality of parts distributed among respective separate components that include a processor, the SPI DDR volatile memory component and the SPI DDR non-volatile memory component, wherein the plurality of parts distributed among the separate components are a part of internal circuitry of the separate components, wherein the SPI DDR interface is operable to access data in the SPI DDR volatile memory component on leading and falling edges of a clock signal, and wherein the SPI DDR interface is operable to access data in the SPI DDR non-volatile memory component on leading and falling edges of the clock signal; and a stacked package comprising the SPI DDR volatile memory component stacked with the SPI DDR non-volatile memory component and a pin to enable or disable the SPI DDR volatile memory component or the SPI DDR non-volatile memory component, wherein the SPI DDR volatile memory component comprises an SPI DDR pseudostatic random access memory (PSRAM) and the SPI DDR non-volatile memory component comprises an SPI DDR flash memory.