Patent ID: 9536818
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a substrate comprising a conductive trace, the conductive trace projecting outwardly from the substrate and in contact with a solder material, wherein a planar surface of the conductive trace is in direct contact with the solder material; and a chip comprising a bump structure electrically coupled to an under bump metal layer, the bump structure providing the solder material and being coupled to the conductive trace to form a bump-on-trace (BOT) interconnection in the semiconductor package, wherein a portion of the planar surface of the conductive trace is in direct contact with an organic solderability preservative (OSP) layer, the planar surface is partially free of the OSP layer, and the OSP layer has a thickness less than about 0.30 microns (μm).