Patent ID: 9641369
Date: 2017-05-02
CPC Classifications: H04L,H05B

Claim:
1. A decoding circuit configured for assembling telegram data patterns from multiple encoded digital data frames demodulated from a low frequency, large amplitude carrier signal modulated with higher frequency, multiple encoded digital data frames, the decoding circuit comprising: a period timer to establish an inter-transition time period between each transition within each of the multiple encoded digital data frames wherein, the inter-transition time period is the time between each transition of the encoded digital data frames between a first data level and a second data level and between the second data level and the first data level; an inter-transition comparator in communication with the period timer and configured to compare each of the inter-transition time periods with valid inter-transition time periods between each transition of the encoded digital data frames for determining when the inter-transition time periods represent valid data frame patterns or are an error; a data extractor configured to receive valid encoded digital data frames from the inter-transition comparator for extracting transmitted digital data frames from within the valid data encoded digital data frames; and a command formatter configured to receive the extracted digital data frames from the data extractor for assembling the telegram data patterns for transfer for subsequent processing.