Patent ID: 9711564
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A preparation method for a high-voltage LED device integrated with a pattern array, characterized in that, comprising the following process steps: a) providing a substrate, and forming a N—GaN limiting layer, an epitaxial light-emitting layer and a P—GaN limiting layer on the substrate in sequence; b) isolating the N—GaN limiting layer, the epitaxial light-emitting layer and the P—GaN limiting layer on the substrate into a plurality of pattern units by means of photo lithography and etching process, the plurality of pattern units comprising a first row of pattern units and a second row of pattern units, wherein each pattern unit in the first row comprises a triangular shape having a similar orientation, each pattern unit in the second row comprises a similar shape having a similar orientation, the first row occupying a first width dimension upon the substrate, the second row occupying a second width dimension upon the substrate, the first width dimension overlapping the second width dimension, and the plurality of the pattern units are distributed in array and arranged as a quadrangle; c) connecting each pattern unit with conductive materials to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips.