Patent ID: 9748133
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method, comprising: defining a conductive line pattern layer over a first dielectric layer, wherein the first dielectric layer is disposed over a second dielectric layer, and wherein an opening in the conductive line pattern layer exposes a first portion of the first dielectric layer, the first portion having a first width; forming spacers along sidewalls of the opening, wherein after forming the spacers a second portion of the first dielectric layer is exposed, the second portion of the first dielectric layer having a second width; etching the second portion of the first dielectric layer using the spacers as a mask to expose a portion of the second dielectric layer; removing the spacers after etching the second portion of the first dielectric layer, the removing exposing third portions of the first dielectric layer; etching the third portions of the first dielectric layer to form a trench in the first dielectric layer, the trench having the first width; and etching the portion of the second dielectric layer to form a via hole in the second dielectric layer, the via hole having the second width.