Patent ID: 9613712
Date: 2017-04-04
CPC Classifications: G11C

Claim:
1. An address decoder circuit, designed to address and bias memory cells of a memory array of a non-volatile memory device, the circuit comprising: a charge-pump stage configured to generate a boosted negative voltage; a control stage, operatively coupled to the charge-pump stage to control switching on/off the charge-pump stage as a function of a configuration signal that determines the value of the boosted negative voltage; a decoding stage, configured so as to decode address signals received at its input and to generate biasing signals for addressing and biasing the memory cells, based on the decoded address signals and, in at least one given operating condition, of the boosted negative voltage; and a negative voltage management module having a regulator stage, configured to receive the boosted negative voltage from the charge-pump stage and to generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.