Patent ID: 9698144
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A Field Effect Transistor (FET), comprising: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; a source contact connected to source pad of each one of the FET cells; wherein the cells are disposed in a loop configuration; and including a gate pad disposed on an upper surface of the substrate connected to the plurality of gate electrodes; wherein the gate contact is disposed on an bottom surface of the substrate; and wherein an electrically conductive gate via passes through the substrate to electrically connect the gate contact to the gate pad.