Patent ID: 9721961
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor memory device, comprising: a plurality of first conducting layers stacked in a first direction, the first conducting layers extending in a second direction intersecting with the first direction, the first conducting layers being arranged in a third direction, the third direction intersecting with the first direction and the second direction; an interlayer insulating film disposed between the first conducting layers arranged in the third direction, the interlayer insulating film extending in the first direction; a second conducting layer disposed between the first conducting layers arranged in the third direction, the second conducting layer extending in the first direction, the second conducting layer having an approximately circular cross-sectional shape intersecting with the first direction; and a variable resistance layer that surrounds a peripheral area of the second conducting layer, the variable resistance layer being disposed at a position between the second conducting layer and the first conducting layer, wherein a width of one of the first conducting layers in the third direction is wider than a distance between the first conducting layers adjacent in the third direction, a width of an outer shape of the variable resistance layer that surrounds the peripheral area of the second conducting layer, in the third direction is wider than the distance between the first conducting layers adjacent in the third direction, and a width of the first conducting layer in the third direction where the first conducting layer is adjacent to the variable resistance layer in the third direction is narrower than a width of the first conducting layer in the third direction where the first conducting layer is not adjacent to the variable resistance layer in the third direction.