Patent ID: 9640764
Date: 2017-05-02
CPC Classifications: H01L,H03K

Claim:
1. A comparator, comprising: a first decoder, a second decoder, and a comparison circuit; each decoder comprising: a signal input terminal and a signal output terminal; the comparison circuit comprising: a first comparison unit for producing a greater-than-or-equal-to signal, and a second comparison unit for producing a less-than-or-equal-to signal; the first comparison unit comprising: a first carbon nanotube field effect transistor (CNFET), a second CNFET, a third CNFET, a fourth CNFET, a fifth CNFET, a sixth CNFET, a seventh CNFET, an eighth CNFET, a ninth CNFET, a tenth CNFET, an eleventh CNFET, a twelfth CNFET, a thirteenth CNFET, a fourteenth CNFET, a fifteenth CNFET, a sixteenth CNFET, a seventeenth CNFET, an eighteenth CNFET, a nineteenth CNFET, a twentieth CNFET, a twenty-first CNFET, a twenty-second CNFET, a twenty-third CNFET, a twenty-fourth CNFET, a twenty-fifth CNFET, a twenty-sixth CNFET, a twenty-seventh CNFET, a twenty-eighth CNFET, a twenty-ninth CNFET, a thirtieth CNFET, a thirty-first CNFET, a thirty-second CNFET, a thirty-third CNFET, a thirty-fourth CNFET, a thirty-fifth CNFET, a thirty-sixth CNFET, a thirty-seventh CNFET, and a thirty-eighth CNFET; the second comparison unit comprising: a thirty-ninth CNFET, a fortieth CNFET, a forty-first CNFET, a forty-second CNFET, a forty-third CNFET, a forty-fourth CNFET, a forty-fifth CNFET, a forty-sixth CNFET, a forty-seventh CNFET, a forty-eighth CNFET, a forty-ninth CNFET, a fiftieth-CNFET, a fifty-first CNFET, a fifty-second CNFET, a fifty-third CNFET, a fifty-fourth CNFET, a fifty-fifth CNFET, a fifty-sixth CNFET, a fifty-seventh CNFET, a fifty-eighth CNFET, a fifty-ninth CNFET, a sixtieth CNFET, a sixty-first CNFET, a sixty-second CNFET, a sixty-third CNFET, a sixty-fourth CNFET, a sixty-fifth CNFET, a sixty-sixth CNFET, a sixty-seventh CNFET, a sixty-eighth CNFET, a sixty-ninth CNFET, a seventieth CNFET, a seventy-first CNFET, a seventy-second CNFET, a seventy-third CNFET, a seventy-fourth CNFET, a seventy-fifth CNFET, and a seventy-sixth CNFET; each of the CNFET comprising: a gate, a drain, and a source; wherein: a first two-bit ternary signal is input into the signal input terminal of the first decoder; a first three-bit binary signal and a phase inverted signal of the first three-bit binary signal are output from the signal output terminal of the first decoder; a second two-bit ternary signal is input into the signal input terminal of the second decoder; and a second three-bit binary signal and a phase inverted signal of the second three-bit binary signal are output from the signal output terminal of the second decoder; the first CNFET, the second CNFET, the third CNFET, the fourth CNFET, the fifth CNFET, the sixth CNFET, the seventh CNFET, the eighth CNFET, the ninth CNFET, the tenth CNFET, the eleventh CNFET, the twelfth CNFET, the thirteenth CNFET, the fourteenth CNFET, the fifteenth CNFET, the sixteenth CNFET, the seventeenth CNFET, the eighteenth CNFET, and the nineteenth CNFET are all P-type CNFETs; and the twentieth CNFET, the twenty-first CNFET, the twenty-second CNFET, the twenty-third CNFET, the twenty-fourth CNFET, the twenty-fifth CNFET, the twenty-sixth CNFET, the twenty-seventh CNFET, the twenty-eighth CNFET, the twenty-ninth CNFET, the thirtieth CNFET, the thirty-first CNFET, the thirty-second CNFET, the thirty-third CNFET, the thirty-fourth CNFET, the thirty-fifth CNFET, the thirty-sixth CNFET, the thirty-seventh CNFET, and the thirty-eighth CNFET are all N-type CNFETs; both the source of the first CNFET and the source of the second CNFET are connected to a power supplier; the drain of the first CNFET, the drain of the second CNFET, the source of the third CNFET, the source of the fourth CNFET, the source of the fifth CNFET, and the source of the sixth CNFET are connected together; the drain of the fifth CNFET, the drain of the sixth CNFET, and the source of the seventh CNFET are connected; the drain of the third CNFET, the drain of the fourth CNFET, the drain of the seventh CNFET, the source of the eighth CNFET, the source of the ninth CNFET, the source of the tenth CNFET, and the source of the eleventh CNFET are connected; the drain of the tenth CNFET, the drain of the eleventh CNFET, and the source of the twelfth CNFET are connected; the drain of the eighth CNFET, the drain of the ninth CNFET, the drain of the twelfth CNFET, the source of the thirteenth CNFET, the source of the fourteenth CNFET, the source of the fifteenth CNFET, and the source of the sixteenth CNFET are connected; the drain of the thirteenth CNFET, the drain of the fourteenth CNFET, the drain of the fifteenth CNFET, the source of the seventeenth CNFET, the source of the eighteenth CNFET, and the source of the nineteenth CNFET are connected; the drain of the sixteenth CNFET, the drain of the seventeenth CNFET, the drain of the eighteenth CNFET, the drain of the nineteenth CNFET, the drain of the twentieth CNFET, the drain of the twenty-first CNFET, the drain of the twenty-second CNFET, and the drain of the twenty-seventh CNFET are connected and a connecting terminal thereof is an output terminal of the greater-than-or-equal-to signal; the source of the twentieth CNFET and the drain of the twenty-third CNFET are connected; the source of the twenty-third CNFET, the drain of the thirty-third CNFET, and the drain of the twenty-eighth CNFET are connected; the source of the twenty-eighth CNFET and the drain of the thirty-fourth CNFET are connected; the source of the twenty-seventh CNFET and the drain of the thirty-second CNFET are connected; the source of the twenty-first CNFET and the drain of the twenty-fourth CNFET are connected; the source of the twenty-fourth CNFET, the drain of the thirty-fifth CNFET, and the drain of the twenty-ninth CNFET are connected; the source of the twenty-ninth CNFET and the drain of the thirty-sixth CNFET are connected; the source of the twenty-second CNFET, the drain of the twenty-fifth CNFET, and the drain of the twenty-sixth CNFET are connected; the source of the twenty-fifth CNFET and the drain of the thirtieth CNFET are connected, the source of the thirtieth CNFET and the drain of the thirty-seventh CNFET are connected; the source of the twenty-sixth CNFET and the drain of the thirty-first CNFET are connected; the source of the thirty-first CNFET and the drain of the thirty-eighth CNFET are connected; the source of the thirty-second CNFET, the source of the thirty-third CNFET, the source of the thirty-fourth CNFET, the source of the thirty-fifth CNFET, the source of the thirty-sixth CNFET, the source of the thirty-seventh CNFET, and the source of the thirty-eighth CNFET are all grounded; the gate of the first CNFET, the gate of the eighth CNFET, the gate of the thirteenth CNFET, the gate of the twenty-first CNFET, the gate of the twenty-fifth CNFET, and the gate of the twenty-seventh CNFET are connected and a connecting terminal thereof are input with a third-bit signal of the first three-bit binary signal; the gate of the second CNFET, the gate of the third CNFET, the gate of the eighteenth CNFET, the gate of the twentieth CNFET, the gate of the thirty-first CNFET, and the gate of the thirty-second CNFET are connected and a connecting terminal thereof are input with a third-bit signal of the phase inverted signal of the second three-bit binary signal; the gate of the fourth CNFET, the gate of the fifteenth CNFET, the gate of the twenty-third CNFET, and the gate of the thirty-seventh CNFET are connected and a connecting terminal thereof are input with a second-bit signal of the phase inverted signal of the second three-bit binary signal; the gate of the fifth CNFET, the gate of the twelfth CNFET, the gate of the fourteenth CNFET, the gate of the twenty-eighth CNFET, the gate of the thirtieth CNFET, and the gate of the thirty-fifth CNFET are connected and a connecting terminal thereof are input with a first-bit signal of the first three-bit binary signal; the gate of the sixth CNFET, the gate of the ninth CNFET, the gate of the twenty-fourth CNFET, and the gate of the thirty-fourth CNFET are connected and a connecting terminal thereof are input with a first-bit signal of the phase inverted signal of the second three-bit binary signal; the gate of the seventh CNFET, the gate of the sixteenth CNFET, the gate of the twenty-second CNFET, and the gate of the thirty-third CNFET are connected and a connecting terminal thereof are input with a second-bit signal of the first three-bit binary signal; the gate of the tenth CNFET and the gate of the thirty-sixth CNFET are connected and a connecting terminal thereof are input with a second-bit signal of the second three-bit binary signal; the gate of the eleventh CNFET and the gate of the twenty-ninth CNFET are connected and a connecting terminal thereof are input with a second-bit signal of the phase inverted signal of the first three-bit binary signal; the gate of the seventeenth CNFET and the gate of the twenty-sixth CNFET are connected and a connecting terminal thereof are input with a first-bit signal of the phase inverted signal of the first three-bit binary signal; and the gate of the nineteenth CNFET and the gate of the thirty-eighth CNFET are connected and a connecting terminal thereof are input with a first-bit signal of the second three-bit binary signal; the thirty-ninth CNFET, the fortieth CNFET, the forty-first CNFET, the forty-second CNFET, the forty-third CNFET, the forty-fourth CNFET, the forty-fifth CNFET, the forty-sixth CNFET, the forty-seventh CNFET, the forty-eighth CNFET, the forty-ninth CNFET, the fiftieth-CNFET, the fifty-first CNFET, the fifty-second CNFET, the fifty-third CNFET, the fifty-fourth CNFET, the fifty-fifth CNFET, the fifty-sixth CNFET, and the fifty-seventh CNFET are all P-type CNFETs; and the fifty-eighth CNFET, the fifty-ninth CNFET, the sixtieth CNFET, the sixty-first CNFET, the sixty-second CNFET, the sixty-third CNFET, the sixty-fourth CNFET, the sixty-fifth CNFET, the sixty-sixth CNFET, the sixty-seventh CNFET, the sixty-eighth CNFET, the sixty-ninth CNFET, the seventieth CNFET, the seventy-first CNFET, the seventy-second CNFET, the seventy-third CNFET, the seventy-fourth CNFET, the seventy-fifth CNFET, and the seventy-sixth CNFET are all N-type CNFETs; both the source of the thirty-ninth CNFET and the source of the fortieth CNFET are connected to a power supplier; the drain of the thirty-ninth CNFET, the drain of the fortieth CNFET, the source of the forty-first CNFET, the source of the forty-second CNFET, the source of the forty-third CNFET, and the source of the forty-fourth CNFET are connected; the drain of the forty-third CNFET, the drain of the forty-fourth CNFET, and the source of the forty-fifth CNFET are connected; the drain of the forty-first CNFET, the drain of the forty-second CNFET, the drain of the forty-fifth CNFET, the source of the forty-sixth CNFET, the source of the forty-seventh CNFET, the source of the forty-eighth CNFET, and the source of the forty-ninth CNFET are connected; the drain of the forty-eighth CNFET, the drain of the forty-ninth CNFET, and the source of the fiftieth-CNFET are connected; the drain of the forty-sixth CNFET, the drain of the forty-seventh CNFET, the drain of the fiftieth-CNFET, the source of the fifty-first CNFET, the source of the fifty-second CNFET, the source of the fifty-third CNFET, and the source of the fifty-fourth CNFET are connected; the drain of the fifty-first CNFET, the drain of the fifty-second CNFET, the drain of the fifty-third CNFET, the source of the fifty-fifth CNFET, the source of the fifty-sixth CNFET, and the source of the fifty-seventh CNFET are connected; the drain of the fifty-fourth CNFET, the drain of the fifty-fifth CNFET, the drain of the fifty-sixth CNFET, the drain of the fifty-seventh CNFET, the drain of the fifty-eighth CNFET, the drain of the fifty-ninth CNFET, the drain of the sixtieth CNFET, and the drain of the sixty-fifth CNFET are connected and a connecting terminal thereof is an output terminal of the less-than-or-equal-to signal; the source of the fifty-eighth CNFET and the drain of the sixty-first CNFET are connected; the source of the sixty-first CNFET, the drain of the seventy-first CNFET, and the drain of the sixty-sixth CNFET are connected; the source of the sixty-sixth CNFET and the drain of the seventy-second CNFET are connected; the source of the sixty-fifth CNFET and the drain of the seventieth CNFET are connected; the source of the fifty-ninth CNFET and the drain of the sixty-second CNFET are connected; the source of the sixty-second CNFET, the drain of the seventy-third CNFET, and the drain of the sixty-seventh CNFET are connected; the source of the sixty-seventh CNFET and the drain of the seventy-fourth CNFET are connected; the source of the sixtieth CNFET, the drain of the sixty-third CNFET, and the drain of the sixty-fourth CNFET are connected; the source of the sixty-third CNFET and the drain of the sixty-eighth CNFET are connected; the source of the sixty-eighth CNFET and the drain of the seventy-fifth CNFET are connected; the source of the sixty-fourth CNFET and the drain of the sixty-ninth CNFET are connected; the source of the sixty-ninth CNFET and the drain of the seventy-sixth CNFET are connected; the source of the seventieth CNFET, the source of the seventy-first CNFET, the source of the seventy-second CNFET, the source of the seventy-third CNFET, the source of the seventy-fourth CNFET, the source of the seventy-fifth CNFET, and the source of the seventy-sixth CNFET are all grounded; and the gate of the thirty-ninth CNFET, the gate of the forty-first CNFET, the gate of the fifty-fifth CNFET, the gate of the fifty-eighth CNFET, the gate of the sixty-fourth CNFET, and the gate of the sixty-fifth CNFET are connected and a connecting terminal thereof are input with a third-bit signal of the phase inverted signal of the first three-bit binary signal; the gate of the fortieth CNFET, the gate of the forty-sixth CNFET, the gate of the fifty-first CNFET, the gate of the fifty-ninth CNFET, the gate of the sixty-third CNFET, and the gate of the seventieth CNFET are connected and a connecting terminal thereof are input with a third-bit signal of the second three-bit binary signal; the gate of the forty-second CNFET, the gate of the fifty-third CNFET, the gate of the sixty-first CNFET, and the gate of the seventy-fifth CNFET are connected and a connecting terminal thereof are input with the second-bit signal of the phase inverted signal of the first three-bit binary signal; the gate of the forty-third CNFET, the gate of the forty-seventh CNFET, the gate of the sixty-second CNFET, and the gate of the sixty-sixth CNFET are connected and a connecting terminal thereof are input with the first-bit signal of the phase inverted signal of the first three-bit binary signal; the gate of the forty-fourth CNFET, the gate of the fiftieth-CNFET, the gate of the fifty-second CNFET, the gate of the sixty-eighth CNFET, the gate of the seventy-second CNFET, and the gate of the seventy-third CNFET are connected and a connecting terminal thereof are input with the first-bit signal of the second three-bit binary signal; the gate of the forty-eighth CNFET and the gate of the sixty-seventh CNFET are connected and a connecting terminal thereof are input with the second-bit signal of the first three-bit binary signal; the gate of the forty-ninth CNFET and the gate of the seventy-fourth CNFET are connected and a connecting terminal thereof are input with the second-bit signal of the phase inverted signal of the second three-bit binary signal; the gate of the fifty-fourth CNFET, the gate of the forty-fifth CNFET, the gate of the sixtieth CNFET, and the gate of the seventy-first CNFET are connected and a connecting terminal thereof are input with the second-bit signal of the second three-bit binary signal; the gate of the fifty-sixth CNFET and the gate of the sixty-ninth CNFET are connected and a connecting terminal thereof are input with the first-bit signal of the phase inverted signal of the second three-bit binary signal; and the gate of the fifty-seventh CNFET and the gate of the seventy-sixth CNFET are connected and a connecting terminal thereof are input with the first-bit signal of the first three-bit binary signal.