Patent ID: 9583440
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a peripheral gate structure crossing over an active region and crossing over a device isolation region in a peripheral region of the device, the peripheral gate structure including a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern, wherein a silicon concentration in a first portion of the metal-silicon-nitride pattern is greater than a silicon concentration in a second portion of the metal-silicon-nitride pattern, the first portion being adjacent to the lower boundary and the second portion being adjacent to the upper boundary.