Patent ID: 9741725
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductor substrate having a main surface; a first semiconductor region of a first conductivity type formed in the semiconductor substrate, and extending in a first direction of the main surface; a first wire coupled with the first semiconductor region, and arranged over the semiconductor substrate in such a manner as to extend in the first direction; a first active region and a second active region formed in the first semiconductor region, and arranged in such a manner as to interpose the first wire therebetween in a second direction orthogonal to the first direction; a gate electrode layer formed over the main surface, and extending in the second direction in such a manner as to cross with each of the first active region and the second active region; a pair of second semiconductor regions having a second conductivity type of the opposite conductivity to the first conductivity type, and arranged in the first active region in such a manner as to interpose the gate electrode layer therebetween; and a pair of third semiconductor regions having the second conductivity type, and arranged in the second active region in such a manner as to interpose the gate electrode layer therebetween, wherein the gate electrode layer has a first gate electrode of the second conductivity type at the crossing part with the first active region, and has a second gate electrode of the second conductivity type at the crossing part with the second active region, and has a non-doped region between the first gate electrode and the second gate electrode.