Patent ID: 9559160
Date: 2017-01-31
CPC Classifications: B82Y,H01L

Claim:
1. A semiconductor structure, comprising: a first semiconductor device comprising a first nanowire disposed above a crystalline substrate, the first nanowire comprising a semiconductor material having a first global crystal orientation; a second semiconductor device comprising a second nanowire disposed above the crystalline substrate, the second nanowire comprising a semiconductor material having a second global crystal orientation different from the first global crystal orientation, and the second nanowire isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire and the crystalline substrate; and a third semiconductor device comprising a third nanowire disposed above the crystalline substrate, the third nanowire comprising a semiconductor material having a third global crystal orientation different from the first and second global crystal orientations, the third nanowire isolated from the crystalline substrate by a second isolation pedestal disposed between the third nanowire and the crystalline substrate, wherein a bottom surface of the first nanowire is co-planar with a bottom surface of the second nanowire and is co-planar with a bottom surface of the third nanowire, and wherein the first nanowire, the second nanowire and the third nanowire are all parallel with one another.