Patent ID: 9685225
Date: 2017-06-20
CPC Classifications: G11C

Claim:
1. A semiconductor storage device comprising: a plurality of memory cells provided in a matrix form; a plurality of word lines provided to correspond respectively to the rows of the memory cells; a first power supply for the memory cells; a second power supply which is supplied independently of the first power supply and supplied to a peripheral circuit which is electrically coupled to the memory cells; and a word line level fixing circuit for fixing the level of the word lines, to which the first power supply is supplied, wherein each of the memory cells comprises access n-channel MOS transistor whose gate are coupled to one of the word lines, wherein the word line level fixing circuit comprises: a plurality of level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a ground potential; and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to the second power supply, wherein the level fixing control circuit makes the level fixing transistors conductive when the second power supply is not supplied.