Patent ID: 9558156
Date: 2017-01-31
CPC Classifications: G06F

Claim:
1. A computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module, wherein the SpMM is of the form Y=AX, where X and Y are dense matricies and A is a sparse matrix, comprising a k-stage pipeline, the method comprising: interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t receiving, at the single FPGA module, a plurality of matrix values of a first matrix A, wherein first matrix A is a sparse matrix stored in a compressed format; receiving, at the single FPGA module, a plurality of matrix values of a second dense matrix, wherein second dense matrix comprises more than one column of values, wherein the plurality of matrix values of the second dense matrix include all values of the second dense matrix; assigning each of the matrix values of the first matrix A to all interleaved threads of a plurality of k interleaved threads on the k-stage pipeline; assigning each of the matrix values of the second dense matrix to an interleaved thread of the plurality of k interleaved threads on the k-stage pipeline such that the first result of thread t outputting a result matrix Y.