Patent ID: 9660059
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method for fabricating a field-effect transistor (FET) structure, the method comprising: forming a fin on a semiconductor substrate; forming a gate on a portion of the fin and the semiconductor substrate; epitaxially growing a semiconductor material on the fin; depositing oxide covering the fin and the epitaxially grown semiconductor material; recessing the deposited oxide and the epitaxially grown semiconductor material to expose a top portion of the fin; removing the fin to form a trench; forming another fin within the trench, such that the another fin directly laterally abuts and contacts a remaining portion of the epitaxially grown semiconductor material; and epitaxially growing an additional semiconductor material only on top of the another fin, wherein the additional semiconductor material fills gaps within the remaining portion of the epitaxially grown semiconductor material to restore an original shape of the epitaxially grown semiconductor material.