Patent ID: 9661752
Date: 2017-05-23
CPC Classifications: G01R,H01L,H05K,Y02P

Claim:
1. A circuit arrangement with a populated circuit carrier, comprising: a flat insulation carrier having a top side and a patterned metallization layer on the top side; a first power semiconductor chip arranged on a first section of the metallization layer, the first power semiconductor chip having a first lower chip load terminal electrically conductively connected to the first section; a shunt resistor arranged on a second section of the metallization layer, the shunt resistor having a lower main terminal electrically conductively connected to the second section; and an electrically conductive connection between the first section and the second section, the electrically conductive connection having a constriction of the metallization layer between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction.