Patent ID: 9666523
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A semiconductor wafer comprising: a semiconductor substrate having a first substrate surface and a second substrate surface; a plurality of build up layers on the first substrate surface, wherein the plurality of build up layers include conductive layers and conductive vias that are electrically coupled to device terminals that are located over the first substrate surface in a device area of the substrate; a plurality of first through substrate vias extending between the first and second substrate surfaces, wherein the plurality of first through substrate vias includes a first subset of one or more trench vias each having a primary axis aligned in a first direction, and a second subset of one or more trench vias each having a primary axis aligned in a second direction that is different from the first direction, and the plurality of first through substrate vias form an alignment pattern in an alignment area of the substrate; a second through substrate via extending between the first and second substrate surfaces in the device area of the substrate; and a conductive layer directly connected to the second substrate surface and to first ends of the plurality of first through substrate vias, wherein the conductive layer is patterned so that a first portion of the conductive layer is directly coupled to the plurality of first through substrate vias, and a second portion of the conductive layer is directly coupled to the second through substrate via, and wherein a conductive material void is present, at the second substrate surface, in the conductive layer.