Patent ID: 9711469
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor structure, comprising: a wafer substrate having a hollow region, a first surface, a second surface opposite to the first surface, and a third surface that surrounds the hollow region, wherein the hollow region is through the first and second surfaces; a first isolation layer located on the first surface of the wafer substrate and having a first opening, wherein the first opening is communicated with the hollow region, and a portion of the first isolation layer protrudes outward from the third surface of the wafer substrate; a conductive pad located on a surface of the first isolation layer facing away from the wafer substrate, the conductive pad covering the first opening so as to be exposed through the hollow region, and the conductive pad having a concave portion that faces the first opening, wherein the first isolation layer has an oblique surface that surrounds the first opening, such that a recess with U-shaped cross-section is formed by the concave portion and the oblique surface, and a diameter of the recess is smaller than a diameter of the hollow region; and a second isolation layer disposed along the second and third surfaces of the wafer substrate, and overlying the portion of the first isolation layer that protrudes outward from the third surface of the wafer substrate, and having a second opening exposing the conductive pad, wherein a diameter of the second opening of the second isolation layer is smaller than the diameter of the recess.