Patent ID: 9721857
Date: 2017-08-01
CPC Classifications: G01R,H01L

Claim:
1. A semiconductor device, comprising: a semiconductor substrate having a main surface which includes a first region and a second region; a field effect transistor formed in the first region; an element for voltage contrast inspection formed in the second region; a first insulating film and a first semiconductor layer stacked on the first region sequentially; a first gate electrode of the field effect transistor formed on the first semiconductor layer via a first gate insulating film; first semiconductor regions formed in the first semiconductor layer so as to sandwich therebetween a channel region of the field effect transistor in the first semiconductor layer under the first gate electrode, one of the first semiconductor regions being a source region of the field effect transistor and another of the first semiconductor regions being a drain region of the field effect transistor; first contact plugs respectively connected with the first semiconductor regions; a second insulating film and a second semiconductor layer stacked on the second region sequentially; a second gate electrode of the element for voltage contrast inspection formed directly over the second semiconductor layer via a second gate insulation film; and second contact plugs respectively connected with the second semiconductor layer without a PN junction, wherein the second semiconductor layer has no PN junction therein.