Patent ID: 9626293
Date: 2017-04-18
CPC Classifications: G06F

Claim:
1. A computer implemented method for assessing cache miss rates for a plurality of threads operating in a simultaneous multi-threading computer processor system having at least one shared cache and shared cache directory with a set of rows that are shared by the plurality of threads, the method comprising: monitoring, based upon use of the shared cache directory by the plurality of threads, first shared cache misses indicated by memory access requests to the shared cache directory; routing the memory access requests to the shared cache directory to a plurality of metering cache directories that each contain a subset of rows from the set of rows, the routing based upon an association between each thread and a corresponding metering cache directory of the plurality of metering cache directories; monitoring, based upon memory access requests for the plurality of metering cache directories, first single thread cache misses for the memory access requests for the plurality of metering cache directories and for each thread of the plurality of threads; determining a first sharing performance indication based upon the first shared cache misses and the first single thread cache misses; modifying at least one of the metering cache directories from the plurality of metering cache directories by changing the rows that are in the subset of rows; and determining a second sharing performance indication based upon second shared cache misses and second single thread cache misses that correspond to the modified rows in the subset of rows.