Patent ID: 9720037
Date: 2017-08-01
CPC Classifications: G01R

Claim:
1. A debug circuit, comprising: a memory configured to store, among code values calculated in accordance with a coding scheme that varies code values according to a signal sequence in a debug-target circuit, a first code value obtained by coding a leading first sequence of a plurality of sequences divided from a detection-target sequence detected from the signal sequence, a second code value obtained by coding a third sequence being a designated value sequence in each of two or more second sequences of the plurality of sequences, and a length of a fourth sequence being a don't-care value sequence in each of the second sequences; a code value calculation circuit configured to calculate third code values by coding the signal sequence in accordance with the coding scheme; a first sequence detection circuit configured to detect the first sequence based on comparison of the first code value with a difference between the current third code value and a fourth code value that is the third code value preceding the current third code value by a length of the first sequence; an expected value calculation circuit configured to calculate an expected value of the third code value at the end of the third sequence based on the second code value and a fifth code value that is one of the third code values at a time when the first sequence or the second sequence is detected; and a determination circuit configured to detect the end of the second sequence based on a length of the fourth sequence when the third code value matches the expected value, notify the expected value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of the detection-target sequence when the end of all the second sequences is detected.