Patent ID: 9543324
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. An array substrate, comprising: a base substrate and a plurality of pixel units located on the base substrate, each of the pixel units including a thin film transistor unit, wherein, the thin film transistor unit includes: a gate electrode located on the base substrate, a gate insulating layer located on the gate electrode, an active layer located on the gate insulating layer and opposed to the gate electrode in position, an ohmic layer located on the active layer, a source electrode and a drain electrode that are located on the ohmic layer and a resin passivation layer that are located on the source electrode and the drain electrode and covers the substrate, wherein, the resin passivation layer contacts with the source electrode and the drain electrode directly, and the resin passivation layer has a via hole passing therethrough for exposing a channel between the source electrode and the drain electrode.