Patent ID: 9535841
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. A cache memory comprising: a tag storage section including a plurality of entries each including a tag address and a remaining number of times for reference, one or more entries being retrieved for reference through searching the plurality of entries by a first address segment which configures part of an access address, wherein each of the plurality of entries includes a field indicating whether or not data in a cache line of the corresponding entry and data in a main memory are identical to each other; a data storage section configured to store pieces of data each corresponding to the plurality of entries; circuitry configured to: compare a second address-segment which configures another part of the access address with the tag address included in each of the one or more of the retrieved entries, thereby to find an entry having a tag address that matches the second address-segment; and select a piece of data corresponding to the found entry from the data storage section, in a read access, wherein, in the read access, the circuitry is configured to invalidate the found entry without performing a write-back operation after the read access in a case that the remaining number of times for reference included in the found entry is equal to one, whereas the circuitry is configured to decrement, by one, the remaining number of times for reference included in the found entry in a case that the remaining number of times for reference is greater than one, and wherein, upon the invalidation of the found entry, the circuitry is configured to set a value of the field to “0”.