Patent ID: 9584719
Date: 2017-02-28
CPC Classifications: G06T,H04N

Claim:
1. An image processing system implemented in a pipeline arrangement, the image processing system comprising: a first multi-line processing block comprising a plurality of inputs configured to receive, in parallel, pixel values relating to a respective plurality of pixel lines of an image, the first processing block comprising a plurality of processing units configured to operate in parallel with each other, wherein each of the processing units is configured to provide processed pixel values relating to a respective one of said pixel lines of the image by applying multi-line processing to the pixel values received at at least some of said inputs of the first processing block; the image processing system further comprising: a second multi-line processing block comprising a plurality of inputs configured to receive from the first processing block, in parallel, the processed pixel values provided by the processing units of the first processing block, the second processing block being configured to apply multi-line processing to the processed pixel values received from the first processing block, wherein no line store module is implemented between the first and second multi-line processing blocks in the pipeline arrangement of the image processing system.