Patent ID: 9672783
Date: 2017-06-06
CPC Classifications: G09G,G11C

Claim:
1. A gate signal line drive circuit including a plurality of basic circuits that output respective gate signals which become high voltage in a signal high period which is cyclically repeated, and become low voltage in a signal low period which is a period other than the signal high period to corresponding gate signal lines, each of the basic circuits comprising: a high voltage application switching element having an input terminal and a control terminal in which a first basic clock signal that is repeated with m clocks (m is an integer equal to or higher than 3) as one cycle, and becomes high voltage in a clock which is the signal high period, and becomes low voltage in the other clocks is input to the input terminal of the high voltage application switching element, and the high voltage is applied to the control terminal of the high voltage application switching element according to the signal high period, to output a voltage of the first basic clock signal to the corresponding gate signal line; a low voltage application switching element having a control terminal to which the high voltage is applied at timing to change from the signal high period to the signal low period, to output the low voltage to the corresponding gate signal line; and a first low voltage application on control element having an input terminal and a control terminal, wherein a second basic clock signal that is repeated with the m clocks as one cycle and becomes high voltage subsequent to the first basic clock signal is input into the input terminal of the first low voltage application on control element, and wherein the first low voltage application on control element outputs a voltage of the second basic clock signal to the control terminal of the low voltage application switching element at least at timing when the second basic clock signal changes from the low voltage to the high voltage.