Patent ID: 9588894
Date: 2017-03-07
CPC Classifications: G06F

Claim:
1. A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache, the method comprising: receiving a non-transactional store address and a first data; mapping the non-transactional store address to a first cache line template in a store buffer, wherein the non-transactional store address is mapped to a first cache line template in the store buffer by a free list; merging the first data into the first cache line template, according to a non-transactional store policy; receiving a thread-specific transactional store address and a second data; mapping the thread-specific transactional store address to a second cache line template in the store buffer; merging the second data into a second cache line template, according to a transactional store policy; and writing-back a copy of a cache line template that is in the store buffer to a cache; and invalidating a contents of a third cache line template, wherein the invalidation frees the third cache line template from a store address mapping.