Patent ID: 9734277
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. A method of designing a semiconductor device comprising: modifying, by a computer, a direction in which first and second wirings extend in a first wiring layer from among a plurality of wiring layers of the semiconductor device that is specified by layer information stored in a storage of the computer; to modify a connection relationship of third and fourth wirings with respect to the first and second wirings in a second wiring layer from among the plurality of wiring layers; storing, in accordance with the modified connection relationship, and via the computer, a management code in a register, the register being provided within a code managing circuit of the semiconductor device and being electrically connected to the first wiring; and generating layout data for the semiconductor device based on the management code, wherein a mask used to manufacture the semiconductor device is generated based on the layout data.