Patent ID: 9645626
Date: 2017-05-09
CPC Classifications: G06F,H02M,Y02B

Claim:
1. A circuit comprising: a voltage regulator configured to maintain an output voltage; a load in communication with the voltage regulator and configured to receive the output voltage, the load further configured to perform logic functions and to output data indicating computational activity at the load; a first feedback loop in communication with the output voltage and an input of the voltage regulator; and a second feedback loop in communication with the load and the voltage regulator and including a transient load current prediction circuit configured to calculate a predicted transient load current from the data indicating computational activity and to manipulate the output voltage in response to the predicted transient load current, wherein the data indicating computational activity includes event counters from the load, and further wherein the transient load current prediction circuit is configured to calculate the predicted transient load current by calculating a difference in aggregate event counters at a present clock cycle and at a previous clock cycle and applying coefficients to the difference in aggregate event counters.