Patent ID: 9552205
Date: 2017-01-24
CPC Classifications: G06F

Claim:
1. A processor comprising: a decode unit to decode a vector indexed load plus arithmetic/logical (A/L) operation plus store instruction that has a single opcode, the vector indexed load plus A/L operation plus store instruction to indicate a source packed memory indices operand that is to have a plurality of packed memory indices, and to indicate a source packed data operand that is to have a plurality of packed data elements; and an execution unit coupled with the decode unit, the execution unit, in response to the vector indexed load plus A/L operation plus store instruction, to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, to perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and to store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.