Patent ID: 9679651
Date: 2017-06-13
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a memory cell array including: a bit line connected to both one end of the first memory string and one end of the second memory string; a first word line connected to a gate of the first memory cell and a gate of the third memory cell; a second word line connected to a gate of the second memory cell; and a control circuit configured to determine a program condition for a write operation for the first memory cell that has been selected, and set a program condition for a write operation for the third memory cell based on the program condition for the write operation for the first memory cell, wherein data corresponding to the program condition for the write operation for the first memory cell is stored by the control circuit in one or more memory cells of a redundancy area of the memory cell array, the one or more memory cells being connected to the first word line.