Patent ID: 9722021
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A process of forming an integrated circuit, comprising the steps: forming an isolated well with a second conductivity type in a substrate with a first conductivity type; forming a transistor gate dielectric on the isolated well and on the substrate; depositing transistor gate material on the transistor gate dielectric; forming a gate photo resist pattern on the transistor gate material with an isolation transistor gate photo resist geometry for forming an isolation transistor gate adjacent to a well contact region within the isolated well; etching the transistor gate material and to form the isolation transistor gate; forming dielectric sidewall spacers on the isolation transistor gate; forming a device diffusion photo resist pattern on the integrated circuit wherein photoresist covers a portion of the isolation transistor gate and covers the well contact region adjacent to a first side of the isolation transistor gate; implanting dopant of the first conductivity type to form a device diffusion adjacent to a second side of the isolation transistor gate; forming a well contact diffusion photo resist pattern on the integrated circuit wherein photoresist covers a portion of the isolation transistor gate and covers the device diffusion; and implanting dopant of the second conductivity type into the well contact region to form a well contact diffusion.