Patent ID: 9542266
Date: 2017-01-10
CPC Classifications: G06F,H03M,H04L

Claim:
1. A semiconductor integrated circuit comprising: a first combinational circuit to output a state value depending on an input signal and output a parity value of the state value; a first flip-flop circuit to store the state value and the parity value output by the first combinational circuit and output a state value, a first parity value, and a first output value; a first parity check circuit to perform a parity check based on the state value and the parity value stored in the first flip-flop circuit and output a first parity error when detecting an error; a second flip-flop circuit, coupled to the first combinational circuit in parallel with the first flip-flop circuit, to store the state value and the parity value output by the first combinational circuit and output a second state value, a second parity value, and a second output value; a second parity check circuit to perform a parity check based on the state value and the parity value stored in the second flip-flop circuit and output a second parity error when detecting an error; and a selector to, when the first parity error is not output but the second parity error is output, output the first state value to the first combinational circuit, and when the first parity error is output but the second parity error is not output, output the second state value to the first combinational circuit, wherein the first combinational circuit outputs a current state value depending on the state value output by the selector and the input signal, and wherein the selector includes