Patent ID: 9633698
Date: 2017-04-25
CPC Classifications: G01R,G06F,G11C

Claim:
1. A method for optimizing power consumption in a platform having a multilane, multiphase wired bus, the method comprising: setting an accuracy parameter for the platform; introducing a first predetermined amount of jitter into the platform; measuring a bit error rate (BER) in the multilane, multiphase wired bus of the platform; determining whether the measured BER exceeds a minimum BER threshold value; if the measured BER does not exceed the minimum BER threshold value, then adjusting the accuracy parameter to decrease an accuracy of the platform; determining whether the measured BER in the platform exceeds a maximum BER threshold value; determining whether the first amount of jitter exceeds a jitter threshold value; if the measured BER does not exceed the maximum BER threshold value and the first predetermined amount of introduced jitter does not exceed the jitter threshold value, then increasing an amount of jitter introduced into the platform until the BER in the platform exceeds the maximum BER threshold value and the amount of jitter introduced into the platform exceeds the jitter threshold value; and if the measured BER does not exceed the maximum BER threshold value and the first predetermined amount of introduced jitter exceeds the jitter threshold value, then adjusting the accuracy parameter and increasing the amount of jitter introduced into the platform until the BER in the platform exceeds the maximum BER threshold value and the amount of jitter introduced into the platform exceeds the jitter threshold value.