Patent ID: 9665520
Date: 2017-05-30
CPC Classifications: G06F,Y02D

Claim:
1. A motherboard comprising: a universal serial bus (USB) communication module configured for coupling to a peripheral input device; a first communication interface obtaining a power signal from a display; a south bridge chip coupling to the first communication interface and configured for obtaining the power signal from the first communication interface, and the south bridge chip communicating with the peripheral input device through the USB communication module; and a switch module coupling to the first communication interface and configured for obtaining the power signal from the first communication interface; wherein when the power signal is power-on, the south bridge chip communicates with the peripheral input device, and the switch module controls a first power supply to supply power for the USB communication module; and wherein when power signal is power-off, the south bridge chip disconnects the communication from the peripheral input device, and the switch module switches off the power supply between the first power supply and the USB communication module; wherein the first communication interface comprises a first idle pin, the first communication interface is electrically coupled to a second communication interface of the display, the first idle pin of the first communication interface is electrically coupled to a second idle pin of the second communication interface; wherein the south bridge chip comprises a general purpose input output (GPIO) terminal and first to fourth USB enable pins; wherein the USB communication module comprises a first USB connector and a second USB connector, both the first USB connector and the second USB connector comprises a first data pin, a second data pin, a power supply pin, and a ground pin; and wherein the first USB enable pin of the south bridge chip is electrically coupled to the first data pin of the first USB connector, the second USB enable pin of the south bridge chip is electrically coupled to the second data pin of the first USB connector, the third USB enable pin of the south bridge chip is electrically coupled to the first data pin of the second USB connector, the fourth USB enable pin of the south bridge chip is electrically coupled to the second data pin of the second USB connector, the GPIO terminal of the south bridge chip is electrically coupled to the first idle pin of the first communication interface, the ground pin of the first USB connector and the second USB connector are grounded, and the power supply pin of the first USB connector and the second USB connector are coupled to the switch module.