Patent ID: 9680484
Date: 2017-06-13
CPC Classifications: G06F,H03L

Claim:
1. A timing circuit comprising: an oscillator control terminal; an oscillator feedback terminal; and at least one reference clock terminal; a first divider coupled to the oscillator feedback input terminal, and operable to generate a first input signal based on an oscillator feedback signal received through the oscillator feedback terminal; a second divider coupled to the reference clock terminal, and operable to generate a second input signal based on a reference clock signal received through the reference clock terminal; PLL circuitry operable to generate an oscillator control signal for output through the oscillator control terminal, wherein the frequency of an oscillator clock signal based on the oscillator control signal corresponds to the frequency of the second input signal, and wherein the PLL generates the oscillator control signal based on the first input signal and the second input signal; the PLL circuitry operable in a holdover mode to generate a holdover control signal for output through the oscillator control terminal, wherein the frequency of an oscillator holdover clock signal is based on the holdover control signal; holdover circuitry operable to control the PLL circuitry to enter and exit the holdover mode, including, for holdover exit conditions, issuing a reset signal to the first divider, wherein the reset signal synchronizes the phase of the first input signal and the second input signal; and a digital lock detector operable to detect holdover exit conditions based on the first input signal and the second input signal.