Patent ID: 9633748
Date: 2017-04-25
CPC Classifications: G11C

Claim:
1. An apparatus comprising: a test channel to couple to a memory tester; a memory channel controller to couple with a plurality of memory arrays via a plurality of memory channels; a test circuit coupled between the test channel and the memory channel controller, the test circuit to provide first and second test clock information to the memory channel controller; wherein the test circuit is to receive a first command in synchronization with the first test clock information, to delay propagation of the first command to a first one or more memory channels of the plurality of memory channels using the second test clock information, to receive a second command from the test circuit, after reception of the first command, in synchronization with the first test clock information, and to propagate the second command to a second one or more memory channels of the plurality of memory channels in synchronization with the first test clock information; and wherein the propagation of the first command to the first one or more of the memory channels and the propagation of the second command to the second one or more memory channels is to at least partially overlap in time.