Patent ID: 9666596
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a first stacked body including a plurality of conductive layers arranged along a first direction; a pillar extending through the first stacked body in the first direction; a memory film provided between the pillar and the first stacked body; a capacitive element including a first conductive member and a second conductive member, and the capacitive element being arranged in a line with the pillar in a direction crossing the first direction; a first wiring electrically connected to the first conductive member; and a second wiring electrically connected to the second conductive member, a first length of the first conductive member in the first direction being longer than a second length of the first conductive member in a second direction crossing the first direction, a third length of the first conductive member in a third direction being longer than the second length, and the first length being longer than a length between a top layer of the conductive layers of the first stacked body and a bottom layer of the conductive layers of the first stacked body in the first direction, the third direction crossing the first direction and the second direction, and a fourth length of the second conductive member in the first direction being longer than a fifth length of the second conductive member in the second direction, a sixth length of the second conductive member in the third direction being longer than the fifth length, and the fourth length being longer than a length of the first stacked body in the first direction.