Patent ID: 9558701
Date: 2017-01-31
CPC Classifications: G09G,G11C

Claim:
1. A shift register comprising: a first Thin Film Transistor (TFT) having a gate and a drain directly connected to a signal input terminal, a source directly connected to a pulling-up node; a second TFT having a gate directly connected to a reset signal terminal, a drain directly connected to the pulling-up node, and a source directly connected to a low level signal terminal; a third TFT having a gate directly connected to the pulling-up node, a drain directly connected to a clock signal terminal, and a source directly connected to a signal output terminal; wherein the pulling-up node is further directly connected to a capacitor, a fourth TFT having a gate directly connected to the reset signal terminal, a drain directly connected to the signal output terminal, and a source directly connected to the low level signal terminal; the capacitor being directly connected between the pulling-up node and the signal output terminal; and a pulling-down module, being connected among the pulling-up node, the pulling-down node, the signal output terminal and the low level signal terminal, for maintaining the pulling-up node and the signal output terminal at a low level during the non-operating time of the shift register and when the pulling-down node is at a high level; wherein the pulling-down module includes: a fifth TFT having a gate and a drain directly connected to the pulling-down signal terminal, and a source directly connected to the pulling-down node; a sixth TFT having a gate directly connected to the pulling-up node, a drain directly connected to the pulling-down node, and a source directly connected to the low level signal terminal; and a seventh TFT having a gate directly connected to the pulling-down node, a drain directly connected to the pulling-up node, and a source directly connected to the low level signal terminal, wherein the shift register further comprises: a first electronic switching module, being connected between the pulling-up node and the low level signal terminal, and connected to a pulling-down signal terminal via a pulling-down node, for maintaining the pulling-up node at a low level during a non-operating time of the shift register and when the pulling-down node is at a low level; and a second electronic switching module, being connected between the signal output terminal and the low level signal terminal, and connected to the pulling-down signal terminal via the pulling-down node, for maintaining the signal output terminal at a low level during the non-operating time of the shift register and when the pulling-down node is at a low level, wherein the first Thin Film Transistor, the second Thin Film Transistor and the fourth Thin Film Transistor are turned off during a non-operating time of the shift register.