Patent ID: 9710586
Date: 2017-07-18
CPC Classifications: G06F,H03K

Claim:
1. An automated method of extracting a state machine representation of a digital logic superconductive circuit from an alphanumeric representation of the circuit, the alphanumeric representation specifying circuit components, including at least inductive elements, their interconnectivity and input and output nodes, the method comprising: receiving, from an input, the alphanumeric representation of the circuit; simulating the circuit with an input signal unit, as directed by a processor, in a suitable software environment utilising the alphanumeric representation received from the input; receiving a circuit output from an output signal unit in communication with the processor and identifying, with the processor, inductive loops in the circuit; identifying one or more of the inductive loops in the circuit capable of storing one or more magnetic fluxons, with the processor, and discarding all others; extracting the state machine representation with the processor, using only the inductive loops in the circuit capable of storing magnetic fluxons; and constructing a Hardware Description Language (HDL) model for the digital logic superconductive circuit with the processor.