Patent ID: 9690543
Date: 2017-06-27
CPC Classifications: G06F,H03M

Claim:
1. Apparatus for processing data comprising: alignment circuitry to align, with respect to bit significance, any of one or more input operands to a programmable significance parameter specified for an output storage element to provide one or more aligned input operands, wherein the programmable significance parameter is indicative of which powers of 2 are to be represented by respective bits of a result value to be stored in the output storage element, and at least one of said one or more input operands is a floating point input operand having an exponent value and a significand value and said alignment circuitry is responsive to said programmable significance parameter and said exponent value to align, with respect to bit significance, said significand with said result value; and arithmetic circuitry coupled to said alignment circuitry to receive said one or more aligned input operands, to perform an arithmetic operation upon said one or more aligned input operands to generate said result value, and to store said result value to said output storage element, wherein said arithmetic circuitry comprises an integer adder or an integer multiplier; wherein said programmable significance parameter is independent of said result value.