Patent ID: 9667083
Date: 2017-05-30
CPC Classifications: G01R,H01M,H02J,Y02E

Claim:
1. A method comprising: a circuit receiving source current via a node and dividing the source current into Ic and Icr; the circuit transmitting Ic to a battery; generating a first voltage that is related to Icr; converting the first voltage into a first digital signal; a processing unit receiving and processing the first digital signal in accordance with instructions stored in a memory; interrupting the transmission of Ic to the battery in response to the processing unit processing the first digital signal; the circuit dividing discharge current provided by the battery into Idc and Idcr; the circuit transmitting Idc to the node; generating a second voltage that is related to Idcr; converting the second voltage into a second digital signal; the processing unit receiving and processing the second digital signal in accordance with instructions stored in the memory; interrupting the transmission of Idc by the battery in response to the processing unit processing the second digital signal; wherein the circuit coupled in series between a battery and a node, and the circuit comprises; first, second, third, and fourth field effect transistors (FETs), each comprising a gate, source, and drain; wherein the source of the first FET is coupled to the node; wherein the source of the third FET is coupled to the battery, and; wherein the drains of the first, second, third, and fourth FETs are directly coupled to each other.