Patent ID: 9564371
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A manufacturing method for forming a semiconductor device, at least comprising the following steps: providing a substrate, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure; forming an interlayer dielectric on the gate structures; forming a hard mask layer and a first photoresist layer on the interlayer dielectric; performing a first etching process on the first photoresist layer, to form at least one first trench in the first photoresist layer and in the hard mask layer, so as to define a region, wherein the region is overlapping the fin structures when the semiconductor device is viewed from the top view; forming a plurality of patterned photoresist layers on the remaining hard mask layer, wherein each patterned photoresist layer is disposed right above each gate structure, and a width of each patterned photoresist is larger than a width of each gate structure, in addition, an area of the each patterned photoresist layer of the plurality of the patterned photoresist layers totally overlaps an area of each corresponding gate structure from the plurality of the gate structures when viewed in top view; and using the remaining hard mask layer and the plurality of patterned photoresist layer as a second hard mask to perform a second etching process to form a plurality of second trenches, wherein the plurality of second trenches are only disposed within the region, and each second trench at least partially overlaps the width of the first trench.