Patent ID: 9691876
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method comprising: forming a gate dielectric layer over a first region and a second region of a semiconductor substrate; forming a first capping layer over the gate dielectric layer in the first region of the semiconductor substrate; forming a second capping layer over the first capping layer in the first region of the semiconductor substrate and over the gate dielectric layer in the second region of the semiconductor substrate; forming a first gate electrode layer over the second capping layer in the first region of the semiconductor substrate; applying a treatment process to the second capping layer over the gate dielectric layer in the second region of the semiconductor substrate to form a third capping layer; removing the first gate electrode layer over the second capping layer in the first region of the semiconductor substrate; and after removing the first gate electrode layer over the second capping layer in the first region of the semiconductor substrate, forming a second gate electrode layer over the first region of the semiconductor substrate and over the second region of the semiconductor substrate, wherein the first capping layer has a top surface facing away from the semiconductor substrate and the third capping layer has a top surface facing away from the semiconductor substrate such that the top surface of the first capping layer directly interfaces with the top surface of the third capping layer.