Patent ID: 9570608
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a stressed substrate stressed by a first stress; a first stressed channel formed in the substrate and having the first stress induced from the stressed substrate; a first strained gate electrode strained by a first strain generating element; a second stressed channel formed in the substrate and having the first stress induced from the stressed substrate; a second strained gate electrode strained by a second strain generating element; and wherein a first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel, wherein a second strained gate electrode is formed over the second stressed channel, the second strained gate electrode including a second lattice-mismatched layer to induce a third stress to the second stressed channel, wherein the first lattice-mismatched layer comprises: wherein the second lattice-mismatched layer comprises: wherein the boron-doped crystalline silicon layer is undoped with the germanium, and wherein the germanium-doped crystalline silicon layer is undoped with the boron.