Patent ID: 9634113
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method of making a semiconductor device, the method comprising: forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack comprising a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the layer of silicon material; and performing a silicidation process to form a source/drain contact comprising a silicide; wherein filling the source/drain contact pattern with the silicide further comprises depositing another silicon layer onto the metallic layer and depositing another a metallic layer onto the another silicon layer.