Patent ID: 9558843
Date: 2017-01-31
CPC Classifications: G09G,G11C

Claim:
1. A shift register unit, comprising: a pull-up module configured to output a pulled up high level signal at a present-stage signal output according to signals from a pull-up control node and a first clock input; a control module connected to a first voltage terminal and a second voltage terminal and configured to control the level at the pull-up control node according to signals from a first signal input and a second clock input; and a reset module configured to reset the high level signal outputted from the present-stage signal output to a low level signal according to a signal from a second signal input, wherein the pull-up module comprises: wherein the control module comprises a first control sub-module and a second control sub-module, and wherein when the signal from the first signal input and the signal from the second clock input are both at high level, the pull-up control node is pulled up to high level; when the pull-up control node is at high level and the signal from the first clock input is at low level, the capacitor is pre-charged, so that when the signal from the first signal input and the signal from the second clock input are both in low level, the pull-up control node is maintained at high level by the second control sub-module according to the feedback signal, which is at high level, from the pull-up control node; and when the signal from the first signal input is at low level while the signal of the second clock input is a high level signal, the pull-up control node is switched to low level, and the pull-up control node is held at low level by the second control sub-module according to the feedback signal , which is at low level, from the pull-up control node.