Patent ID: 9691781
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate; a stack in a memory cell area of the substrate, the stack comprising a first tier and a second tier on the first tier, the first tier comprising a first set of alternating control gate layers and dielectric layers and the second tier comprising a second set of alternating control gate layers and dielectric layers, the stack comprising memory holes, each memory hole comprises a portion in the first tier and a portion in the second tier, and memory films extend along a wall of each memory hole; a transistor formed on the substrate in a peripheral area, peripheral to the memory cell area, the transistor is in a circuit; a first column in the peripheral area, the first column comprises polysilicon, a resistor in the circuit comprises the polysilicon in the first column, and the first column extends from a terminal of the transistor to a height of a top of the first tier, wherein a doping concentration of the first column varies radially relative to a central longitudinal axis of the resistor; and a second column which extends from the height of the top of the first tier to a height of a top of the second tier, the second column is electrically connected to the first column.