Patent ID: 9602107
Date: 2017-03-21
CPC Classifications: H03K

Claim:
1. An integrated circuit comprising: (a) a first state capture device having a first data input, a clock input, and a first data output, and being free of any reset input; (b) a first cell reset node having a first node output coupled to a first reset logic state; (c) a first selection device having a first input coupled to the first data output, a second input coupled to the first node output, a selection output, and a first control input, the selection device selectively coupling a signal on the first input or second input to the selection output in response to a control signal on the control input; (d) a single bit control register having a reset input, a clock input, and a first control bit output coupled to the first control input of the first selection device; (e) a second cell reset node having a second node output coupled to a second reset logic state different from the first reset logic state, and (f) a second selection device having a second node input coupled to the second node output and a second control input coupled to the single bit control register.