Patent ID: 9747200
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. A memory system, comprising: a temporary power supply that provides power to the memory system for a backup time period in the event of a power outage; a printed circuit board having a physical interface configured for connection to a host system; a volatile memory device connected to the printed circuit board for receiving data from the host system via the physical interface and for providing data to the host system via the physical interface, during a first operating mode; and, at least one non-volatile memory device connected to the printed circuit board for receiving and programming data of the volatile memory device to memory cells of the at least one non-volatile memory device during a second operating mode in which the memory system is powered by the temporary power supply, the at least one non-volatile memory device having a plurality of dummy data program/erase cycles executed on the memory cells to program and erase test data before first time use of the at least one non-volatile memory device and before the physical interface of the printed circuit board is connected to the host system such that a worst case programming time for programming the data to the memory cells of the at least one non-volatile memory device in the second operating mode is less than the backup time period, and wherein a worst case programming time of the memory cells of the at least one non-volatile memory device without executing the plurality of dummy data program/erase cycles before first use is greater than the backup time period.