Patent ID: 9646537
Date: 2017-05-09
CPC Classifications: G09G

Claim:
1. An organic light emitting diode display panel structure comprising: a plurality of pixel units arranged in rows and columns; a scan driver configured to generate scan signals for the plurality of pixel units; a plurality of scan lines extending from the scan driver, each of the plurality of scan lines configured to transmit the scan signals to two rows of pixel units arranged adjacent to the scan line; a data driver configured to generate, upon receiving the scan signals, data signals for the plurality of pixel units; a plurality of data lines extending from the data driver, each of the plurality of data lines configured to transmit the data signals to a corresponding column of the plurality of pixel units arranged along the data line; a plurality of reading lines extending from the data driver, each of the plurality of reading lines configured to receive performance information from a corresponding column of the plurality of pixel units arranged along the reading line and transmit the performance information to the data driver to analyze; a voltage supply driver configured to generate a driving voltage for the plurality of pixel units; a plurality of voltage lines extending from the voltage supply driver, each of the plurality of voltage lines configured to transmit the driving voltage to a corresponding row of the plurality of pixel units arranged along the voltage line; and a time controller configured to transmit a coordinating signal to the scan driver, the data driver, and the voltage supply driver to control the scan driver, the data driver, and the voltage supply driver to transmit the scan signals, the data signals, and the driving voltages, respectively; wherein the scan signals transmitted along one scan line of the plurality of scan lines are transmitted to the adjacent rows of the plurality of pixel units arranged along the scan line; wherein each pixel unit operates in a plurality of time events repeating in sequence, the plurality of time events set by the coordinating signal of the time controller; wherein a portion of the plurality of time events of the two adjacent rows of the plurality of pixel units overlaps; wherein the data driver calculates an enhanced data signal for each of the plurality of pixel units according to the corresponding performance information, and transmits the enhanced data signals along the corresponding data lines to the plurality of pixel units; and wherein each of the plurality of pixel units emits light corresponding to the data signal and the enhanced data signal; wherein each pixel unit comprises: a switch transistor configured to receive the corresponding scan signal, the corresponding data signal, and the corresponding enhanced data signal; a storage capacitor configured to receive the data signal and the enhanced data signal from the switch transistor; a driving transistor configured to output a driving current corresponding to the data signal and to the enhanced data signal; an organic light emitting diode configured to emit light corresponding to the enhanced data signal upon receiving the corresponding driving current; and a data circuit configured to transmit the performance information to the data driver; wherein the data circuit comprises a data transistor electrically coupled to the corresponding reading line; the performance information is the driving current, corresponding to the data signal, output by the driving transistor; one data line and one reading line define one column of pixel units; any three adjacent scan lines define one pair of rows of adjacent pixel units; any two adjacent pixel units of one column of pixel units constitute a pixel group; each scan line is configured to transmit the scan signal to the switch transistor of a first pixel unit of the pixel group, and transmit the scan signal to the data transistor of a second pixel unit of the pixel group; the three adjacent scan lines comprise a first scan line configured to transmit the scan signal to the switch transistor of the first pixel unit of the pixel group, a second scan line configured to transmit the scan signal to the switch transistor of the second pixel unit and to the data transistor of the first pixel unit of the pixel group, and a third scan line configured to transmit the scan signal to the data transistor of the second pixel unit of the pixel group; for each pixel unit, the data transistor receives the scan signal before the switch transistor; and of the three adjacent scan lines, the third scan line transmits the scan signal before the second scan line, and the second scan line transmits the scan signal before the first scan line.