Patent ID: 9568786
Date: 2017-02-14
CPC Classifications: G02F,G09G

Claim:
1. An array substrate, comprising: a plurality of scanning lines parallel to one another in a first direction; a plurality of data lines parallel to one another in a second direction, wherein the first direction intersects with the second direction; a plurality of pixel units disposed at intersections of the scanning lines and the data lines; a plurality of common lines, each arranged along and electrically connected to a row of pixel units; a common voltage supply line comprising a common voltage high level supply line and a common voltage low level supply line; and a plurality of dual-channel selection switches, each of which comprises one control terminal, two input terminals and one output terminal, wherein the output terminal of each of the dual-channel selection switches is connected to one of the common lines, the two input terminals of the dual-channel selection switch are connected to the common voltage high level supply line and the common voltage low level supply line respectively, a high level or a low level is selectively applied to the common lines sequentially for frames of display according to a control signal supplied from the control terminal of the dual-channel selection switch; wherein voltage changes are generated sequentially with delays from one common line associated with one frame of display to a next common line associated with the next frame, wherein each of common lines is completely inverse as the starting time of a frame to an adjacent frame.