Patent ID: 9619600
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. A computer-readable storage having instructions thereon for being executed by a processor to perform a method, the method comprising: generating a verification model that represents an electronic design including a proprietary component and one or more design components coupled to the proprietary component, wherein generating the verification model includes inserting an instrumentation component between the proprietary component and the design components so that the proprietary component is coupled to both the design components and the instrumentation component and so that the instrumentation component captures signals passing between the proprietary component and the design components, and wherein the electronic design is a design of an electronic circuit; implementing the verification model using a verification tool; determining a state of the verification model at a first point in time of a verification process applied to the implemented verification model by the verification tool; determining one or more signal values on one or more signal lines that interconnect the proprietary component with the design components from the first point during the verification process until a second point in time during the verification process; and generating a reference model for the electronic design from the verification model.