Patent ID: 9711206
Date: 2017-07-18
CPC Classifications: G11C

Claim:
1. An apparatus, comprising: an array of memory cells; and sensing circuitry coupled to the array of memory cells via a pair of complementary sense lines, wherein the sensing circuitry comprises: wherein the compute component further comprises a third pass transistor and a fourth pass transistor; wherein a first source/drain of the third pass transistor is directly coupled to the first source/drain of the first pass transistor, a first source/drain of the fourth pass transistor is directly coupled to the first source drain of the second pass transistor, a second source/drain of the third pass transistor is directly coupled to the second source/drain of the second pass transistor, and a second source/drain of the fourth pass transistor is directly coupled to the second source/drain of the first pass transistor; and wherein the first pass transistor and the second pass transistor are the same type, and enabled via different control signals.