Patent ID: 9570181
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A memory system comprising: a plurality of first wiring lines; a plurality of second wiring lines; a first storage including a plurality of first memory cells arranged at intersections of the plurality of first wiring lines and the plurality of second wiring lines; a plurality of third wiring lines, each connected to any one of the plurality of first wiring lines; a plurality of fourth wiring lines, each pre-associated with a logical address specified by a host apparatus; and a second storage including a plurality of second memory cells arranged at intersections of the plurality of third wiring lines and the plurality of fourth wiring lines, a resistance state of each of the second memory cells being set to at least a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and a first wiring line, wherein a NAND flash memory is used as the first storage.