Patent ID: 9570448
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, the method comprising: sequentially forming an upper mold layer, a bowing prevention layer, and an upper support layer on a substrate; forming a storage node hole using a dry etching process, the storage node hole passing through the upper support layer, the bowing prevention layer and the upper mold layer; forming a lower electrode in the storage node hole; patterning the upper support layer and the bowing prevention layer to expose a portion of the upper mold layer; removing the upper mold layer and at least a portion of the bowing prevention layer using a first wet etching process; and sequentially forming a dielectric layer and an upper electrode that cover the lower electrode, wherein a first etch rate of the bowing prevention layer is substantially equal to a first etch rate of the upper support layer during the dry etching process, wherein a second etch rate of the bowing prevention layer is higher than a second etch rate of the upper support layer during the first wet etching process, and wherein the upper support layer and bowing prevention layer each have a substantially uniform thickness, and a sum of a thickness of the upper support layer and a thickness of the bowing prevention layer has a value within a range from 15% to 25% of a depth of the storage node hole.