Patent ID: 9711528
Date: 2017-07-18
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device, comprising a first region, a second region, and a third region, the first region including: a part of a stacked body that includes a plurality of conductive layers stacked above a substrate; and a memory columnar body provided along a first direction intersecting the substrate, the memory columnar body having its side surface covered by the stacked body and configuring a memory string, the second region including: a contact; a contact portion connected to the contact, of the conductive layer; and a plurality of first columnar bodies provided along the first direction, the plurality of first columnar bodies each having their side surface covered by the plurality of conductive layers, the third region including: another part of the stacked body; and a second columnar body provided along the first direction, the second columnar body having its side surface covered by the stacked body, and in a plane parallel to the substrate, a total area of the second columnar body in a small region that has the same area as one or more contact portions, in the third region being larger than a total area of the first columnar body in the one or more contact portions.