Patent ID: 9735783
Date: 2017-08-15
CPC Classifications: H03K

Claim:
1. A field programmable gate array (FPGA) comprising: a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links; an embedded memory and a pair of single bit static random access memory (SRAM) cells coupled to each reconfigurable switch, a first SRAM cell being configured to receive and store a first run time configuration from the embedded memory for use in a first clock cycle and a second SRAM cell being configured to receive and store a second run time configuration from the embedded memory during the first clock cycle for use during a second adjacent clock cycle; the reconfigurable switches being reconfigurable during ft the first clock cycle based on the first run time configuration stored in the first SRAM cell, the reconfigurable switches being reconfigurable during the second adjacent clock cycle based on the second run time configuration stored in the second SRAM cell.