Patent ID: 9646894
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor die package, comprising: a first packaged die; a second packaged die; an interconnect substrate having a first side, a second side opposite the first side, and a sidewall extending between the first side and the second side, wherein the interconnect substrate comprises a redistribution structure on the first side, wherein the second side of the interconnect substrate is free from connectors, and wherein the first packaged die and the second packaged die are bonded to the first side of the redistribution structure; and a package substrate with an interconnect structure, the package substrate having a recess, wherein the interconnect substrate is bonded to a bottom surface of the recess, wherein the second side of the interconnect substrate faces the bottom surface of the recess, wherein the sidewall of the interconnect substrate extends into the recess, wherein the sidewall of the interconnect substrate faces a sidewall of the recess, wherein the package substrate is electrically connected to the interconnect substrate using a conductive connector, wherein the conductive connector physically contacts the sidewall of the interconnect substrate and the sidewall of the recess, wherein the first packaged die and the second packaged die are electrically connected to the interconnect substrate and wherein the first packaged die is directly bonded to the package substrate.