Patent ID: 9576612
Date: 2017-02-21
CPC Classifications: G11C,H01L

Claim:
1. A nonvolatile memory device comprising: first word lines and second word lines; a first memory block including first sets of memory cells and electrically connected to the first word lines, the memory cells of each first set being disposed at the same level in the device as one another and the first sets of memory cells being stacked vertically one atop another such that the first memory block contains a plurality of memory cells at each of a plurality of different levels arrayed in a vertical direction in the device; a second memory block including second sets of memory cells and electrically connected to the second word lines, the second memory block adjacent the first memory block in a first horizontal direction, the memory cells of each second set being disposed at the same level in the device as one another and the second sets of memory cells being stacked vertically one atop another such that the second memory block also contains a plurality of memory cells at each of a plurality of levels in the device; first pass transistors enabling a selection of the first word lines; and second pass transistors enabling a selection of the second word lines, wherein the first pass transistors and the second pass transistors are disposed beside the memory blocks and are arrayed two-dimensionally, in parallel rows, in a horizontal plane perpendicular to the vertical direction, each of the rows containing a plurality of respective ones of the pass transistors, the rows spaced apart from each other in the first horizontal direction, and each of the rows of the pass transistors extending in a second horizontal direction different from the first horizontal direction, the memory cells of the first and second memory blocks are arrayed in parallel rows spaced from each other in the first horizontal direction, and each of the rows of memory cells containing a plurality of respective ones of the memory cells and extending in the second horizontal direction, and each of the first pass transistors is located between each of the second pass transistors and the first memory block.