Patent ID: 9595668
Date: 2017-03-14
CPC Classifications: G11C,H01L

Claim:
1. A memory cell comprising: a first electrode and a second electrode formed of one of a metallic material or a semiconducting material; a resistance-switching element formed between the first electrode and the second electrode; a tunnel rectifier formed between and in physical contact with the resistance-switching element and the first electrode, wherein the tunnel rectifier comprises a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric constant (k wherein one of the dielectric layers has a higher dielectric constant, a lower conduction band offset and a higher thickness compared to any other dielectric layer of the multi-layer tunnel stack, wherein the dielectric constant of one of the dielectric layers does not exceed 12 and a dielectric constant of another one of the dielectric layers is between about 20 and about 50, wherein the multi-layer tunnel stack is a stack of three dielectric layers, wherein a dielectric layer is sandwiched between a first neighboring dielectric layer and a second neighboring dielectric layer and has: a dielectric constant (k a conduction band offset (Φ a thickness (t