Patent ID: 9741765
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of fabricating a memory device, comprising: providing a substrate comprising one or more complementary metal-oxide semiconductor devices; fabricating a first insulator layer over the substrate; fabricating a first metal layer over the first insulator layer; fabricating an interlayer dielectric material layer over the first metal layer; fabricating a via through at least a subset of the interlayer dielectric material layer; forming a plurality of material layers over at least a subset of an exposed surface of the interlayer dielectric material layer formed in response to the fabricating the via and within a thermal budget of the one or more complementary metal-oxide semiconductor devices, the plurality of material layers forming a subset of a resistive memory device structure; and fabricating a second metal layer over the resistive memory device structure and forming at least a third metal layer over the second metal layer, wherein a first distance between the first metal layer and the second metal layer is substantially equal to a second distance between the second metal layer and the third metal layer.