Patent ID: 9685316
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A semiconductor process, comprising: providing a wafer on a pedestal; lifting the pedestal to approach a heating source and performing an etching process on the wafer after a contact hole of the wafer being formed; and performing an annealing process on the wafer by the heating source to remove byproducts generated after the etching process in order to complete a pre-cleaning process of a salicide process comprising the etching process and the annealing process for forming a metal silicide in the contact hole of the wafer capable of maintaining vertical sidewalls of the contact hole of the wafer by increasing vertical etching rate while reducing lateral etching rate during the etching process through controlling of temperature difference between the heating source and the pedestal by lifting the pedestal to approach the heating source during the etching process, wherein the annealing process is performed without moving the wafer.