Patent ID: 9590053
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. An integrated chip, comprising: a gate electrode disposed over a substrate between a source region and a drain region; one or more dielectric layers laterally extending from over the gate electrode to over a drift region laterally arranged between the gate electrode and the drain region; a field plate located within a first inter-level dielectric (ILD) layer overlying the substrate, wherein the field plate laterally extends from over the gate electrode to over the drift region and vertically extends from the one or more dielectric layers to a top surface of the first ILD layer; a plurality of metal contacts surrounded by the first ILD layer, wherein the plurality of metal contacts comprise a same material as the field plate; wherein the field plate has a first height over the gate electrode and a second height over the drift region; and wherein the first height is smaller than the second height.