Patent ID: 9646830
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor structure fabrication method, comprising: providing a semiconductor substrate having one or more gate structures, sidewalls of the gate structures being covered by a spacer layer; performing an epitaxy process using a deposition gas to form a semiconductor epitaxial material layer covering the gate structures, the spacer layer, and the semiconductor substrate; performing an etching process using an etching gas to remove the semiconductor epitaxial material layer located on the spacer layer and on the gate structures to form a first semiconductor epitaxial layer on the semiconductor substrate at two sides of the gate structures; performing an selective epitaxy process using the deposition gas and the etching gas to form a second semiconductor epitaxial layer on the semiconductor substrate at the two sides of the gate structures, wherein the second semiconductor epitaxial layer repairs or compensates the first semiconductor epitaxial layer along a horizontal direction; and repeating the epitaxy process, the etching process, and the selective epitaxy process successively one or more times to form elevated source and drain regions on the semiconductor substrate at the two sides of the gate structures.