Patent ID: 9666305
Date: 2017-05-30
CPC Classifications: G11C

Claim:
1. A circuit for testing a memory, the circuit comprising: a complementary charge trap memory cell including a first transistor and a second transistor, a logical value of the complementary charge trap memory cell corresponding to respective states of the first transistor and the second transistor; a first bitline coupled to the first transistor, the first transistor configured to apply a first voltage to the first bitline; a second bitline coupled to the second transistor, the second transistor configured to apply a second voltage to the second bitline; and a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first transistor applying the first voltage to the first bitline and the second transistor applying the second voltage to the second bitline.