Patent ID: 9646688
Date: 2017-05-09
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a three dimensional (3D) memory array comprising memory elements, each memory element having a first side terminal and a second side terminal; a plurality of connected together word lines extending horizontally in one of a plurality of horizontal planes of the 3D memory array and connecting to a common word line driver, each of the word lines connected to a respective first side terminal of corresponding ones of the memory elements, the connected together word lines of the one of said horizontal planes include at least three such connected together word lines; a plurality of vertically oriented bit lines configured to each extend vertically through the 3D memory array and to be interposed between a pair of word lines, each bit line coupled to the second side terminal of a corresponding memory element; bit line switching circuits each connected to a vertically oriented bit line and configured to float the respective bit line while the common word line driver applies a common voltage to the plurality of connected together word lines such that each floated bit line drifts toward the common voltage, the bit line switching circuits each being further configured to drive a selectable one or more of the first plurality of vertically oriented bit lines to an active state; a second plurality of connected together word lines extending horizontally in said one of the planes of the 3D memory array and connected to a second common word line driver that is located in the substrate under the 3D memory array, the second plurality of connected together word lines connecting to respective ones of the first side terminals of corresponding ones of the memory elements; and a second plurality of vertically oriented bit lines extending vertically through the 3D memory array so as to be interposed between pairs among the second plurality of connected together word lines, the second plurality of bit lines connecting to respective ones of the second side terminals of the corresponding ones of the memory elements to whose first side terminals said second plurality of connected together word lines connect.