Patent ID: 9704998
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method of manufacturing a thin film transistor, comprising steps of: forming an active material layer on a substrate; forming an etch barrier material layer on the active material layer, wherein the etch barrier material layer is made of a conductive material capable of blocking a source and drain etching liquid; forming an active layer pattern and an initial etch barrier layer pattern by performing a single patterning process on the active material layer and the etch barrier material layer, wherein the initial etch barrier layer pattern comprises a first region, a second region and a third region, the first region and the third region being regions for forming a source and a drain, respectively, the second region being a region of the initial etch barrier layer pattern excluding the first and third regions; forming the source and the drain on the first region and the third region, respectively, by patterning; and converting the conductive material in the second region of the initial etch barrier layer pattern into an insulation material by an annealing process, so as to form a patterned etch barrier layer; wherein the conductive materials in the first region and the third region remain unchanged and remain conductive during the annealing process.