Patent ID: 9698780
Date: 2017-07-04
CPC Classifications: G06F,H03K

Claim:
1. A method of integrated circuit (IC) design, the method comprising: designing the IC to include a first digital logic circuit having a plurality of inputs and including a plurality of digital logic gates; determining leakage current data of the first digital logic circuit, wherein the leakage current data indicates a leakage current of the first digital logic circuit for each state of the plurality of inputs, wherein the leakage current data is determined at least in part by simulating the first digital logic circuit; selecting a low power state of the first digital logic circuit based at least in part on the leakage current data, wherein the low power state is associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the first digital logic circuit; and designing the IC to include a first polarization circuit to control the plurality of inputs of the first digital logic circuit, wherein the first polarization circuit is operable to control the first digital logic circuit to the low power state when the IC is in a standby mode.