Patent ID: 9589991
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method for manufacturing a thin-film transistor (TFT), the TFT comprising an active layer, a gate insulating layer, a gate electrode, an interlayer dielectric layer, a source electrode and a drain electrode disposed on a base substrate in sequence, the gate insulating layer at least comprising a silicon oxide layer and a silicon nitride layer in a two-layer structure, the interlayer dielectric layer at least comprising silicon oxide layers and silicon nitride layers in a four-layer structure, all the silicon oxide layers and all the silicon nitride layers of the gate insulating layer and the interlayer dielectric layer being alternately arranged, the manufacturing method comprising: alternately depositing the silicon oxide layers and the silicon nitride layers on the base substrate in a process of respectively forming the gate insulating layer and the interlayer dielectric layer, and adjusting technological parameters so that compactness of at least odd-numbered layers or even-numbered layers in all the layers of the gate insulating layer and the interlayer dielectric layer is gradually increased as counted from the silicon oxide layer or the silicon nitride layer, farthest from the base substrate, in the interlayer dielectric layer.