Patent ID: 9702927
Date: 2017-07-11
CPC Classifications: G01R

Claim:
1. A test pattern generation device for generating a test pattern to be inputted into a circuit under test of scan test, comprising: a logic value generation unit for generating a new logic value by referring given logic values of a first bit, a second bit and a third bit and by keeping or reversing a logic value of the second bit; and a storing unit for storing a logic value generated by the logic value generation unit, wherein a logic value of the first bit is the same with a logic value of an initial test pattern which is a given test pattern or with a logic value of a new test pattern generated by the test pattern generation device based on the initial test pattern, wherein a logic value of the second bit is the same with a logic value of the initial test pattern, wherein a logic value of the third bit is the same with a logic value of the initial test pattern or with a logic value of the new test pattern, wherein a logic value of the first bit is, in advance, generated by the logic value generation unit and stored in the storing unit, and wherein the logic value generation unit generates a logic value of a bit included in a newly generated test pattern by keeping or reversing a logic value of the second bit, based on logic values of the first bit stored in the storing unit, the second bit and the third bit.