Patent ID: 9590072
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor device, comprising: forming a fin shaped structure on a substrate; forming a plurality of gate structures across the fin shaped structure; forming a dielectric layer on the substrate, covering the gate structures; removing gate electrodes of the gate structures, to form a first gate trench, a second gate trench, a third gate trench and a fourth gate trench; performing a first threshold voltage implantation process in the first gate trench, to implant a first dopant in a first conductive type; performing a compensated threshold voltage implantation process in the first gate trench, to implant a second dopant in a second conductive type, wherein the second conductive type is opposite to the first conductive type; forming a first work function layer in the fourth gate trench; forming a second work function layer in the first gate trench, the second gate trench and the third gate trench, and on the first work function layer in the fourth gate trench, wherein the first work function layer and the second work function layer have a same conductive type; forming a fifth gate trench while removing the gate electrodes of the gate structures; forming the first work function layer in the fifth gate trench; and performing a second threshold voltage implantation process in the fifth gate trench, to implant a third dopant in the first conductive type.