Patent ID: 9711660
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A vertical JFET, comprising: a semiconductor body having a first surface and a second surface that runs substantially parallel to the first surface; a source metallization arranged on the first surface; a drain metallization arranged on the second surface; and a gate metallization arranged on the first surface, wherein, in a sectional plane substantially perpendicular to the first surface, the semiconductor body comprises: an n-doped first semiconductor region in ohmic contact with the drain metallization and the source metallization; a plurality of p-doped second semiconductor regions in ohmic contact with the gate metallization, substantially extending to the first surface, spaced apart from one another and forming respective first pn-junctions with the first semiconductor region; and a plurality of p-doped body regions in ohmic contact with the source metallization, spaced apart from one another, from the p-doped second semiconductor regions, from the first surface and from the second surface, and forming respective second pn-junctions with the first semiconductor region, wherein the semiconductor body further comprises at least one conductive plug extending from the source metallization to one of the body regions.