Patent ID: 9671430
Date: 2017-06-06
CPC Classifications: G01R

Claim:
1. A tester for testing electrical characteristics of semiconductor devices, comprising; a main body that generates test signals that test the electrical characteristics of a semiconductor device and analyze device signals generated by the semiconductor device in response to the test signals; a head connected to the main body and that processes the test signals and the device signals; a base connected to the head and to which a probe card is secured, wherein the probe card selectively makes contact with the semiconductor device; and a level controller inside of the base and that independently restricts a peripheral deformation of the probe card and a central deformation of the probe card, to control a level of the probe card, wherein the level controller includes: an upper plate connected to the inside of the base and spaced above the probe card; a first lower under the upper plate that is in contact with a central portion of the probe card; a plurality of second lower plates under the upper plate that are in contact with a peripheral portion of the probe card, the plurality of the second lower plates being independently positioned and separated from the first lower plate; a first elastic member interposed between the upper plate and the first lower plate, the first elastic member applying a first restrictive force to the central portion of the probe card in proportion to the central deformation, to restrict the central deformation of the probe card; and a plurality of second elastic members interposed between the upper plate and the plurality of the second lower plates, the second elastic members applying a second restrictive force to the peripheral portion of the probe card in proportion to the peripheral deformation, to restrict the peripheral deformation of the probe card, wherein the first lower plate includes a single disk under a central portion of the upper plate and the plurality of second lower plates includes a plurality of split pieces under a peripheral portion of the upper plate that are spaced apart from and enclose the first lower plate.