Patent ID: 9570319
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: providing a workpiece having a recess and a dielectric layer having a first portion lining the recess and a second portion lining a top surface of the workpiece; forming a conductive structure within the recess, wherein: the conductive structure partially fills the recess; the conductive structure comprises topmost lateral extents disposed within the recess; and formation of the conductive structure leaves the second portion of the dielectric layer exposed; and after forming the conductive structure, removing the second portion of the dielectric layer and exposed regions of the first portion of the dielectric layer, wherein, after the removing, a top surface of the recessed dielectric layer is disposed within the recess, and the recessed dielectric layer is substantially coplanar with a to surface of the conductive structure formed within the recess.