Patent ID: 9571059
Date: 2017-02-14
CPC Classifications: H03H,H05K

Claim:
1. A system comprising: a first PCB layer comprising first traces for differential signals to be transmitted to and from a first circuit disposed on the first PCB layer; a second PCB layer comprising second traces for differential signals to be transmitted to and from a second circuit disposed on the second PCB layer, the second PCB layer being different from the first PCB layer; a common mode choke (CMC) filter disposed on either the first traces or the second traces; and two parallel vias to couple the first traces to the second traces, the two parallel vias being disposed orthogonal to the first traces and the second traces, the two parallel vias being at a predetermined distance from one another, wherein the first traces, the two parallel vias, and the second traces comprise a channel between the first circuit and the second circuit; wherein differential signals transmitted at high speeds in the channel are characterized by an increase in capacitance and a decrease in inductance relative to a second channel having a single via.