Patent ID: 9660107
Date: 2017-05-23
CPC Classifications: B82Y,G06F,G11C,H01L

Claim:
1. A method of forming an array of nonvolatile memory cells, comprising: providing a substrate having an upper dielectric layer and a plurality of transistors disposed below the upper dielectric layer; forming a multi-layer interconnect above the plurality of transistors; forming a doped crystalline semiconductor layer; disposing the doped crystalline semiconductor layer over the upper dielectric layer; etching the doped crystalline semiconductor layer to form a plurality of nanowires that are horizontally-oriented with respect to a surface of the substrate; forming a charge-trapping stack of layers on the plurality of nanowires; forming a plurality of gate electrodes on the charge-trapping stack of layers; forming a first interconnection between a first nanowire of the plurality of nanowires and a first transistor of the plurality of transistors; and forming a second interconnection between a first gate electrode of the plurality of gate electrodes and a second transistor of the plurality of transistors; wherein the substrate is a bulk wafer.