Patent ID: 9589641
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a first page buffer block included in a first memory bank and a second page buffer block included in a second memory bank; an input/output control circuit suitable for transferring input data to data lines; a first column decoder and a second column decoder suitable for selecting the first page buffer block included in the first memory bank and the second page buffer block included in the second memory bank, respectively, to latch the input data transferred through the data lines, based on a plurality of page buffer selection signals and a column address transferred through address lines that are shared by the first and second column decoders; and a control signal generation circuit suitable for generating the plurality of page buffer selection signals, wherein data is input to the first and second memory banks at the same time when a first memory bank address corresponding to the first memory bank is input before a second memory bank address corresponding to the second memory bank is input, and a data input operation of the second memory bank is performed before a data input operation of the first memory bank when the second memory bank address is input before the first memory bank address is input.