Patent ID: 9672045
Date: 2017-06-06
CPC Classifications: G06F

Claim:
1. A system for checkpoint acceleration in a simultaneous multithreading (SMT) processor, the system comprising: circuitry of a processor core of the SMT processor to execute one or more threads comprising in a processing pipeline comprising an instruction fetch unit followed by a completion stage followed by a checkpoint stage, the checkpoint stage storing information to establish a recovery state comprising a next instruction address to execute after encountering a fault; and a checkpoint accelerator disposed between the completion stage and the checkpoint stage, the checkpoint accelerator comprising a backlog queue that stores a list of next-to-complete groups of instructions from the one or more threads anticipated to complete in an upcoming cycle and a selection control that drives one or more of the next-to-complete groups of instructions from the backlog queue to the checkpoint stage based on one or more completion indicators that identify which of next-to-complete groups of instructions actually completed.