Patent ID: 9741841
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A group III-V semiconductor device comprising: at least one buffer layer situated over a substrate; at least one transition layer situated over said at least one buffer layer, said at least one transition layer and said at least one buffer layer comprising different semiconductor materials; a first strain-relieving interlayer situated over said at least one transition layer and a second strain-relieving interlayer situated over said first strain-relieving interlayer; and a first group III-V semiconductor body situated over said second strain-relieving interlayer, wherein said first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in said first group III-V semiconductor body, wherein said first strain-relieving interlayer has a thickness greater than or substantially equal to 0.2 micrometers, wherein said second strain-relieving interlayer has a thickness greater than or substantially equal to 0.01 micrometers, wherein said first strain-relieving interlayer is thicker than said second strain-relieving interlayer.