Patent ID: 9697908
Date: 2017-07-04
CPC Classifications: G11C

Claim:
1. An integrated circuit, comprising: a read-only memory (ROM) array comprising a plurality of ROM cells arranged into a column, wherein the column is disposed proximate to a bit line and to a reference voltage line; wherein the plurality of ROM cells arranged into the column include a plurality of non-discharging ROM cells positioned adjacently to one another, wherein each non-discharging ROM cell has a source terminal, a drain terminal, or both coupled to at least one adjacent non-discharging ROM cell; and wherein the plurality of non-discharging ROM cells comprises: wherein the plurality of non-discharging ROM cells are coupled to the bit line using two or fewer connections comprising a first via and a second via, wherein the first via couples a source terminal or a drain terminal of the first non-discharging ROM cell to the bit line, and the second via couples a source terminal or a drain terminal of the second non-discharging ROM cell to the bit line; and wherein no vias are used to couple the bit line to source terminals or drain terminals of one or more non-discharging ROM cells disposed between the first non-discharging ROM cell and the second non-discharging ROM cell.