Patent ID: 9716037
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A semiconductor structure, comprising: a plurality of gate structures disposed over a three-dimensional active region of a substrate, each of the plurality of gate structures comprising a gate dielectric layer, a gate electrode, sidewall spacers, and a dielectric cap layer between and laterally adjacent to the sidewall spacers, wherein the sidewall spacers comprise a first dielectric material, wherein the dielectric cap layer comprises a second dielectric material different than the first dielectric material, and wherein the first dielectric material of the sidewall spacers and the second dielectric material of the dielectric cap layer meet at an approximately vertical interface; a plurality of contacts, each of the plurality of contacts disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures, and each of the plurality of contacts having a top surface substantially co-planar with a top surface of the dielectric cap layer of the plurality of gate structures, wherein the plurality of contacts comprises first and second immediately neighboring contacts both continuous between a first end and a second end, the first end at a first same location along a length of the plurality of gate structures orthogonal to a longest length of the three-dimensional active region, and the second end at a second same location along the length of the plurality of gate structures orthogonal to the longest length of the three-dimensional active region; and a plurality of contact plugs, each of the plurality of contact plugs disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures, and each of the plurality of contact plugs having a top surface substantially co-planar with the top surface of the dielectric cap layer of the plurality of gate structures, and substantially co-planar with the top surface of the plurality of contacts.