Patent ID: 9728497
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A substrate structure comprising: a base substrate; a plurality of unit substrate regions arranged on the base substrate in an array having one or more rows and one or more columns, the plurality of unit substrate regions in each row and column spaced apart from one another; and dummy substrate regions between the unit substrate regions, wherein in a row direction, a first pitch between central points of two adjacent first unit substrate regions among the unit substrate regions and a second pitch between central points of two adjacent second unit substrate regions among the unit substrate regions are different from each other, or in a column direction, a first pitch between central points of two adjacent first unit substrate regions among the unit substrate regions and a second pitch between central points of two adjacent second unit substrate regions among the unit substrate regions are different from each other, wherein sizes of each of the unit substrate regions are equal to each other, wherein for the array, in the row direction or the column direction, a distance between two adjacent unit substrate regions is smaller than each of the first pitch and the second pitch, and wherein the dummy substrate regions include a cutting region for forming individual semiconductor chips.