Patent ID: 9576620
Date: 2017-02-21
CPC Classifications: G06F,G11C,H03M

Claim:
1. A semiconductor apparatus comprising: a register input selection circuit configured to receive input data of a serial type and output the input data as a first data set and a second data set of a parallel type, or receive register selection output signals and output the register selection output signals as the first and second data sets, in response to a shift control signal and a capture control signal; a first data register configured to receive and store the first data set and output stored data as first register output signals; a second data register configured to receive and store the first and second data sets and output stored data as second register output signals; a register output selection circuit configured to output ones of the first and second register output signals as the register selection output signals; and a data output selection circuit configured to serially output one of the first and second data sets as output data.