Patent ID: 9722072
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device, comprising: providing a semiconductor substrate; forming a patterned conductive structure on the semiconductor substrate, wherein the patterned conductive structure comprises: forming a drain region in the first region of the semiconductor substrate; forming a first drift region in the semiconductor substrate, wherein the first drift region is at least partially formed in the first region of the semiconductor substrate, and the drain region is formed in the first drift region; forming a first isolation structure in the first drift region, wherein at least a part of the first isolation structure is disposed between the drain region and the first sub-gate structure, and another part of the first isolation structure is disposed under the gate structure; and forming a first contact structure on the drain region and the first sub-gate structure, wherein the drain region is electrically connected to the first sub-gate structure via the first contact structure.