Patent ID: 9685438
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A Field Effect Transistor (FET), comprising: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells, the plurality of gate electrodes being finger-like electrode extending outwardly from the gate contact; a drain contact connected to the drain pad of each one of the FET cells; a common source contact connected to source pad of each one of the FET cells; wherein the cells are disposed on a surface in a two-dimensional array; wherein a first portion of the FET cells have the gate electrodes thereof control a flow of carriers passing between the drain pads and the source pads of the first portion of the FET cells; wherein a second portion of the FET cells have the gate electrodes thereof control a flow of carriers passing between the drain pads and the source pads of the second portion of the FET cells; and wherein a plurality of the first portion of the gate electrodes being parallel and extending along a first direction and a plurality of the second portion of the gate electrode being parallel and extending along a second direction, the second direction intersecting the first direction.