Patent ID: 9721645
Date: 2017-08-01
CPC Classifications: G11C,H01L

Claim:
1. A static random access memory (SRAM) array comprising: a first SRAM mini array comprising a first plurality of functional SRAM cells in a first column of the SRAM array, wherein each of the first plurality of functional SRAM cells share a first bit line (BL); a second SRAM mini array comprising a second plurality of functional SRAM cells in the first column, wherein each of the second plurality of functional SRAM cells share a second BL independently controlled from the first BL; and a SRAM dummy array between the first SRAM mini array and the second SRAM mini array, wherein the SRAM dummy array comprises a plurality of SRAM array abut dummy cells in the first column, wherein a line extending along a longitudinal axis of the first BL extends through the first BL and the second BL in a top down view, and wherein a first endpoint of the first BL and a second endpoint of the second BL are disposed in the SRAM dummy array.