Patent ID: 9653664
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A chip package, comprising: a chip substrate which includes conductive portions laminated in one direction to constitute the chip substrate, insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions, a cavity depressed inward of the conductive portions in a region including the insulation portions, and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape; an optical element mounted within the cavity; and a sealing member bonded to the chip substrate by an adhesive agent disposed within the groove portion in order to seal the cavity, the sealing member including a shielding portion formed on one surface corresponding to the groove portion, wherein the groove portion is formed on partial regions of the conductive portions and partial regions of the insulation portions, and the adhesive agent is disposed on the partial regions of the conductive portions and the partial regions of the insulation portions.