Patent ID: 9653468
Date: 2017-05-16
CPC Classifications: G11C,H01L

Claim:
1. An apparatus comprising: first and second semiconductor active regions; a first trench formed in the first semiconductor active region to define first and second legs, wherein the first and second legs sandwich the first trench therebetween; a second trench formed in the second semiconductor active region to define third and fourth legs, wherein the third and fourth legs sandwich the second trench therebetween; first conductive line in electrical contact with the first leg, wherein the first conductive line is elongated to pass through over the second trench with an electrical isolation from each of the third and fourth legs; and a second conductive line in electrical contact with the third leg, wherein the second conductive line is elongated to pass through over the first trench with an electrical isolation from each of the first and second legs.