Patent ID: 9542211
Date: 2017-01-10
CPC Classifications: G06F

Claim:
1. A system comprising: a processor to execute instructions, the processor including at least one core and a dynamic language accelerator to execute bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator, the dynamic language accelerator to receive a pathname from a virtual machine, the pathname to associate the file descriptor with the dynamic language accelerator, wherein the processor is to block execution of native code on the at least one core while the dynamic language accelerator executes is to execute the bytecode and configure, via a system call, a mapping on a native state of the processor to a virtual machine state of a virtual machine that is to trigger the dynamic language accelerator, the virtual machine a state including a bytecode state, and the processor is to associate an identifier with the virtual machine state, the processor further comprising an accelerator native interface coupled to the dynamic language accelerator, where the dynamic language accelerator is to call back to a native library via the accelerator native interface, wherein the processor is to execute a function for the virtual machine using the native library and to continue execution of the bytecode in the dynamic language accelerator after the function is executed; and system memory coupled to a processor.