Patent ID: 9748003
Date: 2017-08-29
CPC Classifications: G11C

Claim:
1. A system, comprising: a plurality of embedded memories, wherein each embedded memory includes a redundant feature selected from the group consisting of a redundant column and a redundant row, and wherein each embedded memory is configured to decode a memory redundancy address to select for the embedded memory's redundant feature while a redundancy enable signal for the embedded memory is asserted; a first decoder configured to decode a first selection address into a first selection signal to select for one of the embedded memories; a second decoder configured to decode a second selection address into a second selection signal to select for another one of the embedded memories; a fuse-programmable memory configured to store the first selection address, a first redundancy address, the second selection address, and a second redundancy address; and a plurality of multiplexers corresponding to the plurality of embedded memories, wherein each multiplexer is configured to both select for the first redundancy address as the memory redundancy address for its corresponding memory and to assert the redundancy enable signal for its corresponding memory when the first selection signal selects for the corresponding memory, and wherein each multiplexer is configured to both select for the second redundancy address as the memory redundancy address for its corresponding memory and to assert the redundancy address its corresponding memory when the second selection signal selects for to provide the second redundancy address as the memory redundancy address to its corresponding memory when the second selection signal selects for the corresponding memory.