Patent ID: 9741749
Date: 2017-08-22
CPC Classifications: G02F,G11C,H01L,H03K

Claim:
1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a capacitor, wherein a gate of the first transistor is electrically connected to one of a pair of terminals of the capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a terminal, wherein the one of the pair of terminals of the capacitor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the pair of terminals of the capacitor is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the pair of terminals of the capacitor is electrically connected to one of a source and a drain of the fifth transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to a second wiring, wherein the other of the source and the drain of the fifth transistor is electrically connected to a third wiring, wherein a gate of the fourth transistor is electrically connected to a fourth wiring, wherein a gate of the fifth transistor is electrically connected to a fifth wiring, wherein the first wiring is configured to be supplied with a power supply voltage, wherein the second wiring is configured to be supplied with a signal, and wherein the third wiring is configured to be supplied with a constant voltage.