Patent ID: 9641167
Date: 2017-05-02
CPC Classifications: G05F,G11C,H03K

Claim:
1. A current mirror circuit comprising: a first transistor connected to a voltage source, a gate of the first transistor being connected to a drain of the first transistor; a current source connected to the drain and the gate of the first transistor, the current source being configured to generate a predetermined first output current; a sample and hold circuit having an input connected to the gate of the first transistor; a second transistor connected to the voltage source, a gate of the second transistor being connected to an output of the sample and hold circuit, a drain of the second transistor being connected to a digital to analog converter (DAC) to provide at least a portion of an output signal for the DAC; and a controller operatively connected to the sample and hold circuit, the controller being configured to generate a control signal at a frequency of the output signal that the DAC generates during operation with a duty cycle of not more than 10% to operate the sample and hold circuit to attenuate bias noise from the first transistor at the frequency and increase bias noise for at least one other frequency other than the predetermined frequency in a second output current from the second transistor.