Patent ID: 9547449
Date: 2017-01-17
CPC Classifications: G06F,G11C

Claim:
1. A memory system, comprising: a primary memory; a back-up memory that mirrors the primary memory; a fault monitor table; and a memory controller operably coupled to the primary memory, the back-up memory, and the fault monitor table, the memory controller configured to: receive a read request including a logical address of a target data; search the fault monitor table for an entry corresponding to the received logical address, the fault monitor table comprising a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory; based on locating an entry corresponding to the received logical address, select one of the primary memory and the backup memory for retrieving the target data, the selection based on contents of the fault monitor table; receive a correction notice indicating correction of one of the memory failure events; and remove an entry in the fault monitor table corresponding to the one of the memory failure events.