Patent ID: 9672926
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory strings, each of the memory strings comprising memory cells connected in series; bit lines connected to the memory strings, respectively; word lines connected to the memory cells, respectively, and connected to the memory strings in common; and a control circuit configured to repeat a program operation of applying a program pulse voltage to a selected word line and programming data in selected memory cells connected to the selected word line, and a verify operation of checking threshold voltages of the selected memory cells, wherein the control circuit performs a first verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage, wherein the first threshold voltage is less than the second threshold voltage, wherein the control circuit performs a charging operation and then performs a sensing operation, wherein the control circuit charges a first bit line for the first verify operation to a first charge voltage and charges a second bit line for the second verify operation to a second charge voltage in the charging operation, the second charge voltage being different from the first charge voltage, wherein the control circuit senses discharge states of the charged first and second bit lines in the sensing operation, wherein the first charge voltage and the second charge voltage are not 0V, and wherein the control circuit simultaneously performs the first verify operation and the second verify operation.