Patent ID: 9559100
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising: forming a first fin structure and a second fin structure; forming an isolation layer so that lower portions of the first and second fin structures are embedded in the isolation layer and upper portions of the first and second fin structure protrude from the isolation insulating layer; forming a dummy gate structure including a dummy dielectric layer disposed over the first and second fin structures and a dummy electrode layer disposed over the dummy dielectric layer; forming an interlayer dielectric layer so that the dummy gate structures are embedded in the interlayer dielectric layer; patterning the dummy electrode layer so that the dummy electrode layer is divided into at least a first dummy electrode layer and a second dummy electrode layer separated by an opening; forming a separation plug by filling the opening with an insulating material; removing the first and second dummy electrode layers so that a first electrode space and a second electrode space are formed and the separation plug is exposed between the first electrode space and the second electrode space; etching the exposed separation plug; and forming a first gate structure and a second gate structure in the first electrode space and the second electrode space, respectively, wherein the first gate structure is disposed over the first fin structure and the second gate structure is disposed over the second fin structure.