Patent ID: 9685535
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor device, the method comprising: forming a gate sack on a semiconductor layer; depositing a first layer of spacer material over the gate stack and exposed portions of the semiconductor layer; depositing a second spacer layer over the first layer of spacer material; removing portions of the second spacer layer to expose portions of the first layer of spacer material; removing portions of the first layer of spacer material to form a spacer adjacent to the gate stack such that a portion of the second spacer layer is arranged on a region of the spacer; removing an exposed portion of the semiconductor layer to expose portions of an insulator layer; etching to remove portions of the insulator layer to form a cavity beneath the semiconductor layer and the spacer; epitaxially growing a source/drain region from exposed portions of the semiconductor layer to fill the cavity with the source/drain region; depositing another insulator layer on the source/drain region and the gate stack; removing portions of the another insulator layer to form a second cavity that exposes portions of the spacer and the source/drain region; removing portions of the source/drain region in the second cavity; and depositing a conductive material in the second cavity.