Patent ID: 9552859
Date: 2017-01-24
CPC Classifications: G11C

Claim:
1. A combination random-access memory (RAM) and read-only memory (ROM) electronic data-storage device, comprising: at least two bit lines; at least two current sources, each of the current sources connected to a corresponding one of the bit lines; a plurality of bit cells, the bit cells each comprising a series connection of a selection element and a variably-resistive storage element, the bit cells each comprising a cell input node having a permanent connection to only one of the bit lines and a cell output node connected to a source line, the selection element having a control input connected to a word line; a first sensing amplifier connected to a first one of the bit lines, the first sensing amplifier configured to output a first voltage when the first bit line is driven above a reference voltage and a second voltage when the first bit line is driven below the reference voltage; a second sensing amplifier connected to a second one of the bit lines, the second sensing amplifier configured to output the first voltage when the second bit line is driven above the reference voltage and the second voltage when the second bit line is driven below the reference voltage.