Patent ID: 9652229
Date: 2017-05-16
CPC Classifications: G06F,Y02D

Claim:
1. A semiconductor device comprising: a data transfer controller operable to transfer plural pieces of data from a source address area to a destination address area continuously based on data transfer information, when a start request is received; and an arithmetic unit operable to perform operation with the concurrent use of the plural pieces of data received from the data transfer controller, wherein the data transfer controller selects a first transfer mode, based on the transfer mode specifying information included in the data transfer information, wherein, in the first transfer mode, the data transfer controller reads the plural pieces of data from the source address area sequentially, and performs transfer operation to transfer the plural pieces of data read to the arithmetic unit in the order of the read, wherein the plural pieces of data comprise: plural pieces of input data used as an arithmetic target of the arithmetic unit; and plural pieces of coefficient data employed in the operation of the arithmetic unit, and wherein the arithmetic unit adds each of results of operation performed to the plural pieces of the input data using the coefficient data corresponding to the input data among the plural pieces of the coefficient data, and generates output data, wherein the arithmetic unit performs a first arithmetic operation to generate one piece of output data, corresponding to a third transfer operation of the transfer operation, wherein the arithmetic unit performs a second arithmetic operation to generate one piece of output data, corresponding to a fourth transfer operation of the transfer operation performed continuously after the third transfer operation, and wherein the arithmetic unit employs the arithmetic result for the kth input data (k is a positive integer) obtained by the first arithmetic operation, as the (k−1)th input data of the second arithmetic operation.