Patent ID: 9640491
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: an intermediate plate; two semiconductor elements connected to one of surfaces of the intermediate plate by a brazing filler metal adjacent to the two semiconductor elements; a main plate connected to the other one of the surfaces of the intermediate plate by a brazing filler metal adjacent to the main plate; and a resin layer, the intermediate plate having an external region extending to an outer side with respect to both a region in which the intermediate plate is connected to the brazing filler metal adjacent to the two semiconductor elements and a region in which the intermediate plate is connected to the brazing filler metal adjacent to the main plate, a first through-hole extending through the intermediate plate in the external region, and a third through-hole extending through the intermediate plate and in an area between the two semiconductor elements, the resin layer covering at least the brazing filler metal adjacent to the two semiconductor elements, the intermediate plate, the brazing filler metal adjacent to the main plate and a surface of the main plate in which the main plate faces the intermediate plate, the resin layer being also arranged inside the first through-hole.