Patent ID: 9577089
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method of fabricating a dual gate semiconductor device, said method comprising: depositing oxide into a first trench and into a second trench that are formed in a substrate, said oxide also deposited over a mesa that is between said first trench and said second trench; depositing first polysilicon into said first trench and into said second trench; performing a first polysilicon polishing process to planarize the exposed upper surfaces of said first polysilicon so that, after said first polysilicon polishing process, exposed surfaces of said first polysilicon are flush with the surface of said oxide; after said polysilicon polishing process, performing an oxide polishing process to remove said oxide from over said mesa and further remove part of said first polysilicon so that, after said oxide polishing process, exposed surfaces of said first polysilicon are flush with said mesa; after said first polysilicon polishing process, forming a third trench in said substrate between said first and second trenches, wherein said third trench is shallower than said first and second trenches; depositing second polysilicon into said third trench; performing a second polysilicon polishing process to planarize an exposed surface of said second polysilicon so that said surface is flush with adjacent surfaces; and forming a first metal contact to said first polysilicon and a second metal contact to said second polysilicon.