Patent ID: 9633912
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe, each formed fin comprising a hard mask layer on a top surface; depositing Si on a first subset of the set of fins in what will be an nFET area; performing a Si—Ge inter-mixing process on the first subset of fins to reduce a concentration of Ge in the first subset of fins while producing a Si—Ge intermix layer; removing the Si—Ge intermix layer leaving the first subset of fins having the reduced concentration of Ge; and forming a second subset of fins in what will be a pFET area, the second subset of fins being formed from the layer of SiGe and having a greater percentage of Ge than a percentage of Ge in the first subset of fins.