Patent ID: 9711238
Date: 2017-07-18
CPC Classifications: G09G,G11C

Claim:
1. A shift register comprising stages each including: a holding circuit; and a clock output circuit, the holding circuit including the gate terminals of the first CMOS circuit, the drain terminals of the second CMOS circuit, and the first output terminal being connected to one another, and the drain terminals of the first CMOS circuit, the gate terminals of the second CMOS circuit, and the second output terminal being connected to one another, the clock output circuit including an output terminal that outputs an output signal having a high electric potential or a low electric potential, depending on at least one of output signals from the holding circuit and on a second clock signal, the holding circuit carrying out a reset operation in accordance with the first clock signal supplied to the reset transistor, and the first clock signal and the second clock signal have respective phases.