Patent ID: 9535847
Date: 2017-01-03
CPC Classifications: G06F,G11C

Claim:
1. An apparatus for compressing and storing configuration data for a multi-core processor, the apparatus comprising: a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program said plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on said die, wherein each of said plurality of cores, upon power-up/reset, accesses and decompresses all of said compressed configuration data, for initialization of elements within said each of said plurality of cores, and wherein a first one of said plurality of data types comprises system hardware configuration data that said each of said plurality of cores employs to initialize control circuit elements within said each of said plurality of cores, and wherein a second one of said plurality of data types comprises microcode patch data that said each of said plurality of cores employs to initialize microcode patch elements within said each of said plurality of cores, said device programmer comprising: a virtual fuse array, configured to store the configuration data for said plurality of cores, said configuration data comprising a plurality of data types; and a compressor, coupled to said virtual fuse array, configured to read said virtual fuse array, and configured to compress the configuration data by employing a plurality of compression algorithms to generate said compressed configuration data, wherein said plurality of compression algorithms correspond to said plurality of data types.