Patent ID: 9536604
Date: 2017-01-03
CPC Classifications: G11C,H05K

Claim:
1. A memory system, comprising: a driver; a conductive trace coupled to an output of the driver at a first end and to a connector junction at a second end; a first discrete resistor coupled to the connector junction at a first end and a first connector lead at a second end, wherein the first connector lead is configured to couple to a first memory module; a second discrete resistor coupled to the connector junction at a first end and a second connector lead at a second end, wherein the second connector lead is configured to couple to a second memory module, wherein resistive values of the first and second resistors are the same, and wherein the resistive values of the first and second resistors result in back reflections at the connector junction when the driver transmits a signal to the first and second connector leads; a third discrete resistor coupled to the connector junction at a first end and a second connector junction at a second end, wherein the third resistor is disposed between the connector junction and the driver; a fourth discrete resistor coupled to the second connector junction at a first end and a third connector lead at a second end, wherein the third connector lead is configured to couple to a third memory module, and wherein a resistance value of the first resistor is an integer multiple of a resistance value of the fourth resistor.