Patent ID: 9570368
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor package, comprising: forming a passivation layer over a semiconductor substrate, wherein the semiconductor substrate comprises a first chip region, a second chip region and a scribe line region, the scribe line region is between the first chip region and the second chip region, and the passivation layer includes a non-planar uppermost surface having a first height over edges of the first and second chip regions as measured from an upper surface of the substrate and having a second height near the scribe line region as measured from the upper surface of the substrate, the second height being less than the first height; forming a bump over the passivation layer on at least one of the first chip region or the second chip region; removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region, wherein the groove has a first width and a first depth with respect to an upper surface of the passivation layer, and wherein the first depth terminates at a groove surface that is substantially parallel to an upper surface of the semiconductor substrate; removing a portion of the semiconductor substrate to extend the groove to a second depth with respect to the upper surface of the passivation layer, the second depth being greater than the first depth and being less than a thickness of the semiconductor substrate, wherein the portion of the semiconductor substrate removed has a second width less than the first width; filling an entirety of the groove with a molding compound layer, wherein the molding compound layer covers the passivation layer, and covers a lower portion of the bump; and separating the first chip region from the second chip region along the scribe line region.