Patent ID: 9685366
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method for forming chamferless vias, the method comprising: receiving a substrate stack comprising a hard mask layer, a porous dielectric layer underlying the hard mask layer, a cap layer underlying the dielectric layer, and a conductive layer underlying the cap layer; opening a portion of the hard mask layer to reveal a portion of the dielectric layer; opening a plurality of vias to extend through the dielectric layer and the cap layer; depositing into the vias a pore filling material comprising a thermally decomposable polymer wherein the pore filling material alone and the dielectric layer containing the pore filling material have different etch selectivities; annealing to harden the pore filling material in the vias and drive the pore filling material into pores of the dielectric layer adjacent to the vias; patterning and etching a trench coincident with the vias wherein etching the trench further comprises selectively etching the pore filling material in the vias to control a plug height of the pore filling material; removing the hard mask layer; and conducting a dissipation process to remove the pore filling material.