Patent ID: 9728468
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A manufacturing method of a semiconductor device, comprising: forming a first well of a first conductivity type in a first region of a semiconductor substrate; forming a second well of a second conductivity type that is opposite to the first conductivity type in a second region of the semiconductor substrate; forming a third well of the second conductivity type in a third region of the semiconductor substrate; forming a fourth well of the first conductivity type in a fourth region of the semiconductor substrate; forming a fifth well of the first conductivity type that is shallower than the third well in the third region; forming a sixth well of the second conductivity type that is shallower than the fourth well at the fourth region; forming a first gate electrode of a first transistor of a first complementary transistor pair on the first well; forming a second gate electrode of a second transistor of the complementary transistor pair on the second well; forming a third gate electrode of a third transistor of a second complementary transistor pair on the fifth well; forming a fourth gate electrode of a fourth transistor of the second complementary transistor pair on the sixth well; forming a first source/drain region of the second conductivity type in the first well and of the first transistor; forming a second source/drain region of the first conductivity type in the second well and of the second transistor; forming a third source/drain region of the second conductivity type in the fifth well and of the third transistor; forming a fourth source/drain region of the first conductivity type in the sixth well and of the fourth transistor; connecting the first well to a first power supply line, and connecting the third well to a second power supply line; forming a first electric conductor electrically connecting the third gate electrode to the fifth well; and forming a second electric conductor electrically connecting the fourth gate electrode to the sixth well, wherein the semiconductor device includes a logic cell that includes the first complementary transistor pair and the second complementary transistor pair, the first complementary transistor pair is electrically connected to an input terminal of the logic cell, and the second complementary transistor pair is electrically connected to an output terminal of the logic cell.