Patent ID: 9626028
Date: 2017-04-18
CPC Classifications: G06F,G09G,G11C

Claim:
1. A Gate Driver on Array (GOA) circuit, comprising: a drive line scan control signal generation circuit configured to generate a drive line scan clock signal and a drive line scan pulse signal; multiple GOA groups connected with the drive line scan control signal generation circuit and connected in series with each other sequentially, which are configured to acquire the drive line scan clock signal, to generate GOA group output signals sequentially according to GOA group input signals, wherein the GOA group output signal generated by one of the GOA groups is the GOA group input signal of a next GOA group so as to realize a shift register function of the multiple GOA groups; multiple drive line scan signal generation circuits connected with the multiple GOA groups respectively and connected with the drive line scan control signal generation circuit, which are configured to acquire the GOA group output signals and the drive line scan pulse signal, and to generate drive line scan signals sequentially; multiple gate line groups connected with the multiple drive line scan signal generation circuits respectively, which are configured to be applied with the drive line scan signals, so as to complete drive line scan for the multiple gate line groups sequentially.