Patent ID: 9570567
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method for manufacturing a FinFET, the method comprising: forming a fin structure on a substrate; forming a dielectric layer on a top surface and two side surfaces of the fin structure, wherein the side surfaces are connected to two opposite edges of the top surface, and the fin structure and the dielectric layer are formed from different materials; forming a dummy gate on a first portion of the dielectric layer; forming two spacers respectively on two opposite sidewalls of the dummy gate, wherein an operation of forming the spacers comprises forming the spacers respectively on two second portions of the dielectric layer and exposing two third portions of the dielectric layer, wherein each of the second portions of the dielectric layer is located between the first portion and one of the third portions of the dielectric layer; performing a first etching operation on the dielectric layer and the fin structure to remove the third portions and a portion of each of the second portions of the dielectric layer, and two first portions of the fin structure underlying the third portions and the portions of the second portions of the dielectric layer, thereby forming two first recesses respectively in the spacers; and performing a second etching operation on the fin structure to remove two second portions of the fin structure which are respectively adjacent to the first portions of the fin structure, thereby forming two second recesses in the dielectric layer, wherein the second recesses respectively communicate with the first recesses.