Patent ID: 9564415
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A semiconductor package device comprising: a semiconductor substrate having a first surface and a second surface, the semiconductor substrate including a plurality of integrated circuits formed proximate to the first surface and a plurality of attachment bumps disposed over the first surface, the semiconductor substrate having a first width; a first passive energy component disposed over the second surface, the first passive energy component including a first non-spherical surface-mount pad and a second non-spherical surface-mount pad, the plurality of attachment bumps having a first melting point and the non-spherical surface-mount pad having a second melting point, the second melting point higher than the first melting point, the non-spherical surface-mount pad having a generally trapezoidal cross-sectional shape; a second passive energy component disposed over the second surface, the second passive energy component including a first non-spherical surface-mount pad and a second non-spherical surface-mount pad, the plurality of attachment bumps having a first melting point and the non-spherical surface-mount pad having a second melting point, the second melting point higher than the first melting point, the second passive energy component different from the first passive energy component, the non-spherical surface-mount pad having a generally trapezoidal cross-sectional shape; a first micro through-substrate via at least substantially extending from the first surface to the second surface, the first micro through-substrate via configured to electrically connect the first passive energy component to a first integrated circuit of the plurality of integrated circuits and a second micro through-substrate via at least substantially extending from the first surface to the second surface, the second micro through-substrate via configured to electrically connect the second passive energy component to a second integrated circuit of the plurality of integrated circuits; a first redistribution layer disposed over the second surface, the first redistribution layer configured to furnish an electrical connection between the first passive energy component and the first through-substrate via, the first passive energy component electrically connected to the first redistribution layer through the first non-spherical surface-mount pad of the first passive energy component; a second redistribution layer disposed over the second surface, the second redistribution layer configured to furnish an electrical connection between the first passive energy component and the second energy component, the first passive energy component electrically connected to the second redistribution layer through the second non-spherical surface-mount pad of the first passive energy component and the second passive energy component electrically connected to the redistribution layer through the first non-spherical surface-mount pad of the second passive energy component; a third redistribution layer disposed over the second surface, the third redistribution layer configured to furnish an electrical connection between the second passive energy component and the second through-substrate via, the second passive energy component electrically connected to the second redistribution layer through the second non-spherical surface-mount pad of the second passive energy component; and an encapsulation structure disposed over the second surface, the encapsulation structure at least substantially encapsulating the first passive energy component and the second passive energy component, the encapsulation structure having a second width, the second width corresponding to the first width, the encapsulation structure comprising a mold compound.