Patent ID: 9621146
Date: 2017-04-11
CPC Classifications: H02M,H03K

Claim:
1. A digital current equalization method, comprising: acquiring a current value from a counter preset value loading module in each synchronization period, wherein the current value is a value of an output current magnitude of a first power supply module in which the counter preset value loading module is located, and is used to represent a modulation frequency of a first pulse frequency modulation (PFM) generator on the first power supply module; and the synchronization period is a synchronization period of the first PFM generator on the first power supply module and a second PFM generator on a second power supply module connected in parallel to the first power supply module; generating a continuous variable frequency pulse according to the current value, and receiving a synchronization signal transmitted by a phase inverter connected to the first PFM generator, wherein the synchronization signal is information about a synchronous updating time acquired by the phase inverter from a digital current equalization bus connected to the first power supply module; transmitting, according to the synchronization signal, the continuous variable frequency pulse to the digital current equalization bus through an open-collector gate of a triode connected to the first PFM generator; counting a frequency of the continuous variable frequency pulse on the digital current equalization bus, wherein an obtained frequency count value is used to represent a current magnitude of a power supply module that currently outputs a greatest current among the first power supply module and the second power supply module connected in parallel; and adjusting an output current of the first power supply module according to the current magnitude of the power supply module among the first power supply module and the second power supply module connected in parallel that currently outputs the greatest current.