Patent ID: 9741729
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A nonvolatile memory device comprising: a charge storage element having a MOS capacitor structure and including a control gate terminal connected to a word line and a body terminal connected to a body bias line; a first half-MOS transistor having a first selection gate terminal connected to the word line and a first impurity junction terminal connected to a bit line and sharing the body terminal with the charge storage element; and a second half-MOS transistor having a second selection gate terminal connected to the word line and a second impurity junction terminal connected to a source line and sharing the body terminal with the charge storage element, wherein the charge storage element is coupled between the first and second half-MOS transistors so that the first half-MOS transistor, the charge storage element, and the second half-MOS transistor are connected in series.