Patent ID: 9722589
Date: 2017-08-01
CPC Classifications: G06F,H01P,H03K

Claim:
1. A clock distribution network for distributing a clock signal in a superconducting integrated circuit, the clock distribution network comprising: a first clock structure comprising a first plurality of unit cells, wherein each of the first plurality of unit cells includes at least one spine and at least one stub, the at least one spine connected to the at least one stub, the at least one stub further inductively coupled to at least one first superconducting element, wherein the clock signal has a wavelength, wherein each of the first plurality of unit cells is spaced apart from each other along the first clock structure by a distance, and wherein the distance is less than one tenth of the wavelength, and wherein the clock distribution network further comprises a second clock structure, and wherein the first clock structure is configured to provide in-phase clock signals and the second clock structure is configured to provide quadrature-phase clock signals.