Patent ID: 9543034
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A non-volatile memory comprising: a memory array; and a current sensing checking block suitable for verifying a programming of a desired group of cells of the memory array by comparing an actual number of programming failures with a reference number of allowable programming failures, wherein the current sensing checking block comprises: a current mirror; a programming status input block comprising a plurality of sub-blocks, each sub-block being provided with a programming status information for each bit-line for the desired group of the cells, the sub-blocks being connected with each other in parallel with respect to a first node, the first node being coupled to the input node of the current mirror; a reference block comprising a plurality of sub-blocks, each sub-block being provided with a 1-bit voltage value based on the reference number of allowable programming failures, the sub-blocks being connected with each other in parallel with respect to a second node, the second node being coupled to the output node of the current mirror; an operational amplifier operable to compare voltage levels of the first node and the second node to determine whether the actual number of programming failures for the desired group of cells exceeds the reference number of allowable programming failures of the reference block; a first switched capacitor operable to couple the first node to a first input node of the operational amplifier and to a ground voltage; and a second switched capacitor operable to couple the second node to a second input node of the operational amplifier and to the ground voltage as well as to couple the output node to the second input node of the operational amplifier.