Patent ID: 9690620
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A method for dynamic heterogeneous polymorphic processing in a processor comprising a plurality of processing cores, each of the plurality of processing cores assigned to one of a plurality of core clusters and each of the plurality of core clusters dynamically forming a coalition comprising two or more processing cores of the plurality of processing cores, the method comprising the steps of: receiving a processing task comprising a plurality of serial threads; dividing each of the plurality of serial threads into a plurality of basic blocks, each of the plurality of basic blocks comprising a single entry point and a single exit point; creating a control flow for the plurality of basic blocks; determining whether each of the plurality of serial threads requires more than one processing core; sending a go-into-coalition-mode-now instruction to ones of the plurality of core clusters for handling ones of the plurality of serial threads that require more than one processing core; adding one of a plurality of sentinel instructions to each of the plurality of basic blocks of the ones of the plurality of serial threads that require more than one processing core, each of the plurality of sentinel instructions comprising information for processing of the plurality of basic blocks; and upon execution completion of each of the ones of the plurality of serial threads that requires more than one processing core, sending a go-out-of-coalition-mode-now instruction to corresponding ones of the plurality of core clusters.