Patent ID: 9679815
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, the method comprising: sequentially forming a hard mask layer and a first sacrificial layer on a substrate; forming an upper mandrel that includes at least first to third upper sub-mandrels on the first sacrificial layer, the first to third upper sub-mandrels each extending in a first direction and being spaced apart from each other in a second direction that intersects the first direction, a width of the first upper sub-mandrel in the second direction being smaller than widths of the second and third upper sub-mandrels in the second direction; forming first spacers on both side walls of each of the first through third upper sub-mandrels; removing the upper mandrel; etching the first sacrificial layer using the first spacers as etching masks to form a lower mandrel that includes a plurality of lower sub-mandrels; forming second spacers on both side walls of the lower sub-mandrels; removing the lower mandrel; patterning the hard mask layer and the substrate using the second spacers as etching masks to form a fin type pattern, the fin type pattern including first to tenth fins which extend alongside each other in the first direction and are spaced apart from each other in the second direction; removing the first, second, fifth and eighth fins; and forming a first gate electrode and a second gate electrode, the first gate electrode extending in the second direction to intersect the third, fourth, sixth and seventh fins, and the second gate electrode extending in the second direction to intersect the sixth, seventh, ninth and tenth fins while not intersecting the third and fourth fins, and being spaced apart from the first gate electrode in the first direction.