Patent ID: 9652239
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A method of executing instructions from an instruction set architecture in a processing unit, the method comprising: receiving an instruction from an instruction stream, the instruction including an extended decode mode indicator that indicates whether the instruction is decoded using an extended decode mode; accessing a page table entry associated with a page of memory within which the instruction is stored in an address space to retrieve a decode-related attribute associated with the page of memory, wherein the decode-related attribute comprises an index, and wherein accessing the page table entry includes accessing the page table entry from a memory address translation data structure; accessing a primary opcode table using the index to select a primary opcode associated with the index from among a plurality of primary opcodes in the primary opcode table; and in response to the extended decode mode indicator indicating that the instruction is decoded using the extended decode mode, decoding the instruction using the instruction and the selected primary opcode from the primary opcode table.