Patent ID: 9581973
Date: 2017-02-28
CPC Classifications: G04F,G04G,H03B,H03K

Claim:
1. An integrated circuit providing a dual mode clock output signal, the integrated circuit comprising: a resonator; a first clock circuit having a first oscillator circuit coupled to the resonator, the first clock circuit for generating a first clock signal having a first frequency in response to the resonator; a second clock circuit having a second oscillator circuit coupled to the resonator and a programmable frequency divider, the second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider; and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit to provide a dual mode clock output signal.