Patent ID: 9741738
Date: 2017-08-22
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: memory cells electrically connected in series in a first direction crossing a substrate, the memory cells including: a first cell transistor at a first level, the first cell transistor including a first semiconductor portion, a first electrode, and a first memory portion provided between the first semiconductor portion and the first electrode, the first cell transistor having a first distance between a central axis and an outer surface of the first semiconductor portion, a second cell transistor at a second level, the second cell transistor including a second semiconductor portion, a second electrode, and a first insulating layer provided between the second semiconductor portion and the second electrode, the second cell transistor having a second distance between a central axis and an outer surface of the second semiconductor portion, and a third cell transistor at a third level, the second level being between the first level and the third level in the first direction, the third cell transistor including a third semiconductor portion, a third electrode, and a second memory portion provided between the third semiconductor portion and the third electrode, the third memory cell having a third distance between a central axis and an outer surface of the third semiconductor portion, wherein the second distance is larger than the first distance and the third distance.