Patent ID: 9613874
Date: 2017-04-04
CPC Classifications: G01N,H01J,H01L

Claim:
1. A method for evaluating a semiconductor device structure, the method comprising: forming a support layer on a first side of a lamellar sample portion of the semiconductor device structure, wherein the lamellar sample portion has a second side opposite the first side, a target analysis area on or proximate the first side, and a first thickness defined from the first side to the second side, wherein forming the support layer comprises forming the support layer using a technique chosen from a physical vapor deposition (PVD) process or an electron beam gas-injection process; milling the second side to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite the first side; removing the support layer from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar sample portion having a second thickness that is defined from the first side to the milled second side and that is less than the first thickness; and evaluating the target analysis area of the reduced thickness lamellar sample portion.