Patent ID: 9627498
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method for forming a 3D circuit, comprising: forming a stack including alternating thin film layers of semiconductor material and insulating material, each of the thin film layers of semiconductor material on respective ones of the thin film lavers of insulating material in the stack, each of the thin film layers of semiconductor material having a thickness less than 20 nm; forming an interlayer insulator over the stack; etching a pattern of openings in the interlayer insulator and the stack to expose landing areas on each of the thin film layers of semiconductor material; forming a layer of sidewall barrier material within the openings; etching the layer of sidewall barrier material to expose the landing areas and form spacers on the sidewalls of the openings; adding some of said semiconductor material on the exposed landing areas within the openings; adding p-type or n-type dopants to the added semiconductor material by ion implantation; depositing a reaction precursor on said doped semiconductor material on the landing areas in the openings and causing reaction of the precursor with the semiconductor material within the openings; and forming interlayer conductors within the openings; wherein each of the landing areas exposed by the openings has a maximum width that is at least one (1) times the thickness of the thin film layer of semiconductor material in the landing areas.