Patent ID: 9666642
Date: 2017-05-30
CPC Classifications: G11C,H01L

Claim:
1. A variable resistance memory device, comprising: a base layer; a plurality of pillar-shaped gate electrodes formed on the base layer and extending substantially perpendicular to a surface of the base layer; a current transfer layer formed to surround the plurality of pillar-shaped gate electrodes; a variable resistance layer formed in an outer portion of the current transfer layer; and a plurality of blocking layers generated between each of the plurality of pillar-shaped gate electrodes and the current transfer layer, wherein the plurality of pillar-shaped gate electrodes are formed of a conductive material and the current transfer layer is formed of a predetermined conductivity-type semiconductor layer, and further comprising: a junction layer interposed between each of the plurality of pillar-shaped gate electrodes and the current transfer layer; and a gate insulating layer interposed between each of the plurality of pillar-shaped gate electrodes and the junction layer.