Patent ID: 9607902
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate having a plurality of NFET regions and a plurality of PFET regions; forming an insulation layer on a surface of the semiconductor substrate; forming a sacrificial layer on the insulation layer; forming a first trench in each of the PFET regions, and a second trench in each of the NFET regions; forming a third trench on bottom of each of the first trenches and the second trenches; forming a first buffer layer in each of the first trenches and the second trenches by filling the third trenches; forming a first semiconductor layer on each of the first buffer layers; removing the first semiconductor layers in the second trenches in the NFET regions; forming a second buffer layer with a top surface in each of the second trenches, wherein the top surface of the second buffer layer is lower than a plane defined by an intersection of the insulation layer and the sacrificial layer; forming a second semiconductor layer on each of the second buffer layers; and removing the sacrificial layer, thereby exposing portions of side surfaces of the first and second semiconductor layers; and forming first and second gate structures on the first and second semiconductor layers respectively.