Patent ID: 9691893
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: preparing a first region and a second region in a semiconductor substrate; forming a first body region having a high concentration of dopant in the first region to form a high-threshold voltage device; forming a second body region having a low concentration of dopant in the second region to form a low-threshold voltage device; forming a gate electrode over the first body region and the second body region; blanket implanting dopants of a second conductivity type into the first body and second body region to form low-doped drain (LDD) regions; forming a spacer next to the gate electrode; and source-drain implanting a second conductivity type of dopant to form a low-resistance source/drain region and low-doped extension that extends under the spacer, wherein the source-drain implantation comprises tilted and rotated implantation, and wherein the blanket implantation and the source-drain implantation are sufficient to compensate for enough of the first body region of the high-threshold voltage device, to ensure a low-resistance link between the source/drain region and a channel region.