Patent ID: 9721658
Date: 2017-08-01
CPC Classifications: G11C

Claim:
1. A memory device, comprising: a plurality of bit lines; plurality of memory elements coupled to the bit lines, each memory element including a memory layer formed between two electrodes, the memory layer being programmable between a plurality of different resistance states by creation and removal of conductive regions therein by application of electric fields; at least one sense amplifier (SA) configured to compare a first value, corresponding to a resistance state of a first memory element, to a second value, corresponding to a resistance state of a second memory element; bit line access devices configured to selectively connect bit lines to the at least one SA; charge circuits configured to charge selected bit lines to a predetermined voltage; and cell access devices configured to isolate the memory elements from the selected bit lines as the selected bit lines are being charged; wherein the cell access devices are further configured to connect one memory element to the selected bit lines after the selected bit lines have been charged.