Patent ID: 9712349
Date: 2017-07-18
CPC Classifications: H04L

Claim:
1. A clock data recovery (CDR) apparatus, comprising: an incremental feed forward equalizer (INC-FFE) in a CDR path; and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to repeatedly adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal until a one of the SNR and the BER has been obtained for each PC index in the PC index table, the calibration component further configured to calibrate the INC-FFE using values in the PC index table corresponding to the PC index for which a best SNR or a best BER was obtained, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.