Patent ID: 9632777
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A method for packed loading and storing of data distributed in a system that includes memory and a processing element, the processing element comprising a vector computation register file comprising a plurality of register file entries, each of the register file entries comprising a plurality of register file elements, and the processing element further comprising a scalar computation register file comprising a same number of register file entries as the vector computation register file, each register file entry of the scalar computation register file with one register file element, the method comprising: fetching and decoding an instruction for execution by the processing element, wherein the instruction comprises at least one sub-instruction accessing the vector computation register file and at least one sub-instruction accessing the scalar computation register file in parallel; distributing in each of at least two separate register file elements of a first register file entry of the register file entries of the vector computation register file, an address of one of a first plurality of non-contiguous locations in the memory of a plurality of data elements to gather; gathering, by the processing element based on the instruction and addresses, the data elements from the first plurality of non-contiguous locations in the memory, wherein each of the data elements is individually addressable and is narrower than a width of the register file elements of the vector computation register file in the processing element; and packing and loading the data elements into one or more of the register file elements of a second register file entry of the register file entries of the vector computation register file by the processing element based on the instruction, such that at least two of the data elements gathered from the first plurality of non-contiguous locations in the memory are packed and loaded into a single register file element of the second register file entry as a plurality of packed data elements in parallel with performing the at least one sub-instruction accessing the register file entries of the scalar computation register file.