Patent ID: 9641464
Date: 2017-05-02
CPC Classifications: H04L

Claim:
1. A first-in first-out (FIFO) buffer system comprising: a first storage partition comprising a single-port memory bank having an input to receive a clock signal, the first storage partition associated with a first subset of memory addresses, the first storage partition further comprises a first prefetch buffer having an input to receive the clock signal; a second storage partition comprising a single-port memory bank having an input to receive the clock signal, the second storage partition associated with a second subset of memory addresses; and FIFO control logic coupled to the first and second storage partitions and having an input to receive the clock signal, in response to a read access for data being received by the FIFO control logic during a clock cycle of the clock signal, the FIFO control logic to access and output the data from the first storage partition in a same clock cycle of the clock signal in which the read access for the data is received and while a write access to the first storage partition is received in the same clock cycle of the clock signal, to determine the first prefetch buffer contains valid data in response to a prefetch of first data completing before the same clock cycle, and to determine the first prefetch buffer does not contain valid data in response to the prefetch of the first data not completing before the same clock cycle, to access and output the data from the first storage partition by accessing and outputting data from the first prefetch buffer in response to determining the first prefetch buffer is storing valid data and by accessing and outputting data available at an output of the single-port memory bank of the first storage partition in response to determining the first prefetch buffer is not storing valid data.