Patent ID: 9640608
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method, comprising: forming a bottom electrode embedded in a first dielectric layer; forming a first recess in a second dielectric layer disposed above the first dielectric layer, the recess exposing at least a portion of the bottom electrode; forming a lower dielectric layer above the bottom electrode; forming a middle electrode in the recess above the lower dielectric layer and above a sidewall of the first recess; forming an upper dielectric layer in the first recess above the middle electrode; forming a third dielectric layer in the first recess; forming a second recess in the third dielectric layer, the second recess including a via opening exposing a portion of the bottom electrode; and forming a conductive material in the second recess to define a top electrode and to define a via coupling the top electrode to the bottom electrode.