Patent ID: 9601387
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method comprising: forming a p-type metal gate stack and a n-type metal gate stack, each surrounded by silicon nitride (SiN) spacers; forming an interlayer dielectric (ILD) surrounding the SiN spacers; planarizing the ILD, the p-type metal gate stack and n-type metal gate stack, and the SiN spacers; determining at least one desired threshold voltage for the p-type metal gate stack; forming a first cavity in the p-type metal gate stack for each desired threshold voltage and forming a second cavity in the n-type metal gate stack; selecting a first nitride layer for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity; forming the first nitride layer in respective first cavities; forming a second nitride layer, with a hydrogen rich reactive gas, in the second cavity; forming the first nitride layer in the second cavity to a thickness of 3 nanometers (nm) to 5 nm concurrently with forming each first nitride layer in each respective first cavity; and removing the first nitride layer from the second cavity, prior to forming the second nitride layers.