Patent ID: 9646988
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the plurality of electrode layers separately stacked each other, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided, the column extending in a stacking direction of the stacked body and including: a semiconductor film extending in the stacking direction, and a charge storage film provided between the semiconductor film and the plurality of electrode layers; and a plurality of insulating portions provided in the first step portion, and extending in the stacking direction; the stacked body including: a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.