Patent ID: 9564217
Date: 2017-02-07
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device, comprising: a semiconductor substrate having a main surface; at least a first dielectric layer on the main surface of the semiconductor substrate; a first oxide semiconductor field effect transistor (OS FET) device disposed on the first dielectric layer; a second OS FET device disposed on the first dielectric layer; at least a second dielectric layer covering the first dielectric layer, the first OS FET device, and the second OS FET device; a first metal-insulator-metal (MIM) capacitor on the second dielectric layer and electrically coupled to the first OS FET device, thereby constituting a dynamic oxide semiconductor random access memory (DOSRAM) cell, wherein the first MIM capacitor comprises a first bottom plate (BP) in a first capacitor trench, a first high-k dielectric layer on the first BP, and a first top plate (TP) on the first high-k dielectric layer; and a second MIM capacitor on the second dielectric layer and electrically coupled to the second OS FET device, thereby constituting a non-volatile oxide semiconductor random access memory (NOSRAM) cell.