Patent ID: 9608033
Date: 2017-03-28
CPC Classifications: H01L,H04N

Claim:
1. A method of manufacturing a solid-state image sensor which includes a pixel area where a plurality of pixels are arrayed and a peripheral circuit area where a circuit configured to read out a signal from the pixel area is arranged, the pixel area including a first MOS transistor, and the peripheral circuit area including a second MOS transistor, the method comprising: a step of forming a gate electrode of the first MOS transistor and a gate electrode of the second MOS transistor on a semiconductor substrate; a step of forming a first insulating film to cover the semiconductor substrate on which the gate electrode of the first MOS transistor and the gate electrode of the second MOS transistor have been formed; a first etching step of etching the first insulating film in the peripheral circuit area in a state in which the pixel area is masked so as to form a side spacer on a side face of the gate electrode of the second MOS transistor from a part of the first insulating film; a second etching step of etching the first insulating film in the pixel area in a state in which the peripheral circuit area is masked; and a step of forming, after the first etching step and the second etching step, the second insulating film to cover the semiconductor substrate on which the gate electrode of the first MOS transistor, the gate electrode of the second MOS transistor, and the side spacers have been formed.