Patent ID: 9570565
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting or doped semiconductor substrate, wherein the lateral semiconductor layers have different band gaps, wherein current can flow between source electrode contact areas and drain electrode contact areas upon application of a voltage between source and drain, wherein current intensity in a channel region between the source electrode contact areas and the drain electrode contact areas is controllable via gate electrode contact areas by means of a gate voltage, wherein a metalization of the source electrode contact areas, a metalization of the drain electrode contact areas and a metalization of the gate electrode contact areas are on a semiconductor surface of the semiconductor layers and have a plurality of metalization layers, between which insulation layers are arranged in a lateral direction, wherein the metalization layers both for the source electrode metalization and for the drain electrode metalization have a comb structure with contact fingers, wherein the contact fingers of the source electrode metalization and of the drain electrode metalization intermesh in a spaced-apart fashion and each contact finger has a contact finger foot and a contact finger tip, wherein a width of the contact finger foot is greater than a width of the contact finger tip.