Patent ID: 9728153
Date: 2017-08-08
CPC Classifications: G09G

Claim:
1. A display comprising: a pixel cell including a set terminal, a reset terminal, an output terminal, and a set/reset circuit coupled to receive a set signal via said set terminal and a reset signal via said reset terminal; and wherein said set/reset circuit responsive to receiving a set signal on said set terminal is operative to assert a first signal on said output terminal and to maintain said first signal on said output terminal until a reset signal is received on said reset terminal; said set/reset circuit responsive to receiving a reset signal on said reset terminal is operative to assert a second signal on said output terminal and to maintain said second signal on said output terminal until a set signal is received on said set terminal; and an optical output of said pixel depends on when said first signal and said second signal are asserted on said output terminal of said set/reset circuit during a predefined modulation period; and wherein said optical output of said pixel depends on multi-bit display data; and bits of said multi-bit display data are not written into said pixel cell.