Patent ID: 9570190
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse applying operation and a verification operation on the memory cell array; and a control logic configured to control the peripheral circuit to selectively perform a single sensing operation or a multi sensing operation during the verification operation, wherein the control logic further configured to: determine whether the verification operation is a last verification operation if a result of the verification operation is determined as pass, reset a target verification voltage if the verification operation is determined as not the last verification operation, and performing subsequent verification operation, based on the reset target verification voltage, wherein the control logic includes: a control signal generator configured to output control signals to control the peripheral circuit during the program pulse applying operation and the verification operation; a counter configured to output a count signal by counting the number of the program pulse applying operations or the verification operations; a comparator configured to compare the count signal with a set bit corresponding to a set number of times, and output a comparison signal whether the number of applied program pulses according to the program pulse applying operation or the number of applied verification voltages according to the verification operation is less than or equal to, or greater than the set number of times; and a determination part configured to determine a type of sensing operation during the verification operation based on the comparison signal, wherein the type of sensing operation includes the multi sensing operation and the single sensing operation, and the determination part configured to control the control signal generator.