Patent ID: 9640625
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method of forming a FinFET semiconductor device, the method comprising: forming a set of gate structures over a substrate; patterning a sacrificial layer to form a set of contact placeholders over a set of fins formed from the substrate; forming a barrier layer over the set of contact placeholders; depositing a fill material over the barrier layer; etching through the barrier layer atop each of the set of contact placeholders; etching a hard mask from the set of contact placeholders to expose the sacrificial layer; removing the sacrificial layer of the contact placeholders; removing an oxide over the set of fins to form the set of SD contact openings in the semiconductor device; patterning a lithography masking structure over the semiconductor device to form the gate contact opening over the at least one of the set of gate structures; forming a gate contact opening by etching an oxide over at least one of the set of gate structures; removing, selective to a metal stack of the at least one of the set of gate structures, the barrier layer and an interlayer fill material within the gate contact opening; removing the lithography masking structure from over the semiconductor device; forming a set of source/drain (S/D) contact openings in the semiconductor device by removing the sacrificial layer from atop the set of fins; and depositing a metal material over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings.