Patent ID: 9728543
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor structure, comprising: receiving a semiconductor substrate; forming a first dummy gate structure and a second dummy gate structure on the semiconductor substrate; forming a recess next to the first dummy gate structure and the second dummy gate structure and in the semiconductor substrate; forming a pair of first spacers adjacent to the first dummy gate structure and a pair of second spacers adjacent to the second dummy gate structure, one of the first spacers extending from a first sidewall of the first dummy gate structure to a first inner sidewall of the recess, and one of the second spacers extending from a second sidewall of the second dummy gate structure to a second inner sidewall of the recess; forming a first isolation layer on a bottom surface of the recess; and forming a first conducting layer on the first isolation layer.