Patent ID: 9728456
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method of forming an interconnect structure, comprising: forming an insulator stack on an upper surface of a semiconductor substrate, the insulator stack comprising a first insulator layer having at least one semiconductor device embedded therein, an etch stop layer interposed between the first insulator layer and a second insulator layer, and at least one electrically conductive local contact extending through the insulator stack to contact the at least one semiconductor device; selectively etching the second insulator layer to form at least one void that stops on an upper surface of the etch stop layer; filling the at least one void with an electrically conductive material to form at least one first layer contact element against a sidewall of the at least one electrically conductive local contact; forming a third insulator layer atop each of the second insulator layer, the at least one first layer contact element, and the at least one electrically conductive local contact; and forming at least one second metal layer element in the third insulator layer, the at least one second metal layer element including at least one electrically conductive via that connects a portion of the at least one second metal layer element to at least one of the at least one first layer contact element and the at least one electrically conductive local contact.