Patent ID: 9588155
Date: 2017-03-07
CPC Classifications: B60R,G01R

Claim:
1. A load current detection circuit for detecting a load current on a bus, the detection comprising: a transconductance circuit that converts a voltage across a sense resistor carrying the load current into an output current; a sample-and-hold circuit that samples the output current during a quiescent phase of the bus to produce a sample current, wherein the sample-and-hold circuit includes a first transistor with a first W/L dimension, wherein the first transistor is used to sample and hold the output current during the quiescent phase of the bus; a distortion-compensating circuit with a gain, for producing a compensation current that is a function of the sample current, wherein the distortion-compensating circuit includes a second transistor with a second W/L dimension different from the first W/L dimension, and a gate of the first transistor is connected to a gate of the second transistor in a current-mirror configuration; a combining circuit that combines the output current, the sample current, the compensation current, and a reference current representative of a threshold value for the load current to produce a combined current; and a discriminator, connected to the combining circuit, that generates a discriminator output having a first value when the combined current exceeds the threshold value and a second value, different from the first value, when the combined current is less than the threshold value.