Patent ID: 9696378
Date: 2017-07-04
CPC Classifications: G01R

Claim:
1. An integrated circuit having an output circuit comprising: a first data input; a second data input; a first data enable input; a second data enable input; a clock input lead; a data output; a first flip-flop having an input coupled with the first data input, a clock input coupled with the clock input lead, and an output; a second flip-flop having an input coupled with the second data input, a clock input coupled with the clock input lead, and an output; multiplexer circuitry having a first input coupled with the output of the first flip-flop, a second input coupled with the output of the second flip-flop, a control input coupled with the second data enable input, and an output; gating circuitry having a first input coupled with the first data enable input, a second input coupled with the second data enable input, and an output; and buffer circuitry having an input coupled with the output of the multiplexer circuitry, a control input coupled with the output of the gating circuitry, and an output coupled with the data output.