Patent ID: 9607689
Date: 2017-03-28
CPC Classifications: G11C

Claim:
1. A charging/discharging control method for a flash chip used in a solid hard disk, a physical page of the flash chip comprising a plurality of multi-layer memory cells, wherein the method comprises the steps of: mapping the physical page to two mutually coupled logic pages, wherein the two mutually coupled logic pages comprise a low-order logic page and a high-order logic page, the low-order logic page being formed by mapping a least significant bit of the plurality of multi-layer memory cells on the physical page to the low-order logic page, and the high-order logic page being formed by mapping a most significant bit of the plurality of multi-layer memory cells on the physical page to the high-order logic page; buffering write data, wherein the write data corresponds to at least one of the two mutually coupled logic pages, in a buffer memory; determining whether the write data corresponds to only one of the two mutually coupled logic pages or both of the two mutually coupled logic pages, determining if a timeout for the waiting period has occurred, performing charging/discharging control for the plurality of multi-layer memory cells on the physical page according to the merged data corresponding to the physical page, so that a voltage state of the plurality of multi-layer memory cells is expressed as a numerical value of the merged data corresponding to the physical page.