Patent ID: 9640240
Date: 2017-05-02
CPC Classifications: G11C

Claim:
1. A device comprising: a plurality of memory banks; a controller controlling storage of data in cells of the plurality of memory banks; a command decoder configured to provide an enable signal responsive to a partial access mode entry command signal; a partial access mode code decoder configured to receive the enable signal, to receive a portion of address signals responsive to the enable signal, to convert the portion of the address signals into a plurality of code flag signals, and further configured to provide a copy operation control signal and the plurality of code signals; and an address decoder circuit coupled to the controller, the address decoder circuit comprising: wherein the controller copies each bit of data stored in the plurality of memory banks that is to be preserved from 1 cell per bit to a plurality of cells per bit by a copy operation from the 1 cell connected with one word line to the plurality of cells connected with a plurality of respective word lines, wherein the switch is configured to receive a corresponding code flag signal of the plurality of code flag signals and further configured to simultaneously select the plurality of word lines responsive to the corresponding code flag signal, and wherein the switch is further configured to delay selection of the plurality of word lines responsive to the portion of address signals, further responsive to the corresponding code flag signal and the delay signal.