Patent ID: 9552871
Date: 2017-01-24
CPC Classifications: G06F,G11C,H01L

Claim:
1. A memory circuit comprising: a plurality of p-channel Metal-Oxide-Semiconductor (MOS) transistors; a p-channel source connection that connects the source terminals of said p-channel MOS transistors; a p-channel substrate connection that connects the substrate terminals of said p-channel MOS transistors; a plurality of n-channel MOS transistors; an n-channel source connection that connects the source terminals of said n-channel MOS transistors; an n-channel substrate connection that connects the substrate terminals of said n-channel MOS transistors; and a power saving mode control circuit that controls voltage differences (Vpb−Vps) and (Vns−Vnb), where the voltage difference (Vpb−Vps) is the voltage difference between the voltage (Vpb) on the p-channel substrate connection and the voltage (Vps) on the p-channel source connection, and the voltage difference (Vns−Vnb) is the voltage difference between the voltage (Vns) on the n-channel source connection and the voltage (Vnb) on the n-channel substrate connection; wherein the power saving mode control circuit is able to control the memory circuit to operate in a power saving mode where the voltage difference (Vps−Vns) under said power saving mode is higher than the threshold voltages of the n-channel MOS transistors, and the voltage differences (Vpb−Vps) and (Vns−Vnb) are both set at positive values so that a standby leakage current flowing from the p-channel source connection to the n-channel source connection of the memory circuit under said power saving mode is reduced by at least 80% relative to the standby leakage current flowing from the p-channel source connection to the n-channel source connection of the same memory circuit under normal operation mode, where “normal operation mode” is defined as the operation condition when the voltage differences (Vpb−Vps) and (Vns−Vnb) are both set to zero.