Patent ID: 9673961
Date: 2017-06-06
CPC Classifications: H04L

Claim:
1. An apparatus comprising: means for receiving a first sequence of symbols from a first lane of a multi-lane interface, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the first lane; means for recovering a clock signal from the multi-lane interface, wherein the means for recovering the clock signal includes a circuit configured to generate edges in the clock signal corresponding to transitions in the signaling state of the N wires between pairs of consecutive symbols in the first sequence of symbols; means for converting the first sequence of symbols to a first set of data bits using the clock signal, including a transcoder adapted to convert the first sequence of symbols to a set of transition numbers and to convert the set of transition numbers to the first set of data bits; and means for deriving a second set of data bits from one or more signals received from a second lane of the multi-lane interface using the clock signal.