Patent ID: 9634114
Date: 2017-04-25
CPC Classifications: B82Y,H01L

Claim:
1. A method of manufacturing a tunnel field effect transistor comprising: growing a group III-V compound semiconductor nanowire on a (111) surface of a portion of a first conductivity type of a group IV semiconductor substrate, the first conductivity type being one of n-type and p-type; forming a gate electrode configured to apply an electric field for controlling flow of a carrier between a source electrode and a drain electrode to an interface between the group IV semiconductor substrate and the group III-V compound semiconductor nanowire; forming one of the source electrode and the drain electrode on the group IV semiconductor substrate such that the one of the source electrode and the drain electrode is not in contact with the group III-V compound semiconductor nanowire; and forming the other of the source electrode and the drain electrode on the group III-V compound semiconductor nanowire, wherein: the growing further includes: