Patent ID: 9620524
Date: 2017-04-11
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a gate of a TFT and a gate insulating layer formed on a surface of a base substrate, and the gate being formed between the substrate and the gate insulating layer; a semiconductor active layer, an etching stop layer, a source and a drain of the TFT sequentially formed on a surface of the gate insulating layer that corresponds to the gate of the TFT, the source and the drain contacting the semiconductor active layer through vias respectively; the array substrate further comprising: a shielding electrode formed between the gate of the TFT and the base substrate; and an insulating layer formed between the gate of the TFT and the shielding electrode; wherein an overlapping area of vertical projections of the gate and the source on the array substrate is smaller than an overlapping area of vertical projections of the shielding electrode and the source on the array substrate; and/or an overlapping area of vertical projections of the gate and the drain on the array substrate is smaller than an overlapping area of vertical projections of the shielding electrode and the drain on the array substrate, and wherein the shielding electrode is made of conductive material and a capacitance is generated between the gate and the shielding electrode and a length of the shielding electrode in a direction in which the source is opposite to the drain is shorter than a length of the gate in the direction in which the source is opposite to the drain.