Patent ID: 9735182
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method for manufacturing an array substrate including a step of forming data lines, scan lines, and a light shielding metal layer on a substrate and a step of forming thin film transistors on the substrate, forming the thin film transistor includes a step of forming a gate electrode, a source electrode, a drain electrode, and an active region, both the thin film transistors and the light shielding metal layer are formed in a plurality of pixel regions defined by the scan lines and the data lines, wherein the light shielding metal layer and the data lines are formed along a direction parallel to a surface of the substrate in a same layer on the substrate in a single step, and are arranged with an interval therebetween on the substrate, the data lines being arranged under the active region, the light shielding metal layer is formed under the active region and at least partially overlaps with the active region in a projection direction, the data line is close to the source electrode and does not overlap with the active region at least partially in the projection direction.