Patent ID: 9735268
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a gate structure on a channel region of a substrate, wherein a source region and a drain region are on opposing sides of said channel region of said substrate; a first metal semiconductor alloy present on an upper surface of at least one of said source region and said drain region, wherein said first metal semiconductor alloy extends to a sidewall of said gate structure; a dielectric layer over said gate structure and said first metal semiconductor alloy, wherein an opening is present through said dielectric layer to a portion of said first metal semiconductor alloy that is separated from said gate structure; and a second metal semiconductor alloy that is present in said opening and in direct contact with said first metal semiconductor alloy, wherein said second metal semiconductor alloy has an upper surface that is vertically offset and located below said upper surface of said first metal semiconductor alloy, and wherein said second metal semiconductor alloy has outer edges that are vertically coincident to sidewall surfaces of said opening.