Patent ID: 9627334
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method of forming an integrated circuit, comprising; forming an interconnect region; forming a top interconnect level in the interconnect region, so that the top interconnect level includes a connection pad; forming a dielectric layer over the top interconnect level; forming a connection opening in the dielectric layer such that a portion of a top surface of the connection pad is exposed, while the dielectric layer overlaps a periphery of the connection pad, and such that a connection opening sidewall is formed at a boundary of the dielectric layer over the connection pad; forming an under bump metal layer on the exposed portion of the top surface of the connection pad and over the dielectric layer, such that the under bump metal layer contacts the connection opening sidewall; selectively removing material from the under bump metal layer over the dielectric layer so as to form a self-aligned under bump metal pad, such that the self-aligned under bump metal pad contacts the connection opening sidewall, and such that the self-aligned under bump metal pad does not contact a top surface of the dielectric layer; and forming a solder ball on a top surface of the self-aligned under bump metal pad.