Patent ID: 9542167
Date: 2017-01-10
CPC Classifications: G06F

Claim:
1. A method of assessing performance of one or more non-native instructions executing on a computing system having a native instruction set architecture, the one or more non-native instructions incapable of native execution on the computing system, wherein emulated execution of the one or more non-native instructions simulates execution of a second computing system having a second native instruction set architecture different from and incompatible with the native instruction set architecture, the method comprising: during emulated execution of non-native program code including non-native instructions: maintaining a program flow history in the computing system representing a flow of program execution of the non-native program code, the program flow history including a jump storage captured from a state of a jump table defined in the non-native instruction set architecture and including a listing of non-native jump instructions for which execution is emulated in the computing system; and capturing one or more statistics regarding performance in native execution of the non-native program code on the computing system; reconstructing an instruction trace based on the program flow history; and correlating the one or more statistics to the program flow history to determine performance of the computing system in executing one or more non-native instructions included in segments of the instruction trace between each of the non-native jump instructions.