Patent ID: 9542985
Date: 2017-01-10
CPC Classifications: G06F,G11C,H03K,Y02D

Claim:
1. An apparatus, comprising: a memory device with a receiver component; a controller associated with a plurality of memory channels, each of the plurality of memory channels having a respective group of data signals and a respective channel clock signal associated therewith; at least one delay component coupled to the controller and configured to, based on a reference clock signal, provide a skew amount to at least one of the channel clock signals such that the at least one of the channel clock signals is out of phase with respect to the channel clock signal of at least one different memory channel; wherein the controller is configured to transmit the respective channel clock signals along with their respective associated data signals to the receiver component in a source-synchronous manner; and wherein the receiver component does not de-skew the respective associated data signals; and wherein the skew amount is provided to the at least one of the channel clock signals such that groups of data signals of every other channel are skewed by a same amount.