Patent ID: 9690505
Date: 2017-06-27
CPC Classifications: G06F,G11C

Claim:
1. A device, comprising: a table to store a plurality of row addresses, including first and second row addresses, of a memory; a plurality of counters including first and second counters, each of the counters to correspond to one of the row addresses of the table; a row unit to determine if an activated row address of the memory is included in the table; a counter unit to increment at least one of the first counter of the first row address and the second counter of the second row address, if the activated row address is not included in the table; and a refresh unit to refresh at least one of the first and second row addresses if at least one of the first and second counters exceeds a counter threshold, wherein at least one the first and second row addresses are adjacent to the activated row address.