Patent ID: 9672917
Date: 2017-06-06
CPC Classifications: G11C,H01L

Claim:
1. An apparatus, comprising: a first NAND string, the first NAND string includes a first drain-side select gate, a first set of memory cell transistors, and a first source-side select gate; and a second NAND string arranged below the first NAND string, the second NAND string includes a second drain-side select gate and a second set of memory cell transistors, the second NAND string includes a second source-side select gate, a source of the second source-side select gate is connected to a source of the first source-side select gate during a memory operation, the first set of memory cell transistors comprises a first number of transistors and the second set of memory cell transistors comprises a second number of transistors different from the first number of transistors, the first NAND string comprises a first vertical NAND structure that comprises one of a single vertical NAND string or a pipe-shaped vertical NAND string, the second NAND string comprises a second vertical NAND structure that comprises one of the single vertical NAND string or the pipe-shaped vertical NAND string, the first vertical NAND structure is different from the second vertical NAND structure.