Patent ID: 9595479
Date: 2017-03-14
CPC Classifications: A61B,B81B,B81C,G01L,G01P,H01L,H03H

Claim:
1. A method for fabricating a three-dimensional integrated circuit device, the method comprising: providing a first substrate having a first crystal orientation; forming at least one or more PMOS devices overlying the first substrate; forming a first dielectric layer overlying the one or more PMOS devices; providing a second substrate having a second crystal orientation; forming at least one or more NMOS devices overlying the second substrate; forming a second dielectric layer overlying the one or more NMOS devices; and coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate; forming a third dielectric layer overlying the hybrid structure; and forming a pressure sensing device overlying the third dielectric layer, wherein forming the pressure sensing device comprising: