Patent ID: 9671456
Date: 2017-06-06
CPC Classifications: G01R,H01L

Claim:
1. A method of analysing a performance of a functional circuit on a semiconductor device arrangement that includes a functional circuit comprising a plurality of timing components, a reference module comprising a plurality of reference components, each reference component comprising a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component, the controllable timing component being arranged to provide a delay in dependence on an applied light stimulus, the method comprising: operating the functional circuit of the semiconductor device arrangement with an operation condition; inspecting the functional circuit during operation to identify a critical timing path and to identify at least one of the plurality timing components as a critical timing component on the critical timing path; identifying one of the plurality of reference components to correspond to the critical timing component as a representative reference component; operating the representative reference component with at least a reference operation condition corresponding to the operation condition of the functional circuit; applying a plurality of light stimuli to the representative reference component; and determining a timing behaviour of the representative reference component in dependence on at least the reference operating condition and the plurality of light stimuli.