Patent ID: 9740486
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A method for processing instructions in a processor core that includes an architecture with an even execution slice having an even physical register file and an odd execution slice having an odd physical register file, the even and odd execution slices each configured to perform operations specified in a first set of instructions on data from its respective physical register file, and together configured to perform operations specified in a second set of instructions on data stored across both the even and odd physical register files, the method comprising: receiving a first instruction specifying an operation, a target register, and at least one source register, the first instruction being of the first set of instructions; identifying a second instruction upon which content of the at least one source register depends; determining that the second instruction is of the second set of instructions; dispatching, in response to the determining, the first instruction to the even execution slice; performing, using the even execution slice, the operation using content of the at least one source register in the even physical register file to produce a result; writing a first copy of the result to the target register in the even physical register file; writing a second copy of the result to the target register in the odd physical register file; setting an indicator; receiving a third instruction specifying a second set of operations, and a second at least one source register, the second at least one source register being the target register; determining that the third instruction is of the second set of operations; dispatching, in response to the determining that the third instruction is of the second set of operations, the third instruction to the even execution slice and the odd execution slice; detecting that the indicator is set; treating, in response to the detecting, content of the second at least one source register in the odd physical register file as an undefined value for the purposes of the second operation, the content of the second at least one source in the odd physical register file being the second copy of the result; and performing, using the even execution slice and the odd execution slice, the second operation using content of the second at least one source register in the even physical register file and the undefined value to produce a second result.