Patent ID: 9646979
Date: 2017-05-09
CPC Classifications: G11C,H01L

Claim:
1. A non-volatile semiconductor memory device comprising a memory cell including a memory transistor having a single-layer gate structure having a floating gate and a switch transistor having a single-layer gate structure having a switch gate electrode, wherein the memory cell has a configuration in which a source line is connected to one end of the memory transistor, a bit line is connected to one end of the switch transistor, and the other end of the memory transistor and the other end of the switch transistor are electrically connected in series to each other, and the memory transistor includes: a high-resistance region between a region below the floating gate and a source-drain region at the other end, wherein a resistance value of the high-resistance region is higher than a resistance value between the region below the floating gate and a source-drain region at the one end; and extension regions respectively formed on both sides of the region below the floating gate, wherein a low-concentration impurity extension region having a lower impurity concentration than that of the extension region at the one end is formed as the high-resistance region.