Patent ID: 9613906
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method for fabricating an integrated circuit, the method comprising: providing a liner on a porous interlayer dielectric (ILD) layer of dielectric material with a conductive metal fill overlying the liner and a protective cap overlying the conductive metal fill while leaving adjacent portions of the porous ILD layer that are adjacent to the protective cap exposed and having exposed surfaces; thereafter, contacting the liner that is disposed adjacent to the porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions effective to react a portion of the liner with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer, wherein the exposed surfaces of the adjacent portions are exposed to the selectively reactive gas to contact the liner with the selectively reactive gas.