Patent ID: 9641194
Date: 2017-05-02
CPC Classifications: H03M

Claim:
1. An encoder for encoding BCH codes of different modes, comprising: a combined matrix unit, for providing a plurality of encoding matrices for multiplying elements from the encoding matrices with one input data having p bits, and outputting the results as a calculated data in a first clock cycle; a linear feedback shift register (LFSR), for linearly shifting the calculated data as an output data, and outputting the output data in a second clock cycle; and an adder, for adding the output data received from the LFSR and a divided processing data having p bits, and outputting the sum as another input data to the combined matrix unit in the second clock cycle, wherein an n-bit initial processing data including a k-bit message and being divided per p bits is sequentially inputted to the adder as the divided processing data; an encoded codeword is obtained in [n/p] clock cycles; the second clock cycle is one clock cycle later than the first clock cycle.