Patent ID: 9720825
Date: 2017-08-01
CPC Classifications: G06F,G11C

Claim:
1. A method comprising: determining, by a processor, that a plurality of dual inline memory modules are populated non-symmetrically across a plurality of memory channels; dividing, by the processor, the dual inline memory modules by bank to create a plurality of interleave groups, wherein each of the interleave groups spans across all of the memory channels, and consecutive accesses to a single interleave group are to banks of different dual inline memory modules on different memory channels; dividing all of the dual inline memory modules of a first type by bank to create a plurality of interleave groups, wherein each of the interleave groups that include the dual inline memory modules of the first type spans across all of the memory channels; and creating a separate interleave group for a first dual inline memory module of the dual inline memory modules in response to the first dual inline memory module being a second type of dual inline memory module.