Patent ID: 9673163
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip orientation on the insulating substrate and including a semiconductor substrate; a source pad electrode and a gate pad electrode disposed face down on a surface of the semiconductor substrate; and a drain pad electrode disposed face up on a back side surface of the semiconductor substrate; a gate connector disposed on the gate pad electrode; a source connector disposed on the source pad electrode; wherein the material of the gate pad electrode and the material of the gate connector are the same, and the material of the source pad electrode and the material of the source connector are the same; a gate bonding layer configured to bond between the gate connector and the gate pad electrode, and a gate connector bonding layer configured to bond between the gate connector and the signal wiring electrode; and a source bonding layer configured to bond between the source connector and the source pad electrode, and a source connector bonding layer configured to bond between the source connector and the power wiring electrode, wherein the gate bonding layer, the gate connector bonding layer, the source bonding layer, and the source connector bonding layer are respectively structured of one kind of metal comprising one of a group consisting of Ag, Au, Ti, Ni, Al, and Cu; the gate bonding layer, the gate connector bonding layer, the source bonding layer, and the source connector bonding layer are bonding layers respective configured to bond between a same one kind of metals selected from a group consisting of Ag, Au, Ti, and Ni; the interface between the bonding metallic material of the gate connector and the bonding metallic material of the gate pad electrode is seamless, and the interface between the bonding metallic material of the source connector and the bonding metallic material of the source pad electrode is seamless; and the gate bonding layer is a layer separate from the gate pad electrode and the gate connector, and the source bonding layer is a layer separate from the source pad electrode and the source connector.