Patent ID: 9564215
Date: 2017-02-07
CPC Classifications: G11C

Claim:
1. A non-volatile memory system, comprising: a bay of non-volatile storage elements configured for programming in a plurality of column address cycles, wherein the bay includes a first group of non-volatile storage elements associated with a plurality of columns and a second group of non-volatile storage elements associated with the plurality of columns; a first sense amplifier circuit associated with the first group of non-volatile storage elements of the bay, wherein the first sense amplifier circuit is configured to program in a first column address cycle a second non-volatile storage element of the first group having a second column address in response to determining that the second non-volatile storage element should be programmed and a first non-volatile storage element of the first group having a first column address can be skipped; and a second sense amplifier circuit associated with the second group of non-volatile storage elements of the bay, wherein the second sense amplifier circuit is configured to program in the first column address cycle a first non-volatile storage element of the second group having the first column address in response to determining that the first non-volatile storage element of the second group should be programmed.