Patent ID: 9575897
Date: 2017-02-21
CPC Classifications: G06F

Claim:
1. A method, comprising: in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions comprise symbolic expressions that specify memory addresses in an external memory in terms of one or more register names; identifying, based on the symbolic expressions of the memory addresses, a sequence of load instructions that access the external memory; further identifying, based on the symbolic expressions of the memory addresses, that the load instructions in the sequence will access a predictable pattern of different memory addresses in the external memory, wherein both the sequence of the load instructions and the predictable pattern are identified independently of numerical values of the memory addresses; in response to a given load instruction in the sequence, and before processing subsequent load instructions in the sequence, retrieving from the external memory at least one cache line that comprises a plurality of data values; saving from the cache line to an internal memory, based on the predictable pattern, the data values that will be requested by the given load instruction and by the subsequent load instructions in the sequence; and assigning the saved data values to be served from the internal memory to one or more instructions that depend on the given load instruction or on the subsequent load instructions.