Patent ID: 9673205
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A nonvolatile memory, comprising: at least two gate stacks located on a substrate, wherein the two gate stacks each from bottom to top sequentially comprise: a tunneling oxide layer, a floating gate, a middle dielectric layer, a control gate, and a mask layer; first spacers located on sidewalls of the two gate stacks; a gate dielectric layer located on an exposed surface of the substrate; an erase gate located between the two gate stacks and having a nonplanar top surface not higher than top surfaces of the control gates; two word lines located on outer sides of the two gate stacks and having nonplanar top surfaces not higher than the top surfaces of the control gates; cap layers located respectively on the erase gate and the word lines; and a first buffer layer disposed between the erase gate and at least one of the cap layers.