Patent ID: 9640644
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: an N-type semiconductor substrate; a plurality of trenches in an upper surface of the N-type semiconductor substrate; a gate trench in the trench with an insulating film interposed therebetween; a planar MOSFET on the upper surface of the N-type semiconductor substrate in a mesa portion between the trenches; a P-type emitter layer between the trench and the planar MOSFET in a lateral direction of the trench in planar view perpendicular to the upper surface of the N-type semiconductor substrate in the mesa portion; and a P-type collector layer on a lower surface of the N-type semiconductor substrate, wherein the planar MOSFET includes an N-type emitter layer, an upper portion of the N-type semiconductor substrate, a P-type base layer between the N-type emitter layer and the upper portion of the N-type semiconductor substrate, and a planar gate on a part of the N-type emitter layer, the upper portion of the N-type semiconductor substrate and the P-type base layer with a gate insulating film interposed therebetween, the planar gate is connected to the gate trench, the P-type emitter layer has a higher impurity concentration than the P-type base layer and has an electric potential equal to an emitter potential of the N-type emitter layer, the P-type emitter layer is provided between the N-type emitter layer and the trench and between the P-type base layer and the trench, the N-type emitter layer and the P-type base layer are not in contact with the insulating film in the trench, and a trench MOSFET is not formed.