Patent ID: 9711628
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first conductivity type first semiconductor layer; a first trench provided to a predetermined depth in a depth direction from one principal surface of the first semiconductor layer; a gate electrode provided in the inner portion of the first trench via a first insulating film; a second conductivity type first semiconductor region provided in the surface layer of the one principal surface of the first semiconductor layer so as to have a depth shallower than that of the first trench and to be in contact with the first insulating film provided on the sidewall of the first trench; a first conductivity type second semiconductor region provided in an inner portion of the first semiconductor region; a second conductivity type third semiconductor region provided, spaced from the first semiconductor region, in the surface layer of the one principal surface of the first semiconductor layer; one of (a) a first conductivity type fourth semiconductor region that has an impurity concentration that is higher than that of the first semiconductor layer, or (b) a second conductivity type fourth semiconductor region that has an impurity concentration that is lower than that of the third semiconductor region, and that is provided in the surface layer of the one principal surface of the first semiconductor layer so as to be in contact with the first semiconductor region and third semiconductor region; a second insulating film covering the fourth semiconductor region; a first electrode provided in contact with the first semiconductor region and the second semiconductor region and on the top of the second insulating film; a second conductivity type second semiconductor layer provided on another principal surface of the first semiconductor layer; and a second electrode in contact with the second semiconductor layer.