Patent ID: 9729171
Date: 2017-08-08
CPC Classifications: G06F,G11C,H03M

Claim:
1. An apparatus comprising: a communication link; and a controller to receive read or write commands for a memory system via the communication link, the controller to execute logic, at least a portion of which is in hardware, the logic to: receive error correction code (ECC) information for ECC encoded data stored in the memory system that indicates a failure to correct one or more bit errors from a plurality of bit errors in the ECC encoded data; identify a low confidence portion of the ECC encoded data that has a lowest probability of error free bits compared to one or more other portions of the ECC encoded data, the low confidence portion to include r bits; flip individual bit values for k bits of the r bits included in the low confidence portion; cause the ECC encoded data to be decoded based on a combinatorial operation that results in a plurality of separate decodes of the ECC encoded data following the flip of the individual bit values for k bits; and determine that one or more separate decodes of the ECC encoded data were able to correct the plurality of bit errors and identify decoded data for these one or more separate decodes as one or more successful decodes of the ECC encoded data.