Patent ID: 9633160
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A computer-implemented method, comprising: a. receiving an instruction adapted for execution by a dynamically reconfigurable processor: b. accessing a software model of the plurality of homogeneous logic elements of a dynamically reconfigurable computer architecture, the software model comprising a plurality of cells and representing the interconnectivity of the plurality of cells, each cell modeling one of the logic elements of the plurality of homogeneous logic elements, wherein a first cell models the first logic element and a second cell models the second logic element: c. in accordance with the instruction, attempting to route a first notional simulated signal route in the software model from the first cell to the second cell by assigning a first selection of cells of the plurality of cells to the notional signal route: d. detecting a failure to successfully route in the software model the first notional signal route through the first selection of cells of the plurality of cells from the first cell to the second cell; e. ripping up all assigned intervening cells until routing to the second cell is possible; f. leaving a third cell of the reconfigurable logic unit uncommitted at a simulated location within the software model; g. retrying the placement of the plurality of cells and routing from the most recently ripped up cell at the next available simulated cell location; and h. sequentially repeating the procedure of steps a through f until a notional signal route is successfully routed in the software model from the first cell to the second cell.