Patent ID: 9564206
Date: 2017-02-07
CPC Classifications: G11C

Claim:
1. A semiconductor device comprising: a verification circuit that sets an error signal to an active level in response to the presence of an error in write data comprising a plurality of bits; a latch circuit that latches a data mask signal in response to a first timing signal and changes said latched data mask signal to an active level in response to said error signal being active-level; a buffer circuit that outputs said data mask signal that was latched in said latch circuit in response to a second timing signal; and a main amplifier that outputs said write data to an internal circuit under the condition that said data mask signal that was output from said buffer circuit is an inactive level; wherein said first timing signal is activated prior to actuation of said second timing signal, said second timing signal is activated after the level of said error signal has been established, and no other latch circuit that performs latching operation synchronized with at least said first timing signal is interposed between said latch circuit and said buffer circuit.