Patent ID: 9571111
Date: 2017-02-14
CPC Classifications: H03L

Claim:
1. A phase lock loop (PLL) calibration apparatus for phased lock loop (PLL) circuit having a voltage controlled oscillator (VCO) providing an output frequency, said apparatus comprising: a logic circuit for setting an initial frequency band value for use in prior calibrating a PLL circuit, and iteratively incrementing said frequency band value settings for said prior PLL circuit calibrating until achieving a PLL circuit lock condition at a particular operating frequency; and a memory storage device operably coupled to said logic circuit for storing said frequency band value setting used for achieving said PLL circuit lock condition at the particular operating frequency, a reset signal received at said logic circuit for triggering a new PLL circuit calibration at said particular operating frequency; a fast calibration signal received at said logic circuit and asserted to directly forward said stored frequency band value setting stored in said memory storage device to said VCO for said new PLL circuit calibration, wherein said VCO uses said frequency band value setting from the prior PLL calibration stored in said memory storage device as said initial frequency for said new PLL circuit calibration, wherein the PLL lock in said new calibration is achieved in a reduced amount of time.