Patent ID: 9690649
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A system for classifying memory errors comprising a computing device having a processor and a memory system, the memory system further comprising: a memory controller configured to access data from a location within a memory array; a memory device that includes at least one bit field to store memory error classification information within the memory array; an ECC decoder configured to determine that there are one or more memory errors in the data; a history bit circuitry module configured to classify the one or more memory errors, wherein the classifying the one or more memory errors includes determining whether the one or more memory errors is a correctable memory error or an uncorrectable memory error, the history bit circuitry module being further configured to: wherein the history bit circuitry module is further configured to store, in response to the classifying, memory error classification information as one or more bit values within the bit field.