Patent ID: 9548736
Date: 2017-01-17
CPC Classifications: H03K

Claim:
1. A counter circuit comprising a relative timed clock gating cell, the counter circuit further comprising: at least one two-bit shift register configured as a ring counter including a first latch and a logic component, wherein the logic component is a second latch or an inverter, a clock input for the first latch and is coupled to a trigger line for transmitting a trigger signal, an output of the first latch and an output of the logic component have opposite values, the output of the logic component provides an input to the first latch and is configured to generate a data clock signal, and the trigger signal is based on a clock signal; a counter cell coupled to the output of the logic component of a last stage two-bit shift register, wherein the counter cell increments on an edge of the data clock signal, and the counter cell is a smaller bit counter than bits counted by the counter circuit.