Patent ID: 9589671
Date: 2017-03-07
CPC Classifications: G06F,G11C

Claim:
1. A memory self-testing device, for testing a plurality of memory control units, comprising: a test control unit, coupled to the memory control units, generating a plurality of access request signals and a plurality of sets of data; a channel control unit, coupled to the test control unit and the memory control units, determining a leading feedback signal among a plurality of feedback signals, the feedback signals being generated by the memory control units in response to the access request signals; and a data control unit, coupled to the test control unit and the memory control units, storing the sets of data, and transmitting the sets of data to the memory control units according a plurality of read/write signals, the read/write signals being generated by the memory control units in response to the access request signals; wherein, the test control unit generates the sets of data according to the leading feedback signal.