Patent ID: 9733945
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. A method comprising: determining an instruction chain comprising at least a first instruction having a first latency and a second instruction having a second latency, the first latency and the second latency each being less than a third latency of a third instruction; submitting the instruction chain to a first execution pipeline of a processor and the third instruction to a second execution pipeline of the processor, wherein execution of the instruction chain at least partially overlaps execution of the third instruction; writing a result of the instruction chain to a register file during one of a writeback slot of the second instruction or a write back slot of the third instruction; determining whether the second instruction is dependent on data from the first instruction; and in response determining that the second instruction is dependent on data from the first instruction, forwarding the data from the first instruction to the second instruction.