Patent ID: 9729415
Date: 2017-08-08
CPC Classifications: H04L

Claim:
1. A controller area network (CAN) node suitable for use in a ring redundant CAN network topology that includes a master CAN node N 0 and N ring CAN nodes Nn (n=1, 2, . . . N, where N is at least 3), interconnected in a ring topology by N+1 CAN bus segments, with bus segment CAN( 1 ) connecting master CAN node N 0 to ring CAN node N 1 , bus segment CAN(N) connecting ring CAN node N(n−1) to ring CAN node Nn, and bus segment CAN(N+1) connecting the last ring CAN node NN to master CAN node N 0 , each ring CAN node Nn comprising: redundant CAN PHY An and CAN PHY Bn physical layer circuits, (n=1, 2, . . . N, where N is at least 3), to respectively interface to CAN bus segments CAN(N) and CAN(N+1); the CAN PHY An and Bn circuits each including a TXD (transmitter dominant) circuit and a RXD (receiver dominant) circuit; the CAN PHY Bn TXD circuit to transmit over a respective CAN(N) bus segment a TXD data signal with differential CAN dominant/recessive states; the CAN PHY Bn RXD circuit to monitor the respective CAN(N) bus segment, and generate an internal RXD signal corresponding to dominant and recessive states of the monitored CAN(N) bus segment; and the CAN PHY An TXD circuit to transmit over a respective CAN(N+1) bus segment a TXD data signal with differential CAN dominant/recessive states; the CAN PHY An RXD circuit to monitor the respective CAN(N+1) bus segment, and generate an internal RXD signal corresponding to dominant and recessive states of the monitored CAN(N) bus segment; and each RXD circuit including an RXD DTO (dominant time out) circuit configured to monitor the internal RXD signal, and detect a DTO stuck-dominant condition if the internal RXD signal is in a dominant state for greater than a pre-defined DTO stuck-dominant time-out period, and operable TXD An and Bn logic combiner circuits with respective TXD outputs connected respectively to the CAN PHY An and Bn circuits, to logically combine a common TXD data signal and the intermediate RXD signal cross-coupled from respectively the CAN PHY Bn and An RXD circuits, and generate a resulting TXD signal for input respectively to the CAN PHY An and Bn circuits; an RXD logic combiner circuit to logically combine respective intermediate RXD signals from respective CAN PHY A and CAN PHY B circuits, and generate a resulting RXD signal; a controller to