Patent ID: 9627403
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A monolithic three-dimensional memory device comprising: a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate; an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the lower stack structure; an etch stop dielectric layer located within the lower stack structure and overlying the first stack of alternating layers and contacting a bottom surface of the upper stack structure and comprising a dielectric material having a different composition than the first electrically insulating layers; a plurality of memory stack structures including respective vertical semiconductor channels, wherein a bottommost portion of each vertical semiconductor channel is electrically shorted to a source region located below the lower stack, and an upper portion of each vertical semiconductor channel is electrically shorted to a drain contact via structure overlying the vertical semiconductor channel; and at least one support pillar structure located within a stepped surface region of the lower and upper stack structures, comprising a same set of materials as the plurality of memory stack structures.