Patent ID: 9583217
Date: 2017-02-28
CPC Classifications: G06F,G11C,H03M

Claim:
1. A decoding method for a rewritable non-volatile memory module comprising a plurality of memory cells, and the decoding method comprising: reading the memory cells according to at least one hard decision voltage to obtain at least one hard bit, wherein the at least one hard bit comprises a first hard bit: performing a parity checking procedure for the at least one hard bit to obtain a plurality of syndromes, wherein each of the at least one hard bit is corresponding to at least one of the syndromes; determining whether the at least one hard bit has at least one error according to the syndromes; if the at least one hard bit has the at least one error, updating the at least one hard bit according to channel information of the at least one hard bit and syndrome weight information corresponding to the at least one hard bit, wherein the step of updating the at least one hard bit according to the channel information of the at least one hard bit and the syndrome weight information corresponding to the at least one hard bit comprises: determining whether first syndrome weight information corresponding to the first hard bit among the syndrome weight information matches a weight condition: if the first syndrome weight information matches the weight condition, determining whether the channel information of the first hard bit matches a channel condition; if the channel information of the first hard bit matches the channel condition, updating the first hard bit; and if the channel information of the first hard bit does not match the channel condition, not updating the first hard bit; and if the at least one hard bit does not have the at least one error, outputting the at least one hard bit.