Patent ID: 9594680
Date: 2017-03-14
CPC Classifications: G06F

Claim:
1. A computer-implemented method for identifying stale entries within an address translation cache, the method comprising: running, by a computing device, a first test case, the first test case to determine which particular set of physical addresses a first set of virtual addresses are mapping to, the running of the first test case including determining that the first set of virtual addresses are mapped to a first set of physical addresses; changing, by the computing device, a mapping in a page table stored in memory, the page table mapping the first set of virtual addresses, for a set of data, to the first set of physical addresses, the changing of the mapping including mapping the first set of virtual addresses to a second set of physical addresses, wherein the changing a mapping includes adding an offset quantity of bits to the first set of physical addresses; executing, by the computing device and in response to the changing of the mapping, one or more flush operations to invalidate one or more entries within one or more Translation Lookaside Buffer (TLB) address translation caches, the one or more entries corresponding to the first set of physical addresses, the TLB address translation caches being buffers within a processor that maps virtual addresses to physical addresses for address translation; running, by the computing device and in response to the executing of the one or more flush operations, a second test case, the second test case to test whether any of the first set of virtual addresses are mapping to the first set of physical addresses; determining, by the computing device and based on the second test case, that at least one of the first set of virtual addresses are mapping to at least one of the first set of physical addresses; determining, by the computing device and based on comparing the first test case with the second test case, that at least one of the one or more entries were not invalidated by the one or more flush operations; running, by the computing device, a third test case, the third test case to determine which particular set of virtual addresses a first set of effective addresses are mapping to, the running of the third test case including determining that the first set of effective addresses are mapped to a second set of virtual addresses; changing, by the computing device, a mapping in a segment table stored in the memory, the segment table mapping the first set of effective addresses, for a second set of data, to the second set of virtual addresses, the changing of the mapping including mapping the first set of effective addresses to a third set of virtual addresses, wherein the changing a mapping in the segment table includes adding an offset quantity of bits to the second set of virtual addresses; executing, by the computing device and in response to the changing of the mapping in a segment table, one or more flush operations to invalidate one or more entries within one or more Segment Lookaside Buffer (SLB) address translation caches, the one or more entries within the one or more SLB address translation caches corresponding to the second set of virtual addresses, the SLB address translation caches being buffers within the processor that maps effective addresses to virtual addresses for address translation; running, by the computing device and in response to the executing of the one or more flush operations to invalidate one or more entries within one or more SLB address translation caches, a fourth test case, the fourth test case to test whether any of the first set of effective addresses are mapping to the second set of virtual addresses; determining, by the computing device and based on the fourth test case, that at least one of the first set of effective addresses are mapping to at least one of the second set of virtual addresses; determining, by the computing device and based on comparing the third test case with the fourth test case, that at least one of the one or more entries of within the one or more SLB address translation caches were not invalidated; and wherein the first test case, the second test case, the third test case, and the fourth test case each share a plurality of fields that are displayed by the computing device, the plurality of fields including: a first field identifying a description of each of the test cases, a second field identifying one or more preconditions needed in order to start each of the test cases, a third field identifying one or more steps needed to complete each of the test cases, a fourth field identifying one or more expected results for each of the test cases, and a fifth field identifying one or more actual results for each of the test cases.