Patent ID: 9672192
Date: 2017-06-06
CPC Classifications: G06F

Claim:
1. A FFT butterfly circuit comprising: a first temporary data register having an input and an output; a second temporary data register having a first input connected to said output of said first temporary register, a second input loadable from a specified address of a first memory, a third input loadable from a specified address of a second memory and an output connected to said input of said first temporary data register; a third temporary data register having a first input loadable from a specified address of a third memory, a second input loadable from a specified address of said second memory and an output; a fourth temporary data register having a first input loadable from a specified address of said first memory, a second input loadable from a specified address of said third memory and an output; a multiplier-accumulator having a first product input connected to said output of said second temporary register, a second product input connected to said output of said third temporary register, a sum input and an output, said multiplier-accumulator forming a product of data on said first product input and said second product input and selectable adding to or subtracting from data on said sum input, and a output; an accumulator including two accumulator registers having one input connected to said output of said multiply accumulator for storing data on said input in a specified one of said accumulator registers, a first output supplying data from the non-specified accumulator register and a second output connected to said sum input of said multiplier accumulator supplying data from the specified accumulator register; a register file including a plurality of registers having a first input connected to said first output of said accumulator for storing data at said first input in a first specified one of the plurality of registers, a second input connected to said output of said fourth temporary register for storing data at said second input in a second specified one of the plurality of registers, a first output for supplying data from a third specified one of the plurality of registers and a second output for supplying data from a fourth specified one of the plurality of registers; an adder/subtracter having a first input connected to said first output of said accumulator, a second input connected to said second output of said accumulator and an output supplying a selected one of a sum of data on said first input and on said second input or a difference of said second input from said first input; and a write buffer including two buffers having an input connected to said output of said adder/subtracter for storing data at said input in a specified one of the buffers and an output supplying data from a specified one of the buffers.