Patent ID: 9601196
Date: 2017-03-21
CPC Classifications: G11C

Claim:
1. A semiconductor integrated circuit comprising: a plurality of first wiring lines; a plurality of second wiring lines crossing the first wiring lines; a plurality of resistive change memories disposed at intersection regions of the first wiring lines and the second wiring lines, the resistive change memories each including a first electrode connected to a corresponding one of the first wiring lines, a second electrode connected to a corresponding one of the second wiring lines, and a resistive change layer disposed between the first electrode and the second electrode, a resistance between the first electrode and the second electrode being changeable among a first resistive state, a second resistive state, and a third resistive state, the second resistive state having a resistance greater than a resistance of the first resistive state, the third resistive state having a resistance lower than the resistance of the first resistive state, the resistive change memories having a first memory state in which the resistance between the first electrode and the second electrode is in the first resistive state, and a second memory state in which the resistance between the first electrode and the second electrode is in the second resistive state; a first driver configured to drive the first wiring lines; a second driver configured to drive the second wiring lines; and a control circuit configured to control the first driver and the second driver, the control circuit controlling the first driver and the second driver to select one of the first wiring lines and one of the second wiring lines for selecting one of the resistive change memories, and to program the selected one of the resistive change memories from the first memory state to the second memory state through the third resistive state, wherein one of the first driver and the second driver includes a plurality of first transistors corresponding to ones of the first wiring lines and the second wiring lines, drains of the first transistors being connected to corresponding ones of the first wiring lines and the second wiring lines, and sources of the first transistors being connected to a first power supply.