Patent ID: 9722616
Date: 2017-08-01
CPC Classifications: H03L,H04L

Claim:
1. A reception circuit comprising: a determination circuit configured to receive an input data signal and determine a value of the input data signal when a logic level of a sampling clock changes; a sampling clock generation circuit configured to generate the sampling clock based on the input data signal, generate a frequency adjustment value based on a frequency difference between the sampling clock and the input data signal, and adjust a frequency of the sampling clock based on the frequency adjustment value; and a frequency pull-in control circuit configured to perform integration on the frequency adjustment value obtained in plurality and obtain a first integral value in an individual first time period, wherein, when the first integral value reaches a first value before a single first time period elapses, the frequency pull-in control circuit outputs a reset signal that causes the sampling clock generation circuit to output an initial value of the frequency adjustment value until the first time period elapses.