Patent ID: 9612838
Date: 2017-04-04
CPC Classifications: G06F

Claim:
1. A data processor of Reduced Instruction Set Computer type, comprising: an instruction execution unit configured to execute instructions of an instruction set, the instruction set including: an operation instruction which causes the instruction execution unit to execute an operation process on operands of large data size and on operands of small data size to thereby generate first and second flags, the large data size operands including high-order bits and low-order bits, and the small data size operands including low-order bits, wherein the first flag is generated based on a result of the operation process on the operands of the large data size, wherein the second flag is generated based on low-order bits of the result of the operation process on the operands of the large data size or based on a result of the operation process on the operands of the small data size; and a prefix instruction which designates, out of the first and the second flags generated by the operation instruction, a flag to be updated by an instruction subsequent to the prefix instruction.