Patent ID: 9559704
Date: 2017-01-31
CPC Classifications: H03L

Claim:
1. A phase-locked loop (PLL) circuit, comprising: an error detector operable to generate an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency; an oscillator, coupled to the error detector, operable to provide a plurality of clock signals having an output frequency based on the error signal; a fractional frequency divider, coupled to the oscillator, operable to generate the feedback clock signal from the plurality of clock signals based on signals providing a first divider value and a control value derived from a second divider value; a multiplier operable to multiply signals providing a first integer value and a first fractional value by a power of two to generate signals providing a second integer value and a second fractional value, respectively; a sigma-delta modulator (SDM) operable to generate the signal providing the second divider value based on the signal providing the second integer value and the signal providing the second fractional value; and a divider operable to divide the signal providing the second divider value by the power of two to generate the signal providing the first divider value.