Patent ID: 9639421
Date: 2017-05-02
CPC Classifications: G06F,G11C,H03M

Claim:
1. An operation method of a flash memory system, comprising: reading data stored in a memory device, wherein the data is encoded by units of message blocks each including a row constituent code and a column constituent code by using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BC-BCH) method; performing a hard decision decoding on the read data; determining, when the hard decision decoding fails, a reference voltage for a message block having an error among the message blocks of the read data; and performing a soft decision decoding by using the determined reference voltage, wherein the reference voltage is determined to maximize average numbers of error bits included in bits that are randomly selected among bits having low reliability in the message block having the error, during the soft decision decoding.