Patent ID: 9653342
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from said top surface into said semiconductor substrate; forming a dielectric liner comprising a first dielectric material on said bottom surface and said sidewalls of said trench to line said trench; after forming the dielectric liner, depositing a second dielectric layer comprising a second dielectric material on the dielectric liner to at least partially fill said trench; partially etching said second dielectric layer to selectively remove said second dielectric layer from an upper portion of said trench while preserving said second dielectric layer on a lower portion of said trench and while preserving the dielectric liner in the upper portion of the trench and the lower portion of the trench, and filling said trench with a fill material which provides an electrical conductivity that is at least that of a semiconductor, wherein the dielectric liner lines the fill material in the trench.