Patent ID: 9685497
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising a first metallization layer comprising a first dielectric layer; a first conductive layer embedded in said first dielectric layer; a first conductive structure embedded in said first dielectric layer on a first side of said first conductive layer; a second conductive structure embedded in said first dielectric layer on a second side of said first conductive layer opposite said first side; a second dielectric layer disposed on said first metallization layer; a second conductive layer disposed on said second dielectric layer and having a lateral dimension in a lateral direction larger than a lateral dimension of said first conductive layer in said lateral direction; a third dielectric layer disposed on said second conductive layer; a first contact disposed in said third dielectric layer and extending through said second conductive layer in a first peripheric region thereof that does not overlap said first conductive layer to contact said first conductive structure; a second contact formed in said third dielectric layer and extending through said second conductive layer in a second peripheric region thereof that does not overlap said first conductive layer to contact said second conductive structure, wherein said second conductive layer electrically connects said first contact to said second contact; and a capacitor structure comprising said first conductive layer, said second dielectric layer, and said second conductive layer.