Patent ID: 9748332
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate; a plurality of memory cells on the semiconductor substrate arranged along a first dimension and along a second dimension that is orthogonal to the first dimension; and a cap dielectric extending continuously across each memory cell of the plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises a channel region in the semiconductor substrate, a tunnel dielectric layer on the channel region, a first electrode layer on the tunnel dielectric layer, and an inter-electrode dielectric layer extending continuously across each memory cell of the plurality of memory cells along the first dimension, wherein, along the first dimension, the channel region of each memory cell of the plurality of memory cells is separated from the channel region of an adjacent memory cell of the plurality of memory cells by a corresponding first air gap, each first air gap extending from below an upper surface of the semiconductor substrate to the inter-electrode dielectric layer, wherein the first air gap extends from below the upper surface of the semiconductor substrate up to and beyond an upper surface of the tunnel dielectric layer, and has a height of about 23 nm or less from a bottom surface of the inter-electrode dielectric layer to the upper surface of the semiconductor substrate, wherein at each first air gap, a bottom surface of the inter-electrode dielectric is exposed to the first air gap, wherein each memory cell of the plurality of memory cells further comprises a second electrode layer on the inter-electrode dielectric, and wherein, along the second dimension, the first electrode layer, the inter-electrode dielectric, and the second electrode layer of each memory cell of the plurality of memory cells are separated from an adjacent memory cell by a corresponding second air gap, each second air gap extending into the cap dielectric to form a distinct recessed region in the cap dielectric.