Patent ID: 9626472
Date: 2017-04-18
CPC Classifications: G06F,H01L

Claim:
1. A method of forming a layout design for fabricating an integrated circuit, the method comprising: placing a first set of layout patterns in a first layout layer, the first set of layout patterns being aligned with one or more grid lines of a first set of grid lines, the first set of layout patterns corresponding to fabricating a first set of components in a first component layer of the integrated circuit, the first set of grid lines extending along a first direction, a first grid line of the first set of grid lines overlapping a first cell boundary of a standard cell layout, and a second grid line of the first set of grid lines overlapping a second cell boundary of the standard cell layout; and placing a second set of layout patterns in a second layout layer, the second set of layout patterns being aligned with one or more grid lines of a second set of grid lines, the second set of layout patterns corresponding to fabricating a second set of components in a second component layer of the integrated circuit, the second set of grid lines extending along the first direction and having at least two different line pitches, a first grid line of the second set of grid lines overlapping the first cell boundary of the standard cell layout, and a second grid line of the second set of grid lines overlapping the second cell boundary of the standard cell layout, and at least one of the above operations being performed by a hardware processor.