Patent ID: 9564928
Date: 2017-02-07
CPC Classifications: H03M,H04L

Claim:
1. A transmitter comprising: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; parity permutator configured to perform parity permutation on the parity bits based on a permutation order; a puncturer configured to perform puncturing on the permutated parity bits based on a puncturing order; and an additional parity generator configured to generate additional parity bits to be transmitted in a previous frame by selecting bits among parity bits punctured by the puncturer, wherein the previous frame is transmitted prior to a current frame, wherein the current frame comprises parity bits which remain after the puncturing is performed, wherein the parity permutator performs the parity permutation by interleaving the parity bits, splitting a codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups, and interleaving the plurality of bit groups based on a following equation and table: where Y wherein all bit groups defined as a part of the puncturing order are punctured, and wherein the part of the puncturing order is based on the permutation order defined in the above table.