Patent ID: 9607673
Date: 2017-03-28
CPC Classifications: G06F,G11C,Y02D

Claim:
1. An apparatus comprising: a physical layer signaling protocol control circuit configured to receive consecutive codewords of a vector signaling code, each codeword represented as a set of symbols received synchronously over a collection of interconnection signal lines, the consecutively received codewords collectively representing an encoded message packet, the physical layer signaling protocol control circuit configured to decode the symbols of each consecutively received codeword into consecutive sets of data bits, and to form a set of link layer bits representing a message packet by concatenating the consecutive sets of data bits, the message packet associated with the encoded message packet and selected from the group consisting of a memory write packet, a memory read packet, and a status interrogation command packet; and, a link layer signaling protocol control circuit configured to generate a set of memory transaction signals based on the set of link layer bits, and to provide the set of memory transaction signals to a memory controller.