Patent ID: 9557996
Date: 2017-01-31
CPC Classifications: G06F

Claim:
1. A digital signal processor comprising: at least one functional unit including one of a vector execution unit, a scalar execution unit or an accelerator; a first memory unit arranged to provide data to be operated on by the functional unit; a third unit; an on-chip network connecting the functional unit, the first memory unit and the third unit, wherein the third unit is arranged to provide addressing data in the form of an address vector to be used for addressing the first memory unit, said third unit being connected to the first memory unit through the on-chip network in such a way that the addressing data provided from the third unit can be used to control the reading from and/or the writing to the first memory unit; and: a memory address interface unit arranged to compensate for the latency between the first memory unit and the third unit by serving as an intermediate storage of the addressing data retrieved from the third unit, the memory address interface unit comprising: