Patent ID: 9720793
Date: 2017-08-01
CPC Classifications: G01R,G06F

Claim:
1. A method for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads in a computer system comprising: providing a processor and test generator apparatus, said processor using said test generator including test generation context controls for performing the steps of: generating separate tests including a main test, and an irritator test for testing the multiple threads with the generated main test and the irritator test being completely independent; saving the generated main test and each irritator test and randomly mixing the generated main test and each irritator test; and combining the saved and mixed main test and each irritator test, wherein the main test is not forced to be generated with any particular irritator; implementing an unexpected exception handler for returning control of an irritator program stream to a known location and a known state at an uninterrupted instruction address in the irritator program stream; running constrained random irritator tests, monitoring the main test and running the main test from start to finish; and responsive to identifying the main test to complete, intervening in execution of each irritator test.