Patent ID: 9542972
Date: 2017-01-10
CPC Classifications: G11B

Claim:
1. A data processing system, the system comprising: a first equalizer circuit operable to equalize a first data input to yield a first equalized output; a first interpolator circuit operable to interpolate a delayed instance of the first data input to yield a first interpolated output; a second equalizer circuit operable to equalize a second data input to yield a second equalized output; a second interpolated circuit operable to interpolate a delayed instance of the second data input to yield a second interpolated output; a first summation circuit operable to sum the first equalized output and the second equalized output to yield a first combined output; a data detector circuit operable to apply a data detection algorithm to the first combined output to yield a detected output; a first loop pulse estimator circuit operable to estimate a first pulse output from the detected output; a second loop pulse estimator circuit operable to estimate a second pulse output from the detected output; a first multiplier operable to multiply a first interim feedback by a first scalar value to yield a first scaled output, wherein the first interim feedback is derived from the first pulse output; a second multiplier operable to multiply a second interim feedback by a second scalar value to yield a second scaled output, wherein the second interim feedback is derived from the second pulse output; and a second summation circuit operable to sum a third interim feedback with a fourth interim feedback to yield a second combined output, wherein the third interim feedback is derived from the first interim feedback and the fourth interim feedback is derived from the second interim feedback.