Patent ID: 9536980
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A device comprising: a gate stack extending over a semiconductor substrate; a hard mask disposed on a top surface of the gate stack; a pair of low-k dielectric spacers on opposing sides of the gate stack, wherein top surfaces of the pair of low-k dielectric spacers are lower than an upper surface of the hard mask; and a contact electrically connected to a source/drain region adjacent to the gate stack, wherein the contact extends laterally over a first low-k dielectric spacer of the pair of low-k dielectric spacers, the first low-k dielectric spacer opposing a second low-k dielectric spacer of the pair of low-k dielectric spacers, wherein a dielectric material of one or more dielectric layers over the first low-k dielectric spacer is disposed between the contact and the first low-k dielectric spacer, wherein top surfaces of one or more dielectric layers over the second low-k dielectric spacer are substantially coplanar with the upper surface of the hard mask, wherein top surfaces of the one or more dielectric layers over the first low-k dielectric spacer are below the upper surface of the hard mask, and wherein the dielectric material has a higher selectivity to etching than material of the first low-k dielectric spacer.