Patent ID: 9679829
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: forming a via hole through a first surface of a substrate to penetrate at least a portion the substrate; forming a metal layer partially filling the via hole, the metal layer including a body portion filling more than half of the via hole from a bottom of the via hole and an extended portion protruding from a top surface of the body portion along an upper sidewall of the via hole, the metal layer including a hole region defined by the top surface of the body portion and an inner sidewall of the extended portion at an upper region of the via hole, and the metal layer including copper; forming an alloy layer on the metal layer and in the hole region to substantially fill the via hole, the alloy layer containing at least one metallic element that is different from that in the metal layer and not containing copper; and polishing a second surface of the substrate opposite the first surface of the substrate to expose the metal layer.