Patent ID: 9570581
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method forming a plurality of connected stack gate structure for use in a non-volatile memory array, said method comprising: forming a stack gate structure by: etching said stack gate structure in a plurality of spaced apart substantially parallel regions, from the second top surface downward into the semiconductor substrate, with each region extending in a first direction; filling the etched spaced apart regions with the third insulating material, thereby forming isolation regions between adjacent active regions in the semiconductor substrate; and between adjacent stack gate structures; planarizing said third insulating material such that the top surface of the third insulating material over the etched spaced apart regions is substantially co-planar with the second top surface; removing the first sacrificial layer; etching said third insulating material such that the first top surface of the first polysilicon layer is substantially cleared of any third insulating material; forming a second polysilicon layer over the first polysilicon layer and over the third insulating material over the etched spaced apart regions, connecting the plurality of spaced apart stack gate structures; forming a fourth insulating material over the second polysilicon layer; and etching the resultant structure in a second direction substantially perpendicular to the first direction.