Patent ID: 9646966
Date: 2017-05-09
CPC Classifications: G06F,H01L

Claim:
1. An integrated circuit, comprising: a substrate; a first set of semiconductor fins aligned in a first direction on the substrate; a second set of semiconductor fins aligned in the first direction on the substrate; an inter-block isolation structure on the substrate having a first side and a second side, and wherein semiconductor fins in the first set have ends proximal to the first side of the inter-block isolation structure and semiconductor fins in the second set have ends proximal to the second side of the inter-block isolation structure; a patterned gate conductor layer including a first gate conductor extending across and overlie a first plurality of sides of at least one fin in the first set of semiconductor fins, and a second gate conductor extending across and overlie a second plurality of sides of at least one fin in the second set of semiconductor fins; and a plurality of patterned conductor layers and interlayer connectors in addition to the patterned gate conductor layer, one or more patterned conductors in the plurality of patterned conductor layers and the interlayer connectors being arranged to connect a semiconductor fin in the first set to a semiconductor fin in the second set, arranged to connect the first gate conductor to the second gate conductor, and arranged to connect a power conductor to at least one semiconductor fin in one of the first and second sets.