Patent ID: 9576960
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A structure comprising: an integrated circuit substrate; an n-type fin set in an nFET region on the integrated circuit substrate; a p-type fin set in a pFET region on the integrated circuit substrate; a gate stack disposed over the n-type fin set and the p-type fin set; a gate spacer disposed over the n-type fin set and the p-type fin set and on opposite sides of the gate stack; a first doped epitaxial material on a source region and a drain region of the p-type fin set, wherein the source and drain regions of the p-type fin set is above the top surface of the integrated circuit substrate, and the gate spacer has a first spacer thickness between the first doped epitaxial material and the gate stack; and a second doped epitaxial material on a source region and a drain region of the n-type fin set, wherein the source and drain region of the n-type fin set is above the top surface of the integrated circuit substrate, the first doped epitaxial material is different than the second doped epitaxial material, the gate spacer has a second spacer thickness between the second doped epitaxial material and the gate stack, and wherein the first spacer thickness is equal to the second spacer thickness.