Patent ID: 9748224
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate having a first major surface and an opposing second major surface; a heterostructure adjacent the first major surface, the heterostructure comprising: a first electrode disposed proximate to a first portion of the channel layer; a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode, wherein the second electrode is electrically decoupled from the semiconductor substrate; a third electrode disposed on the second major surface of the semiconductor substrate; a first control electrode disposed between the first electrode and the second electrode and configured to control a first current path between the first electrode and the second electrode wherein the first control electrode is electrically decoupled from the semiconductor substrate; a trench electrode extending through the heterostructure into the semiconductor substrate, wherein the trench electrode is electrically coupled to the first electrode; and a clamping device disposed in the semiconductor substrate and electrically coupled to the trench electrode and electrically coupled to the third electrode, wherein the clamping device is configured to provide a second current path generally perpendicular to the first current path.