Patent ID: 9710174
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. A semiconductor device, comprising: a central processing unit (CPU); a FLASH (rewritable nonvolatile) memory; a random access memory (RAM); a test sequencer; a memory controller that controls write and erase operations to the FLASH memory; a first multiplexer that couples a first bus with any one of the CPU and the test sequencer; and a second multiplexer that couples the RAM with any one of the first bus and the memory controller, wherein, in a normal operation mode, the RAM is coupled to the CPU via the first and second multiplexer, and the CPU controls the FLASH memory by sending commands to the memory controller via the first bus, and wherein, in a test mode, the RAM couples to the memory controller via the second multiplexer, and the test sequencer controls the FLASH memory by sending commands to the memory controller via the first bus.