Patent ID: 9613175
Date: 2017-04-04
CPC Classifications: G06F

Claim:
1. A method, comprising: obtaining a plurality of design rules for an integrated circuit; dividing said plurality of design rules into an unselected first set of design rules and a selected second set of design rules in a computer system, wherein design rules in said second set do not exist in said first set, and dividing said plurality of design rules comprises selecting said second set of design rules by performing at least one of: performing an automated layout construction process using said computer system, said automated layout construction process creating a layout of said integrated circuit, said automated layout construction process being performed on the basis of said first set of design rules but not on the basis of said second set of design rules; checking said layout of said integrated circuit for design rule violations using said computer system, wherein at least one member of said second set of design rules is not satisfied; and modifying said layout of said integrated circuit in said computer system for bringing said layout of said integrated circuit into conformity with each of said plurality of design rules if one or more design rule violations are found in said checking of said integrated circuit.