Patent ID: 9704962
Date: 2017-07-11
CPC Classifications: B82Y,H01L

Claim:
1. A method comprising: providing a substrate having source, drain and channel regions for a GAA MOSFET, the substrate doped with one of a p-type and an n-type dopant; disposing an etch stop-electric well (ESEW) layer over an entire top surface of the substrate in the channel region, the ESEW layer doped with the other of the p-type and the n-type dopant; disposing a sacrificial layer over an entire top surface of the ESEW layer such that the sacrificial layer is separated from the substrate by the ESEW layer in the channel region, the sacrificial layer doped with the same type dopant as the substrate; disposing a channel layer over an entire top surface of the sacrificial layer in the channel region; patterning a fin out of the ESEW layer, sacrificial layer, and channel layer in the channel region; and selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the channel region of the substrate.