Patent ID: 9594396
Date: 2017-03-14
CPC Classifications: G06F,H04L

Claim:
1. A data processing system comprising: a first clock domain having a first clock rate; a second clock domain having a second clock rate; a data path operable to transfer data items from the first clock domain to the second clock domain, the data path comprising a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner, the buffer having a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer; a read controller configured to define a read pattern for the buffer dependent upon the first clock rate and the second clock rate, to control output from the buffer in dependence upon such a read pattern, to monitor the value of the first pointer of the buffer and to adjust the read pattern as needed in dependence upon a value of the first pointer of the buffer, so as to avoid buffer overrun or buffer overflow.