Patent ID: 9697111
Date: 2017-07-04
CPC Classifications: G06F,G11C

Claim:
1. A system comprising: a system on chip (SoC) including a memory remapper, a first memory controller, a second memory controller and a processor configured to control the memory remapper; a first memory; and a second memory stacked on the SoC, and configured to operate faster than the first memory, the second memory being a wide input/output (I/O) mobile dynamic random access memory (DRAM), wherein the first memory controller receives first access control signals from the memory remapper, and controls an access operation with respect to the first memory based on the first access control signals, wherein the second memory controller receives second access control signals from the memory remapper, and controls an access operation with respect to the second memory based on the second access control signals, wherein the memory remapper performs a memory operation between the first memory and the second memory, by moving first data stored in the first memory to the second memory, by moving second data stored in the second memory to the first memory, and/or by swapping the first data and the second data, and wherein the memory remapper includes: