Patent ID: 9672315
Date: 2017-06-06
CPC Classifications: G06F

Claim:
1. A computer program product for providing an adjusted electronic representation of an integrated circuit layout, the computer program product having a non-transitory computer readable medium with a computer program embodied thereon, the computer program which when executed by a processor provides the adjusted electronic representation of the integrated circuit layout, the computer program comprising: computer program code for generating full node cells from a full node netlist; computer program code for scaling the full node cells to provide shrink node cells; computer program code for generating a timing performance of the full node cells and the shrink node cells; computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells; computer program code for generating first derivative cells from a respective shrink node cell, wherein each first derivative cell generated from the respective shrink node cell comprises a variation of the respective shrink node cell, the variation including at least one of an additional component in each first derivative cell that is not in the respective shrink node cell or a feature of a component in each first derivative cell that is a modification of a corresponding component in the respective shrink node cell; computer program code for generating a timing performance of the first derivative cells; computer program code for comparing the timing performance of the first derivative cells to the timing performance of the full node cells; computer program code for generating a first netlist comprising at least one of the shrink node cells, at least one of the first derivative cells, or a combination thereof; computer program code for generating a timing performance of at least two paths in the first netlist; computer program code for identifying a common path of the at least two paths; computer program code for identifying a first cell in the common path that violates a timing performance parameter, the first cell being a shrink node cell or one of the first derivative cells; computer program code for generating a second derivative cell from a subsequent cell that is in the common path after the first cell; computer program code for in response to the identifying the first cell, replacing the subsequent cell with the second derivative cell to generate a modified netlist; and computer program code for generating a final netlist based on the modified netlist.