Patent ID: 9679520
Date: 2017-06-13
CPC Classifications: G09G,H01L

Claim:
1. An array substrate, comprising: N rows of scan lines, N being a natural number; M columns of data lines, which are arranged to cross with the N rows of scan lines, M being a natural number; a display array, comprising N×M pixel units defined by the N rows of scan lines and the M columns of data lines; and N columns of leading wires, electrically connected to the N rows of scan lines respectively and led out in parallel to the M columns of data lines, wherein each column of the N columns of leading wires is located between two adjacent columns of data lines and there is a constant interval between each two columns of the N columns of leading wires; and wherein: the ┌N/2┐ a first column of the N columns of leading wires is located between two columns of data lines on a first side of the M columns of data lines and electrically connected to a first row of the scan lines, and second through N an N