Patent ID: 9647085
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method for manufacturing an integrated circuit device, the method comprising: providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming an etch stop layer within the semiconductor substrate at a first depth from the first surface; forming a shallow trench isolation in the semiconductor substrate having a second depth from the first surface, the second depth being less than or equal to the first depth; forming a gate insulating layer on the first surface of the semiconductor substrate, a gate electrode on the gate insulating layer and gate sidewalls on side surfaces of the gate electrode; forming a source region and a drain region in the semiconductor substrate, the source region comprising a first portion adjacent to the gate insulating layer and a second portion extending toward the second surface, and the drain region comprising a first portion adjacent to the gate insulating layer and a second portion extending toward the second surface; concurrently forming a source connection terminal on the second surface configured to connect with the source region, a drain connection terminal on the second surface configured to connect with the drain region, and a body terminal on the second surface of the semiconductor substrate between the source connection terminal and the drain connection terminal and directly connected to the semiconductor substrate; forming an interlayer dielectric layer overlying the source and drain connection terminals and the body terminal; and concurrently forming contact openings through the interlayer dielectric layer directly on the source and drain connection terminals and directly on the body terminal, wherein forming the source and drain comprises: performing a first ion implantation into the first surface of the semiconductor substrate to form the first portion of the source region and the first portion of the drain region; and performing a second ion implantation into the second surface of the semiconductor substrate to form the second portion of the source region and the second portion of the drain region.