Patent ID: 9720468
Date: 2017-08-01
CPC Classifications: G06F

Claim:
1. A method of power sequencing a computer including a south bridge by a controller, comprising: providing to the south bridge, before the south bridge has completed power management resets, a real time clock signal at a first frequency; providing to the south bridge, after the south bridge has completed power management resets, a real time clock signal at a second frequency wherein the first frequency is greater than the second frequency; wherein the south bridge counts a number of edges in the real time clock signal at the first frequency such that the south bridge passes through a wait period at an accelerated rate; generating a signal at the first frequency by a system clock; generating a signal at the second frequency by a system oscillator; and receiving the signals generated by the system clock and silicon oscillator by a multiplexer and further receiving a control signal from the south bridge, wherein the control signal determines which of the signal generated by the system clock and the signal generated by the silicon oscillator to provide as the real time clock signal; wherein the south bridge is communicatively connected to a processor; and wherein the controller is communicatively connected to the processor and the south bridge; wherein the control signal switches after the south bridge completes power management resets; wherein the controller comprises a divider and the controller is configured to divide the signal received from the system clock; and wherein the controller stabilizes the system clock and the silicon oscillator.