Patent ID: 9553132
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a first-layer first-row first conductive layer extending in a first direction; a first-layer second-row first conductive layer separated from the first-layer first-row first conductive layer in a second direction crossing the first direction and extending in the first direction; a first-layer first-row second conductive layer separated from the first-layer first-row first conductive layer and the first-layer second-row first conductive layer in a third direction crossing the first direction and crossing the second direction and extending in the second direction; a first-layer first-row memory cell provided between the first-layer first-row second conductive layer and the first-layer first-row first conductive layer; a first-layer second-row memory cell provided between the first-layer first-row second conductive layer and the first-layer second-row first conductive layer; a first-layer first-row contact connected to the first-layer first-row second conductive layer and extending in the third direction between the first-layer first-row first conductive layer and the first-layer second-row first conductive layer; a second-layer first-row second conductive layer separated from the first-layer first-row second conductive layer in the third direction and extending in the second direction, the first-layer first-row second conductive layer being disposed between the second-layer first-row second conductive layer and the first-layer first-row memory cell and between the second-layer first-row second conductive layer and the first-layer second-row memory cell in the third direction; a second-layer first-row intermediate memory cell provided between the first-layer first-row second conductive layer and the second-layer first-row second conductive layer; a second-layer first-row first conductive layer provided between the second-layer first-row intermediate memory cell and the second-layer first-row second conductive layer and extending in the first direction; a second-layer first-row memory cell provided between the second-layer first-row first conductive layer and the second-layer first-row second conductive layer; and a second-layer second-row contact connected to the second-layer first-row second conductive layer, separated from the first-layer first-row contact in the second direction, and extending in the third direction, the first-layer second-row first conductive layer and the first-layer second-row memory cell being disposed between the second-layer second-row contact and the first-layer first-row contact in the second direction, a first length of the first-layer first-row second conductive layer along the second direction being shorter than a second length of the second-layer first-row second conductive layer along the second direction.