Patent ID: 9588863
Date: 2017-03-07
CPC Classifications: G01R,G06F

Claim:
1. A computer system comprising: a memory comprising a definition of an instruction set architecture of a targeted complex-instruction set computer (CISC) processor; and a processor operably coupled to the memory and configured to perform a method comprising: analyzing the instruction set architecture of the targeted CISC processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture; determining a combination of instruction sequences for the targeted CISC processor from the instruction set profile that corresponds to a desired stressmark type, the desired stressmark type defining a metric representative of functionality of interest of the targeted CISC processor; monitoring performance of the targeted CISC processor with respect to the desired stressmark type while executing each of the instruction sequences; identifying one of the instruction sequences as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type; and designing and fabricating the targeted CISC processor based on results of the identified one of the instruction sequences most closely aligning with the desired stressmark type.