Patent ID: 9653457
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A structure comprising: a first semiconductor post extending vertically from a substrate; a first source/drain region in the first semiconductor post; a first gate electrode layer laterally surrounding the first semiconductor post and vertically above the first source/drain region, a first gate dielectric layer being interposed between the first gate electrode layer and the first semiconductor post; a second source/drain region in the first semiconductor post and vertically above the first gate electrode layer, the second source/drain region being connected to a power supply node; a second gate electrode layer laterally surrounding the first semiconductor post and vertically above the second source/drain region, a second gate dielectric layer being interposed between the second gate electrode layer and the first semiconductor post; and a third source/drain region in the first semiconductor post and vertically above the second gate electrode layer.