Patent ID: 9601620
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor structure having a plurality of transistors, comprising: providing a substrate having at least a dummy gate structure having at least dummy gate layer; forming a first dielectric layer on the substrate; thinning the first dielectric layer with a pre-determined depth to cause a top surface of the dielectric layer to be lower than a top surface of the dummy gate structure and expose top portions of side surfaces of the dummy gate structure; forming a stress layer on the exposed portions of the side surfaces of the dummy gate structure; forming a second dielectric layer on the thinned first dielectric layer; removing the dummy gate layer to form an opening with an enlarged top size caused by releasing stress in the stress layer previously formed on the exposed portions of the side surfaces of the dummy gate structure; and forming a gate electrode layer in the opening with the enlarged top size.