Patent ID: 9632866
Date: 2017-04-25
CPC Classifications: G06F,G11C

Claim:
1. A method of managing memory, the method comprising: receiving a write address and write data to be written to a memory location corresponding to the write address; reading a current memory state of the memory location corresponding to the write address; and selecting a codeword for the write data to write to memory according to a metric minimizing overwrite to the memory location corresponding to the write address and maximizing spread of wear across memory cells of the memory location, wherein selecting the codeword for the write data to write to memory according to the metric minimizing overwrite to the memory location corresponding to the write address and maximizing spread of wear across memory cells of the memory location comprises: performing an error correction code (ECC) encoding of the write data to map the write data to an ECC codeword; creating a translate vector using the ECC codeword and data read from the memory location during reading of the current memory state; performing a matching process of the translate vector using a coset sub-code to provide a coset codeword; and performing a Boolean operation using the translate vector and the coset codeword as inputs to output an error vector providing the codeword for the write data, wherein performing the matching process of the translate vector using the coset sub-code to provide the coset codeword comprises: searching the coset sub-code for a representative vector having minimum Hamming weight to the translate vector.