Patent ID: 9741672
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. An integrated circuit for preventing unauthorized use of the integrated circuit in radiation-hardened environments, the integrated circuit comprising: a silicon-on-insulator (SOI) structure comprising a silicon substrate, a buried oxide layer on the silicon substrate, and an active silicon layer on the buried oxide layer; a radiation insensitive sub-circuit formed on the active layer, and including a partially depleted transistor; a radiation sensitive sub-circuit formed on the active layer, and including a fully depleted transistor; and a controller to monitor performances of the radiation insensitive and the radiation sensitive sub-circuits, to determine a difference between the performances of the radiation insensitive and the radiation sensitive sub-circuits, and to prevent operation of the radiation sensitive sub-circuit under specified radiation conditions determined from said difference between the performances of the radiation insensitive and the radiation sensitive sub-circuits; and wherein: each of the partially depleted transistor and the fully depleted transistor includes a channel region formed in the active silicon layer, and the channel regions of the partially depleted transistor and the fully depleted transistor have substantially the same thickness and different doping concentrations.