Patent ID: 9536794
Date: 2017-01-03
CPC Classifications: B82Y,H01L

Claim:
1. A method of forming a complementary metal oxide semiconductor (CMOS) device, the method comprising the steps of: providing a semiconductor-on-insulator (SOI) wafer having a SOI layer separated from a substrate by a buried oxide (BOX); forming nanowires suspended over the BOX, wherein a first one or more of the nanowires are suspended at a first suspension height over the BOX and a second one or more of the nanowires are suspended at a second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires, wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires; depositing a conformal gate metal layer on the conformal gate dielectric both on the wafer and on the nanowires, wherein the conformal gate metal layer fully surrounds the first one or more of the nanowires but only partially surrounds the second one or more of the nanowires due to the conformal gate dielectric on the BOX being in direct physical contact with the conformal gate dielectric around the second one or more of the nanowires; depositing a conformal polysilicon layer on the conformal gate metal layer both on the wafer and on the nanowires; and annealing the CMOS device in an oxygen ambient to grow a conformal oxide layer at an interface between the conformal gate dielectric and the nanowires, wherein the conformal oxide layer grown at the interface between the conformal gate dielectric and the first one or more of the nanowires has a first thickness and the conformal oxide layer grown at the interface between the conformal gate dielectric and the second one or more of the nanowires has a second thickness, and wherein the first thickness is less than the second thickness due to the BOX serving as an oxygen source during growth of the conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.