Patent ID: 9691787
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor structure, comprising: a bulk semiconductor substrate; at least one first dielectric layer over a first portion of the substrate; a semiconductor layer over the first dielectric layer, creating a semiconductor-on-insulator (SOI) region; at least one second dielectric layer over a second portion of the substrate, creating a bulk semiconductor device region horizontally adjacent the SOI region, wherein the at least one second dielectric layer is thicker than the at least one first dielectric layer; and at least one layer of isolation material physically separating the SOI region from the bulk semiconductor device region down to the bulk semiconductor substrate; wherein the bulk region further comprises a layer of semiconductor material above the second portion of the substrate under the at least one second dielectric layer, and wherein the SOI region and the bulk region are co-planar.