Patent ID: 9685206
Date: 2017-06-20
CPC Classifications: G11C

Claim:
1. A memory device comprising: a memory cell array comprising a plurality of memory cells; a page buffer unit comprising a plurality of page buffers, each of the plurality of page buffers configured to store a plurality of pieces of data sequentially read at different read voltages from a memory cell among the plurality of memory cells, and each configured to perform a logic operation on the plurality of pieces of data stored therein and to output a corresponding logic result; a counting unit configured to count a number of memory cells read by the plurality of page buffers that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation output by each of the page buffers; and a valley detecting unit configured to detect a read voltage level that corresponds to a valley between two adjacent states of the memory cells based on the number of the memory cells counted by the counting unit.