Patent ID: 9646711
Date: 2017-05-09
CPC Classifications: G11C,H01L

Claim:
1. A nonvolatile memory device comprising: an anti-fuse memory cell array; a plurality of transistors of the anti-fuse memory cell array, the transistors arranged in a plurality of rows, each row extending in a first direction and including a set of transistors; a first gate electrode extending along a first row of the plurality of rows and connected to a first set of transistors in the first row; a first wiring line above the first gate electrode and separated from the first gate electrode in a vertical direction, the first wiring line extending in the first direction; a plurality of strap contacts arranged along the first direction and first row, each strap contact extending between the first gate electrode and the first wiring line, and each strap contact arranged along the first row being referred to as a 1th strap contact; a second gate electrode extending along a second row of the plurality of rows and connected to a second set of transistors in the second row, the second row being parallel to the first row; at least a first contact arranged in the second row and extending vertically from the second gate electrode to connect to a word line; and first through fourth active regions which extend along a second direction different from the first direction and are arranged sequentially along the first direction, wherein the first gate electrode is formed on the first through fourth active regions to intersect the first through fourth active regions, and the second gate electrode is formed on the first through fourth active regions to intersect the first through fourth active regions, wherein a first 1th strap contact of the plurality of 1th strap contacts is arranged to be at a first side of a second 1th strap contact of the plurality of 1th strap contacts, and the first 1th strap contact and second 1th strap contact are arranged to have two or fewer transistors between them, wherein a third 1th strap contact of the plurality of strap contacts is arranged to be at a second side of the second 1th strap contact opposite the first side, and the third 1th strap contact and second 1th strap contact are arranged to have two or fewer transistors between them, and wherein each of the plurality of 1th strap contacts and the first contact are not arranged with respect to each other in the second direction.