Patent ID: 9614525
Date: 2017-04-04
CPC Classifications: H03K

Claim:
1. A parallel interface comprising: an input unit configured to input, in parallel, a plurality of predetermined data signals and a clock signal; an output unit configured to output, in parallel, the predetermined data signals in synchronization with the clock signal; and a plurality of transmission lines disposed between the input unit and the output unit and configured to transmit, in parallel, the predetermined data signals and the clock signal, wherein the transmission lines are configured with a wiring pattern in which the transmission lines have different electrical lengths and an equal electrical capacitance, wherein a hysteresis buffer for shaping waveforms of the predetermined data signals and the clock signal is disposed at a side of the input unit, and a level converting circuit for converting logic levels of the predetermined data signals is disposed at a side of the output unit, and wherein the wiring pattern is disposed between the hysteresis buffer and the level converting circuit.