Patent ID: 9639644
Date: 2017-05-02
CPC Classifications: G06F

Claim:
1. A computer-implemented method for optimizing a circuit design stored in a computer memory, the method comprising: identifying a target block with an external boundary and external boundary pins in an integrated circuit design; converting an area outside the target block into a first macro, wherein the first macro has a physical library and a timing library, wherein the physical library represents physical attributes of the area outside the target block including an internal boundary that corresponds to the external boundary of the target block and internal boundary pins that correspond to the external boundary pins of the target block, wherein the timing library represents the timing information of the area outside the target block; representing the target block as a netlist; using a computer, optimizing timing characteristics of the netlist with respect to the first macro, wherein optimizing is performed by modifying the netlist to include additional buffers, repeaters, or by re zing gates within a net; wherein the identifying and converting steps are performed with both a master and a clone as the target block forming a first macro and a second macro, and both the master and clone are represented by a netlist in the representing step, and the netlist is optimized with respect to both the first and second macro in the optimizing step; and wherein the optimizing step further comprises defining a first mode/corner definition for a first timing library of the first macro and a second mode/corner definition for a second timing library of the second macro and combining the first mode/corner definition and the second mode/corner definition into a single multi-mode multi-corner definition and optimizing the block netlist using the multi-mode multi-corner definition.