Patent ID: 9704888
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. Display circuitry that forms an active area of a display having an array of display pixels that display images to a user and that forms an inactive area of the display that surrounds the active area, the display circuitry comprising: a substrate; a thin-film transistor formed over the substrate in the active area; a gate insulator layer formed over the substrate; a passivation layer formed on the thin-film transistor, wherein a gate electrode of the thin-film transistor is interposed between the passivation layer and the gate insulator layer; a first dielectric layer formed on the passivation layer; a second dielectric layer formed on the first dielectric layer; a first metal layer that forms conductive routing structures in the inactive area, wherein the first metal layer is interposed between the first dielectric layer and the second dielectric layer and wherein the conductive routing structures in the inactive area couple a display driver circuit in the inactive area to control lines in the active area that control the display pixels; a dielectric planarization layer formed on the second dielectric layer; a second metal layer that forms conductive routing structures in the inactive area interposed between the second dielectric layer and the dielectric planarization layer; a third metal layer that forms conductive routing structures in the inactive area formed on the dielectric planarization layer; a layer of insulating material in the active area and in the inactive area, wherein the third metal layer is interposed between the layer of insulating material and the dielectric planarization layer in the active area and in the inactive area; and a pixel electrode in the active area, wherein the layer of insulating material and the third metal layer are interposed between the pixel electrode and the substrate in the active area.