Patent ID: 9614055
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device including a MISFET forming region of a semiconductor substrate and a peripheral region of the semiconductor substrate, comprising steps of: (a) forming a first semiconductor layer of a first conductive type in the semiconductor substrate; (b) forming a field insulating film in the peripheral region; (c) forming a well region of the second conductive type opposite to the first conductive type in the peripheral region such that the well region is also formed under the field insulating film; (d) forming a first trench in the MISFET forming region, and forming a second trench in the peripheral region such that the second trench penetrates the well region and a bottom of the second trench is located at the first semiconductor layer, wherein the first and second trenches are unified; (e) forming a first gate insulating film in the first trench, and forming a second gate insulating film in the second trench; (f) forming a gate electrode in the first trench through the first gate insulating film, and forming a gate wiring formed in the second trench through the second gate insulating film such that the gate wiring is also formed over the field insulating film, wherein the gate electrode and the gate wiring are unified; (g) after the step (f), forming a second semiconductor layer of the second conductive type in the first semiconductor layer of the MISFET forming region; (h) after the step (f), forming a third semiconductor layer of the first conductive type in the second semiconductor layer; (i) after the steps (g) and (h), forming a contact hole formed in the second and third semiconductor layers such that a bottom of the contact hole is located at the second semiconductor layer; and (j) forming a source wiring in the contact hole and connected to the second and third semiconductor layers.