Patent ID: 9553105
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a stack of alternating insulation layers and gate electrodes; a substrate underlying the stack; a first channel material in a channel recess in the stack; a charge storage structure on the first channel material, in the channel recess; a second channel material on opposing sidewalls of the charge storage structure, in the channel recess; a first insulation layer on a sidewall of the first channel material, wherein the first insulation layer comprises a gate insulation layer that is between the first channel material and a nearest one of the gate electrodes to the gate insulation layer, wherein the gate insulation layer and the nearest one of the gate electrodes are laterally adjacent, and wherein the gate insulation layer undercuts a portion of the first channel material; and a second insulation layer on a portion of the substrate that is spaced apart from the first channel material, wherein an interface of the second insulation layer with the portion of the substrate is non-planar.