Patent ID: 9721629
Date: 2017-08-01
CPC Classifications: G11C

Claim:
1. A memory device comprising: inputs to receive command and address signals from a command and address bus; on-die termination (ODT) circuitry to couple to the inputs; one or more register fields that store register values to specify an impedance value, of an ODT impedance of the ODT circuitry, to be applied to each of the inputs, wherein, when applied, each input includes a corresponding ODT impedance having the impedance value; an input to receive a chip select signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the input that receives the chip select signal; and an input to receive a clock signal, wherein the register values include one or more register values to selectively enable application of an ODT impedance to the input that receives the clock signal.