Patent ID: 9536086
Date: 2017-01-03
CPC Classifications: G06F,Y10T

Claim:
1. A circuit arrangement, comprising: a processor, wherein the processor is configured to perform at least one cryptographic algorithm and to generate an associated signal related to execution properties of the at least one cryptographic algorithm; a memory circuit connected to the processor, wherein the processor is configured to access the memory circuit; a blocking circuit configured to generate one or more randomly generated wait state signals which prevent the processor from accessing the memory circuit, wherein the blocking circuit is configured to generate the one or more randomly generated wait state signals during execution of instructions by the processor, which halt the execution of instructions by the processor and which alters the associated signal; and an integrity checking circuit configured to access the memory circuit during a wait state period of the one or more random wait state signals, wherein the integrity checking circuit is configured to perform an integrity check on memory data in the memory circuit during a randomly generated wait state period during which the processor halts execution of instructions.