Patent ID: 9582457
Date: 2017-02-28
CPC Classifications: G06F,H04L

Claim:
1. A device, comprising: a bus including a first line and a second line; a first set of devices coupled to the bus and configured to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation; and a second set of devices coupled to the bus and configured to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation, wherein in the second mode of operation, data is encoded in transitions between symbols transmitted over the bus, each symbol representing signaling state of the bus, wherein the number of symbol transitions available between each pair of consecutively transmitted symbols is less than the number of signaling states of the bus used for communicating in the second mode of operation.