Patent ID: 9548091
Date: 2017-01-17
CPC Classifications: G11C

Claim:
1. A memory module comprising: first memory chips of a first rank, mounted on a first surface of a printed circuit board; second memory chips of a second rank, mounted on a second surface of the printed circuit board that is opposite to the first surface of the printed circuit board; and a register configured to identically program mode registers of the first memory chips of the first rank and mode registers of the second memory chips of the second rank according to address signals received together with a first mode register set (MRS) command, in response to the first MRS command during testing of the memory module, wherein: the mode registers of the first memory chips are programmed according to the address signals, the mode registers of the second memory chips are programmed according to a first portion of the address signals and mirrored address signals that are converted from a second portion of the address signals, and the second portion of the address signals exclude the address signals within the first portion of the address signals.