Patent ID: 9666575
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A semiconductor arrangement comprising: a well region; a first region disposed within the well region and comprising a first conductivity type; a second region disposed within the well region and comprising the first conductivity type, the second region spaced apart from the first region; a third region disposed within the well region; a fourth region disposed within the well region; a first gate disposed above the well region on a first side of the first region, the second region, the third region, and the fourth region; a second gate disposed above the well region on a second side of the first region and the second region and on the first side of the third region and the fourth region, wherein: a first region contact disposed above the first region and the second region; a second region contact disposed above the third region and the fourth region; and a first multi-gate contact disposed above and in direct, physical contact with the first gate, the second gate, and the first region contact.