Patent ID: 9543970
Date: 2017-01-10
CPC Classifications: H03L

Claim:
1. A phase-locked loop (PLL) circuit, comprising: a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) output signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal; wherein the difference signal comprises a signal UP and a signal DN, when the DCO output signal lags the reference clock signal, the signal UP is used to reflect the phase difference, and when the DCO output signal leads the reference clock signal, the signal DN is used to reflect the phase difference; wherein the digitized difference generator comprises an UP latch chain and a DN latch chain, the UP latch chain propagates a starting edge of a first pulse of the signal UP until the UP latch chain is disabled in response to an ending edge of the first pulse, the DN latch chain propagates a starting edge of a second pulse of the signal DN until the DN latch chain is disabled in response to an ending edge of the second pulse, and outputs of latches of the UP latch chain and outputs of latches of the DN latch chain form the control code.