Patent ID: 9565374
Date: 2017-02-07
CPC Classifications: H04N

Claim:
1. A sampling period control circuit configured to derive a ramp voltage range of a row signal when analyzing a previous row signal in order to control a ramp voltage range of a next row signal, the sampling period control circuit comprising: a row range detector configured to detect a substantial maximum value and minimum value of a row scanning range by analyzing the previous row signal; a row range controller configured to reset a scan ramp maximum value and a scan ramp minimum value based on an error range in the detected substantial maximum value and minimum value of the row scanning range; a ramp controller configured to control scanning and comparing a ramp voltage of a corresponding row using the scan ramp maximum value and the scan ramp minimum value; and a correlated double sampling (CDS) circuit configured to perform a CDS operation on a result of the comparison received from the ramp controller, wherein the row range detector is configured to detect the substantial maximum value and minimum value of the row scanning range from data fed back from the CDS circuit, the data relating to the previous row signal.