Patent ID: 9627329
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A chip package comprising: an interposer having a wiring layer; a die disposed on a surface of the interposer, the die electrically connected to the wiring layer; a die underfill material disposed between the interposer and the die, the die underfill material at least partially covering a side of the die extending away from the surface of the interposer; and a stiffening material disposed in contact with the interposer, the die underfill material, and a side of the die and not in contact with a top surface of the die, the stiffening material having a bottom surface in contact with the interposer, a top surface spaced apart from the bottom surface, and a laterally outer edge that extends between the respective top surface and bottom surfaces, is perpendicular to the surface of the interposer, and is offset inward an edge of the interposer and not dammed, the top surface of the stiffening material including a flat portion parallel to the interposer and a sloping portion between the flat portion and the laterally outer edge of the stiffening material, the stiffening material having a modulus greater than a modulus of the die underfill material.