Patent ID: 9640480
Date: 2017-05-02
CPC Classifications: G06F,H01L

Claim:
1. A metal oxide semiconductor (MOS) device, comprising: a first interconnect extending on a first track in a first direction, the first interconnect being configured in a metal layer; a second interconnect extending on the first track in the first direction, the second interconnect being configured in the metal layer; a third interconnect extending on a second track in the first direction, the third interconnect being configured in the metal layer, the second track being parallel to the first track, the third interconnect being coupled to the second interconnect, the second and third interconnects being configured to provide a first signal; and a fourth interconnect extending on the second track in the first direction, the fourth interconnect being configured in the metal layer, the fourth interconnect being coupled to the first interconnect, the first and fourth interconnects being configured to provide a second signal different than the first signal, wherein the first interconnect and the fourth interconnect are cross coupled across the coupling of the second interconnect and the third interconnect, and the second interconnect and the third interconnect are cross coupled across the coupling of the first interconnect and the fourth interconnect.