Patent ID: 9570575
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor fabrication method comprising: epitaxially growing a strain relaxed buffer on a substrate, the strain relaxed buffer comprising a plurality of first crystalline layers and a plurality of second crystalline layers arranged alternately; epitaxially growing a strained crystalline layer on the strain relaxed buffer; forming a protective layer over the strained crystalline layer; forming a first trench through the protective layer, the strained crystalline layer, and the strain relaxed buffer; selectively etching the plurality of first crystalline layers from with the first trench to create a plurality of first spaces extending laterally from the first trench; depositing a dielectric along surfaces of the first trench and the plurality of first spaces using atomic layer deposition; filling the first trench and the plurality of first spaces with a metal using atomic layer deposition; forming a second trench through the protective layer, the strained crystalline layer, and the strain relaxed buffer; etching the plurality of first crystalline layers and the plurality of second crystalline layers from within the second trench to expose the dielectric and form a cavity and a plurality of second spaces extending laterally from the first trench; and filling the cavity and the plurality of second spaces with the metal using atomic layer deposition.