Patent ID: 9722076
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, the method comprising: providing a substrate having at least two device regions separated by at least one isolation structure which is disposed in the substrate; forming two dummy gate structures on the device regions respectively, wherein each of the dummy gate structures comprises a dummy gate electrode; forming a plurality of doped regions in the substrate, wherein each of the device regions comprises two of the doped regions disposed at two opposite sides of each of the dummy gate structures; forming an interlayer dielectric layer on the substrate to peripherally surround the dummy gate structures, wherein tops of the dummy gate electrodes are exposed; forming an interface layer on the interlayer dielectric layer and the dummy gate structures, wherein a material forming the interface layer is different from a material forming the interlayer dielectric layer, and the interface layer is formed to contact the tops of the dummy gate electrodes; forming a plurality of openings in the interface layer to expose the tops of the dummy gate electrodes; replacing the dummy gate electrodes with two gate electrodes; removing the interface layer; and forming a material layer on the interlayer dielectric layer, wherein the material layer has a top surface which is elevated at the same level with the tops of the gate electrodes, and a ratio of a thickness of a thickest portion of the material layer to a pitch of the gate electrodes ranges from 1/30 to 1/80.