Patent ID: 9620521
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A semiconductor memory device, comprising: a substrate; a plurality of memory cells, each of the plurality of memory cells including an insulating layer and an electrode layer stacked alternately on the substrate; a semiconductor unit provided on the substrate, the semiconductor unit extending in a stacking direction; and a charge storage layer provided between the semiconductor unit and the electrode layer, the electrode layer including a first interconnect and a second interconnect, the first interconnect extending in a first direction, the second interconnect extending in a second direction, the first direction being orthogonal to the stacking direction and tilted with respect to an arrangement direction of the memory cells, the second direction being orthogonal to the stacking direction, being tilted with respect to the arrangement direction of the memory cells, and being different from the first direction.