Patent ID: 9576652
Date: 2017-02-21
CPC Classifications: G11C,H01L

Claim:
1. A resistive memory apparatus, comprising: at least one first resistive memory cell, having a first end, second end, and a control end, wherein the first end of the first resistive memory cell is coupled to a first bit line, a second end of the first resistive memory cell is coupled to a first source line, and the control end of the first resistive memory cell is coupled to a word line; a first bit line selecting switch, having a first end being coupled to the first bit line, a second end being coupled to a first input end of a sense amplifier, and providing the first bit line to be connected to the first input end of the sense amplifier during a first mode of a reading operation; a first source line selecting switch, having a first end being coupled to the first source line, a second end being coupled to the first input end of the sense amplifier, and providing the first source line to be connected to the first input end of the sense amplifier during a second mode of the reading operation; a first pull down switch, coupled between the first end of the first resistive memory cell and a reference ground, receiving a first control signal for being turned on or off; and a second pull down switch, coupled between the second end of the first resistive memory cell and the reference ground, receiving a second control signal for being turned on or off, wherein, when the reading operation is operated on the first resistive memory cell, on or off statuses of the first bit line selecting switch and the second pull down switch are the same, on or off statuses of the first source line selecting switch and the first pull down switch are the same, and on or off statuses of the first and second pull down switches are complementary.