Patent ID: 9659884
Date: 2017-05-23
CPC Classifications: H01L,H05K

Claim:
1. A carrier substrate having a first layout region and a second layout region, comprising: an insulation encapsulation; a plurality of first conductive patterns located in the first layout region and a plurality of second conductive patterns located in the second layout region, wherein the first conductive patterns and the second conductive patterns are embedded in the insulation encapsulation, and the insulation encapsulation exposes top surfaces of the first conductive patterns and the second conductive patterns; and at least one first dummy pattern located in the first layout region and at least one second dummy pattern located in the second layout region, wherein the first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns, the first dummy pattern and the second dummy pattern are embedded in the insulation encapsulation, the insulation encapsulation exposes top surfaces of the first dummy pattern and the second dummy pattern, and an edge profile of the first dummy pattern facing the second dummy pattern is non-linear, wherein the first dummy pattern comprises a first body portion and a plurality of first protrusions protruding toward the second dummy pattern, and wherein the first protrusions are embedded in the insulation encapsulation.