Patent ID: 9671850
Date: 2017-06-06
CPC Classifications: G06F,Y02D

Claim:
1. A method to provide a leakage current variability based power management, the method comprising: receiving computation data from a power controller and one or more processor instruction counters (PICs) of a core of a processor that executes one or more instructions; generating a table of linear combination samples from the computation data, wherein each of the linear combination samples includes a power usage value for a sub-unit of the core; generating a micro-architectural leakage map of the core from the linear combination samples within the table, wherein the one or more instructions are grouped based on one or more sub-units of the core associated with each one of the one or more instructions; in response to detection that a second sub-unit is deactivated based on the micro-architectural leakage map, directing a thread of a subset of the one or more instructions to a first sub-unit; in response to detection that the first sub-unit is unable to compensate the deactivation of the second sub-unit, reactivating the second sub-unit; executing a thread migration operation to move the thread from the first sub-unit to the second sub-unit, the thread to be executed by the second sub-unit; and in response to a completion of an execution of the thread;