Patent ID: 9690695
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A data storage device, comprising: a FLASH memory, providing storage space divided into a plurality of blocks with each block comprising a plurality of pages; and a controller, operating the FLASH memory in accordance with commands issued from a host, wherein: the controller updates a logical-to-physical address mapping table between the host and the FLASH memory in accordance with a first group count of a first buffer block selected from the plurality of blocks of the FLASH memory; the first group count reflects a first logical address distribution of write data buffered in the first buffer block and with non-updated logical-to-physical address mapping information; the higher the first group count, the more dispersed the first logical address distribution showing distribution of logical addresses of the write data buffered in the first buffer block and with non-updated logical-to-physical address mapping information; the controller divides each page of the logical-to-physical address mapping table into X entries for storage of physical address information of X logical addresses; X is a number; X logical addresses, sharing one page for recording the logical-to-physical address mapping information thereof, are classified as belonging to one group; the controller uses 2 the controller further updates the logical-to-physical address mapping table in accordance with the 2 the 2 for the 2 when write data issued from the host has a logical address belonging to a group not counted in the first to N