Patent ID: 9595525
Date: 2017-03-14
CPC Classifications: B82Y,H01L

Claim:
1. A semiconductor device comprising: an n-type field effect transistor comprising a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate; a p-type field effect transistor comprising a plurality of vertically stacked silicon germanium alloy nanowires located in another region of said semiconductor substrate, wherein said vertically stacked silicon-containing nanowires have a different semiconductor composition than said vertically stacked silicon germanium alloy nanowires and wherein each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a first geometric shape and each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor has a second geometric shape, wherein said second geometric shape is different from said first geometric shape; and a passive device located between said n-type field effect transistor and said p-type field effect transistor and yet in another region of said semiconductor substrate, wherein said passive device comprises a gated diode that comprises a semiconductor material body that is entirely composed of a silicon germanium alloy having a germanium content of 40 atomic or less, an N+ region located on one sidewall surface of said semiconductor material body, a P+ region located on another sidewall surface of said semiconductor material body and opposite said sidewall containing said N+ region, and a gate structure straddling over said semiconductor material body, wherein a topmost surface of said semiconductor material body of said passive device is coplanar with a topmost surface of an uppermost silicon-containing nanowire and a bottommost surface of said semiconductor material body of said passive device directly contacts a portion of a topmost semiconductor material surface of said semiconductor substrate.