Patent ID: 9645957
Date: 2017-05-09
CPC Classifications: G06F,G06T

Claim:
1. A data processing device comprising: a first processing block which is connected to a common bus and which processes a plurality of data, which is inputted simultaneously, in parallel; at least one second processing block connected to the common bus; a memory which is consisted of address space which has a plurality of banks; and a common bus arbitration unit which arbitrates a request for access to the memory outputted from the processing block, and controls exchange of data via the common bus between the processing block whose access request has been accepted and the memory, wherein the processing block includes a data transfer control device which changes an order of access to the bank of the memory corresponding to the respective data, unifies the respective data into an exchange data, and exchanges the exchange data with the memory when the processing block performs exchanging of the data to be processed in parallel with the memory via the common bus, wherein the data is consisted of an area of a first direction and an area of a second direction, wherein the first processing block processes a plurality of the data inputted simultaneously in the first direction of the data in parallel, unifies the respective processed data into the exchange data, accesses the bank of the memory in the first direction of the data, and exchanges the exchange data with the memory, and wherein the second processing block accesses the bank of the memory in the second direction of the data, and exchanges at least one of the data which is included in the exchange data with the memory.