Patent ID: 9666366
Date: 2017-05-30
CPC Classifications: C23C,C25D,H01C,H01F,H01G,H05K,Y10T

Claim:
1. A method of making a multi-layer electronic component, comprising the steps of: providing a plurality of insulating substrates each having an upper and a lower surface, said substrates each being delimited laterally by edges; interleaving a plurality of electrodes between selected of said plurality of insulating substrates; exposing selected portions of said electrodes along at least one edge of said substrates; providing anchor tabs interleaved at selected locations between the insulating substrates and positioned such that they are not in direct contact with any of said plurality of electrodes; exposing portions of said anchor tabs at selected edges of the insulating substrates; and submersing the electronic component in a plating solution to deposit at least one layer of termination material directly on said exposed portions of said electrodes and on said exposed portions of said anchor tabs until the exposed portions of selected of said electrodes and anchor tabs are connected by the at least one layer of termination material; wherein the step of plating is performed using an electroless process; the electroless process comprises submersing the multi-layer electronic component in an electroless copper plating solution to form a copper termination layer; and the method further comprises the step of covering the copper termination layer with a resistive layer.