Patent ID: 9653186
Date: 2017-05-16
CPC Classifications: G11C

Claim:
1. A memory-testing device for testing a memory accessed in a functional mode through a first timing path or in a test mode through a second timing path, comprising: a testing circuitry, disposed on the second timing path and coupled to the memory for testing performance of the memory; and a register, disposed on the second timing path and coupled to the testing circuitry and inputted by a testing clock signal, wherein the testing clock signal is different from an original clock signal of the memory and/or the testing circuitry, and the testing clock signal is utilized for adjusting the time when the memory-testing device latches data from the memory to decrease a timing margin of the second timing path for the test mode to be approximately equal to or smaller than a timing margin of the first timing path for the functional mode, and wherein the first timing path is different from the second timing path.