Patent ID: 9627496
Date: 2017-04-18
CPC Classifications: H01L,H03K

Claim:
1. A semiconductor device, comprising: a NOR circuit including four transistors arranged in a line on a substrate, with a source, a drain, and a gate of each of the four transistors being hierarchically disposed in a direction perpendicular to the substrate, each of the four transistors having: a silicon pillar with an upper portion and a lower portion; an insulator surrounding a side surface of the silicon pillar; a gate surrounding the insulator; a source region disposed at the upper portion or the lower portion of the silicon pillar; and a drain region disposed at the upper portion or the lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar, the four transistors including: wherein the gate of the first n-channel MOS transistor and the gate of the first p-channel MOS transistor are connected to one another, the gate of the second n-channel MOS transistor and the gate of the second p-channel MOS transistor are connected to one another, the drain region of the first n-channel MOS transistor, the drain region of the second n-channel MOS transistor, and the drain region of the first p-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars, the source region of the second p-channel MOS transistor is disposed on the side of the substrate relative to the silicon pillar, the drain region of the first n-channel MOS transistor, the drain region of the second n-channel MOS transistor, and the drain region of the first p-channel MOS transistor are connected to one another via a silicide region, the source region of the first p-channel MOS transistor and the drain region of the second p-channel MOS transistor are connected to one another via a contact, the source region of the first n-channel MOS transistor and the source region of the second n-channel MOS transistor are connected to a reference power supply terminal via a contact, and the source region of the second p-channel MOS transistor is connected to a power supply terminal via a silicide region.