Patent ID: 9646923
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first substrate; a plurality of conductive traces disposed over the first substrate, wherein each of the plurality of conductive traces comprises a bottom region proximate the first substrate and a top region opposite the bottom region, wherein the top region comprises a first width, wherein the bottom region comprises a second width, wherein the second width is greater than the first width, and wherein each of the plurality of conductive traces extends laterally over the first substrate over a distance greater than the second width; a second substrate having a plurality of conductive bumps protruding from a surface of the second substrate facing the first substrate, the plurality of conductive bumps substantially aligned with the plurality of conductive traces, each of the plurality of conductive bumps having tapered sidewalls and a lowest surface extending away from the second substrate, wherein the lowest surface is spaced apart from the first substrate and the plurality of conductive traces; a metal-containing oxide layer disposed over the tapered sidewalls of each of the plurality of conductive bumps; a solder joint extending from the lowest surface of each of the plurality of conductive bumps to the first substrate, wherein the solder joint covers sidewalls of each of the plurality of conductive traces, and wherein no solder joint is disposed over the tapered sidewalls of each of the plurality of conductive bumps; and a molding material between the first substrate and the second substrate.