Patent ID: 9576099
Date: 2017-02-21
CPC Classifications: G06F,Y02P

Claim:
1. A method, comprising: receiving an integrated circuit (IC) layout, the IC layout containing first features and second features different from the first features; receiving defect information of a blank reticle with respect to a defect of the blank reticle; determining, based on the defect information and the IC layout, that the defect will cause interference with at least some of the first features if the blank reticle is patterned with the IC layout; and in response to the determining, re-arranging, by one or more electronic processors, the IC layout in a localized manner such that the defect will no longer cause interference with the first features of the re-arranged IC layout; wherein: the IC layout contains a first layout block and a second layout block that is a functional equivalent of the first layout block, the first layout block and the second layout block each containing the first features; the determining comprises determining that the defect will cause interference with at least some of the first features of the first layout block but will not cause any interference with any of the first features of the second layout block if the first and second layout blocks are swapped; the re-arranging of the IC layout comprises swapping the first and second layout blocks; and the re-arranging the IC layout is implemented in fabricating photomasks or the re-arranging the IC layout is provided to a fabrication facility for fabricating semiconductor devices.