Patent ID: 9564439
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor structure, said method comprising: providing a bulk silicon substrate comprising a device region for an n-type semiconductor device of a first conductivity type and another device region located adjacent to said device region for said n-type semiconductor device of said first conductivity type, wherein said another device region is for another semiconductor device having said second conductivity type; recessing an exposed portion of said bulk silicon substrate in said device region to expose a sub-surface of said bulk silicon substrate; forming a semiconductor material stack of, from bottom to top, a semiconductor punch through stop layer containing at least one dopant of a second conductivity type which is opposite from said first conductivity type, a semiconductor diffusion barrier layer containing no n- or p-type dopant, and an epitaxial semiconductor layer on said sub-surface of said bulk silicon substrate; and forming a plurality of semiconductor fins in said device region, wherein each semiconductor fin of said plurality of semiconductor fins comprises, from bottom to top, a remaining portion of said semiconductor punch through stop layer, a remaining portion of said semiconductor diffusion barrier, and a remaining portion of said epitaxial semiconductor layer, wherein said semiconductor punch through stop layer comprises a first silicon germanium alloy layer, said semiconductor diffusion barrier layer comprises a second silicon germanium alloy layer, and said epitaxial semiconductor layer comprises silicon.