Patent ID: 9633745
Date: 2017-04-25
CPC Classifications: G11C

Claim:
1. A semiconductor memory device including a plurality of memory cells, the device comprising: a first page associated with a first memory cell; a second page associated with a second memory cell; a third page associated with a third memory cell; and a row decoder configured to apply voltages to gates of the first to third memory cells, wherein in writing of data, data is written into the first page before data is written into the second page, a data write operation includes a program operation and a program verify operation, the row decoder is configured to apply a first verify voltage to the gate of the first memory cell in the program verify operation for the first page, the row decoder is configured to apply a second verify voltage different from the first verify voltage to the gate of the second memory cell in the program verify operation for the second page, the row decoder is configured to apply a third verify voltage different from the first and second verify voltages to the gate of the third memory cell in the program verify operation for the third page, the second verify voltage is a value which is shifted from the first verify voltage by at least a first coefficient, and the third verify voltage is a value which is shifted from the first verify voltage by at least a second coefficient different from the first coefficient.