Patent ID: 9536783
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor wafer comprising a plurality of semiconductor die areas, comprising: forming a plurality of vias through a semiconductor structure of the semiconductor wafer from a back-side of the semiconductor structure to corresponding front-side metallization elements of the plurality of semiconductor die areas on a front-side of the semiconductor structure; forming a back-side metallization on the back-side of the semiconductor structure and within the plurality of vias such that, for each via of the plurality of vias, a portion of the back-side metallization is within the via and around a periphery of the via; for each via of the plurality of vias, providing one or more barrier layers on the portion of the back-side metallization that is within the via and around the periphery of the via; forming a wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the plurality of vias and around the peripheries of the plurality of vias; and forming streets through the wafer-level die attach metallization around peripheries of the plurality of semiconductor die areas.