Patent ID: 9601465
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A chip-stacked semiconductor package comprising: a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface and the first connection member having a first input/output pad group; a second chip having a second front surface, a second back surface, a second connection member, and a first through-silicon via (TSV), the first TSV electrically connected to the second connection member, the second back surface being opposite to the second front surface, the second connection member on the second front surface and the second connection member having a second input/output pad group corresponding to the first input/output pad; a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first input/output pad group of the first connection member and the second input/output pad group of the second connection member of the second chip being mirror symmetric, wherein the first back surface and side surfaces of the first chip are exposed to an ambient environment; a third connection member on the second back surface of the second chip, the third connection member being different than the first TSV; at least one third chip; and a fourth connection member electrically connected to the third connection member and the third chip, wherein a second sealing member is on a connected portion between the third connection member and the fourth connection member, and the second sealing member is on a side surface of the third chip.