Patent ID: 9619226
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. A method of performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, an immediate, and an opcode, wherein the source vector register comprises a plurality of packed data elements divided into a plurality of data lanes, each data lane corresponds to a destination data element in the destination vector register, the immediate comprises at least a same number of active bits as there are packed data elements in each data lane, and each active bit of the immediate corresponds to one of the plurality of packed data elements in each data lane, the method comprising: executing the single vector packed horizontal add or subtract instruction to, for each data lane of the source vector register, read a value of each active bit position of the immediate to determine whether to negate a value of corresponding data element position of the data lane, responsively negate the values determined to be negated, and sum all negated and unchanged packed data elements in each data lane to create a data lane result; and storing each data lane result in a corresponding destination data element position of the destination register.