Patent ID: 9577678
Date: 2017-02-21
CPC Classifications: H03M,H04L

Claim:
1. A bit group-unit interleaver, comprising: a first memory configured to store a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15; a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; and a second memory configured to store the interleaved codeword corresponding to a modulator for quadrature phase shift keying (QPSK) modulation, wherein the interleaving is performed using the following equation using permutation order: where X wherein the permutation order corresponds to an interleaving sequence represented by the following equation: