Patent ID: 9653358
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device structure, comprising: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation structure embedded in the first insulating layer and the semiconductor substrate; forming a stripe trench embedded in the first insulating layer and the semiconductor substrate; forming a channel region in the stripe trench, wherein forming the channel region comprises: forming a gate stack stripe on the channel region in the stripe trench; wherein the method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate to form a source region and a drain region, wherein after forming the channel region, the method further comprises forming an inner sidewall spacer for the gate above the channel region on inner sidewalls of the stripe trench, and the end of said inner sidewall spacer is flush with the end of the gate stack stripe in the direction of gate width; and wherein forming the gate stack stripe on the channel region comprises: forming a gate dielectric layer on the channel region; forming the gate stack stripe on the gate dielectric layer; removing the first insulating layer; and forming an outer sidewall spacer surrounding the inner sidewall spacer outside of the gate stack stripe; and cutting the gate stack stripe to form electrically isolated gate stacks; wherein at least a portion of a boundary of the channel region overlaps with at least a portion of a boundary of the source region and the drain region in a thickness direction of the semiconductor device structure, and wherein a bottom of the channel region is lower than a bottom of the source region and the drain region.