Patent ID: 9748220
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A gate-bounded silicon controlled rectifier, comprising: a substrate; an N-type well region, disposed in the substrate; a P-type well region, disposed in the substrate, wherein a junction is located between the P-type well region and the N-type well region; a first N-type semiconductor region, connected to a first pin, wherein the first N-type semiconductor region is disposed in the N-type well region; a first P-type semiconductor region, connected to a second pin, wherein the first P-type semiconductor region is disposed in the P-type well region; a second N-type semiconductor region, connected to the second pin, wherein the second N-type semiconductor region is disposed in the P-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region; a second P-type semiconductor region, connected to the first pin, wherein the second P-type semiconductor region is disposed in the N-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region; and a third semiconductor region, located between the second N-type semiconductor region and the second P-type semiconductor region, wherein the first pin and the second pin are respectively connected to an anode and a cathode.