Patent ID: 9570409
Date: 2017-02-14
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a first interconnection line and a second interconnection line, the first interconnection line and the second interconnection line extending along a first axis on a first plane at a first level on a substrate such that the first interconnection line and the second interconnection line are in alignment along the first axis with a gap therebetween; a direct contact plug extending in a direction perpendicular to the substrate towards an active region of the substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate, the second level being different from the first level such that the bypass interconnection line includes a region that is skewed across the gap an amount in a direction perpendicular to the first axis and parallel to the substrate to electrically isolate the bypass interconnect line from the direct contact plug; and a plurality of contact plugs configured to connect the bypass interconnection line to the first interconnection line and the second interconnection line.