Patent ID: 9570982
Date: 2017-02-14
CPC Classifications: H02M,H03K

Claim:
1. A pulse generation circuit for generating a pulse signal at an output terminal, comprising: a PMOS having a source coupled to a first voltage level, a drain coupled to the output terminal, and a gate coupled to receive a first gate control signal; an NMOS having a source coupled to a second voltage level, a drain coupled to the output terminal, and a gate coupled to receive a second gate control signal; and a logic circuit, coupled to the gate of the PMOS and the gate of the NMOS, for generating the first gate control signal according to a control signal and a first logic signal and generating the second gate control signal according to the control signal and a second logic signal; wherein, the first logic signal is a logic operation result based simultaneously on a first delay signal and the second gate control signal, the first delay signal being a delayed signal of the second gate control signal, and the second logic signal is a logic operation result based simultaneously on a second delay signal and the first gate control signal, the second delay signal being a delayed signal of the first gate control signal.