Patent ID: 9741611
Date: 2017-08-22
CPC Classifications: H01L,Y10S

Claim:
1. A method of forming a semiconductor device, the method comprising: providing a semiconductor layer; forming a convex portion and a concave portion surrounding the convex portion in the semiconductor layer; forming a protrusion type isolation layer to fill the concave portion of the semiconductor layer so that an uppermost surface of the isolation layer is at a level higher than an uppermost surface of the convex portion of the semiconductor layer; forming at least one trench traversing the convex portion of the semiconductor layer and having a line shape; forming a gate structure in the at least one trench, a capping layer being at a top of the gate structure, an uppermost surface of the capping layer being at a same level as the uppermost surface of the isolation layer; forming a contact plug by filling a conductive material in a contact hole; and forming a bit line electrically connected to the contact plug and crossing a gate line, wherein the contact plug is on and electrically connected to a source/drain region of the convex portion of the semiconductor layer and is surrounded by the isolation layer.