Patent ID: 9711426
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first die comprising a first pad and a first passivation layer; a second die comprising a second pad and a second passivation layer, wherein the first die has a first sidewall and the second die has a second sidewall; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer comprises: a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of the dielectric layer; wherein surfaces of the first die are not coplanar with corresponding surfaces of the second die; wherein the first passivation layer has a fourth surface adjacent to the dielectric layer; and wherein an angle between the fourth surface of the first passivation layer and a side surface of the dielectric layer is greater than 90 degrees, and wherein the side surface of the dielectric layer is formed between the second surface and the third surface of the dielectric layer.