Patent ID: 9721652
Date: 2017-08-01
CPC Classifications: G11C

Claim:
1. An apparatus, comprising: a plurality of memory cells; and a sense circuit configured to determine a condition of a first unselected memory cell adjacent to a selected memory cell prior to sensing for the selected memory cell; a read circuit configured to perform for the selected memory cell a plurality of sense operations for a plurality of states, the plurality of sense operations for a particular state of the selected memory cell corresponding to different conditions of the first unselected memory cell; and a compensation circuit configured to adjust a pass bias applied to the first unselected memory cell during each of the plurality of sense operations, the pass bias including a first pass voltage for a first condition of the first unselected memory cell during sensing for a first state, a second pass voltage for a second condition of the first unselected memory cell during sensing for the first state, and a third pass voltage for the first condition during sensing for a second state that is different from the first state, the first pass voltage is greater than the second pass voltage and the third pass voltage.