Patent ID: 9728649
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a third dielectric layer disposed on the second dielectric layer and the set of bias lines, wherein a thickness of the third dielectric layer is less than the thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the third dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines, wherein each of the substrate, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the set of bias lines have a same crystallographic orientation.