Patent ID: 9711222
Date: 2017-07-18
CPC Classifications: G11C,H01L

Claim:
1. A content addressable memory cell comprising: a first vertically-oriented pillar-shaped transistor and a second vertically-oriented pillar-shaped transistor each disposed above a substrate; a third vertically-oriented pillar-shaped transistor and a fourth vertically-oriented pillar-shaped transistor each disposed above the first vertically-oriented pillar-shaped transistor and the second vertically-oriented pillar-shaped transistor, the third vertically-oriented pillar-shaped transistor coupled to the first vertically-oriented pillar-shaped transistor, and the fourth vertically-oriented pillar-shaped transistor coupled to the second vertically-oriented pillar-shaped transistor; a fifth vertically-oriented pillar-shaped transistor disposed above the third vertically-oriented pillar-shaped transistor and the fourth vertically-oriented pillar-shaped transistor, the fifth vertically-oriented pillar-shaped transistor coupled to the third vertically-oriented pillar-shaped transistor and the fourth vertically-oriented pillar-shaped transistor; and a first reversible resistance-switching memory element coupled to the first and third vertically-oriented pillar-shaped transistors, and a second reversible resistance-switching memory element coupled to the second and fourth vertically-oriented pillar-shaped transistors.