Patent ID: 9627401
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a stacked body including a plurality of electrode layers stacked with insulators interposed between the electrode layers; a columnar portion penetrating in the stacked body in a stacking direction of the stacked body, the columnar portion including a semiconductor film extending in the stacking direction, and a cylindrical film provided between the electrode layers and the semiconductor film; and a separation portion extending in the stacking direction and in a first direction intersecting the stacking direction and separating the stacked body into a first portion and a second portion of the stacked body in a second direction intersecting the stacking direction and the first direction, the separation portion being disposed between the first portion and the second portion of the stacked body, the first portion and the second portion having a pair of sidewalls facing each other with the separation portion interposed, a width in the second direction between the pair of sidewalls being larger than a diameter of the columnar portion, the sidewalls having shapes in which a plurality of concave portions are disposed in the first direction, the plurality of concave portions being arranged periodically in the first direction.