Patent ID: 9673333
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method for fabricating a Polysilicon Thin-Film Transistor (P-Si TFT), said method comprising: forming a polysilicon active layer; forming a first gate insulation layer and a first gate electrode sequentially on the active layer, wherein a projection of the first gate electrode is located between first and second ends of the active layer; conducting a first ion implantation process on the active layer using the first gate electrode as a mask to form a doped region at each of the first and second ends of the active layer; forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, wherein a projection of each end of the second gate electrode is located between the projection of the first electrode and a respective end of the active layer; and conducting a second ion implantation process on the active layer by using the second gate electrode as an additional mask to form two source/drain implantation regions at two outer sides of the two doped regions of the active layer, wherein an impurity concentration of the doped regions is smaller than that of the source/drain implantation regions.