Patent ID: 9721642
Date: 2017-08-01
CPC Classifications: G06F,G11C,H01L,H04L

Claim:
1. A controller to control operations of a memory component, the controller comprising; a first circuit to transmit commands to the memory component, the commands including a read command that specifies data to be accessed from a memory core of the memory component; a second circuit to receive data sent by the memory component via an external bus, the data sent by the memory component in response to the read command; and, calibration circuitry operable to receive from the memory component, in response to one of the commands, a pattern selected from at least one of a first data pattern and a second data pattern and to, based on the selected pattern, adjust a timing of a timing reference signal for sampling the data at the second receive circuit, wherein, the timing of the timing reference signal is initially set using an initial calibration sequence and then updated during one or more subsequent calibration sequences.