Patent ID: 9589939
Date: 2017-03-07
CPC Classifications: H01L,H05K

Claim:
1. An optoelectronic semiconductor chip comprising: an interconnection layer with a mounting face, wherein the interconnection layer comprises a first electrically conductive contact layer, a second electrically conductive contact layer, and an insulation layer formed of an electrically insulating material that insulates the first and second electrically conductive contact layer from one another; and two optoelectronic semiconductor bodies, wherein the mounting face faces the optoelectronic semiconductor bodies, wherein each of the optoelectronic semiconductor bodies comprises an active region designed to generate radiation, wherein the insulation layer is arranged on a top of the second electrically conductive contact layer facing the optoelectronic semiconductor bodies, wherein the first electrically conductive contact layer is arranged on a top of the insulation layer and remote from the second electrically conductive contact layer so that the insulation layer is located at least in places between the first and the second electrically conductive contact layer and the first and the second electrically conductive contact layer run at least in places parallel, wherein the mounting face is entirely of a planar construction and spans completely over the interconnection layer, wherein an electrically insulating layer is formed between the interconnection layer and a chip carrier on a face of the interconnection layer remote from the mounting face, wherein the electrically insulating layer is of a planar construction on the faces remote from and facing the optoelectronic semiconductor bodies, wherein a contacting region of the second electrically conductive contact layer is arranged on a top of the interconnection layer facing the optoelectronic semiconductor bodies so that the contacting region of the second electrically conductive contact layer is freely accessible from a direction of the optoelectronic bodies, the contacting region being located laterally besides the insulation layer and being located in a common plane with remaining parts of the second electrically conductive contact layer that run in parallel with the mounting face, and wherein the optoelectronic semiconductor bodies are interconnected electrically in parallel by the interconnection layer.