Patent ID: 9536616
Date: 2017-01-03
CPC Classifications: G11C,H01L

Claim:
1. A non-volatile memory device comprising: a first electrode layer; a second electrode layer adjacent to the first electrode layer; a third electrode layer adjacent to the second electrode layer in a first direction from the first electrode layer toward the second electrode layer; a fourth electrode layer adjacent to the third electrode layer in the first direction; a channel body extending through the first electrode layer, the second electrode layer, the third electrode layer, and the fourth electrode layer in the first direction; a charge storage layer extending along the channel body; a plurality of memory cell transistors each including a part of the charge storage layer provided between the channel body and each of the first electrode layer, the second electrode layer, the third electrode layer, and the fourth electrode layer; and a circuit electrically connected to the first electrode layer, the second electrode layer, the third electrode layer, the fourth electrode layer, and the channel body, the plurality of memory cell transistors including a first memory cell transistor provided at a part where the channel body extends through the first electrode layer, the circuit including a first circuit portion and a second circuit portion, the first circuit portion providing the second electrode layer with a first potential, the third electrode layer with a second potential higher than the first potential, and the fourth electrode layer with a third potential between the first potential and the second potential, and the second circuit portion providing the channel body with the potential rising in the first direction and reading out data from the first memory cell transistor.