Patent ID: 9627467
Date: 2017-04-18
CPC Classifications: H01C,H01L

Claim:
1. An integrated circuit, comprising: a first interconnect pad disposed at a first interconnect level; a plurality of second interconnect pads disposed at a second interconnect level, wherein the second interconnect level is above the first interconnect level, and the second interconnect pads comprising: a first inter-level dielectric layer disposed between the first interconnect level and the second interconnect level; a plurality of second vias disposed above the plurality of second interconnect pads, and completely penetrating the silicon oxynitride (SiON) layer; a thin film resistor electrically connecting two of the plurality of second interconnect pads disposed at the second interconnect level, wherein a second interconnect pad and a third interconnect pad of the two of the plurality of second interconnect pads are electrically connected to the thin film resistor, the second interconnect pad and the third interconnect pad having bottom surfaces lower than a bottom surface of the thin film resistor; and at least two end-caps disposed above the thin film resistor, and each end-cap being covered by a corresponding one of the second interconnect pad and the third interconnect pad of the plurality of second interconnect pads, wherein each end-cap contacts both of the thin film resistor and the corresponding one of the second interconnect pad and the third interconnect pad of the plurality of second interconnect pads directly, wherein the second interconnect pad and the third interconnect pad have upper surfaces having protrusions over the at least two end-caps, wherein the protrusions over the at least two end-caps are higher than other portions of the upper surfaces, wherein an upper surface of the first inter-level dielectric layer extending from under the second interconnect pad to under a fourth interconnect pad of the plurality of second interconnect pads is planar, and wherein a protrusion in the first inter-level dielectric layer directly contacts the thin film resistor.