Patent ID: 9741868
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A split gate memory cell, comprising: a select gate disposed over a semiconductor substrate, separated therefrom by a gate dielectric layer; a memory gate arranged at one side of the select gate; a charge trapping layer having a vertical portion disposed between neighboring sidewalls of the select gate and the memory gate and a lateral portion extending under the memory gate; source/drain regions disposed in the semiconductor substrate at opposite sides of the select gate and the memory gate; a memory gate spacer arranged directly above the memory gate having a lateral dimension smaller than that of the memory gate, wherein the memory gate spacer has an inner sidewall disposed along an upper portion of the charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate; a dielectric liner continuously lining the outer sidewall of the memory gate, extending on a portion of a top surface of the memory gate not covered by the memory gate spacer, and extending upwardly along the outer sidewall of the memory gate spacer; and a sidewall spacer disposed alongside the dielectric liner; wherein the dielectric liner extends underneath the sidewall spacer and separates the sidewall spacer from the semiconductor substrate.