Patent ID: 9721957
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A static random access memory (SRAM) cell comprising: a first access gate, a first shared gate, a second access gate, and a second shared gate laterally spaced apart from each other on a substrate; a first access vertical channel portion penetrating the first access gate; a first pull-up vertical channel portion and a first pull-down vertical channel portion which penetrate the first shared gate; a second access vertical channel portion penetrating the second access gate; a second pull-up vertical channel portion and a second pull-down vertical channel portion which penetrate the second shared gate; a gate dielectric layer between each of the vertical channel portions and corresponding ones of the gates; a first node electrode electrically connected to bottom end portions of the first access, first pull-up and first pull-down vertical channel portions; and a second node electrode electrically connected to bottom end portions of the second access, second pull-up and second pull-down vertical channel portions, wherein the first node electrode is electrically connected to the second shared gate, and wherein the second node electrode is electrically connected to the first shared gate.