Patent ID: 9653349
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising: receiving a precursor, the precursor including: a substrate; conductive features extending above the substrate; a dielectric layer between the conductive features; a first capping layer disposed on the conductive features; recessing the dielectric layer adjacent the conductive features with a recessing depth d, wherein the recessing provides a top surface of the dielectric layer below a top surface of the conductive features and the first capping layer; depositing a neutralize layer (NL) over the recessed dielectric layer; depositing a block co-polymer (BCP) layer over the NL layer having a thickness t that extends from the NL to a top layer, wherein t is greater than d such that the BCP layer overlies the conductive features and the first capping layer; annealing the BCP layer to form a first plurality of polymer nanostructures, wherein the first plurality of polymer nanostructures are surrounded by a polymer layer over the dielectric layer, and wherein the first plurality of polymer nanostructures are coplanar, on a horizontal plane above and parallel to a top surface of the substrate with at least one of the first capping layer and the conductive features; forming polymer nano-block by selectively etching the polymer layer using the polymer nanostructure as etch masks; selectively etching the recessed dielectric layer using the polymer nano-blocks as etch masks to form a plurality of nano-trenches in the dielectric layer, wherein each of the plurality of of nano-trenches has a bottommost surface defined by a surface of the recessed dielectric layer, wherein the bottommost surface lies above a bottommost surface of the conductive feature; removing polymer nano-blocks; and depositing a second capping layer over the nano-trenches and over the conductive features and first capping layer, wherein the second capping layer serves to seal the nano-trenches to form nano-air-gaps, wherein the nano-air-gaps are defined by the bottommost surface of each of the plurality of nano-trenches and a top surface defined by an interface with the second capping layer, and wherein the top surface is coplanar with the conductive features on another horizontal plane above and parallel to the top surface of the substrate.