Patent ID: 9692399
Date: 2017-06-27
CPC Classifications: H03K

Claim:
1. A digital delay unit, comprising: an inverter to receive a first signal; a first signal input terminal coupled to a first input terminal of a first NAND gate; the first NAND gate having a second input terminal coupled to an output terminal of the inverter; a second NAND gate, having a first input terminal coupled to an output terminal of the first NAND gate; a third NAND gate, having a first input terminal coupled to an output terminal of the second NAND gate, and a second input terminal coupled to a second signal input terminal; and a fourth NAND gate having a first input terminal to receive the first signal, a second input terminal to receive a second signal, and an output terminal coupled to a second input terminal of the second NAND gate, wherein when the first signal input terminal receives an input signal that is a clock signal, a logic level of the first signal is set to be 0 and the logic level of the second signal input terminal is set to be 1, and when the input signal is sent to the digital delay unit via the second signal input terminal, the logic level of the first signal is set to be 1, and a logic level of the second signal is set to be 1.