Patent ID: 9716044
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A method of making an integrated circuit, the method comprising: forming a first gate stack and a second gate stack on a semiconductor substrate; forming a first source, a first drain, a second source, and a second drain in the semiconductor substrate, wherein the first gate stack interposes the first source and the first drain and the second gate stack interposes the second source and the second drain; forming a stressed contact etch stop layer (CESL) over the first gate stack and the second gate stack, wherein the stressed CESL is configured to provide a tensile-stressed contact etch stop layer (T-CESL) over the first gate stack and a compressive-stressed contact etch stop layer (C-CESL) over the second gate stack, wherein a hydroxide concentration of the T-CESL is greater than a hydroxide concentration of the C-CESL; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP), wherein the HARP process is tuned to reduce the hydroxide concentration of the T-CESL; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.