Patent ID: 9614067
Date: 2017-04-04
CPC Classifications: B82Y,H01L

Claim:
1. A semiconductor device comprising: an insulation substrate; a semiconductor nanowire formed on the insulation substrate and having both end regions doped in a p-type and an n-type, respectively and an intrinsic region, which is not doped, between the p-type doped region and the n-type doped region; doped region electrodes formed on each of the p-type doped region and the n-type doped region of the semiconductor nanowire; a lower insulation layer formed on the intrinsic region of the semiconductor nanowire; an intrinsic region electrode formed on a part of the lower insulation layer; and metal or semiconductor nanoparticle regions formed on the lower insulation layer between the intrinsic region electrode and each of the doped region electrodes and spaced apart from the intrinsic region electrode, wherein the metal or semiconductor nanoparticle regions are positioned at both sides of the intrinsic region electrode, and wherein the metal or semiconductor nanoparticle regions are positioned at parts of the lower insulation which are not covered by the intrinsic region electrode.