Patent ID: 9601632
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer, wherein the source electrode layer comprises a first region and a second region, wherein the drain electrode layer comprises a third region and a fourth region, wherein the second oxide layer is in direct contact with a top surface of the first region and a top surface of the third region, wherein each of the first region and the third region are in direct contact with a top surface of the oxide semiconductor layer, wherein the second region and the fourth region do not overlap with the second oxide layer and the gate insulating layer, and wherein a side surface of the second oxide layer and a side surface of the gate insulating layer are aligned over the source electrode layer and the drain electrode layer.