Patent ID: 9733935
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. A processor comprising: a first register to store a first vector input operand; a second register to a store a second vector input operand; a third register to a store a third vector input operand; a fourth register to store a packed data structure containing a first scalar input operands and a second scalar input operand; a decoder to decode a single instruction, having a first field specifying the first register, a second field specifying the second register, a third field specifying the third register, and a fourth field specifying the fourth register, into a decoded single instruction; and an execution unit comprising a multiplier coupled to the first register, the second register, the third register, and the fourth register, the execution unit to execute the decoded single instruction to for each element position, multiply the first scalar input operand with an element of the first vector input operand to produce a first value, multiply the second scalar input operand with a corresponding element of the second vector input operand to produce a second value, and add the first value, the second value, and a corresponding element of the third vector input operand to produce a result, and store in parallel a result for each element position of the first vector input operand, the second vector input operand, and the third vector input operand into a corresponding element position of a resultant register.