Patent ID: 9563731
Date: 2017-02-07
CPC Classifications: G03F,G06F

Claim:
1. A double patterning method comprising: receiving a circuit design, the circuit design having a first set of cells, one or more of the cells in the first set of cells having a boundary wire at a boundary thereof and a first signal pattern proximate the boundary wire; replacing one or more of the cells in the first set of cells with a second set of cells, each of the cells in the second set of cells having a second signal pattern at a boundary thereof; placing a first cell from the second set of cells and a second cell from the second set of cells in a first layout so that the second signal pattern at the boundary of the first cell from the second set of cells abuts the second signal pattern at the boundary of the second cell from the second set of cells; replacing the second signal patterns at the respective boundaries of the first cell from the second set of cells and the second cell from the second set of cells with a boundary pattern assigned to a first mask and a pair of third signal patterns assigned to a second mask, the boundary pattern located between the pair of third signal patterns and separated from each of the pair of third signal patterns, wherein the step of replacing the second signal patterns defines a second layout different from the first layout, and wherein the first mask and the second mask are used in a double patterning process to pattern a single layer of an integrated circuit according to the second layout.