Patent ID: 9576858
Date: 2017-02-21
CPC Classifications: H01L,H03K

Claim:
1. A method of forming a semiconductor structure comprising: forming a gate cavity laterally surrounded by an interlevel dielectric (ILD) layer, the gate cavity exposing a portion of at least one fin stack comprising a first semiconductor fin, a dielectric fin atop the first semiconductor fin, and a second semiconductor fin atop the dielectric fin; forming a stack in the gate cavity, the stack comprising a gate dielectric located over sidewalls and a bottom surface of the gate cavity, a first work function metal located over the gate dielectric, and a first gate conductor layer portion located over the first work function metal and filling a remaining volume of the gate cavity; recessing the first gate conductor layer portion to provide a first gate conductor, wherein a top surface of the first gate conductor is located between a top surface of the dielectric fin and a bottom surface of the dielectric fin; forming a second work function metal layer on a portion of the first work function metal that is not covered by the first gate conductor and on a top surface of the first gate conductor; and forming a second gate conductor layer on the second work function metal layer to fill the gate cavity.