Patent ID: 9633935
Date: 2017-04-25
CPC Classifications: B81B,H01L

Claim:
1. A stacked chip package, comprising: at least one first substrate having a first side and a second side opposite thereto, wherein the at least one first substrate comprises: a recess in the at least one first substrate and adjoining a side edge of the at least one first substrate; and a plurality of redistribution layers disposed on the at least one first substrate and extending onto a bottom of the recess, wherein at least two of the plurality of redistribution layers comprise an end extending into the recess, and the ends have an expanded portion; at least one second substrate disposed on the first side of the at least one first substrate; a plurality of bonding wires correspondingly disposed on the plurality of redistribution layers in the recess, and extending onto the at least one second substrate; and at least one device substrate disposed on the second side of the at least one first substrate.