Patent ID: 9627076
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. A nonvolatile memory device comprising: a substrate; a peripheral logic structure on the substrate; a lower filling insulating layer covering the peripheral logic structure; a horizontal semiconductor layer on the lower filling insulating layer, the horizontal semiconductor layer including a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions; and a three-dimensional memory cell array on the horizontal semiconductor layer, the three-dimensional memory cell array including a plurality of memory blocks, each of the memory blocks including sub-blocks on corresponding ones of the well regions, and the nonvolatile memory device is configured to perform an erase operation in units of the sub-blocks by independently applying an erase voltage to a selected one of the well regions during the erase operation, wherein the nonvolatile memory device is configured to apply an unselect voltage to an unselected one of the well regions or float the unselected one of the well regions during the erase operation, and a value of the erase voltage is different than a value of the unselect voltage.