Patent ID: 9640434
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method for processing an electroplated copper film in copper interconnect process includes the following steps: Step 1: providing an integrated circuit chip which finished front-end-of-line process, and then performing back-end-of-line processes for all layers of copper interconnects by Cu/Low-k dual damascene processes; wherein an electrochemical plating process is performed to fill copper in order to form an electroplated copper film, and then a first annealing process is performed to the electroplated copper film at or below 180° C. to inhibit grain growth of the electroplated copper film; Step 2: performing a second annealing process to the electroplated copper film at or beyond 240° C. under an atmosphere of mixed hydrogen and nitrogen, which containing 3.6˜4.0 Vol % of hydrogen gas, to increase the grain growth of the electroplated copper film to reach a stable crystalline state; Step 3: performing a final dielectric protective layer deposition of the copper back-end-of-line interconnect process to the chip.