Patent ID: 9699007
Date: 2017-07-04
CPC Classifications: H04L

Claim:
1. A decision feedback circuit comprising: a plurality of decision feedback equalizer (DFE) branches, each DFE branch including: a pre-computation stage configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and a decision feedback stage comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches; where at least one selection input for a first multiplexer circuit in the decision feedback stage of a first DFE branch of the plurality of DFE branches is connected to an intermediate output from a second multiplexer circuit for a second DFE branch of the plurality of DFE branches, wherein the intermediate output is an output from a first multiplexer in the second DFE branch, where the output of the first multiplexer is an input to a second multiplexer in the second multiplexer circuit of the second DFE branch.