Patent ID: 9577067
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductive substrate; a metal gate comprising a metallic layer proximal to the semiconductive substrate; a dielectric layer surrounding the metal gate and including a first surface facing the semiconductive substrate and a second surface opposite to the first surface; a sidewall spacer surrounding the metallic layer with a greater longitudinal height and disposed between the metallic layer and the dielectric layer, wherein the sidewall spacer includes a bottom landing on the semiconductive substrate and a top opposite to the bottom; an etch stop layer over the metal gate and comprising a surface substantially coplanar with the second surface of the dielectric layer, wherein the etch stop layer has a higher resistance to etchant than the dielectric layer, a first portion of the etch stop layer is disposed alongside a sidewall of the sidewall spacer, a second portion of the etch stop layer is over the sidewall spacer and the first portion, and the first portion is narrower than the second portion; and a second dielectric layer laterally lying on the dielectric layer, wherein the second portion of the etch stop layer is between the sidewall spacer and the second dielectric layer, wherein a top of the metal gate is recessed from the top of the sidewall spacer.