Patent ID: 9685141
Date: 2017-06-20
CPC Classifications: G09G,H03K,H03L

Claim:
1. A circuit to generate a local clock signal from a forwarded clock signal, the circuit comprising: a plurality of delay multiplexers connected in a ring to generate the local clock signal, and a propagation delay control circuit, to adjust a propagation delay of each of the plurality of multiplexers, each of the plurality of delay multiplexers being an inverting multiplexer having an adjustable propagation delay, wherein a delay multiplexer of the plurality of delay multiplexers comprises a first branch and a second branch, each of the first and second branches comprising four transistors configured to implement a tri-state inverter with a data input, a differential enable input, and a data output, and wherein each of the first branch and the second branch further comprises a complementary pair of current control transistors.