Patent ID: 9721873
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate; a semiconductor element having a gate electrode and source/drain regions formed on a main surface of the semiconductor substrate; element isolation regions extending in the semiconductor substrate and laterally adjacent to the source/drain regions; an etch stop layer formed over and contacting the gate electrode and source/drain regions; an interlayer insulating film formed over the semiconductor substrate, covering the semiconductor element; a contact plug penetrating the interlayer insulating film and the etch stop layer and being coupled to the source/drain regions of the semiconductor element without contacting the element isolation regions, the contact plug comprising a main conductor film and a barrier conductor film around the main conductor film; a through electrode arranged in a through hole penetrating the interlayer insulating film and the semiconductor substrate; a first insulating film formed between the semiconductor substrate and the through electrode, directly on an upper surface of the interlayer insulating film; and a first wiring penetrating the first insulating film and being coupled to an upper surface of the contact plug, wherein the first insulating film over the interlayer insulating film and the first wiring include a first wiring layer, wherein a thickness of the first insulating film in the through hole in a direction perpendicular to an inner wall of the through hole is greater than a thickness of first insulating film over the interlayer insulating film, and wherein the first insulating film has a lower relative permittivity than a silicon oxide film, wherein the thickness of the first insulating film in the through hole in the direction perpendicular to the inner wall of the through hole is about 1 μm, and the thickness of the first insulating film over the interlayer insulating film is about 0.3 μm.