Patent ID: 9678155
Date: 2017-06-13
CPC Classifications: G01R

Claim:
1. An integrated circuit test architecture comprising: (a) cores of functional circuits; (b) test wrapper architectures, each test wrapper architecture being connected with one core; (c) test access mechanisms, each test access mechanism being connected with one of the test wrapper architectures and having an enable input; (d) a test access mechanism controller having test access mechanism interface buses, each interface bus being connected with one of the test access mechanisms, and having an enable output connected with an enable input of a test access mechanism; and (e) double data rate circuitry, the double data rate circuitry having a double data rate parallel data bus input, a double data rate clock input, a clock output connected to the controller circuitry, a load instruction register output connected to the controller circuitry, mode outputs connected to the controller circuitry, and parallel data bus outputs connected to the controller circuitry and coupled to the functional circuitry.