Patent ID: 9542285
Date: 2017-01-10
CPC Classifications: G06F,G11C

Claim:
1. A memory device comprising: a storage unit in which a plurality of semiconductor chips each comprising a plurality of memory blocks respectively arranged in a planar direction and a plurality of redundant blocks respectively arranged in the planar direction are stacked; a detecting unit configured to detect a defect of each of the memory blocks in the storage unit; a checking unit configured to check free capacity in each of the redundant blocks in the storage unit; a determining unit configured to determine a substitute block to be substituted for the memory block in which the defect has been detected from the redundant blocks having the free capacity; and a control unit configured to access the storage unit, the detecting unit detects the defect upon activation of the memory device, the checking unit checks the free capacity in the redundant blocks upon activation of the memory device, the determining unit determines the substitute block upon activation of the memory device and creates a table defining a correspondence relationship between the memory block in which the defect has been detected and the substitute block, and the control unit accesses the storage unit with reference to the table.