Patent ID: 9720837
Date: 2017-08-01
CPC Classifications: G06F

Claim:
1. A computer program product for allowing non-cacheable loads in a hardware transactional memory environment, wherein transactional loads or stores by a processor are monitored for transactional execution (TX) conflicts in a cache of a hierarchical cache subsystem, the computer program product comprising: a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: accepting a request, by the processor, to execute a transactional execution (TX) transaction; based on execution, by the processor, of a cacheable load instruction, loading first memory data for the TX transaction based on a cache line associated with the first memory data; based on execution, by the processor, of a non-cacheable load instruction for loading second memory data of the TX transaction, loading an address of the second memory data into a non-cache monitor for monitoring memory conflicts of non-cached lines in response to the processor loading the second memory data for execution by the processor; avoiding memory conflicts by both the cacheable loads of the first memory data, and the non-cache memory of the second memory data; implementing a cache coherency protocol for coherency between cacheable loads of the first memory data by setting and clearing coherency protocol bits, and enforcing the cache coherency protocol using cache control logic; monitoring an address of the cache line associated with the first memory data using the cache control logic; aborting the TX transaction in response to a memory conflict including an address matching the address of the cache line that was cached as part of the TX transaction; monitoring the address of the second memory data by the non-cache monitor; and aborting the TX transaction based on the non-cache monitor detecting a memory conflict from another processor of the second memory data, the memory conflict comprising requesting an access, by the other processor, to the address monitored by the non-cache monitor which includes the non-cached lines stored in the non-cache memory device while the processor is executing the non-cacheable load instruction.