Patent ID: 9640525
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. An ESD (Electro-Static Discharge) protection circuit comprising: a power MOS (Metal-Oxide-Semiconductor) transistor provided between an external connection terminal and a reference voltage terminal; a clamping circuit that is provided between the external connection terminal and a gate of the power MOS transistor and clamps a voltage between the external connection terminal and the gate of the power MOS transistor at a predetermined value or less; a first resistive element provided between the gate and a source of the power MOS transistor; and a MOS transistor that is provided in series with the power MOS transistor and has a gate and a source which are commonly connected to each other, wherein the MOS transistor is provided between the external connection terminal and a drain of the power MOS transistor.