Patent ID: 9704756
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming an array on a semiconductor substrate having a major surface, the major surface having a first direction and a second direction different than the first direction, the array comprising a plurality of first regions arranged in a first row of the array and a plurality of second regions arranged in a second row of the array, wherein each of the plurality of first regions comprise a plurality of first devices having a current flow direction oriented in the first direction, wherein each of the plurality of second regions comprise a plurality of second devices having a current flow direction oriented in the second direction, wherein each of the plurality of first devices comprises a first high voltage device, wherein the first high voltage device comprises a first source contact and a first drain contact, wherein at least one first gate contact and at least one second gate contact are disposed between the first source contact and the first drain contact, the first source contact being disposed over and adjacent to a first well disposed within the semiconductor substrate, the first well comprising a first type, the first drain contact being disposed over and adjacent to a second well disposed within the semiconductor substrate, the second well comprising a second type, a junction being disposed between the first well and the second well, wherein a third well having the first type is disposed under the second well and an edge portion of the first well, and wherein the third well forms a junction with the second well.