Patent ID: 9634828
Date: 2017-04-25
CPC Classifications: G06F,G11C,H04L

Claim:
1. A system comprising: a memory controller to control communication with a double data rate memory; and a processor comprising: a plurality of cores; a level 1 instruction cache to cache instructions; a level 1 data cache; a bus interface unit; a plurality of 128-bit registers; a decode unit to decode the instructions from the level 1 instruction cache including an Advanced Encryption Standard (AES) encryption instruction of an instruction set that is to use a first 128-bit source/destination register and a second 128-bit source register; and an execution unit coupled to the decode unit, such that the AES encryption instruction is to cause the execution unit to receive data from the first 128-bit source/destination register and the second 128-bit source register, perform operations for an AES single encryption round including a byte substitution, a shift rows, and an exclusive OR, but omitting a mix columns, and store a result in the first 128-bit source/destination register.