Patent ID: 9606741
Date: 2017-03-28
CPC Classifications: G06F,Y02D

Claim:
1. A system for memory power management comprising: a plurality of real memory portions including a first real memory portion and a second real memory portion, wherein each of the plurality of real memory portions has a dedicated buffer and is a rank of memory located on a dual inline memory module (DIMM) that provides a physical location for data to be stored, including a first dedicated buffer connected to the first real memory portion and a second dedicated buffer connected to the second real memory portion, wherein each of the dedicated buffers is configured to verify channel connectivity, synchronize the DIMMs, and detect errors; a migration bus, the migration bus connecting each of the dedicated buffers; a data management controller, within at least one of the dedicated buffers, the data management controller configured to a memory controller, wherein the plurality of real memory portions is coupled to the memory controller by a memory bus, wherein the memory controller is configured to select the first and second real memory portions, wherein the data management controller is configured to migrate data from the selected first real memory portion to the selected second real memory portion.