Patent ID: 9553108
Date: 2017-01-24
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a base substrate; sources, drains and data lines provided on the base substrate; pixel electrodes and a common electrode; connecting portions; insulating films, the respective insulating films cladding the respective sources, the respective drains and the respective data lines; wherein each insulating film is provided thereon with a first via hole passing therethrough and located above the respective drain, and the respective connecting portions electrically connect the respective drains with the respective pixel electrodes through the respective first via holes; and a passivation layer, at least a part of which is provided between the pixel electrodes and the common electrode, the first via hole passing through the passivation layer; the passivation layer and the common electrode are subsequently laminated above the pixel electrodes, the respective layer connecting portions and the common electrode are provided in the same layer and are insulated from each other; the respective pixel electrodes do not overlap with the patterns of the respective sources, the respective drains and the respective data lines, and the respective connecting portions are electrically connected with the respective pixel electrode via second via holes located above the respective pixel electrode and passing through the passivation layer.