Patent ID: 9627269
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method for fabricating transistors, comprising: providing a substrate having a base and at least a fin on the base; forming an initial gate layer to envelop the fin having a length, the initial gate layer has first side surfaces parallel with a length direction of the fin and second side surfaces perpendicular to the length direction of the fin; forming an initial mask layer on a top surface of the initial gate layer; forming a protective layer on the first side surfaces of the initial gate layer parallel with the length direction of the fin, such that the initial mask layer further covers and connects to a top surface of the protective layer to protect top vertexes of the initial gate layer; removing portions of each of the initial mask layer and the initial gate layer from the fin, thereby providing a mask layer and a gate layer on a length portion of the fin having exposed fin on both sides of the gate layer; forming a sidewall spacer on side surfaces of the protective layer and the second side surfaces of the gate layer; and forming a stress layer in the fin at both sides of the sidewall spacer and the gate layer.