Patent ID: 9716100
Date: 2017-07-25
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a bit line; a power supply line; first and second word lines; first to fourth transistors; first and second capacitors; and first and second retention nodes, wherein first data is input to the first retention node through the first transistor, wherein second data is input to the second retention node through the second transistor, wherein a gate of the third transistor is electrically connected to the first retention node, wherein a first terminal of the third transistor is electrically connected to the bit line, wherein a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor, wherein a second terminal of the fourth transistor is electrically connected to the power supply line, wherein a gate of the fourth transistor is electrically connected to the second retention node, wherein a first terminal of the first capacitor is electrically connected to the first retention node, wherein a second terminal of the first capacitor is electrically connected to the first word line, wherein a first terminal of the second capacitor is electrically connected to the second retention node, wherein a second terminal of the second capacitor is electrically connected to the second word line, wherein the first data and the second data are binary data or multilevel data, and wherein each of the first and second transistors includes an oxide semiconductor in a semiconductor layer.