Patent ID: 9559200
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate having a first conductivity type; an epitaxial structure having the first conductivity type disposed on the substrate; a drain region and a source region disposed in the epitaxial structure; a well region interposed between the drain region and the source region, the well region being disposed in the substrate and the epitaxial structure, the well region having a second conductivity type opposite to the first conductivity type; a first doped region disposed in the well region of the substrate; and a second doped region disposed in the well region of the epitaxial structure; the first doped region and the second doped region being vertically and horizontally offset from each other; each of the doped regions comprising a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.