Patent ID: 9685205
Date: 2017-06-20
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: at least one logic circuit, formed over a semiconductor substrate, including a data input node for receiving a data signal and a clock input node for receiving a clock signal, and comprised of a fin type field-effect transistor; and at least one data buffer, formed over the semiconductor substrate, including a data output node coupled to the data input node of the logic circuit, and comprised of a fin type field-effect transistor, wherein a path of the data signal from the data output node of the data buffer to the data input node of the logic circuit includes gate wiring which is in the same layer as a gate electrode of the fin type field-effect transistors forming the logic circuit and the data buffer, and wherein, as seen in a plane of the semiconductor substrate, a path length of the data signal from the data output node to the data input node is longer than a straight line between the data output node and the data input node.