Patent ID: 9547553
Date: 2017-01-17
CPC Classifications: G06F,G11C,H03M

Claim:
1. A system operative to achieve data resiliency in a shared memory pool, comprising: a plurality of random access memory modules belonging to a shared memory pool and associated respectively with a plurality of data interfaces; a first erasure-coding interface communicatively connected with said plurality of data interfaces using a switching network selected from a group consisting of: (i) a non-blocking switching network, (ii) a fat tree packet switching network, and (iii) a cross-bar switching network; and a first compute element communicatively connected with said first erasure-coding interface, wherein: said plurality of random access memory modules are configured to distributively store a plurality of data sets, such that each data set is distributively stored among at least two of the random access memory modules in a form of a plurality of data fragments coded using a first erasure-coding scheme, and each data fragment is stored on a different one of the at least two random access memory modules; said first compute element is configured to send to the first erasure-coding interface a request for one of the data sets; the first erasure-coding interface is configured to: convert said request into a first plurality of secondary data requests; send, via the switching network, said first plurality of secondary data requests respectively into at least a first sub-set of said plurality of data interfaces; receive as responses, via the switching network, at least a sub-set of said plurality of data fragments associated with said one of the data sets; reconstruct said one of the data sets, using said first erasure-coding scheme, from said data fragments received; and send said reconstruction to the first compute element as a response to said request made; and each of the plurality of data interfaces is configured to: receive, from the first erasure-coding interface, one of said plurality of secondary data requests; extract, from the respective random access memory module, using a random-access read cycle, one of the data fragments associated with said secondary data request; and send the data fragment extracted to said first erasure-coding interface as part of said responses received by the first erasure-coding interface, such that a combined result is that a first period beginning in said sending of the request and ending in said receiving of the response to said request is bounded by 5 (five) microseconds.