Patent ID: 9614040
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor structure, said method comprising: forming at least one strained silicon germanium alloy fin having silicon pedestals located on opposing sidewalls of said at least one strained silicon germanium alloy fin; forming a sacrificial gate structure and a dielectric spacer over a first portion of said at least one strained silicon germanium alloy fin and a first portion of each silicon pedestal; forming, from bottom to top, a raised source/drain (S/D) structure and an interlevel dielectric layer on exposed portions of said at least one strained silicon germanium alloy fin and said silicon pedestals not covered by said sacrificial gate structure and said dielectric spacer; removing said sacrificial gate structure to expose said first portion of each silicon pedestal; removing said first portion of each silicon pedestal, while maintaining a silicon pedestal portion beneath said raised source/drain structure and said interlevel dielectric layer; etching into a sidewall of each silicon pedestal portion to provide silicon pedestal structures, wherein said raised source/drain structure and said interlevel dielectric layer overhang each silicon pedestal structure; and forming a gate spacer, wherein said gate spacer has a first region that is located on said first portion of said at least one strained silicon germanium alloy fin, and said gate spacer has second regions that are present adjacent said first portion of said at least one strained silicon germanium alloy fin that have an upper portion and a lower portion, said lower portion of said gate spacer fills an undercut region beneath said overhang.