Patent ID: 9666296
Date: 2017-05-30
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a memory cell array having a plurality of memory strings disposed in columns, each memory string having a first selection transistor, a second selection transistor, and a plurality of memory cells connected in series between the first and second selection transistors; a plurality of word lines that are each connected across memory strings in adjacent columns to a row of memory cells; a plurality of bit lines that are each connected to first select transistors in a column of memory strings; a plurality of first selection gate lines that are each connected across memory strings in adjacent columns to gates of first selection transistors; a plurality of second selection gate lines that are each connected across memory strings in adjacent columns to gates of second selection transistors; a source line that is connected to each of the second select transistors in the memory cell array; and a controller configured to, during a read operation: