Patent ID: 9673425
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method for manufacturing an active matrix organic light emitting diode (AMOLED) backplane, comprising the following steps: (1) providing a substrate, wherein the substrate comprises a switch thin-film transistor (TFT) zone, a storage capacitor zone, and a drive TFT zone, depositing a first metal layer on the substrate, and conducting a masking operation to patternize the first metal layer so as to form a first gate terminal in the switch TFT zone, a second gate terminal in the drive TFT zone, and a metal electrode in the storage capacitor zone; (2) depositing a gate insulation layer on the first gate terminal, the second gate terminal, and the first metal electrode; (3) sequentially depositing an amorphous silicon layer and a P-type heavily doped amorphous silicon layer on the gate insulation layer, conducting a solid phase crystallization process to have the amorphous silicon layer and the P-type heavily doped amorphous silicon layer crystallized and respectively converted into a poly-silicon layer and a P-type heavily doped poly-silicon layer, and conducting a masking operation to simultaneously subject the poly-silicon layer and the P-type heavily doped poly-silicon layer to patternization so as to respectively form a first poly-silicon section and a second poly-silicon section above the first gate terminal and the second gate terminal; (4) depositing a second metal layer on the first poly-silicon section, the second poly-silicon section, and the gate insulation layer and conducting a masking operation to patternize the second metal layer so as to form first source/drain terminals, second source/drain terminals, and a second metal electrode respectively above the first gate terminal, the second gate terminal, and the first metal electrode; wherein the first source/drain terminals and the second source/drain terminals are respectively in contact with the P-type heavily doped poly-silicon layer of the first poly-silicon section and the second poly-silicon section; and then, with the first source/drain terminals and the second source/drain terminals serving as etch stop layers, the P-type heavily doped poly-silicon layer and a part of the poly-silicon layer that are located in channel sites of the first poly-silicon section and the second poly-silicon section are removed so as to form a first channel and a second channel that are formed in the poly-silicon layer and are respectively located in a middle portion of the first poly-silicon section and a middle portion of the second poly-silicon section; (5) depositing a passivation layer on the first source/drain terminals, the second source/drain terminals, the second metal electrode, and the gate insulation layer; (6) coating a planarization layer on the passivation layer and conducting a masking operation to form a via in the planarization layer and the passivation layer to correspond to the second source/drain terminals; (7) depositing a conductive film on the planarization layer and conducting a masking operation to patternize the conductive film so as to form a pixel electrode layer, wherein the pixel electrode layer is connected through the via to the second source/drain terminals; (8) coating a first organic photoresist layer on the pixel electrode layer and the planarization layer and conducting a masking operation to patternize the first organic photoresist layer so as to form a pixel definition layer; and (9) coating a second organic photoresist layer on the pixel definition layer and the pixel electrode layer and conducting a masking operation to patternize the second organic photoresist layer so as to form photo spacers; wherein the first poly-silicon section, the first gate terminal, and the first source/drain terminals constitute a switch TFT; the second poly-silicon section, the second gate terminal, and the second source/drain terminals constitute a drive TFT; and the first metal electrode and the second metal electrode constitute a storage capacitor.