Patent ID: 9721057
Date: 2017-08-01
CPC Classifications: G06F

Claim:
1. An automated method, implemented as design verification software running on a computer system having a data storage and a processor, for netlist clock domain crossing (CDC) verification, the method comprising: receiving, by a data storage accessible to a processor, (a) a register-transfer-level (RTL) design of an integrated circuit, together with RTL-level CDC constraints for the RTL design, (b) RTL CDC verification results, and (c) a netlist corresponding to the RTL design; migrating, by the processor, the RTL-level CDC constraints to netlist CDC constraints and storing the migrated netlist CDC constraints in the data storage; checking, by the processor, the received netlist for asynchronous clock domain crossings using the migrated netlist CDC constraints to identify correspondences between RTL and netlist level crossings and reporting any CDC violations found in the netlist; and comparing, by the processor, netlist CDC verification results with the received RTL CDC verification results and reporting similarities and differences between the netlist CDC verification results with the received RTL CDC verification results.