Patent ID: 9672922
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A non-volatile semiconductor memory device, comprising: a memory array, comprising a plurality of global blocks, the one global block comprises a plurality of blocks, and the one block comprises a plurality of NAND type strings; a plurality of local bit lines, collectively connected to each of the plurality of blocks in the one global block; a plurality of global bit lines, shared by the plurality of global blocks; and a connecting element, selectively connecting the one global bit line to the m local bit lines, wherein m is an integer greater than 2, and when a read-out operation or a program operation of a selected page is executed in a selected block in the global block, the m local bit lines share the one global bit line via the connecting element, wherein the local bit line comprises a plurality of even-numbered local bit lines and a plurality of odd-numbered local bit lines, the connecting element comprises an even-numbered connecting element selectively connecting the plurality of even-numbered local bit lines to the global bit line and an odd-numbered connecting element connecting the plurality of odd-numbered local bit lines to the global bit line.