Patent ID: 9627509
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate with an active pattern; a gate electrode provided at the active pattern; a gate capping structure disposed above the gate electrode; spacer structures provided on opposite sidewalls of the gate electrode; and contact plugs comprising: wherein the gate capping structure comprises a first gate capping pattern and a second gate capping pattern sequentially stacked on the gate electrode, wherein the first gate capping pattern comprises a horizontally-extended portion extending parallel to a top surface of the substrate and vertically-extended portions extending upward from both edges of the horizontally-extended portion, wherein a top surface of the second gate capping pattern and a top surface of each of the spacer structures are coplanar, and wherein a horizontal distance between the first and the second plugs measured above the top surface of the second capping pattern is greater than a width of the second gate capping pattern.