Patent ID: 9601335
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method for forming a gate cut region, comprising: forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate; forming a dummy gate dielectric and a dummy gate conductor in the trench; planarizing a top surface to reach the hard mask; patterning the dummy gate conductor to form a cut trench in a cut region; recessing the dummy gate conductor to expose a shallow trench isolation region in the substrate; filling the cut trench with a first dielectric material; removing the dummy layer; forming spacers about a gate line; filling gaps using an interlevel dielectric (ILD) deposition; opening up the gate line to expose and remove the dummy gate conductor from the tapered profile gate line trench; depositing a gate dielectric and gate conductor in the tapered profile gate line trench; and forming a gate cap layer to cap a gate structure and provide a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.