Patent ID: 9703562
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. A processor comprising: a decode unit to receive a first instruction and to determine that the first instruction is to be emulated; and emulation mode aware post-decode instruction processor logic coupled with the decode unit, the emulation mode aware post-decode instruction processor logic to process one or more control signals that are to be decoded from an instruction, of a set of one or more instructions, which are to be used to emulate the first instruction, and which are of a same instruction set as the first instruction, differently when in an emulation mode than when not in the emulation mode, wherein the emulation mode aware post-decode instruction processor logic comprises emulation mode aware exceptional condition handler logic to report an exceptional condition, which is to occur while the one or more control signals are processed, to emulation logic, wherein the exceptional condition is one of an interrupt, a fault, a page fault, a memory protection fault, and a division by zero, and wherein the emulation mode aware exceptional condition handler logic is to avoid directly transferring control to an exceptional condition handler in response to the exceptional condition, and wherein one or more instructions of the emulation logic are to transfer control to the exceptional condition handler.