Patent ID: 9608662
Date: 2017-03-28
CPC Classifications: H03M

Claim:
1. A data processing apparatus comprising: floating-point add circuitry to perform a floating-point addition operation for adding or subtracting two floating-point values to generate a result floating-point value; and conversion circuitry to perform a conversion operation to convert a first floating-point value into a second value having a different format to the first floating-point value; wherein the conversion circuitry is capable of performing the conversion operation where the second value is an integer value or a fixed-point value; and the conversion circuitry is physically distinct from the floating-point add circuitry; wherein the conversion circuitry comprises shift circuitry to shift a significand of the first floating-point value by a shift amount depending on the format of the first floating-point value and the format of the second value to generate a shifted significand.