Patent ID: 9629246
Date: 2017-04-18
CPC Classifications: H01L,H05K

Claim:
1. A semiconductor package, comprising: a metal baseplate having a die attach region and a peripheral region; a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate; and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate, the multilayer circuit board comprising a plurality of interleaved signal and ground layers, wherein a first one of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the transistor die, wherein a first one of the ground layers is below the first signal layer, wherein a second one of the signal layers is below the first ground layer and electrically connected to the first signal layer by insulated vias which extend through the first ground layer, wherein a second one of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate.