Patent ID: 9659940
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: preparing a wafer in which a chip area having a first cell area and a first peripheral area and an edge area having a second cell area and a second peripheral area are defined; forming a bottom electrode structure in the first cell area and a dummy structure in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure comprises a plurality of bottom electrodes extending in a first direction perpendicular to a top surface of the wafer in the first cell area of the wafer and first and second supporters extending in parallel with the top surface of the wafer to support the plurality of bottom electrodes, wherein the dummy structure comprises a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area of the wafer, and the second supporter and the second supporter film are at a same level relative to the wafer.