Patent ID: 9712078
Date: 2017-07-18
CPC Classifications: H02M,Y02B

Claim:
1. A synchronous rectification circuit adapted to an electronic transformer, which receives a voltage signal having a sine wave envelope from said electronic transformer, comprising a first transistor switch, a second transistor switch, a third transistor switch, a fourth transistor switch, and a switching control circuit, wherein said first transistor switch, said second transistor switch, said third transistor switch and said fourth transistor switch are configured to be a rectifier bridge; said synchronous rectification circuit has a first input terminal which is a common node between said third transistor switch and said fourth transistor switch; said synchronous rectification circuit has a second input terminal which is a common node between said first transistor switch and said second transistor switch; said switching control circuit detects voltages at said first and second input terminals, and controls on and off states of said first to fourth transistor switches in response to detected voltages, in which said switching control circuit controls an operation state of said second transistor switch in accordance with a voltage at said second input terminal; said switching control circuit controls an operation state of said fourth transistor switch in accordance with a voltage at said first input terminal; and said switching control circuit controls an operation state of said first transistor switch in accordance with operation states of said second and fourth transistor switches; and said switching control circuit controls an operation state of said third transistor switch in accordance with operation states of said second and fourth transistor switches, wherein both said second transistor switch and said fourth transistor switch are inactive in a time interval represented by a dead time signal, said switching control circuit comprises a first switching control circuit, a second switching control circuit, a third switching control circuit, and a fourth switching control circuit, said second switching control circuit comprises a first voltage judgment circuit and a second logic circuit, in which said first voltage judgment circuit receives said voltage at said second input terminal, compares said voltage with a first threshold voltage and a second threshold voltage respectively, and generates a first comparison signal and a second comparison signal, said second logic circuit receives said first comparison signal, said second comparison signal and said dead time signal, generates a second on signal for turning on said second transistor switch in a case that said voltage at said second input terminal is less than said first threshold voltage and said dead time signal is active, and a second off signal for turning off said second transistor switch in a case that said voltage at said second input terminal is larger than said second threshold voltage; said fourth switching control circuit comprises a second voltage judgment circuit and a fourth logic circuit, in which said second voltage judgment circuit receives said voltage at said first input terminal, compares said voltage with a third threshold voltage and a fourth threshold voltage respectively, and generates a third comparison signal and a fourth comparison signal, said fourth logic circuit receives said third comparison signal, said fourth comparison signal and said dead time signal, generates a fourth on signal for turning on said fourth transistor switch in a case that said voltage at said first input terminal is less than said third threshold voltage and said dead time signal is active, and a fourth off signal for turning off said fourth transistor switch in a case that said voltage at said first input terminal is larger than said fourth threshold voltage; said first switching control circuit comprises a first logic circuit, said first logic circuit receives said second off signal and said fourth on signal, performs an AND operation, and generates a first on signal for turning on said first transistor switch; and said first logic circuit receives said second on signal and said fourth off signal, performs an OR operation, and generates a first off signal for turning off said first transistor switch; said third switching control circuit comprises a third logic circuit, said third logic circuit receives said second on signal and said fourth off signal, performs an AND operation, and generates a third on signal for turning on said third transistor switch; said third logic circuit receives said second off signal and said fourth on signal, performs an OR operation, and generates a third off signal for turning off said third transistor switch.