Patent ID: 9715430
Date: 2017-07-25
CPC Classifications: G06F,G11C

Claim:
1. A controller for a solid state drive, the solid state drive comprising a plurality of memory cells, wherein each memory cell comprises a floating gate transistor and each memory cell is adapted to store a symbol when the floating gate transistor is programmed with a threshold voltage associated with that symbol, and wherein each threshold voltage associated with a corresponding symbol is variable over the memory cells of the plurality of memory cells thereby defining a corresponding threshold voltage distribution, the controller comprising: an encoding unit for encoding information bits into encoded bits; a mapping unit for mapping the encoded bits into symbols to be stored, each symbol to be stored being intended to be stored into a respective target memory cell, said mapping unit mapping the encoded bits by associating the symbols to be stored with the target memory cells in such a way that the threshold voltage distributions associated with said symbols to be stored define overlapping regions smaller than a predetermined overlapping region indicative of a bit error rate admitted for the memory cells; a demapping unit for demapping read symbols read from the target memory cells and providing metrics indicative of a distance between the threshold voltage distributions associated with said read symbols, a conversion unit for converting said metrics into an indication of the reliability of the read symbols, and a soft decoding unit for soft decoding the read symbols according to said indication of the reliability of the read symbols thereby obtaining said information bits.