Patent ID: 9632560
Date: 2017-04-25
CPC Classifications: G06F,Y02D

Claim:
1. A computer implemented method comprising: applying a power savings technique to at least a subset of a processor; monitoring pending work items scheduled to be executed by the processor; grouping the pending work items based on the power savings technique, the grouping including delaying a scheduled execution time of at least one of the pending work items to increase an overall number of clock cycles that the power savings technique is applied to the processor; determining that an execution criteria has been met; and executing the pending work items based on the execution criteria being met and the grouping, wherein: the power savings technique is transparent clock gating (TCG), the pending work items include data to be inserted into a pipeline, the grouping results in an idle clock cycle being inserted between two of the pending work items, the executing is by an execution unit on the processor, the power savings technique is applied to the pipeline, and the execution criteria includes receiving a specified number of pending work items.