Patent ID: 9690927
Date: 2017-06-27
CPC Classifications: G01C,G06F,G09C,G11B,H04L,H04N

Claim:
1. A system for providing an authenticating service of a chip, the system comprising: an authentication device comprising an identification engine, a self-test engine, and an intrinsic component associated with a chip that is unique to the chip, results from manufacturing variability, and has an intrinsic feature; the self-test engine configured to retrieve the intrinsic feature and communicate the intrinsic feature to the identification engine; the identification engine further configured to receive the intrinsic feature, generate a first authentication value using the intrinsic feature, and store the authentication value in memory; the self-test engine further configured to generate a second authentication value using an authentication challenge, wherein the authentication challenge is based on an address domain in the intrinsic component, the self-test engine further configured to adjust a word line voltage for a plurality of DRAM cells in order to generate a specified fail count of a subset of DRAM cells from the plurality of DRAM cells, generate a vector pattern corresponding to the subset of DRAM cells, and store the vector fail pattern in a register, and wherein the intrinsic feature is a bit pattern generated from the specified fail count; the identification engine further comprising a compare circuitry configured to compare the first authentication value and the second authentication value; and the compare circuitry further configured to generate an authentication output value based on the results of the compare of the first authentication value and the second authentication value.