Patent ID: 9666699
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate; a buried oxide layer disposed on the substrate; a semiconductor layer having a first conduction type disposed on the buried oxide layer; a first well doped region having the first conduction type disposed in the semiconductor layer; a second well doped region and a third well doped region having a second conduction type opposite to the first conduction type, disposed close to opposite sides of the first well doped region, wherein the second well doped region and the third well doped region are respectively separated from the first well doped region by a first distance and a second distance; an isolation feature covering the first well doped region and the third well doped region; a poly field plate having the first conduction type or the second conduction type disposed on the isolation feature and over the semiconductor layer between the first well doped region and the third well doped region; a first anode doped region having the second conduction type disposed on the second well doped region; a second anode doped region having the first conduction type disposed on the second well doped region; a third anode doped region having the first conduction type disposed on the second well doped region, wherein the second anode doped region is positioned directly on the third anode doped region; and a first cathode doped region having the second conduction type coupled to the third well doped region.