Patent ID: 9558002
Date: 2017-01-31
CPC Classifications: G06F

Claim:
1. A computation apparatus, comprising: a pipelined computation unit, comprising a plurality of pipeline stages, arranged in a relative order, in which outputs from a prior stage are inputs to a later stage, and wherein an intermediate stage is also coupled to produce an output that can be fed back to a prior stage, the pipeline stages configurable to process a single instruction that defines two or more separable computation portions by following one of the portions by another of the portions in time through the plurality of pipeline stages; control circuitry configured to maintain state data describing status of processing of each portion that has begun execution in the pipelined computation unit and that requires iterative refinement, the control circuitry configured to scheduler circuitry configured for scheduling instructions for execution on the pipelined computation unit, the scheduler coupled with the control circuitry to receive the control signal and for determining, based on the control signal, whether to allow an instruction that defines two or more separable portions of computation, each requiring multiple pipeline iterations, to be available for scheduling.