Patent ID: 9728481
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A system, comprising: a first high-power chip disposed on a first side of a chip-packaging substrate; a first thermally insulating layer and a second thermally insulating layer; a first low-power chip embedded in the chip-packaging substrate between the first thermally insulating layer and the second thermally insulating layer and electrically connected to the first high-power chip, and a heat-distribution layer that includes one or more layers of metallic foil and is embedded in the chip-packaging substrate between the first thermally insulating layer and the second thermally insulating layer and adjacent to the first low-power chip, wherein the heat-distribution layer extends from a first edge of the chip-packaging substrate to a second edge of the chip packaging substrate and does not substantially vary in depth, wherein the high-power chip generates at least 10 W of heat and the low-power chip generates less than 5 W of heat.