Patent ID: 9672909
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A method of controlling a resistive memory cell having binary values of 0 and 1, comprising: defining a resistance threshold value for the memory cell, wherein the memory cell is identified by a circuit as erased having a 0 value if a detected resistance of the memory cell is above the resistance threshold value and identified by the circuit as programmed having a 1 value if the detected resistance of the memory cell is below the resistance threshold value; providing the memory cell in a virgin state with no filament formed therein, the virgin state of the memory cell defining a maximum resistance value of the memory cell; forming a filament across an electrolyte switching region of the resistive memory cell by applying an electrical charge, wherein the memory cell having the formed filament has a first resistance below the resistance threshold value; erasing the memory cell by partially shrinking the filament to define an erased state having a 0 value and having a second resistance greater than the first resistance and above the resistance threshold value, but substantially less than the maximum resistance value of the memory cell; programming the memory cell to a quasi-erased state having a 0 value and having a third resistance between the first and second resistances, and above the resistance threshold value such that the memory cell is identified by the circuit as erased; maintaining the memory cell in the quasi-erased state until a reprogramming of the memory cell; and programming the memory cell to a programmed state having a 1 value and having a fourth resistance between the first and third resistances, and below the resistance threshold value such that the memory cell is identified by the circuit as programmed.