Patent ID: 9659957
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a first stacked body including a plurality of first electrode layers and a plurality of first insulating layers, the first electrode layers separately stacked on each other, the first insulating layers provided between the first electrode layers; a second stacked body including a plurality of second electrode layers and a plurality of second insulating layers, the second electrode layers separately stacked on each other, the second insulating layers provided between the second electrode layers, the second stacked body separated from the first stacked body in a first direction crossing a stacking direction of the first stacked body; a first insulating portion provided between the first stacked body and the second stacked body, the first insulating portion provided integrally to the first insulating layers and the second insulating layers; a first interconnect portion extending in the stacking direction and a second direction, the second direction crossing the stacking direction and the first direction; and a second interconnect portion extending in the stacking direction and the second direction, the first interconnect portion, the first stacked body, the first insulating portion, the second stacked body, and the second interconnect portion being provided in sequence in the first direction.