Patent ID: 9715427
Date: 2017-07-25
CPC Classifications: G06F,Y02D

Claim:
1. A memory control apparatus that processes with a pipeline method a read request for requesting to read out payload data from a memory having a plurality of addresses each storing data of a predetermined data width, the memory in which error correcting data is set for each payload data of the data width, payload data of the data width and the error correcting data being correlated with each other are stored across two adjacent addresses, and the data is read out in address units, the memory control apparatus comprising: a cache area in which the data that has been read out from the memory is cached; a read request input unit that receives as input a read request for requesting to read out the payload data of an integral multiple of the data width; a cache determination unit that determines whether or not data of any one of two or more read out candidate addresses has been cached or is going to be cached in the cache area, the two or more read out candidate addresses being addresses in which are stored requested payload data which is payload data being requested by the read request received as input by the read request input unit, and corresponding error correcting data which is error correcting data used for error correction of the requested payload data; and a command output unit that, when the cache determination unit determines that data of any one of the two or more read out candidate addresses has been cached or is going to be cached in the cache area, outputs to the memory a partial read command to instruct to read out data from an address other than a cache address, after a predetermined delay time has elapsed from timing at which the partial read command can be outputted to the memory, the cache address being an address of the data that has been cached or is going to be cached in the cache area out of the two or more read out candidate addresses.