Patent ID: 9721939
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a second conductivity type first semiconductor region disposed in a surface layer of a first conductivity type semiconductor substrate; an active region disposed in a surface layer of the first semiconductor region, the active region being part of a protected device; a first conductivity type second semiconductor region, of a higher concentration than the semiconductor substrate, disposed enclosing the active region, straddling, and in contact with, the first semiconductor region and semiconductor substrate; a first conductivity type third semiconductor region, of a higher concentration than the second semiconductor region, disposed in a surface layer of the second semiconductor region; and a second conductivity type fourth semiconductor region disposed in a surface layer of the second semiconductor region between the third semiconductor region and active region, wherein a guard ring is configured of the second semiconductor region and third semiconductor region, a parasitic bipolar transistor is configured of the fourth semiconductor region, second semiconductor region, and first semiconductor region, and the parasitic bipolar transistor forms an electrostatic discharge (ESD) surge protection element.