Patent ID: 9741791
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: a substrate of a first conductivity type; a lower epitaxial layer having said first conductivity type disposed over said substrate; an upper epitaxial layer having said first conductivity type disposed over said lower epitaxial layer; a doped region having said first conductivity type disposed in said lower epitaxial layer, extending at least up to a top of said lower epitaxial layer and at least down to a bottom of said lower epitaxial layer, a bulk resistivity of said doped region and a bulk resistivity of said substrate being less than a bulk resistivity of said lower epitaxial layer and a bulk resistivity of said upper epitaxial layer; a shallow component disposed in said upper epitaxial layer above said doped region; and a deep component disposed in said upper epitaxial layer and said lower epitaxial layer, outside of said doped region.