Patent ID: 9711693
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a member comprising a first lead electrode and a second lead electrode; a semiconductor stack structure disposed on the member, the semiconductor stack structure comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a plating layer configured to bond the semiconductor stack structure to the member; spacer electrodes respectively disposed on the first and second lead electrodes; and a first wavelength converter that covers at least side surfaces of the semiconductor stack structure, wherein the first electrode comprises a first electrode pad and a first additional electrode disposed on the first electrode pad, wherein the second electrode comprises a second electrode pad and a second additional electrode disposed on the second electrode pad, wherein the plating layer comprises a first plating layer configured to bond the first additional electrode to the spacer electrode on the first lead electrode, and a second plating layer configured to bond the second additional electrode to the spacer electrode on the second lead electrode, wherein the first wavelength converter extends to a space between the semiconductor stack structure and the member and covers the semiconductor stack structure, and wherein the first and second plating layers cover a top surface and only a portion of respective side surfaces of the spacer electrodes.