Patent ID: 9543240
Date: 2017-01-10
CPC Classifications: H01L,H02M

Claim:
1. A power supply system comprising: a leadframe having a plurality of leads and a pad with a first and a second pad surface, the first pad surface having a recessed portion and an un-recessed portion, the recessed portion having a depth and an outline suitable for attaching a plurality of semiconductor chips, the pad tie-able to a switch node terminal of the system; a driver-and-controller chip attached to the second pad surface, said driver-and-controller chip having a plurality of terminals tied by bonding wires to respective leads of the lead frame; package material encapsulating the driver-and-controller chip, the wires and the second surface of the pad and leads, but leaving the first pad surface and at least some of the plurality of leads un-encapsulated creating a pre-molded carrier; a first Field Effect Transistor (FET) chip having a drain terminal of the first FET chip attached to the recessed portion of the first pad surface, and further having a source terminal of the first FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface, the source terminal of the first FET chip tie-able to a board terminal as a grounded output terminal of the system; and a second FET chip having a source terminal of the second FET chip attached to the recessed portion of the first pad surface, and further having a drain terminal of the second FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface, the drain of the second FET chip tie-able to a board terminal as an input terminal of the system.