Patent ID: 9559093
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor device, comprising the steps of: forming a GaN FET by a process comprising the steps of: providing a substrate; forming a low-defect layer comprising gallium nitride over said substrate; forming a barrier layer comprising Al forming a gate over said barrier layer; and forming source and drain contacts that extend into the barrier layer; forming an overvoltage clamping component, and electrically coupling a first end of said overvoltage clamping component to a drain node of said GaN FET, said overvoltage clamping component having a breakdown voltage less than a breakdown voltage of said GaN FET; forming a voltage dropping component, electrically coupling a first end of said voltage dropping component to a second end of said overvoltage clamping component, and electrically coupling a second end of said voltage dropping component to a terminal for an off-state bias potential.