Patent ID: 9543976
Date: 2017-01-10
CPC Classifications: H03M

Claim:
1. A time-interleaved analog-to-digital (AD) converter comprising: N AD converters that each convert an analog input voltage into a digital output value, N representing an integer equal to or larger than two; a frequency divider that receives a clock signal and applies 1/N frequency division to the received clock signal to generate N frequency-divided clock signals; at least (N−1) variable delay circuit that adjusts delay time for at least (N−1) frequency-divided clock signal included in the N frequency-divided clock signals to be supplied to the N AD converters; a low pass filter circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal, or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N−1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.