Patent ID: 9613972
Date: 2017-04-04
CPC Classifications: G03F,H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: forming a pattern group on a substrate, the substrate being divided into first and second regions, each pattern including a silicon layer; forming an insulating layer over the substrate to cover the pattern group, wherein a deposition thickness of the insulating layer on the second region is larger than that of the insulating layer on the first region; forming an insulating pattern by etching the insulating layer, the insulating pattern partially exposing the silicon layer on the first region and blocking the silicon layer on the second region; converting the exposed silicon layer on the first region to a silicide layer while the blocked silicon layer on the second region is protected from the conversion; and performing a subsequent process using, as an overlay vernier, at least a portion of the pattern group formed on the second region.