Patent ID: 9709627
Date: 2017-07-18
CPC Classifications: G01R

Claim:
1. An interposer comprising: (a) a test access port having a test data input lead, a test data output lead, a test clock lead, a test mode select lead, and test control leads; (b) functional circuitry leads that include an address bus, a data bus, functional control signals, a voltage bus, a ground bus, and analog signals; (c) monitor trigger circuitry having inputs coupled to the functional circuitry leads, the test data input lead, and the test control leads, and having an output coupled to the test data output lead, and monitor control outputs; (d) address and data bus monitor circuitry having inputs coupled to the functional circuitry leads, to the monitor control outputs, an input coupled to the test data input lead, an input coupled to the test control leads, and an output coupled to the test data output lead; and (e) voltage and analog signal monitor circuitry having inputs coupled to the functional circuitry leads, to the monitor control outputs, an input coupled to the test data input lead, an input coupled to the test control leads, and an output coupled to the test data output lead.