Patent ID: 9589930
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a first chip stack and a second chip stack mounted side by side on a package substrate and each connected to the package substrate in a wire bonding manner, wherein the first chip stack comprises a plurality of first semiconductor chips that are stepwise stacked on the package substrate to have a descending staircase structure from the first chip stack toward the second chip stack, wherein the second chip stack comprises a plurality of second semiconductor chips that are stepwise stacked on the package substrate to have a descending staircase structure from the second chip stack toward the first chip stack, wherein the first semiconductor chips comprise bonding pads on first edge regions of the top surfaces of thereof, respectively, wherein the top surfaces of first semiconductor chips include second edge regions, respectively, wherein the second edge regions of the first semiconductor chips comprise no bonding pads, wherein the first edge regions of the first semiconductor chips are aligned with a first virtual line in a plan view, wherein the second semiconductor chips comprise bonding pads, respectively, and wherein the bonding pads of second the semiconductor chips are not aligned with the first virtual line in a plan view.