Patent ID: 9653167
Date: 2017-05-16
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device, comprising: in the case that three directions intersecting each other are assumed to be a first direction, a second direction, and a third direction, a memory cell array including a plurality of memory cells and a first wiring line layer and second wiring line layer disposed sequentially above the memory cells in the third direction, the first wiring line layer including a first wiring line and a first dummy wiring line that are aligned in the first direction and have the second direction as a longer direction, and the second wiring line layer including a second wiring line and a second dummy wiring line that are aligned in the first direction and have the second direction as a longer direction; and a control circuit that controls an access operation on the memory cells, the first wiring line layer including a plurality of the first wiring lines and a plurality of the first dummy wiring lines aligned alternately one at a time in the first direction, the second wiring line layer including a plurality of the second wiring lines and a plurality of the second dummy wiring lines aligned alternately one at a time in the first direction, and during the access operation by the control circuit, the first wiring line being electrically connected to one of the memory cells, the second wiring line being electrically connected to another of the memory cells, and the first dummy wiring line and the second dummy wiring line being fixed at a certain first potential.