Patent ID: 9741649
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. An integrated circuit (IC) package, comprising: a first substrate having a backside surface and a top surface with a cavity disposed therein, the cavity having a floor defining a front side surface; a plurality of first electroconductive contacts disposed on the front side surface; a plurality of second electroconductive contacts disposed on the back side surface; a plurality of first electroconductive elements penetrating through the first substrate and coupling selected ones of the first and second electroconductive contacts to each other; one or more first dies each of which contains an IC electroconductively coupled to corresponding ones of the first electroconductive contacts, an entire top surface of each first die being coplanar with all of the top surface of the first substrate outside the cavity; a second substrate having a bottom surface permanently sealingly attached to the top surface of the first substrate outside the cavity, for reducing warpage of the first substrate; and a dielectric material disposed in the cavity and encapsulating each first die.