Patent ID: 9590020
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A manufacture method of an AMOLED back plate, sequentially deposing a buffer layer, an amorphous silicon layer on a substrate, and crystallizing and converting the amorphous silicon layer to be a polysilicon layer, and patterning the polysilicon layer, and then deposing a P type heavy doped micro silicon layer, and implementing a photo process to define a position of a channel, and etching the P type heavy doped micro silicon layer to form a source/a drain, and thereafter, sequentially forming a gate isolation layer, a gate, an interlayer insulation layer, a metal source/a metal drain, a flat layer, an anode, a pixel definition layer and a photo spacer; the source/the drain and the gate do not overlap in the horizontal direction and are mutually spaced, and comprising the following steps: step 1, providing a substrate and deposing the buffer layer on the substrate; step 2, deposing the amorphous silicon layer on the buffer layer, and implementing an excimer laser annealing process to the amorphous silicon layer to make the amorphous silicon layer to be crystallized and converted to be the polysilicon layer; step 3, patterning the polysilicon layer with photo and etch processes to form a first polysilicon section and a second polysilicon section; step 4, deposing the P type heavy doped micro silicon layer on the buffer layer, the first polysilicon section and the second polysilicon section, and implementing the photo process to define the position of the channel, and etching the P type heavy doped micro silicon layer to pattern the P type heavy doped micro silicon layer for forming the source/the drain on the first polysilicon section and an electrode on the second polysilicon section except an area corresponding to the channel; step 5, deposing and patterning the gate isolation layer on the buffer layer, the source/the drain and the electrode; step 6, deposing and patterning a first metal layer on the gate isolation layer to form the gate and a metal electrode, wherein the gate is above the channel, and the source/the drain and the gate are mutually spaced with a certain distance in the horizontal direction; and step 7, sequentially forming the interlayer insulation layer, the metal source/the metal drain, the flat layer, the anode, the pixel definition layer and the photo spacer on the gate isolation layer, the gate and the metal electrode with deposition, photo and etch processes, wherein the metal source/the metal drain are electrically connected to the source/the drain; and the anode is electrically connected to the metal source/the metal drain; wherein the first polysilicon section, the source/the drain, the gate and the metal source/the metal drain construct a drive TFT, and the second polysilicon section, the electrode and the metal electrode construct a storage capacitor.