Patent ID: 9678560
Date: 2017-06-13
CPC Classifications: G06F

Claim:
1. A system comprising: a processor to execute a sleep state entrance routine; a system memory to store system information in response to the processor executing the sleep state entrance routine; one or more audio jack sockets; detection and control logic to generate an audio input device wake event signal and an audio output device wake event signal as separate signals within the system, the audio input device wake event signal being generated in response to detection of an audio plug being inserted into the one or more audio jack sockets for an audio device that sends audio information into the system, the audio output device wake event signal being generated in response to detection of an audio plug being inserted into the one or more audio jack sockets for an audio device that receives audio information from the system, wherein the audio input device wake event signal is distinguishable from the audio output device wake event signal so that a basic input/output system (BIOS) of the system: 1) loads an audio input codec during a power up sequence in response to the audio input device wake event signal without interrogation by a power management unit as to the cause of the wake up and, 2) loads an audio output codec during a power up sequence in response to the audio output device wake event signal without interrogation by the power management unit as to the cause of the wake up.