Patent ID: 9548242
Date: 2017-01-17
CPC Classifications: B82Y,C25D,H01L

Claim:
1. A method of fabricating a nanoscale interconnect by electrical field directed assembly of nanoelements, the method comprising the steps of: (a) providing a nanosubstrate comprising a base layer, a conductive layer deposited onto the base layer, and an insulating layer deposited onto the conductive layer, the insulating layer comprising a via, the via forming a void in the insulating layer and defining a pathway through the insulating layer that exposes the conductive layer; (b) immersing the nanosubstrate in an aqueous suspension of nanoelements; (c) applying an electrical field between the conductive layer and an electrode in the aqueous suspension, the electrical field consisting of the sum of a DC voltage and an AC voltage, whereby the nanoelements from said suspension are assembled on the conductive layer; and (d) withdrawing the nanosubstrate from the aqueous suspension while continuing to apply said electrical field between the conductive layer and the electrode; wherein said assembled nanoelements form a nanoscale interconnect having an electrical connection with the conductive layer.