Patent ID: 9721654
Date: 2017-08-01
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a first interconnection; a second interconnection; a charge storage portion provided between the first interconnection and the second interconnection, the charge storage portion being capable of accumulating an electron; a tunnel film provided between the first interconnection and the charge storage portion, the tunnel film including: a fine particulate layer including conductive fine particulates satisfying the Coulomb blockade condition, a first tunnel insulating layer provided between the first interconnection and the fine particulate layer, and a second tunnel insulating layer provided between the fine particulate layer and the charge storage portion; and a block film provided between the charge storage portion and the second interconnection, the block film having an energy structure in which no concave portion with an energy barrier lower than energy barriers on both sides thereof is present.