Patent ID: 9543983
Date: 2017-01-10
CPC Classifications: G06F,H03M

Claim:
1. A decoding method, for a rewritable non-volatile memory module comprising a plurality of memory cells, the decoding method comprising: sending a read command sequence for reading the plurality of memory cells so as to obtain a plurality of first bits; determining whether the first bits have at least one first error; if the first bits have the at least one first error, executing a first iteration decoding procedure on the first bits so as to obtain a plurality of second bits, and recording first bit flipping information of the first iteration decoding procedure; determining whether the second bits have at least one second error; if the second bits have the at least one second error, executing a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain a plurality of third bits; if the second bits do not have the at least one second error, outputting the second bits; recording second bit flipping information of the second iteration decoding procedure according to the first bit flipping information; determining whether the third bits have at least one third error; if the third bits have the at least one third error, executing a third iteration decoding procedure on the third bits according to the second bit flipping information so as to obtain a plurality of fourth bits; and if the third bits do not have the at least one third error, outputting the third bits, wherein the second bit flipping information indicates a specific bit among the third bits having a bit value different from an original bit value of said specific bit among the first bits.