Patent ID: 9627402
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a stacked body including a plurality of electrode layers stacked separated from each other and an inter-electrode insulating layer between the electrode layers; a semiconductor member extending in a stacking direction of the stacked body and penetrating the stacked body; a tunnel insulating layer provided on a side surface of the semiconductor member; a charge storage layer provided on a side surface of the tunnel insulating layer; a charge block layer provided on a side surface of the charge storage layer and containing oxygen; and an electrode antioxidant layer provided between the charge block layer and the electrode layer and having a composition different from that of the electrode layer, wherein as viewed from a direction vertical to the stacking direction, the charge storage layer and the charge block layer that are stacked in a direction of the semiconductor member on a side surface side of the electrode antioxidant layer project in a direction of the tunnel insulating layer beyond the charge storage layer and the charge block layer that are stacked in the direction of the semiconductor member on a side surface side of the inter-electrode insulating layer.