Patent ID: 9653177
Date: 2017-05-16
CPC Classifications: G11C

Claim:
1. An OTP non-volatile memory, comprising: a memory array comprising M×N memory cells, wherein the memory array is connected with M word lines and 2N bit lines, and the 2N bit lines are divided into N bit line pairs; a controlling circuit comprising a voltage generator, a word line driver, a column driver and a timing controller, wherein the voltage generator provides plural supply voltages to the memory array, the word line driver is connected with the M word lines for determining one of the M word lines as a selected word line, the column driver generates N column decoding signals and activates one of the plural column decoding signals at a time, and the timing controller generates a precharge signal, a reset signal and an enable signal; a precharge circuit connected with the 2N bit lines, wherein when the precharge signal is activated, the precharge circuit provides a precharge voltage to the 2N bit lines; a column selector connected with the 2N bit lines, a reference line and a data line, wherein the column selector determines one of the N bit line pairs as a selected bit line pair according to the N column decoding signals, so that a first bit line of the selected bit line pair is connected with the data line and a complementary first bit line of the selected bit line pair is connected with the reference line; a reset circuit connected with the data line and the reference line, wherein when the reset signal is activated, the reset circuit provides a reset voltage to the data line and the reference line, wherein the precharge voltage is higher than the reset voltage; and a sense amplifier connected with the data line and the reference line, wherein when the enable signal is activated, the sense amplifier generates an output signal according to a result of comparing a voltage level of the data line with a comparing voltage of the reference line.