Patent ID: 9558801
Date: 2017-01-31
CPC Classifications: G11C,H03K

Claim:
1. A data holding circuit comprising: a latch circuit having a first terminal and a second terminal, a logical value held at the first terminal being changed according to a value to be held by the data holding circuit, and the second terminal holding an inverted logical value of the logical value held at the first terminal; and a storing circuit which stores the logical values held at the first terminal and the second terminal in response to a write signal, and sets the logical values held at the first terminal and the second terminal to the stored logical values in response to a read signal, wherein the storing circuit includes two Magnetic Tunnel Junction elements which are connected in series between the first terminal and the second terminal and in reverse directions to each other, and the storing circuit includes a write circuit which flows a write current from one of the first terminal and the second terminal to the other of the first terminal and the second terminal via the two Magnetic Tunnel Junction elements in response to the write signal, a potential of the one of the first terminal and the second terminal being higher than a potential of the other of the first terminal and the second terminal, and sets the two Magnetic Tunnel Junction elements in conditions corresponding to a direction of the write current.