Patent ID: 9711415
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductor substrate; isolation features to separate different regions on the substrate; a p-type field-effect transistor (pFET) core region having a first gate stack on the substrate, the first gate stack including an interfacial layer, a high k (HK) dielectric layer, and a capping layer of a first material and a capping layer of a second material disposed between the interfacial layer and the HK dielectric layer, the first material comprises a p-type metal oxide and the second material comprises an n-type metal oxide, and wherein the capping layer of the second material is directly on the capping layer of the first material and wherein the capping layer of the first material and the capping layer of the second material have a combined first thickness, and wherein the capping layer of the second material in the pFET core region has a first capping layer thickness; an input/output pFET (pFET IO) region having a second gate stack on the substrate, the second gate stack including an interfacial layer, a HK dielectric layer, and a capping layer of the first material between the interfacial layer and the HK dielectric layer, wherein the interfacial layer of the second gate stack has a thickness that is greater than a thickness of the interfacial layer in the first gate stack, and wherein a capping layer of the second material in the pFET region has a second capping layer thickness that is smaller than the first capping layer thickness; an n-type field-effect transistor (nFET) core region having a third gate stack on the substrate, the third gate stack including an interfacial layer, a HK dielectric layer directly on a capping layer of the second material, and wherein the capping layer of the second material in the nFET core region has a third capping layer thickness that is equal to the combined first thickness; an input/output nFET (nFET IO) region having a fourth gate stack on the substrate, the fourth gate stack including an interfacial layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer directly on the capping layer of the second material, wherein the capping layer of the second material in the nFET IO region has a fourth capping layer thickness that is greater than the first capping layer thickness and smaller than the third capping layer thickness; and a high-resistor region having a fifth gate stack on the substrate, the fifth gate stack including an interfacial layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer directly on the capping layer of the second material.