Patent ID: 9684461
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A memory system comprising: one or more memory devices coupled to a memory controller via a memory interface bus; the memory controller operative to receive one or more memory requests via an interconnect, the one or more memory requests comprising one or more read operations with a maximum read data size and a variable setting specifying one or more reduced read data sizes; the memory controller operative to track utilization of the memory interface bus for reads from the one or more memory devices for a selection of the one or more memory requests during a time window; and the memory controller, responsive to detecting utilization of the memory interface bus for reads during the time window reaches a memory utilization threshold, operative to dynamically select one of the one or more reduced read data sizes for a size of data to be accessed from the one or more memory devices for at least one read operation from among the one or more read operations with the maximum read data size and the variable setting specifying the one or more reduced read data sizes, wherein the selected one of the one or more reduced data sizes for the at least one read operation is less than the maximum read data size and greater than zero.