Patent ID: 9621116
Date: 2017-04-11
CPC Classifications: H03F

Claim:
1. An active load circuit comprising: a first transistor placed between a first node and a first reference node; a second transistor placed between a second node and the first reference node; a first resistor of which one end is connected to gate of the first transistor and the other end is connected to the first node; a second resistor of which one end is connected to gate of the second transistor and the other end is connected to the second node; a third transistor placed between the first transistor and the first reference node; a fourth transistor placed between the second transistor and the first reference node; a fifth transistor, together with the second transistor, forming a current mirror circuit and placed between a third node and the first reference node; a sixth transistor, together with the first transistor, forming a current mirror circuit and placed between a fourth node and the first reference node; a seventh transistor placed between the fifth transistor and the first reference node; an eighth transistor placed between the sixth transistor and the first reference node; and a line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.