Patent ID: 9634043
Date: 2017-04-25
CPC Classifications: G02F,H01L

Claim:
1. A method for manufacturing an array substrate, comprising: forming a pattern of an active layer and a gate insulating layer on a base substrate; forming a metal film on the gate insulating layer, patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line, in which the gate line or the data line is disconnected at an intersection of the gate line and the data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole through which the source electrode and the active layer are partially exposed, a drain contact hole through which the drain electrode and the active layer are partially exposed, and bridge structure contact holes through which the disconnected gate line or data line is partially exposed; and forming a transparent conductive film on the base substrate, removing partially the transparent conductive film to form a source contact portion electrically connected with the source electrode and the active layer in the source contact hole and a drain contact portion electrically connected with the drain electrode and the active layer in the drain contact hole, forming a pixel electrode electrically connected with the drain contact portion on the passivation layer on the drain electrode, and forming a bridge structure electrically connected with the disconnected gate line or data line in the bridge structure contact holes and on the passivation layer above.