Patent ID: 9741413
Date: 2017-08-22
CPC Classifications: G11C,H01L

Claim:
1. For an integrated circuit having an array of SRAM cells interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each SRAM cell having a pair of cross-coupled thyristors, each thyristor having first and second semiconductor regions intermediate an anode and a cathode, a first intermediate region of one thyristor connected to the second intermediate region of the other thyristor and a second intermediate region of the one thyristor connected to the first intermediate region of the other thyristor, each thyristor having an anode connected to a first supply voltage and a cathode connected to a second supply voltage, and a pair of bipolar select transistors, each bipolar select transistor having a collector region connected to one of a complementary bit line pair, and an emitter region connected to the first intermediate region of one of the thyristors, and having a base region connected to a word line, a method of reading an SRAM cell in the array comprising: selecting at least one SRAM cell; raising the first supply voltage from a standby mode voltage of the at least one selected SRAM cell; and raising the voltage on the word line connected to the bipolar select transistors of the at least one selected SRAM cell with a delay after the step of raising the first supply voltage; whereby a state of the at least one selected SRAM cell is read through a complementary bit line pair connected to the bipolar select transistors of the at least one selected SRAM cell.