Patent ID: 9728544
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming split gate structures, each including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate, the substrate including the cell region and a logic region adjacent to the cell region; sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region; removing the metal gate film from at least a portion of the cell region and the logic region; forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed; forming a gate electrode film on the logic region and the cell region; and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region by patterning the first and second gate insulating films, the gate electrode film, and a residue of the metal gate film.