Patent ID: 9659932
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device comprising: patterning a semiconductor substrate to form a plurality of fins including at least one first fin and at least one second fin, wherein each of the first fin and second fin comprise a first portion and a second portion; etching the first portion of the second fin to form a recess in the second fin; forming a gate electrode structure overlying the first portion of the plurality of fins, the gate electrode structure comprising a gate electrode, and a gate dielectric layer between the gate electrode and the plurality of fins, wherein the gate electrode structure is in direct physical contact with the first portion of the first fin and the gate electrode structure is spaced apart from the first portion of the second fin; and forming a first electrode overlying the second portion of the plurality of fins, wherein the first electrode is in electrical contact with the second portion of the plurality of fins.