Patent ID: 9665505
Date: 2017-05-30
CPC Classifications: G06F

Claim:
1. An apparatus comprising: a motherboard including multiple sockets, each socket configured to accept an integrated circuit; a first integrated circuit in a first socket of the motherboard, the first integrated circuit including one or more cores and at least one buffer; a second integrated circuit in a second socket of the motherboard, the second integrated circuit including one or more cores and at least one buffer; communication circuitry included on the motherboard configured to transfer messages to buffers of integrated circuits coupled to different sockets; wherein a first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry, where at least one first type of instruction corresponds to a first operation that is performed by the second core without requiring any instructions to be transmitted through the communication circuitry to complete the first operation, and at least one second type of instruction corresponds to a second operation that is performed by the second core requiring at least one message to be transmitted through the communication circuitry to complete the second operation; and wherein the buffer of the second integrated circuit is large enough to store a maximum number of instructions of the second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of the first type.