Patent ID: 9646669
Date: 2017-05-09
CPC Classifications: G11C

Claim:
1. A memory device, comprising: a plurality of memory elements configured to store data; and programming configuration logic configured to program each of the memory elements to a first data value during a first programming phase or a second data value during a second programming phase that is subsequent to the first programming phase by enabling connections to a first voltage or a second voltage for each of the memory elements; wherein a first memory element of the plurality of memory elements includes first and second terminals configured to receive the first voltage or the second voltage based on the connections enabled by the programming configuration logic; wherein the first voltage is an operating voltage and the second voltage is a reference voltage, and wherein to program a desired data value for the first memory element: during the first programming phase, the programming configuration logic is configured to enable the first memory element to receive the second voltage at the first terminal and the first voltage at the second terminal where the first data value is the desired data value, and during the second programming phase, the programming configuration logic is configured to enable the first memory element to receive the first voltage at the first terminal and the second voltage at the second terminal where the second data value is the desired data value; wherein the programming configuration logic is further configured to setup each of the memory elements in a setup phase that is prior to the first programming phase, wherein the second terminal is configured to receive the second voltage during the setup phase, and wherein the first terminal is configured to receive the first voltage during the setup phase for programming of the first data value, or receive the second voltage during the setup phase for programming of the second data value.