Patent ID: 9653171
Date: 2017-05-16
CPC Classifications: G06F,G11C

Claim:
1. An apparatus comprising: a plurality of strings of memory cells, the memory cells formed in a plurality of tiers, the strings of memory cells arrange in memory blocks, wherein a memory block among the memory block includes a first partial block and a second partial block, the first partial block including first memory cells in a first tier of the plurality of tiers, the second partial block including second memory cells in the first tier of the plurality of tiers; global access lines, each of the global access lines shared by memory cells in a respective tier of the plurality of tiers; a first local access line shared by the first memory cells, the first local access line coupled to a global access line of the global access lines through a first string driver; and a second local access line shared by the second memory cells, the second local access line coupled to the global access line through a second string driver.