Patent ID: 9697911
Date: 2017-07-04
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor storage device comprising: a plurality of memory cells provided in a matrix manner; a plurality of write word lines and a plurality of read word lines, the write word lines and the read word lines being respectively provided in a plurality of rows of the plurality of memory cells; a plurality of write bit line pairs and a plurality of read bit lines, the write bit line pairs and the read bit lines being respectively provided in a plurality of columns of the plurality of memory cells; a write word line driver that activates any of the plurality of write word lines; a read word line driver that activates any of the plurality of read word lines; a write selection circuit that selects any of the plurality of write bit line pairs; a read selection circuit that selects any of the plurality of read bit lines; an input driver that outputs write data to a write bit line pair selected by the write selection circuit; a sense amplifier that amplifies a potential difference between a reference potential and a potential of a read bit line selected by the read selection circuit; and a test control circuit that activates, during a test mode, any of the write word lines, and further activates, after a lapse of a predetermined period of time, the read word line in the same row as the any of the write word lines.