Patent ID: 9632825
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A method for scheduling instructions in an out-of-order microprocessor pipeline, said method comprising: selecting a first set of instructions to dispatch from a scheduler to an execution module, wherein said scheduler is operable to dispatch two types of instructions, wherein said execution module comprises two types of execution units, wherein a first type of execution unit executes both a first type of instruction and a second type of instruction and wherein a second type of execution unit executes only said second type of instruction; selecting a second set of instructions to dispatch from said scheduler, wherein said second set is a subset of said first set, and wherein said second set comprises only instructions of said second type; determining a third set of instructions, wherein said third set of instructions is a subset of said first set of instructions, and wherein said third set comprises instructions not selected as part of said second set, wherein said third set comprises said first type of instructions and said second type of instructions; and dispatching said second set of instructions to said execution module and executing said second set of instructions in said execution module using said second type of execution unit and further dispatching said third set of instructions to said execution module and executing said third set of instructions in said execution module using said first type of execution unit.