Patent ID: 9542261
Date: 2017-01-10
CPC Classifications: G06F,H03M

Claim:
1. A system for performing a multi-packet cyclic redundancy check (CRC), the system comprising: an input module for receiving a plurality of bits associated with at least one data packet and identifying packet boundaries within the plurality of bits; a plurality of CRC pre-calculation blocks (CPBs), wherein each CPB receives from the input module a subset of the plurality or bits, each subset containing a portion of a packet less than all of a packet, and calculates a CRC value for its respective subset of bits; and an output module for receiving the calculated CRC values from the plurality of CPBs and using the calculated CRC values to produce packet-specific CRC values, wherein the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values and wherein the output module receives information about the locations of the packet boundaries from the input module and reconfigures internal data paths of the output module to direct data within a given set of packet boundaries to be combined with other data from within the same set of packet boundaries; wherein the output module comprises a number of instances of duplicated components, and wherein each instance of duplicated components comprises a same number of select blocks and a same number of XOR circuits; and wherein the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values by virtue of dynamically controlling the select blocks of the instances of duplicated components.