Patent ID: 9660618
Date: 2017-05-23
CPC Classifications: H03K

Claim:
1. A voltage level shifter comprising: a first input unit suitable for receiving a first input signal and forming a current path of a negative output node; a second input unit suitable for receiving a second input signal and forming a current path of a positive output node; a first PMOS transistor having a source receiving a first voltage and a drain coupled with the negative output node; a second PMOS transistor having a source receiving the first voltage and a drain coupled with the positive output node; a first clamping transistor having a gate receiving a second voltage, a drain coupled with the positive output node, and a source coupled with a gate of the first PMOS transistor; and a second clamping transistor having a gate receiving the second voltage, a drain coupled with the negative output node, and a source coupled with a gate of the second PMOS transistor, wherein the first PMOS transistor is directly connected to the first input unit, and the second PMOS transistor is directly connected to the second input unit.