Patent ID: 9728540
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a bit line contact disposed on a first active region and electrically connected to the first active region; a bit line disposed on the bit line contact and electrically connected to the bit line contact; a storage node contact disposed on a second active region adjacent to the first active region and electrically connected to the second active region; and an insulating layer disposed between the bit line contact and the storage node contact, wherein the insulating layer has a structure in which a first insulating layer with a first dielectric constant, a second insulating layer having a second dielectric constant, a third insulating layer having a third dielectric constant, and a protecting layer having a fourth dielectric constant are stacked, the second dielectric constant being different from the first dielectric constant the third dielectric constant, and the fourth dielectric constant, the protecting layer capping a lower portion of the second insulating layer.