Patent ID: 9551740
Date: 2017-01-24
CPC Classifications: G01R

Claim:
1. A parallel concurrent test system for testing semiconductor devices, comprising: a pick and place (PnP) handler that engages and transports the semiconductor devices along a testing plane, the PnP handler including at least one manipulator that moves along a track located parallel to the testing plane, the manipulator having a plurality of manipulator chucks for selectively picking up, holding, and dropping off designated semiconductor devices at specified locations on the testing plane; a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins; and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol, wherein the stepping pattern test protocol selectively permits parallel concurrent testing using the broadside test socket and only one to the plurality of DFT test sockets, and also selectively permits parallel concurrent testing using the broadside test socket and more than one of the plurality of DFT test sockets, and wherein each semiconductor device is subjected to broadside testing after being placed in the broadside test socket and to DFT testing after being placed in at least one of the plurality of DFT test sockets.