Patent ID: 9570154
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A dual-port SRAM timing control circuit, comprising: a first NMOS transistor, a second NMOS transistor and a third NMOS transistor are connected in series between ground and a node of a first bit line to which each SRAM cell structures correspond; a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor are connected in series between ground and a node of a second bit line to which structures of each SRAM cell correspond; a gate of the first NMOS transistor is connected to a first wordline, a gate of the fourth NMOS transistor is connected to a second wordline, a gate of the second NMOS transistor is connected to a first pulse signal, a gate of the fifth NMOS transistor is connected to a second pulse signal, and both a gate of the third NMOS transistor and a gate of the fifth NMOS transistor are connected to a timing control signal; a first clock signal and a first address signal are inputted from a first port, and a second clock signal and a second address signal are inputted from a second port; the first clock signal and the second clock signal are inputted into a first pulse generator, forming a first pulse signal and a second pulse signal, respectively; a falling edge of the first pulse signal is generated by a plurality of the SRAM cells discharging electricity toward the first bit line, and a falling edge of the second pulse signal is generated by a plurality of the SRAM cells discharging the second bit line, a rising edge of the first pulse signal being generated at the rising edge of the first clock signal, a rising edge of the second pulse signal being generated at the rising edge of the second clock signal; the first address signal and the second address signal, after being latched by an address latch, are inputted into an address comparator for comparison, which outputs the address comparison result to a timing control signal generator; the first pulse signal and the second pulse signal, after undergoing an AND operation, are inputted into the timing control signal generator, which outputs the timing control signal; when the first address signal is identical with the second address signal, the address comparison result is 1; when the first address signal is different from the second address signal, the address comparison result is 0; and when the AND result of the first pulse signal and the second pulse signal is 0, the timing control signal is 1; when the AND result of the first pulse signal and the second pulse signal is 1, the timing control signal is an inverting signal of the address comparison result.