Patent ID: 9559090
Date: 2017-01-31
CPC Classifications: B81B,B81C,G01P,H01L

Claim:
1. A silicon wafer comprising: a plurality of chip patterns arranged parallel to a first direction and a second direction intersecting the first direction, wherein the plurality of chip patterns include one or more patterns arranged in the first direction and the second direction intersecting the first direction in a straight line, and arranged linearly and intermittently, the plurality of chip patterns include a first chip pattern and a second chip pattern adjacent to the first chip pattern, and the second chip pattern is arranged by rotating the first chip pattern at 90 degrees, the plurality of chip patterns are arranged so that an axis in which a cleavage plane of the silicon wafer extends across a surface on the silicon wafer arranged with the first and second chip patterns is alternatingly parallel and perpendicular to the first direction of the first and second chip patterns, an angle between the axis and the first direction of the second chip pattern is 90 degrees, and one or more patterns of the first chip pattern are arranged in the second direction in a straight line to align with the axis of the cleavage plane.