Patent ID: 9570545
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate defined with a device region; a first device doped well within the substrate, wherein the first device doped well encompasses the device region; a gate disposed in the substrate, wherein the gate comprises a gate electrode and a first gate dielectric layer disposed in a first trench, wherein the first trench defines an upper trench portion; a second trench disposed within the gate, wherein the second trench extends below the upper trench portion and defines a lower trench portion; a second gate dielectric layer disposed in the second trench, wherein the second gate dielectric layer at least lines the lower trench portion; a field plate disposed in the second trench, wherein the field plate fills the trench and is disposed adjacent to the gate; first and second diffusion regions disposed within the device region, wherein the gate is displaced from the second diffusion region; and wherein the first device doped well surrounds the upper and lower trench portions and extends to a depth below the lower trench portion, the first device doped well includes same polarity type dopants as the first and second diffusion regions.