Patent ID: 9606155
Date: 2017-03-28
CPC Classifications: G01R

Claim:
1. A circuit comprising: a stacked circuit layer comprising a plurality of reference capacitors, each of the plurality of reference capacitors having a reference capacitance; a plurality of test contact points configured to be electrically coupled to a plurality of under-test capacitors of an under-test module, respectively, wherein the test contact points are independent and different from one another, wherein the under-test capacitors are independent and different from the reference capacitors, wherein the under-test module is one of a first wafer, a first metal-insulator-metal layer, and a first integrated circuit package that comprises a plurality of first metal-insulator-metal capacitors; and a comparator configured to compare the reference capacitance of a selected reference capacitor of the reference capacitors with an under-test capacitance of one of the under-test capacitors corresponding to a selected test contact point of the test contact points, to measure a range of the under-test capacitance.