Patent ID: 9595473
Date: 2017-03-14
CPC Classifications: E04B,F24S,H01L,Y02A,Y02B,Y02E

Claim:
1. A method for fabricating a self-aligned via structure, the method comprising: forming a tri-layer mask on an inter-level dielectric (ILD) layer, the ILD layer disposed over a lower metal wiring layer, and the tri-layer mask comprising a first insulating layer, a second insulating layer, and a metal layer disposed between the first and second insulating layers; defining a trench pattern through the first insulating layer and the metal layer of the tri-layer mask, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern in the tri-layer mask, the first via pattern having a second width, and the second width being larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width of the trench pattern to a third width, the third width defining a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.