Patent ID: 9614031
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a semiconductor substrate region having a first conductivity type; forming neighboring trenches in the semiconductor substrate region, wherein respective depths of the neighboring trenches are between approximately 30 μm and approximately 40 μm, and wherein respective widths of the neighboring trenches are between approximately 1 μm and approximately 2 μm; forming an epitaxial (EPI) liner, which has a second conductivity type, along sidewalls of the neighboring trenches and over bottom surfaces of the neighboring trenches; forming a dielectric layer over the EPI liner to fill the neighboring trenches, wherein the dielectric layer includes outer dielectric sidewalls which contact the EPI liner and which extend inwardly from an uppermost region of the dielectric layer at an uppermost surface of the semiconductor substrate region to a neck region beneath the uppermost surface of the semiconductor substrate region before tapering outwardly to a waist region and then extending inwardly again toward respective bottoms of the neighboring trenches; performing a thermal treatment to out-diffuse dopants from the EPI liner into a surrounding portion of the semiconductor substrate region, thereby forming an out-diffused region having the second conductivity type; forming a gate dielectric and a gate electrode over the semiconductor substrate region between the neighboring trenches; forming body regions at least partially under the gate electrode in the semiconductor substrate region; and forming source regions on opposite sides of the gate electrode and within the body regions.