Patent ID: 9548387
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures each of channel regions having a different thickness at different sites under the gate stack structures along the first direction; wherein the stress layers have connected parts in the fins and that the channel regions enclose the connected parts, wherein the connected parts are of a shape of one of Σ, C, and D; and wherein a top surface of each stress layer in the source and drain regions is above a top surface of a gate insulating layer of each gate stack structure, and wherein each of the stress layers extends in the first direction and has a different thickness at different sites under the gate stack structures along the first direction.