Patent ID: 9634024
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a plurality of word lines formed on a substrate; a plurality of air gaps of which each air gap is interposed between two adjacent word lines; a channel structure penetrating through the plurality of word lines and the plurality of air gaps; and a plurality of memory cells of which each memory cell is interposed between each word line and the channel structure, wherein each memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern, wherein the blocking pattern of each memory cell conformally covers a top surface, a bottom surface, and a first side surface of each word line, wherein the blocking pattern of each memory cell is vertically adjacent to another blocking pattern of a memory cell adjacent to and spaced apart from each memory cell, wherein the first side surface is adjacent to the channel structure, and wherein the charge trap pattern is interposed only between the first side surface and the channel structure.