Patent ID: 9690579
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A processing element comprising: a first storage unit configured to store a control bit having a first state and a second state; a first floating-point operation unit configured to receive a first floating-point variable and a second floating-point variable, and to perform a first floating-point operation on the first floating-point variable and the second floating-point variable so as to generate a first floating-point output having a first precision; a first rounding unit responsive to the control bit and configured to receive and round the first floating-point output if the control bit is in the first state so as to generate a second floating-point output having a second precision being less than the first precision; and a second floating-point operation unit configured to receive a third floating-point variable, and either the first floating-point output if the control bit is in the first state or the second floating-point output if the control bit is in the second state, the second floating-point operation unit further configured to perform a second floating-point operation on the third floating-point variable and either the first floating-point output or the second floating-point output so as to generate a third floating-point output having a third precision.