Patent ID: 9660130
Date: 2017-05-23
CPC Classifications: C23C,H01L,Y02E

Claim:
1. A method for manufacturing a passivation stack on a crystalline silicon solar cell device, the method comprising the steps of: providing a substrate comprising a crystalline silicon layer such as a crystalline silicon wafer or chip; cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer; depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride; and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride wherein the layer of silicon oxynitride is deposited at a temperature from 100° C. to 200° C., the step of depositing the layer of silicon oxynitride including: