Patent ID: 9607973
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A method for interconnecting a first semiconductor die and a second semiconductor die, the method comprising: attaching a splice interposer to a top surface of a substrate through a first plurality of pillars formed on a bottom surface of the splice interposer; attaching the first semiconductor die to the top surface of a substrate through a second plurality of pillars formed on a bottom surface of the first semiconductor die; attaching the first semiconductor die to a top surface of the splice interposer through a third plurality of pillars formed on the bottom surface of the first semiconductor, wherein the height of the second plurality of pillars is greater than the height of the third plurality of pillars; and attaching the second semiconductor die to the top surface of the splice interposer through a fourth plurality of pillars formed on a bottom surface of the second semiconductor die; wherein the first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.