Patent ID: 9542988
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a memory cell; a bit line connected to the memory cell; a sense circuit which senses data of the memory cell based on first current and second current that flows through the memory cell; a first transistor of a first conductivity type, which is connected to the bit line and through which the second current flows; and a second transistor of the first conductivity type, through which the first current flows, wherein the first transistor and the second transistor include: a semiconductor substrate; a gate structure provided on the semiconductor substrate; a first conductive region of the first conductivity type provided in the semiconductor substrate inwardly from an end portion of the gate structure; a second conductive region of a second conductivity type different from the first conductivity type, which is provided in the semiconductor substrate more inwardly from the end portion of the gate structure than the first conductive region; and a third conductive region of the first conductivity type provided in the semiconductor substrate and outside the end portion of the gate structure.