Patent ID: 9543426
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A device, comprising: a gate structure positioned above a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate; raised source/drain regions positioned laterally adjacent to opposing sides of said gate structure; a first sidewall spacer positioned between said gate structure and said raised source/drain regions, wherein said first sidewall spacer is positioned on and in contact with a lower sidewall surface of each of said two upstanding portions of said gate insulation layer; a liner layer comprising one of silicon nitride and silicon oxynitride, wherein said liner layer comprises a first liner layer portion positioned on and in contact with an upper sidewall surface of each of said two upstanding portions of said gate insulation layer and a second liner layer portion positioned laterally adjacent a sidewall surface of each of said raised source/drain regions, each of said first and second liner layer portions having a lower surface that is in direct contact with an upper surface of said first sidewall spacer, wherein said two respective upstanding portions are positioned between and separate said first liner layer portions and respective sidewall surfaces of said gate electrode; and a low-k sidewall spacer positioned on said liner layer, wherein a portion of said low-k sidewall spacer is positioned between and separates said first and second liner layer portions and is in direct contact with said upper surface of said first sidewall spacer.