Patent ID: 9666595
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a first layer; a plurality of memory areas provided on the first layer in a first direction; a plurality of contact wires, the contact wires having a longitudinal direction in a second direction perpendicular to the first layer, the contact wires being provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction; a first shunt wire commonly connecting the contact wires; a second shunt wire extending in the first direction, the second shunt wire being electrically connected to the first shunt wire; and interblock insulating layers positioned between side walls of the memory areas and side walls of the contact wires, wherein each interblock insulating layer has a groove extending in the third direction, and the first shunt wire is positioned inside the groove.