Patent ID: 9553093
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method of making a semiconductor comprising: patterning a first transistor comprising one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area the first source-drain area and the second source drain area each comprising a horizontal surface, the horizontal surface being on an upper surface of the source-drain area and wherein the upper surface is level with the bottom surface of the gate stack; forming dielectric spacers on gate stack side walls; depositing a first nitride liner on the first and second transistors; masking the second transistor; etching to selectively remove the first nitride material from the spacer from the first source-drain area; growing a first epitaxial layer on the first source-drain area by an epitaxial growth process such that the epitaxial layer extends the length of the first source-drain area and covers the horizontal surface of the first source drain area except areas covered by the gate stack and the dielectric spacers: depositing a second nitride liner on the first and second transistors; masking the first transistor; etching to remove the second nitride material from the second transistor source-drain area; and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process such that the epitaxial layer extends the length of the second source-drain area and covers the horizontal surface of the second source drain area except areas covered by the gate stack and the dielectric spacers.