Patent ID: 9673169
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method comprising: forming a first plurality of dies on a first wafer in a die area of the first wafer, the first plurality of dies being arranged laterally adjacent to each other; forming a first plurality of die bond rings in the die area of the first wafer, the first plurality of die bond rings encircling each of the first plurality of dies, the first plurality of die bond rings comprising a first polymer material, the first plurality of die bond rings having a first width and a first spacing; forming a first wafer seal ring on the first wafer in a seal ring area of the first wafer, the first wafer seal ring comprising a second polymer material, the first wafer seal ring having within an innermost boundary the first plurality of die bond rings and the first plurality of dies, the innermost boundary of the first wafer seal ring comprising a stair-shaped pattern, the innermost boundary of the first wafer seal ring being symmetrical under 90 degree rotation around a center of the first wafer, an entirety of an outermost boundary of the first wafer seal ring being co-terminus with an entirety of an edge of the first wafer, the first wafer seal ring having a plurality of lines having a second width and a second spacing, wherein a cross-section of the first width and the first spacing of the first plurality of die bond rings is approximately equal to the second width and the second spacing of the first wafer seal ring, wherein each of the plurality of lines physically contacts the innermost boundary of the first wafer seal ring and extends towards the outermost boundary of the first wafer seal ring as a single straight line segment that physically contacts the outermost boundary of the first wafer seal ring, and wherein the first wafer seal ring has a same pattern along the entirety of the edge of the first wafer; and forming a second plurality of dies in the seal ring area of the first wafer, wherein the second plurality of dies are interposed between the innermost boundary of the first wafer seal ring and the outermost boundary of the first wafer seal ring, and wherein the first wafer seal ring is disposed along a plurality of scribe lines in the seal ring area of the first wafer.