Patent ID: 9697899
Date: 2017-07-04
CPC Classifications: G11C,H03M

Claim:
1. An apparatus for computing, comprising: a set of Content Addressable Memory (“CAM”) cells, comprising at least a Distance CAM (“D-CAM”) cell to store a set of distance codes and a first and a second literal-Length CAM (“L-CAM”) cell to store a set of literal and length codes; a computer processor and a memory, wherein the memory comprises a parallel CAM management module; wherein the parallel CAM management module is to decompress a deflate bit stream in parallel using the set of CAM cells, wherein to decompress the deflate bit stream in parallel using the set of CAM cells, the parallel CAM management module is further to: decode a deflate header from the deflate bit stream; obtain a set of Huffman codes from the decoded deflate header, wherein the set of Huffman codes comprises literal and length codes and distance codes; and load the literal and length codes into the first and second L-CAM cells.