Patent ID: 9734110
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. A computer-implemented method, comprising: instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state, wherein the two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state; determining that the two or more processors have achieved their respective target frequencies for the slow state; entering the slow state, responsive to the determining; calculating a first greatest potential rate differential between a first processor of the two or more processors and a remainder of the two or more processors during the slow state, wherein the calculating comprises: responsive to the entering the slow state, instructing the first processor to send empty packets across an interconnect to compensate for the first greatest potential rate differential between the first processor and the remainder of the two or more processors during the slow state, wherein a percentage of empty packets sent as compared to total packets sent by the first processor is based on the first greatest potential rate differential.