Patent ID: 9727493
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. An apparatus, comprising: an extended address register including a plurality of configuration bits indicative of an offset and a size; an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits; a buffer configured to store data in a plurality of cache lines, each cache line of the plurality of cache lines having a respective usage field, the data including data to be stored in the storage area and further including data not to be stored in the storage area, the data to be stored in the storage area and data not to be stored in the storage area identified by information included in the respective usage field of the cache line of the plurality of cache lines in which the data is stored, each respective usage field of each respective cache line indicating whether the respective cache line is in use and includes write data not yet stored in the storage area; and a memory control circuit coupled to the buffer and configured to identify data to be stored in the storage area based on information included in the respective usage fields of the plurality of cache lines in which data is stored, and responsive, at least in part, to a flush command, cause the buffer to store the data identified as data to be stored in the storage area in the storage area of the array and to not store the data identified as data not to be stored in the storage area until after the data to be stored in the storage area is stored; wherein the memory control circuit is further configured to interrupt the flush command to prepare for a read command or a write command and resume the flush command once the read command or the write command is performed.