Patent ID: 9712347
Date: 2017-07-18
CPC Classifications: H04L,H04Q

Claim:
1. A clock recovery system, comprising: an ADC (analog-to-digital converter) circuit configured to sample an analog signal in response to sample a clock signal and generate a digital signal comprising sequence of digital data samples, wherein the analog signal comprises a stream of data symbols, wherein each data symbol comprises a plurality n of symbol components, including at least a first symbol component and a second symbol component, and wherein each digital data sample corresponds to one data symbol in the analog signal; a FFE (feed forward equalizer) circuit configured to remove precursor ISI (intersymbol interference) from the digital data samples and at least partially remove postcursor ISI from the digital data samples, and output FFE equalized data samples; a DFE (decision feedback equalizer) circuit configured to remove a first component of postcursor ISI from the FFE equalized data samples, and output DFE equalized data samples, wherein the first component of postcursor ISI of a given data sample arises from the first symbol component of a previous data sample; and a DFFE (decision feedforward equalizer) circuit configured to remove a second component of postcursor ISI from the DFE equalized data samples, and generate DFFE equalized data samples, wherein the second component of postcursor ISI of a given data sample arises from the second symbol component of a previous data sample; wherein the DFFE circuit is further configured to remove all but one of the n symbol components from each DFFE equalized data sample, and output an equalized 2-level digital signal comprising a sequence of equalized 2-level data samples; and wherein the DFE circuit comprises: