Patent ID: 9681546
Date: 2017-06-13
CPC Classifications: H01L,H05K

Claim:
1. A wiring substrate comprising: a first insulation layer composed of a thermosetting insulative resin; a first wiring layer formed on an upper surface of the first insulation layer; a second insulation layer stacked on the upper surface of the first insulation layer and covering the first wiring layer, wherein the second insulation layer includes a filler and is composed of a thermosetting insulative resin; a third insulation layer stacked directly on an upper surface of the second insulation layer, wherein the third insulation layer is filler-free and composed of a thermosetting insulative resin; a through electrode extending through the second and third insulation layers in a thicknesswise direction; and a fine wiring structure stacked directly on the third insulation layer, wherein the fine wiring structure includes: a second wiring layer stacked directly on an upper surface of the third insulation layer and an upper surface of the through electrode, wherein the through electrode electrically connects the second wiring layer to the first wiring layer: a fourth insulation layer formed from a photosensitive insulative resin, wherein the fourth insulation layer is stacked on the third insulation layer and covers the second wiring layer; and a third wiring layer is stacked on the fourth insulation layer and electrically connected to the second wiring layer, the second wiring layer and the third wiring layer form finer wires than wires of the first wiring layer such that the second wiring layer and the third wiring layer each satisfy a fine wire specification in which wire width/wire interval is less than 5 μm/5 μm and wherein each of a thickness of the second wiring layer and a thickness of the third wiring layer being thinner than a thickness of the first wiring layer, the upper surface of the third insulation layer and the upper surface of the through electrode are flush with each other, the third insulation layer includes a first through hole, the second insulation layer includes a second through hole that is communicated with the first through hole, the through electrode extends continuously through the first through hole and the second through hole from the upper surface of the third insulation layer to an upper surface of the first wiring layer, and the upper surface of the third insulation layer is a continuously flat surface that has a lower surface roughness than a wall surface of the first through hole.