Patent ID: 9741811
Date: 2017-08-22
CPC Classifications: B82Y,H01L

Claim:
1. An integrated circuit device comprising: a stack on a substrate, the stack comprising a plurality of channel regions and a plurality of gate electrodes stacked in an alternating sequence in a vertical direction that is perpendicular to a surface of the substrate and the plurality of channel regions comprising impurities having a first conductivity type; source/drain regions on respective opposing sides of the stack, the source/drain regions being spaced apart from each other in a horizontal direction that is parallel to the surface of the substrate and comprising impurities having a second conductivity type that is different from the first conductivity type; and a plurality of extension regions between respective ones of the plurality of channel regions and one of the source/drain regions and comprising impurities having the second conductivity type, each of the plurality of extension regions having a thickness in the vertical direction that is less than those of the plurality of channel regions and the one of the source/drain regions, wherein each of the plurality of channel regions overlaps with the plurality of gate electrodes in plan view, and the thickness of the plurality of channel regions in the vertical direction is uniform.