Patent ID: 9633987
Date: 2017-04-25
CPC Classifications: G03F,G06F,H01L

Claim:
1. A semiconductor chip, comprising: a gate electrode level including a plurality of linear-shaped conductive structures defined to extend lengthwise in a first direction, the plurality of linear-shaped conductive structures positioned in accordance with a fixed pitch such that a distance as measured in a second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the fixed pitch, wherein the plurality of linear-shaped conductive structures includes a first set of linear-shaped conductive structures corresponding to a first sub-layout and a second set of linear-shaped conductive structures corresponding to a second sub-layout, the second set of linear-shaped conductive structures interleaved with the first set of linear-shaped conductive structures such that each linear-shaped conductive structure of the second set of linear-shaped conductive structures is separated from at least one adjacently located linear-shaped conductive structure of the first set of linear-shaped conductive structures by the fixed pitch as measured in the second direction between their first-direction-oriented-lengthwise-centerlines, wherein the first set of linear-shaped conductive structures is manufactured using a first mask, and wherein the second set of linear-shaped conductive structures is manufactured using a second mask different from the first mask, and wherein the first set of linear-shaped conductive structures is manufactured separately from the second set of linear-shaped conductive structures.