Patent ID: 9583705
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: forming semiconductor patterns on a semiconductor substrate such that sides of the semiconductor patterns are surrounded by a lower interlayer insulating layer; forming a lower insulating layer that covers the semiconductor patterns and the lower interlayer insulating layer; forming a contact structure that penetrates the lower insulating layer and the lower interlayer insulating layer and is spaced apart from the semiconductor patterns, an upper surface of the contact structure being higher than the semiconductor patterns; forming an upper insulating layer that covers the contact structure and the lower insulating layer; patterning the upper and lower insulating layers to form insulating patterns that expose the semiconductor patterns and cover the contact structure, each of the insulating patterns including a lower insulating pattern and an upper insulating pattern sequentially stacked; and forming metal-semiconductor compounds on the exposed semiconductor patterns after forming the insulating patterns.