Patent ID: 9646974
Date: 2017-05-09
CPC Classifications: G11C,H01L

Claim:
1. A dual-port static random access memory (SRAM) cell confined in a region defined by first through fourth boundaries, the first and second boundaries parallel to each other, and the third and fourth boundaries connected the first and the second boundaries and parallel to each other, the dual-port SRAM comprising: first through third power lines; a storage unit connected to the first through third power lines; a first port comprising first and second pass-gate transistors controlled by a first wordline, the first pass-gate transistor coupling a first bitline and the storage unit to each other and the second pass-gate transistor coupling a second bitline and the storage unit to each other; and a second port comprising third and fourth pass-gate transistors controlled by a second wordline, the third pass-gate transistor coupling a third bitline and the storage unit to each other and the fourth pass-gate transistor coupling a fourth bitline and the storage unit to each other, wherein the first through fourth bitlines and the first through third power lines each extend in a first direction and are formed of a first metal layer, the first wordline extends in a second direction substantially perpendicular to the first direction and is formed of a second metal layer above the first metal layer, and the second wordline extends in the second direction and is formed of a upper-level metal layer above the second metal layer.