Patent ID: 9748110
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method for increasing pattern density of a structure on a substrate using an integration scheme, the integration scheme configured to meet integration targets, the method comprising: providing a substrate in a process chamber, the substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer, wherein the first underlying layer is one of a layer of silicon anti-reflective coating (SiARC), titanium anti-reflective coating (TiARC), optical dispersive layer (ODL), or spin on hardmask (SOH), and wherein the second underlying layer is one of an organic planarizing layer (OPL), advanced planarizing layer (APL), ODL, or SOH; selecting two or more operating variables to control one or more processes of the integration scheme; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, the pull process on the conformal layer, thereby generating a second spacer pattern, wherein the spacer RIE process includes adsorption and reaction of etch gases to form fluorosilicates, wherein the etch gases comprise a combination of F-based and N-based gases; transferring the second spacer pattern into the target layer, the transferring generating a target pattern; and concurrently controlling the two or more selected operating variables of one or more processes of the group including performing the conformal spacer deposition process using titanium oxide or silicon oxide, the deposition creating the conformal layer; performing the spacer RIE process and the pull process; and/or transferring the second spacer pattern into the target layer; wherein the integration targets include selectively etching various spacer films within a target spacer etch rate, enhanced simultaneous selectivity for the oxide relative to the first underlying layer and the second underlying layer while performing spacer etch, and/or preventing pattern damage to the second spacer pattern.