Patent ID: 9653146
Date: 2017-05-16
CPC Classifications: G06F,G11C

Claim:
1. A memory module comprising: a plurality of device sites; a data buffer component coupled to the plurality of device sites; at least eighteen dynamic random access memory (DRAM) devices disposed at respective device sites; nine data buffer components coupled to the at least eighteen DRAM devices, each of the nine data buffer components being coupled to a respective pair of the at least eighteen DRAM devices, wherein the nine data buffer components includes the data buffer component; and a command and address (CA) buffer component coupled to the at least eighteen DRAM devices, wherein the data buffer component is to couple to point-to-point data-links of a memory channel, wherein the data buffer component comprises: three primary ports to couple to three multi-drop data-links in a first mode and to couple to three point-to-point data-links in a second mode; and three secondary ports coupled to three of the at least eighteen DRAM devices.