Patent ID: 9614445
Date: 2017-04-04
CPC Classifications: H02M,H05B

Claim:
1. An error amplifier for processing a reference signal and an input signal associated with a current of a power conversion system, the error amplifier comprising: a first operational amplifier including a first input terminal, a second input terminal and a first output terminal, the first input terminal being configured to receive a reference signal; a first transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, the first transistor terminal being configured to receive a first amplified signal from the first output terminal, the third transistor terminal being coupled to the second input terminal; a second operational amplifier including a third input terminal, a fourth input terminal and a second output terminal, the third input terminal being configured to receive an input signal associated with a first current flowing through a primary winding of a power conversion system; a second transistor including a fourth transistor terminal, a fifth transistor terminal and a sixth transistor terminal, the fourth transistor terminal being configured to receive a second amplified signal from the second output terminal, the sixth transistor terminal being coupled to the fourth input terminal; a current mirror component including a first component terminal and a second component terminal, the first component terminal being coupled to the second transistor terminal; a switch including a first switch terminal and a second switch terminal, the first switch terminal being coupled to the second component terminal, the second switch terminal being coupled to the fifth transistor terminal; a first resistor including a first resistor terminal and a second resistor terminal, the first resistor being associated with a first resistance, the first resistor terminal being coupled to the second input terminal; and a second resistor including a third resistor terminal and a fourth resistor terminal, the second resistor being associated with a second resistance, the third resistor terminal being coupled to the fourth input terminal; wherein: