Patent ID: 9720604
Date: 2017-08-01
CPC Classifications: G06F,G11C

Claim:
1. A memory device comprising: a random access memory; a non-volatile solid state memory; a memory controller configured to access the non-volatile solid state memory; a first double data rate bus coupled to the random access memory, wherein the random access memory is accessible by a host system via the first double data rate bus; a second double data rate bus coupled to the random access memory, wherein the random access memory is accessible by the memory controller via the second double data rate bus; and a block storage protocol interface in communication with the memory controller, wherein the block storage protocol interface and the first double data rate bus are on parallel communication paths from the host system, wherein the memory controller is configured to receive a command from the host system via the block storage protocol interface and to transfer data from the random access memory to the non-volatile solid state memory over the second double data rate bus in response to the command.