Patent ID: 9661052
Date: 2017-05-23
CPC Classifications: H04L

Claim:
1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a streams manager residing in the memory and executed by the at least one processor, the streams manager executing a streaming application that comprises a flow graph that includes a plurality of processing elements that process a plurality of data tuples, wherein a first of the plurality of processing elements receives data tuples from a plurality of the processing elements that comprise a plurality of latency paths in the streaming application; and a latency reconfiguration mechanism that monitors latency in the plurality of latency paths in the streaming application, and when there is a mismatch between a first of the plurality of latency paths that provides data tuples to the first processing element and a second of the plurality of latency paths that provides data tuples to the first processing element, the latency reconfiguration mechanism reconfigures at least one of the plurality of processing elements to reduce the mismatch between the first and second latency paths.