Patent ID: 9570195
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A memory characterization circuit comprising: a first programmable delay line having an input receiving a system clock signal and an output; a second programmable delay line having an input connected to said output of said first programmable delay line and an output; an address register having a plurality of address memory elements for storing an address, each address memory element having an input receiving a corresponding address input bit, an output supplying a stored address bit and a clock input connected to said output of said second programmable delay line, each address memory element storing an address bit corresponding to said address input bit upon a predetermined edge of said output of said second programmable delay line at said clock input, said output of each address memory element connected to a corresponding address bit input of a memory to be tested; a data register having a plurality of data memory elements for storing data, each data memory element having an input receiving a corresponding data input bit, an output supplying a stored data bit and a clock input connected to said output of said second programmable delay line, each data memory element storing a data bit corresponding to said data input bit upon a predetermined edge of said output of said second programmable delay line at said clock input, said output of each data memory element connected to a corresponding data bit input of a memory to be tested; an output register having a plurality of output memory elements for storing data, each output memory element having an input receiving a corresponding data output bit of the memory to be tested, an output supplying a stored data bit and a clock input receiving said system clock signal, each output memory element storing a data bit corresponding to said data output bit of the memory to be tested upon a predetermined edge of the system clock signal at said clock input, said output of each output memory element connected to a corresponding data bit input of a memory to be tested; a finite state machine controller supplying an address to said address register, data to said data register and controlling a delay of said first programmable delay line and said second programmable delay line in at least one predetermined sequence to determine an operating characteristic of the memory to be tested.