Patent ID: 9543395
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A method of manufacturing a junction field effect transistor, comprising the steps of: (a) providing on a first main surface of a silicon-carbide-based semiconductor substrate having a first conductivity type, a first silicon-carbide-based semiconductor epitaxial layer having the first conductivity type and a lower impurity concentration than the semiconductor substrate; (b) forming a first structure having a plurality of first gate impurity regions by doping a surface of the first silicon-carbide-based semiconductor epitaxial layer with an impurity having a second conductivity type by ion implantation to introduce, into the surface of the first epitaxial layer, the plurality of first gate impurity regions; (c) after the step (b), performing first activation annealing on the first structure; (d) after the step (c), forming, on the surface of the first epitaxial layer , a second silicon-carbide-based semiconductor epitaxial layer having the first conductivity type and a lower impurity concentration than the semiconductor substrate; (e) forming a second structure having a plurality of second gate impurity regions by doping a surface of the second silicon-carbide-based semiconductor epitaxial layer with an impurity having the second conductivity type by ion implantation to introduce, into the surface of the second epitaxial layer, the plurality of second gate impurity regions respectively coupled to the plurality of first gate impurity regions; (f) after the step (e), performing second activation annealing on the second structure; (g) after the step (f), forming, over the second epitaxial layer, a third silicon-carbide-based semiconductor epitaxial layer having the first conductivity type and a lower impurity concentration than the semiconductor substrate; (h) forming a third structure having a plurality of third gate impurity regions by doping a surface of the third silicon-carbide-based semiconductor epitaxial layer with an impurity having the second conductivity type by ion implantation to introduce, into the surface of the third epitaxial layer, the plurality of third gate impurity regions respectively coupled to the plurality of second gate impurity regions; (i) after the step (h), performing third activation annealing on the third structure; and (j) after the step (i), forming a source region of the first conductivity type between adjacent third gate impurity regions in the third epitaxial layer, wherein a spacing between the third gate impurity regions is larger than a spacing between the second gate impurity regions.