Patent ID: 9721624
Date: 2017-08-01
CPC Classifications: G11C

Claim:
1. A memory comprising: a regular array of storage elements; and a regular array of write multiplexers, each write multiplexer to select from among a plurality of bit lines an active bit line to write write data to a selected storage element within said regular array of storage elements, wherein said write multiplexer connects said active bit line to a precharged node via a discharge transistor and, in dependence upon an asserted write word line coupled to a gate of the discharge transistor, said write multiplexer applies a corresponding bit line value to the precharged node, wherein said write multiplexer has an inverter and at least one keeper transistor connected between said precharged node and said selected storage element, such that said precharged node is coupled to said selected storage element via said inverter, wherein an output of said inverter is connected to a gate of said at least one keeper transistor, and an output of said at least one keeper transistor is connected to an input of said inverter at said precharged node, and wherein said at least one keeper transistor is activated based on the output of said inverter so as to maintain the corresponding bit line value to which said discharge node is driven.