Patent ID: 9680015
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A complementary metal oxide semiconductor (CMOS) device, comprising: a substrate; gate structures formed in both a first polarity type region and a second polarity type region of the substrate, the gate structures having sidewall spacers adjacent thereto; first epitaxially grown source/drain (SD) regions formed in the first polarity type region; a protection layer selectively formed only on surfaces of the first epitaxially grown SD regions, the protection layer being excluded from upper surfaces of the gate structures located in the first epitaxially grown SD regions; second epitaxially grown SD regions formed in the second polarity type region; and first and second electrically conductive SD contacts, an end of the first electrically conductive SD contacts formed on an upper surface of the first epitaxially grown SD regions and an end of the second electrically conductive SD contacts formed on an upper surface of the second epitaxially grown SD regions, wherein a portion of the first electrically conductive SD contacts are surrounded by the protection layer.