Patent ID: 9633931
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A package, comprising: a plurality of lead frames configured to extend inwardly from an outer circumferential portion of the package, and including a first lead frame and a second lead frame adjacent to the first lead frame; a die pad region surrounded with the plurality of lead frames in a plane view; a semiconductor chip mounted on the die pad region, and having a vertex at which a first side and a second side of the semiconductor chip meet; a plurality of bonding pads disposed on the semiconductor chip and at the sides of the semiconductor chip, and including a first bonding pad formed on the first side of the semiconductor chip closest to the vertex and a second bonding pad formed on the second side of the semiconductor chip closest to the vertex; and a plurality of bonding wires configured to connect the plurality of lead frames and the plurality of bonding pads, respectively, wherein the semiconductor chip is disposed at a location below where the plurality of lead frames are disposed, and is mounted on the die pad region at a bottom of the package, wherein the plurality of bonding wires connects front end portions of the plurality of lead frames, which are disposed higher than the plurality of bonding pads within the package, and the plurality of bonding pads, respectively, wherein the semiconductor chip has a square shape in the plane view, wherein the semiconductor chip is disposed at a 45 degree angle with respect to the outer circumferential portion of the package in the plane view, and wherein the first lead frame is connected to the first bonding pad and the second lead frame is connected to the second bonding pad.