Patent ID: 9728243
Date: 2017-08-08
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a circuit; and a first memory cell, wherein the circuit includes a first transistor, a second transistor, first to sixth capacitors, first to fourth wirings, a first sense amplifier, and a second sense amplifier, wherein the first sense amplifier includes a first input/output terminal and a second input/output terminal, wherein the second sense amplifier includes a third input/output terminal and a fourth input/output terminal, wherein the first memory cell is over the first sense amplifier and the second sense amplifier, wherein the first wiring is electrically connected to a first electrode of the first capacitor, one of a source and a drain of the first transistor, a first electrode of the fifth capacitor, and the first input/output terminal, wherein the second wiring is electrically connected to a first electrode of the second capacitor, one of a source and a drain of the second transistor, a first electrode of the sixth capacitor, and the second input/output terminal, wherein the third wiring is electrically connected to a first electrode of the third capacitor, the other of the source and the drain of the first transistor, a second electrode of the sixth capacitor, and the third input/output terminal, wherein the fourth wiring is electrically connected to a first electrode of the fourth capacitor, the other of the source and the drain of the second transistor, a second electrode of the fifth capacitor, and the fourth input/output terminal, and wherein the first memory cell is electrically connected to the first wiring.