Patent ID: 9642133
Date: 2017-05-02
CPC Classifications: H04J,H04W

Claim:
1. A master communication apparatus comprising: processing circuitry which, in operation, generates multiple slots for communicating synchronization messages, and allocates the multiple slots to slave communication apparatuses, respectively, including at least first and second slave communication apparatuses; and communication circuitry which, in operation, establishes wired connections with the slave communication apparatuses, respectively; communicates to the slave communication apparatuses slot allocation information indicative of which of the multiple slots is allocated to which of the slave communication apparatuses; exchanges the synchronization messages with the first slave communication apparatus, over the wired connection, using the slot allocated to the first slave communication apparatus wherein the synchronization messages are usable for the first slave communication apparatus to correct a first internal clock; and exchanges the synchronization messages with the second slave communication apparatus, over the wired connection using the slot allocated to the second slave communication apparatus wherein the synchronization messages are usable for the second slave communication apparatus to correct a second internal clock.