Patent ID: 9711494
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor die assembly, comprising: stacking at least one level of mutually laterally spaced semiconductor dice previously thinned from an initial wafer thickness and comprising integrated circuitry and having conductive through vias over unsingulated, mutually laterally separated semiconductor die locations of a semiconductor wafer previously thinned from the initial wafer thickness, each semiconductor die location comprising integrated circuitry, having conductive through vias and having conductive elements on a surface thereof opposite the at least one level of mutually laterally spaced semiconductor dice; stacking another level of mutually laterally spaced semiconductor dice of the initial wafer thickness and comprising integrated circuitry, without conductive through vias, and of a same length and width as a length and width of the semiconductor dice of the at least one level over uppermost semiconductor dice of the at least one level with active surfaces facing toward the semiconductor wafer; vertically operably connecting integrated circuitry of semiconductor dice in each level of a stack and integrated circuitry of an associated semiconductor die location with conductive elements between the semiconductor dice of the stack and the conductive through vias within the semiconductor dice of the at least one level and through conductive elements between a lowermost semiconductor die of the stack and the conductive through vias of the associated semiconductor die location to the conductive elements on the opposite surface of the associate semiconductor die location; placing a dielectric material between the semiconductor dice of each stack and between a semiconductor die of each stack and the associated unsingulated die location to surround the conductive elements and substantially fill space between the semiconductor dice of each stack and between a semiconductor die of each stack and the associated unsingulated die location; substantially simultaneously placing encapsulant material over and around each stack of semiconductor dice, contacting and covering a lateral periphery of each stack of semiconductor dice and the dielectric material with the encapsulant material extending between the stacks and onto the wafer; and removing the encapsulant material from over the another level of semiconductor dice; reducing the initial wafer thickness of the semiconductor dice of the another level from the initial wafer thickness to a thickness substantially the same to thicknesses of the previously thinned mutually laterally spaced semiconductor dice and the previously thinned semiconductor wafer; and singulating the stacks of semiconductor dice through the encapsulant material extending between the stacks of semiconductor dice and through the semiconductor wafer between the mutually laterally separated semiconductor die locations.