Patent ID: 9748111
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor structure, comprising the steps of: providing a substrate; forming a first layer on the substrate; conformally forming a second layer over the first layer, wherein the second layer and the first layer have different compositions; forming a third layer over the second layer, wherein the third layer and the second layer have different compositions; performing a planarizing process on the third layer until portions of the second layer are exposed so as to produce a remaining third layer and an exposed second layer; performing a first cleaning process comprising a step of providing hydrofluoric acid to the remaining third layer and the exposed second layer and a step of providing an aqueous oxidant to the remaining third layer and the exposed second layer, wherein an amount of the remaining third layer removed in the first cleaning process is greater than the exposed second layer removed in the first cleaning process, wherein a top surface of the third layer is lower than a top surface of the second layer when the first cleaning process is completed; performing a second cleaning process to removing the exposed second layer by phosphoric acid until portions of the first layer are exposed after the first cleaning process; and etching back the second layer and the first layer.