Patent ID: 9578268
Date: 2017-02-21
CPC Classifications: H03M,H04N

Claim:
1. A ramp signal calibration apparatus comprising: an analog-to-digital converter (ADC) comprising a trimmable transistor having a gain value that varies according to stored data, the ADC configured to receive a ramp signal in a state where the gain value is set to a first gain value, and to output a first output signal and a second output signal based on the received ramp signal; a subtractor configured to calculate a difference between the first output signal and the second output signal; a digital comparator configured to compare the calculated difference with a reference value and to determine whether a slope of the ramp signal has changed based on a result of the comparing; and a counter configured to change the stored data based on the determining of whether the slope of the ramp signal has changed; wherein when the counter changes the stored data, the first gain value of the trimmable transistor is changed to a second gain value according to the changed data, wherein the trimmable transistor comprises a reference transistor, N metal oxide semiconductor (MOS) transistors, and N switches connected in parallel, and each of the N switches is disposed on a side of each of the N MOS transistors, respectively, and the N switches are turned on or off according to the data, and wherein the ramp signal comprises a coarse ramp signal and a fine ramp signal, the first output signal comprises an output of the fine ramp signal, which corresponds to a first level of the coarse ramp signal, and the second output signal comprises an output of the fine ramp signal, which corresponds to a second level of the coarse ramp signal, and a difference between the second level and the first level corresponds to a least significant bit (LSB) of the coarse ramp signal.