Patent ID: 9747397
Date: 2017-08-29
CPC Classifications: G06F,G06T

Claim:
1. A method comprising: determining, by a computing device, one or more clusters of sink pins of circuit elements in a circuit design; placing, by the computing device, clock tree nodes of a clock tree for the circuit design within the one or more clusters; determining, by the computing device, multiple sets of clock tree timing variation parameters for the placed clock tree nodes within the one or more clusters; measuring, by the computing device, multiple delays from a root node of the clock tree to the sink pins within the one or more clusters, wherein the multiple delays are measured for the multiple sets of clock tree timing variation parameters, respectively; determining, by the computing device, skews for the one or more clusters using the delays measured for the multiple sets of clock tree timing variation parameters; and reducing, by the computing device, clock tree skew across the multiple sets of clock tree timing variation parameters using the multiple measured delays and skews.