Patent ID: 9748985
Date: 2017-08-29
CPC Classifications: H01L,H03F,H04B

Claim:
1. An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns, the integrated circuit architecture comprising: a first operating frequency region implemented in the die structure including a first transmit chain and a first receive chain; a second operating frequency region implemented in the die structure including a second transmit chain and a second receive chain; a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the shared region including either one or both of a shared power input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain; and a shared voltage regulator disposed in the shared region of the die structure and connected to the shared power input pad, the shared voltage regulator including a first operating frequency regulated power output connected to the first transmit chain and the first receive chain, and a second operating frequency regulated power output connected to the second transmit chain and the second receive chain.