Patent ID: 9721964
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a plurality of stacks of conductive strips alternating with insulating strips, at least one of the insulating strips comprising an insulating material with a dielectric constant equal to or lower than 3.6, the plurality of stacks of conductive strips including a plurality of intermediate planes of conductive strips arranged as word lines connected to a row decoder, the plurality of intermediate planes of conductive strips being disposed between a top plane of conducting strips in the stacks and a bottom plane of conducting strips in the stacks; a plurality of structures of a conductive material arranged orthogonally over the plurality of stacks; and memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of structures, wherein the insulating strips have non-simple spatial periods through the intermediate planes of conductive strips.