Patent ID: 9547733
Date: 2017-01-17
CPC Classifications: G06F

Claim:
1. A computer implemented method, performed by a processor, for logic equivalence checking, said processor is coupled to memory which stores instructions that, when executed by said processor, cause said processor to perform said method comprising: accessing a first register-transfer level (RTL) design of an integrated circuit comprising a plurality of interconnects, wherein a respective interconnect in said first RTL design comprises a first plurality of flip-flops; accessing a first physical implementation of said integrated circuit, wherein said first physical implementation comprises said plurality of interconnects, wherein said respective interconnect in said first physical implementation comprises a second plurality of flip-flops, inverters, and buffers; replacing said first plurality of flip-flops with buffers to generate a second RTL design; replacing said second plurality of flip-flops with buffers to generate a second physical implementation; checking logic equivalence between said second RTL design and said second physical implementation; and identifying a logic error in said first physical implementation based on said checking.