Patent ID: 9553595
Date: 2017-01-24
CPC Classifications: G06F,H03K,H03L

Claim:
1. A clock generating method of generating delayed clocks to be supplied to each of one or more functional modules and a control circuit that controls operations of the one or more functional modules in a semiconductor chip on which the one or more functional modules and the control circuit are mounted, the method comprising: generating a variable divided clock by dividing a source clock in accordance with a division ratio setting signal; calculating one or more numbers of clocks by each of which the variable divided clock is delayed in synchronization with the source clock for each of the variable divided clocks connected to the one or more functional modules depending on a wiring distance of each of the variable divided clocks connected to the one or more functional modules from a variable frequency division circuit that generates the variable divided clock when a clock synchronization circuit delaying the variable divided clock is not provided, in order to operate the control circuit and each of the one or more functional modules in synchronization with the variable divided clock; calculating a maximum number of clocks that is a number of clocks greater than or equal to a largest number of clocks out of the calculated numbers of clocks; generating a first delayed clock, wherein the first delayed clock is delayed by the maximum number of clocks from the variable divided clock, in synchronization with the source clock and supplying the first delayed clock to the control circuit operating in synchronization with the first delayed clock; and generating one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock, in synchronization with the source clock and supplying each of the one or more second delayed clocks to each of the one or more functional modules operating in synchronization with each of the one or more second delayed clocks.