Patent ID: 9666241
Date: 2017-05-30
CPC Classifications: G06F,G11C,H04L

Claim:
1. A system for firmware protection and validation comprising: a memory device, including BIOS firmware; a chipset wherein the chipset controls communication between the memory device and the microprocessor including allowing the microprocessor to load and execute the BIOS firmware; the microprocessor in electrical communication with the chipset; a secure logic device in electrical communication with the chipset and the memory device wherein, prior to validation of the BIOS firmware, the secure logic device prevents the microprocessor from operating including executing instructions; and a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset and the microprocessor, wherein the secure logic device applies a hold signal to the microprocessor through the chipset, while the hold signal is applied to the chipset by the secure logic device, the power on reset circuit de-asserts the reset signal, when the reset signal is de-asserted, only the secure logic device validates the content of the firmware in the memory device, and further wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the hold signal applied to the chipset, further wherein the hold signal is continuously asserted from the receipt of the reset signal until the content of the firmware in the memory device is validated.