Patent ID: 9698257
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A symmetric LDMOS transistor, comprising: a semiconductor substrate; a well of a first type of conductivity in the substrate; wells of an opposite second type of conductivity in the well of the first type of conductivity, the wells of the second type of conductivity being arranged at a distance from one another; source/drain regions in the wells of the second type of conductivity; a gate dielectric on the substrate; a gate electrode on the gate dielectric; a doped region of the second type of conductivity in the well of the first type of conductivity, the doped region of the second type of conductivity comprising areas separated from one another and being arranged between the wells of the second type of conductivity at a distance from the wells of the second type of conductivity; a gap of the gate electrode above the doped region of the second type of conductivity, the gate electrode overlapping regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity; and a body contact region connected with the well of the first type of conductivity and arranged between the areas of the doped region of the second type of conductivity, wherein the gap of the gate electrode is arranged above the body contact region, wherein the areas of the doped region of the second type of conductivity and the wells of the second type of conductivity are arranged symmetrically with respect to the body contact region, wherein the body contact region is a strip region arranged at the same distance from the wells of the second type of conductivity and divides the doped region of the second type of conductivity, and wherein a connection between the areas of the doped region of the second type of conductivity is provided by an external connection via a metallization belonging to a wiring.