Patent ID: 9563565
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. An apparatus, comprising: a memory array including an area designated as a storage area for persistent data storage; a buffer coupled to the memory array and configured to store data to the memory array, the buffer including a plurality of cache lines, each cache line of the plurality of cache lines configured to store data, wherein each of the cache lines of the plurality of cache lines includes a usage field configured to store information indicating whether the cache line includes data to be stored in the storage area of the memory array; and a memory control unit coupled to the array and the buffer, the memory control unit configured to cause the buffer to store the data responsive, at least in part, to a write command, the memory control unit further configured to identify data stored in the buffer as data to be stored in the storage area based on the information stored in the usage field and further configured to cause the identified data to be stored in the storage area of the array responsive, at least in part, to a flush command, the memory control unit further configured to interrupt the flush command to prepare for a read command or the write command and resume the flush command once the read command or the write command is performed.