Patent ID: 9672912
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A semiconductor integrated circuit including a content addressable memory device, comprising: a memory cell array including: an equalizer circuit disposed between the first match line and the second match line; a first precharge circuit coupled to the first match line; and a second precharge circuit coupled to the second match line, wherein the first precharge circuit precharges the first match line to a first potential and the second precharge circuit precharges the second match line to a second potential different from the first potential, the equalizer circuit couples, in accordance with a control signal, the first match line and the second match line after the first match line and the second match line are precharged, the first search line and the second search line are active when the first match line and the second match line are coupled by the equalizer circuit, and where the entry data does not match the search data, both the first match line and the second match line are discharged to the second potential.