Patent ID: 9564244
Date: 2017-02-07
CPC Classifications: G09G,G11C

Claim:
1. A shift register unit, comprising: a buffering module, a resetting module, a signal generation module, a first pulling-down module and a second pulling-down module, wherein the buffering module is connected with a signal input terminal; the resetting module is connected with a reset terminal, a power supply terminal and an output terminal of the buffering module, and is used for resetting the output terminal of the buffering module to a level of the power supply terminal under the control of a reset signal from the reset terminal; the first pulling-down module is connected with the reset terminal, the power supply terminal and a signal output terminal, and is used for pulling down the signal output terminal to the level of the power supply terminal under the control of the reset signal from the reset terminal; the signal generation module is connected with a clock terminal, the signal output terminal and the output terminal of the buffering module, and is used for outputting a clock signal from the clock terminal to the signal output terminal under the control of a signal output from the output terminal of the buffering module; the second pulling-down module is connected with a pulling-down node, the output terminal of the buffering module, the power supply terminal and the signal output terminal, and is used for pulling down the signal output terminal and the output terminal of the buffering module to the level of the power supply terminal under the control of a signal from the pulling-down node; characterized in that the shift register unit further comprises a holding module connected with the output terminal of the buffering module, the pulling-down node and the power supply terminal, and used for pulling down the pulling-down node to the level of the power supply terminal when the output terminal of the buffering module is at a high level, characterized in that the buffering module comprises a first thin film transistor, a gate and a drain of the first thin film transistor are connected with the signal input terminal; the resetting module comprises a second thin film transistor, a gate of the second thin film transistor is connected with the reset terminal, a source of the second thin film transistor is connected with the power supply terminal, and a drain of the second thin film transistor is connected with a source of the first thin film transistor; the signal generation module comprises a third thin film transistor and a capacitor connected with the third thin film transistor, one terminal of the capacitor is connected with a gate of the third thin film transistor, the other terminal of the capacitor is connected with a source of the third thin film transistor and the signal output terminal; the first pulling-down module comprises a fourth thin film transistor, a gate of the fourth thin film transistor is connected with the reset terminal, a source of the fourth thin film transistor is connected with the power supply terminal, and a drain of the fourth thin film transistor is connected with the source of the third thin film transistor; and the second pulling-down module comprises a tenth thin film transistor and an eleventh thin film transistor, gates of the tenth and eleventh thin film transistors are connected with the pulling-down node, sources of the tenth and eleventh thin film transistors are connected with the power supply terminal, a drain of the tenth thin film transistor is connected with the drain of the fourth thin film transistor, and a drain of the eleventh thin film transistor is connected with the drain of the second thin film transistor.