Patent ID: 9652404
Date: 2017-05-16
CPC Classifications: G06F,H04L,Y02D

Claim:
1. A method of coherent data processing system comprising the steps of: temporarily storing data in a cache memory of at least one processing core of a plurality of processing cores; storing data in a plurality of memory endpoints; storing each of a plurality of coherence maintenance addresses in a corresponding entry, each entry storing an address of an access request committed to a shared memory at a corresponding memory endpoint and an assigned ID tag; assigning an available ID tag from a set of ID tags to the entry of an access request committed to the shared memory for storage; retiring a coherence maintenance address entry upon receipt of a completion signal from the shared memory indicating completion of the corresponding access request; and comparing the address of a memory access request with all stored coherence maintenance addresses; and generating a hazard stall signal if the address of a memory access request matches any stored coherence maintenance address.