Patent ID: 9557348
Date: 2017-01-31
CPC Classifications: B32B,C23F,G01B,G01Q,H01L

Claim:
1. A method for fabricating a semiconductor testing structure, comprising: providing a substrate having a device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the device structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer; planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer by a first planarization process until the first surface of the dielectric layer is exposed; bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer; and removing the substrate to expose a second surface relative to the first surface of the dielectric layer and a surface of the device structure.