Patent ID: 9632951
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A cache memory comprising: a tag memory array including at least one tag memory; a data memory array including at least one data memory, with the at least one data memory and the at least one tag memory together forming at least one cache way; a control register for separately storing a mode byte, a tag base address, and a data base address, with the mode byte recording a reconfiguration status of the at least one cache way, with the tag base address being a start address of the tag memory array, and with the data base address being a start address of the data memory array; a memory controller electrically connected to the tag memory array, the data memory array, and the control register, with the memory controller controlling a data access state of the tag memory array according to the mode byte and the tag base address, and with the memory controller controlling a data access state of the data memory array according to the mode byte and the data base address; and a selection module electrically connected between the tag memory array, the data memory array, and the memory controller, with the selection module permitting the memory controller to control the tag memory array and the data memory array to access data, with the memory controller including a tag draft controller and a data draft controller, with the tag draft controller electrically connected to the tag memory array, the control register, the selection module, a cache address port, and a cache data write-in port, and with the data draft controller electrically connected to the data memory array, the control register, the selection module, the cache address port, and the cache data write-in port, with the tag draft controller including a tag comparator, with the tag comparator connected to the cache address port and the tag base address with the data draft controller including a data comparator connected to the cache address port and the data base address.