Patent ID: 9601627
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. An integrated circuit comprising: a fin; a first source/drain region in the fin, the first source/drain region having a first conductivity type; a second source/drain region in the fin, the second source/drain region having a second conductivity type, the first conductivity type being different than the second conductivity type; a channel region interposed between the first source/drain region and the second source/drain region, the channel region having the second conductivity type, the second source/drain region having a higher dopant concentration of the second conductivity type than the channel region; and a gate over the channel region, the gate having a first edge closest to the first source/drain region and a second edge closest to the second source/drain region, wherein the first edge is laterally offset from an interface between the channel region and the first source/drain region in a plan view, wherein the gate and the second source/drain region are electrically coupled.