Patent ID: 9728640
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device, comprising: orienting a semiconductor layer of a semiconductor-on- insulator (SOI) substrate with a base substrate of the SOI; exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench; forming spacers on sidewalls of the trench; epitaxially growing the base substrate from a bottom of the trench to form an extended region; epitaxially growing a fin material from the extended region within the trench; restoring the mask layer and the dielectric layer over the trench; etching p-type field-effect transistor (PFET) fins on the base substrate and N-type field-effect transistor (NFET) fins in the semiconductor layer; and overetching the fins into the buried dielectric and the extended region using an etch chemistry configured to protect material of the semiconductor layer during etching.