Patent ID: 9627357
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A memory device comprising: a system element for the memory device, the system element including a plurality of pads; and a memory stack connected with the system element, the memory stack including one or more memory die layers, a connection of the system element and the memory stack including a plurality of interconnects for connecting a first memory die layer and the plurality of pads of the system element; wherein for a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, wherein the first subset of the plurality of pads are spaced such that at least one pad is located between each pad of the first subset of pads; and wherein for two or more memory die layers in the memory stack, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.