Patent ID: 9712185
Date: 2017-07-18
CPC Classifications: G06F,H03M

Claim:
1. A residue converter configured to convert a fractional binary value to a fractional residue value comprising: an input register that receives a plurality of binary input digits, the plurality of binary input digits configured as a parallel binary input receiving a binary fractional value; a modulus shift register that stores a plurality of modulus values and to output each of the plurality of modulus values in sequence; a first plurality of digit processing units that performs one or more arithmetic operations on a plurality of binary input digits and on a sequence of modulus values, and to generate a plurality of digit values and modulus values, each digit processing unit comprising: a second plurality of digit processing units that receive digit values and modulus values from said first plurality of digit processing units, and to perform one or more modular arithmetic operations on a plurality of residue digits, each digit processing unit comprising: wherein after a plurality of processing cycles, a fractional residue number equivalent to a binary fractional input is stored in the plurality of said residue digit registers.