Patent ID: 9734891
Date: 2017-08-15
CPC Classifications: G11C

Claim:
1. A circuit comprising: a static random access memory (SRAM) cell comprising at least a wordline coupled to a plurality of NFETs of a transistor array; and a wordline driver comprising a plurality of inverters coupled to a wordline group decode node, a power supply and the wordline, wherein overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage, wherein: the plurality of inverters of the word line driver are coupled to a wordline pull down network, in a retention state, the wordline pull down network comprises a first NFET and a second NFET, wherein the first NFET controls whether to pass a negative voltage to a first node and the second NFET controls whether to pass 0V (GND) to the first node, only one of the first NFET and the second NFET will be on depending on whether the retention state is on or off, such that, when the retention state is on the first NFET is on allowing the negative voltage to pass and the second NFET is off, and, when the retention state is off, the first NFET is off and the second NFET is on allowing 0V (GND) to pass, and a gate of the second NFET is coupled to the word line group decode node and a gate of the first NFET is coupled to the word line group decode node through an inverter.