Patent ID: 9660049
Date: 2017-05-23
CPC Classifications: H01L,Y10S

Claim:
1. A method for forming a transistor comprising: forming a recess in a transistor region of a semiconductor substrate, the recess extending continuously from a first shallow trench isolation (STI) region at a first end of the transistor region to a second STI region at a second end of the transistor region; introducing impurities of a first impurity type into the transistor region; forming a first silicon carbide layer over a channel region in the recess of the transistor region; forming an SiB or SiP layer over the first silicon carbide layer; forming a second silicon carbide layer over the SiB or SiP layer; forming a silicon layer over the second silicon carbide layer in the recess of the transistor region; forming a gate dielectric over the silicon layer above the channel region after forming the recess; forming a gate electrode over the gate dielectric above the channel region; and performing an angled ion implantation to introduce additional impurities of the first impurity type into the semiconductor substrate under the gate electrode, within the channel region at edges thereof while a surface of the silicon layer is exposed adjacent the channel region.