Patent ID: 9715725
Date: 2017-07-25
CPC Classifications: G06T

Claim:
1. A computer-implemented method for detecting defects on a wafer, comprising: altering one or more design clips for a current layer being inspected on the wafer based on how the one or more design clips printed on a wafer will appear in output generated by a wafer inspection process for the wafer; aligning the one or more altered design clips to the output generated for the wafer during the wafer inspection process; determining if one or more features in the output correspond to previous layer features on a layer of the wafer other than the current layer being inspected in the wafer inspection process by identifying portions of the output that appear to correspond to patterned features on the wafer that are not included in the one or more altered design clips as corresponding to the previous layer features and eliminating the one or more features corresponding to the previous layer features from the output prior to detecting defects on the wafer; and detecting the defects on the wafer based on the output aligned to the one or more altered design clips, wherein said altering, aligning, and detecting are performed by one or more computer systems.