Patent ID: 9589659
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A method of operating a memory, comprising: storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node; storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, wherein the second memory cell is a neighbor of the first memory cell; programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state, the program verify operation comprising: inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression.