Patent ID: 9595348
Date: 2017-03-14
CPC Classifications: G11C

Claim:
1. A memory circuit comprising: a control part configured to output a control signal; a fuse circuit which is driven by the control signal and is configured to output a fuse signal having a signal level determined based on a state of a first fuse element; and a holding circuit configured to update and hold a signal based on the fuse signal in response to the control signal output from the control part and to output the held signal as an output signal, wherein the fuse circuit further includes a first switch element configured to control driving of the fuse circuit based on the control signal, the first switch element having a resistance component, wherein the signal level of the fuse signal is determined based on a magnitude relationship between a resistance of the first fuse element and a resistance of the first switch element, wherein the first fuse element has one end connected to a first power supply, wherein the first switch element has one end connected to the other end of the first fuse element, the other end connected to a second power supply having an electric potential lower than an electric potential of the first power supply, and a control terminal connected to the control part, wherein the signal level of the fuse signal is determined based on an electric potential of a first node which is a connection point between the first fuse element and the first switch element, and wherein the driving of the fuse circuit is performed as the first switch element is turned on and off based on the control signal supplied to the control terminal of the first switch element.