Patent ID: 9646919
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor device package comprising: a lateral semiconductor device comprising one of interspersed and interdigitated source and drain regions and one or more gate regions; a single layer clip; a leadframe; a plurality of source pads and a plurality of drain pads coupled to the source and drain regions and the one or more gate regions, the plurality of source pads and plurality of drain pads arranged in one of an interspersed arrangement and an interdigitated arrangement with respect to each other; a plurality of source tracks coupled to the plurality of source pads, the plurality of source tracks comprising a plurality of source standoff contacts; a plurality of drain tracks coupled to the plurality of drain pads, the plurality of drain tracks comprising a plurality of drain standoff contacts; and at least one gate pad, the at least one gate pad coupled to one or more gate standoff contacts; wherein the single layer clip is coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe; wherein the single layer clip is configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.