Patent ID: 9705518
Date: 2017-07-11
CPC Classifications: A61B,H03M

Claim:
1. An apparatus, comprising: at least one ultrasonic transducer; a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR ADC in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and an SAR controller that receives a first clock signal and a second clock signal as inputs thereto; wherein the SAR controller is configured to generate a first control signal in response to the first clock signal that causes the sample and hold stage to sample an input analog signal thereto, and to generate a second control signal in response to the second clock signal that causes the comparator to compare the sampled input analog signal to an output signal of the DAC, with an output of the comparator configured to generate a DAC update event corresponding to an individual bit conversion; and wherein conversion of a most significant bit (MSB) of the SAR ADC is triggered by the second control signal being responsive to the second clock signal, and conversion of other bits of the SAR ADC is triggered by the second control signal being responsive to a previous bit conversion.