Patent ID: 9627057
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. A memory, comprising: a set of two-terminal memory cells having respective first terminals connected to respective bitlines of a set of bit lines of the memory, and having respective second terminals connected to a first local wordline of a set of local wordlines of the memory, wherein a number of bitlines of the set of bit lines is less than a second number of local wordlines of the set of local wordlines, and a second local wordline of the set of local wordlines is connected to a second set of two-terminal memory cells that connect to respective bitlines of a second set of bit lines, wherein the first local wordline and the second local wordline are on a same row in an array of two-terminal memory cells; a power source configured to be selectively connected to or disconnected from respective ones of the set of local wordlines, wherein the first local wordline and the second local wordline are configured to be connected to or disconnected from the power source by a single global wordline of the memory; and a memory controller configured to perform memory operations for the memory, and configured to program a memory cell of the set of two-terminal memory cells at least in part by performance of operations comprising: activation of the single global wordline, and selective connection of the power source to the first local wordline and a second terminal of the memory cell, and selective electrical isolation of the power source from the second local wordline that is not connected to the memory cell; and application of a program signal from the power source to the first local wordline, wherein the program signal provides a higher potential to the first local wordline than a second voltage applied to a bitline of the set of bitlines that is connected to the memory cell.