Patent ID: 9564500
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method of forming a metal-oxide semiconductor field-effect transistor (MOSFET) device, the method comprising the steps of: providing a semiconductor-on-insulator (SOI) wafer comprising an SOI layer separated from a substrate by a buried oxide (BOX); forming a dummy gate oxide and one or more dummy gates on portions of the SOI layer that serve as channel regions of the MOSFET device, wherein the dummy gate oxide separates the dummy gates from the SOI layer, and wherein the dummy gates are formed by blanket depositing a poly-silicon layer on the wafer, patterning dummy gate hardmasks on the poly-silicon layer with a footprint and location of the dummy gates, and etching the poly-silicon layer using the dummy gate hardmasks to form the dummy gates; forming spacers on opposite sides of the dummy gates; forming doped source and drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric on the wafer, filling any gaps between the spacers; removing the dummy gates and the dummy gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates and the dummy gate oxide to form one or more u-shaped grooves that extend part way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source and drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.