Patent ID: 9728558
Date: 2017-08-08
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising a base substrate, and a plurality of pixel units arranged in a matrix, each of which has a pixel electrode, wherein, with two adjacent rows of the pixel units as a group of pixel unit rows, each group of the pixel unit rows share one gate line located between the two rows of the pixel units, and there is one data line between every two adjacent columns of the pixel units; in each group of the pixel unit row, pixel electrodes in two adjacent pixel units of a same column are respectively electrically connected with two output terminals of a composite transistor, a control terminal of the composite transistor being electrically connected with the gate line, and an input terminal of the composite transistor being electrically connected with the data line; wherein, the composite transistor respectively opens conductive paths between the two output terminals and the input terminal under control of different levels of control voltages, wherein the composite transistor includes a first thin film transistor and a second thin film transistor which are disposed in a stacking manner in a direction perpendicular to the base substrate; one of the first thin film transistor and the second thin film transistor is of top gate type, and the other one is of bottom gate type; and wherein the first thin film transistor and the second thin film transistor share a gate electrode.