Patent ID: 9576665
Date: 2017-02-21
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the plurality of memory cells, the plurality of memory cells including a first memory cell and a second memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; and a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, wherein a data writing operation includes applying first to n-th (n is an integer of 2 or more) program voltages to a word line and applying first to n-th verify voltage to the word line, the k-th (k is an integer that satisfies 1≦k≦n) verify voltage being applied after the k-th program voltage, the (m+1)-th (m is an integer that satisfies 1≦m≦(n−1)) program voltage is larger than the m-th program voltage, when the first string is selected and the first word line is selected, a first voltage is applied to the first word line before the first program voltage is applied to the first word line, and the first voltage is larger than the first program voltage.