Patent ID: 9570308
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method for fabricating a transistor including a gate structure, a source/drain extended region, a source/drain region and a halo region, the method comprising: performing a hot temperature implantation using a first species to form the source/drain region having a broadened doping profile, wherein the hot temperature implantation is performed at a temperature higher than a room temperature; performing a cold temperature implantation using a second species to form the halo region having a suppressed doping profile, wherein the cold temperature implantation is performed at a temperature lower than the room temperature; and performing an additional hot temperature implantation using a third species to form the source/drain extended region, wherein the first species and the third species comprises the same material, wherein the halo region covers the source/drain extension region, and covers a side portion of the source/drain region that is adjacent to the gate structure, and wherein the source/drain region extension region contact with the side portion of the source/drain region, and has a depth shallower than the source/drain region.