Patent ID: 9627416
Date: 2017-04-18
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a substrate; a plurality of gate lines and a plurality of data lines disposed on the substrate, wherein the gate lines and the data lines are insulated from each other and cross each other, and are connected to a plurality of pixel units, wherein the plurality of pixel units comprise at least a first set of pixel units, wherein the first set of pixel units comprises a first pixel unit, a second pixel unit, and a third pixel unit, and wherein a first data line is disposed between the first pixel unit and the second pixel unit; a first insulating layer disposed above the first data line; first and second signal lines electrically connected to each other, and disposed on the first insulating layer, wherein the first pixel unit comprises a first film transistor, and the second pixel unit comprises a second film transistor, and wherein each of the first and second film transistors includes a gate electrode, a first electrode, and a second electrode, a second insulating layer disposed on the first signal line and on the second signal line, wherein a common electrode layer is disposed on the second insulating layer, wherein a region of the common electrode layer between the third pixel unit and the first pixel unit is electrically insulated and the electrically insulated region of the common electrode layer is a common electrode opening region, and wherein a projection of a region of the common electrode layer between the first pixel unit and the second pixel unit on the first data line is overlapped with the first data line.