Patent ID: 9536029
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. A method comprising: encoding, by use of a processor, a logic design as a linear array comprising a plurality of logic states, each logic state comprising one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values; displaying combination maps of a plurality of fields at two or more successive display levels having a top display level and at least one lower display level, wherein each field corresponds to one or more minterms; receiving a selection of a first field of the plurality of fields; displaying the first field and one or more successive combination maps for the first field, wherein each of the one or more successive combination maps is displayed with a field identifier of a predecessor field; and displaying relationship arrows linking the first field and each successive field of the first field.