Patent ID: 9742424
Date: 2017-08-22
CPC Classifications: H03M

Claim:
1. An analog-to-digital converter (ADC) comprising: a comparator arrangement comprising two comparators; a digital-to-analog converter (DAC) arrangement comprising two DACs, wherein each DAC of the two DACs is connected to a respective comparator of the two comparators; and an adder circuit connected to the comparator arrangement, wherein the ADC is configured to receive an input value and further configured, over a plurality of conversion cycles of the ADC, to generate an output value representative of the input value, wherein, for each respective DAC, the DAC is configured to sample the input value, and to generate a plurality of threshold levels over the plurality of conversion cycles, the sampled input value and the plurality of threshold levels to be received by the respective comparator, wherein the plurality of threshold levels are defined, at least in part, by predetermined redundancy levels that are binary-scaled over the plurality of conversion cycles and generated by the DAC, and, wherein a respective threshold level of the plurality of threshold levels is associated with a respective conversion cycle of the plurality of conversion cycles, wherein the comparator arrangement is configured to provide an output code for the respective conversion cycle based on the sampled input value and the respective threshold level associated with at least one of the two comparators, and, wherein, for at least two adjacent conversion cycles of the plurality of conversion cycles, the two comparators are adapted to collectively provide output codes having two bits based on the sampled input value and the respective threshold levels associated with the two comparators, wherein the respective threshold levels for a predetermined conversion cycle of the at least two adjacent conversion cycles is dependent on the output code having two bits of a previous conversion cycle of the at least two adjacent conversion cycles, and wherein the adder circuit is configured to provide a plurality of output bits corresponding to the output value, wherein the adder circuit is capable of overlapping and adding a first significant bit of the output code having two bits provided for the predetermined conversion cycle with a second significant bit of the output code having two bits provided for the previous conversion cycle to generate one output bit of the plurality of output bits.