Patent ID: 9612461
Date: 2017-04-04
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a gate line and a data line intersecting with each other to define a plurality of pixel regions arranged in a matrix form; a thin film transistor disposed in a vicinity of an intersection of the gate line and the data line, a gate electrode of the thin film transistor being connected to the gate line, and a source electrode of the thin film transistor being connected to the data line; and a common electrode and a pixel electrode disposed in each pixel region, wherein the common electrode is provided with a plurality of patterns of strip hole structure respectively above each pixel region, the gate line, the data line and the common electrode are fabricated on different layers and partially overlap each other, and the common electrode is provided with a pattern of a first hole structure at the intersection of the gate line and the data line.