Patent ID: 9659342
Date: 2017-05-23
CPC Classifications: G06F,G06T

Claim:
1. A method comprising: setting a valid address in a pointer register to a buffer location by a scheduler, the addressed buffer location being a start of an instruction sequence of a second context; executing instructions of a first context at a graphics processor and incrementing a head pointer after the execution of each instruction, the head pointer indicating the location of a next instruction to be executed, the context having a sequence of instructions in a first addressable buffer, at least one of the instructions being a preemption instruction, the preemption instruction having a reference to the address in the pointer register that was set by the scheduler; updating the head pointer based on the address in the pointer register; upon executing the preemption instruction, stopping execution of the first context before the sequence of instructions is completed; storing an address for an instruction with which the first context will be resumed; executing the second context at the graphics processor based on the updated head pointer; and upon completion of the execution of the second context, resuming the execution of the first context at the stored address and updating the head pointer based on the stored address.