Patent ID: 9650240
Date: 2017-05-16
CPC Classifications: B81B,B81C

Claim:
1. A method for manufacturing a vertical hybrid integrated component, the method comprising: providing at least two semiconductor elements; and bonding the two elements to one another via a bond of at least one metallic starting layer and at least one further starting layer, at least one of the two element surfaces to be bonded being provided with the at least one metallic starting layer, out of which at least one first layer area is structured, at least one of the two element surfaces to be bonded being provided with at least one further starting layer, out of which at least one second layer area is structured which is situated so that it forms together with the first layer area of the first starting layer a bonding layer for the two elements during the bonding process, wherein the starting layers are structured so that the layer areas which are assigned to one another have differently sized areal extents and the layer thicknesses of the two starting layers are selected so that the layer areas which are assigned to one another meet the material ratio necessary for the bonding process; wherein the at least two semiconductor elements include at least one of: (i) at least two MEMS elements; at least two ASIC elements; and at least one MEMS element and at least one ASIC element, and wherein the elements of the vertical hybrid integrated component are situated above one another in the form of a chip stack and are bonded to one another.