Patent ID: 9535125
Date: 2017-01-03
CPC Classifications: B82Y,G01R

Claim:
1. A test access port comprising: a test clock input; a test mode select input; a test data in input; a test data out output; a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input; an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the control bus input of the controller, the instruction register also having a mode signal output and a test signal output; a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the test signal output, the Update-DR signal, and the Shift-DR signal, the boundary scan register having a modified Clock-DR input, the boundary scan register including an observe only input boundary cell having a test input connected to the test signal output, a Shift-DR input connected to the Shift-DR signal, and a modified Clock-DR input connected to the modified Clock-DR input; a delay circuit connected to the test clock input and having a delayed clock output; and decay test circuitry having inputs connected to the delayed clock output, the control bus output, the Update-DR signal, the Clock-DR signal, and having a modified Clock-DR output connected to the modified Clock-DR input to test the RC time decay of functional signals received by the boundary scan register, the decay test circuitry having a capture test strobe enable input and the control bus output includes a capture test strobe enable output connected to the capture test strobe enable input of the decay test circuitry.