Patent ID: 9748289
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A manufacturing method for a semiconductor device comprising: forming gate electrodes over corresponding gate insulation film portions on a first and second regions on a substrate and the second region having a cell and at least one transistor; forming a first impurity introducing region by introducing an impurity to the first and second regions using said gate electrodes as a mask; forming a first conductivity type region in the second region; stacking a first insulating film and a second insulating film on the whole surface of said first region and said second region; forming a mask on the second region; forming a sidewall comprised of the first and second insulating films; forming a second impurity introducing region by introducing an impurity using the sidewall and the gate electrode as a mask; forming a sidewall of a single layer film made of a third insulating film on the side wall of the gate electrodes in said first region and forming a sidewall by said third insulating film through said first and second insulating films on the side wall of said gate electrodes in said second region by forming a third insulating film on the whole surfaces of said first region and said second region and there after etching back said third insulating film; forming a third impurity introducing region by introducing an impurity in said first region and said second region using said gate electrodes and said sidewall as a mask; and forming a silicide layer at the third impurity introducing region of said first region or at said third impurity introducing region and the gate electrodes and wherein the second region with an image sensor is substantially entirely free of any silicide material throughout the entire image sensor region and wherein the silicide layer is formed by forming a metal film and selectively removing non-reacted portions to form the silicide layer by a salicide method; and further wherein the second region includes locations of protective circuit elements.