Patent ID: 9620073
Date: 2017-04-11
CPC Classifications: G09G,G11C

Claim:
1. A gate driving circuit comprising a plurality of shift register circuits, the plurality of shift register circuits being cascade-connected in series, each of the plurality of shift register circuits comprising: a first pull-up circuit, a second pull-up circuit, a first pull-down circuit, a second pull-down circuit and a pull-down control circuit; wherein the first pull-up circuit and the second pull-up circuit are electrically connected in series between a preceding-stage gate driving signal and a gate driving signal output terminal; the first pull-down circuit, the second pull-down circuit and the pull-down control circuit are electrically connected with the first pull-up circuit and the second pull-up circuit in parallel; the pull-down control circuit is electrically coupled to the preceding-stage gate driving signal, the first pull-down circuit, the second pull-down circuit, a first voltage level and a second voltage level; and the pull-down control circuit is configured for controlling the first pull-down circuit and the second pull-down circuit according to the preceding-stage gate driving signal; wherein the shift register circuit further comprises a first capacitor and a second capacitor; the first pull-up circuit comprises a first transistor, a gate and a sourced of the first transistor are electrically connected to receive the preceding-stage gate driving signal; the second pull-up circuit comprises a second transistor, a gate of the second transistor is electrically connected to a drain of the first transistor, a source of the second transistor is electrically connected to receive a first clock signal, and a drain of the second transistor is electrically connected to the gate driving signal output terminal; the first capacitor is electrically connected between the drain and the gate of the second transistor; the first pull-down circuit comprises a third transistor, a source of the third transistor is electrically connected to the gate driving signal output terminal, and a drain of the third transistor is electrically connected to the first voltage level; the second pull-down circuit comprises a fourth transistor, a source of the fourth transistor is electrically connected to the drain of the first transistor, and a drain of the fourth transistor is electrically connected to the first voltage level; a terminal of the second capacitor is electrically connected to the first voltage level, and another terminal of the second capacitor is electrically connected to the gate of the third transistor and the gate of the fourth transistor.