Patent ID: 9595344
Date: 2017-03-14
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a memory cell array in which memory cells are provided; word lines, including a first word line, a second word line and third word lines, connected to the memory cells, and the third word lines located between the first and second word lines; and a control circuit, wherein the memory cell array has at least two select transistors and memory cells connected in series between the select transistors, the select transistors have gates connected to at least two select lines, the first word line is connected to a first memory cell of the memory cells next to at least one of the select transistors, the second word line is connected to a second memory cell of the memory cells next to at least another one of the select transistors, and the third word line is connected to a third memory cell of the memory cells, and wherein the control circuit erases the first, second and third memory cells in an erase operation, and the control circuit, in the erase operation, sets a first voltage to the first word line, sets a second voltage to the second word line, and sets a third voltage less than the first and second voltages to the third word lines.