Patent ID: 9748271
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A hybrid circuit comprising: a tunneling field effect transistor (TFET) comprising a positively doped TFET source, a TFET body, a negatively doped TFET drain, and a TFET gate, wherein the TFET gate is electrically connected to a bias supply voltage, Vbias; a metal oxide field effect transistor (MOSFET) comprising a negatively doped MOSFET source, a MOSFET body, a negatively doped MOSFET drain, and a MOSFET gate, wherein the negatively doped MOSFET drain is electrically connected to the positively doped TFET source; and a negative supply voltage, Vss, electrically connected to the MOSFET source, wherein an impedance of the MOSFET gate is lower than an impedance of the TFET drain.