Patent ID: 9698970
Date: 2017-07-04
CPC Classifications: H03K,H03L

Claim:
1. A phase interpolator circuit, comprising: a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to output thermometer codes; a pre-mixer configured to receive input clock signals and provide pre-mixed clock signals, the pre-mixer segmented into a plurality of unit circuits that are enabled or disabled based on bits of a first pre-mixer thermometer code of the thermometer codes; a mixer configured to receive the pre-mixed clock signals and provide mixed clock signals, the mixer segmented into a plurality of unit circuits that are enabled or disabled based on bits of a first mixer thermometer code of the thermometer codes; and a post-mixer configured to receive the mixed clock signals and provide output clock signals, the post-mixer segmented into a plurality of unit circuits that are enabled or disabled based on bits of a first post-mixer thermometer code of the thermometer codes.