Patent ID: 9558816
Date: 2017-01-31
CPC Classifications: G11C

Claim:
1. A method of adjusting read voltages for a NAND flash memory device, the method comprising: reading first page data from a first page corresponding to a paired page of a second page; dividing a range of a first test read voltage and a range of a third test read voltage into a plurality of sections; simultaneously changing the first test read voltage and the third test read voltage to read second page data from a second page; performing a bitwise operation on the first page data and the second page data; counting a number of memory cells corresponding to a first threshold voltage state and a fourth threshold voltage state by using a result of the bitwise operation; and setting a first read voltage as a voltage corresponding to a section in which a change in the number of memory cells corresponding to the first threshold voltage state is a lowest value in the range of the first test read voltage, and setting a third read voltage as a voltage corresponding to a section in which a change in the number of memory cells corresponding to the fourth threshold voltage state is a lowest value in the range of the third test read voltage.