Patent ID: 9610543
Date: 2017-04-04
CPC Classifications: B01D,B81B,B81C,Y10T

Claim:
1. A method comprising: providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface; performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, wherein the plurality of individual semiconductor chips comprises at least one of membrane filters, sieves, grids, hole plates, and pressure impulse attenuators; and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.