Patent ID: 9627087
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. A memory device comprising: a string unit including a plurality of memory cell transistors which are connected in series, a first select transistor connected to a first end of the plurality of memory cell transistors, and a second select transistor connected to a second end of the plurality of memory cell transistors; and a bit line connected to the first select transistor, wherein: the memory device is configured to execute a program on a selected memory cell transistor of the string unit, and to verify a result of the program, and the memory device is configured to cause, at a time of verifying the result, while charging the bit line, a voltage of a control gate electrode of the selected memory cell transistor to transition to a low state, and to cause a voltage of a control gate electrode of an unselected memory cell transistor to transition from a low state to a high state, after setting the first select transistor and the second select transistor to an OFF state.