Patent ID: 9704765
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method of controlling an etch-pattern density of a polysilicon layer on a surface of a semiconductor wafer for facilitating process control of a polysilicon-etch processing step, the method comprising the steps of: depositing the polysilicon layer on the surface of the semiconductor wafer, wherein the semiconductor wafer comprises circuit-device areas and non-circuit-device areas, the circuit-device areas having active or passive electronic devices manufactured thereon, and the non-circuit-device areas having no active or passive electronic devices manufactured thereon; determining polysilicon-etch regions within the circuit-device areas, the determined polysilicon-etch regions including one or more source regions of one or more DMOS devices; calculating an etch area of the polysilicon-etch regions; comparing the calculated etch area of the polysilicon-etch regions to a predetermined minimum etch area; adding the polysilicon-etch regions within the non-circuit-device areas to the determined polysilicon-etch regions within the circuit-device areas until the comparing step results in the calculated etch area of the polysilicon-etch regions being greater than the predetermined minimum etch area; and etching the polysilicon from the polysilicon-etch regions in both the circuit-device areas and the non-circuit-device areas.