Patent ID: 9536946
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate having a plurality of active regions; device isolation disposed in the substrate to define the active regions, upper portions of the active regions protruding upward beyond the device isolation; a gate structure intersecting the plurality of active regions and extending longitudinally in a first direction parallel to a top surface of the substrate; a plurality of first source/drain regions and a plurality of second source/drain regions adjacent opposite sides of the gate structure, respectively; and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively, wherein each of the first source/drain regions is in contact with the first modified contact, at least one of the second source/drain regions is in contact with the second modified contact, and the number of the second source/drain regions in contact with the second modified contact is less than the number of the first source/drain regions in contact with the first modified contact.