Patent ID: 9536467
Date: 2017-01-03
CPC Classifications: G02F,G09G

Claim:
1. A display device comprising: a plurality of pixels a plurality of scanning signal lines supplying a scanning signal to the plurality of pixels respectively, a driving circuit sequentially applying the scanning signal from one ends of the plurality of scanning signal lines, a first clock signal line supplying a first clock signal to the driving circuit, a third clock signal line supplying a third clock signal to the driving circuit, wherein the driving circuit has multiple stages of circuit blocks which output the scanning signal to the plurality of scanning signal lines, wherein at least one stage of the circuit block in the multiple stages of circuit blocks includes, a first transistor that has a gate being connected to a first node having an active potential during an output period including a period in which the scanning signal is applied to the corresponding scanning signal line, and controls electrical conduction between the first clock signal line and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period which is a period other than the output period, and controls electrical conduction between the first node and an inactive potential line fixed to an inactive potential, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and the third clock signal line, a fourth transistor that is diode-connected between the third clock signal line and the second node, wherein the third clock signal has an active potential at the time of termination of the output period and an inactive potential during the output period.