Patent ID: 9570516
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of fabricating memory cells, comprising: depositing onto a substrate a first layer stack, wherein the substrate includes a plurality of selector contacts and wherein the selector contacts have an upper surface; patterning and etching the first layer stack to form a plurality of word lines and to form a plurality of trenches; depositing a first insulating layer within the plurality of trenches; etching a first insulating layer; depositing a metal within the plurality of trenches; patterning and etching the metal to form a vertical post and to form a plurality of holes, wherein the vertical posts are disposed on the upper surface of the selector contacts; depositing a second insulating layer within the plurality of holes; etching the second insulating layer, wherein the etching is biased towards a side of each of the plurality of holes; and depositing a conductive material into the plurality of holes.