Patent ID: 9548401
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a lower electrode comprising first and second impurity diffusion regions in an active region of a substrate, the first and second impurity diffusion regions having different doping concentrations; an upper electrode facing both the first and second impurity diffusion regions of the lower electrode; and an insulating layer interposed between the first and second impurity diffusion regions of the lower electrode and the upper electrode, and wherein the lower electrode, the upper electrode and the insulating layer constitute a single MOS capacitor, and the second impurity diffusion region has a bottom and sides, and the first impurity diffusion region surrounds the second impurity diffusion region along the bounds of the sides of the second impurity diffusion region such that the first impurity region extends around the second impurity diffusion region.