Patent ID: 9728719
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. An integrated circuit device, comprising: a metal-insulator-metal structure including a first dielectric layer between a top conductive layer and a bottom conductive layer, wherein an outermost sidewall of the top conductive layer is aligned with an outermost sidewall of the bottom conductive layer; a capping layer separating the first dielectric layer from the top conductive layer, the capping layer having a composition that differs from the top conductive layer; a diffusion barrier layer under and contacting a bottom surface of the bottom conductive layer, wherein the diffusion barrier layer and the bottom conductive layer collectively have a T-shaped profile; wherein the first dielectric layer comprises: the top conductive layer abuts and is above the capping layer; the bottom conductive layer abuts and is below the central region of the first dielectric layer; and the bottom conductive layer does not abut the peripheral region of the first dielectric layer.