Patent ID: 9601497
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A Static Random Access Memory (SRAM) cell, comprising: a first pull-up transistor and a first pull-down transistor; a second pull-up transistor and a second pull-down transistor; first and second pass-gate transistors; a first buried contact electrically connecting a drain region of the first pull-up transistor and gate electrodes of the second pull-up transistor and the second pull-down transistor, and including a first metal layer formed in a region confined by spacers of a first gate layer by which the gate electrodes of the second pull-up transistor and the second pull-down transistor are formed and a first electrically conductive path formed at a level below the spacers of the first gate layer; and a second buried contact electrically connecting a drain region of the second pull-up transistor and gate electrodes of the first pull-up transistor and the first pull-down transistor, and including a second metal layer formed in a region confined by spacers of a second gate layer by which the gate electrodes of the first pull-up transistor and the first pull-down transistor are formed and a second electrically conductive path formed at the level below the spacers of the second gate layer.