Patent ID: 9729155
Date: 2017-08-08
CPC Classifications: H01L,H03K

Claim:
1. A field programmable gate array (FPGA), comprising: a switching block routing array comprising a plurality of signal inputs and a plurality of signal outputs; a transistor element coupled to the switching block routing array, wherein the transistor element comprises a gate, a first terminal and a second terminal, wherein the first terminal is coupled to a signal input from the plurality signal inputs, and wherein the second terminal is coupled to a signal output from the plurality of signal outputs, and wherein the gate is configured to electrically couple the signal input to the signal output in response to a gate control signal and wherein the transistor element, the signal input and the signal output form a first junction of the switching block routing array; a plurality of resistive elements coupled to the transistor element, wherein each resistive element from the plurality of resistive elements comprises a first electrode and a second electrode, wherein each resistive element is characterized by a plurality of resistive states including a low resistive state and a high resistive state, wherein each resistive element is characterized by a polarity, wherein the polarity for each resistive element is characterized by a high resistive state in response to a first voltage applied from the second electrode to the first electrode exceeding an erase voltage and is characterized by a low resistive state in response to a second voltage applied from the first electrode to the second electrode exceeding a programming voltage, wherein the plurality of resistive elements includes a first resistive element and a second resistive element, wherein a first electrode of the first resistive element is selectively coupled to a first plurality of voltages, wherein a first electrode of the second resistive element is selectively coupled to a second plurality of voltages, wherein the plurality of resistive elements provides the gate control signal in response to a first resistive state of the first resistive element, to a second resistive state of the second resistive element, to a first voltage from the first plurality of voltages and to a second voltage from the second plurality of voltages; a shared node coupled to a second electrode of the first resistive element, to a second electrode of the second resistive element, and to the gate of the transistor element; a programming circuit coupled exclusively to the shared node of the first resistive element and the second resistive element via an output path, wherein the programming circuit is configured to facilitate entry to the first resistive state of the first resistive element in response to a first voltage applied to the shared node, and wherein the programming circuit is configured to facilitate entry of the second resistive state of the second resistive element in response to a second voltage applied to the shared node; a second transistor element coupled to a second junction of the switching block routing array, the first junction and the second junction sharing a row of the FPGA; a second plurality of resistive elements having a second shared node that is coupled to the second transistor element; a second programming circuit coupled exclusively to the second shared node of the second plurality of resistive elements; a row program transistor coupled to both the programming circuit and to a second programming circuit associated with the second transistor element, the row program transistor comprising a gate that is conductively connected to activation inputs of the programming circuit and of the second programming circuit, and comprising a drain conductively connected to, and configured to apply the first plurality of voltages to, both the first electrode of the first resistive element and to a corresponding first electrode of the second plurality of resistive elements.