Patent ID: 9646982
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a pair of wires extending in a first direction with a first interval; a pair of leading lines, each of the leading lines being drawn from an end portion of the corresponding wire, and the leading lines extending, with a second interval wider than the first interval, in a second direction crossing the first direction; a dummy pattern provided between the pair of leading lines, an interval between the dummy pattern and the leading line and an interval between the dummy pattern and the wire being less than 100 nm; and a pair of pads provided between the pair of leading lines at the side of the second direction with respect to the dummy pattern, each of the pads being connected to the corresponding leading line, wherein the dummy pattern comprises a first dummy pattern and a second dummy pattern arranged in the first direction and separated from each other, the first dummy pattern is connected to one of the pair of pads in the second direction, and the second dummy pattern is connected to the other of the pair of pads in the second direction.