Patent ID: 9606920
Date: 2017-03-28
CPC Classifications: G06F,Y02D

Claim:
1. A multi-CPU processor comprising: a first multi-core CPU including a first core, a second core and a first cache controller connected in signal communication to the first and second cores; a second multi-core CPU including a third core, a fourth core and a second cache controller connected in signal communication to the third and fourth cores; and an L2 cache including a first area and a second area: wherein the first area includes a shared first portion and a dedicated second portion, the first cache controller connected in signal communication to the shared first portion and the second cache controller connected in signal communication to the shared first portion and the dedicated second portion, wherein the second area includes a shared third portion and a dedicated fourth portion, the first cache controller is connected in signal communication to the shared third portion and the second cache controller is connected in signal communication to the shared third portion and the dedicated fourth portion, the first multi-core CPU includes the shared first portion and the shared third portion, the second multi-core CPU includes the L2 cache including the shared first portion, the dedicated second portion, the shared third portion and the dedicated fourth portion, the shared first portion and the shared third portion are shared physically by the first multi-core CPU and the second multi-core CPU, the first cache controller is configured to control access to the shared first portion and the shared third portion, the second cache controller is configured to control access to the shared first portion and the dedicated second portion, the shared third portion, and the dedicated fourth portion, and power supplied to each of the first core, the second core, the third core, the fourth core, the shared first portion, the dedicated second portion, the shared third portion and the dedicated fourth portion is controlled independently to facilitate CPU scaling from the first multi-core CPU to the second multi-core CPU.