Patent ID: 9622352
Date: 2017-04-11
CPC Classifications: H01L,H05K,Y02P,Y10T

Claim:
1. A manufacturing method for a component incorporated substrate in which, in an insulating substrate including a wiring pattern on a surface, an electric or electronic component including a terminal electrically connected to the wiring pattern is incorporated, the manufacturing method comprising: a mark forming step for forming a copper layer to be patterned as the wiring layer on a supporting plate and forming a mark formed by a plating method on a second surface on an opposite side of a first surface in contact with the supporting plate of the copper layer, the mark having a proximal end face in contact with the second surface, a side surface extending from an outer circumferential edge of the proximal end face in a direction orthogonal to the second surface, an outer circumferential curved surface tapering and extending in an arcuate shape from a proximal end edge of the side surface, and a top surface extending from a distal end edge of the outer circumferential curved surface and opposed to the proximal end face; a component mounting step for, after detecting the mark using detecting means for detecting a detection target in a square search range set in an image pickup screen that reflects a picked-up image of the detection target, positioning the component with reference to the detected mark and mounting the component on the second surface of the copper layer with an insulative adhesive layer interposed therebetween; an embedding layer forming step for forming, on the second surface of the copper layer on which the component is mounted, an embedding layer functioning as the insulating substrate in which the component and the mark are embedded; a window forming step for, after peeling the supporting plate off the copper layer, etching and removing, with a copper etching agent used for etching of copper, a part of the copper layer from the first layer side of the copper layer exposed by the peeling and forming a window for partially exposing the embedding layer together with the entire proximal end face of the mark; a conduction via forming step for specifying a position of the terminal of the component with reference to the mark exposed from the window and, after forming a via hole reaching the terminal, filling a conductive material in the via hole and forming a conduction via for electrically connecting the terminal and the copper layer; and a pattern forming step for forming the copper layer electrically connected to the terminal via the conduction via into the wiring pattern, wherein in the mark forming step, when an imaginary line extending from a search center, which is a center of the search range, to an edge side of the search range is represented as a search reference line and an imaginary line extending, in a state in which a center of the mark is matched with the search center, from the center of the mark in a same direction as the search reference line and to an outer ridgeline, which is a boundary between the top surface and the outer circumferential curved surface in the mark, is represented as a mark reference line, the mark is formed in a shape in which the outer ridgeline of the mark is present in a position where a length of the mark reference line is in a range of 30% or more of the search reference line.