Patent ID: 9620175
Date: 2017-04-11
CPC Classifications: G11C

Claim:
1. A semiconductor memory including: a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and a plurality of sense amplifiers which are disposed corresponding to the plurality of bit line pairs respectively, and each comprising an amplifier portion for amplifying a potential difference between the bit line pair, a switch portion for switching the connection of the bit line pair and a data bus line, and a precharge portion for precharging the bit line pair, in which the plurality of sense amplifiers are arranged in a vertical direction perpendicular to the extending direction of the bit line, and a number of repetition of a layout pattern of the amplifier portion of the plurality of the sense amplifiers arranged in the vertical direction is different from a number of repetitions of the layout pattern of the switch portion or the precharge portion of the plurality of sense amplifiers arranged in the vertical direction.