Patent ID: 9590021
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. An array substrate, comprising a substrate having a first surface and a first data line, a second data line, a gate line, a first electrode, a second electrode, and a thin-film transistor formed on the first surface of the substrate, wherein the gate line is connected to the gate, the first data line and the first electrode being respectively connected to the first source and the first drain, the second data line and the second electrode being respectively connected to the second source and the second drain; and wherein the thin-film transistor comprises a gate, a first source, a second source, a first drain, a second drain, a first semiconductor layer, a second semiconductor layer, a first insulation layer, and a second insulation layer, the gate comprising a first surface and a second surface that are opposite to each other, the first insulation layer being formed on the first surface and covering the first surface, the first semiconductor layer being formed on the first insulation layer, the first drain and the first source being formed on the first semiconductor layer in a spaced manner, the second insulation layer being formed on the second surface and covering the second surface, the second semiconductor layer being formed on the second insulation layer, the second drain and the second source being formed on the second semiconductor layer in a spaced manner; wherein the first electrode is a block electrode, the second electrode being a strip electrode, the first electrode being spaced from the substrate by a distance that is smaller than a distance by which the second electrode is spaced from the substrate, the first electrode and the second electrode being located at different layers.