Patent ID: 9691840
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method comprising: forming a first opening in a first region of a substrate, wherein the first opening extends from a front surface of the substrate into the substrate; forming a second opening in a second region of the substrate, wherein the second opening extends from the front surface into the substrate; forming a first conductive layer to fully fill the first opening and partially fill a portion of the second opening; forming a first insulation layer over the first conductive layer; forming a second conductive layer over the first insulation layer; performing a planarization process to remove excess portions of the first conductive layer, the first insulation layer, and the second conductive layer, wherein the excess portions are outside the first opening and the second opening; forming a second insulation layer over the second conductive layer; forming a third conductive layer over the second insulation layer, wherein the second insulation layer and the third conductive layer are filled into the second opening; and after the third conductive layer is formed, grinding a back surface of the substrate to expose the first conductive layer, the first insulation layer and the second conductive layer, wherein the first conductive layer, the first insulation layer, and the second conductive layer form a capacitor in the second opening, and the first conductive layer forms a through-substrate via (TSV) in the first opening.