Patent ID: 9703579
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. An emulation environment for debugging an electronic design concurrently emulated with other electronic designs, the emulation environment comprising: an emulation system including an emulator including configurable hardware and connection structure to interconnect the configurable hardware, the emulator configurable to implement multiple electronic designs, emulated simultaneously using the configurable hardware, as a combined model of the multiple electronic designs, an emulation clock manager configured to maintain independent clocks for the multiple electronic designs, and a virtual model link configured to facilitate message traffic with the emulator; an emulation trace module configured to capture trace data from a selected one or more of the multiple electronic designs during operation of the emulator; and a model state module comprising memory circuitry within the emulator configured to capture state data corresponding to a selected one or more of the multiple electronic designs during operation of the emulator.