Patent ID: 9747225
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. An interrupt controller, comprising: a fabric slave circuit to connect to a fabric for a computing system, the fabric slave circuit configured to receive requests for MMIO interrupts for different interrupt targets in the form of MMIO write requests received from the fabric, each of the MMIO write requests include a respective MMIO address and respective MMIO write data, the respective MMIO write data includes an indication of a task to be done for a respective MMIO interrupt; a plurality of output interrupt lines that connect to the different interrupt targets; a plurality of interrupt registers, each interrupt register corresponds to at least one output interrupt line of the plurality of output interrupt lines, each interrupt register is configured to store one or more indications of tasks to be done for one or more MMIO interrupts for the corresponding output interrupt line, storing one or more indications of tasks to be done for one or more MMIO triggers assertion of the corresponding output interrupt line; and a MMIO routing circuit connected to the fabric slave circuit and the plurality of interrupt registers, the MMIO routing circuit configured to route MMIO write data received from the fabric by the fabric slave circuit to any of the interrupt registers based on the respective MMIO address.