Patent ID: 9728276
Date: 2017-08-08
CPC Classifications: G11C

Claim:
1. An integrated circuit, comprising: a core circuit to execute operations of the integrated circuit; and a memory storing a subsystem and a repair system, wherein when the repair system runs, the repair system detects whether there is a defect in the memory, when the repair system detects the defect, the repair system repairs the defect according to a repair approach selected from a defect-repair library, and when the repair system does not detect a defect, a fake defect is injected into the memory to verify whether the repair system runs correctly, wherein the core circuit is further configured to: access a defect model library which stores repair approaches for repairing different types of fake defects; acquire one of the repair approaches from the defect model library as an expected repair approach, the expected repair approach corresponding to the fake defect injected into the memory; enable the repair system to detect the memory for the fake defect injected into the memory and acquire an actual repair approach adopted by the repair system according to the defect-repair library in response to a detection of the fake defect injected into the memory; and check whether the actual repair approach adopted by the repair system according to the defect-repair library matches the expected repair approach acquired from the defect model library to determine whether the repair system runs correctly.