Patent ID: 9589650
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A circuit for erasing data, comprising: a high voltage generation unit, adapted for generating an erasing signal; a first control unit, adapted for modifying the erasing signal to a first conduction control signal with a decreased voltage ascending speed; a second control unit, adapted for sending a second conduction control signal based on the first conduction control signal, when the first conduction control signal resides in a first signal period, voltage of the second conduction control signal is identical to that of the erasing signal; and when the first conduction control signal resides in a second signal period, the voltage of the second induction control signal drops, where voltage of the first conduction control signal is less in the first signal period than in the second signal period; a lift unit, adapted for lifting an output voltage at an output end of the circuit for erasing data based on the first conduction control signal; a switch unit, adapted for, based on the second conduction control signal, forming an electrical access between the high voltage generation unit and the output end of the circuit for erasing data; and a reference current generation unit, adapted for providing a bias current to the first control unit and the second control unit.