Patent ID: 9646877
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming an interlayer insulating layer; forming an etch stop pattern over the interlayer insulating layer, wherein the etch stop pattern includes first openings each having a first width; forming a bit line mask pattern on the etch stop pattern having the first openings, wherein the bit line mask pattern includes second openings each having a second width equal to or less than the first width; forming contact holes by etching the interlayer insulating layer using the bit line mask pattern and the etch stop pattern as an etch barrier; forming contact plugs by filling lower portions of the contact holes with a first conductive layer; forming bit line trenches by etching the etch stop pattern and upper portions of the interlayer insulating layer using the bit line mask pattern as an etch barrier, wherein the contact plugs are exposed in the bit line trenches; and forming bit lines by filling the bit line trenches with a second conductive layer, wherein the bit lines are coupled to the contact plugs inside the interlayer insulating layer.