Patent ID: 9581638
Date: 2017-02-28
CPC Classifications: G01R,H01L

Claim:
1. A method for testing a chip-on-wafer (CoW) structure comprising: providing a standardized testing structure design for a CoW structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area within a top die in the CoW structure, wherein the top die comprises functional circuits independent from and formed on a same substrate as the testing structure, wherein the testing structure has a same circuit layout as an additional testing structure within an additional top die of an additional CoW structure, and wherein the additional top die comprises additional functional circuits having a different circuit layout than the functional circuits of the top die; and electrically testing a plurality of microbumps between the top die and another die in the CoW structure by applying a universal testing probe card to transmit an electrical signal through the testing structure, wherein a same electrical signal is sent through the additional testing structure as the electrical signal when electrically testing the additional CoW structure.