Patent ID: 9552328
Date: 2017-01-24
CPC Classifications: G06F

Claim:
1. A reconfigurable integrated circuit device, which is configured by configuration data comprising: a plurality of processing elements each of which includes an arithmetic circuit, and which are configured by the configuration data; and an inter-processing element network which connects the plurality of processing elements in a state configured by the configuration data, wherein the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, the processing element includes an input data holding register which holds the input data signal, an arithmetic processing circuit which computes the input data signal, and an output data holding register which holds computing result data of the arithmetic processing circuit, when updating from a first context which includes a circuit configured by a first configuration data to a second context which follows the first context and includes a circuit configured by a second configuration data, a second processing element which is included in the second context and is configured in a hold mode holds, in the input data holding register, as the input data signal, an output data signal held by an output data holding register of a first processing element which is included in the first context, when the configuration of the processing element is updated by configuration data that makes the hold mode valid, the processing element inputs the input data signal held in the input data holding register to the arithmetic processing circuit, and when the configuration of the processing element is updated by configuration data that makes the hold mode invalid, the processing element continuously inputs the input data signal, which is to be input, to the arithmetic processing circuit without using the input data holding register.