Patent ID: 9712164
Date: 2017-07-18
CPC Classifications: G06F,H03K

Claim:
1. A semiconductor device, comprising: a plurality of logic blocks in which a power supply thereto is controlled; and a plurality of power switches each of which controls, for each logic block of the plurality of logic blocks, a supply and an interruption of power with respect to the each logic block, wherein each power switch of the plurality of power switches includes a plurality of transistors arranged in parallel between the each logic block and a power supply line of the power supply, each transistor of the plurality of transistors including a gate electrode connected to a well via a contact electrode, and a body region connected to a connection portion of the well with the contact electrode via a well resistor under an element isolation insulating film, having a delay characteristic which is a time constant based on a resistance value of the well resistor between the connection portion of the well with the contact electrode and the body region, and controlling a threshold voltage by changing an electric potential applied to the body region in accordance with a signal of the gate electrode, wherein the plurality of transistors include a plurality of first transistors having a first delay characteristic and a plurality of second transistors different from the plurality of first transistors having a second delay characteristic different from the first delay characteristic.