Patent ID: 9548236
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method for forming a structure, the method comprising: providing a first substrate having a graded layer disposed thereon, a relaxed layer disposed on the graded layer, the first substrate further having a first strained semiconductor layer having a first strain type and disposed on the relaxed layer, and the first substrate further having a second strained semiconductor layer having a second strain type disposed on the first strained semiconductor layer, wherein the providing the first substrate comprises providing a cleave plane in the relaxed layer; bonding the second strained semiconductor layer directly to an insulator layer disposed on a second substrate; removing the first substrate from the first strained semiconductor layer, wherein removing the first substrate from the first strained semiconductor layer comprises cleaving, the cleaving separates the relaxed layer into two portions at the cleave plane, the first strained semiconductor layer and second strained semiconductor layer remaining bonded to the insulator layer; and planarizing the first strained semiconductor layer where the relaxed layer has been removed, the planarizing the first strained semiconductor layer comprises an anneal performed at a temperature greater than approximately 800° C.