Patent ID: 9612844
Date: 2017-04-04
CPC Classifications: G06F

Claim:
1. A method for executing instructions on a multi-threaded processor having a plurality of hardware threads that have different hardware execution resources, comprising: fetching a respective next instruction for each of a plurality of streams of instructions; pre-decoding each fetched next instruction at a respective one of a plurality of different instruction pre-decoders each associated with a respective hardware thread; detecting, during the pre-decoding, for each fetched next instruction, whether that fetched next instruction requires a resource for execution that is not available in the associated hardware thread, and responsively generating a flag that such fetched next instruction should not be run on said associated hardware thread that does not have the resource required for execution; at an instruction scheduler configured for scheduling instructions on the plurality of hardware threads, preventing each fetched next instruction for which a flag was generated from running on its associated hardware thread; and for each fetched next instruction for which a flag was not generated during pre-decoding, executing that instruction in its associated hardware thread determined to be available to execute that instruction and which has the resource required by that instruction.