Patent ID: 9543006
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A non-volatile memory cell comprising: a latch structure having a storage node and an inverted storage node, configured to store a pair of bits when the non-volatile memory cell is powered by a working voltage, wherein the latch structure is electrically coupled to a reading word line; a first read/write circuit, electrically coupled to a bit line, a first control line and the latch structure; a second read/write circuit, electrically coupled to an inverted bit line, the first control line and the latch structure; a first memristor, directly connected to the first read/write circuit and a second control line; and a second memristor, directly connected to the second read/write circuit and the second control line, wherein the first read/write circuit comprises a fifth transistor and a sixth transistor, and the second read/write circuit comprises a seventh transistor and an eighth transistor; each of the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor has a first terminal, a second terminal and a control terminal; the second terminal of the fifth transistor is coupled to a system ground, and the control terminal of the fifth transistor is coupled to the first control line; the second terminal of the sixth transistor is coupled to the first memristor and the control terminal of the sixth transistor is coupled to the bit line; the first terminal the fifth transistor is connected to the first terminal of the sixth transistor, and is electrically coupled to the latch structure; the second terminal of the seventh transistor is coupled to the system ground and the control terminal of the seventh transistor is coupled to the first control line; the second terminal of the eighth transistor is coupled to the second memristor, and the control terminal of the eighth transistor is coupled to the inverted bit line; and the first terminal of the seventh transistor is connected to the first terminal of the eighth transistor, and is electrically coupled to the latch structure; wherein when the non-volatile memory cell is powered off, the first memristor and the second memristor are configured to store the pair of bits, wherein when a voltage of the reading word line is at the working voltage, the bit line, the first control line and the second control line control the first read/write circuit to write data from the storage node into the first memristor, or read data from the first memristor into the storage node, and the inverted bit line, the first control line and the second control line control the second read/write circuit to write data from the inverted storage node into the second memristor, or read data from the second memristor to the inverted storage node.