Patent ID: 9607685
Date: 2017-03-28
CPC Classifications: G11C,H01L

Claim:
1. A memory array, comprising: a plurality of memory cells arranged in columns and rows, the columns of memory cells are arranged in a first direction, the rows of memory cells are arranged in a second direction different from the first direction, each memory cell of the plurality of memory cells comprises: a plurality of first-type strap cells arranged in a row substantially parallel to at least one of the word line portions of the memory cells, wherein each first-type strap cell comprises a first-type well strap structure, and the first-type well strap structure is configured to electrically connect a first-type well of the first-type strap cell with a first voltage connector electrically coupled with the first voltage line; and a plurality of second-type strap cells arranged in a row substantially parallel to the at least one word line portion or at least one other word line portion, wherein each second-type strap cell comprises a second-type well strap structure, and the second-type well strap structure is configured to electrically connect a second-type well of the second-type strap cell with a second voltage connector electrically coupled with the second voltage line, wherein each column of memory cells of the array of memory cells is bracketed by at least one first-type strap cell of the plurality of first-type strap cells at a first end of the column and at least one second-type strap cell of the plurality of second-type strap cells at a second end of the column opposite the first end of the column.