Patent ID: 9746734
Date: 2017-08-29
CPC Classifications: G02F,H01L

Claim:
1. A pixel structure, comprising a plurality of columns of pixels, a data line being provided between every two adjacent columns of pixels, each pixel comprising a pixel electrode and a thin film transistor comprising a gate, an active layer, a source and a drain, wherein, a gate protective layer is provided between the gates and the active layers, and grooves, each of which is at least partially located between two adjacent columns of pixels, are provided in the gate protective layer; and for opposite ends of the pixel electrodes of the two adjacent columns of pixels and the data line between the two adjacent columns of pixels, one is located in the groove(s), and the other is located on a part of the gate protective layer without the groove; and wherein, the grooves are located at both sides of the data lines, respectively, and the entire opposite ends of the pixel electrodes of the two adjacent columns of pixels are located in the grooves, respectively.