Patent ID: 9582282
Date: 2017-02-28
CPC Classifications: G06F,Y02D

Claim:
1. A data processing apparatus comprising: prefetch circuitry configured to prefetch cache lines comprising one or more instructions from a memory to store the prefetched cache lines in an instruction cache; and a prefetch lookup table configured to store a plurality of prefetch entries, each prefetch entry corresponding to a region of a memory address space and identifying at least one block of one or more cache lines within the region from which an instruction was accessed in the instruction cache by processing circuitry on a previous occasion; wherein: the prefetch circuitry is configured to detect, based on a program counter, whether an instruction to be executed by the processing circuitry is from a new region of the memory address space; and in response to detecting based on said program counter that said instruction to be executed is from said new region of the memory address space, the prefetch circuitry is configured to perform a prefetch lookup operation comprising determining whether the prefetch lookup table stores a target prefetch entry corresponding to the new region, and in response to determining that the prefetch lookup table stores the target prefetch entry, prefetching said at least one block identified by the target prefetch entry.