Patent ID: 9543152
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device, the method comprising: providing a substrate; forming a bottom electrode on the substrate; forming a capacitor dielectric layer on the bottom electrode, the capacitor dielectric layer having a first region and a second region adjoining the first region; forming a top electrode on the capacitor dielectric layer; forming an etching stop layer on the top electrode; forming a first anti-reflective coating layer on the etching stop layer; removing entire portions of the first anti-reflective coating layer, the etching stop layer, and the top electrode over and aligned with the second region of the capacitor dielectric layer, such that respective sidewalls of the remaining portions of the first anti-reflective coating layer, the etching stop layer, and the top electrode together form a stacked sidewall; and depositing a capping layer on the stacked sidewall, the remaining portion of the etching stop layer, and the second region of the capacitor dielectric layer, wherein the capping layer is formed from oxide or nitride.