Patent ID: 9654119
Date: 2017-05-16
CPC Classifications: H03L

Claim:
1. A phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the phase locked loop (PLL) comprising: a divider configured to divide the output clock signal to generate a divided clock signal; a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal; and a digitally controlled oscillator comprising an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined based on a time constant of the LC resonance circuit and the time-pulse conversion signal, wherein a sustainment time of changed capacitance for which capacitance of the LC resonance circuit is maintained in a changed state is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.