Patent ID: 9577180
Date: 2017-02-21
CPC Classifications: H01F,H01L,H03K

Claim:
1. A method for fabricating a logic cell, the method comprising: depositing and patterning a layer of conductive material on a substrate to define a first electrode; depositing a first layer of anti-ferromagnetic material or ferrimagnetic material directly on the electrode; depositing a dielectric material layer over the first layer of anti-ferromagnetic material or ferrimagnetic material; patterning the first layer of anti-ferromagnetic material or ferrimagnetic material and the dielectric material layer to define a magnetic portion and a dielectric portion of the cell; and forming a second electrode portion in contact with the dielectric material layer; wherein the first layer of anti-ferromagnetic material or ferrimagnetic material includes a first sublayer formed of rare earth ions and a second sublayer of formed of transition metal ions directly contacting the first sublayer, wherein the first and second layers are antiferromagnetically coupled so that moments of the first and second sublayers point towards opposite directions and have equal and opposite moments.