Patent ID: 9570361
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: forming at least one gate trench in a semiconductor substrate, the gate trench exposing a semiconductor portion of the substrate; forming a high dielectric-constant (high-k) layer in the at least one gate trench and on the semiconductor portion; forming at least one workfunction layer having an arrangement of first and second workfunction granular portions on an upper surface of the high-k layer to define a workfunction of the semiconductor device, the arrangement of first and second workfunction granular portions defining a granularity of the at least one workfunction layer; and performing a thermal anneal process that controls a concentration of oxygen vacancies in the high-k layer based on the granularity of the at least one work function metal layer so as to reduce a variation in the threshold voltage.