Patent ID: 9679907
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and a memory stack structure extending through the alternating stack and comprising a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, wherein: a lower portion of the memory film comprises a first lateral stack including, from outside to inside, a lower portion of a blocking dielectric layer, a charge trapping layer, and a lower portion of a tunneling dielectric layer; and an upper portion of the memory film comprises a second lateral stack including, from outside to inside, an upper portion of the blocking dielectric layer and an upper portion of the tunneling dielectric layer in physical contact with the upper portion of the blocking dielectric layer, wherein: the three-dimensional memory device comprises a vertical NAND device located over the substrate; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device; the substrate comprises a silicon substrate; the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and the array of monolithic three-dimensional NAND strings comprises: