Patent ID: 9542990
Date: 2017-01-10
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device, comprising a four-terminal oxide heterojunction transistor in 1T configuration in which the oxide heterojunction transistor functions both as a storage element and as a control element and which comprises: an oxygen-contained compound substrate; an oxygen-contained compound film on the oxygen-contained compound substrate, wherein an interfacial layer between the oxygen-contained compound substrate and the oxygen-contained compound film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxygen-contained compound film and electrically connected with the interfacial layer; a front gate on the oxygen-contained compound film; and a back gate on a lower surface of the oxygen-contained compound substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation,and wherein the semiconductor memory device is a memory cell in an array of memory cells, the array comprising a plurality of bit lines arranged orthogonally to a plurality of word lines, wherein each memory cell is directly connected to two of the plurality of word lines and to two of the plurality of bit lines, and each memory cell comprises only the four-terminal oxide heterojunction transistor.