Patent ID: 9666303
Date: 2017-05-30
CPC Classifications: G06F,G11C

Claim:
1. A chip comprising: a region-specific error profile configured to indicate reliability traits of respective regions of the chip according to a given operating parameter value, the region-specific error profile configured to provide reliability traits of a given region as a function of respective different values of the operating parameter value; the region-specific error profile further configured to obtain first indications of respective reliabilities of the regions according to a first target operating parameter value and to obtain second indications of respective reliabilities of the regions according to a second target operating parameter value; and a first set of the regions selected based on the first indications of the respective reliabilities, and a second set of the regions selected based on the second indications of the respective reliabilities; and the first and second sets of selected regions being made available or unavailable based on the selection thereof.