Patent ID: 9640533
Date: 2017-05-02
CPC Classifications: G06F,H01L

Claim:
1. A method, comprising: forming a set of fins of a first transistor, said set of fins comprising a first outer fin, an inner fin, and a second outer fin; performing an oxide deposition process for depositing an oxide material upon said set of fins and within spaces between said fins; performing a first recess process for removing a portion of the oxide material, leaving a portion of the oxide material on inside walls of said first and second outer fins; performing a spacer nitride deposition process for depositing a spacer nitride material upon said set of fins and on outer walls of the first and second outer fins; preforming a spacer nitride removal process, leaving spacer nitride material on a first portion at the outer walls of the first and second outer fins; performing a second recess process for removing said oxide material from the inside walls of said first and second outer fins; and performing an epitaxial layer deposition process upon said set of fins and said outer walls of said first and second outer fins, wherein any lateral over-growth of epitaxial layer on said outer walls of said first and second outer fins is suppressed by said spacer nitride material at the first portion, and wherein lateral overgrowth of the epitaxial layer occurs on a second portion of the outer walls of said first and second outer fins.