Patent ID: 9640535
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: an isolation region laterally defining an active region in a semiconductor substrate; a gate structure positioned above said active region; a sidewall spacer positioned adjacent to sidewalls of said gate structure; an etch stop layer positioned above and covering a portion of said active region; an interlayer dielectric material positioned above said active region and covering said etch stop layer; a confined raised source/drain region positioned on and in contact with an upper surface of said active region, wherein said confined raised source/drain region extends laterally between and contacts a lower sidewall surface portion of said sidewall spacer and at least a portion of a sidewall surface of said etch stop layer; and a conductive contact element extending through said interlayer dielectric material and directly contacting an upper surface of said confined raised source/drain region.