Patent ID: 9685972
Date: 2017-06-20
CPC Classifications: H03K,H03M

Claim:
1. An asynchronous successive approximation register analog-to-digital conversion (ASAR ADC) circuit, comprising: a comparator circuit, an XOR gate circuit, an ASAR logic circuit, a metastable state detection (MD) circuit, a capacitor, and a digital-to-analog converter (DAC) circuit, wherein: the comparator circuit has a first input terminal connected to an analog signal, a first output terminal of the comparator circuit respectively connected to a first input terminal of the ASAR circuit and a first input terminal of the XOR gate circuit, a second output terminal of the comparator circuit respectively connected to a second input terminal of the ASAR gate circuit and a second input terminal of the XOR gate circuit, and an enable signal input terminal connected to a control signal output terminal of the ASAR logic circuit; the XOR gate circuit has an output terminal connected to a third input terminal of the ASAR logic circuit and a first input terminal of the MD circuit; the MD circuit has a second input terminal connected to a control signal output terminal of the ASAR logic circuit, and an output terminal of the MD circuit connected to the first input terminal or the second input terminal of the comparator circuit through the capacitor; and the DAC circuit has an input terminal connected to an output terminal of the ASAR logic circuit, and an output terminal of the DAC circuit connected to the second input terminal of the comparator circuit, wherein: the output terminal of the ASAR logic circuit is connected to a digital signal output terminal of the ASAR DAC circuit.