Patent ID: 9647089
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A thin film transistor substrate comprising: a substrate; a crystalline silicon layer on the substrate, the crystalline silicon layer comprising a source region, a drain region, and a channel between the source and drain regions; a capping layer covering the crystalline silicon layer and comprising a first portion having a first thickness and a second portion having a second thickness that is greater than the first thickness; a gate electrode on the capping layer, a bottom surface of the gate electrode being below an upper surface of the second portion of the capping layer in a direction normal to the substrate; and a source electrode contacting the source region of the crystalline silicon layer and a drain electrode contacting the drain region of the crystalline silicon layer, a distance between the second portion of the capping layer and the channel being greater than a distance between a contact position of the source electrode or the drain electrode on the crystalline silicon layer and the channel in a direction parallel to the substrate.