Patent ID: 9536771
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of integrated chip processing, comprising: forming a source region or a drain region comprising an embedded epitaxial region extending as a positive relief from a location within a semiconductor substrate to a position above the semiconductor substrate; forming a gate structure comprising a gate electrode and a sidewall spacer separated from the embedded epitaxial region by a gap; depositing a flowable dielectric material within the gap between the gate structure and the embedded epitaxial region, wherein the flowable dielectric material is separated from the gate electrode by the sidewall spacer; selectively etching the flowable dielectric material to remove the flowable dielectric material from a portion of a sidewall of the gate structure, so that a first part of the sidewall abuts the flowable dielectric material and a second overlying part of the sidewall does not abut the flowable dielectric material; depositing a pre-metal dielectric (PMD) layer onto the flowable dielectric material using a vapor deposition process, wherein the PMD layer extends from the sidewall spacer to cover an entirety of the source region or the drain region and the flowable dielectric material, and wherein the PMD layer has an upper surface that is substantially co-planar with an upper surface of the gate electrode; forming a first inter-level dielectric (ILD) layer over the PMD layer and the gate electrode; and forming a metal contact within the first ILD layer, wherein the metal contact electrically contacts the gate electrode.