Patent ID: 9721935
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first chip having a first semiconductor layer including a first circuit surface and a first rear surface opposite to the first circuit surface, a first wiring layer provided on the first circuit surface, and a first through electrode extending through the first semiconductor layer and connected to the first wiring layer; a second chip stacked on a first wiring layer side of the first chip and having a second semiconductor layer with a second circuit surface and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface between the second semiconductor layer and the first chip and connected to the first wiring layer of the first chip, and a second through electrode extending through the second semiconductor layer and connected to the second wiring layer; and a third chip that is stacked on a second rear surface side of the second chip, and having a third semiconductor layer with a third circuit surface and a third rear surface positioned opposite to the third circuit surface, a third wiring layer provided on the third circuit surface, and a third through electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second through electrode, wherein the third semiconductor layer is between the third wiring layer and the second chip, and wherein a spacing between the first and second chips is less than a spacing between the second and third chips.