Patent ID: 9691455
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. An integrated circuit, comprising: an input circuit configured to provide an encoded address via multiple address lines; an address decoding circuit configured to directly translate the encoded address provided via the multiple address lines, wherein the address decoding circuit comprises multiple decoding blocks with each block having a first stage coupled to a second stage, wherein the first stage of each block comprises a first number of decoding transistors configured to decode first address bit values from the multiple address lines, and wherein the second stage of each block comprises a second number of decoding transistors configured to decode second address data bit values from the multiple address lines, and wherein the first address bit values are different than the second address bit values; an output circuit configured to provide a decoded address; and a clock circuit configured to provide a clock signal to each block of the multiple decoding blocks, wherein the first stage for each block of the multiple decoding blocks comprises first and second input transistors with the decoding transistors of the first number of decoding transistors interposed therebetween, and wherein the clock circuit provides the clock signal to a gate of each first input transistor and a gate of each second input transistor.