Patent ID: 9734913
Date: 2017-08-15
CPC Classifications: G11C,H01L

Claim:
1. A non-volatile memory device comprising: a memory cell array including a plurality of memory cells; a control circuit; and a counter, wherein each of the plurality of memory cells comprises a channel layer, a charge trap layer disposed over the channel layer, and a control electrode disposed over the charge trap layer, the charge trap layer being shared by the plurality of memory cells in the memory cell array, wherein the charge trap layer comprises: wherein the control circuit is configured to control the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions, wherein the control circuit performs a two-step erasing operation comprising: wherein, before the two-step erasing operation is performed, the control circuit performs a pre-programming operation for charging the program regions and the charge spread blocking regions of the charge trap layer with charges having a same polarity by applying a program voltage to the control electrodes of the plurality of memory cells simultaneously, and wherein the counter counts a number of times that the two-step erasing operation is performed, and the control circuit receives information regarding the number of times that the two-step erasing operation is performed from the counter and, when the two-step erasing operation is repeated a specific number of times, performs the pre-programming operation before the specific number of times the two-step erasing operation is performed.