Patent ID: 9600232
Date: 2017-03-21
CPC Classifications: G06F

Claim:
1. A method of aligning first-in-first-out buffer (‘FIFO’) pointers in a data communications lane of a serial link, the lane comprising a FIFO, wherein the FIFO comprises: a write side configured to operate on a write clock and a write pointer, the write pointer comprising a circular pointer incrementing in dependence upon a rate of the write clock; a read side configured to operate on a read clock and a read pointer, the read pointer comprising a circular pointer incrementing in dependence upon a rate of the read clock, the read clock operating at a higher rate than the write clock; the write side further configured to receive data in parallel form from a source; and the read side configured to provide data serially to a target, wherein the method comprises: resetting, by a write control block coupled to the write side of the FIFO, the write pointers to an initial value; iteratively, until a one or more bits retrieved by the read side from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing, by the write control block, the read pointer from incrementing for a predetermined period of time.