Patent ID: 9666573
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A method of forming integrated circuitry, comprising: forming a first dielectric material over a first substrate; forming in the first dielectric material at least one first conductive pad and at least one conductive line spaced apart from each other; the first dielectric material, the at least one conductive pad and the at least one first conductive line including respective upper surfaces that are substantially coplanar with one another; forming a second dielectric material over a second substrate; forming at least one second conductive pad in the second dielectric material; and bonding the first and second dielectric materials to one another to form a hybrid-bonding structure, wherein the at least one first conductive pad and the at least one second conductive pad are in contact with each other and the at least one conductive line is capped by the second dielectric material and electrically isolated from the at least one first conductive pad and the at least one second conductive pad.