Patent ID: 9570407
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device including a substrate, a semiconductor chip mounted on the substrate having a functional element, a resin that seals a circumference of the semiconductor chip, and a flat plate-like protective cover bonded to an upper surface of the resin, the method comprising: a fixing step in which a plurality of semiconductor chips each corresponding to the semiconductor chip in the semiconductor device are mounted on and fixed to predetermined positions on an upper surface of a single starting substrate that is to form individual pieces each corresponding to the substrate in the semiconductor device; a connection step in which electrodes of the plurality of semiconductor chips and corresponding electrodes of the starting substrate are connected by wires, respectively; a sealing step in which on the upper surface of the starting substrate, the resin with thermosetting is provided by potting among the plurality of semiconductor chips to seal the semiconductor chips with the resin over an entire lateral circumference of each of the semiconductor chip, so that a height of the resin is larger than a highest position of the wires around each semiconductor chip; a semi-curing step to bring the resin into a semi-cured state by heating the resin; a bonding step in which a single starting protective cover that is to form individual pieces each corresponding to the protective cover is bonded to a surface of the resin so as to extend over the plurality of semiconductor chips; a curing step to cure the resin to which the starting protective cover is bonded; and a cutting step in which an assembly of the semiconductor devices formed by bonding the starting protective cover to the starting substrate via the resin is cut to pieces each corresponding to the semiconductor device, wherein in the bonding step, the starting protective cover is bonded to the upper surface of the resin that seals the entire lateral circumference of each semiconductor chip so that a space in which each of the wires is partially exposed is formed between an upper surface of each semiconductor chip and an inner surface of the starting protective cover.