Patent ID: 9570453
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a substrate; one or more adjacent memory cells on the substrate, a memory cell of which includes a gate structure on the substrate, a control gate layer on the gate structure, and a first mask layer on the control gate layer, wherein, in a direction parallel to a surface of the substrate, a size of a first portion of the control gate layer being smaller than a size of the gate structure or the first mask layer; an electrical contact layer on a sidewall of the first portion of the control gate layer and on an exposed surface of the substrate; a barrier layer on the substrate and a sidewall of the memory cell, wherein the barrier layer has an opening therein, the opening exposing at least the electrical contact layer on the surface of the substrate on both sides of the memory cell; and a conductive structure in the opening, such that a distance between the conductive structure and the control gate layer is significantly larger than a distance between the conductive structure and the gate structure, and the barrier layer forms an isolation layer between the conductive structure and the control gate layer.