Patent ID: 9627393
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A NAND flash memory comprising: a plurality of word lines in a NAND memory array area; a plurality of contact pads and lead lines in a word line hookup area, each of the plurality of word lines electrically connected to a corresponding contact pad by a corresponding lead line; wherein the plurality of word lines in the memory array area have a first height and low-profile areas of one or more lead lines in the word line hookup area have a second height that is less than the first height; a plurality of cuts through the one or more lead lines, each of the plurality of cuts extending through a corresponding low-profile area of the one or more lead lines to isolate a contact pad from a word line thereby leaving the word line connected only to its corresponding contact pad; wherein the corresponding low-profile area surrounds an individual cut of the plurality of cuts and the individual cut extends through an individual lead line of the one or more lead lines at least a minimum distance from a perimeter of the corresponding low-profile area; and a plurality of air gaps separating the plurality of word lines and wherein the plurality of air gaps terminate in the word line hookup area and do not intersect the plurality of cuts.