Patent ID: 9748231
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate; a first active region formed in the substrate and that includes a first region that has a first width, a second region that has a second width larger than the first width and extended in a first direction, and a boundary of the first region and the second region that has a step formed by a difference between the first width and the second width; a second active region formed in the substrate and extended in parallel to the second region of the first active region; an element isolation insulating film formed in the substrate and that partitions the first active region and the second active region, respectively; a first gate electrode and a second gate electrode formed on the second region of the first active region; and a third gate electrode and a fourth gate electrode formed on the second active region; wherein each of the first active region and the second active region is a single continuous region, the second region of the first active region includes a depressed part depressed in a second direction that is perpendicular to the first direction in a plan view, the first active region and the second active region are next to each other, the first gate electrode and the third gate electrode are connected to each other, the second gate electrode and the fourth gate electrode are connected to each other, the second region of the first active region includes the depressed part in a region except the boundary, extended in the first direction from the first gate electrode to the second gate electrode, and a width of the depressed part in the second region of the first active region is narrower than the second width.