Patent ID: 9621192
Date: 2017-04-11
CPC Classifications: H03M,H04L

Claim:
1. A bit interleaving method for interleaving bits of a codeword generated based on a quasi-cyclic low-density parity check coding scheme including a repeat-accumulate quasi-cyclic low-density parity check coding scheme, the bit interleaving method comprising: a bit permutation step of applying a bit permutation process to the codeword made up of N cyclic blocks each consisting of Q bits, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; and a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, wherein N is not a multiple of M, the bit permutation rule defines the reordering of the bits of the codeword, such that the Q bits in each of N′=N−X cyclic blocks of the N cyclic blocks are each allocated to a bit of an identical bit index in Q constellation words and the Q constellation words are each made up of one bit in each of M cyclic blocks, the M cyclic blocks being common to the Q constellation words, where X is a remainder of N divided by M, the codeword is generated by performing parity interleaving on a parity section, and X cyclic blocks include a cyclic block in the parity section of the codeword.