Patent ID: 9721965
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A non-volatile memory device, comprising: a substrate having a well; a first vertical channel structure and a second vertical channel structure, wherein the first and second vertical channel structures are in contact with the well and protrude from the well; a horizontal channel structure connecting the first and second vertical channel structures; a first gate electrode formed over the substrate and under the horizontal channel structure and surrounding side surfaces of the first and second vertical channel structures; a second gate electrode stacked over the first gate electrode and surrounding the horizontal channel structure; a plurality of third gate electrodes stacked over the second gate electrode and surrounding the side surfaces of the first and second vertical channel structures; and a plurality of interlayer insulating layers formed between the first, second and third gate electrodes, wherein the first and second vertical channel structures vertically pass through the first, second and third gate electrodes to be directly in contact with the well, and wherein the first vertical channel structure is connected to a first end surface of the horizontal channel structure, and the second vertical channel structure is connected to a second end surface of the horizontal channel structure opposite to the first end surface of the horizontal channel structure.