Patent ID: 9608130
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate including a diffusion region; a plurality of capacitor regions disposed within the diffusion region of the substrate, each capacitor region including a plurality of trenches disposed therein; and a metal-insulator-metal (MIM) capacitor formed within the plurality of trenches of a first capacitor region, the metal-insulator-metal (MIM) capacitor defining a seam to facilitate stress management, wherein the plurality of trenches disposed within the first capacitor region of the plurality of capacitor regions are at least substantially perpendicular to the plurality of trenches disposed within a second capacitor region of the plurality of capacitor regions, the second capacitor region adjacent to the first capacitor region, respective trenches of the plurality of trenches having an aspect ratio ranging from about one hundred and twenty-five to one (125:1) to about one hundred and fifty to one (150:1), the metal-insulator-metal capacitor comprising a capacitive density ranging from three hundred femtoFarads per square micrometer (300 fF/um