Patent ID: 9721846
Date: 2017-08-01
CPC Classifications: B82Y,H01L

Claim:
1. A method for manufacturing a nanowire semiconductor device, the method comprising: providing a substrate, said substrate including an active NMOS region and an active PMOS region; providing an isolation structure formed on the substrate; performing a first selective epitaxial growth process to form a first polygon nanowire structure in the active NMOS region, wherein the first selective epitaxial growth process to form the first polygonal structure nanowire in the active region of NMOS includes: forming a first patterned hard mask layer on the substrate having the isolation structure, said first hard mask layer having a first through hole, the bottom of said first through hole exposing a portion of the substrate of active region of NMOS; the first selective epitaxial growth process is performed to form a first polygonal structure nanowire on the exposed substrate at the bottom of the first through hole; removing the first hard mask layer; performing a second selective epitaxial growth process to form a second polygon nanowire structure in the active PMOS region; removing a portion of the substrate through an etching process, such that the first nanowire is suspended above the substrate; oxidizing and annealing the said first nanowire; and on the substrate, sequentially forming a gate dielectric layer and a gate electrode layer on the first nanowire and the second nanowire.