Patent ID: 9614151
Date: 2017-04-04
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a first plane comprising a first phase change memory cell, which comprises a first electrode line and a second electrode line, with a first phase change memory element and a first diode connected in series between said first and second electrode lines; a second plane in a stacked configuration with said first plane and comprising a second phase change memory cell, which comprises the second electrode line and a third electrode line, with a second phase change memory element and second diode connected in series between the second and third electrode lines, wherein at least the second and third electrode lines are selectively connectable to a driver circuit and a sense circuit based at least in part on an initiated write operation associated with the memory device; and a third plane in a stacked configuration with said first and second planes and comprising a third phase change memory cell, which comprises the third electrode line and a fourth electrode line, with a third phase change memory element and third diode connected in series between the third electrode line and fourth electrode line.