Patent ID: 9620619
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method comprising: forming a gate structure, comprising: forming a space within the gate structure by removing the material and the masking material, defined by the spacers; forming device spacers on the side of the spacers and the patterned gate dielectric material and the work function metal, extending to the substrate; forming source and drain regions on the substrate and sides of the device spacers; blanket depositing a sealing material in the space, over the gate structure and on the source and drain regions comprising semiconductor material; removing the sealing material from over the gate structure and on the semiconductor material, while leaving the sealing material within the space; forming an interlevel dielectric material over the gate structure subsequent to the removing of the sealing material; patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure; and forming a contact in the opening formed in the interlevel dielectric material, wherein: the masking material, the spacers, the device spacers and the sealing material are formed of a first material type, the material is a second material type, different than the first material type, the interlevel dielectric material is different than the first material type, and the patterning the interlevel dielectric material is a selective etch such that the spacers, the device spacers and the sealing material of the first material type remain intact during the patterning of the interlevel dielectric material.