Patent ID: 9736085
Date: 2017-08-15
CPC Classifications: H04L

Claim:
1. A switch, comprising: one or more ports; a memory; packet processing circuitry configured to identify a priority value in a first inner layer-2 header of a packet encapsulated with a first outer encapsulation header, wherein the priority value indicates a class of service associated with priority-based flow control for the packet, and wherein the first outer encapsulation header comprises a first switch identifier identifying the switch and a second switch identifier identifying a second switch in a routed network; and flow control circuitry configured to, in response to detecting a potential buffer overflow for the class of service, generate a pause frame comprising a second inner layer-2 header for the class of service associated with the priority-based flow control, wherein the second inner layer-2 header is encapsulated with a second outer encapsulation header comprising the second switch identifier as a destination identifier, and wherein the first and second outer encapsulation headers are based on a same encapsulation protocol.