Patent ID: 9647002
Date: 2017-05-09
CPC Classifications: G02F,G09G,H01L

Claim:
1. An array substrate, comprising: a substrate; a first gate scanning line formed on the substrate; a first gate insulating layer formed on the first gate scanning line; an active layer formed on the first gate insulating layer; a data scanning line formed on the active layer and perpendicular to the first gate scanning line; a pixel electrode formed in a pixel unit defined by the first gate scanning line and the data scanning line and over the data scanning line; and Z a second gate scanning line formed over or below the first gate scanning line, wherein the second gate scanning line is arranged to be insulated from the first gate scanning line, the active layer, the data scanning line, and the pixel electrode, respectively; wherein the first gate scanning line comprises a first conductive strip and a plurality of first projections projecting from a side of the first conductive strip, the first projections being arranged at an equal interval therebetween along an extending direction of the first conductive strip on a side of the conductive strip and the plurality of first projections and the first conductive strip being formed integrally; the second gate scanning line comprises a second conductive strip and a plurality of second projections projecting from a side of the second conductive strip, the plurality of second projections and the second conductive strip being formed integrally to allow the plurality of first projections and the plurality of second projections being located in different levels that are not coplanar, the second projections being arranged at an equal interval therebetween along an extending direction of the second conductive strip on a side of the second conductive strip that is opposite to the first projections, and the second projections being arranged alternately with the first projections; and wherein the second gate scanning line being is at least partially overlapped with the first gate scanning line in a stacking direction of the array substrate.