Patent ID: 9589096
Date: 2017-03-07
CPC Classifications: G06F

Claim:
1. A method implemented by an electronic design and verification tool to generate a timing report for a circuit, the circuit having at least one signal path, the at least one signal path having at least one stage, the method implemented by one or more processors and comprising: performing path-based analysis (PBA) for each stage of the at least one signal path based on a netlist modeling the circuit; performing SPICE simulation for each stage of the at least one signal path based on a waveform at a start point of the at least one signal path, wherein the SPICE simulation is performed at least partly in parallel with the PBA for each stage; collecting at least one output from the PBA and at least one output from the SPICE simulation; correlating, stage-by-stage, the at least one PBA output with the at least one SPICE output; and generating the timing report on a stage-by-stage basis for the circuit based on the correlated output values.