Patent ID: 9563504
Date: 2017-02-07
CPC Classifications: G06F,G11C,H01L

Claim:
1. A system, comprising: a memory array, the memory array includes a set of memory cells connected to a word line; a control circuit configured to identify one or more word lines within the memory array in response to a fail bit count associated with a first set of data stored within the set of memory cells connected to the word line satisfies an error threshold, the control circuit configured to acquire a second set of data to be programmed into memory cells connected to the one or more word lines, the one or more word lines include the word line and a second word line that has not been programmed since a last erase operation on the second word line; an erase circuit configured to erase the memory cells connected to the one or more word lines such that other memory cells connected to one or more other word lines within the memory array are not erased; and a write circuit configured to write the second set of data into the memory cells connected to the one or more word lines.