Patent ID: 9632979
Date: 2017-04-25
CPC Classifications: G06F,G06T

Claim:
1. A method comprising: providing a plurality of data elements to a graphics processor unit (GPU) for input to a prefix sum operation; storing the plurality of data elements in specified data element positions of a first register of the GPU; performing a series of single instruction multiple data (SIMD) operations using the plurality of data elements, the SIMD operations performed using regioning techniques to generate the prefix sum, the SIMD operations including a first plurality of simultaneous addition operations to add specified data elements to generate intermediate results and further including a second plurality of simultaneous addition operations to add the intermediate results to other intermediate results to generate the prefix sum; wherein the intermediate results are to be stored in data element positions within the first register; wherein at least each intermediate result is to be stored in a data element position previously occupied by one of the data elements used to generate the intermediate result; wherein the simultaneous addition operations comprise SIMD8 copy with regioning and SIMD4 copy with regioning operations; and wherein the SIMD4 copy with regioning and SIMD8 copy with regioning operations comprise one or more instructions which specify one or more stride values to identify data element positions to be used for the operations.