Patent ID: 9560003
Date: 2017-01-31
CPC Classifications: H04L

Claim:
1. An apparatus comprising: a processor; a memory in communication with the processor, the memory holding executable instructions that, when executed by the processor, cause the processor to: generate valid addressees to electronic messages, in response to input by a user of an input device; in response to transmissions of outgoing electronic messages having valid addressees, record the valid addressees and associated chronological message data; determine a numerical risk that at least one of first valid addressees of a first outgoing electronic message containing at least two addressees authored by the user is unintended, based at least in part on (i) whether or not a keyword in the first outgoing electronic message is designated as sensitive or is inconsistent with a category assigned to the at least one of the first valid addressees, and (ii) on first associated chronological message data; if the numerical risk exceeds a predetermined threshold, then for one or more combinations of the at least two addressees, query a database to determine a time period T representing the amount of time between when a past message was last sent from the user to the one or more combinations of the at least two addressees and the present; determine whether T exceeds a predetermined amount of time; and in response to determining that T exceeds the predetermined amount of time, delay transmission of the first outgoing electronic message to permit review of the at least two addressees by the user.