Patent ID: 9705454
Date: 2017-07-11
CPC Classifications: G05F,H03F,H03H

Claim:
1. A circuit comprising: a bias circuit for a biased transistor, the bias circuit including a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to a gate of the biased transistor and configured to provide a bias voltage, wherein the reference transistor has a first transconductance substantially identical to a second transconductance of the biased transistor, wherein the gate of the biased transistor receives an additional input signal, and wherein the master-slave source follower circuit comprises: a master transistor configured to operate as a first source follower and provide a master reference voltage to the reference transistor; and a slave transistor configured to operate as a second source follower and provide the bias voltage according to the master reference voltage.