Patent ID: 9685434
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, the method comprising: forming a first dummy gate in an active area on a first portion of a semiconductor device, wherein the first dummy gate includes undoped amorphous silicon; forming a second dummy gate and a third dummy gate on a second portion of the semiconductor device, wherein the second dummy gate and the third dummy gate include undoped amorphous silicon; depositing a filling material on the semiconductor device, wherein the filling material is doped amorphous silicon; performing a chemical-mechanical polishing process (CMP) on the filling material; removing a hard mask, a dummy gate oxide, and undoped amorphous silicon from each of the first dummy gate, the second dummy gate, and the third dummy gate; depositing a high-K dielectric on the semiconductor device; forming a first replacement gate, a second replacement gate, and a third replacement gate, wherein the first, the second, and the third replacement gate each include a work function metal, a fill metal, and a hard mask cap; and masking a portion of the filling material between the second replacement gate and the third replacement gate, wherein a mask covers the portion of the filling material for a resistor.