Patent ID: 9684744
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A method for design verification, comprising: receiving a definition of a design of an integrated circuit device and at least one assertion of a property that is to be verified over the design; compiling the definition into a graph of processing elements, including first processing elements that simulate operation of the device and at least one second processing element representing the at least one assertion, the at least one second processing element comprising a hierarchical arrangement of at least one operator node and one or more leaf nodes corresponding to inputs of the at least one assertion; executing, on a processor, a simulation of the design by triggering the processing elements in the graph in multiple, consecutive clock cycles; and evaluating the property by performing on the processor, during execution of the simulation: initiating, by the at least one operator node in each clock cycle in a sequence of the clock cycles, one or more threads for execution by at least one of the leaf nodes; executing the threads in each clock cycle, by the at least one of the leaf nodes, in order to evaluate a matching condition over the inputs; reporting in each clock cycle, from the at least one of the leaf nodes to the operator node, results of executing the threads in the clock cycle; and based on the results reported by the at least one of the leaf nodes, generating an output from the at least one operator node in each clock cycle, indicating whether at least one assertion was satisfied.