Patent ID: 9571071
Date: 2017-02-14
CPC Classifications: H03K,H03L,H04B

Claim:
1. A frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module configured to delay an input reference signal to generate a delayed reference signal; a duty cycle module configured to generate the oscillator enable signal based on a period of the input reference signal and the delay of the delayed reference signal such that a ratio between the output frequency and a frequency of the input reference signal is a non-integer; wherein the delay module comprises: a time delay oscillator driven by an oscillator control voltage and configured to delay the delay module input reference signal by an amount based on a number of stages of the time delay oscillator: and wherein the delay module further comprises; a multiplexer with a selectable channel input; and a copy time delay oscillator configured to be controlled by said oscillator control voltage and operable to delay the input reference signal to generate the delayed reference signal.