Patent ID: 9667261
Date: 2017-05-30
CPC Classifications: H03L,H04L

Claim:
1. A clock data recovery circuit, comprising: a phase comparator that compares a phase of a recovered clock with a phase of received data to generate an up/down signal; a restoration signal generation unit that enables a restoration signal when the up/down signal indicates up for a time greater than or equal to a first specific time and changes to indicate down afterwards, or when the up/down signal indicates down for the time greater than or equal to the first specific time and changes to indicate up afterwards; a processing circuit including one or more stages for sequentially processing the up/down signal, wherein a last one of the one or more stages holds a process result thereof for a second specific time when the restoration signal is enabled; and a phase interpolator that generates the recovered clock in response to the process result of the last stage, wherein the processing circuit comprises: a first stage including: a second stage that accumulates the added value and outputs the accumulated value as a result value; and a third stage that generates a control code for controlling the phase interpolator so that the phase interpolator generates the recovered clock having a phase corresponding to the result value of the second stage.