Patent ID: 9640612
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first conductivity type semiconductor substrate having trenches formed therein and a first principal surface; a plurality of second conductivity type base regions formed on the first principal surface; and a plurality of second conductivity type semiconductor regions, each of respective top edges of the second conductivity type semiconductor regions contacting one of the second conductivity type base regions, the second conductivity type semiconductor regions extending in extension directions that are parallel to the first principal surface, the second conductivity type semiconductor regions further extending in a direction vertical to the first principal surface, the second conductivity type semiconductor regions respectively being embedded in a plurality of the trenches formed in the first conductivity type semiconductor substrate so that the second conductivity type semiconductor regions are extended in a row direction in parallel with the first principal surface of the semiconductor substrate or a column direction in parallel with the first principal surface of the semiconductor substrate, the second conductivity type semiconductor regions being spaced apart from each other by gaps, each of the second conductivity type semiconductor regions being in a respective one of the plurality of trenches, wherein the extension directions parallel to the first principal surface in which the second conductivity type semiconductor regions extend, include at least two directions including a first direction and a second direction different from the first direction, each second conductivity type semiconductor region of a first group of the plurality of the second conductivity type semiconductor regions is formed so as to extend in the first direction, and each second conductivity type semiconductor region of a second group of remaining ones of the second conductivity type semiconductor regions is formed so as to extend in the second direction, each respective trench of the trenches that the first group is within, has a first crystal plane and a second crystal plane, the first crystal plane being a crystal plane of a sidewall at a long side of the respective trench, the second crystal plane being a crystal plane of a sidewall at a shorter side of the respective trench, and each respective trench of the trenches that the second group is within, has a third crystal plane and a fourth crystal plane, the third crystal plane being a crystal plane of a sidewall at a long side of the respective trench, the fourth crystal plane being a crystal plane of a sidewall at a shorter side of the respective trench, each of the trenches that the first group is within, is arranged so as to be orthogonal to each of the trenches that the second group is within, each of the first crystal planes forms a same plane with a corresponding one of the fourth crystal planes and has a same crystal structure as the corresponding one of the fourth crystal planes, and each of the second crystal planes forms a same plane with a corresponding one of the third crystal planes and has a same crystal structure as the corresponding one of the third crystal planes, and the plurality of the second conductivity type semiconductor regions and parts of the first conductivity type semiconductor substrate between the second conductivity type semiconductor regions are depleted by a depletion layer extending in a direction parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the first conductivity type semiconductor substrate and the plurality of the second conductivity type semiconductor regions.