Patent ID: 9601471
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A vertical stack system in package (SiP) comprising: a pair of first level die encapsulated in a first level molding compound; a first redistribution layer (RDL) on the encapsulated pair of first level die; a second level die stack including a pair of back-to-back stacked die on the first RDL and encapsulated in a second level molding compound; a second RDL on the encapsulated second level die stack; a third level logic die on the second RDL and encapsulated in a third level molding compound, wherein the third level logic die is back facing toward the second RDL; and a third RDL on the encapsulated third level logic die; wherein each of the first level die is a first type of memory die and each of the back-to-back stacked die are a second type of memory die that is different than the first type of memory die, and each of the back-to-back stacked die have larger x-y dimensions than each of the first level die.