Patent ID: 9690544
Date: 2017-06-27
CPC Classifications: G06F,H05K

Claim:
1. A computer system for executing a machine instruction in a central processing unit, the machine instruction being defined for computer execution according to a computer architecture, the system comprising: an instruction fetching unit for fetching instructions to be executed; a floating point arithmetic unit for executing floating point operations of fetched floating point instructions; and an operand storage in communication with said floating point arithmetic unit; wherein the computer system performs a method comprising: a) executing, by a computer processor, a decimal floating point instruction configured to perform a decimal floating point operation, the decimal floating point instruction configured to utilize a round-for-reround mode, the executing step comprising: b) subsequent to execution of the decimal floating point instruction, executing, by the computer processor, a decimal reround instruction, the decimal reround instruction configured to round a decimal floating point number to any of a plurality of rounding precisions, executing the decimal reround instruction execution comprising: