Patent ID: 9691843
Date: 2017-06-27
CPC Classifications: B82Y,H01L

Claim:
1. A semiconductor structure, comprising: a first semiconductor device comprising a first nanowire disposed above a crystalline substrate, the first nanowire comprising a first semiconductor material; a second semiconductor device comprising a second nanowire disposed above the crystalline substrate, the second nanowire comprising a second semiconductor material different from the first semiconductor material, and the second nanowire isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire and the crystalline substrate; and a third semiconductor device comprising a third nanowire disposed above the crystalline substrate, the third nanowire comprising a third semiconductor material different from the first and second semiconductor materials, the third nanowire isolated from the crystalline substrate by a second isolation pedestal disposed between the third nanowire and the crystalline substrate, wherein a bottom surface of the first nanowire is co-planar with a bottom surface of the second nanowire and is co-planar with a bottom surface of the third nanowire, and wherein the first nanowire, the second nanowire and the third nanowire are all parallel with one another.