Patent ID: 9543315
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a memory cell formed in a first region of a semiconductor substrate; and a capacitive element formed in a second region of the semiconductor substrate, wherein the memory cell includes: a first conductor piece disposed on a main surface of the semiconductor substrate via a first insulator piece; a second conductor piece disposed on the first conductor piece via a second insulator piece; a third conductor piece disposed on the main surface of the semiconductor substrate via a third insulator piece, and disposed on side surfaces of the first conductor piece and the second conductor piece via a fourth insulator piece; and a pair of semiconductor regions formed in the main surface of the semiconductor substrate such that the first conductor piece and the third conductor piece are interposed therebetween, wherein the capacitive element includes: a fourth conductor piece formed on the main surface of the semiconductor substrate and having an upper surface; a plurality of mesa-like fifth conductor pieces disposed on the fourth conductor piece via a fifth insulator piece, and each having an upper surface and side surfaces on the fourth conductor piece; a sixth insulator piece disposed on the upper surface of the fourth conductor piece and on the side surfaces of each of the fifth conductor pieces; and a sixth conductor piece disposed between the neighboring fifth conductor pieces via the sixth insulator piece, wherein the first conductor piece and the fourth conductor piece are made of a first conductor film, wherein the second conductor piece and the fifth conductor pieces are made of a second conductor film, and wherein the third conductor piece and the sixth conductor piece are made of a third conductor film.