Patent ID: 9711542
Date: 2017-07-18
CPC Classifications: G02F,H01L

Claim:
1. A method for fabricating a display panel, comprising: forming a first patterned conductive layer on a first substrate, wherein the first patterned conductive layer comprises a first gate electrode; forming a gate insulation layer on the first substrate and the first patterned conductive layer; forming a semiconductor channel layer on the gate insulation layer, wherein the semiconductor channel layer overlaps the first gate electrode in a vertical projective direction; forming a first passivation layer on the gate insulation layer and the semiconductor channel layer; forming a patterned photoresist layer on the first passivation layer, wherein the patterned photoresist layer comprises a first photoresist pattern, a second photoresist pattern, and a plurality of openings, and a thickness of the first photoresist pattern is higher than a thickness of the second photoresist pattern; removing the first passivation layer exposed by the openings to expose a first contact section and a second contact section of the semiconductor channel layer; performing an ashing process to remove the second photoresist pattern and partially exposing an upper surface of the first passivation layer; forming a conductive layer on the patterned photoresist layer, wherein the conductive layer contacts the first contact section and the second contact section, and the conductive layer contacts the upper surface of the first passivation layer exposed by the patterned photoresist layer; performing a lift-off process to remove the patterned photoresist layer and the conductive layer on the patterned photoresist layer to form a second patterned conductive layer including a source electrode contacting the first contact section, a drain electrode contacting the second contact section, and a data line disposed on the upper surface of the first passivation layer and connected to the source electrode; forming a second passivation layer on the second patterned conductive layer; and forming a pixel electrode on the second passivation layer, wherein the pixel electrode is electrically connected to the drain electrode.