Patent ID: 9563566
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. An integrated nonvolatile memory control subsystem, comprising: a nonvolatile buffer cache configured to maintain one or more cache blocks; a nonvolatile journal area configured to maintain one or more journal blocks; nonvolatile storage configured to maintain one or more data blocks; and an integrated memory control unit for performing a read operation, a write operation, a commit operation and a checkpoint operation on the cache blocks of the nonvolatile buffer cache and the journal blocks of the nonvolatile journal area, wherein the integrated memory control unit sets each of data blocks of the nonvolatile storage as one among valid state, erasable state and invalid state, depending on being cached or not, being journaled or not, and being a clean cache or not, considers data stored in a data block of the nonvolatile storage to be authentic original if the data block is of valid state or erasable state, and considers data stored in any one of cache block and journal block to be authentic original if a corresponding data block of the nonvolatile storage is of invalid state, so as to maintain an authentic original up-to-date consistent data within any one of the nonvolatile buffer cache, the nonvolatile journal area and the nonvolatile storage.