Patent ID: 9721911
Date: 2017-08-01
CPC Classifications: G06F,H01L

Claim:
1. A chip package, comprising: a chip having a conductive pad, a first surface, and a second surface opposite to the first surface, wherein the conductive pad is located on the first surface, and the second surface has a first through hole to expose the conductive pad; a laser stopper located on the conductive pad that is in the first through hole, and having a concave surface; an isolation layer located on the second surface and in the first through hole, and having a third surface opposite to the second surface, and having a second through hole to expose the concave surface of the laser stopper; a redistribution layer disposed along the third surface of the isolation layer, a sidewall of the second through hole, and the concave surface of the laser stopper that is in the second through hole, such that at least one portion of the redistribution layer extends into the laser stopper; an insulating layer located on the third surface and the redistribution layer, and having an opening to expose the redistribution layer; and a conductive structure located on the redistribution layer that is in the opening of the insulating layer, such that the conductive structure is electrically connected to the conductive pad.