Patent ID: 9607682
Date: 2017-03-28
CPC Classifications: G06F,G11C

Claim:
1. An integrated circuit, comprising: a plurality of decoder modules, each decoder module for selecting a region of address space among multiple regions within the integrated circuit, wherein each decoder module includes: shifting hardware having a first shifter input configured to receive a constant value and a second shifter input configured to receive a number of bits that the constant value is to be shifted, wherein the number of bits corresponds to a window size of the region of address space, the shifting hardware configured to produce a mask output; first hardware logic configured to receive a base address of the region of address space on a first hardware-logic input and to receive a transaction address on a second hardware-logic input and to logically combine the base address and the transaction address to produce an output; and second hardware logic configured to combine the output of the first hardware logic and the mask output to produce an output indicative of whether the transaction address is within the region of the address space.