Patent ID: 9627415
Date: 2017-04-18
CPC Classifications: G09G,H01L

Claim:
1. A display device, comprising: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver; and wherein the clock signal wiring is positioned at a first side of the gate driver, wherein the voltage wiring is disposed on a second side facing the first side of the gate driver, wherein the plurality of stages have spaces between each adjacent stages, wherein the clock signal wiring has a main clock signal line extending in a first direction and a sub clock signal line extending in a second direction substantially perpendicular to the first direction, wherein the voltage wiring has a main voltage line extending in a first direction and a sub voltage line extending in a second direction, and wherein the sub clock signal line is disposed on a first space among the spaces and the sub voltage line is disposed on a second space different from the first space.