Patent ID: 9668350
Date: 2017-05-30
CPC Classifications: H01L,H05K

Claim:
1. A semiconductor module, comprising: a printed circuit board comprising a structured first metalization layer, which has a first section and a second section, and comprising a structured second metalization layer, which has a first section, a second section and a third section; at least one first semiconductor chip which is embedded in the printed circuit board, each of the at least one first semiconductor chips having a first load connection and a second load connection; and at least one second semiconductor chip, which is embedded in the printed circuit board, each of the at least one second semiconductor chips having a first load connection and a second load connection; wherein: the first section of the second metalization layer has a comb-shaped structure comprising a plurality of first protrusions; the second section of the first metalization layer has a comb-shaped structure comprising a plurality of second protrusions; the first section of the second metalization layer and the second section of the first metalization layer are electrically conductively connected to one another by virtue of the fact that the printed circuit board has a number of first plated-through holes, each of which is permanently electrically conductively connected both at one of the first protrusions to the first section of the second metalization layer and at one of the second protrusions to the second section of the first metalization layer; each of the first semiconductor chips and each of the second semiconductor chips is arranged between the first metalization layer and the second metalization layer; wherein the first section of the first metalization layer is configured as a first power supply terminal that is conductively connected to the first load connection of each of the first semiconductor chips, wherein the second section of the second metalization layer is configured as a second power supply terminal that is conductively connected to the first load connection of each of the second semiconductor chips; and wherein the second load connection of each of the first semiconductor chips is electrically connected to the first load connection of each of the second semiconductor chips by the first section of the second metalization layer, the second section of the first metalization layer and the first plated-through holes.