Patent ID: 9698258
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a deep well region located on a semiconductor substrate; a second conductivity type drift region and a first conductivity type body region in contact with each other and located on the deep well region; a second conductivity type drain region located on the drift region; a second conductivity type source region located on the body region; a gate insulating layer comprising a gate electrode located on the gate insulating layer, wherein the drift region extends from the drain region towards a direction of the source region and towards a part of the region of the first gate insulating layer, wherein the second gate insulating layer comprises a first edge portion, a second edge portion and a planar bottom surface extending from the first edge portion to the second edge portion, and wherein a thickness of the second gate insulating layer decreases in a concave curve shape to each of the first edge portion and the second edge portion and a top surface of the gate insulating layer extends continuously from the curve shape into a top surface of the first gate insulating layer.