Patent ID: 9660621
Date: 2017-05-23
CPC Classifications: G01R,H03C,H03F,H03K

Claim:
1. An active analog signal conditioning circuit comprising: an input signal node to receive an input signal; an output signal node to output an output signal; a reference signal node to output a reference signal; an error correction signal node to output an error correction signal; a forward module configured to condition and sum the input signal and the error correction signal to present the output signal at the output signal node such that the input signal is applied to a first forward sensitivity between the input signal node and the output signal node, and the error correction signal is applied to a second forward sensitivity between the error correction signal node and the output signal node; a reference module configured to condition and sum the output signal and the error correction signal to present the reference signal at the reference signal node such that the reference signal is inverted in sign to the output signal, the output signal is applied to a first reference sensitivity between the output signal node and the reference signal node, and the error correction signal is applied to a second reference sensitivity between the error correction signal node and the reference signal node; and a correcting comparison module configured to condition and sum the output signal and the reference signal to present the error correction signal at the error correction signal node such that the output signal is applied to a first comparison sensitivity between the output signal node and the error correction signal node, and the reference signal is applied to a second comparison sensitivity between the reference signal node and the error correction signal node; wherein the second forward sensitivity and the first and second reference sensitivities are configured such that error correction signal components of the reference signal from the respective first and second reference sensitivities are equal in magnitude and inverted in sign; and wherein the forward module and the reference module are configured to each include at least one passive element formed on a same first substrate.