Patent ID: 9634008
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: an element isolation insulating film having a first depth and partitioning an element arrangement area on one main face side of a semiconductor substrate; a gate electrode film disposed above the semiconductor substrate within the element arrangement area, through a gate insulating film, and extending in a first direction; source/drain regions containing a first impurity of a predetermined conductivity type diffused therein, the source/drain regions being disposed near a surface of the semiconductor substrate on both sides of the gate electrode film in a second direction perpendicular to the first direction; a channel region containing a second impurity of a predetermined conductivity type diffused therein, the channel region being disposed near a surface of the semiconductor substrate below the gate electrode film; and an air gap disposed at a region of the element isolation insulating film contacting the channel region.