Patent ID: 9640646
Date: 2017-05-02
CPC Classifications: B82Y,H01L

Claim:
1. A semiconductor device, comprising: a group III-V material channel region disposed above a substrate; a gate stack disposed on the group III-V material channel region, the gate stack comprising a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode, wherein the graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode, wherein the graded high-k gate dielectric layer comprises MAlOx having a greater concentration of aluminum proximate the III-V material channel region and a lesser concentration of aluminum proximate the gate electrode, where M is selected from the group consisting of Ta, Zr, Hf, Gd, and Ti; and source/drain regions disposed on either side of the gate stack.