Patent ID: 9721924
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A stack package comprising: a substrate including a substrate body layer and first circuit patterns and second circuit patterns, the substrate body layer has a first surface and a second surface opposite to the first surface, and the first circuit patterns are disposed on the second surface of the substrate body layer and the second circuit patterns are disposed on the first surface of the substrate body layer; a first semiconductor chip disposed over the first surface of the substrate body layer and including a first bump, the first bump penetrating the substrate body layer and a dielectric layer to be electrically coupled to the first circuit patterns; and a second semiconductor chip disposed over the first surface of the substrate body layer to be stacked on a surface of the first semiconductor chip and including a second bump, the second bump thoroughly bypasses the first semiconductor chip, penetrating the dielectric layer in such a way that the sides of the second bump are in contact with the dielectric layer and a protection layer, to be electrically coupled to the second circuit patterns, wherein the first and second bumps have the same length.