Patent ID: 9652027
Date: 2017-05-16
CPC Classifications: G06F,Y02D

Claim:
1. In a computing system comprising a plurality of processing units that correspond to a particular processing unit model, a method of scheduling threads on the plurality of processing units, the method comprising: obtaining a first record that includes three or more performance states associated with the plurality of processing units for the particular processing unit model, wherein each performance state comprises a performance level and a power requirement for one or more processing units of the particular processing unit model; obtaining a second record that includes a mapping of three or more idle states associated with the plurality of processing units, wherein each idle state comprises an exit latency for exiting from the idle state and a power requirement at the idle state for the one or more processing unit of the particular processing unit model; correlating the information from the first record with the information from the second record to identify both a performance state and an idle state for at least one processing unit of the plurality of processing units for the particular processing unit model; and scheduling a thread from a thread scheduler for execution on at least one of the plurality of processing units based on at least both the performance state information from the first record and the idle state information from the second record.