Patent ID: 9620472
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method, comprising: applying solder paste to at least one electrically conductive portion of a package; applying a high-voltage depletion-mode transistor onto the solder paste; applying a low-voltage enhancement-mode transistor onto the solder paste; applying solder paste onto the high-voltage depletion-mode transistor; applying solder paste onto the low-voltage enhancement-mode transistor; applying an electrically conductive member onto the solder paste on the high-voltage depletion-mode transistor and onto the solder paste on the low-voltage enhancement-mode transistor to form an assembly; and heat treating the assembly to produce an electrical connection between the high-voltage depletion-mode transistor and the low-voltage enhancement-mode transistor via the electrically conductive member.