Patent ID: 9627305
Date: 2017-04-18
CPC Classifications: G06F,H01L,H05K

Claim:
1. A semiconductor package, comprising: a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces; a semiconductor die attached to the first main surface of the support substrate; an electrically conductive lead separate spaced apart from the support substrate; an encapsulation material at least partly covering the support substrate, the semiconductor die and the electrically conductive lead, the encapsulation material comprising a bottom side that is coplanar with the second main surface of the support substrate and a top side that is vertically spaced apart from the bottom side; a first protrusion extending outward from the support substrate, forming an interlocked connection with the encapsulation material, and terminating in the encapsulation material, wherein the first protrusion comprises a narrower portion and a wider portion, the narrower portion being arranged closer to the support substrate than the wider portion; and a second protrusion extending outward from the electrically conductive lead and being vertically offset from the bottom and top sides of the encapsulation material, the second protrusion forming an interlocked connection with the encapsulation material, wherein the electrically conductive lead has a first part covered by the encapsulation material and a second part uncovered by the encapsulation material, wherein the second protrusion extends from the first part of the electrically conductive lead, wherein the first protrusion comprises a completely curved perimeter.