Patent ID: 9667219
Date: 2017-05-30
CPC Classifications: G01R,H02M,H03H,H03K

Claim:
1. A phase noise measurement (PNM) circuit, comprising: a delay circuit, wherein an input of the delay circuit receives a first input signal, and wherein an output of the delay circuit outputs a delayed version of the first input signal; a phase detector (PD), wherein a first input of the PD receives the first input signal, wherein a second input of the PD receives the delayed version of the first input signal, and wherein the PD outputs a first voltage signal that corresponds to a phase difference between the first input signal and the delayed version of the first input signal; circuitry to generate a second voltage signal based on the first voltage signal, wherein the second voltage signal corresponds to a phase noise level in the first input signal; wherein the circuitry to generate the second voltage signal comprises: (1) a first charge pump (CP) to charge or discharge a first capacitor based on the first voltage signal outputted by the PD, and (2) the first capacitor, wherein a voltage at a terminal of the first capacitor is outputted as the second voltage signal; and wherein the delay circuit comprises: (1) a voltage controlled delay line (VCDL) and a fixed delay line electrically coupled in series, (2) a second CP to charge or discharge a second capacitor based on the first voltage signal outputted by the PD, and (3) the second capacitor, wherein a voltage at a terminal of the second capacitor is provided as a control voltage to the VCDL.