Patent ID: 9640476
Date: 2017-05-02
CPC Classifications: H01L,H03K

Claim:
1. A driving circuit having a pin output order arranging function, the driving circuit comprising: (M*N) pins comprising a first pin, a second pin, . . . , and a (M*N)-th pin, wherein the first pin, the second pin, . . . , and an N-th pin of the (M*N) pins are arranged along a first direction in a specific distance spaced to form a first row of pins, a (N+1)-th pin, a (N+2)-th pin, . . . , and an 2N-th pin of the (M*N) pins are arranged along the first direction in the specific distance spaced to form a second row of pins, . . . , and a [(M−1)*N+1]-th pin, a [(M−1)*N+2]-th pin, . . . , and a (M*N)-th pin of the (M*N) pins are arranged along the first direction in the specific distance spaced to form a M-th row of pins; the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered along a second direction in a staggering way or an aligning way, and M and N are integers larger than 1; and an arranging module, coupled to the (M*N) pins, the arranging module correspondingly arranging a pin output order S1˜SMN of the (M*N) pins according to different application modes of the driving circuit.