Patent ID: 9568934
Date: 2017-02-14
CPC Classifications: G05F

Claim:
1. A semiconductor system comprising: a first semiconductor device configured to output a command signal, a first power supply voltage, a second power supply voltage and a third power supply voltage; and a second semiconductor device configured to drive an internal power supply voltage with the first power supply voltage in response to an internal command signal generated by decoding the command signal, generate first output data from first internal data by being supplied with the internal power supply voltage and the second power supply voltage, and generate second output data from second internal data by being supplied with the internal power supply voltage and the second power supply voltage, wherein the second semiconductor device comprises: an internal power supply voltage driving block configured to drive the internal power supply voltage with the first power supply voltage in response to the internal command signal; a first output data generation block configured to be supplied with the internal power supply voltage and the second power supply voltage, and generate the first output data from the first internal data; and a second output data generation block configured to be supplied with the internal power supply voltage and the second power supply voltage, and generate the second output data from the second internal data.