Patent ID: 9563084
Date: 2017-02-07
CPC Classifications: G02F,G09G,H01L

Claim:
1. An array substrate comprising: a first data line and a second data line, wherein the first data line and the second data line extend along a first direction and are spacedly disposed along a second direction perpendicular to the first direction; a first pixel electrode and a second pixel electrode, wherein the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line and spaced from each other along the second direction, the first pixel electrode is disposed adjacent to the first data line, the second pixel electrode is disposed adjacent to the second data line, the first data line is configured for supplying a grayscale voltage to the second pixel electrode, and the second data line is configured for supplying a grayscale voltage to the first pixel electrode; a first thin film transistor and a second thin film transistor disposed between the first data line and the second data line, wherein the first data line is electrically connected to a source of the first thin film transistor, the second pixel electrode is electrically connected to a drain of the first thin film transistor, the second data line is electrically connected to a source of the second thin film transistor, and the first pixel electrode is electrically connected to a drain of the second thin film transistor; a first via hole and a second via hole, wherein the first via hole and the second via hole respectively are arranged on same straight lines with the first thin film transistor and the second thin film transistor along a direction perpendicular to the first data line as well as the second data line, the second pixel electrode is electrically connected to the drain of the first thin film transistor through the first via hole, and the first pixel electrode is electrically connected to the drain of the second thin film transistor through the second via hole.