Patent ID: 9727468
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. An integrated circuit comprising: a plurality of processing cores coupled to a shared inclusive cache to store information contained within each of a plurality of local caches corresponding to the plurality of processing cores; and circuitry to save, in a storage external to the shared inclusive cache, coherency state information of a cache line stored in the shared inclusive cache on detection of a miss for a read request from a requestor to the cache line in a local cache of one of the plurality of processing cores that is to cause an access to the cache line in the shared inclusive cache, invalidate the cache line stored in the shared inclusive cache when the read request is to cause a cross snoop, and fill the cache line and refill, from the storage, the coherency state information of the cache line into the shared inclusive cache after the cache line is delivered to the requestor.