Patent ID: 9594668
Date: 2017-03-14
CPC Classifications: G06F

Claim:
1. A computer-implemented method executed by at least one processor for debugging a plurality of instructions in a computer program, the method comprising: providing a computer program including a plurality of instructions that includes at least one vector instruction; compiling the plurality of instructions and generating a debug table that specifies a vector register, a corresponding address range for the specified vector register, and a corresponding endian reformatting type for the specified vector register; and running a debugger, the debugger receiving a request to display contents of a vector register at a current instruction in the computer program, and in response, the debugger determines whether the current instruction has an address within an address range in the debug table, and when the current instruction is not within an address range in the debug table, the debugger displays the contents of the vector register, and when the current instruction has an address within an address range of the debug table, the debugger determines from the debug table an endian reformatting type corresponding to the address range, and displays the contents of the vector register and additionally displays the contents of the vector register after reformatting the contents according to the endian reformatting type.