Patent ID: 9748128
Date: 2017-08-29
CPC Classifications: B65G,G01B,G03F,H01L

Claim:
1. A method for aligning a wafer, the method comprising: performing a coarse alignment procedure by (a) estimating misalignment of the wafer based on a comparison of a set of vias fabricated on the wafer and a via template, and (b) adjusting a position of the wafer based on the estimated misalignment; and after performing the coarse alignment procedure, performing a fine alignment procedure by (a) determining a center location of individual vias of the set of vias fabricated on the wafer, (b) averaging the center locations of the individual vias together to obtain an average center location of the set of vias, (c) comparing the average center location with a reference location, and (d) adjusting the position of the wafer based on the averaged center location comparison if the average center location is not within a described distance of the reference location.