Patent ID: 9734981
Date: 2017-08-15
CPC Classifications: H01J

Claim:
1. A charged particle beam writing apparatus comprising: a storage configured to store writing data which defines data on a chip including a plurality of figure patterns; a first mesh region setting processing circuitry configured to set, in a case where a charged particle beam is deflected such that it moves between a plurality of small regions obtained by virtually dividing a writing region of a target object into mesh-like small regions by a predetermined same size by using one deflector of multiple stage deflector, a plurality of first mesh regions obtained by virtually dividing a region of the chip into mesh-like regions by length and width sizes same as those of each of the plurality of small regions; a dividing-into-shots processing circuitry configured to divide each of the plurality of figure patterns into a plurality of shot figures by a size that can be irradiated by one shot of the charged particle beam; a shot-figure-existence determination processing circuitry configured to assign the plurality of shot figures to the plurality of first mesh regions, and determine whether a shot figure having been assigned exists in each of the plurality of first mesh regions; a merge processing circuitry configured to perform, with respect to the plurality of first mesh regions, merging of two or more adjacent first mesh regions; a measurement processing circuitry configured to measure, for each second mesh region of a plurality of second mesh regions each obtained by merging two or more first mesh regions, a number of first mesh regions each of which has been determined that the shot figure having been assigned exists therein, in a second mesh region concerned of the plurality of second mesh regions; a per-chip region-with-shot-figure number map generation processing circuitry configured to generate a region number map for each the chip, where the number of first mesh regions with the shot figure which has been measured is defined as a map value; a deflection time estimation processing circuitry configured to estimate, by using the region number map, a deflection time for deflecting the charged particle beam to move between the plurality of small regions in a case of writing the chip concerned; and a writing mechanism including a stage on which the target object is placed, a charged particle beam source, and the multiple stage deflector, configured to write the plurality of figure patterns in the chip concerned on the target object while performing multiple stage deflection of the charged particle beam by the multiple stage deflector.