Patent ID: 9728554
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. An array substrate, comprising: a substrate; a first transistor disposed on the substrate; and a second transistor disposed on the substrate, and the first transistor and the second transistor being electrically connected and sharing a semiconducting layer, and the semiconducting layer comprising: a first lateral portion; a turning portion, connecting to the first lateral portion; and a bottom portion, connecting to the turning portion, wherein a first outer edge extending line of the first lateral portion, a second outer edge extending line of the bottom portion and a third outer edge of the turning portion completely enclose a first region, and a first inner edge extending line of the first lateral portion, a second inner edge extending line of the bottom portion and a third inner edge of the turning portion completely enclose a second region, wherein the third outer edge and the third inner edge have a same turning direction, and wherein an area of the first region is smaller than an area of the second region.