Patent ID: 9613941
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a lead frame comprising a first die paddle having at least one cavity formed entirely therethrough, and a ledge formed at at least two opposite sides of the at least one cavity, wherein a thickness of the ledge is less than a thickness of the first die paddle; a first die comprising a lower surface, wherein: a plurality of bond wires electrically connecting the first die to the lead frame; and a molding compound encapsulating an upper surface of the lead frame, the bond wires, and an upper portion of the first die, wherein the semiconductor package is mounted on a printed circuit board after application of the molding compound using solder paste, wherein the solder paste fills at least a portion of the at least one cavity and contacts the second portion of the lower surface of the first die.