Patent ID: 9741816
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method for manufacturing an electrical device, the method comprising: providing a first layer of a first conductivity type; providing an intrinsic layer onto the first layer; providing one or more deep trenches into the intrinsic layer such that the intrinsic layer has a reduced thickness at at least one portion; filling the one or more deep trenches with a material of a second conductivity type opposite to the first conductivity type; and providing a second layer of the second conductivity type onto the intrinsic layer, wherein an area of the at least one portion is less than 30% of an active area in which the first and second layers face each other, wherein the at least one portion is formed by one or more indenters having the second conductivity type, wherein the one or more indenters are electrically connected to the second layer and extend into the intrinsic layer, and wherein the one or more indenters are arranged in the deep trenches so as to form a pin-junction between the one or more indenters and the first layer with the intrinsic layer in-between.