Patent ID: 9595563
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A nonvolatile memory device comprising: a substrate; a first transistor located on the substrate, the first transistor including a first terminal and a first common terminal; a second transistor located adjacent to the first transistor in a first direction on the substrate, the second transistor including a second terminal and the first common terminal; a third transistor located adjacent to the first transistor in a second direction not parallel with the first direction on the substrate, the third transistor including a third terminal and a second common terminal; a fourth transistor located adjacent to the second transistor in the second direction and adjacent to the third transistor in the first direction, the fourth transistor including a fourth terminal and the second common terminal; a first first-wiring being gates of the first and third transistors, the first first-wiring extending in the second direction; a second first-wiring being gates of the second and fourth transistors, the second first-wiring extending in the second direction, the first first-wiring and the second first-wiring being disposed in a first wiring layer; a first second-wiring extending in the first direction, the first second-wiring partially overlapping with the first first-wiring and the second first-wiring in a plan view, the first second-wiring electrically connected to the first common terminal; a second second-wiring extending in the first direction, the second second-wiring partially overlapping with the first first-wiring and the second first-wiring in the plan view, the second second-wiring electrically connected with the second common terminal, the first second-wiring and the second second-wiring being disposed in a second wiring layer located above the first wiring layer; a first third-wiring extending in the first direction; a second third-wiring extending in the first direction; a first fourth-wiring extending in the first direction, the first fourth-wiring being located over the first second-wiring and between the first third-wiring and the second third-wiring; a second fourth-wiring extending in the first direction, the second fourth-wiring being located over the second second-wiring, the second third-wiring being located between the first fourth-wiring and the second fourth-wiring, the first and second third-wirings and the first and second fourth-wirings being disposed in a third wiring layer located above the second wiring layer; a first resistance-change element electrically connected between the first terminal of the first transistor and the first third-wiring; a second resistance-change element electrically connected between the second terminal of the second transistor and the first third-wiring; a third resistance-change element electrically connected between the third terminal of the third transistor and the second third-wiring; a fourth resistance-change element electrically connected between the fourth terminal of the fourth transistor and the second third-wiring; a first first-contact plug connecting the first second-wiring to the first fourth-wiring, the first first-contact plug located at an intersection of two virtual diagonals of a tetragon defined by the first, second, third and fourth resistance-change elements in the plan view; and a second first-contact plug connecting the second second-wiring to the second fourth-wiring, the second first-contact plug being in a linear symmetry with the first first-contact plug with respect to second third-wiring in the plan view, wherein the first to fourth resistance-change elements are disposed in a layer above the second wiring layer.