Patent ID: 9607118
Date: 2017-03-28
CPC Classifications: G06F

Claim:
1. A method, implemented on the at least one processor circuit, the method comprising: supplying, to a linear circuit simulator running on the at least one processor circuit, a linear power distribution model of an integrated circuit (IC) and a first set of voltage regulator equivalent resistances, all voltage regulator equivalent resistances of the first set of voltage regulator equivalent resistances having identical values, and the voltage regulator equivalent resistances of the first set of voltage regulator equivalent resistances corresponding proportionally to a duty cycle of a switching regulator providing a direct current (DC) supply voltage to a portion of the IC, the first set of voltage regulator equivalent resistances being input by a designer, through a user interface, into the linear circuit simulator, the duty cycle of the switching regulator being a ratio of an active time interval of the switching regulator to a period of a power gating signal; calculating, with the linear circuit simulator running on the at least one processor circuit, a first DC steady-state voltage at a sense point located on a power grid of the IC, the first DC steady-state voltage corresponding to the first set of voltage regulator equivalent resistances; supplying, to the linear circuit simulator running on at the least one processor circuit, a second set of voltage regulator equivalent resistances, the second set of voltage regulator equivalent resistances being different than the first set of voltage regulator equivalent resistances; calculating, with the linear circuit simulator running on the at least one processor circuit, a second DC steady-state voltage at the sense point of the IC, the second DC steady-state voltage corresponding to the second set of voltage regulator equivalent resistances; interpolating, with the at the least one processor circuit, using the first set and the second set of voltage regulator equivalent resistances and the first and second DC steady-state voltages at the sense point of the IC, a slope of a resistance versus voltage curve of the linear power distribution model; calculating, with the at least one processor circuit, using the slope of the resistance versus voltage curve, an updated set of voltage regulator equivalent resistances, the updated set of voltage regulator equivalent resistances corresponding to a target DC steady-state voltage at the sense point of the IC; calculating, with the linear circuit simulator running on the at least one processor circuit, the linear circuit simulator supplied with the updated set of voltage regulator equivalent resistances, a set of four performance metrics and an updated DC steady-state voltage at the sense point of the IC, the set of four performance metrics including a minimum voltage, a maximum voltage, a minimum to maximum voltage gradient and an average voltage error; supplying, to the linear circuit simulator running on the at least one processor circuit, a third set of voltage regulator equivalent resistances and calculating, with the linear circuit simulator, a third DC steady-state voltage at the sense point of the IC, the third DC steady-state voltage corresponding to the third set of voltage regulator equivalent resistances; and generating, with the at least one processor circuit, a voltage gradient plot displaying a plurality of DC steady-state voltages corresponding to a plurality of sense points on the IC, the plot including at least the updated DC steady state voltage at the sense point of the IC.