Patent ID: 9715935
Date: 2017-07-25
CPC Classifications: G11C

Claim:
1. A data erasing method of a non-volatile semiconductor memory apparatus, wherein memory cells are formed in the non-volatile semiconductor memory apparatus, and each of the memory cells comprises a control gate, a charge accumulation layer and a channel region, the data erasing method comprising: after maintaining the control gate at a fixed voltage and applying a high-voltage first erase pulse to the channel region, so as to emit electrons from the charge accumulation layer to the channel region, maintaining the control gate at the fixed voltage and applying a first weak erase pulse with a voltage lower than the voltage of the first erase pulse to the channel region, wherein the voltages of the first erase pulse and the first weak erase pulse are positive; and performing a first erase verification of determining whether the data erasing is qualified, wherein the first erase verification is performed after the first erase pulse and the first weak pulse are applied, wherein the first weak erase pulse is immediately applied following the first erase pulse, the first weak erase pulse and the first erase pulse are considered as a set, and then the first erase verification is performed after the set of the first weak erase pulse and the first erase pulse, wherein when the data erasing is determined as disqualified through the first erase verification, maintaining the control gate at the fixed voltage and applying a second erase pulse with a voltage greater than the voltage of the first erase pulse to the channel region, and maintaining the control gate at the fixed voltage and applying a second weak erase pulse with a voltage lower than the voltage of the second erase pulse to the channel region, wherein the voltages of the second weak erase pulse is larger than or equal to the voltage of first weak erase pulse.