Patent ID: 9741633
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: a substrate; a first bonding member on the substrate; a second bonding member on the substrate and spaced apart from the first bonding member to surround the first bonding member; a semiconductor chip on the first bonding member; a barrier member on the second bonding member to surround the semiconductor chip; a groove defined by a space bounded by the first bonding member, the second bonding member and the substrate; and a sealing member sealing the groove, the first bonding member, and the semiconductor chip in a space between the substrate, the second bonding member, and the barrier member; wherein the barrier member comprises a plurality of separate barrier elements, and the plurality of separate barrier elements are connected to one another to provide the barrier member; wherein the plurality of separate barrier elements are ring-shaped structures, and the barrier member is provided by vertically stacking the ring-shaped structures.