Patent ID: 9740439
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A system comprising: a main board and a solid-state storage board separate from the main board, the main board being located on a host computer, the main board coupled to the solid-state storage board via an interface bus, the solid-state storage board including an address translation module, a solid-state memory device, and flash memory devices, the flash memory devices including a plurality of physical memory locations identified by physical addresses, the flash memory devices including a first flash memory device, the system configured to split a management complexity of the first flash memory device between the main board, the solid-state storage board, and the address translation module, the solid-state storage board configured to perform a first portion of the management complexity, which includes: retrieve valid pages within data from a first physical address on the first flash memory device, and the main board configured to perform a second portion of the management complexity, which includes: the address translator module configured to facilitate a read physical address flash operation from the first flash memory device and provide low latency and high bandwidth delivery of flash commands to the first flash memory device by translating the first logical address to the first physical address on the first flash memory device based on the correspondence, the translation of the first logical address by the address translator module is responsive to the request to read the data received by the system, wherein the acceleration operations include utilizing an error correction coding of an error correction code decoder and a table to support the translations between logical addresses and physical addresses, wherein the establishment of the correspondence between the first logical address and the first physical address is responsive to a projected performance of the main board and characteristics of at least one of the flash memory devices to account for a location of prior errors outputted by the error correction code decoder, wherein the acceleration operations include the primary error correction code and redundant array of independent disks acceleration operations to support the writing of the write data and to avoid implementing a second portion of the management complexity by the solid-state storage board, wherein the acceleration operations includes a garbage collection operation comprising: