Patent ID: 9735138
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method of making an integrated circuit package having first and second metal plates, comprising: (a) forming a circuit layered structure out of the first metal plate that includes a metal substrate and a circuit pattern, the metal substrate having opposite first and second surfaces, the circuit pattern including at least two spaced apart die contacts that protrude from the first surface of the metal substrate, the metal substrate directly interconnecting the die contacts; (b) bonding first and second terminal contacts of an electronic die to the die contacts, respectively, so as to form an assembly of the electronic die and the circuit layered structure having the metal substrate directly interconnecting the die contacts; (c) forming a first insulator layer on the first surface of the metal substrate of the assembly of the electronic die and the circuit layered structure to encapsulate the die and the die contacts; (d) etching the metal substrate from the second surface to form an interconnection sub-structure that includes a patterned first interconnection layer and at least one first contact; where the first interconnection layer having upper and lower surfaces and an interconnecting segment, the first contact protruding from the lower surface of the first interconnection layer, the die contacts protruding from the upper surface of the first interconnection layer, the interconnecting segment directly interconnecting the first contact and one of the die contacts, and the die contacts are not physically connected to each other through the interconnection sub-structure; (e) forming an interconnection layered structure out of the second metal plate that includes an interconnection substrate and at least one second contact protruding from the interconnection substrate and then bonding the second contact to the first contact; (f) etching the interconnection substrate so as to form the interconnection substrate into a patterned second interconnection layer which is formed with at least one through-hole to expose a portion of the first interconnection layer and a portion of the first insulator layer; and (g) forming a second insulator layer that fills the through-hole in the second interconnection layer and an inner space between the first and second interconnection layers.