Patent ID: 9553594
Date: 2017-01-24
CPC Classifications: H03K,H03L

Claim:
1. A delay-locked loop (DLL), comprising: a first phase detector that receives a clock signal and a first delayed version of the clock signal and generates first up and down signals; a counter that is connected to the first phase detector and receives the first up and first down signals, receives a first control signal, and generates a count value, wherein the counter modifies the count value based on the first control signal when the DLL is not in a true-lock condition; a delay circuit that receives the clock signal and a select signal, and is connected to the counter for receiving the count value, and generates the first delayed version of the clock signal based on the count value and a second delayed version of the clock signal based on the count value and the select signal; and a false-lock detection and recovery circuit, connected to the counter and the delay circuit, that receives the clock signal, the count value, and the second delayed version of the clock signal, and generates the select signal and the first control signal, wherein the DLL is in the true-lock condition when the average of the phase difference between the clock signal and the second delayed version of the clock signal is greater than a first threshold value and less than a second threshold value.