Patent ID: 9728619
Date: 2017-08-08
CPC Classifications: B82Y,H01L

Claim:
1. A system, comprising: a wafer, including a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer, the wafer having a first region and a second region, the first region having a pair of first SOI pads connected via a first plurality of first nanowire channels formed therein in a first parallel, ladder-like formation, one of the first SOI pads comprising a first exterior face, and the second region having a pair of second SOI pads connected via a second plurality of second nanowire channels formed therein in a second parallel, ladder-like formation, which is oriented in parallel and in phase with the first parallel, ladder-like formation such that corresponding ones of the first and second nanowire channels respectively extend longitudinally along a same linear path, one of the second SOI pads comprising a second exterior face; and an entirely removable silicon nitride mask directly covering respective entireties of top surfaces and side surfaces of the first SOI pads and the first nanowire channels in only the first region and preventing a thinning of the second SOI pads and the second nanowire channels in the second region due to oxidation from having effect at the top and side surfaces of the first SOI pads and the first nanowire channels in the first region, wherein: none of the SOI pads or nanowire channels of the first or the second region directly contact any of the SOI pads or nanowire channels of the second or the first region, respectively, such that the first and second exterior faces are disposed in parallel to oppositely face one another at a distance.