Patent ID: 9741752
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method for manufacturing a thin-film transistor (TFT) substrate, comprising the following steps: (1) providing a base plate and depositing, in sequence, a buffer layer, a semiconductor layer, an insulation layer, and a gate metal layer on the base plate; (2) coating a layer of photoresist material on the gate metal layer and subjecting the layer of photoresist material to patterning treatment by using a partial transmitting mask so as to form a center-raised-side-recessed photoresist layer, wherein the photoresist layer comprises a first photoresist segment located at a central portion and second photoresist segments respectively located at two opposite sides of the first photoresist segment with a thickness of the first photoresist segment being greater than a thickness of the second photoresist segments; (3) applying a first etching operation to remove portions of the gate metal layer and the insulation layer that are not covered by the photoresist layer; and applying a second etching operation to remove a portion of the semiconductor layer that is not covered by the photoresist layer to form an active layer; (4) subjecting the photoresist layer to an ashing operation so as to thin the first photoresist segment and remove the second photoresist segments; applying an etching operation to remove portions of the gate metal layer and the insulation layer that are not covered by the photoresist layer so as to form a gate electrode and a gate insulation layer; and applying treatment to the active layer, with the photoresist layer, the gate electrode, and the gate insulation layer as a blocking layer, so as to enhance electrical conductivity of portions of the active layer that are not covered by the gate electrode and the gate insulation layer to form a source contact zone, a drain contact zone, and a channel zone that is located between the source contact zone and the drain contact zone; (5) removing a remaining portion of the photoresist layer and depositing an interlayer dielectric layer on the gate electrode, the active layer, and the buffer layer and subjecting the interlayer dielectric layer to patterning treatment by using one mask so as to form, in the interlayer dielectric layer, a first via and a second via respectively corresponding to the source contact zone and the drain contact zone; and (6) depositing a source/drain metal layer on the interlayer dielectric layer, subjecting the source/drain metal layer to patterning treatment by using one mask so as to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively in contact engagement with the source contact zone and the drain contact zone of the active layer through the first via and the second via thereby forming a TFT substrate.