Patent ID: 9709629
Date: 2017-07-18
CPC Classifications: G01R

Claim:
1. A method for launch-off-shift at-speed scan testing for at least two scan chains of an integrated circuit, comprising: iteratively shifting set values for functional elements of a first one of the scan chains clocked with a shift clock; iteratively shifting set values for functional elements of a second one of the scan chains clocked with the shift clock; launching an at-speed scan test clocked with a functional clock for the first one of the scan chains at a first last shift cycle of the first one of the scan chains; delaying a second last shift cycle of the second one of the scan chains relative to the first last shift cycle of the first one of the scan chains for a predetermined time span based on a clock cycle of the functional clock; launching an at-speed scan test clocked with the functional clock for the second one of the scan chains at the second last shift cycle of the second one of the scan chains; capturing the sample values of the functional elements of the first one of the scan chains after the first last shift cycle of the first one of the scan chains; and capturing the sample values of the functional elements of the second one of the scan chains after the second last shift cycle of the second one of the scan chains.