Patent ID: 9703730
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. An arbitration circuit comprising: an interface circuit configured to store transactions output from a plurality of master circuits in a first-in-first-out type first buffer and outputs the stored transactions stored in the first buffer to a slave circuit; and a control circuit configured to control the interface circuit based on results of monitoring the transactions output from the plural master circuits, wherein, when a high-priority transaction higher in priority than one of the stored transactions is output from one of the plural master circuits, the interface circuit outputs, according to the control by the control circuit, a cancel request of a low-priority transaction whose priority is lower than the priority of the high-priority transaction and which is included in the stored transactions, to a first-in-first-out type second buffer which is in the slave circuit and in which the same transactions as the stored transactions are stored, and when the cancel request is successful, the interface circuit outputs the high-priority transaction to the slave circuit, and outputs the low-priority transaction whose cancel request is successful to the slave circuit after outputting the high-priority transaction to the slave circuit.