Patent ID: 9646838
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a semiconductor structure comprising at least one first circuit element comprising a first semiconductor material and at least one second circuit element comprising a second semiconductor material, wherein said at least one first circuit element comprises one or more first field effect transistors, each of said one or more first field effect transistors comprising a gate electrode and a sidewall spacer formed adjacent to sidewalls of said gate electrode; performing an ion implantation process to implant dopant ions into a source region and a drain region of said one or more first field effect transistors in the presence of said sidewall spacer, wherein an entire outer sidewall surface of said sidewall spacer is directly exposed to said ion implantation process; forming a dielectric layer having an intrinsic stress, said dielectric layer comprising a first portion over said at least one first circuit element and a second portion over at least a portion of each of said at least one second circuit element, wherein said first portion of said dielectric layer covers said entire outer sidewall surface of said sidewall spacer that was exposed to said ion implantation process; performing a first annealing process, wherein an intrinsic stress is created at least in said first semiconductor material by stress memorization; and after said first annealing process, removing said first portion of said dielectric layer, forming a layer of a metal and performing a second annealing process wherein said metal and said first semiconductor material react chemically to form a silicide, said second portion of said dielectric layer substantially preventing a chemical reaction between said second semiconductor material and said metal in at least a portion of each of said at least one second circuit element.