Patent ID: 9735788
Date: 2017-08-15
CPC Classifications: H03K,H03L

Claim:
1. A phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the phase locked loop (PLL) comprising: a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal; a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal; an interpolator controller configured to generate an interpolator control signal that enables one of the first and second interpolator clock signals to be selected in a specific ratio; a multiplexer configured to select one of the first and second interpolator clock signals according to the interpolator control signal; a divider configured to divide the selected one of the first and second interpolated clock signals to generate a divided clock signal; and a digitally controlled oscillator configured to control a frequency of the output clock signal corresponding to a phase difference between the reference clock signal and the divided clock signal.