Patent ID: 9598772
Date: 2017-03-21
CPC Classifications: C23C,H01L

Claim:
1. A method of forming a semiconductor device, comprising: providing a substrate; forming a first under-bump metallurgy (UBM) layer on the substrate; forming a mask layer on the first UBM layer, wherein the mask layer has an opening exposing a portion of the first UBM layer; performing an electroless plating process to form a second UBM layer on the exposed portion of the first UBM layer within the opening of the mask layer, wherein performing the electroless plating comprises forming a layer of palladium over the first UBM layer and plating a copper layer over the layer of palladium; forming a solder layer overlying the second UBM layer within the opening of the mask layer; removing the mask layer; removing the first UBM layer not covered by the solder layer; and forming a Cu post between the second UBM layer and the solder layer within the opening of the mask layer, wherein the Cu post and the second UBM layer have sidewalls that are substantially coplanar to each other, and wherein an entirety of the solder layer and the Cu post have sidewalls that are substantially coplanar to each other.