Patent ID: 9659635
Date: 2017-05-23
CPC Classifications: G11C,H01L

Claim:
1. An integrated circuit structure comprising: a Static Random Access Memory (SRAM) array comprising a first sub-array comprising a first plurality of rows and a plurality of columns of SRAM cells, and a second sub-array comprising a second plurality of rows and the plurality of columns of SRAM cells, and each of the SRAM cells in the SRAM array comprises: a first bit-line and a first complementary bit-line connected to the first and the second pass-gate MOS devices of SRAM cells in a column in the first sub-array; a second bit-line and a second complementary bit-line connected to the first and the second pass-gate MOS devices of SRAM cells in the column in the second sub-array, wherein the first bit-line and the first complementary bit-line are disconnected from the second bit-line and the second complementary bit-line; a sense amplifier circuit electrically coupled to, and configured to sense, the first bit-line, the first complementary bit-line, the second bit-line, and the second complementary bit-line; and a first bridging metal line and a second bridging metal line connected to the first bit-line and the first complementary bit-line, respectively, wherein the first bridging metal line and the second bridging metal line cross over the second sub-array without connected to SRAM cells in the second sub-array.