Patent ID: 9553602
Date: 2017-01-24
CPC Classifications: H03M

Claim:
1. An apparatus comprising: a comparator, the comparator is configured with a first high input, a first low input, and is configure to receive a clock signal; a logic/latch block, the logic/latch block is configured to receive the clock signal and an output from the comparator, the logic/latch block is configured to output a control signal and a digital N-bit output signal; and a first local charge-averaging capacitor array (LCACA), the first LCACA is configured to receive the control signal and a reference voltage, an output of the first LCACA is coupled to the first low input, the first LCACA is divided into a high sub-array and a low sub-array, the high sub-array to be pre-charged to a high reference voltage and the low sub-array to be pre-charged to a low reference voltage, the high reference voltage is greater than the low reference voltage, wherein in operation an analog signal is input to the first high input and the digital N-bit output signal is the digital conversion of the analog signal.