Patent ID: 9626465
Date: 2017-04-18
CPC Classifications: G06F

Claim:
1. A method of verifying operation of an arbiter in a hardware design, the arbiter receiving a plurality of requests over a plurality of clock cycles, the plurality of requests comprising a watched request, the method comprising, in a processor: identifying, for each clock cycle, any requests received by the arbiter in that clock cycle; identifying, for each clock cycle, any requests output from the arbiter in that clock cycle; tracking a priority of the watched request relative to other pending requests in the arbiter using a counter, the counter updated based on the requests identified as being received by and output from the arbiter in each clock cycle and a mask identifying a relative priority of requests received by the arbiter in a same clock cycle; and verifying operation of the arbiter using an assertion written in an assertion-based language, the assertion establishing a relationship between the counter and a clock cycle in which the watched request is output from the arbiter.