Patent ID: 9614537
Date: 2017-04-04
CPC Classifications: H03L

Claim:
1. A clock generator circuit, comprising: a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock; a digitally controlled delay line (DCDL) configured to delay the reference clock based on a first control code; a pulse generator configured to generate pulses based on the delayed reference clock; a digitally controlled oscillator (DCO) including an injection input coupled to the pulse generator to receive the pulses, the DCO configured to generate an output clock based on the pulses and a second control code; a phase detector configured to compare phases of the output clock and the reference clock and generate the phase error signal; and a control circuit configured to generate the first and second control codes based on the phase error signal.