Patent ID: 9560739
Date: 2017-01-31
CPC Classifications: H01L,H05K

Claim:
1. A wiring substrate comprising a layered structure including one or more insulation layers and one or more conductor layers, the wiring substrate being characterized in that a plurality of connection terminals are formed on the layered structure so as to be separated from one another; a filling member is filled between the connection terminals; the filling member has a thickness smaller than that of the connection terminals; each of the connection terminals has an upper surface and a side surface, the side surface composed of a contact surface which is in contact with the filling member and a spaced surface which is not in contact with the filling member and which is located above the contact surface and below a top surface of the filling member such that a space is defined between the spaced surface and the filling member with the space having a depth of 4 μm or less; and a metal plating layer is formed on the upper surface and the spaced surface of each of the connection terminals and enters the space defined between the spaced surface and the filling member; wherein the layered structure has thereon a solder resist layer having an opening through which the plurality of connection terminals are exposed, the solder resist layer covering a wiring pattern connected to the connection terminals, and wherein the solder resist layer and the filling member are integrally formed.