Patent ID: 9621339
Date: 2017-04-11
CPC Classifications: G06F,H04L

Claim:
1. A host device, coupled to a slave device through a bus interface, comprising: a frequency detector, receiving a first work frequency, and determining whether the first work frequency is the same as a second work frequency of the slave device; a jitter detector, receiving a first clock signal, and determining whether a jitter difference corresponding to the first clock signal exceeds a predetermined range; and a signal processing unit, comprising a clock signal input pin that receives the first clock signal, a data input pin that receives data, and an output pin that outputs a data signal; wherein when the first work frequency is the same as the second work frequency and the jitter difference is within the predetermined range, the signal processing circuit outputs the data signal to the slave device through the bus interface according to the first clock signal, the data and Seems System Management Bus protocol, and the bus interface has only one communication pin.