Patent ID: 9576639
Date: 2017-02-21
CPC Classifications: G11C

Claim:
1. A method for controlling a memory device comprising: supplying a clock signal from a controller to the memory device; supplying a chip select signal from the controller to the memory device; supplying a mode register setting command from the controller to the memory device to set an internal mode signal in the memory device; supplying an access command from the controller to the memory device; wherein the controller activates the chip select signal at the same time as the access command if the mode register setting command sets the internal mode signal to a deactivated level and the controller activates the chip select signal a first predetermined number of cycles of the clock signal earlier than the access command if the mode register setting command sets the internal mode signal to an activated level; and wherein the memory device delays the chip select signal by the first predetermined number of cycles of the clock signal to provide a first internal chip select signal, selects the chip select signal as a second internal chip select signal when the internal mode signal is deactivated, selects the first internal chip select signal as the second internal chip select signal when the internal mode signal is activated, and decodes the access command to provide first internal command signals when the second internal chip select signal is activated.