Patent ID: 9607687
Date: 2017-03-28
CPC Classifications: G11C

Claim:
1. A memory cell circuit for storing data, comprising: a plurality of p-type metal oxide semiconductor (PMOS) devices and a plurality of n-type metal oxide semiconductor (NMOS) devices for storing states of the memory cell circuit; a plurality of access devices with each access device being coupled to at least one of the plurality of PMOS devices and at least one of the plurality of NMOS devices, the plurality of access devices to provide access for storing states of the memory cell circuit; and a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices coupled to the plurality of PMOS devices, the set of electrically inactive PMOS devices in combination with the plurality of PMOS devices to enable a continuous p-type diffusion layer for the memory cell circuit, wherein a gate of a first electrically inactive PMOS device is coupled to a gate of a first electrically active PMOS device of the plurality of PMOS devices.