Patent ID: 9600382
Date: 2017-03-21
CPC Classifications: G06F,Y02D

Claim:
1. An error recovery circuit based on an on-chip monitoring circuit, said error recovery circuit including an error signal statistics module, a voltage and frequency control module, an error recovery control module, a local error recovery module, and a global error recovery module, wherein: the on-chip monitoring circuit is integrated at a terminal of each first N−1 pipeline stages of a Central Processing Unit (CPU) core in N-stage pipeline architecture, and monitors a time sequence information of each clock cycle in an operating circuit, where N− is the number of pipeline stages and is a positive integer greater than or equal to 3 but smaller than 20; the on-chip monitoring circuit feeds any error signals detected by it into the error signal statistics module; the error signal statistics module performs statistics on a percentage of the number of error signals in a specific number of clock cycles to a total number of clock cycles, and such percentage is considered as an error ratio R the voltage and frequency control module controls an increase and decrease of the operating voltage and frequency of the system as well as the control accuracy, and the voltage and frequency control module and error signal statistics module feed system state and error ratio R the error recovery control module has a preset comparative threshold T