Patent ID: 9728570
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method of forming an integrated circuit, comprising: forming a deep trench grid from an upper surface of a substrate at a back side of the substrate; forming a passivation layer lining the deep trench grid within the substrate, the passivation layer including a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer; forming a first dielectric layer over the passivation layer, lining the deep trench grid and extending over the upper surface of the substrate; and forming a second dielectric layer over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid; wherein the air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.