Patent ID: 9547596
Date: 2017-01-17
CPC Classifications: G06F,Y02D

Claim:
1. A data processing apparatus for forming a portion of a coherent cache system, comprising: a master device configured to perform data processing operations, including a wait for event operation causing the master device to enter a power saving mode; a cache coupled to the master device and arranged to store data values for access by the master device when performing said data processing operations; coherency handling circuitry within the cache, and responsive to a coherency request from another portion of the coherent cache system, to detect whether a data value identified by the coherency request is present in the cache, and if so to cause a coherency action to be taken in respect of that data value stored in the cache; and wake event circuitry within the cache, and responsive to the coherency handling circuitry, to locally issue a wake event to the master device if the coherency action is taken; the master device being responsive to the wake event to exit the power saving mode, wherein: during performance of said data processing operations, the master device is configured to perform an access operation to access a semaphore stored in shared memory, performance of the access operation causing a current value of the semaphore to be stored in the cache, the shared memory being shared with at least one further master device within the coherent cache system, and the semaphore being used to maintain an ordering between one or more data processing operations performed by the master device and one or more data processing operations performed by the at least one further master device; and if the current value obtained by the access operation indicates a stall condition, the master device is configured to perform the wait for event operation.