Patent ID: 9666489
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A method for fabricating semiconductor devices, the method comprising: forming a substrate having a first insulator layer, a first semiconductor layer arranged on the first insulator layer, a second insulator layer arranged on the first semiconductor layer, and a second semiconductor layer arranged on the second insulator layer; etching to form a first fin and a second fin each fin comprising a portion of the first semiconductor layer, the second insulator layer, and the second semiconductor layer; forming a sacrificial gate stack over a channel region of the first fin and the second fin; epitaxially growing a first source/drain region on an exposed portion of the first semiconductor layer of the first fin, growing a second source/drain region on an exposed portion of the first semiconductor layer of the second fin, growing a third source/drain region on an exposed portion of the second semiconductor layer of the first fin, and growing a fourth source/drain region on an exposed portion of the second semiconductor layer of the second fin; depositing an insulator layer over the source/drain regions; removing a portion of the insulator layer to expose the fourth source/drain region; removing the fourth source/drain region to expose a portion of the second semiconductor layer of the second fin; and epitaxially growing a fifth source/drain region on the exposed portion of the second semiconductor layer of the second fin, the fifth source/drain region formed from a different material than the first source/drain region.