Patent ID: 9690707
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A method for prefetching an instruction cache line, comprising: during execution in a processor in a computer system, performing a current instruction cache access which is directed to a current cache line; if the current instruction cache access causes a cache miss or is a first demand fetch for a previously prefetched cache line, determining whether the current instruction cache access is discontinuous with a preceding instruction cache access, wherein the current instruction cache access is discontinuous with the preceding instruction cache access if a difference between an address for the current cache line and an address for a cache line associated with the preceding instruction cache access exceeds a predetermined threshold that is greater than or equal to 1; and if the current instruction cache access is discontinuous, completing the current instruction cache access by: performing a cache access to service the cache miss or the first demand fetch; and using location data for a predicted cache line associated with a discontinuous instruction cache access which is predicted to follow the current instruction cache access to prefetch the predicted cache line, wherein using the location data comprises using a set value and a way value which collectively specify a location in an outer-level cache for the predicted cache line, and wherein a next line table (NLT) stores the set value and the way value as the location for the predicted cache line instead of saving an address for the predicted cache line in the outer-level cache; and wherein an NLT entry which contains the location data is stored in the outer-level cache, wherein the outer-level cache is set-associative, wherein the NLT entry is associated with the same tag in the outer-level cache as the current cache line, and whereby a lookup to service a cache miss for the current instruction cache access can return the NLT entry as well as the current cache line.