Patent ID: 9627410
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A FinFET structure comprising: a semiconductor-on-insulator substrate including a bottom semiconductor layer and an electrically insulating layer adjoining the bottom semiconductor layer; a plurality of semiconductor fins mounted to the substrate, each of the fins having base portions adjoining the electrically insulating layer and sidewalls including (110) surfaces; a plurality of parallel gate structures operatively associated with the semiconductor fins, the gate structures including sidewalls and extending perpendicularly with respect to the semiconductor fins; a first set of dielectric sidewall spacers adjoining the sidewalls of the gate structures; a second set of dielectric sidewall spacers adjoining the first set of dielectric sidewall spacers and covering portions of the source/drain structures; a plurality of pairs of unmerged epitaxial source/drain structures including (111) planes, each pair of source/drain structures being operatively associated with one of the semiconductor fins; a plurality of parallel, fin-shaped cavities between and separating each pair of source/drain structures, the cavities extending to the electrically insulating layer of the semiconductor-on-insulator substrate, and a metal silicide layer formed on the (111) planes of the epitaxial source/drain structures and adjoining the source/drain structures and filling the plurality of cavities.