Patent ID: 9608203
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A method for manufacturing a memory device, comprising: forming a block copolymer layer on a substrate, the block copolymer layer containing a first polymer and a second polymer having a lower surface energy than that of the first polymer; performing a thermal treatment on the block copolymer layer, the thermal treatment separating the block copolymer layer such that a first phase containing the first polymer and extending in a first direction and a second phase containing the second polymer and extending in the first direction are alternately arrayed; forming a first metal wiring layer selectively on the first phase, the first metal wiring layer extending in the first direction; forming a memory layer on the first metal wiring layer, a resistance of the memory layer being changed by application of a voltage; and forming a second metal wiring layer on the memory layer, the second metal wiring layer extending in a second direction, the second direction intersecting the first direction.