Patent ID: 9726952
Date: 2017-08-08
CPC Classifications: G02F,G09G

Claim:
1. A liquid crystal display, comprising: a gate line configured to receive a gate-on signal during a first period of a frame period; a data line crossing the gate line to receive a data voltage; a first sub-pixel connected to the gate line and the data line to receive the data voltage in response to the gate-on signal; a second sub-pixel connected to the gate line and the data line to receive the data voltage in response to the gate-on signal; a first sharing capacitor including a first electrode and a second electrode; a connection part electrically connecting the first electrode of the first sharing capacitor to the second sub-pixel after the first period; a first reset line configured to receive a first reset signal; a first transistor connected to the gate line and the first reset line to output the first reset signal in response to the gate-on signal; and a second reset line configured to receive a second reset signal, wherein the first electrode of the first sharing capacitor is connected to the first transistor and the second electrode of the first sharing capacitor is connected to the second reset line.