Patent ID: 9676619
Date: 2017-06-13
CPC Classifications: B81C,G01R,H01L

Claim:
1. A method for wafer-level chip scale package testing, comprising: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; applying an external stimulus; for each strip carrier, detecting a response of a reference sensor disposed on the strip carrier; for each strip carrier, adjusting a position of the strip carrier based on the response of the reference sensor to accomplish a positional calibration of the strip carrier relative to the external stimulus; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices.