Patent ID: 9568542
Date: 2017-02-14
CPC Classifications: G01R,G11C

Claim:
1. A circuit comprising: a data line having a transmit channel and a receive channel connected in parallel to a data pin, the transmit channel including a transmit amplifier and a transmit latch, the receive channel including a receive amplifier and a receive latch; a data strobe line having a strobe transmit channel and a strobe receive channel connected in parallel to a data strobe pin, the strobe transmit channel connected to a clock input of the transmit latch, the strobe receive channel connected to a clock input of the receive latch; a pattern generator connected to the transmit channel; a control circuit configured to actuate the pattern generator to generate a pattern signal to the transmit channel; and a pattern checker connected to the receive channel, the pattern checker configured to receive the pattern signal at the receive channel and output a verify signal indicating integrity of the pattern signal; a multiplexer connected in series to the receive channel between the receive amplifier and the receive latch, the multiplexer having a second input connected to the transmit channel at a node between the transmit latch and the transmit amplifier; wherein the control circuit is further configured to 1) in a first test mode, actuate the pattern generator and the multiplexer to propagate the pattern signal through a first loop including the transmit channel, the receive channel, the transmit amplifier and the receive amplifier, and 2) in a second test mode, actuate the pattern generator and the multiplexer to propagate the pattern signal through a second loop including the transmit channel and the receive channel and excluding the transmit amplifier and the receive amplifier.