Patent ID: 9711513
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a semiconductor structure comprising a semiconductor material; forming a layer of a floating gate material that is surrounded by at least one electrically insulating material over said semiconductor material; forming a gate stack over said semiconductor structure; patterning said gate stack, said patterning of said gate stack forming a select gate, said select gate comprising a first portion and a second portion, wherein said first portion of said select gate is provided over a portion of said semiconductor material adjacent to said layer of floating gate material and said second portion of said select gate is provided over a portion of said layer of floating gate material adjacent to said first portion of said select gate; and after said patterning of said gate stack, forming a control gate insulation layer above at least a portion of said select gate and forming a control gate material above said control gate insulation layer to define a control gate over a portion of said layer of floating gate material.