Patent ID: 9607903
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A method for forming field effect transistors, the method comprising: forming a first dummy gate stack over a first fin; forming a second dummy gate stack over a second fin; depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin; patterning a first masking layer on the first dummy gate stack and the first fin; etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack; removing the first masking layer; epitaxially growing a silicon material on the second fin; depositing a layer of oxide material on the first layer of spacer material, the silicon material and the second dummy gate stack; depositing a second layer of spacer material on the layer of oxide material; patterning a second masking layer over the second dummy gate stack and the second fin; removing exposed portions of the second layer of spacer material; removing exposed portions of the layer of oxide material; etching to remove portions of the first layer of spacer material and form a spacer adjacent to the first dummy gate stack; removing the second masking material; epitaxially growing a silicon material on the first fin; patterning a third masking layer on the first dummy gate stack and the first fin; removing exposed portions of the second layer of spacer material; and removing the third masking layer.