Patent ID: 9698156
Date: 2017-07-04
CPC Classifications: G11C,H01L

Claim:
1. A memory device, comprising: first and second stacks of conductive strips having sidewalls; data storage structures on the sidewalls of the conductive strips in the first and second stacks, and on top surfaces of the first and second stacks; first and second vertical thin channel films having outside surfaces and inside surfaces, the outside surfaces disposed on the data storage structures on the sidewalls of the first and second stacks; first memory cells at cross-points between the outside surfaces of the first vertical thin channel films and the conductive strips in the first stacks of conductive strips, and second memory cells at cross-points between the outside surfaces of the second vertical thin channel films and the conductive strips in the second stacks of conductive strips; a reference conductor below the first and second stacks, and wherein the first and second vertical thin channel films are in physical contact with the reference conductor; and insulating structures isolating the first vertical thin channel films of adjacent first memory cells along the conductive strips in the first stack of conductive strips, and isolating the second vertical thin channel films of adjacent second memory cells along the conductive strips in the second stack of conductive strips.