Patent ID: 9748252
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor antifuse device, comprising: a non-planar diffusion area having a fin configured with an upper tapered channel portion and a lower portion wherein, in a cross-sectional view perpendicular to the fin, the upper tapered channel portion has a width that narrows from a base of the tapered channel portion to a top of the tapered channel portion, wherein the width at the top is 50% or more thinner than the width at the base; a layer of insulation material on opposing sides of the lower portion of the fin; and a gate structure on opposing sides of the tapered channel portion and the top of the tapered channel portion, the gate structure including a first conductive contact and a dielectric isolation layer between the tapered channel portion and the first conductive contact; wherein a programmed state of the antifuse device includes a low resistance conductive path through the dielectric isolation layer electrically connecting the non-planar diffusion area and the first conductive contact.