Patent ID: 9691885
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. Method for manufacturing a transistor, the method comprising: arranging a stack on a semiconductor substrate, the stack comprising a sacrificial layer and an insulator layer; the insulator layer at least partially being arranged between the semiconductor substrate and the sacrificial layer, wherein a recess is formed within the stack, wherein the recess extends through the stack to the semiconductor substrate, so that the recess at least partially overlaps with a collector region of the semiconductor substrate, and wherein the collector region extends from a main surface of the semiconductor substrate into a substrate material of the semiconductor substrate; generating a base structure at the collector region and in the recess, wherein the base structure contacts and covers the collector region within the recess of the sacrificial layer; generating an emitter structure at the base structure, wherein the emitter structure contacts and at least partially covers the base structure within the recess of the sacrificial layer; removing the sacrificial layer at least partially such that a lateral surface region of the base structure is exposed; and generating a doped electrode layer by epitaxially growing a semiconductor material to the exposed lateral surface region of the base structure, such that the doped electrode layer connects the lateral surface region of the base structure.