Patent ID: 9536779
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of forming a wiring structure for an integrated circuit device, the method comprising: forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines such that first portions of the first and second metal lines are covered and second portions of the first and second metal lines are not covered so as to define exposed regions, the masking selected regions comprising depositing a nitrogen-doped silicon carbide layer over the ILD layer and first and second metal lines, and patterning and removing portions of the nitrogen-doped silicon carbide layer; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis; and following the plating of the metal cap regions over the exposed regions of the first and second metal lines, forming a conformal insulator layer over the metal cap regions and remaining portions of the nitrogen-doped silicon carbide layer.