Patent ID: 9569393
Date: 2017-02-14
CPC Classifications: G06F,G11C

Claim:
1. A memory comprising: buffer circuitry for coupling to a primary data bus having a primary data bus width, the primary data bus to route data of a primary data transfer continuous throughput; plural memory device groups coupled to the buffer circuitry via respective secondary data bus paths, each having a continuous throughput smaller than the primary data transfer continuous throughput, each group responsive to a memory request to transfer data groups collectively forming a data thread, the plural memory device groups isolated from the primary data bus by the buffer circuitry; and a memory controller coupled to the buffer circuit via the primary data bus, the memory controller to interface the transfer of a first data thread across one of the secondary data bus paths with the transfer of the first data thread across the primary data bus width over a first interval, the transfer of the first data thread across the primary data bus using less than the primary data transfer continuous throughput during the first time interval, the memory controller to issue scheduled memory commands that are organized based on the data groups, and the transfer of the data threads is responsive to the issued memory commands; and where the memory controller comprises