Patent ID: 9607901
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A method, comprising: depositing a hard mask on a tensile strained silicon semiconductor layer supported by a substrate; patterning said hard mask and tensile strained silicon semiconductor layer into a plurality of fins; said plurality of fins including a first group of fins in a first area of the substrate and a second group of fins in a second area of the substrate; forming sidewall spacers on the plurality of fins; depositing and patterning a tensile strained material to cover the second group of fins in the second area but not cover the first group of fins; performing an anneal which relaxes the tensile strained silicon semiconductor of the second group of fins in the second area of the substrate; depositing and patterning a masking material to cover the first group of fins in the first area of the substrate but not cover the second group of fins; providing silicon-germanium material on the second group of fins in the second area of the substrate; driving germanium from the silicon germanium material into the second group of fins to produce compressive strained silicon-germanium semiconductor fins in the second area of the substrate; and removing the masking material to produce tensile strained silicon semiconductor fins in the first area of the substrate.