Patent ID: 9734129
Date: 2017-08-15
CPC Classifications: G06F,H03M

Claim:
1. A circuit configured to perform an inverse Fourier transform operation based on an input vector and to generate a group of results corresponding to the inverse Fourier transform operation, the circuit comprising: a first number of inputs, each input configured to receive an element of the input vector and coupled to a multiplexer configured to iteratively produce intermediate values using a delay element in a feedback path that includes a multiplier, the feedback path between a multiplexer input of the multiplexer and a multiplexer output of the multiplexer; multipliers coupled to the multiplexer outputs and configured to perform multiple iterations of calculations associated with the inverse Fourier transform operation; and adders coupled to the multipliers and configured to iteratively output subgroups of the group of results corresponding to the inverse Fourier transform operation based on signals from the multipliers, wherein the first number is less than a number of inverse Fourier transform results in the group of results corresponding to the inverse Fourier transform operation.