Patent ID: 9553055
Date: 2017-01-24
CPC Classifications: B06B,B81B,H01L

Claim:
1. A method for fabricating semiconductor devices, the method comprising the steps of: providing a wafer; forming a device layer on a top surface of the wafer; etching the device layer to form a plurality of separation trenches so as to expose a plurality of sections of the wafer, the plurality of separation trenches separating the device layer into a plurality of structure members; and forming one or more reinforcing elements connecting one or more structure members of the plurality of structure members to the wafer so as to strengthen an integration of the plurality of structure members and the wafer; wherein the one or more reinforcing elements are made of a dielectric material; wherein the wafer has a substrate and an insulation layer on top of the substrate; wherein the device layer is attached to the insulation layer; wherein the substrate and the plurality of structure members form a plurality of electrode units; wherein the plurality of structure members are a plurality of upper electrodes; wherein the substrate is a lower electrode layer; and wherein the substrate and the plurality of structure members are made of a low resistance silicon.