Patent ID: 9537776
Date: 2017-01-03
CPC Classifications: H04L

Claim:
1. An Ethernet traffic management device, comprising: a first port; a second port; a third port; a first deterministic multi-threaded micro-controller controlling traffic through said first port; a second deterministic multi-threaded micro-controller controlling traffic through said second port; a third deterministic multi-threaded micro-controller controlling traffic through said third port; said first deterministic multi-threaded micro-controller comprises a first hardware thread allocated to manage incoming data packets on said first port and a second hardware thread allocated to manage outgoing data packets on said first port, each of said first and second hardware threads are managed in hardware such that each of said first and second hardware thread executes an instruction on alternating clock cycles: said second deterministic multi-threaded micro-controller comprises a first hardware thread allocated to manage incoming data packets on said second port and a second hardware thread allocated to manage outgoing data packets on said second port, each of said first and second hardware threads are managed in hardware such that each of said first and second hardware thread executes an instruction on alternating clock cycles: said third deterministic multi-threaded micro-controller comprises a first hardware thread allocated to manage incoming data packets on said first port and a second hardware thread allocated to manage outgoing data packets on third port each of said first and second hardware threads are managed in hardware such that each of said first and second hardware thread executes an instruction on alternating clock cycles; and said first deterministic multi-threaded micro-controller, said second deterministic multithreaded micro-controller, and said third deterministic multi-threaded micro-controller cooperatively operate to selectively communicate data packets between each of said first, second and third ports.