Patent ID: 9711464
Date: 2017-07-18
CPC Classifications: H01L,H05K

Claim:
1. An anti-reverse engineering semiconductor structure, comprising: a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, said first wiring level closest to said semiconductor substrate and said last wiring level furthest from said semiconductor substrate, said stack of wiring levels including an intermediate wiring level between said first wiring level and said last wiring level; active devices contained in said semiconductor substrate and said first wiring level, each wiring level of said stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from said intermediate wiring level, through said first wiring level into said semiconductor substrate; a liner on sidewalls and a bottom of said trench such that said trench comprises an open space; a cap sealing a top of said open space of said trench, wherein each of said liner and said cap is configured to be damaged during a reverse engineering process such that said trench is exposed to said at least one wiring level of said stack of wiring levels; and a chemical agent filling said open space of said trench, wherein said liner and said cap are chemically inert to said chemical agent, wherein portions of said at least one wiring level of said stack of wiring levels are not chemically inert to said chemical agent or a reaction product of said chemical agent, and wherein upon said liner or said cap being damaged during said reverse engineering process, said chemical agent is configured to damage wires, dielectric layers, dielectric materials, and said active devices of said at least one wiring level of said stack of wiring levels.