Patent ID: 9559715
Date: 2017-01-31
CPC Classifications: H03M

Claim:
1. A successive approximation register analog-to-digital converter to perform a sampling operation and a hold operation, the successive approximation register analog-to-digital converter comprising: a dual capacitor array configured to include a first capacitor array for converting most significant bits of n bits and a second capacitor array for converting least significant bits of the n bits; a comparator configured to compare a level signal outputted from the first capacitor array with a level signal outputted from the second capacitor array; an SAR logic circuit configured to convert an analog input voltage into a digital signal having the n bits by using the comparison result; and a first MOS switch and a second MOS switch configured to shift the analog input voltage sampled in the sampling operation, wherein the first capacitor array includes a 1-1 capacitor circuit and a 1-2 capacitor circuit and the second capacitor array includes a 2-1 capacitor circuit and a 2-2 capacitor circuit, and wherein each of the capacitor circuits includes capacitors connected in parallel each other.