Patent ID: 9747132
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. A multi-core processor comprising: a plurality of processor cores performing parallel processing of a plurality of tasks using a pipeline containing a plurality of stages, the pipeline being divided into a plurality of former-stage pipeline portion ending, respectively, with an a plurality of instruction decode stages, and one or more latter-stage pipeline portion starting, respectively, with an one or more instruction execution stage; a load distribution processing portion referring to decoded instructions in the instruction decode stages in the former-stage pipeline portions, and controlling, based on the decoded instructions, to assign at least one of the one or more latter-stage pipeline portions with a latter-stage-needed decoded instruction among the decoded instructions, the latter-stage-needed decoded instruction being a decoded instruction whose processing needs to use at least one of the one or more latter-stage pipeline portion portions; a plurality of queues provided to have one-to-one correspondence to the plurality of former-stage pipeline portions, each of the plurality of queues permitting each of the plurality of former-stage pipeline portions to execute tasks one by one; and a task information storage storing a task information table that holds (i) processing time information about a plurality of tasks and (ii) dynamic execution states about the plurality of tasks, wherein the load distribution processing portion refers to the task information table to perform distribution processing of a new task among the plurality of queues, wherein the one or more latter-stage pipeline portions includes a plurality of latter-stage pipeline portions, the load distribution processing portion is configured to control, based on the decoded instructions, to assign one of the plurality of latter-stage pipeline portions with one or more latter-stage-needed decoded instructions among the decoded instructions, the latter-stage-needed decoded instructions being decoded instructions whose processing needs to use the one or more latter-stage pipeline portions, the multicore processor further includes a latter-stage process distribution portion arranged in between (i) the plurality of former-stage pipeline portions following the plurality of queues having one-to-one correspondence to the plurality of former-stage pipelines portions and (ii) the plurality of latter-stage pipeline portions, the latter-stage process distribution portion being caused, based on the decoded instructions in the plurality of instruction decode stages in the plurality of former-stage pipeline portions, by the load distribution processing portion that refers to the task information table to assign one of the plurality of latter-stage pipeline portions with the one or more latter-stage-needed decoded instructions among the decoded instructions, to distribute the latter-stage-needed decoded instruction into the one of the plurality of latter-stage pipeline portions, and a first number of the plurality of former-stage pipeline portions that are configured to be followed by the latter-stage process distribution portion is different from a second number of the plurality of latter-stage pipeline portions, wherein the processing time information held by the task information table includes a remaining execution time and a processing limit time with respect to each of the plurality of task; and the load distribution processing portion calculates, with respect to each of the plurality of queues, a share of each of the plurality of tasks presently in a waiting state using a ratio of the remaining execution time to the processing limit time, and obtains a share total that totals the shares of the plurality of tasks; and the load distribution processing portion finds a minimum-shared queue that is the queue providing the share total that is minimum among the share totals of the plurality of queues, and assigns the found minimum-shared queue with a next new task, wherein the load distribution processing portion finds a high-shared queue that is the queue providing the share total that is high among the share totals of the plurality of queues, finds a low-shared queue that is the queue providing the share total that is low among the share totals of the plurality of queues, gives a high priority to a high-shared former-stage pipeline portion that is one former-stage pipeline portion among the plurality of former-stage pipeline portions corresponding to the high-shared queue in assigning first and second latter-stage pipeline portions among the plurality of latter-stage pipeline portions with first and second latter-stage-needed decoded instructions chosen from the one or more latter-stage-needed decoded instructions in the high-shared former-stage pipeline portion, gives a low priority to a low-shared former-stage pipeline portion that is one former-stage pipeline portion among the plurality of former-stage pipeline portions corresponding to the low-shared queue in assigning a third latter-stage pipeline portion, different from the first and second latter-stage pipeline portions, among the plurality of latter-stage pipeline portions with a third latter-stage-needed decoded instruction chosen from the one or more latter-stage-needed decoded instructions in the low-shared former-stage pipeline portion.