Patent ID: 9728641
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: forming an isolation feature in a substrate; forming a first gate stack and a second gate stack over the substrate; forming a first recess cavity and a second recess cavity in the substrate, wherein the first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack; growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, wherein a topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane; and etching the first epi material and the second epi material, wherein the topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane.