Patent ID: 9697137
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A method for managing a plurality of translation lookaside buffers, each translation lookaside buffer including a plurality of translation lookaside buffer entries from a page table stored in physical memory, and each translation lookaside buffer being associated with a corresponding processing element of a plurality of processing elements, the method comprising: maintaining a filter separate from the page table and separate from any of the translation lookaside buffers, the filter including a plurality of filter entries, each filter entry corresponding to a mapping between a virtual memory address and a physical memory address and including a presence indicator indicative which processing elements of the plurality of processing elements have the mapping present in their respective translation lookaside buffers; receiving a translation lookaside buffer invalidation instruction for a first mapping between a first virtual memory address and a first physical memory address; determining whether a first filter entry corresponding to the first mapping exists in the filter in response to receiving the translation lookaside buffer invalidation instruction; if the first filter entry exists in the filter, partitioning the plurality of processing elements into a first partition of zero or more processing elements that have the first mapping present in their translation lookaside buffers and a second partition of zero or more processing elements that do not have the first mapping present in their translation lookaside buffers based on the presence indicator of the first filter entry; sending the translation lookaside buffer invalidation instruction to the processing elements included in the first partition of processing elements; and suppressing sending of the translation lookaside buffer invalidation instruction to the processing elements included in the second partition of processing elements.