Patent ID: 9684466
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A semiconductor device comprising: a memory unit having a first memory without an error correcting function, a second memory with an error correcting function, and a plurality of access nodes for the first memory and the second memory; a plurality of buses coupled to the plurality of access nodes of the memory unit; a direct memory input circuit which performs control to write data supplied from outside the semiconductor device in the first memory without an error correcting function through a bus among the plurality of buses; and a plurality of data processing modules which each process a program and can asymmetrically access the memory unit through the plurality of buses other than the bus, wherein the first memory is an area to store primary data before data processing by the data processing modules, wherein the second memory is an area to store secondary data after data processing by the data processing modules, wherein the memory unit includes a plurality of memory local buses which are each used for a specific one of the access nodes and the first memory and the second memory are coupled to each of the memory local buses, wherein the direct memory input circuit which performs control to write data supplied from outside the semiconductor device in the first memory through a first memory local bus among the memory local buses, wherein one of the data processing modules is an accelerator specialized in processing of specific data, wherein one of the buses is an accelerator bus for coupling the accelerator to a second memory local bus among the memory local buses, wherein one of the buses is a global bus, wherein one of the data processing modules is a first data processing module and another one thereof is a second data processing module, wherein the global bus includes a first single master bus coupled to the first data processing module as one bus master, a second single master bus coupled to the second data processing module as one bus master, and a multi-master bus coupled to the accelerator and other bus masters as a plurality of bus masters, and wherein the multi-master bus, the first single master bus, and the second single master bus are each coupled to a third memory local bus and a fourth memory local bus other than the first memory local bus and the second memory local bus.