Patent ID: 9564231
Date: 2017-02-07
CPC Classifications: G11C

Claim:
1. A non-volatile memory device comprising: a common well configured to be biased at a bulk voltage; a memory array in said common well and comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising a pair of current-conduction regions, a control-gate region between the pair of current-conduction regions, and a control-gate terminal coupled to the control-gate region, with the control-gate terminal of a same row of memory cells being coupled together and biased at a respective control-gate voltage; and a control-gate decoder configured to select and bias the control-gate regions of the rows of memory cells and the respective control-gate terminals at the respective control-gate voltages; said control-gate decoder comprising a plurality of biasing wells and a plurality of driver blocks in the plurality of biasing wells, with each biasing well being separate and distinct from one another and having a respective driver block therein, said plurality of driver blocks configured to supply the respective control-gate voltages to the rows of the memory cells, each driver block comprising a plurality of MOSFET transistors configured to withstand an upper operating voltage limit, and said control-gate decoder is configured, during an erase operation in said memory array, to: