Patent ID: 9660028
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor device, the method comprising: forming a stack of nanowires/nano sheets on a substrate, the stack of nano sheets comprising a first layer of a first nanosheet material arranged on the substrate and a second layer of a second nanosheet material arranged on the first layer, a third layer of the first nanosheet material arranged on the second layer, and a fourth layer of the second nanosheet material arranged on the third layer; removing portions of the stack of nanosheets to form a nanosheet fin on the substrate; forming a first sacrificial gate on a first channel region of the nanosheet fin and a second sacrificial gate on a second channel region of the nanosheet fin; forming a first sacrificial spacer along sidewalls of the first sacrificial gate and the second sacrificial gate; removing exposed portions of the nanosheet fin; removing portions of the first nanosheet material to form cavities in the nanosheet fin; filling the cavities with a second sacrificial spacer; removing the first sacrificial spacer from along the sidewalls of the first sacrificial gate and the second sacrificial gate; depositing an insulator material over the substrate and the sidewalls of the first sacrificial gate and the second sacrificial gate; removing portions of the insulator material to form a spacer adjacent to sidewalls of the first sacrificial gate and the second sacrificial gate, and to expose fourth layer and the third layer; removing additional portions of the insulator material to expose portions of the second layer and the first layer, wherein the exposed portion of the second layer and the first layer are arranged under the second sacrificial gate; forming source/drain regions adjacent to the first sacrificial gate and the second sacrificial gate; and forming a gate stack over the first channel region and the second channel region.