Patent ID: 9673194
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor arrangement comprising: forming a trench in a substrate; forming a first implant region in sidewalls of the substrate that define the trench, in a surface of the substrate that defines a bottom of the trench, and in a first portion of a top surface of the substrate; filling the trench with a dielectric after the first implant region is formed to define a shallow trench isolation (STI) region; forming, after the first implant region is formed, a first gate structure on a second portion of the top surface of the substrate; forming, after the first implant region is formed, a second gate structure on a third portion of the top surface of the substrate, wherein the first portion is between the second portion and the third portion; and forming a second implant region in the first portion of the top surface of the substrate, wherein the first implant region in the first portion of the top surface of the substrate and the second implant region define a source/drain region that is shared by the first gate structure and the second gate structure.