Patent ID: 9748244
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first fin-shaped semiconductor layer on a substrate; a second fin-shaped semiconductor layer on the substrate; a first insulating film around the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer; a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer; a second pillar-shaped semiconductor layer on the second fin-shaped semiconductor layer, where a width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer; an n-type diffusion layer in an upper portion of the first fin-shaped semiconductor layer; a p-type diffusion layer in an upper portion of the second fin-shaped semiconductor layer; a first gate insulating film around the first pillar-shaped semiconductor layer; a first metal gate electrode around the first gate insulating film; a second gate insulating film around the second pillar-shaped semiconductor layer; a second metal gate electrode around the second gate insulating film; and a metal gate line connected to the first metal gate electrode and the second metal gate electrode and extending in a direction perpendicular to the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer.