Patent ID: 9679620
Date: 2017-06-13
CPC Classifications: G11C

Claim:
1. A memory device, comprising: a plurality of first sense amplifiers including a plurality of corresponding first input terminals, a plurality of second sense amplifiers including a plurality of corresponding second input terminals, the plurality of first and second sense amplifiers being suitable for amplifying data received through the respective plurality of first and second input terminals, and for outputting the amplified data which include first and second data outputted by the plurality of first sense amplifiers and third and fourth data outputted by the plurality of second sense amplifiers; a plurality of first pipe latches suitable for latching and outputting the first and second data at a specific interval; a plurality of second pipe latches suitable for latching and outputting the third and fourth data at a specific interval; and an input/output line coupled to the plurality of first and second pipe latches, suitable for outputting the first, second, third and fourth data.