Patent ID: 9660076
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A semiconductor memory device, comprising: a substrate; a plurality of conductive members provided on the substrate, the plurality of conductive members extending in a first direction, being separated from each other in a second direction, and including a metal, the first direction being parallel to an upper surface of the substrate, the second direction intersecting the first direction and being parallel to the upper surface of the substrate; a stacked body provided in each region between the conductive members, the stacked body including a plurality of insulating films and a plurality of electrode films, each of the plurality of insulating films and each of the plurality of electrode films being stacked along a third direction, the third direction intersecting the upper surface of the substrate; a semiconductor pillar extending in the third direction and piercing the stacked body; a memory film provided between the semiconductor pillar and one of the electrode films; and a plurality of internal stress films extending in the first direction, being separated from each other in the second direction, and including a material having internal stress having the reverse polarity of internal stress of the metal, the internal stress films being disposed above the conductive members and above the stacked bodies.