Patent ID: 9590066
Date: 2017-03-07
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor construction, comprising: a silicon-containing semiconductor base; a gate extending into the silicon-containing semiconductor base; a first region of the silicon-containing semiconductor base adjacent the gate being a conductively-doped source region, and a second region of the silicon-containing semiconductor base adjacent the gate and spaced from the first region being a conductively-doped drain region; a gate dielectric comprising a first segment between the conductively-doped source region and the gate, a second segment between the conductively-doped drain region and the gate, and a third segment between the first and second segments; wherein at least a portion of the gate dielectric comprises ferroelectric material; wherein the gate dielectric, along a cross-section, is configured as an upwardly-opening container having the gate therein; wherein the first segment of the gate dielectric comprises a first leg of the upwardly-opening container, the second segment of the gate dielectric comprises a second leg of the upwardly-opening container, and the third segment of the gate dielectric comprises a bottom of the upwardly-opening container; wherein at least a portion of the gate dielectric comprises a first material as an outer boundary of the upwardly-opening container and which is directly against the silicon-containing semiconductor base, and comprises a second material between the first material and the gate; wherein the second material is the ferroelectric material; wherein the first material is a non-ferroelectric material; and wherein the ferroelectric material is only within the first segment.