Patent ID: 9716062
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A three-dimensional memory device, comprising: alternating stacks of word lines and insulating layers located in a device region over a major surface of the substrate, wherein an entirety of each word line and each insulating layer in the alternating stacks extend substantially parallel to the major surface of the substrate; backside trenches, wherein each of the alternating stacks is laterally spaced apart from one another by the backside trenches that vertically extend from a bottommost level of the alternating stacks to a topmost level of the alternating stacks; a respective array of memory structures located in the device region between each neighboring pair of the backside trenches, wherein each array of memory structures includes a respective set of multiple rows of memory structures; an insulating fill layer, wherein a respective first insulating material portion of the insulating fill layer is located over each first stepped word line contact region such that a bottom surface of each first portion of the insulating fill layer provides a respective first terrace structure;