Patent ID: 9548118
Date: 2017-01-17
CPC Classifications: G11C

Claim:
1. A device comprising: a plurality of non-volatile memory elements connected in series, the plurality of non-volatile memory elements being operable to: store a first symbol or value in a first mode wherein at least a first of the non-volatile memory elements is in a first impedance state and at least a second of the non-volatile memory elements is in a second impedance state; store a second symbol or value in a second mode wherein at least the second of the non-volatile memory elements is in the first impedance state and at least the first non-volatile memory element is in the second impedance state; the device further comprising: an input circuit to place the plurality of non-volatile memory elements in the first mode or the second mode based, at least in part, on a data value of an input signal, wherein the input circuit comprises a conducting element to apply a voltage based on the input signal to a first terminal of the first of the non-volatile memory elements and a first terminal of the second of the non-volatile memory elements in response to a first periodic voltage signal; and an output circuit to generate an output signal based, at least in part, on a current mode of the plurality of non-volatile memory elements and synchronized with the input signal.