Patent ID: 9673228
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A display panel, comprising: a substrate; a first metal layer on the substrate, wherein the first metal layer includes a gate electrode and a gate line connecting to the gate electrode; a first insulation layer on the first metal layer; a planarization layer on the first insulation layer; an opening defined by sidewalls of the planarization layer and a surface of the first insulation layer, wherein the opening overlaps the gate electrode; an active layer on the planarization layer and covering the opening; and a second metal layer on the active layer, wherein the second metal layer includes a source electrode contacting the active layer and a data line connecting to the source electrode, wherein the planarization layer and the first insulation layer are disposed between the data line and the gate line, an etch stop layer on the active layer and the planarization layer, wherein the etch stop layer includes a plurality of contact vias to expose parts of the active layer on the opening, the source electrode contacts the active layer through one of the contact vias, and the etch stop layer, the planarization layer, and the first insulation layer are disposed between the data line and the gate line; a second insulation layer on the planarization layer, wherein the active layer is disposed on the second insulation layer, and the etch stop layer, the second insulation layer, the planarization layer, and the first insulation layer are disposed between the data line and the gate line.