Patent ID: 9734879
Date: 2017-08-15
CPC Classifications: G11C,H01L

Claim:
1. A first memory device, comprising: a set of data interfaces, wherein each data interface in the set of data interfaces corresponds to a contiguous set of conducting regions; a set of memory banks; a data interface selection circuit that (1) selects one or more data interfaces in the set of data interfaces as active data interfaces, and (2) routes electrical signals between the set of memory banks and the contiguous sets of conducting regions corresponding to the active data interfaces; and wherein the first memory device is part of a stack of at least two dies, wherein the first memory device and a second memory device are arranged in a clamshell configuration in the stack of at least two dies, and wherein the first memory device and the second memory device are disposed in the clamshell configuration such that each data interface in the first memory device is substantially aligned with a corresponding data interface in the second memory device along a perpendicular direction with respect to the at least two dies.