Patent ID: 9620536
Date: 2017-04-11
CPC Classifications: G02F,H01L

Claim:
1. A low temperature poly-silicon (LTPS) array substrate, comprising a plurality of LTPS thin-film transistors, a bottom transparent conductive layer, a protective layer formed on the bottom transparent conductive layer, and a top transparent conductive layer formed on the protective layer, each of the LTPS thin-film transistors comprising a substrate; a patternized light shield layer formed on the substrate; a buffering layer formed on the substrate and the patternized light shield layer; a patternized poly-silicon layer formed on the buffering layer; a gate insulation layer formed on the patternized poly-silicon layer and the buffering layer; a first metal layer formed on the gate insulation layer, the first metal layer being patternized to form a scan line, the scan line having an orthogonal projection cast on the light shield layer; an insulation layer formed on the patternized first metal layer; a second metal layer formed on the insulation layer, the second metal layer being patternized to form a data line and a source/drain electrode, the data line and the scan line being arranged to intersect each other; a planarization layer formed on the insulation layer and the patternized second metal layer, the bottom transparent conductive layer being formed on the planarization layer, wherein: the patternized light shield layer covers the scan line and the source/drain electrode, a patternized third metal layer being formed between the bottom transparent conductive layer and the protective layer, the patternized third metal layer comprises a first zone and a second zone arranged to intersect the first zone, the first zone shielding the data line, the second zone having a portion overlapping a side portion of the light shield layer that is close to the source/drain electrode so as to shield, in combination with the light shield layer, the source/drain electrode and a portion of the scan line.