Patent ID: 9589608
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A device comprising: a plurality of bit lines each extending in a first direction, the bit lines being arranged substantially in parallel to one another in a second direction crossing the first direction so that the bit lines include odd-numbered bit lines and even-numbered bit lines in the second direction; a plurality of memory elements each coupled to an associated one of the odd-numbered and even-numbered bit lines; a reference line; a first sense amplifier including first and second input terminals, the second input terminal being coupled to the reference line; a second sense amplifier including third and fourth input terminals, the fourth input terminal being coupled to the reference line; a plurality of first switches each including first and second nodes, the first nodes of the first switches being coupled in common to the first input terminal of the first sense amplifier, and the second nodes of the first switches being coupled to the odd-numbered bit lines, respectively; a plurality of second switches each including third and fourth nodes, the third nodes of the second switches being coupled in common to the third input terminal of the second sense amplifier, and the fourth nodes of the second switches being coupled to the even-numbered bit lines, respectively; a voltage line; a third switch coupled between the voltage line and the first input terminal of the first sense amplifier; and a fourth switch coupled between the voltage line and the third input terminal of the second sense amplifier.