Patent ID: 9748281
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor device, comprising: forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer; forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including an intrinsic layer, a doped layer, and a third sacrificial layer, the intrinsic layer directly contacting the second portion of the semiconductor material; etching the first sacrificial layer to create a first contact region within the first gate structure; etching the third sacrificial layer to create a second contact region within the second gate structure; and forming silicide in the first and second contact regions of the first and second gate structures, respectively.