Patent ID: 9728553
Date: 2017-08-08
CPC Classifications: G01R,G06F,H01L

Claim:
1. A monolithic integrated circuit (IC) that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, a gate contact (GATECNT) layer, a via to interconnect stack (V0) layer, a first wiring (M1) layer, a second wiring (M2) layer, and an M1-to-M2 via (V1) layer, said IC comprising at least: (i) a plurality of logic cells selected from a standard cell library in which each logic cell has a height configured for abutted instantiation with other logic cells in the library, supply rail configuration configured for abutted instantiation with other logic cells in the library, and GATE pitch (CPP) configured for abutted instantiation with other logic cells in the library; and, (ii) a plurality of at least four different, non-contact electrical measurement (NCEM)-enabled fill cells, each of said NCEM-enabled fill cells having a height configured for abutted instantiation with logic cells in the library, supply rail configuration configured for abutted instantiation with logic cells in the library, and CPP configured for abutted instantiation with logic cells in the standard cell library, said plurality of NCEM-enabled fill cells including: