Patent ID: 9690146
Date: 2017-06-27
CPC Classifications: G02F,H01L

Claim:
1. A method for manufacturing an array substrate, comprising a step of: forming, on a substrate, a common electrode with a slit structure, and a pixel electrode with a slit structure not overlapping the common electrode, wherein the step of forming, on the substrate, the common electrode with the slit structure, and the pixel electrode with the slit structure not overlapping the common electrode comprises: forming a gate electrode, a gate insulating layer, a semiconductor layer and a source/drain electrode on the substrate; forming patterns of a protective layer and a passivation layer with slit structures on the substrate formed with the gate electrode, the gate insulating layer, the semiconductor layer and the source/drain electrode; and forming a transparent conductive film on the substrate formed with the patterns of the protective layer and the passivation layer, the transparent conductive film being used to form the common electrode with the slit structure located on the protective layer and the pixel electrode located at a slit region in the slit structures of the protective layer and the passivation layer, the pixel electrode being directly lapped onto the drain electrode.