Patent ID: 9568905
Date: 2017-02-14
CPC Classifications: G05B

Claim:
1. A central processing unit (CPU) of a programmable logic controller (PLC) controlling a control target, the CPU comprising: a microprocessor; a memory having a main memory of the microprocessor; a first communication circuit transmitting first output data and receiving first input data with a PLC system bus; and a second communication circuit transmitting second output data and receiving second input data with a field network, wherein the CPU of the PLC is configured to control the control target by repeating transmission of the first output data and the second output data, reception of the first input data and the second input data, and execution of a control program that uses the first input data and the second input data to generate the first output data and the second output data, the memory is used for storage of the control program and a system program, the microprocessor executes the system program and the control program stored in the memory, the system program includes a command generating, in the main memory, a calculation buffer in which, accompanying execution of the control program, the first input data and the second input data are read and the first output data and the second output data are written; a first transfer buffer storing the first output data transmitted by the PLC system bus and the first input data received by the PLC system bus; and a second transfer buffer storing the second output data transmitted by the field network and the second input data received by the field network, the system program further includes a command controlling execution of the control program and a command controlling input/output of the first input data, the second input data, the first output data, and the second output data, the microprocessor controls, by executing the system program, execution of: the microprocessor controls, by executing the system program, at least one of the first communication circuit and the second communication circuit such that a first input/output process and a second input/output process are executed in parallel, wherein