Patent ID: 9734272
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. A computer program product for producing a physical representation of an in silico integrated circuit (IC) having an in silico multi-mode redundant (MMR) pipeline circuit, the computer program product stored on a non-transitory computer-readable storage medium and including instructions to cause a processor device to: load a gate-level netlist of the in silico IC into an electronic design automation (EDA) program; generate an IC layout of the in silico IC based on the gate-level netlist with the EDA program, wherein the IC layout has an MMR pipeline circuit layout of the in silico MMR pipeline circuit, and the MMR pipeline circuit layout includes initial redundant combinational logic circuit (CLC) layouts and multi-mode redundant self-correcting sequential state element (MMRSCSSE) layouts; render the MMRSCSSE layouts immotile within the IC layout; remove the initial redundant CLC layouts of the MMR pipeline circuit layout from the IC layout; and place updated redundant CLC layouts in the MMR pipeline circuit layout based on the gate-level netlist with the EDA program after the MMRSCSSE layouts have been rendered immotile.