Patent ID: 9590060
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. An enhancement-mode transistor, comprising: a III-N structure including a conductive channel therein; a source contact and a drain contact, the source and drain contacts electrically contacting the conductive channel; a gate electrode positioned between the source and drain contacts; an insulator layer over the III-N structure, wherein a first recess is formed through the insulator layer in a gate region of the III-N enhancement-mode transistor, the first recess comprising a first bottom surface, and wherein the gate electrode is at least partially in the first recess; an electrode defining layer having a thickness, the electrode defining layer being over the insulator layer, wherein a second recess is formed through a portion of the electrode defining layer, the second recess comprising a second bottom surface, wherein the first bottom surface of the first recess has a first edge and a second edge, the first edge being between the source contact and the second edge, and wherein the second bottom surface of the second recess has a third edge and a fourth edge, the third edge being between the source contact and the fourth edge; and a field plate having a portion that is in the second recess, the field plate being electrically connected to the source contact, wherein the third edge of the second bottom surface is between the second edge of the first bottom surface and the drain contact.