Patent ID: 9569222
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A system for implementing an enhanced out of order processor instruction issue queue comprising: a processor; an instruction issue queue coupled to said processor; queue entry logic coupled to each queue entry of said instruction issue queue for selectively accepting instructions; a queue counter coupled to said instruction issue queue for assigning ages to the accepted queue entry instructions; issue logic including a series of levels of multiplexers coupled to said instruction issue queue for selectively issuing a queue entry instruction from the instruction issue queue based upon resources being ready and ages of the instructions; and selectively decrementing ages of the queue entry instructions and decrementing the queue counter, responsive to issuing the instruction; and said instruction issue queue includes a first compare comparing respective entries from a respective level of multiplexers, and providing a select input to a next level multiplexer providing a feed back age input to a second compare comparing age of the issuing instruction with ages of queue entry instructions, and providing an input to a decrement, said decrement ages of the queue entry instructions younger than the issuing instruction.