Patent ID: 9659978
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method for manufacturing an array substrate, the array substrate includes a gate driver on array (GOA) circuit area which includes a thin film transistor (TFT) area for outputting a gate row-driving signal and a lead-wire area connected to the TFT area, and a display area which includes a data line and a gate line which are arranged crosswise; wherein the GOA circuit area further includes a first electrode and a second electrode, the method comprising: forming a resin layer having a first via on a substrate on which the TFT area is formed such that the first via penetrates through the resin layer to expose a data-line metal layer of the TFT area; forming a first electrode on the surface of the resin layer such that the first electrode is electrically connected to the data-line metal layer through the first via; forming a passivation layer having a second via on the substrate on which the first electrode is formed such that the second via penetrates through the passivation layer, the resin layer, and a gate-insulating layer of the TFT area to expose a gate-line metal layer of the TFT area; and forming a second electrode on the surface of the passivation layer such that the second electrode is electrically connected to the gate-line metal layer through the second via, to form a capacitor between the first electrode and the second electrode.