Patent ID: 9590040
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method, comprising: forming a sacrificial fin structure on a surface of a semiconductor substrate; forming a layer of insulating material around said sacrificial fin structure; performing at least one etching process to remove said sacrificial fin structure and thereby define a replacement fin cavity in said layer of insulating material that exposes an upper surface of said substrate; performing an isotropic etching process through said replacement fin cavity to remove portions of said substrate and thereby define a recess in said substrate under said replacement fin cavity that is wider than a width of said replacement fin cavity; forming a replacement fin in said recess and in said replacement fin cavity on said exposed upper surface of said substrate; recessing said layer of insulating material so as to thereby expose at least an upper portion of said replacement fin; and forming a gate structure around at least a portion of said replacement fin exposed above said recessed layer of insulating material.