Patent ID: 9548289
Date: 2017-01-17
CPC Classifications: H01L,H05K

Claim:
1. A semiconductor package assembly, comprising: a system-on-chip (SOC) package, comprising: a logic die having first pads thereon; a first redistribution layer (RDL) structure coupled to the logic die; and a molding compound surrounding the logic die, being in contact with the first RDL structure and the logic die; and a dynamic random access memory (DRAM) package stacked on the SOC package, comprising: a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface; and a dynamic random access memory (DRAM) die mounted on the die-attach surface, coupled to the body through the bonding wires, wherein one of the SOC package and the DRAM package further comprises an additional dynamic random access memory (DRAM) die embedded therein, wherein the additional DRAM die has through silicon via (TSV) interconnects formed through the additional DRAM die, wherein the additional DRAM die is embedded in the SOC package, coupled to first vias on the first semiconductor die and the first RDL structure, wherein the DRAM package is coupled to the first RDL structure of the SOC package by second vias passing through the molding compound between the DRAM package and the first RDL structure, and wherein the logic die is surrounded by the second vias.