Patent ID: 9710359
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. Apparatus for processing data comprising: a processing pipeline configured to execute a sequence of program instructions; a debug interface configured to receive debug command signals corresponding to debug program instructions to be executed; instruction buffer circuitry configured to store both said debug program instructions and non-debug program instructions; an arbiter coupled to said instruction buffer and configured to arbitrate between both said debug program instructions and said non-debug program instructions stored within said instruction buffer to select said sequence of program instructions to be executed by said processing pipeline; memory system circuitry configured to process memory access program instructions for accessing at least one of stored values within a memory and memory mapped devices, wherein said memory system circuitry is shared by both said debug program instructions and said non-debug program instructions executed by said processing pipeline, wherein said memory system circuitry comprises coherency control circuitry coupled to said processing pipeline and configured to maintain memory coherency for access operations to said memory system circuitry; wherein the apparatus comprises a plurality of memories and said coherency control circuitry is configured to track which of said plurality of memories are storing a most up-to-date stored value corresponding to a given memory address within a memory address space.