Patent ID: 9536791
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of forming a multiple threshold voltage transistor structure, the method comprising: forming at least one narrow channel and at least one long channel on a fin, the fin being deposited on a substrate, wherein spacers on the fin define the at least one narrow channel and the at least one long channel, wherein an epitaxial layer is formed on the fin, and wherein an interlayer dielectric layer is formed on the epitaxial layer; depositing a high-k dielectric material in the at least one narrow channel and the at least one long channel; depositing a metal layer on the high-k dielectric material in the at least one narrow channel and the at least one long channel; recessing a height of the high-k dielectric material in the at least one narrow channel, after performing a protective process to protect the at least one long channel; removing the metal layer from the at least one narrow channel and the at least one long channel; depositing a work function metal in the at least one narrow channel and the at least one long channel; depositing a gate conduction metal to fill the at least one narrow channel and the at least one long channel; and depositing a capping layer on a top surface of the spacers, the interlayer dielectric layer, the work function metal, and the gate conduction metal.