Patent ID: 9640643
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a transistor region in which an insulated gate bipolar transistor having a gate electrode and an emitter electrode is provided; a termination region arranged around the transistor region; and a PN junction region arranged between the transistor region and the termination region, wherein an N type buffer layer is provided below an N type drift layer in the transistor region and the termination region, a first P type collector layer is provided below the N type buffer layer in the transistor region, a second P type collector layer is provided below the N type buffer layer in the termination region, a collector electrode is connected to the first and second P type collector layers, and a peak impurity concentration of the second P type collector layer is higher than a peak impurity concentration of the N type drift layer and lower than a peak impurity concentration of the N type buffer layer, and wherein a first P type layer is provided on the N type drift layer in the PN junction region, a gate wiring is provided on the first P type layer via an insulating film, the gate wiring is connected to the gate electrode, and the first P type collector layer and the second P type collector layer have a same, substantially uniform, thickness in both the transistor region and the termination region.