Patent ID: 9685376
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A semiconductor device including: a support plate having a thickness of no more than 50 μm; a semiconductor chip mounted on a principal surface of the support plate via an adhesive layer, with an element circuit surface of the chip being directed upward; an insulation material layer that seals the semiconductor chip and a periphery of the semiconductor chip; openings formed on an electrode arranged on the element circuit surface of the semiconductor chip in the insulation material layer; conductive portions formed in the openings so as to be connected to the electrode of the semiconductor chip; a wiring layer formed on the insulation material layer so as to be connected to the conductive portions and partially extending to a peripheral region of the semiconductor chip; and external electrodes formed on the wiring layer, wherein the support plate is a flat plate that has the semiconductor chip mounted thereon and is separated from other flat plates that constitute a combined support plate, the flat plate constituting the combined support plate in which the plurality of flat plates used in a process of manufacturing the semiconductor device is laminated to each other, the adhesive layer is present on the support plate only where the semiconductor chip is mounted; and the semiconductor device is free from warpage.