Patent ID: 9685236
Date: 2017-06-20
CPC Classifications: G06F,G11C

Claim:
1. A storage device comprising: a first nonvolatile semiconductor memory chip; and a controller circuit configured to access the first nonvolatile semiconductor memory chip, wherein the first nonvolatile semiconductor memory chip sets a parameter therein in accordance with an instruction from the controller circuit, and sets an operation mode thereof to one of first and second modes indicated by the parameter, the controller circuit sends to the first nonvolatile semiconductor memory chip a first request for reading from a first address, if the first nonvolatile semiconductor memory chip is in the first mode, the first nonvolatile semiconductor memory chip is capable of performing a first read operation in response to the first request and outputting a first busy signal to the controller circuit during the first read operation, if the first nonvolatile semiconductor memory chip is in the second mode, the first nonvolatile semiconductor memory chip is capable of performing a second read operation in response to the first request and outputting a second busy signal to the controller circuit during the second read operation, a period of the first busy signal is shorter than a period of the second busy signal, the first nonvolatile semiconductor memory chip outputs first data to the controller circuit, and after the outputting the first data, the first nonvolatile semiconductor memory chip keeps staying in the operation mode indicated by the parameter at the time of the receiving the first request, until the parameter is changed.