Patent ID: 9570618
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A thin-film transistor (TFT) substrate manufacturing method, comprising the following steps: (1) providing a substrate and sequentially depositing a buffer layer and an amorphous silicon layer on the substrate; (2) subjecting the amorphous silicon layer to excimer laser annealing or solid phase crystallization to convert the amorphous silicon layer into a low temperature poly-silicon layer and applying a photolithographic process to pattern the low temperature poly-silicon layer to form a first active layer and a second active layer that are spaced from each other; (3) coating a photoresist layer on the first active layer, the second active layer, and the substrate, subjecting the photoresist layer to exposure and development to expose two end portions of the first active layer, using the photoresist layer as a shielding layer to subject the two end portions of the first active layer to injection of N-type or P-type ion so as to form a first source contact zone and a first drain contact zone respectively at the two end portions of the first active layer; and defining a zone between the first source contact zone and the first drain contact zone as a first channel zone; (4) subjecting the photoresist layer to ashing and partly etching off the first source contact zone and the first drain contact zone of the first active layer in such a way that heights of the first source contact zone and the first drain contact zone are both less than a height of the first channel zone; (5) peeling off the photoresist layer, depositing a gate insulation layer on the first active layer, the second active layer, and the substrate, depositing a first metal layer on the gate insulation layer, applying a photolithographic process to pattern the first metal layer in order to form a first gate terminal and a second gate terminal respectively located above and corresponding to the first active layer and the second active layer; (6) coating a photoresist layer on the first gate terminal and the second gate terminal and subjecting the photoresist layer to exposure and development to expose the second gate terminal and a portion of the gate insulation layer corresponding to the second active layer; using the second gate terminal as a shielding layer to subject two end portions of the second active layer to injection of P-type or N-type ion to form a second source contact zone and a second drain contact zone respectively at the two ends of the second active layer; defining a zone between the second source contact zone and the second drain contact zone as a second channel zone; (7) peeling off the photoresist layer, depositing an interlayer dielectric layer on the first gate terminal and the second gate terminal, and the gate insulation layer, applying a photolithographic process to pattern the interlayer dielectric layer and the gate insulation layer to form, in the interlayer dielectric layer and the gate insulation layer, first vias respectively corresponding to the first source contact zone and the first drain contact zone and second vias respectively corresponding to the second source contact zone and the second drain contact zone; (8) depositing a second metal layer on the interlayer dielectric layer and applying a photolithographic process to pattern the second metal layer so as to form a first source terminal, a first drain terminal, a second source terminal, and a second drain terminal, wherein the first source terminal and the first drain terminal are respectively connected through the first vias to the first source contact zone and the first drain contact zone and the second source terminal and the second drain terminal are respectively connected through the second vias to the second source contact zone and the second drain contact zone; (9) coating a planarization layer on the first source terminal, the first drain terminal, the second source terminal, the second drain terminal, and the interlayer dielectric layer and depositing a passivation layer on the planarization layer and applying a photolithographic process to pattern the planarization layer and the passivation layer to form a third via in the planarization layer and the passivation layer to correspond to the second drain terminal; and (10) depositing a transparent conductive semiconductor layer on the passivation layer and applying a photolithographic process to pattern the transparent conductive semiconductor layer to form a pixel electrode, wherein the pixel electrode is connected through the third via to the second drain terminal thereby completing the manufacture of a TFT substrate.