Patent ID: 9638972
Date: 2017-05-02
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a base substrate, gate scanning lines located on the base substrate, a gate-insulating layer located on the gate scanning lines, an active layer located on the gate-insulating layer, data lines located on the active layer, a passivation layer located over the data lines, pixel electrodes located on the passivation layer; wherein the array substrate further comprises: a bridge structure and a connection line corresponding to each data line; and wherein the bridge structure is located on the passivation layer and is provided in a same layer as the pixel electrodes; and each connection line is located on the base substrate, and each connection line is connected with the data line, through the bridge structure in an LED region and in a region under a scribe line of a counter substrate, wherein the bridge structure is contacted with the connection line and the data line, respectively.