Patent ID: 9639364
Date: 2017-05-02
CPC Classifications: G06F

Claim:
1. A method for managing mappings of storage on a code cache for a processor, comprising: storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, wherein the guest addresses reference guest instruction blocks comprising instructions from a guest instruction architecture and the corresponding converted native addresses reference native conversion blocks comprising instructions from a native instruction architecture; receiving a subsequent request for a guest address at the conversion look aside buffer; indexing the conversion look aside buffer using at least one guest address of a guest instruction block to determine whether there exists an entry in the conversion look aside buffer that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index; upon a hit on the tag, accessing the corresponding entry to retrieve a pointer, wherein the pointer is operable to index the code cache memory and wherein the pointer indicates where in the code cache memory a corresponding block of converted native instructions reside; and fetching the corresponding block of converted native instructions from the code cache memory for execution.