Patent ID: 9537469
Date: 2017-01-03
CPC Classifications: H03K

Claim:
1. A digital level shifter adapted to shift an input signal from switching between a low voltage and the low voltage less a first offset voltage, to an output switching between a high voltage and a voltage equal to the high voltage less a second offset voltage, the high voltage being greater than the low voltage, comprising: a glitch generator configured to generate pulses at rising and falling transitions of the input signal; a multiple-level current source configured to provide a high current during the pulses from the glitch generator, and a low current at other times; a differential pair of high voltage transistors having sources coupled to the multiple-level current source, with a first transistor of the pair having a gate coupled to the input signal and a second transistor of the pair having a gate coupled to a complement of the input signal; an active load and buffer circuit, the active load powered by the high voltage and configured to drive the output to the high voltage when the input signal has a first value, and to drive the output to the voltage equal to the high voltage less the second offset when the input signal has a second value.