Patent ID: 9548379
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method of fabricating an asymmetrical semiconductor device, the method comprising: forming at least one semiconductor fin on an upper surface of a semiconductor substrate, the at least one fin extending along a length of the semiconductor substrate to define a fin length and having a first fin area reserved for a first source/drain region and a second fin area reserved for a second source/drain region opposite the second fin area, forming, on the upper surface of the semiconductor substrate, a plurality of gate structures that wrap around the sidewalls and upper fin surface of the at least one semiconductor fin, the plurality of gate structures including at least one desired gate structure surrounded by at least one sacrificial gate structure; selectively removing the at least one sacrificial gate structure so as to increase the first fin area with respect to the second fin area; forming asymmetrical gate spacers on opposing sidewalls of the desired gate structure; and implanting dopants in the first and second fin areas, wherein the asymmetrical gate spacers control a lateral diffusion of the dopants along the fin length so as to form asymmetrical first and second source/drain regions, wherein selectively removing the at least one sacrificial gate structure comprises: forming a transfer layer atop the substrate so as to cover the at least one fin and the plurality of gate structures; forming a mandrel layer atop the transfer layer, and patterning the mandrel layer to form at least one mandrel that covers the at least one desired gate structure while the at least one sacrificial gate structure is not covered by a mandrel; and performing a directional etch process that removes the transfer layer and the at least one sacrificial fin, while the at least one mandrel preserves the desired gate structure.