Patent ID: 9582273
Date: 2017-02-28
CPC Classifications: G06F,H04N

Claim:
1. A digital signal processor comprising: a data register file including a plurality of data registers storing data, each data register designated by a corresponding register number; an instruction memory storing instructions each specifying a data processing operation and at least one data operand by register number; an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand; an operational unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder, said data processing operations including performing a sum of absolute differences (SAD) operation comprising two sets of a plurality of rows, each row producing a SAD output and including wherein said operational unit includes a first mode forming 2M SADs from N bit pixel data and a second mode forming M SADs from 2N bit pixel data, said first mode and said second mode selected by carry chain control in said absolute value difference units and said row summers; and wherein a first set of a plurality of rows operates on pixel data in a first half of said first instruction specified data register and a second set of a plurality of rows operates on pixel data in a second half of said first instruction specified data register.