Patent ID: 9666641
Date: 2017-05-30
CPC Classifications: G11C,H01L

Claim:
1. A compact three-dimensional memory (3D-M C ) comprising at least a first memory level stacked above a semiconductor substrate with transistors thereon, said first memory level comprising: a continuous and conductive first x-line; a contact via coupling said first x-line with said semiconductor substrate; a continuous and conductive y-line intersecting said first x-line at a first intersection, at least the portion of said first x-line at said first intersection comprising a heavily doped semiconductor material, wherein a first memory device is formed at said first intersection; a continuous and conductive first control line intersecting said first x-line at a second intersection, the portion of said first x-line at said second intersection comprising a lightly doped semiconductor material, wherein a first switching device is formed at said second intersection, said first switching device is located between said first memory device and said contact via; wherein said first switching device is configured to block current conduction in said first x-line in a first mode and allow current conduction in said first x-line in a second mode.