Patent ID: 9559040
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method, comprising: forming one or more intra-wafer through substrate vias (TSVs) extending from a front side of a substrate of a first integrated circuit (IC) chip to a back side of the substrate of the first IC chip; forming a local architecture in a front side wiring layer of the first IC chip, the local architecture having one or more local features electrically connected to the one or more intra-wafer TSVs; forming a global architecture in a back side wiring layer of the first IC chip, the global architecture connecting to the one or more intra-wafer TSVs and electrically coupling the one or more local features together; bonding the first IC chip to a second IC chip, the second IC chip comprising a front side wiring layer and a back side wiring layer; and forming one or more inter-wafer TSVs after bonding the first IC chip to the second IC chip, the one or more inter-wafer TSVs extending through an entire thickness of a periphery of the first IC chip and an entire thickness of a periphery of the second IC chip, the one or more inter-wafer TSVs electrically connecting the back side wiring layer of the second IC chip to the back side wiring layer of the first IC chip, the one or more inter-wafer TSVs having a width that is approximately n times larger than a width of the one or more intra-wafer TSVs, with the value of n being selected to reduce the number of repeaters required for distributing global signals, and n varying between approximately 8 and approximately 10.