Patent ID: 9728490
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate; a via structure in the substrate, wherein a portion of the via structure extends past a surface of the substrate; a protection layer pattern structure on the surface of the substrate, wherein the protection layer pattern includes a first protection layer pattern and a second protection layer pattern on the first protection layer pattern, the first protection layer pattern surrounding a lower sidewall of a protruding portion of the via structure from the surface of the substrate, the second protection layer pattern being spaced apart from the protruding portion of the via structure by a predetermined distance; a pad structure on the via structure and the protection layer pattern structure, wherein the pad structure covers a portion of a top surface of the first protection layer pattern; and a seed pattern disposed between the via structure and the pad structure, between the top surface of the first protection layer pattern and the pad structure, or between the second protection layer pattern and the pad structure, wherein the pad structure laterally overlaps the first and second protection layer patterns by a first distance and the seed pattern laterally overlaps the first and second protection layer patterns by a second distance that is less than the first distance, and wherein the via structure comprises: a via hole in the substrate; a via electrode in the via hole, the via electrode including a conductive pattern and a barrier pattern on a sidewall of the conductive pattern; and an insulation layer pattern in the via hole surrounding the via electrode, wherein the insulation layer pattern is between the via electrode and the substrate.