Patent ID: 9602401
Date: 2017-03-21
CPC Classifications: H03M,H04L

Claim:
1. A network interface circuit for high-speed data transmission, the network interface circuit comprising network port logic including: a physical coding sublayer (PCS) logic to (i) encode first data to be transmitted into first encoded data blocks using a 66 b/64 b line code; and (ii) insert an alignment marker block into the first encoded data blocks after every first integer number of encoded data blocks to generate first aligned data blocks at a first PCS lane speed; and a forward error correction (FEC) logic to encode the first aligned data blocks into first FEC codewords that each start at a predefined offset from an alignment marker block of the first aligned data blocks, wherein each of the first FEC codewords includes a second number of aligned data blocks and wherein the first integer number of encoded data blocks plus one and the second number of aligned data blocks have a greatest common divisor greater than one.