Patent ID: 9620369
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device comprising: providing a dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer, wherein a top surface of the poly-silicon gate electrode and a top surface of the poly-silicon element layer are coplanar; forming a first spacer on sidewalls of two opposite sides of the dummy gate; forming a second spacer on sidewalls of two opposite sides of the passive device; after forming the first spacer and the second spacer, forming a hard mask layer conformally on the first spacer, the second spacer, the dummy gate and the passive device; performing a first etching process to remove a portion of the hard mask layer and a portion of the poly-silicon element layer to form a recess in the passive device exposing a remaining portion of the poly-silicon element layer; forming an inner layer dielectric (ILD) on the dummy gate and the poly-silicon element layer; flattening the ILD by using the hard mask layer as a polish stop layer; performing a second etching process to remove the poly-silicon gate electrode; and forming a metal gate electrode on the location where the poly-silicon gate electrode was initially disposed.