Patent ID: 9634017
Date: 2017-04-25
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor structure, comprising: a nonvolatile memory cell comprising a first nonvolatile bit storage element and a second nonvolatile bit storage element, said first and second nonvolatile bit storage elements having a common source region provided in a semiconductor material and a common control gate structure, each of said first and second nonvolatile bit storage elements comprising: a drain region and a channel region provided in said semiconductor material, said channel region having a select gate side portion and a floating gate side portion; a select gate structure at said select gate side portion of said channel region; a floating gate structure at said floating gate side portion of said channel region; and an erase gate structure above said select gate structure and adjacent said floating gate structure; wherein said floating gates for said first and second nonvolatile bit storage elements are separated by an isolation region, said floating gates for said first and second nonvolatile bit storage elements isolation structure have coplanar upper surfaces, and said common control gate structure is disposed on said coplanar upper surfaces and extends above said floating gate structures of said first and second nonvolatile bit storage elements.