Patent ID: 9594683
Date: 2017-03-14
CPC Classifications: G06F

Claim:
1. A data processing system comprising: at least one page mover positioned closer to a main memory of multiple processors and is connected to cache memories of at least one cache level shared between the multiple processors, the main memory and to multiple processors to move data between the cache memories of the at least one cache level, the main memory and the multiple processors, wherein in response to a request from one requesting processor of the multiple processors, the at least one page mover fetches data of a storage area line-wise from at least one of the following memories: the cache memories of the at least one cache level or the main memory maintaining multiple processor cache memory access coherency; wherein the at least one page mover comprises a data processing engine which performs filtering of the fetched data, wherein the data processing engine comprises at least one filter engine to filter data of a storage area line-wise by comparing elements of a fetched line from a source address of one or more of the at least one cache level or the main memory with filter arguments to create a bitmask, and to write comparison results as bitmask data in a bitmask buffer of a target storage area located at a target address of one or more of the at least one cache level or the main memory based on a corresponding request from one processor of the multiple processors containing a filter command with the filter arguments and source and target information; and wherein the page mover moves processed data to at least one of the following components: cache memories of the at least one cache level, the main memory or the requesting processor maintaining multiple processor cache memory access coherency.