Patent ID: 9569363
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A microprocessor, comprising: a translation lookaside buffer; a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer, the requested page table entry is included in a page table, the page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry; hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table; a second request to prefetch the second cache line into the microprocessor, the second request is selectively generated based at least on the determination made by the hardware logic; to make the determination of whether the second cache line is outside the page table, the hardware logic determines whether the first cache line is the last cache line encompassed by the page table; and to determine whether the first cache line is the last cache line encompassed by the page table, the hardware logic determines whether predetermined bits of the virtual address all have a value of one.