Patent ID: 9704874
Date: 2017-07-11
CPC Classifications: G11C,H01L

Claim:
1. A bitline including: a plurality of connections to a respective plurality of bit memory cells; wherein the bitline comprises first and second bitline segments containing, respectively, approximately ⅓ of the plurality of connections and approximately ⅔ of the plurality of connections; and wherein the first and second bitline segments are electrically coupled to provide a single bitline output, the bitline further including: first and second shutdown transistors connected, respectively, to the first and second bitline segments; and first and second bitline keepers arranged in series with the respective first and second shutdown transistors, wherein the first and second bitline keepers comprise first and second bitline keeper transistors, and wherein the gate lengths of the first and second shutdown transistors are longer than a gate length of a transistor of a bit memory cell.