Patent ID: 9742552
Date: 2017-08-22
CPC Classifications: H03L,H04L

Claim:
1. A phase locked loop comprising: an integer phase detector to detect an integer phase by measuring a cycle number of at least one of an output signal of an oscillator and an oscillation signal that is a division signal of the output signal of the oscillator; a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal; a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal based on a frequency control signal which controls a frequency of the reference signal, and the integer and fractional phases; a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal when an absolute value of the frequency error signal is equal to or larger than a specific threshold value and to output the frequency error signal when the absolute value of the frequency error signal is smaller than the specific threshold value; a phase error generator to generate a phase error by integrating an output signal of the glitch corrector by temporal integration; an oscillator controller to control an oscillation frequency of the oscillation signal based on the phase error signal; and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in a phase-lock state based on the output signal of the glitch corrector, and to stop detection of the integer phase when the phase-lock state is detected.