Patent ID: 9576824
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A semiconductor wafer or sample etching system comprising: a first chamber having a loading port for passage of a semiconductor wafer or sample between an exterior and an interior of the first chamber, and a vacuum port in communication with the interior of the first chamber, wherein the interior of the first chamber defines a first volume; a sample holder mounted on a floor of the first chamber and disposed in the interior of the first chamber for supporting the semiconductor wafer or sample passed through the loading port; a sample lift mechanism for lowering and lifting the semiconductor wafer or sample to and from the sample holder; and a subchamber assembly disposed within the first chamber, the subchamber assembly moveable by a lifting/lowering mechanism with respect to the sample holder, which is stationary during movement of the subchamber assembly, between an open position where the subchamber assembly is lifted for sample loading, wherein the semiconductor wafer or sample passed through the loading port can be loaded on the sample holder, and a closed position where the subchamber assembly is lowered, wherein the combination of the subchamber assembly and the first chamber form a second chamber defining a second, smaller volume that includes the sample holder and the vacuum port therein, and wherein the sample lift mechanism is coupled to the subchamber assembly and arranged to move with the subchamber assembly.