Patent ID: 9594861
Date: 2017-03-14
CPC Classifications: G06F

Claim:
1. A computer-implemented method for circuit design verification, comprising: invoking at least an equivalency checker that executes a sequence of instructions with at least one micro-processor of a computing system in performing a set of processes, the set of processes comprising: identifying a specification design; identifying an implementation design; generating a set of transactions to be applied to the specification design and the implementation design; applying the set of transactions in a specified order to the specification design and the implementation design, such that a first order of transactions is output from the specification design and a second order of transactions is output from the implementation design; and determining equivalency between the specification design and the implementation design by checking whether the first order of transactions matches the second order of transactions, wherein the equivalency is identified even when the specification design and the implementation design are not matchable on a cycle-by-cycle basis.