Patent ID: 9627354
Date: 2017-04-18
CPC Classifications: G11C,H01G,H01L

Claim:
1. A semiconductor memory device provided with a memory chip including a circuit surface having a center pad region with a plurality of center pads formed therein, and a back surface on a side opposite from the circuit surface, the semiconductor memory device comprising: a thin-film capacitor disposed at a position facing the circuit surface except for the center pad region; and a first insulating layer formed on a side opposite from the memory chip with respect to the thin-film capacitor, the first insulating layer having a transmission line formed thereon, wherein the thin-film capacitor includes: a first plane electrode including a first power supply input portion to which a power supply voltage of one polarity to the memory chip is supplied, and a first power supply output portion disposed near the center pad region to output the supplied power supply voltage of one polarity to the center pads; a thin-film dielectric layer of a paraelectric material or a ferroelectric material formed on the first plane electrode except for the first power supply input portion and the first power supply output portion; and a second plane electrode formed on the thin-film dielectric layer and including a second power supply input portion to which a power supply voltage of another polarity to the memory chip is supplied and a second power supply output portion disposed near the center pad region to apply the supplied power supply voltage of the other polarity to the center pads, and the transmission line includes a signal input portion to which a signal to the memory chip is supplied, and a signal output portion disposed near the center pad region to supply the supplied signal to the center pads.