Patent ID: 9627433
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method of manufacturing a junction field effect transistor having a channel region disposed at a position of a semiconductor substrate, deeper than one of a source region and a drain region, the method comprising: a first step of forming a first mask over the semiconductor substrate in which a gate region of the junction field effect transistor formed by a first semiconductor region of a first conductivity type is disposed to be surrounded by another of the source region and the drain region formed by a semiconductor region of a second conductivity type opposite to the first conductivity type, the first mask having a first opening portion disposed to be surrounded by the gate region in plan view; a second step of forming a channel region of the junction filed effect transistor formed by a second semiconductor region of the second conductivity type, in a partial area of the first semiconductor region, by implantation of ions of the second conductivity type, using the first mask; and a third step of forming the one of the source and the drain region of the junction field effect transistor by a third semiconductor region of the second conductivity type, by the implantation of ions of the second conductivity type, using the first mask, wherein the source region, the drain region, and the channel region of the junction field effect transistor are formed by the first step, the second step, and the third step so as to be disposed in this order in a depth direction and be superposed in plan view.