Patent ID: 9647011
Date: 2017-05-09
CPC Classifications: G02F,H01L

Claim:
1. A manufacturing method of a thin film transistor array panel, comprising: forming a gate line in a display area of a substrate and forming a first driving signal transfer line in a peripheral area of the substrate; forming a data line in the display area of the substrate and forming a second driving signal transfer line in the peripheral area of the substrate; forming a passivation layer on the data line in the display area and the second driving signal transfer line in the peripheral area; forming a first insulating layer on the gate line and the data line positioned in the display area; forming a photosensitive film on the first insulating layer in the display area and on the passivation layer in the peripheral area; forming a first photosensitive pattern in the display area and a second photosensitive pattern in the peripheral area, by exposing and developing the photosensitive film; etching the first insulating layer using the first photosensitive pattern as an etching mask; and forming a first photosensitive layer and a second photosensitive layer only in the peripheral area by removing the first photosensitive pattern and decreasing a height of the second photosensitive pattern, wherein the first insulating layer is formed only in the display area.