Patent ID: 9595522
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductor substrate; a first gate structure including first gate spacers disposed over a first channel region of the semiconductor substrate; a second gate structure including second gate spacers disposed over a second channel region of the semiconductor substrate; a first stress region disposed between the first and second gate structures and within the first and second channel regions, the first stress region including first dislocations underlying one gate spacer of the first gate spacers and underlying one gate spacer of the second gate spacers; and a second stress region distinct from the first stress region and disposed between the first and second gate structures directly over the first stress region and within the first and second channel regions, the second stress region including top portions of the first dislocations and second dislocations underlying the one gate spacer of the first gate spacers and underlying the one gate spacer of the second gate spacers.