Patent ID: 9564373
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method comprising: forming a first hardmask on a tensile strained semiconductor layer; removing a portion of the first hardmask to form an opening, the opening exposing an upper surface of the tensile strained semiconductor layer; removing a portion of the tensile strained semiconductor layer, selective to the first hardmask, down to a buried insulator layer, to form an undercut opening that it extends laterally beneath the first hardmask; forming a first epitaxial layer in the undercut opening adjacent to and contacting a sidewall of the tensile strained layer; forming a second epitaxial layer in the undercut opening adjacent to and contacting a sidewall of the first epitaxial layer; forming a third epitaxial layer in the undercut opening adjacent to and contacting the second epitaxial layer; removing the first hardmask; forming a second hardmask on an upper surface of the tensile strained semiconductor layer, an upper surface of the first epitaxial layer, an upper surface of the second epitaxial layer, and only a portion of an upper surface of the third epitaxial layer; forming an upper epitaxial layer on an exposed portion of the upper surface of the third epitaxial layer; and performing a thermal oxidation process, such that the upper epitaxial layer is converted to an upper oxide layer and thermal condensation causes a portion of the epitaxial layer below to become a compressive strained layer.