Patent ID: 9672904
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A memory datapath architecture comprising: a plurality of transistors arranged to form a bit cell, said bit cell comprising a first transistor, a second transistor, a third transistor and a fourth transistor configured to store a bit of data; a fifth transistor having a gate coupled to a Data Bar (DB) signal, said fifth transistor having a drain coupled to a drain of said first transistor (Node T) and a Source coupled to an XWR node also selectively connected to a Word Line Bar (WLB) signal; a sixth transistor having a gate coupled to a Data (D) signal, a drain coupled to a drain of said third transistor (Node B) and a source coupled to a source of said fifth transistor and to said XWR node; and wherein said bit cell comprises: