Patent ID: 9653170
Date: 2017-05-16
CPC Classifications: G11C,H01L

Claim:
1. A pillar-shaped semiconductor memory device comprising: a semiconductor substrate; semiconductor pillars on the semiconductor substrate, extending in a direction perpendicular to a surface of the semiconductor substrate, and in at least two rows; a tunnel insulating layer surrounding an outer periphery of each of the semiconductor pillars; a data charge storage insulating layer surrounding an outer periphery of the tunnel insulating layer; a first interlayer insulating layer surrounding an outer periphery of the data charge storage insulating layer; and a first stacked material layer and a second stacked material layer that are on the semiconductor substrate so that one row of the semiconductor pillars is interposed between the first stacked material layer and a second stacked material layer, the first stacked material layer being at least one laminate including, as one set, the second stacked material layer being at least one laminate including, as one set, wherein a pitch length between semiconductor pillars adjacent to each other in the one row of the semiconductor pillars is smaller than a pitch length between a semiconductor pillar in the one row and a semiconductor pillar in a row other than the one row, in plan view, shapes of the first conductor layer and the second conductor layer, the shapes facing the semiconductor pillars, are semicircular arcs, and, between the semiconductor pillars adjacent to each other, the semicircular arcs of the first conductor layer are in contact with each other and the semicircular arcs of the second conductor layer are in contact with each other, in plan view, the first interlayer insulating layer is between a contact point of the semicircular arcs of the first conductor layer and a contact point of the semicircular arcs of the second conductor layer, the first interlayer insulating layer is connected to upper surfaces of the stacked material layer and the second stacked material layer, and data writing and erasing due to a data charge transfer between the semiconductor pillars and the data charge storage insulating layer through the tunnel insulating layer or a data charge retention by the data charge storage insulating layer is performed by application of a voltage to the first conductor layer and the second conductor layer.