Patent ID: 9684624
Date: 2017-06-20
CPC Classifications: G06F,H04L

Claim:
1. A method operational on a master device, comprising: providing a clock signal on a serial clock line (SCL line) of a serial bus, wherein the clock signal controls data transmissions on a serial data line (SDA line) of the serial bus; generating a receive clock from transitions on the SCL line when a slave device is transmitting data on the SDA line; calibrating a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal; providing a modified receive clock by adding the delay to the receive clock; and receiving data from the SDA line using the modified receive clock, wherein the clock signal provided on the SCL line controls double data rate transmissions on the SDA line.