Patent ID: 9543903
Date: 2017-01-10
CPC Classifications: H03F

Claim:
1. An apparatus comprising: a plurality of amplifier circuits having a respective plurality of outputs each configured to couple with a respective one of a plurality of load circuits, the plurality of amplifier circuits configured to receive an input radio frequency (RF) signal; and at least one interconnection circuit configured to switchably short together at least two of the plurality of outputs of at least two of the plurality of amplifier circuits at a summing node with a respective at least two of the plurality of load circuits, wherein the plurality of amplifier circuits comprises first and second amplifier circuits, the first amplifier circuit comprising a first gain transistor and a first cascode transistor, and the second amplifier circuit comprising a second gain transistor and a second cascode transistor, and wherein the at least one interconnection circuit comprises a third cascode transistor coupled between a drain of the first gain transistor and a drain of the second cascode transistor, and a fourth cascode transistor coupled between a drain of the second gain transistor and a drain of the first cascode transistor.