Patent ID: 9673708
Date: 2017-06-06
CPC Classifications: H01L,H02M

Claim:
1. A switched-capacitor DC-to-DC converter comprising: a logic cell having (i) a first substrate, (ii) a plurality of active elements disposed over the first substrate, (iii) a first interlayer insulation layer disposed over a top surface of the first substrate to cover the active elements, and (iv) a plurality of interconnection patterns disposed in the first interlayer insulation layer and electrically connected to the active elements, wherein the plurality of interconnection patterns include first and second interconnection patterns; a capacitor cell having (i) a second substrate, (ii) a capacitor disposed over a top surface of the second substrate, (iii) a second interlayer insulation layer disposed over the second substrate to cover the capacitor, (iv) a lower interconnection pattern disposed in the second interlayer insulation layer and electrically connected to a lower electrode pattern of the capacitor, and (v) an upper interconnection pattern disposed in the second interlayer insulation layer and electrically connected to an upper electrode pattern of the capacitor, wherein the second interlayer insulation layer is bonded to the first interlayer insulation layer so that the logic cell vertically overlaps with the capacitor cell; a first through via penetrating the second substrate and the second interlayer insulation layer and extending into the first interlayer insulation layer to contact the first interconnection pattern; a second through via penetrating the second substrate to contact the lower interconnection pattern; a third through via penetrating the second substrate and extending into the second interlayer insulation layer to contact the upper interconnection pattern; a fourth through via penetrating the second substrate and the second interlayer insulation layer and extending into the first interlayer insulation layer to contact the second interconnection pattern; a first external circuit pattern disposed over a bottom surface of the second substrate and electrically connected to the first and second through vias; and a second external circuit pattern disposed over the bottom surface of the second substrate and electrically connected to the third and fourth through vias, wherein the first substrate and the first interlayer insulation layer are in direct contact with each other.