Patent ID: 9570028
Date: 2017-02-14
CPC Classifications: G09G,H01L

Claim:
1. A PMOS gate driving circuit, comprising a plurality of gate driver on array (GOA) unit circuits which are cascade connected, and the GOA unit circuit of every stage comprises a pull-up controlling module, a pull-up module, a transmission module, a first pull-down module, a bootstrap capacitor and a pull-down holding module; N is set to be a positive integer, and in the GOA unit circuit of the Nth stage: the pull-up controlling module is electrically coupled to a first node and the pull-down holding module; the pull-up controlling module at least comprises a P type thin film transistor, and at least receives a stage transfer signal of the GOA unit circuit of the former N−1th stage and a constant negative voltage level; the pull-up module comprises: a twenty-second P-type thin film transistor, and a gate of the twenty-second P-type thin film transistor is electrically coupled to the first node, and a source is electrically coupled to an Mth clock signal, and a drain is electrically coupled to a scan driving signal; the transmission module comprises: a twenty-first P-type thin film transistor, and a gate of the twenty-first P-type thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the Mth clock signal, and a drain is electrically coupled to the stage transfer signal; the first pull-down module is electrically coupled to the first node and the scan driving signal, and comprises a fortieth P-type thin film transistor and a forty-first P-type thin film transistor which are mutually cascade connected, and employed to pull up a voltage level of the first node to a voltage level of the scan driving signal in a non-functioning period; one end of the bootstrap capacitor is electrically coupled to the first node, and the other end is electrically coupled to the scan driving signal; the pull-down holding module comprises: an inverter comprising a plurality of P-type thin film transistor, and an input end of the inverter is electrically coupled to the first node, and an output end is electrically coupled to a second node; a thirty-second P-type thin film transistor, and a gate of the thirty-second P-type thin film transistor is electrically coupled to the second node, and a source is electrically coupled to a drain of the forty-first P-type thin film transistor, and a drain is electrically coupled to a first constant positive voltage level; a forty-second P-type thin film transistor, and a gate of the forty-second P-type thin film transistor is electrically coupled to the second node, and a drain is electrically coupled to the first node, and a source is electrically coupled to a drain of an eighty-second P-type thin film transistor; the eighty-second P-type thin film transistor, and a gate of the eighty-second P-type thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the constant negative voltage level, and the drain is electrically coupled to a drain of an eighty-first P-type thin film transistor; the eighty-first P-type thin film transistor, and a gate of the eighty-first P-type thin film transistor is electrically couple to the second node, and a source is electrically couple to a second constant positive voltage level, and the drain is electrically couple to the drain of the eighty-second P-type thin film transistor; the first constant positive voltage level is lower than the second constant positive voltage level.