Patent ID: 9535877
Date: 2017-01-03
CPC Classifications: G06F,Y02D

Claim:
1. A system, comprising: a plurality of processors, each comprising a plurality of processor ports; and a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; wherein the plurality of dynamically configurable communication elements are interspersed among the plurality of processors and coupled to respective ones of the plurality of processors; wherein each the plurality of dynamically configurable communication elements is configured to be used by at least two of the plurality of processors; wherein, for each respective one of the processors, a first portion of the plurality of processor ports are coupled to a respective subset of the plurality of dynamically configurable communication elements and a second portion of the plurality of processor ports are directly coupled to a respective subset of the plurality of processors that are physically adjacent to the processor; wherein, for each of the dynamically configurable communication elements, the plurality of communication ports comprise a first subset of communication ports coupled to a subset of the plurality of said processors and a second subset of communication ports coupled to a second subset of the plurality of dynamically configurable communication elements; and wherein, for each of at least a plural subset of said dynamically configurable communication elements, the first memory of a respective dynamically configurable communication element is shared among a respective subset of the processors.