Patent ID: 9659851
Date: 2017-05-23
CPC Classifications: H01L,H05K,Y10T

Claim:
1. A semiconductor package interposer comprising: a substrate having a first surface and a second surface; a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate; metal plugs at least partially filling the plurality of vias; depressions in the first surface of the substrate at distal ends of the metal plugs, wherein the metal plugs (i) extend beyond bottoms of the depressions and (ii) are separated from the substrate in the depressions; and solder bumps that (i) cover the distal ends and (ii) at least partially fill the depressions between sides of the metal plugs and the sides of the depressions; wherein the metal plugs extend beyond (i) tops of the depressions and (ii) the first surface of the substrate.