Patent ID: 9721860
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A packaged transistor device comprising: a semiconductor chip having a thickness, the chip including a transistor with terminals distributed on a first side and an opposite second side of the semiconductor chip; a slab of silicon including a recessed central area suitable to accommodate the semiconductor chip and at least one ridge bordering the recessed central area the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth at least equal to the chip thickness, the at least one ridge having a metal layer configured as terminals of the transistor device and the recessed central area having pads; and the terminals of the first side attached to the pads so that the terminals of the opposite second side are co-planar with the device terminals wherein the slab serves as a package of the transistor device, wherein the terminals of the opposite second side are exposed from the package.