Patent ID: 9698240
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor device comprising: forming a dielectric layer over a dummy gate, over a first active area of a fin and over a first shallow trench isolation (STI) portion surrounding the first active area, the dummy gate over a channel portion of the fin and over a gate portion of the STI surrounding the channel portion of the fin, where a first active area top surface of the first active area is coplanar with a first STI top surface of the first STI portion; removing the dummy gate, such that a channel top surface of the channel portion of the fin is exposed and such that the gate portion of the STI is exposed; removing the gate portion of the STI, such that channel sidewalls of the channel portion of the fin are exposed; and forming a gate over the channel top surface and adjacent the channel sidewalls of the channel portion of the fin, such that the first active area top surface of the first active area remains coplanar with the first STI top surface of the first STI portion.