Patent ID: 9583574
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A semiconductor material stack, comprising: a silicon substrate having a first lattice constant; a group III-N device layer disposed over the silicon substrate, the group III-N device layer having a second lattice constant different than the first lattice constant; a top barrier layer formed above the group III-N device layer wherein the top barrier layer comprises a multilayer stack comprising an Al N-type group source and drain regions disposed on the top barrier layer; a gate electrode disposed between the N-type group III-N source and drain regions, wherein the top barrier layer has a first thickness between the gate electrode and the group III-N device layer and a second, greater, thickness between the N-type group III-N source and drain regions and the group III-N device layer, and a third thickness between a spacer region disposed between the gate electrode and each of the group III-N source and drain regions and the group III-N device layer, wherein the third thickness is intermediate to the first thickness and the second thickness; a gate dielectric disposed below the gate electrode and adjacent to sidewalls of the gate electrode; a pair of ohmic contacts disposed on the N-type group III-N source and drain regions, wherein an uppermost surface of the pair of ohmic contacts is co-planar or substantially co-planar with an uppermost surface of the gate electrode and with an uppermost surface of the gate dielectric; and a buffer disposed between the silicon substrate and the group III-N device layer, wherein the buffer includes an Al