Patent ID: 9703595
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. A multi-core system comprising: a lower sub-system including a first processor and a plurality of slave processing cores, said first processor configured to control processing on said plurality of slave processing cores; and said first processor including a system dispatcher configured to control transactions having Transaction Control Blocks (TCBs) for execution on said plurality of slave processing cores; said first processor further including a plurality of hardware drivers for receiving said transactions being in a TCB format from said system dispatcher, converting said transactions from said TCB format into a native format required by each of said plurality of slave processing cores, wherein at least one of said plurality of slave processing cores has a different native format than another one of said plurality of slave processing cores; wherein after execution of a first transaction of said transactions by a first slave processing core of said slave processing cores associated with a first hardware driver of said plurality of hardware drivers, said first hardware driver providing results of said execution to said system dispatcher in said TCB format for further execution by one of said slave processing cores; wherein said TCB format includes a resource identification field, a job identification field, a priority field, a function identification field, a context pointer field, an input data pointer field, an output data pointer field and a next transaction field.