Patent ID: 9723179
Date: 2017-08-01
CPC Classifications: H04N

Claim:
1. A Time Delay and Integration (TDI) image sensor comprising: an array of light sensing elements arranged in a row, each light sensing element configured to accumulate charge proportional to an intensity of light incident on the light sensing element from a field of view, the array of light sensing elements including a light sensing element at an end of the row of light sensing elements; at least one clock coupled to the array of light sensing elements, the at least one clock configured to operate the array of light sensing elements to sequentially transfer the accumulated charge of each light sensing element in the row to an adjacent light sensing element at a first phase to produce a first total accumulated charge at the light sensing element at the end of the row, and to sequentially transfer the accumulated charge of each light sensing element in the row to an adjacent light sensing element at a second phase to produce a second total accumulated charge at the light sensing element at the end of the row, the first phase being different than the second phase; a first memory bank coupled to the light sensing element at the end of the row of light sensing elements and configured to store a first total accumulated value corresponding to the first total accumulated charge; a second memory bank coupled to the light sensing element at the end of the row of light sensing elements and configured to store a second total accumulated value corresponding the second total accumulated charge; and an image processor coupled to the array of light sensing elements and configured to read out a first signal corresponding to the first total accumulated value from the first memory bank, to read out a second signal corresponding to the second total accumulated value from the second memory bank, and to combine the first signal and the second signal to generate an image, wherein the image processor is further configured to read out the first signal and the second signal in parallel from the first memory bank and the second memory bank.