Patent ID: 9698245
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method of making a vertical transistor, comprising: forming a fin or a vertical nanowire over a semiconductor substrate; forming a bottom source/drain region, and a bottom spacer that laterally contacts the bottom source/drain region, prior to the forming of a gate electrode, wherein the bottom source/drain region is located between the fin or the vertical nanowire and a top semiconductor layer of the semiconductor substrate, and the bottom spacer separates the gate electrode from the top semiconductor layer of the semiconductor substrate; forming the gate electrode over sidewalls of the fin or vertical nanowire; forming a sacrificial spacer over the gate electrode; forming a bottom source/drain contact adjacent to the sacrificial spacer; removing the sacrificial spacer to create a cavity between the gate electrode and the bottom source/drain contact; and depositing a dielectric material into the cavity, wherein the dielectric material comprises a vertical air-gap.