Patent ID: 9690510
Date: 2017-06-27
CPC Classifications: G06F,G11C,H01L

Claim:
1. A memory device comprising: a first memory cell array on a first tier; a second memory cell array on a second tier, the second tier being arranged in an integrated circuit package which encloses both the first and second tiers so the second tier is arranged over the first tier, or vice versa; a control circuit configured to perform a first read/write operation during a first time interval by writing a first data value to a first group of memory cells on the first tier while concurrently reading a second data value from a second group of memory cells on the second tier; wherein the control circuit is further configured to perform a second read/write operation during a second time interval by writing a third data value to a third group of memory cells on the second tier while concurrently reading a fourth data value from a fourth group of memory cells on the first tier, the second time interval being after the first time interval; and wherein the first data value and third data value are collectively made up of N-bits and collectively correspond to an N-bit input data word provided onto input pins of the memory device at a first time prior to the first time interval.