Patent ID: 9620217
Date: 2017-04-11
CPC Classifications: G11C,H01L

Claim:
1. A method of operating a NAND array that includes a plurality of blocks of memory cells, wherein a block of memory cells in the plurality of blocks comprises a plurality of NAND strings having channel lines between first string select switches and second string select switches, and in which the plurality of NAND strings shares a set of word lines between the first and second string select switches, comprising: applying a channel-side erase voltage to the channel lines of the NAND strings through the first string select switches in a selected block; applying word line-side erase voltages to a selected subset of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, the selected subset including more than one member of the set of word lines; inhibiting tunneling in memory cells coupled to an unselected subset of the set of word lines shared by NAND strings in the selected block, the unselected subset including more than one member of the set of word lines; applying a first control voltage to turn on word line drivers for word lines in the selected subset; and applying a second control voltage to turn off word line drivers for word lines in the unselected subset, when applying a global word line voltage matching the second control voltage to inputs of the word line drivers for word lines in the unselected subset, wherein the first control voltage is different than the second control voltage.