Patent ID: 9748387
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of forming a first NMOS FinFET device, a PMOS FinFET device and a second NMOS FinFET device for a CMOS integrated circuit product formed on a semiconductor substrate made of a first semiconductor material, the method comprising: forming first, second and third fins for said first NMOS FinFET device, said PMOS FinFET device and said second NMOS FinFET device, respectively, wherein said first fin consists entirely of said first semiconductor material, said second fin comprising a lower substrate fin portion made of said first semiconductor material and an upper fin portion made of a second semiconductor material, said third fin comprising a lower substrate fin portion made of said first semiconductor material and an upper fin portion made of a third semiconductor material that is positioned above said lower substrate fin portion of said third fin, wherein said second semiconductor material and said third semiconductor material are each different from said first semiconductor material, and wherein said second semiconductor material is different from said third semiconductor material; performing at least one process operation to form a recessed layer of insulating material adjacent said first, second and third fins, said recessed layer of insulating material comprising a recessed upper surface that exposes at least a portion of said first fin and at least a portion of said upper fin portion of both of said second and third fins; forming a first patterned masking layer that covers said first NMOS FinFET device and said PMOS FinFET device and exposes said second NMOS FinFET device; with said first patterned masking layer in position, performing an epitaxial deposition process to form a semiconductor material cladding on said exposed upper portion of said third fin for said second NMOS FinFET device, wherein said semiconductor material cladding is a different semiconductor material than that of said third semiconductor material; forming a PMOS gate structure for said PMOS FinFET device around said exposed upper portion of said second fin of said PMOS device; and forming a first NMOS gate structure for said first NMOS FinFET device around said exposed portion of said first fin and a second NMOS gate structure for said second NMOS FinFET device around said semiconductor material cladding.