Patent ID: 9620522
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: providing a multilayered structure in which different material layers are alternately stacked over a substrate; etching partially the material layers to form a multi-step structure, each step being formed of at least one pair of the material layers; forming an interlayer insulating layer to cover the multi-step structure; forming first slits, each first slit vertically passing through the interlayer insulating layer and partially exposing a top face of each step; forming vertical support layers by filling the first slits with an insulating material for the vertical support layers, each vertical support layer being disposed on a top surface of each step; forming second slits vertically passing through the interlayer insulating layer to expose sidewalls of the material layers; removing partially the material layers to form recesses; filling the recesses with a conductive material to form gate lines, the gate line defining an upper portion of the step; and forming vertical contact plugs respectively on the upper portion of the step.