Patent ID: 9547566
Date: 2017-01-17
CPC Classifications: G06F,G11C

Claim:
1. A storage control apparatus comprising: a memory controller configured to write pages of data into memory and read the pages of the data from the memory, a block of the memory includes at least a first one of the pages and a second one of the pages, wherein the first one of the pages includes first data along with an error detection and correction code for the first data, the second one of the pages includes second data along with an error detection and correction code for the second data, wherein a third one of the pages includes third data along with an error detection and correction code for the third data, the third data includes an error detection and correction code for the block, wherein the memory controller is configured to prohibit access to the block when an error in the first data or the second data is uncorrectable, and wherein the third one of the pages includes an uncorrectable error generation flag, the uncorrectable error generation flag indicates that the error in the first data or the second data is correctable or uncorrectable.