Patent ID: 9589980
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first semiconductor pattern including a plurality of protrusions formed on a whole sidewall thereof, wherein the first semiconductor pattern vertically passes through first gate electrodes included in a lower part of gate electrodes of memory cells stacked each other; a second semiconductor pattern respectively coupled to the first semiconductor pattern and increasing in width away from joining surfaces where the first semiconductor pattern and the second semiconductor pattern are coupled, wherein the second semiconductor pattern vertically passes through second gate electrodes included in an upper part of gate electrodes of memory cells which are stacked over the lower part of the gate electrodes, wherein the protrusions are formed at a top gate electrode in the lower part of the gate electrodes stacked over each other, wherein the first semiconductor pattern has a greater width than that of the second semiconductor pattern at the joining surface, and each of the protrusions has a round shape; a third semiconductor pattern coupling at least two first semiconductor patterns; and fourth semiconductor patterns having a greater width than that of the first semiconductor patterns, wherein each of the fourth semiconductor patterns is interposed between a corresponding one of the first semiconductor patterns and the third semiconductor pattern.