Patent ID: 9606841
Date: 2017-03-28
CPC Classifications: G06F

Claim:
1. A method for scheduling a plurality of processes of a workload on hardware threads of a plurality of processing elements in a computing system, the method comprising: representing processing resources of the computing system by generating a processor space having locations corresponding to the hardware threads of the plurality of processing elements, the processor space generated based at least in part on hardware resources associated with the hardware threads of the plurality of processing elements such that hardware threads associated with similar hardware resources are assigned proximate locations of the processor space; assigning process dimensions to the plurality of processes of the workload based at least in part on at least one processing attribute associated with each process among the plurality of processes, the process dimensions representative of one or more locations in the processor space and depending at least in part on the at least one processing attribute associated with each process; analyzing the process dimensions assigned to each process; grouping the plurality of processes into one or more groups based at least in part on the determined process dimensions for each process to map related processes to proximate hardware threads and/or map processes having similar hardware resource requirements to hardware threads in different processing elements; mapping each process among the plurality of processes to at least one location in the processor space based at least in part on the assigned process dimensions using a place and route algorithm; and causing the processor to schedule each process among the plurality of processes to at least one hardware thread corresponding to the at least one location to which the process is mapped.