Patent ID: 9602244
Date: 2017-03-21
CPC Classifications: H03M,H04L

Claim:
1. A low density parity check (LDPC) encoder, comprising: first memory configured to store an LDPC codeword having a length of 16200 and a code rate of 4/15; second memory configured to be initialized to 0; and a processor configured to generate the LDPC codeword having a length of 16200 and a code rate of 4/15, corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM), wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 4320, a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080, and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10800, and wherein the sequence is represented by the following Sequence Table: