Patent ID: 9558145
Date: 2017-01-31
CPC Classifications: G06F,H04L

Claim:
1. An apparatus comprising: timing logic to associate a first value with a unit of data upon entry into a path of a physical layer coupled to a serial interconnect; latency logic to associate a second value upon an exit from the path of the physical layer and to determine a latency associated with the path of the physical layer based on the first value and the second value; a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, wherein the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, wherein the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value, the latency logic comprising the resolution logic.