Patent ID: 9728617
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate comprising a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas, wherein the gate electrode is electrically insulated from the neighboring semiconductor mesas by a gate trench dielectric; forming a respective pillar on each of the neighboring semiconductor mesas leaving an opening between the pillars above the trench; forming dielectric contact spacers in the opening along respective pillar side walls to narrow the opening above the gate electrode; and after forming the dielectric contact spacers, forming a conductor having an interface with the gate electrode, the interface extending along an extension of the gate electrode, wherein the conductor has a conductivity greater than the conductivity of the gate electrode, removing the pillars on each of the neighboring semiconductor mesas after forming the conductor so as to expose a top surface of the neighboring semiconductor mesas, and depositing a conformal dielectric layer that contacts the exposed top surface of the neighboring semiconductor mesas, the dielectric contact spacers and the conductor.