Patent ID: 9715854
Date: 2017-07-25
CPC Classifications: G06T,G09G

Claim:
1. A matrix liquid crystal display having at least N rows and P columns, and comprising an image memory containing the luminance data for the pixels received for an image to be displayed, including data for each of M rows containing a non-zero image information item, M less than or equal to N, and a graphics processor that is capable of extracting from the memory the addresses of the M rows, and, for each of these, P luminance levels to be applied by P column conductors to the P pixels of the row, with a periodic duration T L for writing a row, and a high-voltage stage having N inputs and having N outputs that are each respectively connected to a respective row conductor that is common to the pixels of one and the same row of the matrix in order to allow the selection of a row of pixels for the purpose of writing luminance data to this row, the display further comprising: N sampling and conversion circuits having at least one common signal input to be sampled, this input receiving from the graphics processor a pattern of N successive binary words in the course of a duration T a sampling control circuit that is actuated at the frequency F a control input of the high-voltage stage in order to apply to the N row conductors voltages corresponding to the voltages that are present on the outputs of the sampling and conversion circuits at the end of reception of the succession of N binary words, and in order to maintain these voltages over a duration that is necessary for writing a row.