Patent ID: 9741871
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A junction field effect transistor comprising: an insulating carrier substrate; a base semiconductor substrate formed on the insulating carrier substrate; a gate region formed on the base semiconductor substrate wherein the gate region forms a junction with the base semiconductor substrate; a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region; a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region; and a gate stack deposited on the gate region, a first source/drain stack deposited on the first source/drain region and a second source/drain stack deposited on the second source/drain region wherein at least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack, wherein the gate stack comprises an intrinsic semiconductor layer having a bottom portion in contact with the base semiconductor substrate, a doped crystalline semiconductor material layer and a gate metal electrode layer.