Patent ID: 9704720
Date: 2017-07-11
CPC Classifications: H01J,H01L

Claim:
1. A method of forming an integrated circuit, comprising the steps: forming a silicon nitride feature on a substrate; forming a surface layer of oxidized silicon on an exposed surface of said silicon nitride feature; placing said substrate in a etch tool, so that the substrate is on a substrate base of said etch tool, said substrate base being at a first temperature; generating a plasma in said etch tool using a fluorine-containing gas, ammonia and an inert gas so as to produce fluorine radicals which adsorb onto said surface layer of oxidized silicon and react with said surface layer of oxidized silicon while said substrate is on said substrate base; raising said substrate off said substrate base proximate to a heated element of said etch tool so that by-products of a reaction between said fluorine radicals and said surface layer of oxidized silicon are removed, said heated element being at a second temperature greater than the first temperature; subsequently lowering said substrate onto said substrate base; and generating a plasma in said etch tool using fluorine-containing reagents which are substantially free of ammonia so as to produce fluorine radicals which react with silicon in said silicon nitride feature so as to remove at least a portion of said silicon nitride feature.