Patent ID: 9651843
Date: 2017-05-16
CPC Classifications: G02F,H01L

Claim:
1. A thin film transistor array substrate, comprising: a bottom gate of a thin film transistor, disposed on a substrate; a bottom gate insulating layer, disposed on the substrate and covering the bottom gate; a semiconductor oxide layer, disposed on the bottom gate insulating layer; an etch blocking layer, disposed on the bottom gate insulating layer and covering the semiconductor oxide layer, wherein the etch blocking layer comprises a first via, a portion of the semiconductor oxide layer is exposed through the first via; a drain and a source of the thin film transistor, disposed on the etch blocking layer, the drain contacting with the semiconductor oxide layer through the first via; an insulating protection layer, disposed on the etch blocking layer and covering the drain and source; a second via, arranged in the insulating protection layer, the etch blocking layer and the bottom gate insulating layer, a portion of the bottom gate being exposed through the second via; and a top gate, disposed on the insulating protection layer and the top gate contacting with the bottom gate through the second via.