Patent ID: 9548739
Date: 2017-01-17
CPC Classifications: H03F,H03K

Claim:
1. A circuit comprising: a transistor stack comprising a series connection of a first transistor device, a second transistor device, and an output transistor device, the output transistor device having an output terminal and a control terminal, the first transistor device having an input terminal configured for a connection to a control voltage; a capacitive coupling between the control terminal and the output terminal configured to drive the control terminal with a coupled signal that continuously tracks an output signal on the output terminal; and a biasing circuit connected to the control terminal of the output transistor device, the biasing circuit configured to provide a DC bias voltage that is combined with the coupled signal to provide a drive signal on the control terminal, the biasing circuit further configured to respond to changes in a voltage level of the drive signal substantially with no delay in order to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level.