Patent ID: 9747966
Date: 2017-08-29
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device comprising: a memory cell which includes a variable resistance element; a reference signal generation circuit configured to generate a reference signal; a sense amplifier including a first input terminal and a second input terminal; a first transistor configured to electrically couple the memory cell and the first input terminal of the sense amplifier; a second transistor configured to electrically couple the reference signal generation circuit and the second input terminal of the sense amplifier; a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor; a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor; a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor; and a functional circuit including a third transistor, wherein threshold voltages of the first transistor and the second transistor are greater than a threshold voltage of the third transistor.