Patent ID: 9679528
Date: 2017-06-13
CPC Classifications: G09G,G11C

Claim:
1. A shift register unit, employed for providing a gate voltage to a nth pixel of a liquid crystal display, wherein the shift register unit comprises a first N-type transistor, a second N-type transistor, and a third N-type transistor, wherein, a gate of the first N-type transistor receives a gate voltage of a n−2th pixel, and a first end of the first N-type transistor receives a first input signal, and a second end of the first N-type transistor is coupled to a gate of the third N-type transistor; wherein the gate voltage of the n−2th pixel is employed to control on-off of the first N-type transistor, and to control on-off of the first input signal to the third N-type transistor; wherein n is a natural number larger than 2; a gate of the second N-type transistor receives a gate voltage of a n−2th pixel, and a first end of the second N-type transistor receives a second input signal, and a second end of the second N-type transistor is coupled to the gate of the third N-type transistor; wherein the gate voltage of the n−2th pixel is employed to control on-off of the second N-type transistor, and to control on-off of the second input signal to the third N-type transistor; a first end of the third N-type transistor is coupled to a first or second clock signal, and a second end of the third N-type transistor is employed as being a voltage output end of the shift register unit to be coupled to the nth pixel for charging and discharging the nth pixel, and to provide a gate voltage; wherein the shift register unit further comprises a fourth N-type transistor, and a gate of the fourth N-type transistor receives the first or second clock signal, and a first end of the fourth N-type transistor is coupled to the gate of the third N-type transistor, and a second end of the fourth N-type transistor is coupled to a second end of the third N-type transistor, and the gate of the fourth N-type transistor and the first end of the third N-type transistor receive the same clock signal.