Patent ID: 9673210
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a semiconductor structure comprising a nonvolatile memory cell element comprising an active region formed in a semiconductor material, a select gate structure, a dummy control gate structure and a transfer gate structure, and an electrically insulating structure extending around each of said select gate structure, said dummy control gate structure and said transfer gate structure; removing said dummy control gate structure, wherein a first recess is formed in said semiconductor structure; after removing said dummy control gate structure, depositing a charge trapping layer and a layer of a control gate electrode material over said semiconductor structure; and removing portions of said charge trapping layer and said layer of said control gate electrode material over said electrically insulating structure, portions of said charge trapping layer and said layer of said control gate electrode material in said first recess providing a control gate structure of said nonvolatile memory cell.