Patent ID: 9553262
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method of forming an array of memory cells, comprising: forming shallow trenches into conductively doped silicon-comprising semiconductor material of a first conductivity type, second conductivity type semiconductor material being elevationally inward of the conductively doped first type semiconductor material; reacting metal with silicon of bases of the shallow trenches to form conductive metal silicide over the bases; forming deep trenches through the conductive metal silicide, through the conductively doped first type semiconductor material, and into the second conductivity type semiconductor material to form buried access lines running along and between the deep trenches; the forming of the deep trenches forming pillars comprising conductively doped first type semiconductor material extending elevationally outward of and spaced along the buried access lines; forming outer access lines elevationally outward of the pillars; providing a plurality of conductive vias spaced along and electrically coupling pairs of individual of the buried and outer access lines, a plurality of the pillars being spaced between immediately adjacent of the vias along the pairs; and providing a memory cell within individual of the pillars.