Patent ID: 9705665
Date: 2017-07-11
CPC Classifications: H03L,H04L

Claim:
1. A clock and data recovery circuit, comprising: a data input configured to receive input data from an electronic device; a clock configured to generate a first clock signal; a phase locked loop configured to receive the first clock signal and generate a plurality of second clock signals mutually out of phase with each other; a sampler circuit coupled to the phase locked loop and the data input and configured to generate a plurality of samples based on the input data and the second clock signals; a frequency divider coupled to the phase locked loop and configured to divide a frequency of the first clock signal by a division ratio; and a unit interval movement controller coupled to the frequency divider and configured to output to the frequency divider a command to change the division ratio from a base value to a repositioning value when a relative position of a selected center sample has drifted from a selected position of a current input data bit by more than a threshold value, wherein the frequency divider is configured to change the division ratio back to the base value after one clock cycle at the repositioning value.