Patent ID: 9558086
Date: 2017-01-31
CPC Classifications: G06F

Claim:
1. A System on Chip (SOC) comprising: a first UART controller and a second UART controller having different baud rates; a debug controller coupled to the second UART controller and a system bus for generating a control signal with a first state and checking whether a received data from the second UART controller is equal to a keyword after power-up or a hardware reset; a UART port comprising a R×D pin and a T×D pin, wherein the R×D pin of the UART port is coupled to a R×D pin of the second UART controller; a first multiplexer for coupling the R×D pin of the UART port to the R×D pin of the first UART controller in response to the first state of the control signal, and for coupling a voltage terminal applied with a UART idle signal to the R×D pin of the first UART controller in response to a second state of the control signal; and a second multiplexer for coupling a T×D pin of the first UART controller to the T×D pin of the UART port in response to the first state of the control signal, and for coupling a T×D pin of the second UART controller to the T×D pin of the UART port in response to the second state of the control signal; wherein when the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.