Patent ID: 9570678
Date: 2017-02-14
CPC Classifications: G11C,H01L

Claim:
1. A method for fabricating a semiconductor device having a non-volatile memory device, comprising: disposing a first dielectric material above substrate, wherein the first dielectric material comprises a first surface; forming a plurality of first electrodes above the first surface of the first dielectric material, wherein the plurality of first electrodes includes a first electrode and a second electrode; disposing a second dielectric material above the first surface of the first dielectric material and between the plurality of first electrodes, wherein the plurality of first electrodes and the second dielectric material have a first co-planar surface; forming a patterned third material upon the a first portion of the first co-planar surface, wherein the third material contacts at least a first portion of the first electrode, and wherein a second portion of the first co-planar surface is exposed; disposing a fourth dielectric material above the second portion of the first co-planar surface, wherein the fourth dielectric material contacts at least a second portion of the first electrode, wherein the patterned third material and the fourth dielectric material contact at a first interface region, wherein the first interface region is characterized by a plurality of defects, and wherein the patterned third material and the fourth dielectric material have a second co-planar surface; forming a plurality of second electrodes upon the second co-planar surface, wherein the plurality of second electrodes includes a third electrode, wherein the third electrode contacts a portion of the patterned third material, a portion of the fourth dielectric material, and the first interface region, wherein the plurality of second electrodes comprises a plurality of metal particles that are configured to be diffused within the first interface region upon application of a bias voltage.