Patent ID: 9640477
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method of producing a semiconductor package, comprising: planarizing a surface that extends from at least part of a plurality of connection regions to a pair of terminals by disposing a semiconductor element that includes the plurality of connection regions at a surface thereof and a capacitor element that includes the pair of terminals such that the semiconductor element and the capacitor element do not overlap each other in plan view of the semiconductor element, and by filling a portion between the semiconductor element and the capacitor element with an insulator layer, the capacitor element supplying electric current to the semiconductor element, the plurality of connection regions being where a circuit element is provided and being provided for connecting the circuit element to an outside, the pair of terminals being provided for connection to an outside; directly connecting part of the plurality of connection regions and one of the pair of terminals to a first metal layer by forming the first metal layer on top of the plurality of connection regions, on top of the pair of terminals, and on top of the insulator layer; forming a dielectric layer on top of the first metal layer; and forming a capacitor layer by forming a second metal layer on top of the dielectric layer, the capacitor layer including the first metal layer, the dielectric layer, and the second metal layer.