Patent ID: 9692623
Date: 2017-06-27
CPC Classifications: H03K,H03M,H04L

Claim:
1. A receiver comprising: a receiver circuit configured to receive a pulse width modulated signal, the signal assuming at least a first signal level, a second signal level and an intermediate signal level between the first signal level and the second signal level; and a quantization circuit configured to determine a value encoded in the signal based on an intermediate time period between a first transition and an intermediate transition and based on a main time period between the first transition and a second transition, the first transition and the second transition having the same direction, wherein the first transition comprises the first signal level, wherein the intermediate transition comprises the intermediate signal level, and wherein the second transition comprises the second signal level; wherein the receiver circuit is configured to receive the pulse width modulated signal assuming a plurality of intermediate signal levels between the first signal level and the second signal level, the plurality of intermediate signal levels comprising the intermediate signal level, wherein the quantization circuit is configured to determine the value encoded in the signal based on the main time period and on a plurality of intermediate time periods between the first transition and a plurality of intermediate transitions, and wherein each of the plurality of intermediate transitions comprises a different intermediate signal level of the plurality of intermediate signal levels, and wherein the plurality of intermediate signal levels are located between the first signal level and the second signal level.