Patent ID: 9633162
Date: 2017-04-25
CPC Classifications: G06F,H01L

Claim:
1. A method, comprising: specifying a first modular tile of an integrated circuit, wherein the first modular tile has a square shape and performs a first function; specifying a second modular tile of the integrated circuit, wherein the second modular tile has a square shape of the same size as the first modular tile, wherein the second modular tile performs a second function, wherein each of the first modular tile and the second modular tile has a standardized set of connectors disposed at fixed locations on each of the four edges of each modular tile such that a first set of connectors on an edge of the first modular tile aligns with a second set of connectors on an edge of the second modular tile regardless of whether the second modular tile is disposed to the right, to the left, above, or below the first modular tile; generating a physical layout for the integrated circuit such that an end application of the integrated circuit is operational when the first function and the second function are performed regardless of whether the second modular tile is disposed to the right, to the left, above, or below the first modular tile; and manufacturing the integrated circuit using the physical layout.