Patent ID: 9652580
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A method generating a layout design for a semiconductor device, the method comprising: generating an initial layout design from a schematic circuit design including a first circuit having a first transistor with a first gate configured from a first gate line pattern and a second circuit having a second transistor with a second gate configured from a second gate line pattern, wherein each of the first and second gate line patterns are designated with a mark in the initial layout design to indicate that the respective widths of the first and second gate line patterns cannot be modified within the initial layout design; optimizing the first circuit in view of a performance characteristic for the first transistor and removing the designation mark for the first gate line pattern during generation of a final layout design; generating the final layout design from the initial layout design, wherein the final layout design includes: (a) the designation mark for the second gate line pattern indicating that the width of the second gate line pattern cannot be modified within the final layout design and (b) the absence of the designation mark for the first gate line pattern, indicating that the width of the first gate line pattern can be modified within the final layout design; and manufacturing the semiconductor device using the final layout design.