Patent ID: 9627062
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. A memory unit comprising: a) a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell; b) the first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line and the second group access switch being configured to be controlled by the first column bit line, in which the first and second group access switches comprise Active Bit Line Enabled NMOS devices having a low voltage off state and a high voltage on state, and wherein the first and second access transistors comprise the NMOS devices.