Patent ID: 9633882
Date: 2017-04-25
CPC Classifications: G02B,H01L

Claim:
1. A method of producing an integrated circuit comprising: forming a base layer overlying a substrate; forming an alignment mark overlying the base layer; forming a first layer overlying the base layer and the alignment mark, wherein the first layer comprises a first layer thickness; forming a second layer overlying the first layer, wherein the second layer comprises a second layer thickness, and wherein a combined thickness of the first layer thickness and the second layer thickness is from about 2 micrometers to about 50 micrometers; and forming a second component from the second layer, wherein forming the second component comprises viewing the alignment mark through the first layer and the second layer, wherein the first layer comprises a first refractive index measured at 589 nanometers, wherein the second layer comprises a second refractive index measured at 589 nanometers, and wherein the second refractive index is within about 0.05 units of the first refractive index.