Patent ID: 9541855
Date: 2017-01-10
CPC Classifications: B41J,G02B,G03G,H03K

Claim:
1. A signal processing device that generates an output signal in accordance with image data, using a clock corresponding to pixels of the image data, the signal processing device comprising: a delayed signal group generator configured to generate a group of delayed signals with a delay element group formed with a plurality of stages of delay elements, the delay element group delaying the clock in a plurality of stages within a time equivalent to one pulse of the clock; a clock adjuster configured to generate a modulation/synchronization clock from the group of delayed signals by referring to i) phase data matching the clock with a predetermined phase, and ii) frequency modulation coefficient data converting the clock to a predetermined frequency, the modulation/synchronization clock having a frequency and a synchronization state adjusted; and a PWM processor configured to generate a PWM signal from the group of delayed signals which are the same as the group of delayed signals used for generating the modulation/synchronization clock by referring to the phase data, the frequency modulation coefficient data, the modulation/synchronization clock, and the image data, the PWM signal having a pulse width corresponding to a value of the image data and being adjusted to the predetermined frequency while being synchronized with the predetermined phase, wherein: the delayed signal group generator generates delay amount data indicating a delay time equivalent to one stage of the group of delayed signals based on how many stages of the group of delayed signals are equivalent to one cycle of the clock, and supplies the delay amount data together with the group of delayed signals to the clock adjuster and the PWM processor, the clock adjuster selects desired delayed signals from the group of delayed signals and generates the modulation/synchronization clock by further referring to the delay amount data, and the PWM processor selects desired delayed signals from the group of delayed signals and generates the PWM signal by further referring to the delay amount data.