Patent ID: 9626467
Date: 2017-04-18
CPC Classifications: G06F,H01L

Claim:
1. A method for modeling and simulating a SOI (silicon-on-insulator) MOS (metal-oxide semiconductor) device using a BSIMSOI (Berkeley Short-Channel IGFET Model Silicon on Insulator) model, wherein the SOI MOS device is a SOI MOS device having source-drain injection not reaching a bottom, and the method comprises: establishing an overall model comprising a primary MOS device model simulating a SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model, wherein the source body PN junction bottom capacitance model and the drain body PN junction bottom capacitance model are PN junction capacitance models in SPICE (Simulation Program with Integrated Circuit Emphasis), wherein a side junction capacitance is set as zero, and wherein the side junction capacitance is set as zero by setting at least one of a PN junction perimeter capacitance and a PN junction unit perimeter capacitance as zero.