Patent ID: 9735260
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A transistor comprising: a first layer including a first III-V nitride semiconductor, the first layer being a channel layer; a second layer stacked on a top surface of the first layer and including a second III-V nitride semiconductor, the second layer being an electron supply layer; a surface layer stacked on a top surface of the second layer and including a III-V nitride semiconductor having a first conductivity type; and a gate electrode formed at a top surface side of the surface layer; wherein: the second layer has one of a second conductivity type opposite to the first conductivity type or a semi-insulating type, a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V nitride semiconductor, two dimensional electron gas is generated within the first layer during on state, and at least the second layer that is located under the gate electrode and is configured to include a thickness that is to be substantially depleted, forming a depletion region extending from a junction between the surface layer and the second layer to the first layer along a stack direction, when zero voltage is applied to the gate electrode.