Patent ID: 9639360
Date: 2017-05-02
CPC Classifications: G06F

Claim:
1. Apparatus for processing data comprising: data processing circuitry configured to execute data processing operations specified by program instructions; and instruction decoder circuitry configured to decode said program instructions to generate control signals for controlling said data processing circuitry to execute said data processing operations specified by said program instructions; wherein: said data processing circuitry and said instruction decoder circuitry are part of a processing pipeline and said data processing circuitry is downstream of said instruction decoder circuitry within said processing pipeline; said instruction decoder circuitry is configured to decode a sequence of program instructions and said data processing circuitry is configured to execute the decoded sequence of program instructions to evaluate a data processing function; said sequence of program instructions includes an intermediate value generating instruction; decoding of said intermediate value generating instruction by said instruction decoding circuitry generates control signals that control said data processing circuitry to execute said intermediate value generating instruction to generate, at a location downstream of said instruction decoder circuitry within said processing pipeline, an intermediate data value and an embedded opcode value; said sequence of program instructions includes, after said intermediate value generating instruction, an intermediate value consuming instruction for consuming said intermediate data value; and said instruction decoder circuitry and said data processing circuitry are configured to operate in dependence upon said embedded opcode value.