Patent ID: 9634245
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a lower conductive line extending in a first direction, the lower conductive line comprising alternating layers of at least a first material and at least a second material; an upper conductive line extending in a second direction and crossing the lower conductive line, the upper conductive line comprising alternating layers of at least a third material and at least a fourth material; wherein at least one of the alternating layers of the upper and lower conductive lines comprises tungsten and carbon; and a memory cell stack interposed at an intersection between the upper and lower conductive lines, the memory cell stack including: a first active element disposed over the lower conductive line and a second active element disposed over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element; an electrode interposed between the first active element and the lower conductive line; and a second electrode interposed between the second active element and the upper conductive line.