Patent ID: 9552310
Date: 2017-01-24
CPC Classifications: G06F

Claim:
1. A signal control circuit, comprising: an acquiring unit that acquires a first signal from a data signal based on a rising edge of a reference signal and that acquires a second signal from the data signal based on a falling edge of the reference signal; a delay adding unit that generates a rising-edge preceding signal by giving the reference signal a first variable delay, generates a rising-edge following signal by giving the rising-edge preceding signal a first fixed delay, determines the first variable delay such that a rising edge of the rising-edge preceding signal and a rising-edge of the rising-edge following signal are before and after a falling edge of the benchmark signal as a first delay, and gives the first signal the first delay and that generates a falling-edge preceding signal by giving a reference signal a second variable delay, generates a falling-edge following signal by giving the falling-edge preceding signal a second fixed delay, determines the second variable delay such that a falling edge of the falling-edge preceding signal and a falling-edge of the falling-edge following signal are before and after a falling edge of the benchmark signal as a second delay, and gives the second signal the second delay; and a data capturing unit that captures, based on the benchmark signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given.