Patent ID: 9568960
Date: 2017-02-14
CPC Classifications: G06F,H01L

Claim:
1. A semiconductor structure comprising: a substrate that includes one or more cooling layers, one or more cooling channels, one or more coolant inlets and outlets in fluid communication with the cooling channels, a device layer disposed on the cooling layers that has one or more connection points and a device layer area, wherein a device layer thermal coefficient of expansion is substantially equal to that of the one or more cooling layers; a plurality of laminate substrates arranged in an array that are disposed on, and electrically attached to, the device layer, wherein a laminate substrate thermal coefficient of expansion differs from that of the device layer, and each laminate substrate is smaller in area than an area of the device layer portion to which it is attached, and each laminate substrate includes sides with, gaps between sides of adjacent laminate substrates, wherein the laminate substrates are not electrically or mechanically connected to each other across the gaps between laminate substrates and the laminate substrates are small enough to substantially prevent warping and unacceptable stress of the device layer, interconnection and cooling layers due to thermal expansion.