Patent ID: 9543018
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A non-volatile memory, comprising: a memory array comprising at least two rows of memory cells, a line decoder common to the entire memory array, comprising a first driver coupled to a control line of a first row of the at least two rows of memory cells, a second driver coupled to a control line of a second row of the at least two rows memory cells, and a predecoder supplying the drivers with selection signals of variable polarity, either positive or negative, which are combined by the drivers to supply the control lines with control signals of variable polarity depending on the selection signals, and wherein the first driver is made in a first well in a semiconductor substrate, the second driver is made in a second well in the semiconductor substrate electrically insulated from the first well, and the at least two rows of memory cells are produced in a single memory array well in the semiconductor substrate that is electrically insulated from the first and second wells.