Patent ID: 9570550
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor device, the method comprising: forming a stack of nanowires, the stack including: a third nanowire having a third length, the third nanowire arranged above the second nanowire, wherein the forming of the stack of the nanowires comprises: forming a first layer of a first semiconductor material on a substrate; forming a first layer of a second semiconductor material on the first layer of the first semiconductor material; forming a second layer of the first semiconductor material on the first layer of the second semiconductor material; forming a second layer of the second semiconductor material on the second layer of the first semiconductor material; forming a third layer of the first semiconductor material on the second layer of the second semiconductor material; forming a third layer of the second semiconductor material on the third layer of the first semiconductor material; removing portions of the stack of semiconductor material to expose portions of the substrate and define the first nanowire comprising the first layer of the second semiconductor material, the second nanowire comprising the second layer of the second semiconductor material, and the third nanowire comprising the third layer of the second semiconductor material; forming a sacrificial gate stack over a portion of the third nanowire; forming a first spacer adjacent to the sacrificial gate stack prior to growing the source/drain regions; patterning a mask over a portion of the third nanowire; removing an exposed portion of the third nanowire; removing a portion of the mask to expose a portion of the third nanowire; removing an exposed portion of the third layer of the first semiconductor material; removing an exposed portion of the third nanowire and an exposed portion of the second nanowire; removing the mask; removing the first layer, the second layer, and the third layer of the first semiconductor material; removing the first spacer after removing the first layer, the second layer, and the third layer of the first semiconductor material; forming a second spacer adjacent to the sacrificial gate stack after removing the first spacer; growing a source/drain region on the first, second, and third nanowires; removing the sacrificial gate stack to expose channel regions of the first, second, and third nanowires; and forming a gate stack over the channel regions.