Patent ID: 9536992
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a semiconductor structure comprising a first transistor region, a second transistor region, and a silicon dioxide layer on said first transistor region and said second transistor region; depositing a layer of a high-k dielectric material on said silicon dioxide layer; forming a layer of a first metal over said second transistor region, wherein said layer of said first metal does not cover said first transistor region; after the formation of said layer of said first metal, depositing a layer of a second metal over said first transistor region and said second transistor region; performing a first annealing process, said first annealing process initiating a scavenging reaction between said second metal and silicon dioxide from a portion of said silicon dioxide layer on said first transistor region; and after said first annealing process, forming a ferroelectric transistor dielectric over said first transistor region.