Patent ID: 9691467
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. A memory including instruction codes executed by one or more microprocessors to perform operations comprising: a plurality of word lines each of which are connected to one or more memory cells, wherein each of the memory cells includes a cell transistor and a cell capacitor; performing a counting operation in response to a refresh command and generating a counting address according to a result of the counting operation; detecting a target address of a target word line among the plurality of word lines, wherein the target word line has an activation history satisfying a predetermined condition; activating a first refresh activation signal in response to the refresh command, activating a second refresh activation signal two or more times when the refresh command is applied after the target address is detected, generating a first adjacent address by subtracting 1 from the target address and a second adjacent address by add 1 to the target address, and outputting the target address, the first adjacent address or the second adjacent address; activating an active signal in response to an active command, the first refresh activation signal or the second refresh activation signal, transferring an external applied address as address signals when the active command is activated, transferring the counting address as the address signals when the first refresh activation signal is activated and transferring the generated address of one of the target address, the first adjacent address and the second adjacent address as the address signals when the second refresh activation signal is activated; and sequentially activating and precharging a word line corresponding to the transferred address signals among the plurality of word lines when the active signal is activated; wherein the predetermined condition is that a number of activations of the target word line is equal to or greater than a reference number.