Patent ID: 9548087
Date: 2017-01-17
CPC Classifications: G11C,H01L

Claim:
1. A sensing circuit for a flash memory device comprising: a reference column including a reference voltage node, a reference memory cell, a first differential threshold PMOS transistor that is diode-connected and has a drain connected to the reference voltage node, and a first differential threshold NMOS transistor having a drain connected to the reference voltage node; circuitry comprising a comparator that includes a second differential threshold NMOS transistor having a gate connected to a reference voltage line and a source connected to a first node, a third differential threshold NMOS transistor having a drain connected to the first node, a second differential threshold PMOS transistor that is diode-connected and has a drain connected to a second node, a third differential threshold PMOS transistor having a gate connected to the second node and a drain connected to a third node, a fourth differential threshold NMOS transistor having a source connected to the first node, a fourth differential threshold PMOS transistor having a gate connected to the third node and a drain connected to an output node, and a fifth differential threshold NMOS transistor having a drain connected to the output node, wherein gates of the fourth and fifth differential threshold NMOS transistors are connected to a common control line; wherein one or more of the differential threshold transistors are transistors that each have a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage; and wherein one or more of the differential threshold transistors comprises: