Patent ID: 9685443
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: an active device formed in a semiconductor layer of a first conductivity type, the active device being formed at least partially on a first buried layer of a second conductivity type; a first guard ring of the first conductivity type formed in the semiconductor layer surrounding at least part of the active device; a second guard ring formed in the semiconductor layer surrounding the first guard ring and the active device, the second guard ring comprising alternating first well regions of the first conductivity type and the second well regions of the second conductivity type along a path of the second guard ring surrounding the first guard ring, the first well regions and the second well regions being formed on a second buried layer of the second conductivity type, the first and second well regions being electrically shorted together and electrically coupled to a ground potential or floating; and a third guard ring of the first conductivity type formed in the semiconductor layer surrounding the second guard ring, wherein the first and third guard rings do not receive direct electrical connection.