Patent ID: 9641931
Date: 2017-05-02
CPC Classifications: H03F,H03K,H03M,H04R

Claim:
1. A drive circuit to which a three-value signal including a value representing 0 is input, and which outputs two two-value signals for driving two drive elements such that a difference between the values representing the two two-value signals corresponds to a value representing the three-value signal, which is input, the drive circuit is connected to a logic circuit being input the three-value signal and a memory storing a flag value of the first flag determined based on the three-value signal input to the logic circuit, the drive circuit determining a combination of the two two-value signals, which are output, according to the flag value of the first flag stored in the memory and a value of the three-value signal, which is input to the logic circuit, in the case where the value of the three-value signal represents 0.