Patent ID: 9612901
Date: 2017-04-04
CPC Classifications: G06F

Claim:
1. A system comprising: a system memory comprising memory devices to provide data storage corresponding to a range of memory addresses, a first portion of the memory addresses to be protected by an error correcting code (ECC) technique and a second portion of the memory addresses to not be protected by the ECC technique; a memory control device coupled with the system memory, the memory control device comprising a plurality of processing paths, wherein a first set of the processing paths operate to apply the ECC technique to data before storage of the data and a second set of the processing paths operate to cause the data to be stored without application of the ECC technique, the memory control device to selectively apply the ECC technique based on a per-transaction indicator of ECC/no-ECC protection so that ECC protection/no-ECC protection is implemented at per-cache line granularity and wherein an ECC protected transaction is able to target a cache line that is not ECC protected, the memory controller comprising logic to, in response to the ECC protected transaction targeting the cache line that is not ECC protected and irrespective of whether the ECC protected transaction is a read transaction or a write transaction, calculate an ECC value for the cache line and write the cache line with the ECC value into the system memory.