Patent ID: 9740518
Date: 2017-08-22
CPC Classifications: G05B,G06F

Claim:
1. A processing device, comprising: a first processor core supporting a first virtual machine; a second processor core supporting a second virtual machine; a hypervisor capable of communicating with the first and second virtual machines; a peripheral device shareable between the first and second virtual machines through an interface of the peripheral device, the interface comprising a set of registers; and a conflict detection circuit capable of communicating with the hypervisor and the first and second virtual machines, wherein the conflict detection circuit is arranged to support a first and a second virtual image of the set of registers, each virtual image containing a set of register images each mapped to corresponding ones of the set of registers, wherein the first virtual image is associated with the first virtual machine and the second virtual image is associated with the second virtual machine, wherein the conflict detection circuit is arranged to handle an access request to the peripheral device before the hypervisor by: wherein, the hypervisor is configured to merge data of the current write request with data previously stored by the first virtual machine, and to write the merged data to the peripheral device.