Patent ID: 9728512
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first well region disposed in a substrate, the first well region comprising a first doping type; a first source/drain region disposed in the first well region, the first source/drain region being coupled to a first potential node; a second source/drain region disposed in the first well region, the first and the second source/drain regions comprising a second doping type, the second doping type being opposite to the first doping type, the second source/drain region being coupled to a second potential node; an OR logic block; a first gate electrode disposed above the substrate, the first gate electrode disposed between the first and the second source/drain regions, the first gate electrode coupled to an output of the OR logic block; a pickup region disposed in the first well region, the pickup region comprising the first doping type, the pickup region coupled to an input of the OR logic block; and a body contact region comprising the first doping type and disposed in the first well region, the body contact region being coupled to the second potential node, wherein the body contact region is coupled to a body region of a transistor through a substrate resistor, wherein the pickup region is coupled to the body region of the transistor without the substrate resistor, the transistor comprising the first source/drain region and the second source/drain region, wherein the body contact region is coupled to a first portion of the first well region adjacent the first source/drain region through the substrate resistor, the substrate resistor comprising a second portion of the first well region and a portion of the substrate.