Patent ID: 9691499
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a first memory element enabled to take a first resistance value and a second resistance value different from the first resistance value; a first reference resistance element configured to have a resistance value between the first resistance value and the second resistance value; a first bit line connected to the first memory element; a second bit line connected to the reference resistance element; a first transistor, a first signal being input to a gate of the first transistor, one end of the first transistor being connected to a power supply terminal, the other end of the first transistor being connected to the first bit line; a second transistor, the first signal being input to a gate of the second transistor, one end of the second transistor being connected to the power supply terminal, the other end of the second transistor being input to the second bit line; and a first read circuit configured to sense a difference in potential between the first bit line and the second bit line to determine data read from the first memory element, wherein in a read operation on the first memory element, the first signal changes from a first logic level to a second logic level different from the first logic level in response to the determination of the data read from the first memory element, and a voltage of the first bit line transitions from a first voltage to a second voltage and a voltage of the second bit line transitions from a third voltage to the second voltage when the first signal changes to the second logic level, the third voltage is different from the first voltage.