Patent ID: 9614530
Date: 2017-04-04
CPC Classifications: H03K

Claim:
1. A buffer, comprising: a differential pair of input transistors comprising a first input transistor and a second input transistor; a first output load resistor coupled in series with the first input transistor; a second output load resistor coupled in series with the second input transistor; a first output at a first node between the first output load resistor and the first input transistor; a second output at a second node between the second output load resistor and the second input transistor; a first hold capacitor configured to be switchably coupled to the first output to provide a semi-constant voltage source to the first output via a first low-resistance path; and a second hold capacitor configured to be switchably coupled to the second output to provide a semi-constant voltage source to the second output via a second low-resistance path.