Patent ID: 9570422
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor device package comprising: a first semiconductor die having an active side, an inactive side opposite the active side, and a plurality of through-silicon vias (TSVs) conductively connecting the active side to the inactive side, the active side including logic circuitry of the first semiconductor die, the inactive side not including any logic circuitry of the first semiconductor die; a laminate layer having a side attached to the first semiconductor die at the active side thereof via a plurality of solder bumps, the laminate layer being the substrate for the first semiconductor die; a plurality of solder balls at the side of the laminate layer attached to the first semiconductor die, around the first semiconductor die, the solder balls configured to attach the semiconductor device package to an external circuit board; an overmold layer over the laminate layer and having a plurality of through-mold vias (TMVs) to which to conductively connect the semiconductor device package to another semiconductor device package; a second semiconductor die within the overmold layer and conductively connected to the laminate layer; and a plurality of exposed pads without overmold or TMVs.