Patent ID: 9613902
Date: 2017-04-04
CPC Classifications: G11C,H01L

Claim:
1. A memory array having a plurality of memory sub-arrays separated by a bare line region and a socket region, the memory array comprising: a first bundle of conductive lines extending straight and parallel to one another in a first direction and passing through the bare line region; a second bundle of conductive lines extending parallel to the first direction and passing through the socket region adjacent to the bare line region, each of the second bundle of conductive lines having a horizontal jog in the socket region; a third bundle of conductive lines extending parallel to the first direction into the socket region and terminating in the socket region, wherein at least two of the third bundle of conductive lines co-terminate at substantially the same position along the first direction and at least one of the third bundle of conductive lines does not co-terminate with the at least two conductive lines and extends farther along the first direction into the socket region; and wherein the first bundle of conductive lines are separated from the second bundle of conductive lines and the third bundle of conductive lines by a seam extending in the first direction and having a seam space width.