Patent ID: 9582283
Date: 2017-02-28
CPC Classifications: G06F

Claim:
1. A microprocessor core comprising: a plurality of registers in which commands are received and processed, the plurality of registers being scalable and configurable by a user; a point-to-point transport network coupled to the plurality of registers, the point-to-point transport network interfacing directly with each register within the plurality of registers and providing point-to-point communication between a routine source register and a routine destination register; a decoder, coupled to the point-to-point transport network and program memory, the decoder configured to decode data fetched from the program memory and transmit this decoded data to at least one register within the plurality of registers; and a memory management unit, coupled to the program memory, data memory and at least one register within the plurality of registers, the memory management unit creating a virtual memory map by combining at least a portion of the program memory and at least a portion of the data memory.