Patent ID: 9647013
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A manufacturing method of a TFT array substrate, the TFT array substrate being formed to comprise a plurality of scanning lines, a plurality of data lines and a plurality of pixel units defined by intersecting these scanning lines and these data lines with each other, each of the pixel units comprising a TFT and a pixel electrode, the TFT being formed to comprise: a gate electrode, a gate insulating layer, a metal oxide semiconductor layer used as an active layer, an etch stopping layer formed on a portion of the surface of the metal oxide semiconductor layer, a source electrode and a drain electrode, wherein the metal oxide semiconductor layer, the source electrode and the drain electrode are formed by a same patterning process using one single-tone mask, during the same patterning process using one single-tone mask for forming the metal oxide semiconductor layer, the source electrode and the drain electrode, the metal oxide semiconductor layer is formed at the same time of forming the source electrode and the drain electrode, the source electrode and the drain electrode directly contact a portion of the metal oxide semiconductor layer, and during the same patterning process using one single-tone mask for forming the metal oxide semiconductor layer, the source electrode and the drain electrode, a portion of the metal oxide semiconductor layer which is directly opposite to the gate electrode is completely remained.