Patent ID: 9634019
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method of forming a pair of memory cells, comprising: forming a polysilicon layer over and insulated from a semiconductor substrate; forming a pair of spaced apart conductive control gates over and insulated from the polysilicon layer, wherein the control gates having inner side surfaces facing each other and outer side surfaces facing away from each other; forming a first insulation layer that extends directly along the inner and outer side surfaces of the control gates; forming a second insulation layer that extends directly along the first insulation layer; removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates; forming first insulation spacers that extend directly along the second insulation layer and indirectly along the outer side surfaces of the control gates; forming second insulation spacers that extend directly along the second insulation and indirectly along the inner side surfaces of the control gates; forming an HKMG layer extending along the first and second insulation spacers and along portions of the substrate adjacent the outer side surfaces of the control gates, wherein the HKMG layer includes: removing portions of the HKMG layer extending along the second insulation spacers; removing the second insulation spacers; removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates; forming a source region in the substrate adjacent the inner side surfaces of the control gates; forming a conductive erase gate over and insulated from the source region, wherein the erase gate is insulated from each of the control gates by at least the first insulation layer and the second insulation layer; forming conductive word line gates laterally adjacent to the first insulation spacers, wherein for each of the word line gates, the HKMG layer includes a first portion disposed between the word line gate and one of the first insulation spacers and a second portion disposed between the word line gate and the substrate; and forming drain regions in the substrate each disposed adjacent to one of the word line gates.