Patent ID: 9659601
Date: 2017-05-23
CPC Classifications: G11C

Claim:
1. A memory module operable in a computer system with a system memory controller, comprising: a register device to receive first input command/address signals from the system memory controller and to output first control signals in response to the first input command/address signals; and a plurality of DRAM packages, each DRAM package comprising: data terminals via which the each DRAM package communicates data signals with the system memory controller, and control terminals via which the each DRAM package receives the first control signals from the register device; stacked array dies including a first group of array dies and a second group of at least one array die; die interconnects including first die interconnects and second die interconnects, the first die interconnects in electrical communication with the first group of array dies and not in electrical communication with the second group of at least one array die, the second die interconnects in electrical communication with the second group of at least one array die and not in electrical communication with the first group of array dies; and a control die including first data conduits between the first die interconnects and the data terminals, and second data conduits between the second die interconnects and the data terminals, the first data conduits including first drivers, the second data conduits including second drivers, the first drivers and the second drivers being controlled in accordance with the first control signals such that the first drivers drive first data signals corresponding to the first input command/address signals and the second drivers do not drive the first data signals.