Patent ID: 9548308
Date: 2017-01-17
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising a first memory comprising: a first transistor, a second transistor, a third transistor, and a fourth transistor electrically connected to each other in series in order; and a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor electrically connected to each other in series in order, wherein one of a source and a drain of the first transistor and one of a source and a drain of the fifth transistor are electrically connected to a high power supply potential line, wherein one of a source and a drain of the fourth transistor and one of a source and a drain of the eighth transistor are electrically connected to a low power supply potential line, wherein a gate of the second transistor, a gate of the third transistor, a gate of the sixth transistor, and a gate of the seventh transistor are electrically connected to a first terminal, wherein a gate of the fifth transistor and a gate of the eighth transistor are electrically connected to a second terminal, wherein the second terminal is electrically connected between the second transistor and the third transistor, wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to a third terminal, wherein the third terminal is electrically connected between the sixth transistor and the seventh transistor, wherein each of the first transistor and the fifth transistor is a p-channel transistor, wherein each of the second transistor, the third transistor, the sixth transistor, and the seventh transistor is a transistor comprising an oxide semiconductor layer, and wherein each of the fourth transistor and the eighth transistor is an n-channel transistor.