Patent ID: 9711644
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A method of forming a transistor device, the method comprising: forming a trench in a semiconductor substrate, said trench having an exposed interior surface; after forming said trench having said exposed interior surface, forming a liner semiconductor material above the entire exposed interior surface of said trench, said liner semiconductor material defining a transistor cavity; forming a plurality of spaced-apart source/drain placeholder structures that are at least partially positioned within said transistor cavity, said spaced-apart source/drain placeholder structures defining a gate cavity therebetween where a portion of said liner semiconductor material is exposed within said gate cavity; forming a gate structure that is at least partially positioned within said gate cavity; after forming said gate structure, removing at least a portion of said source/drain placeholder structures to define a plurality of source/drain cavities within said transistor cavity on opposite sides of said gate structure; and forming a source/drain structure in each of said source/drain cavities, wherein at least a portion of each of said source/drain structures is positioned within said transistor cavity.