Patent ID: 9548317
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor structure, comprising: (a) providing a substrate, which comprises, from bottom to top, a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; (b) implementing ion implantation doping to the buried ground layer; (c) forming a gate stack, sidewall spacers and source/drain regions on the substrate; (d) forming a mask layer on the substrate to cover the gate stack and source/drain regions, and etching the mask layer to expose the source region; (e) etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; and (f) filling the opening by an epitaxial process to form a contact plug for the buried ground layer.