Patent ID: 9722083
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method of forming a source/drain region for a transistor, comprising: forming a first recess in a substrate; epitaxially growing a first semiconductor material in the first recess; performing a first plasma implant comprising a pre-amorphization implant to the first semiconductor material; following the first plasma implant, performing a second plasma doping comprising doping the first semiconductor material with phosphorus to form a first ultra-shallow junction in a first source/drain region, wherein the second plasma doping of the phosphorous is performed at a continuously decreasing energy level; after the second plasma doping, forming a silicide layer over the first source/drain region; and performing a microwave anneal on the first source/drain region at a first temperature between 300 and 600 degrees Celsius, wherein the microwave anneal substantially repairs damaged portions of a crystalline structure of the first source/drain region, wherein a concentration of the phosphorus at the first ultra-shallow junction is between about 2.0×10