Patent ID: 9698243
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method of forming a transistor device, comprising: forming a substantially v-shaped source/drain recess within a semiconductor substrate; forming outer un-doped strain-inducing regions in outermost lateral tips of the substantially v-shaped source/drain recess, the outer un-doped strain-inducing regions having a first strain-inducing component at a first concentration; and forming an intermediate un-doped strain-inducing region which extends along a lower angled sidewall of the substantially v-shaped source/drain recess and which extends between the outer un-doped strain-inducing regions without completely filling the substantially v-shaped source/drain recess, the intermediate un-doped strain-inducing region having a second strain-inducing component at a second concentration that is greater than the first concentration.