Patent ID: 9726723
Date: 2017-08-08
CPC Classifications: G01R,G06F

Claim:
1. A method for scanning a partially functional chip, the method comprising: performing a testing operation on the partially functional chip; receiving, into a set of scan status registers within the partially functional chip, a failed core bitmap produced by the testing operation and containing a plurality of bits that represent the functional status of cores of the partially functional chip; applying the failed core bitmap to the partially functional chip; bypassing, with a bypass logic, based on contents of the failed core bitmap, a failed core scan chain having a pad latch between a plurality of core scan latches, the failed core scan chain having a fail latch, adjacent to the plurality of core scan latches, configured to indicate a functional status of a core; filling, using an input gating logic coupled to the bypass logic, the plurality of core scan latches of a failed core with a constant logic value; inserting, using an output gating logic coupled to the bypass logic, a constant logic value in place of output values of the plurality of core scan latches; performing a comparison of scan status information to the failed core bitmap; and inhibiting, based on results of the comparison, movement of scan data from the failed core.