Patent ID: 9690898
Date: 2017-06-27
CPC Classifications: G03F,G06F

Claim:
1. A semiconductor device design layout generation computer program product stored on non-transitory computer readable storage media in the form of computer executable code including instructions that when executed by a computing device cause the computing device to perform a method comprising: applying a generative model to generate a plurality of candidate layout images based on at least a feature library including features extracted from known layouts, the features being represented by respective feature images in a first colorspace and the plurality of candidate layout images being in a second colorspace, each candidate layout image including at least one respective probabilistic layout image in the second colorspace; ranking the plurality of candidate layout images based on a first difference value representing a degree of difference between each candidate layout image and the feature images in the feature library; removing any candidate layout image having a first difference value below a predefined minimum first difference threshold to form a culled group of candidate layout images; performing a repair procedure on the culled group to produce a plurality of compliant candidate layout images in the first colorspace; and ranking the plurality of compliant candidate layout images based at least in part on a respective second difference value representing a degree of difference between each compliant candidate layout image and the feature images of the feature library.