Patent ID: 9666606
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; and a capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein a gate of the first transistor is electrically connected to the first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring, wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the third transistor is electrically connected to a third wiring, wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth wiring, wherein one electrode of the capacitor is electrically connected to the gate of the third transistor, and wherein the other electrode of the capacitor is electrically connected to the other of the source and the drain of the third transistor.