Patent ID: 9590102
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising: forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer; forming an isolation insulating layer so that the channel layer of the fin structure protrudes from the isolation insulating layer and at least a part of the oxide layer or an entirety of the oxide layer is embedded in the isolation insulating layer; forming a gate structure over a part of the fin structure and over the isolation insulating layer; forming a recessed portion by etching a part of the fin structure not covered by the gate structure to expose the oxide layer; forming a recess in the exposed oxide layer by removing a portion of the exposed oxide layer; forming a seed layer for epitaxial growth in the recess in the oxide layer; and forming an epitaxial layer in and above the recessed portion, wherein the epitaxial layer is in contact with the seed layer.