Patent ID: 9620183
Date: 2017-04-11
CPC Classifications: G11C,H01L

Claim:
1. A method comprising: performing at least one of a data eye training operation or a memory array timing training operation at a memory vault controller (MVC) associated with a first stacked-die memory vault, the first stacked-die memory vault comprising a plurality of memory arrays, the plurality of memory arrays located on a plurality of stacked memory dies, the plurality of stacked memory dies including a first memory die and a second memory die, the plurality of memory arrays of the first stacked-die memory vault including a first memory array and a second memory array, the first memory array located on the first memory die, the second memory array located on the second memory die, the first memory die further including a third memory array, the second memory die further including a fourth memory array, the third and fourth memory arrays forming a second stacked-die memory vault, wherein performing the at least one of the data eye training operation or the memory array timing training operation at the MVC includes: at least one of adjusting a delay associated with a data clock used to clock a plurality of data bits to a transmit register using a first series of iterations or adjusting a delay associated with a data strobe used to strobe the plurality of data bits to a receive register using a second series of iterations; determining whether the data bits are successfully received at the receive register; and selecting at least one of an operational delay associated with the data clock or an operational delay associated with the data strobe in accordance with the determining act.