Patent ID: 9627290
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first metal pad directly on a top surface of a substrate; a passivation layer directly disposed on the top surface of the substrate and on a top surface of the first metal pad; a first polymer layer over the first metal pad and the passivation layer, wherein the first polymer layer is in direct contact with the first metal pad; a second polymer layer over the first polymer layer, wherein the second polymer layer does not directly contact the first metal pad; a third polymer layer over the second polymer layer; and a bump formed in an opening through the first polymer layer, the second polymer layer and the third polymer layer, wherein the second polymer layer extends into the opening, the third polymer layer extends into the opening and a portion of the second polymer layer within the opening is in direct contact with the first polymer layer; a second metal pad spaced a distance from the first metal pad, the second metal pad directly on the top surface of the substrate, and wherein the passivation layer is disposed directly on the top surface of the second metal pad; a first post-passivation interconnect (PPI) on the second metal pad, wherein a first portion of the first PPI interposes the first and the second polymer layers such that the first PPI interfaces the top surface of the first polymer layer and a bottom surface of the second polymer layer an under-bump metallurgy (UBM) layer is disposed between the bump and the metal pad, wherein the UBM layer is disposed between sidewalls of the bump and the second polymer layer.