Patent ID: 9620500
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A series-connected transistor structure, comprising: a first source over a substrate; a second source over the substrate and laterally adjacent to the first source; an isolation portion between the first source and the second source to electrically isolate the first source from the second source; a second channel-drain structure over the first source, the second channel-drain structure comprising a second channel and a second drain over the second channel; a third channel-drain structure over the second source and substantially parallel to the second channel-drain structure, the third channel-drain structure comprising a third channel and a third drain over the third channel; a gate dielectric layer surrounding the second channel and the third channel; a continuous gate surrounding the gate dielectric layer; and a second drain pad over and in contact with the second drain and the third drain.