Patent ID: 9704953
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductor layer of a first conductivity type including a plurality of first semiconductor regions of the first conductivity type, each of the first semiconductor regions extending in a first direction, the first semiconductor regions being arranged in a second direction orthogonal to the first direction, each of the first semiconductor regions extending in a third direction orthogonal to the first direction and the second direction; a plurality of second semiconductor regions of a second conductivity type, each of the second semiconductor regions extending in the first direction and the third direction, the first semiconductor regions and the second semiconductor regions being provided alternately in the second direction; a plurality of third semiconductor regions of the second conductivity type, each of the third semiconductor regions extending in the first direction, the third semiconductor regions being respectively provided on the second semiconductor regions, an impurity concentration of the second conductivity type of the third semiconductor region being higher than an impurity concentration of the second conductivity type of the second semiconductor regions; a plurality of fourth semiconductor regions of the second conductivity type, each of the fourth semiconductor regions extending in the second direction, the fourth semiconductor regions being arranged in the third direction, each of the fourth semiconductor regions provided on the first semiconductor regions and the third semiconductor regions; a plurality of fifth semiconductor regions of the first conductivity type, each of the fifth semiconductor regions extending in the second direction, the fifth semiconductor regions being arranged in the third direction, the fifth semiconductor regions being respectively provided on the fourth semiconductor regions; a plurality of gate electrodes, each of the gate electrodes extending in the second direction, the gate electrodes being arranged in the third direction, the gate electrodes being provided on the fourth semiconductor regions and the fifth semiconductor regions with gate insulation layers interposed, each of the gate electrodes being provided on the first semiconductor regions and the third semiconductor regions; and a sixth semiconductor region of the first conductivity type contacting the semiconductor layer, the sixth semiconductor region opposing to the gate electrodes in the first direction, an impurity concentration of the first conductivity type of the sixth semiconductor region being higher than an impurity concentration of the first conductivity type of the semiconductor layer.