Patent ID: 9691904
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: an insulating layer; a metal oxide layer over the insulating layer; a first electrode and a second electrode over and electrically connected to the metal oxide layer; a gate electrode over the metal oxide layer; and a gate insulating layer between the metal oxide layer and the gate electrode, wherein the insulating layer includes a projecting portion, wherein a top surface of the projecting portion is positioned inside an outline of the metal oxide layer when seen in a plan view, wherein the first electrode and the second electrode cover first parts of a top surface and first parts of side surfaces of the metal oxide layer, and first side surfaces of the projecting portion, wherein a bottom surface of the gate electrode is positioned below the top surface of the projecting portion, and wherein the gate electrode and the gate insulating layer cover a second part of the top surface and second parts of the side surfaces of the metal oxide layer and second side surfaces of the projecting portion of the insulating layer.