Patent ID: 9582359
Date: 2017-02-28
CPC Classifications: G06F,G11C,H03M

Claim:
1. A method for mitigating hard errors, comprising the steps of: creating a plurality of inter-bit dependencies between a current bit in a sequence of data bits and a plurality of neighboring bits in the sequence of data bits to generate a plurality of mapped bits; writing the plurality of mapped bits among at least two cells of a plurality of memory cells in a memory with at least two of the plurality of mapped bits stored in each of the plurality of memory cells; generating a plurality of log-likelihood ratio values in response to reading the plurality of mapped bits from the memory, wherein each of the log-likelihood ratio values is based on two or more of the mapped bits and is representative of the plurality of inter-bit dependencies, and the plurality of inter-bit dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state; and decoding the plurality of mapped bits based on the plurality of log-likelihood ratio values to recover the current bit.