Patent ID: 9672321
Date: 2017-06-06
CPC Classifications: G06F

Claim:
1. A system to perform physical synthesis of a chip design, the system comprising: a memory device configured to store instructions; and a processor configured to execute the instructions to perform a baseline synthesis to determine timing slack associated with each of a plurality of devices, the timing slack indicating a margin by which timing requirements for the associated device are exceeded, analyze a histogram of the timing slack to determine whether a threshold that indicates a spread of the timing slack among the plurality of devices has been exceeded, and when the threshold has been exceeded, execute a stage-by-stage physical synthesis that includes running a stage of the stage-by-stage physical synthesis to determine real timing slack, mapping the real timing slack to virtual timing slack that is lower than the real timing slack, and running a next stage of the stage-by-stage physical synthesis using the virtual timing slack.