Patent ID: 9735057
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method comprising: fabricating a field effect transistor, the field effect transistor comprising a source region and a drain region separated by a channel region with a gate structure overlying an upper surface of the channel region, and the fabricating comprising: wherein the first material comprises a phase of silicon and silicon doped with phosphorous with a crystal lattice structure, and the second material comprises the phase of silicon and the silicon doped with phosphorous of the first material with the crystal lattice structure of the first material and a second dopant that is not present in the first material disposed interstitially with respect to the crystal lattice structure, wherein the first portion is formed within at least one cavity adjacent the channel region that extends from the upper surface of the channel region, and wherein the first portion extends above the upper surface of the channel region.