Patent ID: 9653450
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. An electrostatic discharge (ESD) protection semiconductor device comprising: a substrate; a gate set formed on the substrate; a source region and a drain region formed in the substrate respectively at two sides of the gate set, and the source region and the drain region comprising a first conductivity type, wherein the drain region is electrically connected to an input/out (I/O) pad; at least a first doped region formed in the drain region; the first doped region comprising a second conductivity type complementary to the first conductivity type, and the first doped region being electrically connected to a ground potential, wherein the gate set is disposed in between the source region and the first doped region; and a first blocking structure surrounding the first doped region and isolating the first doped region from the drain region.