Patent ID: 9703916
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. A method comprising: incorporating, by a computing system, a validation system into a circuit design, wherein the validation system includes multiple validation devices configured to monitor at least a portion of an electronic device described in the circuit design, and wherein the validation devices are arranged in a serial pipelined configuration with each of the validation devices configured to transmit signals on each of a plurality of communication buses; identifying, by the computing system, trace signals associated with the electronic device to route to the validation system; and configuring, by the computing system over one of the communication buses in the serial pipelined configuration, the validation system to detect one or more conditional events from one or more trigger signals routed to the validation system from the electronic device, wherein the validation system is configured to transmit at least one of the trace signals associated with the electronic device, over another one of the communication buses in the serial pipelined configuration, for debugging in response to a detection of at least of the conditional events.