Patent ID: 9575880
Date: 2017-02-21
CPC Classifications: G06F,G11C

Claim:
1. A semiconductor memory device comprising: a memory bank including a first section and a second section, each of which being comprised of a plurality of memory cells and a first word line of the first section and a second word line of the second section being different from each other; a row decoder configured to activate the first word line and the second word line such that a first activated period of the first word line overlaps with a second activated period of the second word line; an LIO (Local input and output) line switching circuit configured to generate first and second selection signals, the first selection signal being activated while the first word line is activated, and the second selection signal being activated while the second word line is activated; and an input/output (I/O) circuit configured to access the first section based on the first selection signal and access the second section based on the second selection signal.