Patent ID: 9703899
Date: 2017-07-11
CPC Classifications: G06F,H05K

Claim:
1. A product synthesis process for generation of an electronic system, the electronic system having a power source selected from a family of power sources, each possible power source having a cost/size/performance attribute, the electronic system also having power distribution, system clock distribution, and a CPU selected from a family of CPUs, each CPU in said family of CPUs having a cost attribute, size attribute, and performance attribute, each possible CPU also having connectivity to at least one interface, the product synthesis process comprising: an interface selection step for the selection of one or more interfaces, each interface having an associated schematic symbol, a PCB symbol, a mechanical model, a cost attribute, size attribute, and performance attribute, each interface having an interface type which matches the available connectivity of said CPU interface type; a constraint identification step for the selection of one or more constraints, including the identification of a power source type, and an optional performance requirement, cost requirement, or low power requirement, each constraint having a weight which indicates a relative importance; a schematic generation step whereby a netlist describing the component interconnects is generated from said selected CPU, said selected power source, and said selected interface; a printed circuit board (PCB) placement step whereby PCB symbols associated with each said selected interface and said selected CPU are provided in a proposed PCB placement for rearrangement according to a user requirement; a PCB routing step whereby electrical connectivity is provided for said PCB using interconnecting traces on said PCB; a mechanical packaging step whereby mechanical enclosure files are generated, said mechanical enclosure files describing an enclosure which accommodates and provides mounting for the printed circuit board of said PCB placement step, said mechanical enclosure files describing one or more apertures positioned in a corresponding locations identified in said mechanical model for each said interface; an API generation step whereby an application program interface is generated which enables a program written for said CPU to access or control at least one of said interfaces; an optimization step operative on a weighted constraint for each of cost, size, and performance, and iteratively performed whereby the associated cost metric, size metric, and performance metric are multiplied by an associated constraint weight, thereby providing each possible unique combination of selected CPU, selected interface, and said mechanical enclosure with a final metric based on the application of said weighted constraints, thereafter presenting a candidate design based on a best final metric.