Patent ID: 9576646
Date: 2017-02-21
CPC Classifications: G11C

Claim:
1. A memory cell, comprising: a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline; a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline; and a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR), the GNDL being connected to a transistor of a first inverter of the cross coupled inverters and the GNDR being connected to a first transistor of a second inverter of the cross coupled inverters, wherein during read access for the second bitline, the GNDL is raised by about 10% of Vdd above GND and/or GNDR is lowered by about 10% of Vdd below GND.