Patent ID: 9647672
Date: 2017-05-09
CPC Classifications: H03L

Claim:
1. A digitally compensated phase locked oscillator (DCPLO), comprising: a DCPLO input for receiving a reference signal at a known frequency; a DCPLO output for outputting a signal at a desired frequency; a phased locked loop (PLL), the phased locked loop comprising: a first direct digital synthesizer (DDS), the first DDS having an output coupled to the PLL to supply a DDS signal to the PLL for adjusting a frequency within the PLL; a temperature sensor; a processor coupled to the first DDS, the phase frequency detector, and the temperature sensor; and a second DDS having an input coupled to the processor and having a second DDS frequency that is set based on a frequency setting of the first DDS, the processor configured to set the frequency of the first DDS according to a temperature sensed by the temperature sensor, and to offset the frequency of the PLL using the second DDS frequency, so as to maintain the PLL in a phase locked state and at a lowest phase noise within an operational temperature range of the DCPLO.