Patent ID: 9684623
Date: 2017-06-20
CPC Classifications: G06F,Y02D

Claim:
1. An integrated circuit chip comprising: core circuitry to output data in parallel along a set of data paths; interface circuitry coupled to the core circuitry, the interface circuitry to receive in parallel a first portion of the data from a first number of the data paths from the core circuitry and to output in parallel the first portion of the data along a second number of output pins that are less than the first number of data paths, wherein the ratio of the first number to the second number is a non-power-of-2 value; and clock logic coupled to the core circuitry and the interface circuitry, the clock logic to generate a first clock signal for the core circuitry, and a second clock signal for the interface circuitry, wherein the first clock signal and the second clock signal are derived from a bit rate clock signal.