Patent ID: 9614056
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of forming a tri-gate FinFET device, comprising: forming a fin that is positioned above and vertically spaced apart from an upper surface of a semiconductor substrate, said fin having an upper surface, a lower surface opposite of said upper surface, a first side surface, and a second side surface opposite of said first side surface, wherein an axis of said fin in a height direction of said fin is oriented substantially parallel to said upper surface of said substrate, and wherein an entirety of said first side surface of said fin contacts and is completely covered by a first insulating material that is formed above said semiconductor substrate and laterally adjacent to said first side surface of said fin; forming a gate structure around said fin, wherein said gate structure covers at least a portion of said upper surface, said second side surface and said lower surface of said fin but does not cover any portion of said first side surface of said fin; and forming a gate contact structure that is conductively coupled to said gate structure.