Patent ID: 9576958
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A semiconductor structure comprising: a semiconductor substrate wherein the semiconductor substrate includes at least one nFET and at least one pFET; an interfacial layer on the semiconductor substrate and the at least one nFET and the at least one pFET; a gate dielectric layer on the interfacial layer; a pFET work function metal layer on a portion of the gate dielectric layer over an area above the pFET wherein the area above the pFET includes at least the area over the pFET; a nFET work function metal layer on a portion of the gate dielectric layer over an area above the nFET wherein the area above the nFET includes at least the area over the nFET and on the pFET work function metal layer in the area above the pFET wherein the area above the pFET includes at least the area over the pFET; a gate electrode metal on the nFET work function metal layer; and