Patent ID: 9704561
Date: 2017-07-11
CPC Classifications: G11C

Claim:
1. A device comprising: an active area having a square shape, the active area being divided into first, second, third, fourth, fifth, sixth, seventh, eighth and ninth regions arranged in a matrix, the first, second, third and fourth regions being arranged at respective corners of the square, the fifth region being arranged at a center of the matrix, and the sixth, seventh, eighth and ninth regions being arranged between the first and second regions, the second and third regions, the third and fourth regions and the fourth and first regions, respectively; a plurality a memory arrays each including a plurality of memory cells arranged in each of the first, second, third and fourth regions; a plurality of data terminals arranged in the eighth region; a first switching buffer coupled between a data node of one of the memory arrays and one of the data terminals, the first switching buffer being arranged in the seventh region; and a second switching buffer coupled between the data node of the one of the memory cell arrays and a different one of the data terminals, the second switching buffer being arranged in the seventh region.