Patent ID: 9613960
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor structure having a plurality of FinFETs, comprising: providing a semiconductor substrate having a first region and a second region; forming at least a first fin on the semiconductor substrate in the first region and at least a second fin on the semiconductor substrate in the second region; forming a first gate structure over the first fin and a second gate structure over the second fin; forming a first stress layer on the first fin at both sides of the first gate structure and a first cover layer layered on the first stress layer in the first region; forming a second stress layer on the second fin at both sides of the second gate structure and a second cover layer layered on the second stress layer in the second region; performing a first potential barrier reducing ion implantation process on the first cover layer, layered on the first stress layer in the first region; performing a second potential barrier reducing ion implantation process on the second cover layer, layered on the second stress layer in the second region; and forming a first contact layer on the first cover layer and a second contact layer on the second cover layer.