Patent ID: 9652231
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. An apparatus, comprising: a floating point vector register file containing at least two floating point registers; a permute unit coupled to the floating point vector register file, the permute unit having at least two operand inputs for receiving input operands containing data to be permuted from the at least two floating point registers, the at least two floating point registers being vector registers each having at least four vector elements, and at least one control vector input for receiving a control vector indicating a permutation pattern as a floating point vector, the control vector comprising a plurality of control vector elements, wherein each of the vector elements of the at least two floating point registers, and each of the control vector elements of the control vector, stores a floating point value comprising a mantissa and an exponent; and a result vector register coupled to the permute unit, wherein the permute unit generates a result output, that is stored in the result vector register, based on a permutation operation performed by the permute unit on the input operands according to the control vector, wherein the permutation operation provides an all-to-all permutation of the input operands such that any vector element of any of the input operands may be selected for storing in any vector element of the result vector register, wherein each control vector element of the control vector comprises exponent bits and mantissa bits, and a portion of the permutation pattern associated with each control vector element of the control vector is encoded by way of at least one of high-order mantissa bits of the mantissa bits of that control vector element and an exponent value of the exponent bits of that control vector element, or low-order mantissa bits of the mantissa bits of that control vector element and an exponent value of the exponent bits of that control vector element.