Patent ID: 9735174
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device comprising a capacitor structure, the method comprising the steps of: providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over said substrate and a semiconductor layer formed over said BOX layer; forming an isolator structure in said wafer to define a first region of said wafer and a second region of said wafer; removing said semiconductor layer in said first region of said wafer to expose an upper surface of said BOX layer; removing said semiconductor layer and said BOX layer in a first portion of said second region adjacent to said isolator structure while maintaining said semiconductor layer and said BOX layer in a second portion of said second region adjacent to said first portion; forming a dielectric layer over said exposed upper surface of said BOX layer in said first region; forming a conductive layer over said dielectric layer; and forming a transistor device in at least one of said second portion of said second region of said wafer and a third region of said wafer that is electrically isolated from at least one of said first region and said second region, wherein a gate electrode of said transistor device comprises a part of said conductive layer and a gate dielectric of said transistor device comprises a part of said dielectric layer.