Patent ID: 9728270
Date: 2017-08-08
CPC Classifications: G11C

Claim:
1. A device comprising: a first circuit configured to temporarily store information represented by a plurality of bits, each of the plurality of bits taking one of first and second levels; a second circuit configured to detect a number of bits of the plurality of bits that each takes the first logic level; a plurality of fuses provided correspondingly to the plurality of bits; and a third circuit configured to blow up one or ones of the plurality of fuses corresponding to the bit or bits each taking the first logic level when the number of the bits each taking the first logic level is not larger than a number of bits of the plurality of bits that each takes the second logic level and to blow up one or more of the plurality of fuses corresponding to the bit or bits each taking the second logic level when the number of the bits each taking the first logic level is larger than the number of bits each taking the second logic level.