Patent ID: 9575386
Date: 2017-02-21
CPC Classifications: G02F,H01L

Claim:
1. A thin film transistor substrate comprising: a base substrate; a display area including a plurality of pixels, wherein the pixels are connected to gate lines and data lines; a gate driver connected to the gate lines; a plurality of data pads connected to the data lines; a plurality of dummy pattern parts disposed on the base substrate and comprising a plurality of dummy patterns spaced apart by a predetermined distance and electrically isolated from each other and formed of a same layer as the gate lines; a planarization layer disposed on the base substrate in spaces between adjacent dummy patterns; and a non-display area in which the gate driver, data pads, and dummy pattern parts are disposed, wherein the dummy pattern parts are disposed in an area within the non-display area where the gate driver is not disposed, and one of the dummy pattern parts is disposed overlapping with the data pads, and wherein the planarization layer has a thickness that is less than a step difference, wherein the step difference is defined by a height difference between an upper surface of the base substrate and an upper surface of the dummy patterns.