Patent ID: 9640546
Date: 2017-05-02
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate having a main surface; and a first nonvolatile memory cell and a second nonvolatile memory cell formed on the main surface of the semiconductor substrate, each of the first and second nonvolatile memory cells including a first MIS transistor for storing data and a second MIS transistor for selecting the first MIS transistor; wherein a first gate electrode of the first MIS transistor of the first nonvolatile memory cell and a first gate electrode of the first MIS transistor of the second nonvolatile memory cell extend in a first direction so as to sandwich a common source region of the first MIS transistors of the first and second nonvolatile memory cells in a plan view, wherein the first gate electrode of the first MIS transistor of the first nonvolatile memory cell has a first contact portion extending in a second direction substantially perpendicular to the first direction in the plan view to provide an electrical contact thereto, and the first contact portion extends to be adjacent to the first gate electrode of the first MIS transistor of the second nonvolatile memory cell, wherein the first gate electrode of the first MIS transistor of the second nonvolatile memory cell has a second contact portion extending in the second direction in the plan view to provide an electrical contact thereto, and the second contact portion extends to be adjacent to the first gate electrode of the first MIS transistor of the first nonvolatile memory cell, and wherein the first contact portion and the second contact portion are arranged in an offset relation to each other in the first direction and in an overlap relation in the second direction, so that a portion of an edge of the first contact portion faces, and is spaced apart from in the first direction, a portion of an edge of the second contact portion in an opposing relationship.