Patent ID: 9582411
Date: 2017-02-28
CPC Classifications: G06F,G11C

Claim:
1. A memory controller comprising: a host interface configured to electronically receive host computer data from a host computer along with a writing command that instructs the memory controller to perform a writing process, the writing command includes a logical block address and a logical page address; a substitution processing unit configured to electronically convert the logical page address into a physical page address and to electronically convert the logical block address into a physical block address, the physical block address identifies a location of a data storing block in memory and the physical page address identifies a location of a data storing page in the data storing block; and a memory interface configured to electronically send the host computer data to the memory during the writing process, the memory controller is configured to control a writing of the host computer data to the data storing page during the writing process, wherein the memory controller is configured to electronically determine whether or not a writing error has occurred during the writing of the host computer data to the data storing page, the memory controller is configured to electronically determine whether or not an unused substitution page exists in the data storing block when the writing error has occurred during the writing of the host computer data to the data storing page.