Patent ID: 9747118
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. A method comprising: decoding, by decode circuitry of a processor, a first macro-instruction first issued by a guest of a virtual machine managed by a virtual machine monitor, -into a first group of micro-instructions, using a read-only micro-instruction storage, the read-only micro-instruction storage storing native microcode to support a native instruction set architecture of the processor, wherein the virtual machine including its guest and the virtual machine monitor are all running on the processor, the first macro-instruction is first issued by the guest on transfer of control of the processor to the guest from the virtual machine monitor, after the virtual machine monitor storing guest-specific microcode into a writeable micro-instruction storage; executing, by the processor, the first group of micro-instructions in response to the first issue of the first macro-instruction to execute the first issue of the first macro-instruction in a first way; determining, by multiplexing circuitry of the processor based on a multiplexer control indicator, without exiting the virtual machine, that the first macro-instruction from a second issuance by the guest is to be decoded using writeable micro-instruction storage instead of the read-only micro-instruction storage, wherein the multiplexer control indicator is set on detecting a condition indicating that a modification to behavior of the guest is desired; the first macro-instruction is second issued by the guest, on transfer of control of the processor from the virtual machine monitor to the guest, after the multiplexer control indicator is set by the virtual machine monitor to indicate that the first macro-instruction is to be decoded using the writeable micro-instruction storage to allow the processor to execute the first macro-instruction as an instruction not in the native instruction set architecture of the processor, wherein the multiplexer control indicator is set by the virtual machine monitor on detecting a condition indicating that a modification to the behavior of the guest is desired; decoding, by the decode circuitry, without exiting the virtual machine, the first macro-instruction from the second issuance-, into a second group of micro-instructions different from the first group of micro-instructions, using the guest-specific microcode in the writeable micro-instruction storage; and executing, by the processor, without exiting the virtual machine, the second group of micro-instructions in response to the first macro-instruction from the second issuance to allow the processor to execute the first macro-instruction from the second issuance, in a second way that is different from the first way.