Patent ID: 9537425
Date: 2017-01-03
CPC Classifications: H02M,Y02B

Claim:
1. A multilevel inverter comprising: a first half bridge connected in series with a second half bridge, the first and second half bridges each comprising a semiconductor-based switch having a channel, the semiconductor-based switch being configured to block a substantial voltage in a first direction during a first mode of operation, to conduct substantial current through the channel in the first direction during a second mode of operation, and to conduct substantial current through the channel in a second direction during a third mode of operation, wherein during the third mode of operation a gate of the semiconductor-based switch is biased relative to a source of the semiconductor-based switch at a voltage that is less than a threshold voltage of the semiconductor-based switch; a third half bridge having a low-side switch coupled to a high-side switch; and a first filter and a second filter, wherein the first filter is coupled between an output node of the first half bridge and a power terminal of the high-side switch, the first filter being directly connected to ground, and wherein the second filter is coupled between an output node of the second half bridge and a power terminal of the low-side switch, the second filter being directly connected to ground, such that the low-side switch and the high-side switch of the third half bridge are to be switched at a substantially lower frequency than a switching frequency of the semiconductor-based switch.