Patent ID: 9698149
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A non-volatile memory, comprising: a first column of non-volatile storage elements including a first set of charge storage regions arranged in a column direction and separated from a surface of a substrate by a tunnel dielectric and a first set of intermediate dielectric regions overlying the first set of charge storage regions; a second column of non-volatile storage elements adjacent to the first column of non-volatile storage elements in a row direction, the second column including a second set of charge storage regions separated from the surface of the substrate by a tunnel dielectric and a second set of intermediate dielectric regions overlying the second set of charge storage regions; an isolation region in the substrate between an active area underlying the first column of non-volatile storage elements and an active area underlying the second column of non-volatile storage elements; a bit line air gap formed in the isolation region; and a set of dielectric caps formed over the bit line air gap between the first column of non-volatile storage elements and the second column of non-volatile storage elements, at least a portion of each cap extending continuously in the row direction over the bit line air gap between and at a level adjacent to corresponding intermediate dielectric regions of the first column and the second column, the set of dielectric caps having a lower dielectric constant than a dielectric constant of the intermediate dielectric regions.