Patent ID: 9705497
Date: 2017-07-11
CPC Classifications: G11C,H01C,H03F,H03K

Claim:
1. A method of self-calibrating a configurable resistance on an integrated circuit capable of being coupled to a reference resistor, the method comprising: (A) tuning a digital resistor network to configure a digital portion of the configurable resistance; (B) tuning an analog resistor network to configure an analog portion of the configurable resistance; wherein the configurable resistance comprises the digital resistor network and the analog resistor network coupled in parallel, wherein the configurable resistance is capable of being coupled in series with the reference resistor to form a voltage divider with an output, wherein the digital resistor network comprises a plurality of selectable resistive branches in parallel and a plurality of digital control signals, each branch being coupled to one of the digital control signals and selected according to the state of that digital control signal, and wherein the tuned resistance of the digital resistor network is determined by the combined state of the digital control signals; and wherein step (A) comprises the sub-steps of: (A1) varying the number of selected resistive branches in the digital resistor network; (A2) comparing the voltage at the output of the voltage divider to a reference voltage when the number of selected resistive branches is varied; (A3) determining from the voltage comparisons a first combined state of the digital control signals required to produce the lowest value of voltage at the output of the voltage divider that is higher than the reference voltage; (A4) determining from the voltage comparisons a second combined state of the digital control signals required to produce the highest value of voltage at the output of the voltage divider that is lower than the reference voltage; (A5) selecting the one of the first combined state of digital control signals and the second combined state of digital control signals that determines the larger tuned resistance of the digital resistor network; and (A6) storing the selected one of the first combined state of the digital control signals and the second combined state of the digital control signals.