Patent ID: 9571846
Date: 2017-02-14
CPC Classifications: H04N

Claim:
1. An apparatus, comprising: a block processing pipeline comprising a plurality of stages each configured to perform one or more operations on blocks of pixels from a current frame passing through the pipeline; wherein the block processing pipeline is configured to store data from processed blocks of the current frame as reference data to a memory according to a tile format, wherein the tile format stores reference data from each processed block of the frame in a corresponding tile, wherein each tile includes two or more contiguous memory blocks in the memory, each memory block of a block request size of the memory, and wherein the tiles are stored to a reference frame corresponding to the current frame passing through the pipeline in the memory in sequential order of the blocks of pixels in the frame; and wherein the block processing pipeline is further configured to fetch one or more windows of reference data from a reference frame corresponding to another frame, wherein the reference frame was previously stored to the memory according to the tile format, and process at least one block of pixels from the current frame according to the fetched one or more windows of reference data from the reference frame corresponding to the other frame; wherein at least one of the one or more windows overlaps at least a portion of at least two of the tiles in the reference frame, and wherein, to fetch the overlapping window of reference data from the reference frame according to the tile format, the block processing pipeline is configured to, for each overlapped tile: