Patent ID: 9548325
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method of manufacturing a thin film transistor array panel, comprising: forming a first insulation layer on a substrate; forming a first semiconductor material layer on the first insulation layer; forming an etching passivation material layer on the first semiconductor material layer; forming a first photoresist layer on the etching passivation material layer; etching, using the first photoresist layer as a mask, the etching passivation material layer to form an etching passivation layer; etching, using the first photoresist layer as a mask, the first semiconductor material layer to form a first semiconductor pattern comprising a protrusion not covered by the etching passivation layer; forming, sequentially, a second insulation layer and a second semiconductor material layer on the etching passivation layer and the first semiconductor pattern; forming a second photoresist layer on the second semiconductor material layer; etching, using the second photoresist layer as a mask, the second semiconductor material layer to form a first semiconductor; etching the first insulation layer not covered by the second photoresist layer and the protrusion not covered by the etching passivation layer to form a second semiconductor comprising an undercut region under the etching passivation layer; and forming, in the first insulation layer, a stepped portion spaced apart from an edge of the second semiconductor.