Patent ID: 9685979
Date: 2017-06-20
CPC Classifications: H03M

Claim:
1. Circuitry for generating parallel CRC signature bits, the circuitry comprising: a data input for receiving parallel input data, the parallel input data having a plurality of input bits; a plurality of first multiplexors, each of the first multiplexors having a plurality of first multiplexor inputs, at least one of each of the first multiplexor inputs being coupled to the data input and at least one of each of the first multiplexor inputs being coupled to a circuitry output for receiving CRC signature bits; a plurality of second multiplexors, each of the plurality of second multiplexors having a first input coupled to an output of one of the first plurality of multiplexors and a second input coupled to a predetermined voltage; a plurality of third multiplexors, each of the plurality of third multiplexors having inputs coupled to outputs of the second plurality of multiplexors by exclusive OR (XOR) gates, the outputs of the third plurality of multiplexors being coupled to the circuitry output; and a decoder for decoding a polynomial to selection data for selecting the inputs passed by the multiplexors; in which the parallel CRC signature bits are generated at the circuitry output in a single clock pulse.