Patent ID: 9564433
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method comprising: forming a first gate stack and a second gate stack over a semiconductor substrate, wherein the first gate stack includes a gate dielectric layer physically contacting the semiconductor substrate, wherein a sidewall spacer is disposed along the first gate stack and physically contacts the gate dielectric layer; forming a source/drain feature in the semiconductor substrate, wherein the source/drain feature is associated with the first gate stack and the sidewall spacer physically contacts the source/drain feature; forming a first interlayer dielectric layer over the first and second gate stacks; forming a first contact within the first interlayer dielectric layer such that the first contacts extends to the source/drain feature, wherein a length of the first contact is larger than a width of the first contact, and wherein the length is in a direction parallel to a channel width direction of the first gate stack and the width is in a direction perpendicular to the channel width direction of the first gate stack; forming a second interlayer dielectric layer over the first and second gate stacks; and forming a second contact within the second interlayer dielectric layer, wherein the second contact has a bottom surface physically contacting the first contact that extends continuously to physically contact the first gate stack, wherein the bottom surface of the second contact faces the semiconductor substrate and physically contacts the first interlayer dielectric layer and the sidewall spacer, wherein a length of the second contact is in the direction parallel to the channel width direction of the first gate stack and wherein the length of the first contact is larger than the length of the second contact.