Patent ID: 9542183
Date: 2017-01-10
CPC Classifications: G06F,H05K

Claim:
1. A method comprising: generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces; generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph, with the generation of the first assembly pattern file using data from the following tables: (i) a conditional pattern table, (ii) a static address table, and (iii) a dynamic address table; running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results using data from the following tables: (i) the conditional pattern table, (ii) the static address table, and (iii) the dynamic address table; generating a second assembly pattern file, for use with a second ISA/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph; and generating the set of branch traces by: (i) inputting a benchmark/customer application data set into a hardware simulator, and (ii) inputting a benchmark/customer application traces data set to a branch trace processing tool; wherein: the generation of the first assembly pattern file uses a first application binary interface data set, specific to the first ISA/microarchitecture set, so that the assembly pattern file can run on the first ISA/microarchitecture set; and the generation of the second assembly pattern file uses a second application binary interface data set, specific to the second ISA/microarchitecture set, so that the assembly pattern file can run on the second ISA/microarchitecture set.