Patent ID: 9653491
Date: 2017-05-16
CPC Classifications: G02F,H01L

Claim:
1. An array substrate comprising: a plurality of data lines and a plurality of gate lines arranged to intersect with each other; an annular common signal line surrounding the data lines and the gate lines; and at least one annular repair line, the repair line being electrically connected with the common signal line through an anti-static ring, wherein the repair line comprises a first line segment and a second line segment insulated from each other, wherein the first line segment intersects with and is insulated from each of the data lines, the second line segment does not intersect with the data lines and is electrically connected with the common signal line through the anti-static ring, and wherein a repair portion is arranged between the first line segment and the second line segment, the repair portion being used for enabling the first line segment to be electrically connected with the second line segment after being welded.