Patent ID: 9727680
Date: 2017-08-08
CPC Classifications: G06F,G11C,H01L

Claim:
1. A design structure tangibly embodied in a non-transitory machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: One or more Static Random-Access Memory (SRAM) cell groups, wherein each of the one or more SRAM cell groups includes two or more SRAM cells that are connected to an input of a local read amplifier by at least one common local bit-line, and wherein outputs of the local read amplifiers are connected to a shared global bit-line, the shared global bit-line being connected to a pre-charge circuit that is adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data, the pre-charge circuit including a limiter circuit comprising: an evaluation and translation circuit connected to a pre-charge regulator circuit and the shared global bit-line to compensate for leakage current of the shared global bit-line without changing a voltage level of the global bit-line; and a pre-charge regulator circuit connected to the shared global bit-line to pre-charge the shared global bit-line with the programmable pre-charge voltage, wherein the pre-charge regulator circuit comprises: