Patent ID: 9559878
Date: 2017-01-31
CPC Classifications: H04L

Claim:
1. An apparatus comprising: a phase adjustment circuit to generate phase lead/lag adjustment data; a clock and data recovery (CDR) circuit including a phase detector to receive a serial data signal and an data edge detection signal, and to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by a phase lead/lag adjustment data; and a decision feedback equalization (DFE) loop to provide equalization to the CDR circuit based, at least in part, on pre-cursor and post-cursor data samples of the serial data signal captured by a pre-cursor tap and a post-cursor tap, respectively, of the DFE loop, wherein the phase adjustment circuit is to generate the phase lead/lag adjustment data based, at least in part, on one of the pre-cursor or the post-cursor data samples captured by the DFE loop.