Patent ID: 9691476
Date: 2017-06-27
CPC Classifications: G11C,H03K

Claim:
1. An integrated circuit comprising: first and second data lines; a first memory cell comprising first and second resistance changing elements connected in series between the first and second data lines and a first selection transistor including a drain connected to a connection node of the first and second resistance changing elements; a second memory cell comprising third and fourth resistance changing elements connected in series between the first and second data lines and a second selection transistor including a drain connected to a connection node of the third and fourth resistance changing elements; a first sense amplifier comprising first input terminals and a first output terminal, the first input terminals connected to the first and second data lines; a second sense amplifier comprising second input terminals and a second output terminal, the second input terminals connected to the first and second data lines; a multiplexer comprising third input terminals and a third output terminal, the third input terminals connected to the first and second output terminals; and a control circuit controlling operations of the first and second sense amplifiers and the multiplexer in reading data from the first or second memory cell.