Patent ID: 9646836
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device including a parallel p-n layer wherein a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region are repeatedly and alternately disposed, the semiconductor device manufacturing method comprising: performing a first formation step by: forming the parallel p-n layer by causing the first-conductivity-type impurity of the first first-conductivity-type impurity region and the second-conductivity-type impurity of the second-conductivity-type impurity region to diffuse using thermal processing, wherein the first formation step further includes selectively introducing, into an uppermost one of the first semiconductor layers, the first-conductivity-type impurity into an area between adjacent ones of the first first-conductivity-type impurity region and the second-conductivity-type impurity region, thereby increasing the first-conductivity-type impurity concentration on respective sides of the second-conductivity-type impurity region, in the uppermost one of the first semiconductor layers, in a second introduction step.