Patent ID: 9684568
Date: 2017-06-20
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A data storage device, comprising: a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages; and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory, wherein: the microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory to record mapping information between the host and the flash memory, allocates the blocks of the flash memory to provide a system block, and records a link table indicator in the system block to indicate a position of the link table; the link table indicates positions of the plurality of logical-to-physical address mapping tables, each entry in the link table corresponds to one logical-to-physical address mapping table; and wherein the microcontroller erases user data of logical addresses corresponding to N logical-to-physical address mapping tables by downloading the link table from the flash memory to the random access memory, invalidating N entries corresponding to the N logical-to-physical address mapping tables in the link table on the random access memory, uploading the link table with the N entries of invalid data back to the flash memory, and updating the system block with an updated link table indicator, where N is an integer.