Patent ID: 9563468
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. A computer-implemented method, comprising, in a transactional memory environment including a plurality of processors comprising a first processor and one or more additional processors: identifying a memory location; sending a probe request from said first processor to said one or more additional processors, said probe request including said memory location and said probe request comprises a cross-interrogate; generating an indication, by each of said one or more additional processors, said indication comprising a status code for said memory location of a transaction on said one or more additional processors; sending said indication from each of said one or more additional processors to said first processor; proceeding, by said first processor, to branch based on said indication; wherein said transaction has associated therewith a read-set and a write-set; wherein at least one of said read-set or said write-set comprises one or more memory locations; wherein said status code is represented by two bits; wherein said two bits are in any one state selected from the group consisting of: wherein said one or more additional processors do not detect any access to said memory location and do not interpret said probe request as a transaction abort condition.