Patent ID: 9536892
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A pillar-shaped semiconductor memory device comprising: a semiconductor substrate; a first semiconductor pillar disposed on the semiconductor substrate and extending in a direction perpendicular to a surface of the semiconductor substrate; a tunnel insulating layer surrounding an outer periphery of the first semiconductor pillar; a data charge storage insulating layer surrounding an outer periphery of the tunnel insulating layer; a first interlayer insulating layer surrounding an outer periphery of the data charge storage insulating layer; a second interlayer insulating layer surrounding an outer periphery of the first interlayer insulating layer; a first conductor layer surrounding an outer periphery of the second interlayer insulating layer; and a third interlayer insulating layer that is in contact with an upper surface or a lower surface of the first conductor layer and that surrounds an outer periphery of the second interlayer insulating layer, wherein at least one stacked material layer including the first conductor layer and the third interlayer insulating layer as one set is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the second interlayer insulating layer is continuously formed between the first semiconductor pillar and a side surface of the at least one stacked material layer, the side surface facing the first semiconductor pillar, in a direction perpendicular to the at least one stacked material layer and extends to an upper surface of an uppermost layer of the at least one stacked material layer, and data writing and erasing due to a data charge transfer between the first semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer or a data charge retention by the data charge storage insulating layer is performed by application of a voltage to the first conductor layer.