Patent ID: 9711495
Date: 2017-07-18
CPC Classifications: G03F,H01L

Claim:
1. A semiconductor device, comprising: a first linear-shaped gate electrode level structure configured to form a gate electrode of a first transistor, the first linear-shaped gate electrode level structure oriented to extend lengthwise in a first direction; a second linear-shaped gate electrode level structure configured to form a gate electrode of a second transistor, the second linear-shaped gate electrode level structure oriented to extend lengthwise in the first direction, wherein the first and the second linear-shaped gate electrode level structures are positioned next to each other such that their respective lengthwise-oriented centerlines are separated from each other by a gate electrode pitch as measured in a second direction perpendicular to the first direction; a first linear-shaped interconnect level structure configured to extend lengthwise in the second direction over both the first linear-shaped gate electrode level structure and the second linear-shaped gate electrode level structure; a second linear-shaped interconnect level structure configured to extend lengthwise in the second direction over both the first linear-shaped gate electrode level structure and the second linear-shaped gate electrode level structure; a third linear-shaped interconnect level structure configured to extend lengthwise in the second direction over both the first linear-shaped gate electrode level structure and the second linear-shaped gate electrode level structure; a first interlevel connection structure having a rectangular-shaped horizontal cross-section defined by a first size as measured in the first direction and a second size as measured in the second direction, the second size of the horizontal cross-section of the first interlevel connection structure being at least twice the first size of the horizontal cross-section of the first interlevel connection structure, the second size of the horizontal cross-section of the first interlevel connection structure being larger than twice a size of the first linear-shaped gate electrode level structure as measured in the second direction, the first interlevel connection structure positioned in a substantially centered manner on the first linear-shaped gate electrode level structure relative to the second direction, the first interlevel connection structure positioned in a substantially centered manner on the first linear-shaped interconnect level structure relative to the first direction; a second interlevel connection structure having a rectangular-shaped horizontal cross-section defined by a first size as measured in the first direction and a second size as measured in the second direction, the second size of the horizontal cross-section of the second interlevel connection structure being at least twice the first size of the horizontal cross-section of the second interlevel connection structure, the second interlevel connection structure positioned in a substantially centered manner on the second linear-shaped interconnect level structure relative to the first direction, the second interlevel connection structure positioned in a substantially centered manner on a position located one-half of the gate electrode pitch as measured in the second direction away from the lengthwise-oriented centerline of the first linear-shaped gate electrode level structure; a third interlevel connection structure having a rectangular-shaped horizontal cross-section defined by a first size as measured in the first direction and a second size as measured in the second direction, the second size of the horizontal cross-section of the third interlevel connection structure being at least twice the first size of the horizontal cross-section of the third interlevel connection structure, the third interlevel connection structure positioned in a substantially centered manner on the third linear-shaped interconnect level structure relative to the first direction, the third interlevel connection structure positioned in a substantially centered manner on a position located one-half of the gate electrode pitch as measured in the second direction away from the lengthwise-oriented centerline of the first linear-shaped gate electrode level structure, such that the second and third interlevel connection structures are located on different sides of the first linear-shaped gate electrode level structure relative to the second direction.