Patent ID: 9584142
Date: 2017-02-28
CPC Classifications: H03L

Claim:
1. A fractional N frequency synthesizer, comprising: a phase frequency comparator comparing a reference frequency with the phase frequency of an input signal and outputting the difference between the reference frequency and the phase frequency; a voltage controlled oscillator outputting a clock signal in response to the output of the phase frequency comparator; a ΔΣ modulator accumulating a fractional set value at each cycle of the reference frequency and generating a carryover signal when the accumulated value exceeds the maximum value of an accumulator in the ΔΣ modulator; a frequency divider dividing the frequency of the clock signal from the voltage controlled oscillator by a first frequency division value when the carryover signal has been generated by the ΔΣ modulator, at each cycle of the reference frequency, dividing the frequency of the clock signal from the voltage controlled oscillator by a second frequency division value when the carryover signal has not been generated by the ΔΣ modulator, at each cycle of the reference frequency, the second frequency division value being different from the first frequency division value, and using the clock signal with the divided frequency as the input signal to the phase frequency comparator; a calculator calculating the remainder of the division of which the dividend is the minimum accumulated value at which a carryover occurs in the ΔΣ modulator and the devisor is the fractional set value, and if the remainder is not zero, repeatedly calculating the quotient and remainder of the division of which the dividend is the devisor of the previous division and the devisor is the value of the remainder obtained in the previous division until the value of the remainder becomes zero; an abnormal noise determiner determining, after the calculator has calculated the quotient and remainder of the division using a fractional set value to be set in the ΔΣ modulator until the remainder has become zero, that the fractional set value causes periodic abnormal noise when the calculated quotients include a value exceeding a threshold and determining that the fractional set value does not cause periodic abnormal noise when the calculated quotients do not include a value exceeding the threshold; and a fractional setter, comprising the calculator and the abnormal noise determiner, changing the fractional set value to the extent that the frequency of the clock signal eventually obtained by the voltage controlled oscillator does not exceed a given value when the abnormal noise determiner has determined that periodic abnormal noise has occurred, and setting the changed fractional set value as the fractional set value of the ΔΣ modulator when the abnormal noise determiner has determined that the changed fractional set value has not caused periodic abnormal noise.