Patent ID: 9704564
Date: 2017-07-11
CPC Classifications: G11C,H01L

Claim:
1. An integrated circuit structure comprising: a Static Random Access Memory (SRAM) cell comprising: an elongated contact over and electrically coupled to a source of the first pull-down MOS device; a first metal layer, with a bit-line and a CVdd line in the first metal layer; a first CVss landing pad overlapping and electrically coupled to the elongated contact, wherein the first CVss landing pad has a portion in the SRAM cell, with the portion having a first length and a first width smaller than a second length and a second width of the SRAM cell; a first word-line having a first lengthwise direction, wherein the first word-line and the first CVss landing pad are in a second metal layer over the first metal layer; and a first CVss line in a third metal layer over the second metal layer, wherein the first CVss line is electrically coupled to the first CVss landing pad, and the first CVss line has a second lengthwise direction perpendicular to the first lengthwise direction.