Patent ID: 9721948
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A chip structure comprising: a first transistor including a first source/drain region, a second source/drain region, and a gate electrode, the gate electrode having a long axis aligned in a first direction and a short axis aligned in a second direction that is perpendicular to the first direction; a second transistor including a first source/drain region, a second source/drain region, and a gate electrode, the gate electrode having a long axis aligned in the first direction and a short axis aligned in the second direction; a first contact level including a first contact directly and physically connected with the first source/drain region of the first transistor and a second contact directly and physically connected with the first source/drain region of the second transistor; and a first wiring level including a first wire directly and physically connected with the first contact and directly and physically connected with the second contact, the first wire having a width and a length aligned in the second direction such that the first wire crosses over the long axis of the gate electrode of the first transistor and the long axis of the gate electrode of the second transistor.