Patent ID: 9653079
Date: 2017-05-16
CPC Classifications: G10L

Claim:
1. A method comprising: monitoring audio samples in a first component in an integrated circuit during a time that a remainder of the integrated circuit is powered down, wherein the first component is powered on during the time and is operating according to a first clock; detecting a key phrase in the audio samples by the first component; powering up at least a portion of the integrated circuit responsive to the detecting; determining that a second clock used within the integrated circuit is available, wherein the second clock has at least one characteristic that is closer to an ideal clock characteristic than a corresponding characteristic of the first clock, wherein the second clock becomes available responsive to powering up the portion of the integrated circuit, and wherein the at least one characteristic comprises a duty cycle, and wherein the second clock has a duty cycle that is closer to a 50% duty cycle than a duty cycle of the first clock; and switching to the second clock in the first component at a time that is prior to an arrival of subsequent audio samples to ensure that no more than a threshold number of audio samples is lost or corrupted during the switching.