Patent ID: 9595588
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a silicon substrate having a first area and a second area; at least a first cell positioned in the first area and formed in a trench of the silicon substrate, and the first cell comprising: a first dielectric layer formed on sidewalls and a bottom of the trench; a floating gate formed on the first dielectric layer and embedded in the trench; a second dielectric layer formed on the floating gate and embedded in the trench; and a control gate formed on the second dielectric layer and embedded in the trench, wherein the control gate is separated from the floating gate by the second dielectric layer; and at least a second cell positioned in the second area and formed on the silicon substrate; wherein the second cell comprises a metal gate formed above the silicon substrate, and a top surface of the metal gate of the second cell is higher than a top surface of the control gate of the first cell.