Patent ID: 9612979
Date: 2017-04-04
CPC Classifications: G06F

Claim:
1. An apparatus, comprising: memory check logic circuitry to generate first error checking information from program code after the program code has been loaded into a protected region of a system memory and during execution of the program code from the protected region of the system memory, wherein the memory check logic circuitry is to calculate the first error checking information from the protected region of system memory for every Nth memory location; and comparison logic circuitry comprising a first input and a second input, the first input to receive the first error checking information, the second input to receive second error checking information, the second error checking information retrieved from a non volatile memory and including an image of the program code, the comparison logic circuitry to generate an error signal if the comparison logic circuitry detects a mismatch between the first error checking information and the second error checking information; and, circuitry to generate the second error checking information in response to an update of the program code prior to the loading and execution of the program code and to store the second error checking information in the non volatile memory.