Patent ID: 9716075
Date: 2017-07-25
CPC Classifications: B23K,H01L,H05K,Y10T

Claim:
1. A method for forming a microelectronic assembly comprising: providing a substrate including a first dielectric layer having a first composition having electrically conductive elements thereon, the first dielectric layer having a coefficient of thermal expansion of at least 10 parts per million/° C.; forming a second dielectric layer overlying the first dielectric layer having a surface at which electrically conductive substrate contacts respectively overlying the conductive elements are exposed, the second dielectric layer having a Young's modulus of less than about 2 GPa; electrically connecting the conductive elements respectively with the substrate contacts by conductive vias extending through the second dielectric layer, the vias being disposed entirely below the respective substrate contacts; and joining the substrate contacts to respective contacts exposed at a face of a microelectronic element, the surface of the substrate confronting the face of the microelectronic element, wherein the microelectronic element further includes a dielectric region, in which the dielectric region includes a dielectric material having a low-k dielectric constant, and wherein a stiffness of the substrate contacts is such that the substrate contacts have a capability to move that limits an amount of stress transferred by the substrate contacts to the dielectric region of the microelectronic element by said movement of the substrate contacts to below a level of stress that would be transferred to the dielectric region of the microelectronic element, such as caused by differential expansion or contraction absent said movement of the substrate contacts, in which the amount of stress is lower than a tolerance level of stress of the dielectric region.