Patent ID: 9734752
Date: 2017-08-15
CPC Classifications: G02F,G09G

Claim:
1. A display device comprising: a display panel configured to display an image based on first and second frames; a timing controller configured to output a plurality of image signals for each of the first and second frames and to output a test signal during a reset section; a source driving chip configured to output a plurality of data voltages corresponding to the image signals or a test voltage corresponding to the test signal; and a plurality of driving lines configured to receive the data voltage or the test voltage and electrically connecting the display panel to the source driving chip, wherein: the reset section is arranged after the first frame and before the second frame; the source driving chip comprises a plurality of source units, each source unit being electrically connected to a corresponding one of the driving lines; the source driving chip is configured to block the data voltage in the second frame from being output to driving lines having an arrival time period equal to or less than a reference time period during the reset section, the arrival time period representing the amount of time taken to arrive at the test voltage from an initial voltage; and each source unit comprises: a comparator configured to compare the test voltage received through a first terminal with a feedback voltage received through a second terminal and to provide a comparison voltage according to a comparison result to a corresponding driving line; a sensing circuit configured to receive the test voltage and the comparison voltage and to sense the arrival time period representing the amount of time taken for the comparison voltage to arrive at the test voltage from the initial voltage; and a control circuit configured to output a disable signal comprising an activated state disabling the comparator when the arrival time period is equal to or less than the reference time period.