Patent ID: 9564237
Date: 2017-02-07
CPC Classifications: G11C

Claim:
1. A nonvolatile memory device comprising: a memory cell array connected to a plurality of word lines; a voltage generator for supplying a select read voltage to a select word line, a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line and a second unselect read voltage to remaining unselect word lines in the memory cell array; an input/output circuit electrically coupled to bit lines associated with the memory cell array; and a control circuit electrically coupled to said input/output circuit and said voltage generator, said control circuit configured to control said voltage generator so that a level of the first unselect read voltage is set according to an elapsed time of a memory block within the memory cell array to be read after a program of the memory block.