Patent ID: 9666528
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A method of forming an electrical device comprising: forming an array of metal lines; depositing a dielectric cap atop and within the space separating adjacent metal lines within the array of metal lines, wherein a thickness of the dielectric cap pinches off within the space separating said adjacent metal lines to substantially enclose a plurality of air gaps; depositing at least one interlevel dielectric layer overlying a level including said air gaps and said array of metal lines, wherein the interlevel dielectric layer entirely encapsulates the plurality of air gaps; forming a plurality of trenches in the interlevel dielectric layer, wherein at least one trench opens at least one of the plurality of air gaps; and depositing an electrically conductive material in the trenches to form a vertical fuse in an opened air gap, the vertical fuse being present in said space between adjacent metal lines.