Patent ID: 9609610
Date: 2017-03-28
CPC Classifications: H03L,H04J,H04W

Claim:
1. A system comprising: a root node configured to receive a first clock signal at a first port, to generate a first frame including a first overhead portion, the first overhead portion comprising a synchronization value based on at least one parameter of the first clock signal, and to determine whether a second clock signal has failed or is inaccurate, the second clock signal being received at a second port of the root node; a radio channel network in communication with the root node for transmitting the first frame; and a first child node including a first phase lock loop, the first child node configured to receive the first frame and to synchronize at least one parameter of the first phase lock loop with the at least one parameter of the first clock signal using the synchronization value in the first overhead portion of the first frame.