Patent ID: 9548947
Date: 2017-01-17
CPC Classifications: H04L

Claim:
1. A method comprising: (a) receiving first packet data from a first credit-aware device via a bus and onto a memory system; (b) receiving second packet data from a second credit-aware device via the bus and onto the memory system; (c) sending the first packet data out of the memory system; (d) sending the second packet data out of the memory system; (e) storing an initial first Credits To Be Returned (CTBR) value and an initial second CTBR value in the memory system; (f) receiving a first command onto the memory system, wherein the first command includes a first Packet Portion Identifier (PPI) and does not include a first credit number; (g) determining the first credit number from the first PPI; (h) adding the first credit number to the initial first CTBR value thereby obtaining an updated first CTBR value; (i) sending the updated first CTBR value from the memory system via the bus to the first credit-aware device; (j) receiving a second command onto the memory system, wherein the second command includes a second PPI and does not include a second credit number; (k) determining the second credit number from the second PPI; (l) adding the second credit number to the initial second CTBR value thereby obtaining an updated second CTBR value; and (m) sending the updated second CTBR value from the memory system via the bus to the second credit-aware device, wherein (a) through (m) are performed by the memory system, and wherein the first credit-aware device and the second credit-aware device and the memory system are parts of a single integrated circuit.