Patent ID: 9595477
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A method comprising: forming a gate structure over a substrate; forming lightly doped source and drain (LDD) regions in the substrate, wherein the gate structure is disposed between the LDD regions; after forming the LDD regions, forming a conformal first spacer material layer by depositing SiCN abutting a top surface and sidewalls of the gate structure on the substrate; forming a conformal second spacer material layer overlying the first spacer material layer, wherein the conformal second spacer material layer overlies the top surface and sidewalls of the gate structure; etching the conformal first spacer material layer and the conformal second spacer material layer concurrently to form a first spacer and a second spacer respectively, wherein the etching includes removing the first spacer material layer and the second spacer material layer from the top surface of the gate structure; forming an epitaxy region on the substrate over the LDD regions, wherein the epitaxy region interfaces the first and second spacers; after forming the epitaxy region, removing the second spacer to provide a space, wherein the space has a width defined by a first vertical sidewall of the epitaxy region and a vertical sidewall of the first spacer, the distance there between providing the width of the space; using one deposition process, forming an interlayer dielectric layer (ILD) in the space; and forming a contact feature in the ILD layer and contacting the epitaxy region.