Patent ID: 9543422
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type that is provided above the first semiconductor region; a gate electrode including a portion that is surrounded by the second semiconductor region via a gate insulating layer; a first electrode that includes a portion surrounded by the second semiconductor region via a first insulating layer, the first electrode being separated from the gate electrode; a third semiconductor region of the second conductivity type that is provided in a portion of the second semiconductor region between the first insulating layer and the gate insulating layer, the third semiconductor region contacting the first insulating layer and having a concentration of carriers of the second conductivity type that is higher than a concentration of carriers of the second conductivity type in the second semiconductor region; a fourth semiconductor region of the first conductivity type that includes a first portion aligned along a first direction with the third semiconductor region and is provided on the second semiconductor region and the third semiconductor region and between the gate electrode and the first electrode; and a fifth semiconductor region of the second conductivity type that is provided in the fourth semiconductor region, the fifth semiconductor region contacting the gate insulating layer and aligned along a second direction with the first portion, the second direction being perpendicular to the first direction.