Patent ID: 9607944
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a plurality of first wires, wherein each of the first wires forms a closed polygon and surrounds a center; a plurality of second wires, wherein each of the second wires forms the closed polygon and surrounds the center, and wherein the first and second wires are interlaced, and none of the first and second wires are coupled to each other; a first conductive layer, having an entire surface structure, disposed on the first and second wires and coupled to the first wires; and a second conductive layer, having an entire surface structure, disposed on the first and second wires and coupled to the second wires, wherein the first conductive layer is disposed between the second conductive layer and the first and second wires, and the first and second conductive layers are not coupled to each other.