Patent ID: 9620371
Date: 2017-04-11
CPC Classifications: C25D,H01L

Claim:
1. A method, comprising: forming a silicide layer directly on a substrate; forming at least one low resistance conduction path in an interlevel dielectric layer above the silicide layer, wherein the at least one low resistance conduction path is located within a dicing channel; forming an active device on the substrate and in contact with the silicide layer; forming a barrier layer in direct contact with the low resistance conduction path; forming an electroplated seed layer in direct contact with the barrier layer; forming a second interlevel dielectric layer over the interlevel dielectric layer; patterning the second interlevel dielectric layer to form a first opening exposing conductive material within the at least one low resistance conduction path; and patterning the second interlevel dielectric layer to form a second opening above the active device, wherein the at least one low resistance conduction path comprises a plurality of separate vias, wherein the first opening extends over the plurality of vias, wherein forming the barrier layer comprises forming the barrier layer on sidewalls and a bottom of the first opening such that the barrier layer is formed over the plurality of vias, and wherein forming the barrier layer comprises forming the barrier layer on sidewalls and a bottom of the second opening.