Patent ID: 9673099
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A fabricating method of an integrated circuit device, the method comprising: providing a substrate having a first region and a second region defined therein; forming a first fin in the first region and forming a second fin in the second region; forming a first gate electrode intersecting the first fin in the first region and forming a second gate electrode intersecting the second fin in the second region; forming a first recess in the first fin at either side of the first gate electrode in the first region and forming a second recess in the second fin at either side of the second gate electrode in the second region; forming a first source/drain in the first recess; and forming a second source/drain in the second recess, wherein a depth of the first recess is different from a depth of the second recess, and wherein an impurity concentration of the first source/drain is different from an impurity concentration of the second source/drain.