Patent ID: 9646766
Date: 2017-05-09
CPC Classifications: H01G,Y10T

Claim:
1. A process of making a dielectric laminated capacitor with increased dielectric breakdown strength, comprising: providing a bottom electrode having a bottom electrode thickness; depositing a first dielectric layer on the bottom electrode; depositing a first conductive oxide layer on the first dielectric layer; depositing a second dielectric layer on the conductive oxide layer wherein the conductive oxide layer is embedded within the first and second dielectric layers; and depositing a top electrode having a top electrode thickness on the second dielectric layer, to form a laminated capacitor wherein the conductive oxide layer is not in contact with the electrodes so as to redistribute trapped charges within the dielectric layers and wherein said top electrode thickness is less than the bottom electrode thickness wherein said conductive oxide layer comprises a layer having a thickness of 3 nm to 10 nm and wherein said electrodes and the conductive oxide layer are components of the laminated capacitor wherein said conductive oxide layer comprises a sputtered layer embedded between the first and the second dielectric layers and wherein the conductive oxide layer comprises between 0.1% to 0.9% of total thickness of the final laminated capacitor.