Patent ID: 9559105
Date: 2017-01-31
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a first memory circuit comprising a first inverter circuit and a second inverter circuit; a first switching circuit configured to control an input of a data signal; a second switching circuit; a third inverter circuit; a fourth inverter circuit; a second memory circuit comprising a first transistor and a first capacitor; a third memory circuit comprising a second transistor and a second capacitor; and a precharge circuit comprising a third transistor and a fourth transistor, wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor, wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit, wherein an input terminal of the second inverter circuit is electrically connected to an output terminal of the first inverter circuit, wherein the first switching circuit is electrically connected to the input terminal of the first inverter circuit, wherein the output terminal of the first inverter circuit is electrically connected to an input terminal of the third inverter circuit via the second switching circuit, wherein the input terminal of the third inverter circuit is electrically connected to an output terminal of the fourth inverter circuit, wherein an input terminal of the fourth inverter circuit is electrically connected to an output terminal of the third inverter circuit, wherein one of a source and a drain of the first transistor is electrically connected to the output terminal of the first inverter circuit, wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor, wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the second inverter circuit, wherein the other of the source and the drain of the second transistor is electrically connected to the second capacitor, wherein one of a source and a drain of the third transistor is electrically connected to the output terminal of the first inverter circuit, wherein the other of the source and the drain of the third transistor is electrically connected to a power supply line, wherein one of a source and a drain of the fourth transistor is electrically connected to the output terminal of the second inverter circuit, and wherein the other of the source and the drain of the fourth transistor is electrically connected to the power supply line.