Patent ID: 9735117
Date: 2017-08-15
CPC Classifications: H01L,H04B

Claim:
1. A semiconductor device, comprising: a die having a semiconductor substrate with an intrinsic region; a metal layer in direct contact with the intrinsic region; a passivation layer disposed over and in contact with the metal layer and the intrinsic region, the passivation layer defining an opening dimensioned to expose at least a portion of the metal layer; and an interconnect conductor disposed over and in contact with the metal layer and electrically connected to the metal layer through the opening, the interconnect conductor having a saw-tooth cross-section with a linear portion in contact with the metal layer along the length of the linear portion, and a pair of extensions that extend at a non-perpendicular angle from opposite ends of the linear portion and in opposite directions to proximal ends of the interconnect conductor, each of the pair of extensions having a distal surface that extends from the linear portion to a proximal end aligned with a proximal surface of the passivation layer, a proximal surface that extends from the linear portion to a proximal end spaced above and vertically aligned with the proximal end of the distal surface of the extension, and a vertical segment that extends between and connects the proximal ends of the distal and proximal surfaces of each extension, the pair of angled extensions extending over an edge of the opening of the passivation layer, each of the angled extensions wedging a wedge-shaped portion of the passivation layer thereunder to inhibit or reduce the likelihood of the passivation layer de-laminating from the edge.