Patent ID: 9569219
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A method for assisting operations of a processor core, the processor core being coupled to a first memory and a second memory with a faster speed than the first memory, the method comprising: examining instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information of the instructions; creating a plurality of tracks based on the extracted instruction information; and filling one or more instructions from the first memory to the second memory based on one or more tracks from the plurality of tracks before the processor core starts executing the one or more instructions, such that the processor core fetches the one or more instructions from the second memory for execution, wherein filling the one or more instructions further includes: pre-fetching from the first memory to the second memory instruction segments containing the one or more instructions corresponding to at least two levels of branch target instructions based on the one or more tracks.