Patent ID: 9634044
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method for fabricating an array substrate, comprising: forming, on a substrate, at least two semiconductor active islands, first patterns positioned on both sides of each of the semiconductor active islands, second patterns positioned at outer side of a part of the first patterns, and third patterns positioned at outer side of the rest of the first patterns, through a single patterning process; doping a semiconductor at the second patterns for once to form a semiconductor of a first conductivity type; and doping a semiconductor at the third patterns for once to form a semiconductor of a second conductivity type; wherein after doping the semiconductor at the second pattern for once to form the semiconductor of a first conductivity type, the method further comprises: sequentially forming a gate insulation layer, a gate metal layer comprising a gate electrode pattern, and a protection layer on the substrate done with the previous steps; and forming a first via hole in the gate insulation layer and a second via hole in the protection layer through a single patterning process; the first via hole and the second via hole exposes at least the third patterns.