Patent ID: 9685364
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method for fabricating a silicon-on-insulator integrated circuit comprising: providing a silicon-on-insulator substrate that comprises a semiconductor layer disposed over an insulating layer, which in turn is disposed over a substrate; forming a plurality of first shallow isolation trenches completely through the semiconductor layer to expose a portion of the insulating layer therebelow; forming a plurality of second shallow isolation trenches only part-way, but not fully, through the semiconductor layer; subsequent to forming the plurality of second shallow isolation trenches, implanting conductivity-determining ions into the semiconductor layer beneath the plurality of second shallow isolation trenches; subsequent to implanting the conductivity-determining ions, filling the plurality of first and second shallow isolation trenches with an insulating material to form a plurality of first and second shallow trench isolation structures; forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second shallow trench isolation structures and a second portion disposed in between the at least two of the plurality of second shallow trench isolation structures, wherein no first shallow trench isolation structures are formed in between the at least two of the plurality of second shallow trench isolation structures; and forming contact plugs to the gate structure and to a body contact region.