Patent ID: 9689804
Date: 2017-06-27
CPC Classifications: G01B,G01N,H01L

Claim:
1. A system inspecting a backside surface of a wafer with multi-channel focus control comprising: a plurality of inspection sub-systems including a first inspection sub-system positionable at a first wafer position and at least an additional inspection sub-system positionable at an additional wafer position, wherein the wafer is secured at one or more edge portions of the wafer, wherein the backside surface of the wafer is distorted; wherein the first inspection sub-system comprises: a first optical assembly; a first actuation assembly, wherein the first optical assembly is disposed on the first actuation assembly; and a first positional sensor configured to sense a position characteristic between a portion of the first optical assembly and the backside surface of the wafer; wherein the at least an additional inspection sub-system comprises: at least an additional optical assembly; at least an additional actuation assembly, wherein the at least an additional optical assembly is disposed on the at least an additional actuation assembly; and at least an additional positional sensor configured to sense a position characteristic between a portion of the at least an additional optical assembly and the backside surface of the wafer; and a controller, wherein the controller is communicatively coupled to the first actuation assembly, the at least an additional actuation assembly, the first positional sensor and the at least an additional positional sensor, wherein the controller is configured to execute a set of program instructions configured to cause one or more processors to: acquire one or more wafer profile maps of the backside surface of the wafer; and adjust at least one of a first focus position of the first inspection sub-system or at least an additional focus position of the at least an additional inspection sub-system based on the received one or more wafer profile maps to correct for focus error caused by the distortion of the backside surface of the wafer.