Patent ID: 9577085
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: interlayer insulating layers stacked in a first direction and separated from each other; word lines formed between the interlayer insulating layers; sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed; and cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a lower sidewall of the first pillar portion to surround the lower sidewall of the first pillar portion and contacting a sidewall of one of the word lines, the first protruding portion having a bottom surface or a top surface facing one of the sacrificial insulating layers, wherein the cell contact plugs have different depths.