Patent ID: 9735316
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method for manufacturing a high voltage LED flip chip, comprising: providing a substrate, wherein the substrate comprises two or more regions, and the two or more regions comprise a first region where an upper electrode is to be formed and a second region where a lower electrode is to be formed; forming an epitaxy stacking layer on the substrate, wherein the epitaxy stacking layer comprises a first semiconductor layer, a second semiconductor layer and a quantum well layer between the first semiconductor layer and the second semiconductor layer; etching the epitaxy stacking layer to form at least one first groove in each of the two or more regions, wherein the first groove exposes the first semiconductor laver, and a remaining portion of the epitaxy stacking layer on each of the two or more regions forms a Mesa-platform; forming a first electrode on each of the Mesa-platforms, wherein an area between the first electrodes in two adjacent regions forms a second groove; forming a first insulation layer, wherein the first insulation layer covers the Mesa-platforms and the first electrodes, and the first insulation layer fills the second groove and fills the first grooves; etching the first insulation layer to form a third groove between two adjacent Mesa-platforms and at least one fourth groove in each of the two or more regions, wherein the third groove exposes a surface of the first semiconductor layer, and the at least one fourth groove exposes a surface of the first electrode; forming an interconnection electrode, wherein the interconnection electrode comprises a first portion connecting the first semiconductor layer through the third groove in a particular region with the first electrode through the fourth groove in another region adjacent to the particular region, a second portion connecting with the first semiconductor layer in the first region and a third portion connecting with the first electrode in the second region, wherein a fifth groove is formed between two adjacent portions of the interconnection electrode; forming a second insulation layer, wherein the second insulation layer covers the interconnection electrode and fills the fifth groove; forming a sixth groove in the second insulation layer, wherein the sixth groove exposes the interconnection electrode in the first region; and forming a second electrode, wherein the second electrode completely covers the second insulation layer and connects with the interconnection electrode through the sixth groove in the first region.