Patent ID: 9595322
Date: 2017-03-14
CPC Classifications: G11C

Claim:
1. A method for optimizing a storage device, comprising: connecting, by at least one data bus line, phase change memory integrated circuits (PCM ICs) to a channel controller, wherein the PCM ICs are arranged in sub-channels and each of the sub-channels comprises several PCM ICs corresponding to a respective finite state machine within the channel controller; and optimizing a plurality of the sub-channels and/or a plurality of sub-banks in a matrix configuration, based on characteristics of the PCM ICs; wherein the channel controller is configured to write data to and/or read data from the PCM ICs according to the matrix configuration of PCM ICs, wherein: a plurality of columns of the matrix configuration respectively corresponds to the plurality of the sub-channels, the plurality of the sub-channels forming a channel; and a plurality of rows of the matrix configuration respectively corresponds to the plurality of sub-banks, the plurality of sub-banks forming a bank, wherein each of the plurality of sub-banks comprises PCM ICs that each belong to distinct sub-channels of the plurality of the sub-channels.