Patent ID: 9536032
Date: 2017-01-03
CPC Classifications: G06F,H01L,H03K

Claim:
1. A method of forming a layout design for fabricating an integrated circuit, the method comprising: identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design, the region of the layout design being sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality, K being an integer equal to or greater than two, the first set of grid lines extending along a first direction and corresponding to placement of a first set of layout patterns of a first layout layer of the layout design, the second set of grid lines extending along the first direction and corresponding to placement of a second set of layout patterns of a second layout layer of the layout design, the first set of grid lines having a first line pitch, and the second set of grid lines having a second line pitch different from the first line pitch, wherein the line pattern includes a layout pattern aligned with a grid line of the first set of grid lines overlapping a layout pattern aligned with a grid line of the second set of grid lines; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns, k being an order index ranging from 1 to K, and at least one of the above operations being performed by a hardware processor.