Patent ID: 9633148
Date: 2017-04-25
CPC Classifications: G01R,G06F

Claim:
1. A method for improving path delay calculation in static timing analysis (STA) for a circuit design, the method comprising: determining, by a processor, a connectivity between a first device and a second device located in a path of the circuit design, wherein a previous path delay of the path in a previous STA exceeds a desired delay specified by a timing requirement, and wherein determining the connectivity between the first device and the second device in the path of the circuit design comprises: generating, by a processor, a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device; calculating, by a processor, a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint; and performing, by a processor, timing optimization to the path based on the calculated path delay.