Patent ID: 9748172
Date: 2017-08-29
CPC Classifications: G11C,H01L

Claim:
1. A method of forming a staircase word line in a 3D memory having memory elements arranged in a three-dimensional pattern with a plurality of parallel layers stacked on top of a substrate, the method includes forming layer-by-layer a slab of the plurality of parallel layer, comprising: (a) providing a semiconductor substrate; (b) forming a multi-layer structure on top of the substrate, the multi-layer structure being repeated subsets of layers, each subset of layers including a dielectric layer and a layer of word line material for forming word lines; (c) partitioning the multi-layer structure by opening a plurality of trenches and refilling with isolation oxides to form an array of segments in each layer of word line material so that the segments from all layers of word line material in the multi-layer structure constituting an array of stacks of segments, each stack of segments being a column of segments from all layers of word line material; (d) along a direction in which the staircase word line is to run from left to right and rising from bottom to top of the multi-layer structure, opening a stairwell between two adjacent left and right stacks of segments to expose at least a portion of a first segment in a first layer of word line material in the left stack and at least a portion of a second segment in a second layer of word line material in the right stack; and (e) selectively connecting the portion of the first segment with the portion of the second segment with an insulated conductive sidewall layer in the stairwell; whereby a conductive riser is formed between the first and second segments.