Patent ID: 9715564
Date: 2017-07-25
CPC Classifications: G06F

Claim:
1. A method for identifying causality of gate unobservability within an optimized logic circuit comprising: receiving an unoptimized version of a logic circuit and an optimized version of said logic circuit; identifying an optimized gate in said optimized version of said logic circuit; generating a first netlist, said first netlist comprising a representation of said unoptimized version of said logic circuit; inducing an error on said optimized gate; generating a second netlist, said second netlist comprising a copy of said first netlist reflecting changes to said unoptimized version of said logic circuit based on said error on said optimized gate; propagating fan-out boundaries of said unoptimized version of said logic circuit for said first netlist and said second netlist, said fan-out boundaries reflecting reductions performed on said optimized version of said logic circuit within said first netlist and said second netlist relative to said fan-out boundaries; analyzing a redundancy report representing a plurality of optimization steps performed to obtain said optimized version of said logic circuit, said analyzing identifying which optimization steps are adequate to cause unobservability of said optimized gate; and responsive to said error becoming undetectable at said fan-out boundaries under constraints derived from said redundancy report, identifying a minimal set of reductions from said first netlist.