Patent ID: 9748167
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A silicon interposer, comprising: a substrate having a frontside surface and a backside surface; a first redistribution layer (RDL) structure disposed on the frontside surface; a plurality of first connecting elements disposed on the first RDL structure, wherein the plurality of first connecting elements have a first pitch; a second redistribution layer (RDL) structure disposed on the backside surface; a plurality of second connecting elements disposed on the second RDL structure, wherein the plurality of second connecting elements have a second pitch, wherein the second pitch is greater than the first pitch; a passivation layer on the backside surface; a dielectric layer on the passivation layer; and a plurality of through silicon vias (TSVs) in the substrate to electrically connect the first RDL structure to the second RDL structure, wherein the passivation layer surrounds ends of the plurality of the TSVs, and wherein the ends of the TSVs are flush with a top surface of the dielectric layer, and wherein the second RDL structure is in direct contact with the plurality of TSVs, the passivation layer and the dielectric layer.