Patent ID: 9614529
Date: 2017-04-04
CPC Classifications: H03K

Claim:
1. An apparatus, comprising: a pull-up circuit including a first transistor and a second transistor coupled in series between a first voltage rail and an output; a pull-down circuit including a third transistor and a fourth transistor coupled in series between the output and a second voltage rail; a first voltage generator configured to generate a first bias voltage responsive to a voltage at the output, wherein a control input of the second transistor is configured to receive the first bias voltage, the first bias voltage configured to transition from a first relatively high voltage to a first relatively low voltage approximately when the voltage at the output begins transitioning from a first low logic voltage towards a first high logic voltage due to the pull-up circuit coupling the first voltage rail to the output and the pull-down circuit decoupling the output from the second voltage rail, and the first bias voltage also configured to transition from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the first low logic voltage towards the first high logic voltage; and a second voltage generator configured to generate a second bias voltage responsive to the voltage at the output, wherein a control input of the third transistor is configured to receive the second bias voltage, the second bias voltage configured to transition from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the first high logic voltage towards the first low logic voltage due to the pull-down circuit coupling the output to the second voltage rail and the pull-up circuit decoupling the first voltage rail from the output, and the second bias voltage also configured to transition from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the first high logic voltage towards the first low logic voltage.