Patent ID: 9602272
Date: 2017-03-21
CPC Classifications: H03L,H04L

Claim:
1. A clock and data recovery circuit comprising: a phase detection circuit configured to generate an early phase detection signal and a late phase detection signal by comparing a clock signal and data; a filtering circuit configured to generate an up signal and a down signal based on a number of generation times of the early phase detection signal and a number of generation times of the late phase detection signal; a phase information summing circuit configured to receive an output of the filtering circuit at each cycle of the clock signal, and generate first and second phase control signals by summing up numbers of the up signals and the down signals received from the filtering circuit during a summing-up time n times larger than the cycle of the clock signal where n is an integer equal to or more than two; and a phase interpolator configured to adjust a phase of the clock signal according to the first and second phase control signals, when being updated at each cycle of the summing up time.