Patent ID: 9536943
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A vertical power MOSFET, comprising: (a) a silicon based semiconductor substrate having a first main surface and a second main surface; (b) a cell region extending from the first main surface of the semiconductor substrate to the inside thereof; (c) a drain region having N conductivity provided in the surface of the second main surface; (d) a drift region which is provided in the cell region and in a main portion extending from a boundary with the drain region to the first main surface, and in which columnar N conductivity drift regions and columnar P conductivity drift regions are placed alternately; (e) a gate electrode provided, via a gate insulating film, in a surface region on the side of the first main surface and over the surface of each of the columnar N conductivity drift regions; (f) a body region having P conductivity provided in the surface of the drift region on the side of the first main surface and extending from each of the columnar P conductivity drift regions to the columnar N conductivity drift region adjacent thereto, the body region having a net doping concentration that peaks between about 10 (g) an undergate heavily doped N region provided in the surface of each of the columnar N conductivity drift regions along the gate electrode and between a pair of the body regions adjacent to each other, having a depth shallower than that of the body region, and having a concentration higher than that of the columnar N conductivity drift region, the undergate heavily doped N region having a flat portion at a position nearer to the first main surface from inside the substrate, and having a net doping concentration that ranges from about 10 (h) a source region having the N conductivity provided in the surface of each of the body regions and extending from the vicinity of the end portion of the gate electrode to the outside and having a concentration higher than that of the undergate heavily doped N region; (i) a metal source electrode provided over the first main surface of the semiconductor substrate and electrically coupled to the body region and the source region; and (j) a metal drain electrode provided over the second main surface of the semiconductor substrate and electrically coupled to the drain region, wherein a profile of a channel P body-N column cross section A has a net doping concentration of about 2×10