Patent ID: 9704451
Date: 2017-07-11
CPC Classifications: G09G,G11C

Claim:
1. A shift register cell, comprising a start signal input terminal, a clock signal terminal, a high-level input terminal, a low-level input terminal, a signal output terminal, a first signal conversion module and a second signal conversion module, wherein an input terminal of the first signal conversion module is connected to the start signal input terminal, an output terminal of the first signal conversion module is connected to an input terminal of the second signal conversion module, and an output terminal of the second signal conversion module is connected to the signal output terminal, the first signal conversion module is further connected to the clock signal terminal, the high-level input terminal and the low-level input terminal, respectively, the second signal conversion module is further connected to the clock signal terminal, the high-level input terminal and the low-level input terminal, respectively, one of a high-level signal inputted from the high-level input terminal and a low-level signal inputted from the low-level input terminal is an active signal, and the other is an inactive signal, and a clock signal is inputted from the clock signal terminal; in a preprocessing stage where the clock signal is at a first level and the start signal is an inactive signal, an inactive signal is outputted to the second signal conversion module by the first signal conversion module, and an inactive signal is outputted by the second signal conversion module based on the inactive signal outputted by the first signal conversion module and the clock signal; in a first signal writing stage where the clock signal is at a second level and the start signal is an active signal, an inactive signal is outputted to the second signal conversion module by the first signal conversion module, and an inactive signal is outputted by the second signal conversion module based on the inactive signal outputted by the first signal conversion module and the clock signal; in a second signal writing stage where the clock signal is at the first level and the start signal is an active signal, an active signal is outputted to the second signal conversion module by the first signal conversion module, and an inactive signal is outputted by the second signal conversion module based on the active signal outputted by the first signal conversion module and the clock signal; in a first output stage where the clock signal is at the second level and the start signal is an inactive signal, an active signal is outputted to the second signal conversion module by the first signal conversion module, and an active signal is outputted by the second signal conversion module based on the active signal outputted by the first signal conversion module and the clock signal; and in a second output stage where the clock signal is at the first level and the start signal is an inactive signal, an inactive signal is outputted to the second signal conversion module by the first signal conversion module, and an active signal is outputted by the second signal conversion module based on the inactive signal outputted by the first signal conversion module and the clock signal.