Patent ID: 9568550
Date: 2017-02-14
CPC Classifications: G01R

Claim:
1. A method for identifying at least one failure indicating scan test cell of an integrated circuit-under-test (CUT) the CUT having a plurality of scan test cells, the method comprising generating a plurality of error signatures by means of a compactor of the CUT, each of the error signatures of the plurality of error signatures having a respective sequence of bits comprising at least one failure indicating bit; assigning each error signature of the plurality of error signatures to one of at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature; and mapping at least a predefined minimum number of error signatures of the plurality of error signatures to respective scan test cells of the plurality of scan test cells, for each error signature of the plurality of error signatures, a priority for the mapping determined by the signature type the respective error signature has been assigned to.