Patent ID: 9727676
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A method of compressing a timing model representing at least one circuit path of an electronic circuit, the circuit path traversing at least one circuit stage coupled to a plurality of pins, the method comprising: predefining a plurality of alternate input parameter values for a predetermined input parameter and a plurality of alternate output parameter values for a predetermined output parameter for the circuit path, each of the predefined alternate input parameter values having associated therewith an input signal waveform representing voltage change over time; and executing a processor to generate a timing model for instantiating each combination of predefined alternate input and output parameter values, the timing model defining a timing arc between each selected combination of predefined alternate input and output parameter values, the timing arc being decomposed into at least first and second timing arc components; the generation of the timing model including: wherein the first timing arc component defines, for each of the predefined alternate input parameter values, a first arc output waveform based on the corresponding predefined alternate input parameter value and subject to a common value of the predetermined output parameter at the waveform invariant node, and wherein the second timing arc component defines, for each of the predefined alternate output parameter values, a second arc output waveform based commonly on the uniform waveform and subject to the corresponding predefined alternate output parameter value; wherein the electronic circuit is adaptively updated responsive to testing based on the timing model.