Patent ID: 9679969
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A method of reducing carrier number fluctuation and flicker noise of a finFET device, the method comprising: forming, on an upper surface of a semiconductor substrate, at least one semiconductor fin completely comprising a first semiconductor material that extends from the upper surface of the semiconductor substrate to an upper surface of the at least one semiconductor fin, the at least one semiconductor fin having a channel region interposed between opposing source/drain regions; forming a flowable insulator layer on the source/drain regions, and forming a dummy gate structure on the channel region; forming a high-k gate oxide layer between the dummy gate structure and the at least one semiconductor fin; selectively removing the dummy gate structure with respect to the flowable insulator layer so as to expose the channel region of the at least one semiconductor fin; and forming a dual channel region to increases a distance of carrier paths further away from the high-k gate oxide layer, the dual channel region formed by depositing a heterojunction semiconductor material in the area where the dummy gate has been removed such that dual channel region includes a surface channel portion that completely surrounds sidewalls and an upper surface of a buried channel portion.