Patent ID: 9564449
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a well of a first conductivity type located within a substrate of a second conductivity type; a well terminal electrically coupled to the well; a floating gate disposed over the well; a floating gate terminal electrically coupled to the floating gate; a control gate disposed over the floating gate; and a control gate terminal electrically coupled to the control gate; wherein the control gate terminal is electrically connected with the well terminal; wherein the floating gate terminal is configured to receive a first voltage; wherein the control gate terminal and the well terminal are configured to receive a second voltage; wherein the well comprises a source region and a drain region; wherein the well of the first conductivity type is an N-well and the substrate is a P-type substrate; and wherein the semiconductor device is configured to conduct an electric current in the well between the source region and the drain region when the floating gate is negatively charged by the first voltage.