Patent ID: 9698305
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A high voltage LED flip chip, comprising: two or more regions, wherein the two or more regions comprise a first region where an upper electrode is to be formed and a second region where a lower electrode is to be formed; a Mesa-platform comprising a first semiconductor layer, a quantum well layer and a second semiconductor layer, wherein the Mesa-platform in each of the two or more regions has a first groove; a first electrode located on the Mesa-platform, wherein an area between the first electrodes in two adjacent regions forms a second groove; a first insulation layer, wherein the first insulation layer covers the Mesa-platforms and the first electrodes, the first insulation layer fills the second groove and partially fills the first groove, and a part of the first groove which is not filled forms a third groove; a fourth groove formed in the first insulation layer, wherein the fourth groove exposes a surface of the first electrode; an interconnection electrode, wherein the interconnection electrode comprises a first portion connecting the first semiconductor layer through the third groove in a particular region with the first electrode through the fourth groove in another region adjacent to the particular region, the interconnection electrode further comprises a second portion connecting with the first semiconductor layer in the first region and a third portion connecting with the first electrode in the second region, wherein a fifth groove is formed between two adjacent portions of the interconnection electrode; a second insulation layer, wherein the second insulation layer covers the interconnection electrode and fills the fifth groove; a sixth groove formed in the second insulation layer, wherein the sixth groove exposes the interconnection electrode in the second region; a second electrode, wherein the second electrode covers the second insulation layer and connects with the interconnection electrode through the sixth groove in the second region; a conductive plate located on the second electrode; a seventh groove formed between adjacent regions, wherein the seventh groove partitions the first semiconductor layers, the quantum well layers and the second semiconductor layers in different regions; and an eighth groove formed in the first semiconductor, wherein the eighth groove exposes the interconnection electrode in the first region.