Patent ID: 9588890
Date: 2017-03-07
CPC Classifications: G06F,G11C,H01L

Claim:
1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes: a substrate; a first contact plug formed over the substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer formed over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance; and a second electrode layer formed over the variable resistance layer.