Patent ID: 9728266
Date: 2017-08-08
CPC Classifications: G11C,H01L

Claim:
1. An apparatus comprising: a conductive line; a first memory cell string and a second memory cell string; and a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus; a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level; a first select line to provide a first voltage to the first select gate during an operation of the apparatus; a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value; a third select line to provide a third voltage to the third select gate during the operation; a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values; first control lines coupled to the first memory cell string; and second control lines coupled to the second memory cell string, the second control lines being different from the first control lines, and the operation includes one of an operation of storing information in a memory cell of the first memory cell string and an operation of reading information from a memory cell of the first memory cell string.