Patent ID: 9535788
Date: 2017-01-03
CPC Classifications: G06F,H03M

Claim:
1. A memory controller, comprising: circuitry configured to: a plurality of registers, wherein each register of the plurality of registers is configured to a given one of a plurality of coefficients of the ELP; a first plurality of multipliers, wherein a first multiplier of the first plurality of multipliers is configured to multiply a first one of the plurality of the coefficients of the ELP by a first corresponding power of a first field element of the plurality of field elements to generate a first bit of an interim product during a first cycle; and a second plurality of multipliers, wherein each multiplier of the second plurality of multipliers is configured to calculate, in parallel, a next power of a second field element of the plurality of field elements in response to a determination that the interim product is non-zero.