Patent ID: 9679631
Date: 2017-06-13
CPC Classifications: G06F,G11C

Claim:
1. An SRAM memory device comprising: a memory array comprising a plurality of SRAM banks, wherein each SRAM bank includes a block of SRAM memory cells organized as a matrix of X-rows and Y-columns and memory cell access circuitry; a pair of separate and distinct pipes associated with each of the SRAM banks, each pair of pipes providing independent access to its associated SRAM bank, wherein each pair of pipes includes: a write pipe configured with a separate complete write address pre-decoder bus, separate write control signals, a separate internal write data input bus, a separate m-deep write buffer that manages write data and write address propagation from input pins to memory array, and a write timing clock signal circuit; and a read pipe configured with a separate complete read address pre-decoder bus, separate read control signals, a separate internal read data output bus, a separate k-stage output pipeline that manages read data propagation from memory to output pins, and associated read timing clock signals; and wherein the device is configured such that each pair of pipes provides the access to its associated SRAM bank substantially parallel to, or staggered overlap in time, with access to other SRAM banks via other pairs of pipes.