Patent ID: 9666480
Date: 2017-05-30
CPC Classifications: G02F,G09G,H01L

Claim:
1. An array substrate comprising a plurality of pixel units, wherein each pixel unit comprises a thin-film transistor, a pixel electrode and a common electrode, a passivation layer covers on the pixel electrode and the thin-film transistor, the common electrode is located on the passivation layer and corresponds to the location of the pixel electrode, and a drain electrode of the thin-film transistor is electrically connected with the pixel electrode, and wherein a passivation layer via hole is formed in the passivation layer; each pixel unit further comprises an electrical connection block that fills the passivation layer via hole; the drain electrode of the thin-film transistor is provided on the pixel electrode and directly lapped on the pixel electrode, and one end of the electrical connection block is provided in contact with the drain electrode of the thin-film transistor via the passivation layer via hole, and the other end is exposed to the surface of the array substrate.