Patent ID: 9685437
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A high-voltage transistor device, comprising: a p-type semiconductor substrate provided with a p-type epitaxial layer; a high-voltage transistor, formed with an n-type well in the p-type epitaxial layer, a p-type body region in the p-type epitaxial layer, an n-type source region in the p-type body region, an n-type drain region in the n-type well, a channel region arranged in the p-type body region between the n-type well and the n-type source region, and a gate electrode arranged above the channel region, wherein a substrate compensation region is present at the boundary between the p-type semiconductor substrate and the p-type epitaxial layer, the substrate compensation region forming a p-type deep body region underneath the n-type source region and the channel region, the p-type semiconductor substrate and the p-type epitaxial layer are present adjacent to the p-type deep body region, and the p-type deep body region has a higher dopant concentration than the adjacent p-type semiconductor material; and a further high-voltage transistor, which is formed with a p-type well in the p-type epitaxial layer above an n-type body well, an n-type body region in the p-type epitaxial layer, a p-type source region in the n-type body region, a p-type drain region in the p-type well, a further channel region arranged in the n-type body region between the p-type well and the p-type source region, a further gate electrode arranged above the further channel region, and an n-type sinker well region in the p-type semiconductor substrate and in the p-type epitaxial layer underneath the p-type source region and the further channel region, wherein the n-type sinker well region has a higher dopant concentration than the n-type body well, the n-type sinker well region extends the n-type body region towards the p-type semiconductor substrate with increasing dopant concentration and connects the n-type body region electrically to the n-type body well, the p-type epitaxial layer has a first sublayer and a second sublayer, the first sublayer being arranged between the second sublayer and the p-type semiconductor substrate, a lower boundary of the n-type well and a lower boundary of the p-type well are arranged in the first sublayer of the p-type epitaxial layer, and the dopant concentration of the first sublayer is smaller than the dopant concentration of the second sublayer and smaller than the dopant concentration of p-type semiconductor substrate at the boundary between p-type semiconductor substrate and the p-type epitaxial layer.