Patent ID: 9558828
Date: 2017-01-31
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a first NAND string including a plurality of memory cells and first and second select memory cells whose source and drain are serially connected, a second NAND string including a plurality of memory cells and third and fourth select memory cells whose source and drain are serially connected, the third select memory cell being selected at a same time as the first select memory cell and having a threshold voltage different from a threshold voltage of the first select memory cell, and the fourth select memory cell being selected at a same time as the second select memory cell and having a threshold voltage different from a threshold voltage of the second select memory cell, a bit line arranged in correspondence to the first and second NAND strings, a first source line connected to the second NAND string, a second source line connected to the first NAND string, and a plurality of word lines that select plural memory cells arranged in a row direction from among the plurality of memory cells, wherein the first NAND string is selected by the first to fourth select memory cells and data is written in a first memory cell of the first NAND string, then the second NAND string is selected by the first to fourth select memory cells and data is written in a second memory cell of the second NAND string, then a verify read operation is performed for the first memory cell, then a verify read operation is performed for the second memory cell, and then if it is detected as a verify read result that the memory cell is insufficiently written, data is written again in the first memory cell of the first NAND string and in the second memory cell of the second NAND string at a write time, and the bit line is arranged between the first and second NAND strings and connected to the first and second NAND strings.