Patent ID: 9607918
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A Fan-Out Wafer Level Package (FO-WLP), comprising: a molded package body; a first microelectronic device embedded in the molded package body and having a backside contact; an Embedded Ground Plane (EGP) further embedded in the molded package body; and a backside EGP interconnect structure embedded in the molded package body and bonded to the backside contact such that the first microelectronic device is electrically coupled to the EGP through the backside EGP interconnect structure; a second microelectronic device embedded in the molded package body and electrically coupled to the EGP through the backside EGP interconnect structure; wherein the second microelectronic device has a height less than the first microelectronic device; and wherein the backside EGP interconnect structure comprises one or more stepped features compensating for the difference in height between the first and second microelectronic devices.