Patent ID: 9588528
Date: 2017-03-07
CPC Classifications: G05F,H02H

Claim:
1. An inrush current suppression circuit, comprising: an input circuitry configured to receive an input voltage from a voltage source and configured, upon receipt thereof, to supply a gate voltage; an output circuitry configured to supply an output voltage; a current limiter circuit coupled between the input circuitry and the output circuitry, the current limiter circuit including a field effect transistor (FET) that comprises a gate terminal coupled to receive the gate voltage, the current limiter circuit configured, based on the gate voltage, to vary current flow from the output circuitry to the load; a load enable circuit coupled to the gate terminal, the load enable circuit configured to (i) sense the gate voltage and (ii) supply a load enable signal when the gate voltage is equal to or exceeds a predetermined voltage magnitude; and a load coupled to receive (i) the output voltage from the output circuitry and (ii) the load enable signal from the load enable circuit, the load configured such that it will not be fully energized until it receives the load enable signal.