Patent ID: 9721633
Date: 2017-08-01
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: banks each including a memory cell array; word lines connected to rows in each of the banks; a first address latch circuit which latches a full row address specifying one of the word lines, the full row address including a first row address and a second row address; and a second address latch circuit which latches a column address specifying one of the columns of the bank, wherein: the first address latch circuit receives a first command and a second command and includes a first latch circuit and a second latch circuit, the first latch circuit latches the first row address in response to the first command, the second latch circuit latches the second row address in response to the second command, the first latch circuit and the second latch circuit are separate from each other, and the second address latch circuit receives the second command and latches the column address in response to the second command.