Patent ID: 9548301
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate including a first region and a second region; a first gate structure disposed on the first region; a second gate structure disposed on the first region; a third gate structure disposed on the second region; a fourth gate structure disposed on the second region; a first embedded stressor disposed in the first region and disposed between the first gate structure and the second gate structure; and a second embedded stressor disposed in the second region and disposed between the third gate structure and the fourth gate structure, wherein a first shortest distance between the first gate structure and the second gate structure is different from a second shortest distance between the third gate structure and the fourth gate structure, the first embedded stressor includes a first lower semiconductor layer and a first upper semiconductor layer disposed on the first lower semiconductor layer, the second embedded stressor includes a second lower semiconductor layer and a second upper semiconductor layer disposed on the second lower semiconductor layer, and a first thickness between an uppermost portion and a lowermost portion of the first upper semiconductor layer is different from a second thickness between an uppermost portion and a lowermost portion of the second upper semiconductor layer.