Patent ID: 9704955
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor device comprising: providing a heavily doped semiconductor layer; forming a lightly doped semiconductor layer on the heavily doped semiconductor layer; forming a first trench and a second trench in the semiconductor layer, the first and second trenches forming a mesa in the lightly doped semiconductor layer; forming by epitaxial growth a first epitaxial layer of a first conductivity type on sidewalls of the first and second trenches, adjacent the mesa; forming by epitaxial growth a second epitaxial layer of a second conductivity type opposite the first conductivity type on the first epitaxial layer; forming a first dielectric layer in the first and second trenches, adjacent the second epitaxial layer, the first dielectric layer filling at least part of the trenches; forming a gate dielectric layer on the sidewalls of the first and second trenches above the first dielectric layer; and forming a gate conductive layer in the first and second trenches above the first dielectric layer and adjacent the gate dielectric layer, wherein the first epitaxial layer and the second epitaxial layer form adjacent doped regions along the sidewalls of the first and second trenches, wherein charges in a region of the mesa between the doped regions along the sidewalls of the first and second trenches and charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation.