Patent ID: 9673151
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface of the substrate; an encapsulant encapsulating the first surface of the substrate and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, wherein each of the package units has at least one of the semiconductor components; a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface of the substrate exposed from the metal layer, wherein the metal layer is formed on a groove surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface; and a filling material for filling the second groove, wherein the filling material is an insulating material or a conductive material having a conductivity lower than that of the metal layer.