Patent ID: 9727466
Date: 2017-08-08
CPC Classifications: G06F,Y02D

Claim:
1. An interconnect for connecting devices, the devices including a plurality of master devices, one or more of the master devices having associated cache storage, the interconnect comprising: coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices; snoop filter circuitry to maintain address-dependent caching indication data and, responsive to a data access transaction specifying a target address, to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage; the coherency control circuitry being responsive to said snoop control data to issue a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data; and analysis circuitry to determine from the snoop response data an update condition where there is an inconsistency between the snoop response data and the snoop control data, and upon detection of said update condition to trigger performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data to remove said inconsistency.