Patent ID: 9721959
Date: 2017-08-01
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a memory cell comprising: wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor and an electrode of the capacitor, wherein a gate electrode of the second transistor is electrically connected to the other of the source electrode and the drain electrode of the third transistor, wherein the first transistor and the third transistor each comprise an oxide semiconductor layer, wherein a channel formation region of the second transistor comprises a semiconductor material other than an oxide semiconductor, wherein the gate electrode of the second transistor is directly connected to only the third transistor, and wherein the gate electrode of the second transistor is directly connected to only the other of the source electrode and the drain electrode of the third transistor.