Patent ID: 9671294
Date: 2017-06-06
CPC Classifications: G01K

Claim:
1. A semiconductor device comprising: first and second power lines; an output node; a pull up circuit comprising a first transistor coupled between the first power line and the output, node, the pull up circuit configured to generate a pull up current (Ipup); a pull down circuit comprising a second transistor coupled between the second power line and the output node, the pull down circuit configured to generate a pull down current (Ipdn); a first additional current path comprising a third transistor and a first switch coupled in series between the first power line and the output node, the first additional current path configured to generate a first additional current that combines with the pull up current (Ipup) to generate a first output current (Ia); and a second additional current path comprising a fourth transistor and a second switch coupled in series between the second power line and the output node, the second additional current path configured to generate a second additional current that combines with the pull down current (Ipdn) to generate a second output current (Ib).