Patent ID: 9548945
Date: 2017-01-17
CPC Classifications: H04L

Claim:
1. A chip comprising a network, wherein the network includes: a plurality of processing engines; and a matrix of on-chip routers, wherein each of the on-chip routers is communicatively coupled with a distinct group of the processing engines and with on-chip routers nearest to that on-chip router in the matrix of on-chip routers, and wherein each of the on-chip routers includes a plurality of input ports, a plurality of output ports, and a plurality of an output port arbiters such that there is one of the output arbiters at each of the output ports, wherein each one of the plurality of output port arbiters uses a global grant vector shared by all of the plurality of output port arbiters of that on-chip router and a local grant vector unique to that one of the plurality of output port arbiters to grant a query request from one of the input ports such that the grant of the query request by the one of the plurality of output arbiters is based on both the global grant vector shared by the plurality of output arbiters and the local grant vector associated with the one of the plurality of output arbiters.