Patent ID: 9666517
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a lower package comprising a lower substrate and a lower semiconductor chip on the lower substrate; an interposer substrate on the lower substrate and laterally spaced apart from the lower semiconductor chip, the interposer substrate comprising a first thickness that is unequal to a second thickness of the lower semiconductor chip; lower connection terminals between the lower substrate and the interposer substrate to electrically connect the lower substrate to the interposer substrate, the lower connection terminals comprising a first pitch; upper connection terminals on the interposer substrate and electrically connected to the interposer substrate, the upper connection terminals comprising a second pitch longer than the first pitch of the lower connection terminals; and an upper package on the interposer substrate and the lower semiconductor chip and electrically connected to the upper connection terminals, the upper package comprising an upper substrate and an upper semiconductor chip, wherein some of the upper connection terminals form m rows that are adjacent and parallel to a first outer side of the interposer substrate, wherein some of the lower connection terminals form n rows that are adjacent the first outer side of the interposer substrate, wherein m is greater than n, and wherein each of n and m is a natural number.