Patent ID: 9691971
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method for fabricating an integrated circuit that includes a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM), the method comprising: forming a metal interconnect above a semiconductor substrate and aligned with a normal axis substantially perpendicular to the semiconductor substrate, wherein the metal interconnect has an upper surface including a central portion and an outer portion; forming a lower electrode on the central portion of the upper surface of the metal interconnect and aligned with the normal axis, wherein the lower electrode comprises a conductive metal plug; forming a MTJ stack on the lower electrode aligned with the normal axis, wherein the MTJ stack has a top surface, a bottom surface, and opposite side surfaces extending from the bottom surface to the top surface; depositing a passivation layer directly on the top surface and the opposite side surfaces of the MTJ stack and forming the passivation layer with an upper surface having an uppermost segment directly overlying the MTJ stack, lowermost segments adjacent to the MTJ stack, and vertically-extending segments extending from the uppermost segment to the lowermost segments; and depositing an interlayer dielectric material directly on the uppermost segment, the vertically-extending segments, and the lowermost segments of the upper surface of the passivation layer.