Patent ID: 9576841
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first-conductivity-type semiconductor layer including a second-conductivity-type channel layer formed between the active region and the marginal region so as to form a front surface of the semiconductor layer; at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer; a gate insulation film formed on an inner surface of the at least one gate trench; a gate electrode formed inside the gate insulation film in the at least one gate trench; a plurality of isolation trenches arranged between the active region and the marginal region to surround the outer periphery of the active region and formed to extend from the front surface of the semiconductor layer through the channel layer, the plurality of isolation trenches having a depth equal to a depth of the at least one gate trench, the plurality of isolation trenches being formed in a trench isolation region between the active region and the marginal region; a trench insulation film formed on an inner surface of the isolation trenches, the trench insulation film having a bottom portion formed on a bottom surface of the isolation trenches and a side portion formed on side surfaces of the isolation trenches, and a thickness of the bottom portion being larger than a thickness of the side portion; at least one dummy cell arranged at an outer most part of the active region to form an outer edge of a lattice of a plurality of unit cells, and not being given a function of the transistor; and a buried electrode formed inside the trench insulation film to be in each of the plurality of isolation trenches.