Patent ID: 9659840
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method comprising: providing a gate stack, with source/drain regions at opposite sides thereof, and a shallow trench isolation (STI) layer on a silicon substrate; forming a nitride layer directly over the gate stack, the STI layer, and the silicon substrate; forming a through silicon via (TSV) trench, laterally separated from the gate stack, through the nitride layer, STI layer and the silicon substrate; forming an isolation layer directly on an entirety of the nitride layer without any intervening layer between the isolation layer and the nitride layer when viewed in cross-section, with a single deposition process, such that the isolation layer is formed on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.