Patent ID: 9619377
Date: 2017-04-11
CPC Classifications: G06F,G11C,Y02D

Claim:
1. An integrated circuit comprising: at least one processor forming a central processing unit in the integrated circuit; a power management circuit configured to transmit voltage requests to an external power management unit to supply one or more voltages to the integrated circuit, wherein the external power management unit is external to the integrated circuit; a memory controller coupled to a memory during use, wherein the power management circuit is configured to cause a power down of the memory controller via communication to the external power management unit; and a first component coupled to the processor and the memory controller, wherein the first component is configured to remain powered while the processor, the power management circuit, and the memory controller are powered off, and wherein the first component is coupled to the external power management unit separate from the power management circuit and is configured to cause the memory controller to power up via communication to the external power management unit that is separate from the power management circuit, to program the memory controller using memory controller configuration data stored in the first component, and to communicate with the memory controller during a time that the processor is powered down.