Patent ID: 9619427
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. An integrated circuit, comprising: a first processor; a plurality of messaging signal registers, wherein the first processor is configured to write a transmit set of messaging signals into the messaging signal registers; a plurality of GPIO pins; a GPIO interface configured to receive a first set of signals from the first processor and to transmit a portion of the first set of signals as GPIO signals to a remote processor over the plurality of GPIO pins; a dedicated transmit pin; and a finite state machine (FSM) configured to receive a remaining portion of the first set of signals from the GPIO interface and to serially transmit the remaining portion as a transmit set of virtual GPIO signals to the remote processor over the dedicated transmit pin, and wherein the FSM is further configured to retrieve a transmit set of messaging signals from the messaging signal registers and to serially transmit the transmit set of messaging signals to the remote processor over the dedicated transmit pin.