Patent ID: 9584309
Date: 2017-02-28
CPC Classifications: G06F,H03K,H04L

Claim:
1. A bit-leveling circuit for performing bit-leveling for a data interface including operating first and second calibration processes, the circuit comprising at least: a circuit for providing a data strobe signal; a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit signal to provide a delayed data bit signal; at least one flip-flop for sampling the delayed data bit signal; a bit-leveling controller circuit responsive to the sampled delayed data bit signal and for controlling the delay of the programmable delay line; wherein the bit leveling circuit: wherein operation of the bit leveling circuit includes performing the first calibration process comprising: determining a sum of Ta and Tb; wherein if the sum of Ta and Tb is less than a pre-determined jitter detection threshold value, the bit leveling circuit performs the second calibration process comprising: