Patent ID: 9673334
Date: 2017-06-06
CPC Classifications: G09G,H01L

Claim:
1. A low temperature poly silicon thin film transistor (LTPS TFT), comprising: a substrate; a first gate arranged on the substrate; a polysilicon layer arranged on the substrates, wherein the polysilicon layer covers the first gate, and the polysilicon layer comprises a source area, a drain area, and a trench area formed between the source area and the drain area; a second gate arranged on the polysilicon layer; wherein when the LTPS TFT has been driven, the first gate and the second gate are respectively applied with a first voltage and a second voltage, and a polarity of the first voltage is opposite to the polarity of the second voltage; wherein the first gate, the trench area, and the second gate are at least partially overlapped, respectively; wherein the LTPS TFT further comprising: a gate insulation layer covering the polysilicon layer and the second gate; a source being arranged above the gate insulation layer, and the source connects to the source area via a first through hole arranged within the gate insulation layer; and a drain being arranged on the gate insulation layer, and the drain connects to the drain area via a second through hole arranged within the gate insulation layer.