Patent ID: 9564587
Date: 2017-02-07
CPC Classifications: G11C,H01L

Claim:
1. A method for fabricating memory with a segmented interconnect, comprising: forming a stack of layers comprising a set of insulator layers comprising an electrical insulating material and a set of electrode layers comprising an electrical conducting metal, wherein insulator layers alternate with electrode layers in the stack of layers that are stacked in a first direction; etching a via in the stack of layers comprising removing a portion of at least one electrode layer of the set of electrode layers, wherein the via segments the at least one electrode layer into a first portion and a second portion, exposing to the via a first surface of the first portion and a second surface of the second portion, and wherein at least one of the first surface or the second surface forms an oblique angle with respect to the first direction; forming within the via, a second electrode layer differing from the set of electrode layers and comprising another electrical conducting metal; and forming a switching layer between the second electrode layer and the first surface and between the second electrode layer and the second surface.