Patent ID: 9691883
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A split gate flash memory cell comprising: a semiconductor substrate comprising a first source/drain region and a second source/drain region laterally spaced from the first source/drain region; an erase gate arranged over the first source/drain region; a floating gate and a word line laterally spaced over the semiconductor substrate between the first and second source/drain regions, wherein the floating gate is arranged between the word line and the erase gate, wherein the floating gate comprises an asymmetric profile about an axis at a width-wise center of the floating gate, and wherein the word line is L-shaped with a single ledge adjacent to the second source/drain region; a first dielectric layer arranged between the floating gate and the word line, wherein the first dielectric layer is L-shaped, spaced from the floating gate, and in contact with the word line, and wherein a bottom surface of the first dielectric layer is even with bottom surfaces respectively of the word line and the floating gate; a dielectric spacer arranged over and contacting the single ledge of the word line; a control gate arranged over the floating gate; and a second dielectric layer over the floating gate, and between the control and erase gates, wherein the second dielectric layer has an L-shaped profile and is spaced from the erase gate, the floating gate, and the control gate, and wherein the second dielectric layer has a single ledge extending laterally to a sidewall of the second dielectric layer that is adjacent to the erase gate and that is aligned to a sidewall of the floating gate; wherein a top corner of the erase gate neighbors the control gate and is even with top surfaces respectively of the first dielectric layer and the dielectric spacer, wherein a bottom corner of the floating gate neighbors the erase gate, wherein the top corner of the erase gate is laterally spaced from the bottom corner of the floating gate in a direction away from the floating gate, wherein the dielectric spacer has a rectangular profile with a planar to surface that is coplanar with planar top surfaces respectively of the first and second dielectric layers, wherein the floating gate comprises a single ledge that is adjacent to the erase gate and that is recessed below a top surface of the floating gate, and wherein a bottom surface of the second dielectric layer is vertically spaced between the single ledge of the word line and the single ledge of the floating gate.