Patent ID: 9548654
Date: 2017-01-17
CPC Classifications: G05F,H02M,H03K

Claim:
1. A delay circuit for providing a dead time delay to operate a driver transistor of a switching DC to DC conversion system, the delay circuit comprising: a first inverter circuit, comprising: a diode-connected MOS transistor coupled to provide an impedance between the first inverter circuit and a first one of the regulated voltage node and the constant voltage node; a MOS capacitor coupled between the first inverter output node and the first one of the regulated voltage node and the constant voltage node, the MOS capacitor and the diode-connected MOS transistor establishing a first inverter delay for the first inverter circuit; a second inverter circuit, comprising: an output inverter circuit, comprising: a supply circuit providing a voltage at the first compensated voltage node which decreases with increasing temperature.