Patent ID: 9723231
Date: 2017-08-01
CPC Classifications: H04N

Claim:
1. An image data processing apparatus comprising: N×N memories configured to store pixel data of N (N≧2) read lines of image pickup devices; write control circuit configured to select, in a row or column direction, memories for writing from among the N×N memories, write the pixel data in sets of N pixels to each of the memories selected for writing, and switch a selection direction for selecting the memories for writing each time writes of the pixel data of the N read lines are completed; and read control circuit configured to select, in a direction different from the selection direction, N memories for reading from among the N×N memories and start parallel reads of the written pixel data of the N read lines during writes of the pixel data of every N-th read line, wherein: among the N×N memories, each of the memories to be first selected in the writes of the pixel data of every N-th read line performs a write and a read using different terminals thereof and each of remaining memories performs a write and a read using a common terminal thereof; the write control circuit writes N sets of first parallel data in sets of N pixels to each of the N memories selected for writing, the N sets of first parallel data each having a data sequence where one out of every N pixels in a reading order of the pixel data being read from the image pickup devices appears; and each of N sets of second parallel data read from the N memories selected for reading has a data sequence sorted in the reading order.