Patent ID: 9590594
Date: 2017-03-07
CPC Classifications: H03K

Claim:
1. A level shifter circuit comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; a ninth transistor; a tenth transistor; a first capacitor; a second capacitor; a first potential power supply line; a second potential power supply line; a third potential power supply line; an output signal line; an inverted output signal line; an input signal line; and an inverted input signal line, wherein one of a source and a drain of the first transistor is electrically connected to the first potential power supply line, wherein the other of the source and the drain of the first transistor is electrically connected to the inverted output signal line, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the sixth transistor, wherein one of a source and a drain of the second transistor is electrically connected to the first potential power supply line, wherein the other of the source and the drain of the second transistor is electrically connected to the output signal line, wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fifth transistor, wherein one of a source and a drain of the third transistor is electrically connected to the inverted output signal line, wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the ninth transistor, wherein a gate of the third transistor is electrically connected to the input signal line, wherein one of a source and a drain of the fourth transistor is electrically connected to the output signal line, wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the tenth transistor, wherein a gate of the fourth transistor is electrically connected to the inverted input signal line, wherein the other of the source and the drain of the fifth transistor is electrically connected to the second potential power supply line, wherein a gate of the fifth transistor is electrically connected to the input signal line, wherein the other of the source and the drain of the sixth transistor is electrically connected to the second potential power supply line, wherein a gate of the sixth transistor is electrically connected to the inverted input signal line, wherein one of a source and a drain of the seventh transistor is electrically connected to the input signal line, wherein the other of the source and the drain of the seventh transistor is electrically connected to a gate of the ninth transistor, wherein a gate of the seventh transistor is electrically connected to the third potential power supply line, wherein one of a source and a drain of the eighth transistor is electrically connected to the inverted input signal line, wherein the other of the source and the drain of the eighth transistor is electrically connected to a gate of the tenth transistor, wherein a gate of the eighth transistor is electrically connected to the third potential power supply line, wherein the other of the source and the drain of the ninth transistor is electrically connected to the second potential power supply line, wherein the other of the source and the drain of the tenth transistor is electrically connected to the second potential power supply line, wherein a first electrode of the first capacitor is electrically connected to the output signal line, wherein a second electrode of the first capacitor is electrically connected to the gate of the ninth transistor, wherein a first electrode of the second capacitor is electrically connected to the inverted output signal line, and wherein a second electrode of the second capacitor is electrically connected to the gate of the tenth transistor.