Patent ID: 9626311
Date: 2017-04-18
CPC Classifications: G06F,H01L

Claim:
1. A three-dimensional (3D) integrated circuit (IC) (3DIC) comprising: a plurality of semiconductor IC tiers; a memory controller circuit disposed in a semiconductor IC tier among the plurality of semiconductor IC tiers and coupled to one or more memory buses; at least one processor core disposed in at least one of the plurality of semiconductor IC tiers and communicatively coupled to the memory controller circuit; at least one memory IC disposed in at least one of the plurality of semiconductor IC tiers; a plurality of distributed through-silicon-via (TSV) farms each configured to electrically interconnect the plurality of semiconductor IC tiers, wherein each of the plurality of distributed TSV farms comprises a plurality of TSVs; and two or more memory-access TSV farms selected from the plurality of distributed TSV farms and configured to provide interconnections to the at least one memory IC; wherein each of the one or more memory buses is connected to the at least one memory IC through a respective memory-access TSV farm among the two or more memory-access TSV farms; wherein the memory controller circuit is placed to provide an approximately equal wire-length to each of the two or more memory-access TSV farms; wherein the memory controller circuit is configured to service memory access requests between the at least one processor core and the at least one memory IC.