Patent ID: 9658282
Date: 2017-05-23
CPC Classifications: G01R

Claim:
1. A method for determining a fault probability of a location on a chip, comprising: applying, using a computer, a number of tests at a number of input nodes of a circuit chip, wherein each test defines for each input node a test input choice; measuring for each test a signal at each of a number of measurement nodes to acquire for each measurement node a number of measurement values, wherein each measurement value is associated to the test it was measured for and to the measurement node it was measured at; determining relevance values for detection of a fault on the circuit chip, wherein each relevance value is calculated based on a correlation between normalized test input choices and normalized measurement values associated to the test it was measured for and to the measurement node it was measured at, each relevance value representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for detection of a fault on a chip, determining for each signal path of a fourth number of signal paths of the chip, a distance from a location to each of the fourth number of signal paths of the chip, wherein each signal path extends from an input node of the first number of input nodes to a measurement node of the second number of measurement nodes; and determining the fault probability based on adding the distances to each of the fourth number of paths weighted by the relevance value of the combination of the input node the respective path extends from, and the measurement node the respective path extends to.