Patent ID: 9607852
Date: 2017-03-28
CPC Classifications: G03F,H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: designing target pattern layouts, including layouts of lower target patterns and upper target patterns by using a computer; combining each lower target pattern with an upper target pattern that at least partially overlaps a top surface of the lower target pattern to form combination structures by using the computer; dividing the combination structures into a first combination structure and a second combination structure, wherein the first combination structure and the second combination structure are respectively formed by a first exposure process and a second exposure process by using the computer; forming first to fourth exposure masks, the first exposure mask and the third exposure mask being used for forming the lower target pattern and the upper target pattern in the first combination structure, the second exposure mask and the fourth exposure mask being used for forming the lower target pattern and the upper target pattern in the second combination structure; forming a first lower pattern from a first object layer on a substrate using the first exposure mask in a first lithography process; forming a second lower pattern from the first object layer using the second exposure mask in a second lithography process; forming an insulating interlayer and a second object layer on the first and second lower patterns; form a first upper pattern from the second object layer using the third exposure mask in a third lithography process; and forming a second upper pattern from the second object layer using the fourth exposure mask in a fourth lithography process.