Patent ID: 9575692
Date: 2017-02-21
CPC Classifications: G06F

Claim:
1. A cache control device having a fault-tolerant function, comprising: a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data; a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data; and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation, wherein each of the cache memory and the shadow cache memory comprises a tag memory and a data memory, the specific address is stored in the tag memory of each of the cache memory and the shadow cache memory, the first data and the first parity bit are stored in the data memory of the cache memory, and the second data and the second parity bit are stored in the data memory of the shadow cache memory, and wherein the first data and the second data are same as each other, and the first parity bit and the second parity bit are same as each other, when the result of the parity check operation on the first data indicates that there is an error, the fault detector compares the first parity bit and the second parity bit, when the first parity bit and the second parity bit are different from each other, the fault detector performs the parity check operation on the second data, and when there is no error in the second data, the fault detector transmits the second data to the processor, and when the first parity bit and the second parity bit are same as each other, the fault detector outputs an error message.