Patent ID: 9660034
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: a plurality of silicon on insulator (SOI) type MOS transistors; an insulator layer supporting said plurality of SOI type MOS transistors; a substrate layer supporting said insulator layer, said substrate layer including a plurality of first wells configured to be separately biased, wherein each first well is doped with a first conductivity type, and wherein each first well includes, under the insulator layer of each SOI type MOS transistor, a back gate region that is more heavily doped than the first well, and wherein the first wells are separated from each other by and included within a second well configured to be separately biased and doped with a second conductivity type; and wherein at least one of the back gate regions is doped with the second conductivity type and is positioned adjacent to an overdoped region of the first conductivity type located under a corresponding insulator layer.