Patent ID: 9595315
Date: 2017-03-14
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; a bit line sense amplifier to sense an electric potential difference between a bit line and a complementary bit line during a sensing operation for the memory cells; a first column select gate to transfer an electric potential on the bit line to a local sense amplifier based on a column select signal; and a second column select gate to transfer an electric potential on the complementary bit line to the local sense amplifier based on the column select signal, wherein the first and second column select gates have different sizes which correspond to different current drive abilities to compensate a difference in hit line interconnection resistance, wherein an interconnection length between the bit line and the first column select gate is different from an interconnection length between the complementary bit line and the second column select gate, and wherein, when an interconnection length between the complementary bit line and the second column select gate is greater than an interconnection length between the bit line and the first column select gate, the current drive ability of the second column select gate is greater than the current drive ability of the first column select gate.