Patent ID: 9666609
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. An array substrate wiring comprising: a first wiring formed on an substrate for transmitting electric signals; an insulating layer formed on the first wiring; a second wiring formed on the insulating layer for protecting the first wiring, being opposite to the first wiring, the second wiring being in a floating state, wherein the first wiring comprises a scan line wiring located in a scan line wiring area and a data line wiring located in a data line wiring area, and the second wiring comprising a scan line protection wiring located in the scan line wiring area and a data line protection wiring located in the data line wiring area, and wherein the first wiring is formed in synchronization with a gate metal layer, and the second wiring is formed in synchronization with a source drain metal layer, and the data line wiring is connected with the source drain metal layer through a transparent electrode layer.