Patent ID: 9570475
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. An array substrate, comprising a display region and a non-display region, the display region comprising a transistor, the transistor comprising a source electrode, a drain electrode and an active layer, the source electrode and the drain electrode being provided on the active layer and being respectively provided at two ends of the active layer, wherein, the non-display region is provided with an alignment mark, the alignment mark is provided in a same layer as the active layer; the active layer comprises a semiconductor layer and an ohmic contact layer which are sequentially stacked, the ohmic contact layer is provided on the semiconductor layer, and the ohmic contact layer is provided to correspond to and in contact with the source electrode and the drain electrode; a film for forming the semiconductor layer and a film for forming the ohmic contact layer are further formed in the non-display region; and the alignment mark comprises a first alignment mark, the first alignment mark is formed in the film for forming the semiconductor layer and in the film for forming the ohmic contact layer.