Patent ID: 9583066
Date: 2017-02-28
CPC Classifications: G09G

Claim:
1. A driving apparatus of a display panel, comprising: a first gate driver connected to a first trigger signal terminal, configured to drive odd lines of gate lines on the display panel; a second gate driver connected to a second trigger signal terminal, configured to drive even lines of gate lines on the display panel; a first gating control module, connected in series between the first trigger signal terminal and the first gate driver; and a second gating control module, connected in series between the second trigger signal terminal and the second gate driver; wherein the first gating control module and the second gating control module each comprises a mode control signal terminal configured to receive a mode control signal; wherein the first gating control module and the second gating control module are configured to respectively control the first gate driver and the second gate driver to drive in a first mode when the mode control signal is in a first state and to respectively control the first gate driver and the second gate driver to drive in a second mode when the mode control signal is in a second state; wherein, in the first mode, when odd frames of images are displayed, the odd lines of gate lines are driven sequentially by the first gate driver, and when even frames of images are displayed, the even lines of gate lines are driven sequentially by the second gate driver; or, when the odd frames of images are displayed, the even lines of gate lines are driven sequentially by the second gate driver, and when the even frames of images are displayed, the odd lines of gate lines are driven sequentially by the first gate driver; and wherein in the second mode, when various frames of images are displayed, respective lines of gate lines are driven progressively; wherein, the first gating control module further comprises a first gating clock signal terminal; wherein the second gating control module further comprises a second gating clock signal terminal; wherein the first gating control module comprises a first Negated AND (NAND) gate, and a second NAND gate, a first NOT gate and a second NOT gate; wherein the first NOT gate has: an input terminal which is the first gating clock signal terminal of the first gating control module: and an output terminal connected to a first input terminal of the said NAND gate; wherein the first NAND gate has: a second input terminal which is the mode control signal terminal of the first gating control module: and an output terminal connected to a first input terminal of the second NAND gate; wherein the second NAND gate has: a second input terminal connected to the first trigger signal terminal: and an output terminal connected to an input terminal of the second NOT gate; and wherein the second NOT gate has an output terminal connected to the first gate driver.