Patent ID: 9536778
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method, comprising: forming a hard mask over a dielectric layer; forming a patterning template including a plurality of parallel linear elements disposed on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces between said adjacent parallel linear elements; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines, wherein forming said cut mask further defines a power line perpendicular to and at an end of the two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.