Patent ID: 9715916
Date: 2017-07-25
CPC Classifications: G11C

Claim:
1. An apparatus, comprising: a plurality of signal lines including a pair of complementary bit line signal lines, a first word line signal line and a second word line signal line; a supply line; and a bitcell configured to store a bit state, said bitcell including a common node and first and second complementary resistance state storage cells, each resistance state storage cell having an input coupled to the common node and an output coupled to a complementary bit line signal line, each complementary resistance state storage cell having a storage cell switch transistor having an input coupled to the first word line signal line, and a resistance state ferromagnetic device coupled in series with the storage cell switch transistor of the complementary resistance state storage cell and having a resistance state complementary to a resistance state of the resistance state ferromagnetic device of the complementary resistance state storage cell, and a supply switch transistor having an input coupled to the second word line signal line and configured to couple the common node to the supply line when activated.