Patent ID: 9595565
Date: 2017-03-14
CPC Classifications: G01N,H01L

Claim:
1. A memory structure, comprising: a substrate; a plurality of word lines, disposed in parallel on said substrate; a plurality of bit lines, disposed in parallel on said substrate, perpendicular to the parallel direction of said plurality of word lines, interlacing with and covering said plurality of word lines at a plurality of cross points, and the material of said plurality of bit lines being iridium oxide, ruthenium oxide, platinum, palladium, cobalt, rhenium, rhodium, or graphene; and a plurality of middle layers disposed at said plurality of cross points and located between said plurality of word lines and said plurality of bit lines and including a first dielectric film and a second dielectric film arranged bottom-up sequentially; where the material of said second dielectric film is selected from the group consisting of gadolinium oxide, hafnium oxide, tantalum oxide, nickel oxide, zirconium oxide, chromium oxide, titanium oxide, tungsten oxide, cerium oxide, and germanium oxide; wherein a top surface of said plurality of bit lines includes a plurality of nanometer micro holes.