Patent ID: 9666252
Date: 2017-05-30
CPC Classifications: G06N,G11C

Claim:
1. A semiconductor device comprising: a memory cell array in which a plurality of memory cells are disposed in a matrix configuration; a word line provided in correspondence with rows of the plurality of memory cells; a bit line pair provided in correspondence with columns of the plurality of memory cells; and a word decoder configured to activate the word line, wherein the word line is activated and the bit line pair is fixed to a voltage at the same level; wherein the word decoder is a multiword decoder configured to multiplex a word address according to an input of a multiplicity specify signal to the word line and simultaneously activate a plurality of word lines; and a driver configured to drive the bit line pair and simultaneously subject the plurality of memory cells activated by the plurality of the word lines to a write operation or a read operation; wherein in the memory cell array, a group of a predetermined number of the plurality of memory cells is collected in a unit and a plurality of the units are disposed with an adjacency; the plurality of units further include an arithmetic operation circuit configured to receive a value of a memory cell in another unit in adjacency and outputs a value subjected to an arithmetic operation based on the received value and a coefficient stored on an memory cell; the memory cell array further includes an address decoder configured to specify the group of units in adjacency that operates the arithmetic operation in synchronization; and the arithmetic operation is performed a predetermined number of times for each group of units specified by the address decoder and then a process is repeated in which memory cells of the plurality of units are sequentially activated using the multiword decoder; wherein after the arithmetic operation is performed the predetermined number of times, a process is performed in which the plurality of memory cells of the plurality of units are sequentially activated using the multiword decoder and a power supply voltage below a predetermined voltage is supplied to the plurality of memory cells of the plurality of units.