Patent ID: 9590117
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A memory device comprising: a semiconductor layer including two slit-shaped trenches, the slit-shaped trenches extending in a first direction; device isolation insulating layers provided in the slit-shaped trenches; a first electrode provided above the semiconductor layer between the device isolation insulating layers; a first layer including a first metal oxide and provided above the first electrode; a second layer including an oxide and provided above the first layer; a third layer including a second metal oxide and provided above the second layer; and a second electrode including a Ti-nitride layer and a W layer, the Ti-nitride layer provided above the third layer, and the W layer provided above the Ti-nitride layer, wherein the oxide has a higher barrier height than both the first and the second metal oxides, the W layer extends in a second direction crossing the first direction over the device isolation insulating layers and the first electrode, the first layer, the second layer, the third layer are an insulating film of a DRAM capacitor, and a first conductive line is provided on the device isolation insulating layers and above a part of the semiconductor layer, and extends in the second direction crossing the first direction.