Patent ID: 9748396
Date: 2017-08-29
CPC Classifications: G02F,H01L

Claim:
1. A method of manufacturing a thin film transistor comprising a gate electrode, a gate insulating film, a channel layer containing an oxide semiconductor, a source electrode, a drain electrode, and a protective film covering the source electrode and the drain electrode, the method comprising: forming at least one of the source electrode and the drain electrode by using a laminated metal film comprising a lower barrier layer, a low-resistance main wiring layer, and an upper cap layer arranged in this order when viewed from the channel layer toward the protective film, the low-resistance main wiring layer mainly containing one of copper and an copper alloy, the lower barrier layer mainly containing a molybdenum alloy, and the upper cap layer mainly containing a molybdenum alloy containing nickel and made from a different material from the low-resistance main wiring layer; and patterning the lower barrier layer, the low-resistance main wiring layer, and the upper cap layer of the laminated metal film together by wet etching using a solution mainly containing hydrogen peroxide and an organic acid.