Patent ID: 9654100
Date: 2017-05-16
CPC Classifications: G09G,H03K

Claim:
1. An output buffer comprising: a first amplifier configured to amplify an input signal and output first to fourth amplified signals; a first transistor comprising a first drain, a first gate configured to receive the first amplified signal, and a first source; a second transistor comprising a second drain directly connected to the first drain at a first node, a second gate configured to receive the second amplified signal, and a second source; a third transistor comprising a third drain, a third gate configured to receive the third amplified signal, and a third source directly connected to the second source; a fourth transistor comprising a fourth drain directly connected to the third drain at a second node, a fourth gate configured to receive the fourth amplified signal, and a fourth source; an output node directly connected to the first and second nodes; and a first controller configured to selectively supply a control voltage to the first to fourth gates in response to a control signal.