Patent ID: 9716092
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a plurality of transistors arranged in two rows and n columns on a substrate, where n≧4, to constitute a NAND circuit having g input signals, where n=h×g, and each of g and h is an integer, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate, each of the plurality of transistors including: the plurality of transistors including: wherein the n p-channel MOS transistors and the n n-channel MOS transistors are arranged such that a p-channel MOS transistor in a k-th column and an n-channel MOS transistor in the k-th column form a pair, where k=1 to n, the gate of the p-channel MOS transistor in the k-th column and the gate of the n-channel MOS transistor in the k-th column being connected to one another, the drain regions of the n p-channel MOS transistors and the drain regions of h n-channel MOS transistors in first to h-th columns are located on a side of the silicon pillars close to the substrate, and are connected to one another via a silicide region, and the n columns are grouped into g sets each having h columns, and the source regions of n-channel MOS transistors in a g-th set and the drain regions of n-channel MOS transistors in a (g+1)-th set are connected to one another.