Patent ID: 9621167
Date: 2017-04-11
CPC Classifications: H03K,H03L

Claim:
1. A logic circuit, comprising: a setting circuit which holds and outputs setting information; a first flip-flop which holds data written to the setting circuit and outputs it in synchronization with an inputted clock; a second flip-flop which holds a write address for selecting the setting circuit and outputs it in synchronization with the inputted clock; and a third flip-flop which holds write enable which allows writing to the setting circuit and outputs it in synchronization with the inputted clock, wherein the setting circuit includes a fourth flip-flop which holds the setting information in synchronization with a given timing signal, a selector which gives one of the output of the fourth flip-flop and the output of the first flip-flop to the input of the fourth flip-flop, and a gate circuit which controls a selection state of the selector on a basis of the output of the second flip-flop and the output of the third flip-flop, and wherein the setting circuit further includes a fifth flip-flop which holds the output of the third flip-flop and outputs a write clock to the fourth flip-flop as the timing signal in synchronization with the inputted clock.