Patent ID: 9599671
Date: 2017-03-21
CPC Classifications: G01R

Claim:
1. A method for performing a partial-scan test of at least one integrated circuit, comprising: obtaining a plurality of test cubes including at least one justification cube of the at least one integrated circuit; identifying a plurality of scan flip-flops in the test cubes; and with a cube merging procedure, (i) identifying each previously-identified scan flip-flop of the integrated circuit that is individually convertible to a non-scan flip-flop, and (ii) performing the partial-scan test based on only the test cubes; wherein the identification procedure of each previously-identified scan flip-flop further includes identifying a particular previously-identified scan flip-flop (i) where there are no 0-1 conflicts between a particular test cube that requires the particular previously-identified scan flip-flop to be at a particular value and a particular justification cube associated with the particular previously-identified scan flip-flop for the particular value, and (ii) where the particular justification cube does not specify a bit of the particular previously-identified scan flip-flop to a 0 or a 1.