Patent ID: 9564424
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. An ESD device comprising: an input of the ESD device; a common return of the ESD device; a semiconductor substrate of a first conductivity type; a first semiconductor layer of a second conductivity type on the semiconductor substrate and having a first doping concentration; a first blocking structure formed as a first closed polygon having a periphery that surrounds a first portion of the first semiconductor layer; a first transistor formed on the first semiconductor layer and within the first portion of the semiconductor substrate, the first transistor having a first current carrying electrode coupled to one of the input or the common return, the first transistor having a control electrode and a second current carrying electrode; a first semiconductor region of the first conductivity type within the first portion of the first semiconductor layer, wherein the first semiconductor region forms a portion of the first transistor, the first semiconductor region having a second doping concentration that is greater than the first doping concentration of the first semiconductor layer; a first low capacitance diode formed on the first semiconductor layer and external to the first portion of the semiconductor substrate, the first low capacitance diode coupled in series between the input and the first current carrying electrode of the first transistor; a first conductor having a first conductor portion formed in an opening that extends through the first semiconductor layer to a portion of the semiconductor substrate and physically and electrically contacting a portion of the semiconductor substrate, the first conductor having a second conductor portion electrically coupled to the second current carrying electrode of the first transistor; and a trigger device formed on the first semiconductor layer and within the first portion of the first semiconductor layer, the trigger device having a trigger voltage and coupled to the control electrode of the first transistor wherein the trigger device is configured to enable the first transistor responsively to the input of the ESD device receiving a voltage that is no less than the trigger voltage of the trigger device.