Patent ID: 9673815
Date: 2017-06-06
CPC Classifications: H01S,H03F,H03K,H04B

Claim:
1. A circuit comprising: a first input node configured to receive a first signal of a differential input signal; a second input node configured to receive a second signal of the differential input signal; first and second output nodes; an amplification circuit coupled to the first and second input nodes, the amplification circuit configured to receive the first signal and the second signal of the differential input signal and to generate a first intermediate signal based on the first signal of the differential input signal and to generate a second intermediate signal based on the second signal of the differential input signal; a transistor circuit coupled to the first and second output nodes and the amplification circuit, the transistor circuit configured to conduct based on the first and second intermediate signals; an adjust circuit configured to receive the first and second intermediate signals and to generate a first adjusted intermediate signal based on the first intermediate signal and to generate a second adjusted intermediate signal based on the second intermediate signal; and an output circuit coupled to the amplification circuit and the first and second output nodes, the output circuit configured to output first and second output signals on the first and second output nodes based on the respective first and second adjusted intermediate signals.