Patent ID: 9568970
Date: 2017-02-14
CPC Classifications: G06F,H04L,Y02D

Claim:
1. A hardware element of one or more of a System on Chip (SoC) and Network on Chip (NoC) implemented at a first level of the one or more of the NoC and the SoC, the hardware element configured to: execute a power state switching sequence for one or more first set of hardware elements that are in direct connection to the hardware element, based on instructions received from one or more second set of hardware elements to be configured in accordance with a power profile, wherein the power profile comprises a power state for each of the one or more first set of hardware elements, the power state indicative of the each of the one or more first set of hardware elements to be on or off, wherein the power state switching sequence comprises a sequence to power on or power off the one or more of the first set of hardware elements.