Patent ID: 9553111
Date: 2017-01-24
CPC Classifications: G02F,H01L

Claim:
1. A thin film transistor array substrate comprising: a substrate having a surface; a thin film transistor formed on said surface of said substrate; a common wiring formed on said substrate; a first interlayer insulating film formed on said thin film transistor and said common wiring; a second interlayer insulating film formed on said first interlayer insulating film; a common electrode formed on said second interlayer insulating film; a third interlayer insulating film formed on said common electrode; and a pixel electrode formed on said third interlayer insulating film, wherein said pixel electrode is connected with a drain electrode of said thin film transistor via a first aperture formed on said second interlayer insulating film, a second aperture that includes a bottom portion of said first aperture and is formed on said common electrode, a third aperture that includes at least a part of the bottom portion of said first aperture, is included in said second aperture and is formed on said third interlayer insulating film, a fourth aperture that is formed on said first interlayer insulating film having a shape similar, in a plan view, to a shape of an overlap region where said third aperture overlaps with the bottom portion of said first aperture, and the direction of viewing for the plan view is along a normal to said surface of said substrate.