Patent ID: 9653160
Date: 2017-05-16
CPC Classifications: G11C

Claim:
1. A memory device comprising: a memory cell array including a normal memory region and a redundant memory region, the normal memory region operating in response to a data signal and a plurality of normal memory region signals, the redundant memory region operating in response to the data signal and a plurality of redundant memory region signals; and an address decoder including a normal memory region signal generator and a redundant memory region signal generator, wherein the normal memory region signal generator activates first normal memory region signals and the redundant memory region signal generator activates a first redundant memory region signal simultaneously when the address decoder operates in a test mode, wherein the first normal memory region signals correspond to an address signal and are included in the plurality of the normal memory region signals, wherein the first redundant memory region signal corresponds to the address signal and is included in the plurality of the redundant memory region signals, wherein the normal memory region signal generator deactivates the first normal memory region signals when one of the redundant memory region signals is activated when the address decoder operates in a normal mode, wherein the address decoder further includes a block signal generator configured to output a result of performing a logical OR operation on the plurality of the redundant memory region signals as a block signal.