Patent ID: 9659126
Date: 2017-05-23
CPC Classifications: G03F,G05B,G06F

Claim:
1. A non-transitory computer-readable medium holding computer-executable instructions for identifying and modeling pattern dependent effects in a 3-D virtual semiconductor device fabrication environment provided by a computing device, the instructions when executed causing the computing device to: generate a 2-D local mask from a 3-D model of a semiconductor device structure; combine a global mask corresponding to 2D design layout data with the local mask to create a combined mask; convolve at least one proximity function with the combined mask to create at least one convolved mask; create a loading map using the at least one convolved mask, the loading map indicative of process behavior for a pattern dependent process step for virtual semiconductor device fabrication that varies as a result of one or more of pattern density, feature size or aspect ratio dependence; and execute an algorithm to model the pattern dependent process step during virtual semiconductor device fabrication, a behavior of the algorithm altered based on the loading map.