Patent ID: 9570582
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of forming a metal gate comprising the steps of: forming a dummy gate dielectric layer and a dummy gate electrode on a surface of a semiconductor substrate; forming sidewall spacers on opposing sides of dummy gate electrode and the dummy gate dielectric layer; forming source/drain regions in the semiconductor substrate; depositing an interlayer insulating layer and an interlayer dielectric layer; removing a portion of the interlayer insulating layer and the interlayer dielectric layer above the dummy gate electrode to expose the dummy gate electrode; removing the dummy gate electrode; removing the dummy gate dielectric layer by a first plasma to expose the semiconductor substrate; then removing a fluorinated compound on the surface of the semiconductor substrate by a second plasma; forming a gate dielectric layer and a metal gate in sequence on the surface of the semiconductor substrate within sidewall spacers; wherein a material of the dummy gate dielectric layer contains Si and O; the first plasma contains F, and the second plasma contains H