Patent ID: 9691635
Date: 2017-06-27
CPC Classifications: H01L,Y10T

Claim:
1. A method of manufacturing a semiconductor package, the method comprising: coupling a semiconductor die and a substrate, wherein: encapsulating the semiconductor die and the substrate to form an encapsulation that covers at least the perimeter die sides and the first substrate side, but does not cover the second substrate side, the encapsulation comprising a first encapsulation side facing away from the substrate and a second encapsulation side facing the substrate; laser-ablating a via hole through at least the encapsulation, the entire via hole extending through only insulative material; depositing conductive material within the via hole to form a conductive via; forming a first buildup dielectric layer on the encapsulation; ablating an artifact in the first buildup dielectric layer, wherein the ablated artifact comprises a channel in the first buildup dielectric layer, the channel extending in a direction parallel to the first substrate side; and depositing a first metal layer in the ablated artifact to form at least a portion of a first electrically conductive pattern in the first buildup dielectric layer.