Patent ID: 9568944
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. An apparatus comprising: a first silicon device configured in accordance with an Advanced RISC Machines™ (ARM) architecture, the first silicon device having a timer and at least one processing element; a second silicon device configured in accordance with the ARM architecture, the second silicon device having a timer and at least one processing element; an interconnect coupled between the first silicon device and the second silicon device such that both the first and second silicon devices have access to any of the processing elements disposed on both the first and second silicon devices; and at least one of the first and second silicon devices configured to determine an offset between the timer of the first silicon device and the timer of the second silicon device in accordance with a total delay of a first synchronization message transmitted from the first silicon device to the second silicon device and a total delay of a second time synchronization message transmitted from the second silicon device to the first silicon device.