Patent ID: 9696379
Date: 2017-07-04
CPC Classifications: G01R,G11C

Claim:
1. A semiconductor device, comprising: a first chip and a second chip, which are physically conjoined to form a vertically stacked structure with vertical connections between the first and second chips; wherein the first chip comprises functional circuitry and memory elements to store system state data which represents a microarchitecture of the functional circuitry; wherein the second chip comprises control circuitry for accessing and restoring system state data in the memory elements on the first chip; and wherein in response to an occurrence of a state capture triggering event, the control circuitry of the second chip is configured to: wherein the functional circuitry on the first chip comprises a plurality of scan cells comprising scannable flip-flops and latches; wherein the second chip further comprises scan testing circuitry, and a scan testing I/O (input/output) interface, wherein the scan cells of the first chip are connected to the scan testing I/O interface, and wherein the scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry; wherein the scan testing circuitry on the second chip comprises: demultiplexer circuits; multiplexer circuits; and scan chain configuration and testing control circuitry, wherein each demultiplexer circuit has an input that is connected to an output of a scan cell on the first chip through the scan testing I/O interface, and two or more outputs that are connected to inputs of different multiplexer circuits; wherein each multiplexer circuit has an output that is connected to an input of a scan cell on the first chip through the scan testing I/O interface, and two or more inputs that are connected to outputs of different demultiplexer circuits; wherein the scan chain configuration and testing control circuitry generates control signals to control the demultiplexer and multiplexer circuits to dynamically configure the electrical connections between outputs and inputs of the scan cells on the first chip to form the scan chains or scan rings.