Patent ID: 9638976
Date: 2017-05-02
CPC Classifications: G02F,H01L

Claim:
1. A method of fabricating a thin film transistor array substrate, the method comprising: providing a substrate comprising a plurality of photo-sensitive spacer areas and a plurality of planarized layer opening areas, the photo-sensitive spacer areas being in close proximity to the planarized layer opening areas; forming a plurality of thin film transistors on the substrate, each of the plurality of thin film transistors comprises a source and a drain; patterning a light shielding layer on the substrate between the plurality of thin film transistors and the substrate using a mask, wherein the light shielding layer overlaps the drains and channel areas of the plurality of thin film transistors but does not overlap the photo-sensitive spacer areas; forming a first planarized layer over the plurality of thin film transistors; etching the first planarized layer to form a plurality of planarized layer openings wherein the said openings expose the drains of the plurality of thin film transistors; forming a pixel electrode layer on the first planarized layer, wherein the pixel electrode layer contacts the drains through the planarized layer openings but only partially fills the said openings; forming a second planarized layer on the pixel electrode layer, wherein the second planarized layer fills the planarized layer openings; patterning the second planarized layer using the same mask for the light shielding layer to form a portion of the second planarized layer in an area corresponding to the light shielding layer; and removing a remaining portion of the second planarized layer in the photo-sensitive spacer areas.