Patent ID: 9601487
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A power transistor comprising: a semiconductor body comprising a plurality of semiconductor fins that are spaced in a first lateral direction of the semiconductor body, and a semiconductor layer adjoining the semiconductor fins in a vertical direction of the semiconductor body, wherein the plurality of semiconductor fins comprises a first group of first semiconductor fins and a second group of second semiconductor fins, wherein a width of the second semiconductor fins of the second group is larger than a width of the first semiconductor fins of the first group; a plurality of source regions, wherein each first semiconductor fin of the first group includes one of the plurality of source regions; a plurality of drain regions, wherein each second semiconductor fin of the second group includes one of the plurality of drain regions; a plurality of body regions, wherein each body region is arranged between one of the plurality of source regions and one of the plurality of drain regions; a plurality of gate electrodes, wherein each gate electrode is arranged in a corresponding trench adjacent one of the first group of first semiconductor fins, is adjacent one of the plurality of body regions, and is dielectrically insulated from the one of the plurality of body regions by a gate dielectric; a source node electrically coupled to each of the source regions; a drain node electrically coupled to each of the drain regions; and a gate node electrically coupled to each of the gate electrodes.