Patent ID: 9577027
Date: 2017-02-21
CPC Classifications: H01L,H05K

Claim:
1. A semiconductor device, comprising: a substrate including a first surface; a seed layer disposed on the first surface; a first patterned metal layer disposed on the seed layer, the first patterned metal layer having a first thickness, and the first patterned metal layer including a first part and a second part; a first dielectric layer disposed on the first part of the first patterned metal layer; a second metal layer disposed on the first dielectric layer and having a second thickness, wherein the first thickness is greater than the second thickness; and a third metal layer, wherein the third metal layer is disposed on the first part of the first patterned metal layer or disposed between the first part of the first patterned metal layer and the first dielectric layer, and the third metal layer has a third thickness, wherein the third thickness is greater than the second thickness; wherein the first part of the first patterned metal layer, the first dielectric layer and the second metal layer form a capacitor, and wherein the first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.