Patent ID: 9698148
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A transistor, comprising: a first fin disposed on a first region of a substrate; a gate structure and a first dummy gate disposed on the first fin; a first gate oxide layer disposed between the gate structure and the first fin, and also disposed between the first dummy gate and the first fin; a source region disposed at least partially within the first fin, wherein the source region is disposed between the gate structure and the first dummy gate; a second fin disposed on a second region of the substrate and spaced laterally apart from the first fin; second and third dummy gates disposed on the second fin; a second gate oxide layer disposed between the second dummy gate and the second fin, and also disposed between the third dummy gate and the second fin; and a drain region disposed at least partially within the second fin, wherein the drain region is disposed between the second and third dummy gates; wherein a thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer; wherein the first region of the substrate is doped with dopant atoms of a first conductivity tune, and wherein the second region of the substrate is doped with dopant atoms of a second conductivity type; wherein the second region of the substrate is further divided into a first sub-region and a second sub-region that are laterally adjacent to one another, wherein the second sub-region of the second region of the substrate is disposed beneath the drain region and not beneath the are structure; and wherein a first dopant concentration of the first sub-region is less than a second dopant concentration of the second sub-region.