Patent ID: 9606948
Date: 2017-03-28
CPC Classifications: G06F,H04L

Claim:
1. A method of bus edge-timing control suitable for use in a controller area network (CAN) including nodes communicating over a differential bus including differential (dominant) data bit signals with a differential voltage, and common-mode (recessive) data bit signals with a common-mode voltage, each with a transmission bit period, comprising: transmitting transmit data (TxD) generated by a node including dominant and recessive data bit signals; detecting a dominant-to-recessive data bit falling-edge transition in the transmit data (TxD); and during the dominant-to-recessive falling-edge transition, performing a recessive nulling operation by adding at least one recessive nulling impedance based on the common-mode voltage in parallel with the differential bus starting at the time of the dominant-to-recessive data bit transition and extending for a selected recessive nulling time period in order to increase a rate of decay of the dominant-to-recessive falling-edge transition.