Patent ID: 9559112
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A semiconductor memory device, comprising: a plurality of bit lines on a substrate and spaced apart from each other in a first direction, the bit lines extending in a second direction that intersects the first direction; a string selection line between the substrate and the bit lines, the string selection line extending in the first direction; a plurality of word lines between the substrate and the string selection line, the word lines extending in the first direction; a plurality of vertical channels connected to the bit lines and surrounded by the word lines and the string selection line, the vertical channels extending in a third direction being substantially perpendicular to a surface of the substrate; a plurality of data storage layers between the word lines and the vertical channels; and a word line cut between the plurality of vertical channels, the word line cut penetrating the string selection line and the plurality of word lines, the word line cut extending in the first direction, wherein the word line cut includes a void, and wherein an upper surface of the void is positioned at a higher level than a lower surface of the string selection line.