Patent ID: 9633856
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method comprising: forming a dielectric layer over a semiconductor substrate; forming a metal layer over the dielectric layer, wherein the metal layer has a first work function type; treating the metal layer to incorporate a dopant into the metal layer to form a treated metal layer having a second work function type that is opposite the first work function type, wherein the treated metal layer has a top surface facing away from the semiconductor substrate and opposing bottom surface facing the semiconductor substrate such that a thickness of the treated metal layer is measured from the bottom surface to the top surface of the treated metal layer, wherein a region extending from the bottom surface of the treated metal layer toward the top surface of the treated metal layer is free of the dopant, wherein the region extends away from the bottom surface by at least 10% of the thickness of the treated metal layer; forming a conductive layer over the treated metal layer; and patterning the conductive layer, the treated metal layer, and the dielectric layer to form a gate structure.