Patent ID: 9698791
Date: 2017-07-04
CPC Classifications: G06F,H03K

Claim:
1. A forwarding plane comprising: a scalable array of field programmable gate array (FPGA) devices that is configured to execute a networking application source code that is partitioned among the FPGA devices as a plurality of computing elements executed by the FPGA devices with a uniform global memory address space; a memory bank that includes an allocated portion of one or more of the FPGA devices, wherein the memory bank is addressable by the uniform global memory address space; FPGA data and transport network ports that are configured to be coupled to one or more data networks, wherein the FPGA data and transport network ports include one or more ingress ports that are configured to receive traffic and egress ports that are configured to transmit traffic; and an array interconnect that is included in the scalable array, wherein the array interconnect is configured to: