Patent ID: 9570457
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor structure for a split gate flash memory cell device, the semiconductor structure comprising: a semiconductor substrate including a first source/drain region and a second source/drain region; a control gate and a memory gate spaced over the semiconductor substrate between the first and second source/drain regions; a charge trapping dielectric structure arranged between the memory gate and the control gate, and arranged under the memory gate; and a hard mask arranged over the control gate and including an asymmetric profile, the asymmetric profile tapering in height away from the memory gate, wherein the hard mask is a dielectric and shares a width with the control gate, and wherein the hard mask and the control gate share a first common sidewall on a first side of the control gate and a second common sidewall on a second side of the control gate that is opposite the first side.