Patent ID: 9684459
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A memory system comprising: a nonvolatile memory; a host interface configured to receive a first read command indicating a logical address to access the nonvolatile memory from a host system, the memory system functioning as an external storage device of the host system, the host system accessing the memory system according to an operating system (OS); and a controller configured to determine whether or not the first read command and a second read command indicating logical addresses top of which is sequential to end of logical addresses indicated by the first read command are sequentially received by the host interface and an increase rate of a size of read data requested in the second read command with respect to a size of read data requested in the first read command matches a predetermined increase rate, the predetermined increase rate being larger than zero, and to execute, when the first read command and the second read command are sequentially received by the host interface and the increase rate of the size of read data requested in the second read command with respect to the size of read data requested in the first read command matches the predetermined increase rate, a process according to a third read command indicating logical addresses top of which is sequential to end of the logical addresses indicated by the second read command before the host interface receives the third read command.