Patent ID: 9715936
Date: 2017-07-25
CPC Classifications: G11C

Claim:
1. A nonvolatile memory device comprising: a nonvolatile memory cell array; an x-selector configured to select a plurality of memory cells among the nonvolatile memory cell array based on an address; and a page buffer configured to read identification data and user data from the plurality of memory cells, a peripheral circuit configured to receive a command, to select one of a single data rate (SDR) mode and a double data rate (DDR) mode in response to the command, and to receive a first signal toggling between a high level and a low level; wherein, in the SDR mode, the identification data is output in synchronization with a rising edge or a falling edge of the first signal during a data output cycle, in the DDR mode, the user data is output in synchronization with both the rising edge and the falling edge of the first signal during the data output cycle, and the identification data includes at least one of a maker code, a device code, a page size and a block size of the nonvolatile memory device, wherein the identification data is only output in the SDR mode, and the user data is output in the selected mode among the SDR mode and the DDR mode.