Patent ID: 9689914
Date: 2017-06-27
CPC Classifications: G01R,H01L

Claim:
1. A method of testing a three-dimensional integrated circuit (3DIC), the method comprising: applying a voltage through at least one testing element and at least one conductive line, wherein the at least one conductive line traces a perimeter of at least one of a top chip or an interposer parallel to an outer edge of the at least one top chip or the interposer, and the at least one conductive line is configured to electrically connect a plurality of conductive connectors; and measuring a current responsive to the applied voltage, wherein determining the integrity of the 3DIC comprises comparing a resistance determined from the measured current to a calculated resistance based on the at least one testing element, the at least one conductive line, and a conductive connector of the plurality of conductive connectors.