Patent ID: 9665980
Date: 2017-05-30
CPC Classifications: G06T

Claim:
1. A graphics processing unit (GPU) configured to perform a tiling operation and a tessellation operation, comprising: a pre-tiler configured to perform the tiling operation before the tessellation operation; a post-tiler configured to perform the tiling operation after the tessellation operation; and a control logic configured to control, based on input data, whether the pre-tiler or the post tiler performs the tiling operation, wherein the control logic controls the post-tiler to perform the tiling operation after the tessellation operation if the input data does not correspond to a first patch, wherein the control logic control the post-tiler to perform the tiling operation after the tessellation operation if a geometry of a second patch is at the outside of a convex hull defined by control points of the second patch, and wherein the control logic controls the post-tiler to perform the tiling operation after the tessellation operation if a geometry of a tessellated primitive corresponding to a third patch changes according to a shading operation, wherein the control logic is a circuit.