Patent ID: 9613964
Date: 2017-04-04
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a source line; a bit line; a first signal line; a second signal line; a word line; and a memory cell connected between the source line and the bit line, wherein the memory cell comprises: wherein the first channel formation region includes an impurity element imparting a conductivity type so that a threshold voltage of the first transistor is positive, wherein the first gate electrode, the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other to form a node for holding charge, wherein the source line is electrically connected to the first source electrode, wherein the bit line is electrically connected to the first drain electrode, wherein the first signal line is electrically connected to the second source electrode, wherein the second signal line is electrically connected to the second gate electrode, and wherein the word line is electrically connected to the other of the electrodes of the capacitor, wherein the first channel formation region includes single crystal silicon, wherein the second channel formation region includes an oxide semiconductor, and wherein an off current of the second transistor is less than or equal to 10 zA at room temperature.