Patent ID: 9641175
Date: 2017-05-02
CPC Classifications: G01R,G11C,H03H,H03K

Claim:
1. A method for controlling first, second, third, fourth, fifth and sixth unit output buffers each having a first plurality of transistors connected between a power supply terminal and a data terminal comprising: receiving a first plurality of impedance control signals; receiving first, second, and third selection signals; turning-on ones of the first plurality of transistors in the first unit buffer if corresponding ones of the first plurality of impedance control signals are activated and the first selection signal is activated; turning-off ones of the first plurality of transistors in the first unit buffer if corresponding ones of the first plurality of impedance control signals are deactivated or the first selection signal is deactivated; turning-on ones of the first plurality of transistors in the second and third unit buffers if corresponding ones of the first plurality of impedance control signals are activated and the second selection signal is activated; turning-off ones of the first plurality of transistors in the second and third unit buffers if corresponding ones of the first plurality of impedance control signals are deactivated or the second selection signal is deactivated; turning-on ones of the first plurality of transistors in the fourth, fifth and sixth unit buffers if corresponding ones of the first plurality of impedance control signals are activated and the third selection signal is activated; and turning-off ones of the first plurality of transistors in the fourth, fifth and sixth unit buffers if corresponding ones of the first plurality of impedance control signals are deactivated or the third selection signal is deactivated.