Patent ID: 9542305
Date: 2017-01-10
CPC Classifications: G01R,G06F,G11C,H03K,H04L,H05K,Y02D

Claim:
1. An electronic assembly comprising: a memory device including a memory cell and a first communication line in electrical communication with the memory cell, wherein the first communication line is elongated and has a first end connected to the memory cell and a second end terminating at a via; a substrate supporting the via and including a second communication line connected to the second end at the via and extending therefrom; a first impedance matching circuit including a first Thevenin network connected to the first communication line; and a second impedance matching circuit including a second Thevenin network connected to the first communication line, the second impedance matching circuit being different than the first impedance matching circuit, and the second impedance matching circuit including a plurality of different impedance paths connected at different depths to the via and selectable to tune an impedance of the second impedance matching circuit to match the second communication line.