Patent ID: 9665493
Date: 2017-05-30
CPC Classifications: G06F

Claim:
1. A method for increased cache performance efficiency by a processor device in a computing environment, the method comprising: distributing to each one of a plurality of central processing units (CPUs) workload operations for creating complete cache tracks from partial cache tracks by creating a complete cache track queue and a partial cache track pointer without a lock by each one of the CPUs; using, by each one of the CPUs, an assembler queue to accumulate each of the complete cache tracks from the partial cache tracks including using a pointer copy of a partial cache track to assemble a complete cache track, the assembler queue sending each of the complete cache tracks to the complete cache track queue; creating sub-queues in front of each of the assembler queues accumulating the complete cache tracks, the sub-queues including both an append queue and a build queue, wherein the build queue fills the append queue using segments from the partial cache track pointer copy combined with a partial cache track and the append queue fills the assembler queue; and creating and throttling a plurality of demote scan tasks to continuously maintain pace with the filling of the complete cache track queue, the assembler queue, and the sub-queues.