Patent ID: 9747453
Date: 2017-08-29
CPC Classifications: G06F,H04L

Claim:
1. A virtualization platform comprising: a plurality of integrated independent levels of security components, interconnected via communication channels, integrated interceptor modules connected to said security components via said communication channels, wherein each integrated interceptor module being interposed in the communication channel connecting two components, wherein each integrated interceptor module is implemented by multiple threads comprising a first testing thread adapted to transmit data from an integrated analyzing device to a receiver component, and a second testing thread adapted to transmit data from a sender component into said analyzing device; and the integrated analyzing device connected to said integrated interceptor modules and comprising a control device and a testing device, said control device being configured to put each interceptor module in an operational mode selected out of a set of predetermined operational modes including a testing mode, and said testing device being configured to locally test the components connected to the interceptor modules being put in the testing mode, wherein in a testing mode a first testing thread of a first integrated interceptor module connected to a component under test is adapted to perform a blocked read on a destination port connected to the testing device and to introduce testing packets from the testing device into the component under test, and in that a second testing thread of a second integrated interceptor module connected to the component under test is adapted to transmit an output result from the component under test into the testing device, and perform a blocked read on the destination of a queuing channel connected to the sender component, said testing device being configured to test the reaction of the component under test by analyzing said output result; wherein the integrated interceptor module, the integrated analyzing device, control device, testing device, the first testing thread, the second testing thread, the sender component, and the receiver component are implemented using one or more hardware processing unit.