Patent ID: 9684516
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A processor that implements an instruction set architecture that aliases architected registers having different sizes, comprising: a physical register file comprising a plurality of physical registers configured to store data; and a register renamer distinct from the physical register file that, during operation, renames architected registers to corresponding physical registers, wherein the register renamer is organized into independently accessible even and odd banks, wherein the even bank and the odd bank each include a respective plurality of entries; wherein to rename a first architected register of a first size, the register renamer, during operation, stores an identifier of one of the physical registers within an entry selected from either the even bank or the odd bank; and wherein to rename a second architected register of a second size, wherein the second architected register is one of multiple architected registers of the second size that alias to the first architected register, the register renamer, during operation, stores an identifier of one of the physical registers within an entry selected from either the even bank or the odd bank and causes a false dependency to be generated with respect to the multiple architected registers other than the second architected register.