Patent ID: 9589653
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. An array of non-volatile memory (NVM) elements utilizing field effect transistors (FETs) comprising: a wordline with at least one NVM element, wherein the at least one NVM element includes a first FET coupled to bitline true of the at least one NVM element and a second FET coupled to bitline complement of the at least one NVM element, wherein the first FET is substantially similar to the second FET; a first negative channel FET (NFET) coupled to the bitline complement and a second NFET coupled to the bitline true, the first NFET configured to pull the bitline true toward ground in response to the bitline complement reaching a first voltage to give the at least one NVM element a default logical value, the second NFET configured to pull the bitline complement toward ground in response to the bitline true reaching a second voltage to give the at least one NVM element a programmed logical value; and at least one wordline driver for the wordline coupled to the at least one NVM element, wherein the at least one wordline driver is coupled to the at least one NVM element such that a first path from the at least one wordline driver is coupled to the first FET and a second path from the at least one wordline driver is coupled to the second FET, wherein the first path is current-limited respective to the second path such that a first slew rate between the at least one wordline driver and the first FET is slower than a second slew rate between the at least one wordline driver and the second FET when a signal for the wordline is raised before the wordline has been programmed such that the bitline complement will reach the first voltage.