Patent ID: 9646125
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. A method implemented in a computing infrastructure, comprising: obtaining an existing available microprocessor design; selecting a reliability grade for a desired level of immunity for an ionizing radiation event; evaluating a probability that one or more components of the existing available microprocessor design will be affected by a single event upset (SEU) using a computing device, the evaluating comprising: selecting a design choice based on the reliability grade for replacing the one or more components from the design choices comprising: a triple modular redundancy, a substitution of every transistor by a stacked device for complementary CMOS gates in SOI technologies which are resistant to latch up, a substitution of every latch with a DICE latch, and a substitution of only sensitive latches with an equivalent latch having at least one stacked device in SOI technologies which are resistant to latch up; selecting a process enhancement to provide an immune device; and replacing the one or more components in the existing available processor design, including each latch having the estimated failure rate greater than the target percentage, with a component immune to the SEU based on the selected design choice to create a final microprocessor design, wherein the reliability grade takes into account different factors including failure over a predetermined time period, failure rate to a specific flux, reliability of the final microprocessor design, cost of the final microprocessor design, size of the microprocessor design, and probability of failure at certain energy levels.