Patent ID: 9735772
Date: 2017-08-15
CPC Classifications: G01R,H01L,H03K

Claim:
1. An integrated circuit comprising: at least one integrated cell disposed at a location of the integrated circuit; a multiplexer coupled to at least one site of the integrated cell; first and second integrated devices coupled to the multiplexer and respectively oriented in two directions of orientation, the first integrated device being usable because of the first integrated device's direction of orientation and the second integrated device being unusable because of the second integrated device's direction of orientation; and a controller comprising two integrated test devices separate from the first and second integrated devices and respectively oriented in the two directions of orientation, the two integrated test devices being usable in each of the two directions of orientation, the controller being configured to detect a usability of the first integrated device and control the multiplexer to couple the first integrated device electrically to the at least one site.