Patent ID: 9684755
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A non-transitory computer readable medium storing instructions for isolating emulated units, the instructions to configure a host system to: identify a first set of field programmable gate arrays (FPGAs) included in an emulator and selected to emulate a first unit in a design under test (DUT); identify a second set of FPGAs included in the emulator and selected to emulate a second unit in the DUT, the second set of FPGAs different than the first set of FPGAs; designate an FPGA included in the emulator for routing connections between units of the DUT, the designated FPGA not part of the first and the second set of FPGAs; and determine a route for a connection between the first unit and the second unit through the designated FPGA.