Patent ID: 9646926
Date: 2017-05-09
CPC Classifications: H01L,H05K

Claim:
1. A wiring substrate comprising: a first wiring layer including a first wiring part having a first wiring interval and a second wiring part adjacent to the first wiring part and having a second wiring interval wider than the first wiring interval; a first insulation layer formed on the first wiring layer; a metal plane layer formed on a portion of the first insulation layer, the first wiring part being located below the portion; a second insulation layer formed on the first insulation layer and the metal plane layer; a first via hole extending, with a continuously linear central axis, from an upper surface of the second insulation layer, through the first and second insulation layers, to the second wiring part of the first wiring layer; a first via conductor formed in the first via hole and connected to the second wiring part of the first wiring layer; a second via hole formed in the second insulation layer and reaching the metal plane layer; a second via conductor formed in the second via hole; a second wiring layer formed on the second insulation layer and connected to the first wiring layer via the first via conductor; and a third wiring layer formed on the second insulation layer and connected to the metal plane layer via the second via conductor, wherein the first wiring part includes at least two lines and a first space between adjacent lines of the first wiring part, in a direction perpendicular to a longitudinal direction of each of the at least two lines of the first wiring part, is the first wiring interval, the second wiring part includes at least two lines and a second space between adjacent lines of the second wiring part, in a direction perpendicular to a longitudinal direction of each of the at least two lines of the second wiring part, is the second wiring interval, and the second space is larger than the first space.