Patent ID: 9638752
Date: 2017-05-02
CPC Classifications: G01R,H03K

Claim:
1. Measurement circuitry for measuring a clock node to output node delay of a flip-flop comprising: a main ring oscillator consisting of a plurality of main unit cells arranged sequentially to form a main ring, each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop, the flip-flop being configured to be responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry being configured to generate from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period; a reference ring oscillator consisting of a plurality of reference unit cells arranged sequentially to form a reference ring, and configured to generate a second output signal having a second oscillation period, each reference unit cell comprising components configured such that the second oscillation period provides an indication of a propagation delay through the pulse generation circuitry of the main unit cells of the main ring during the first oscillation period; and calculation circuitry configured to determine the clock node to output node delay of the flip-flop from the first oscillation period and the second oscillation period.