Patent ID: 9547767
Date: 2017-01-17
CPC Classifications: G06F,H04L

Claim:
1. An apparatus for protecting a basic input/output system (BIOS) in a computing system, the apparatus comprising: a BIOS read only memory (ROM), comprising: an event detector, configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, wherein said event comprises one or more occurrences of a change in processor speed; and a tamper detector, operatively coupled to said BIOS ROM and said event detector, configured to access said BIOS contents and said encrypted message digest upon assertion of said BIOS check interrupt, and configured to direct a microprocessor to generate a second message digest corresponding to said BIOS contents and a decrypted message digest corresponding to said encrypted message digest using said symmetric key algorithm and said key, and configured to compare said second message digest with said decrypted message digest, and configured to preclude said operation of said microprocessor if said second message digest and said decrypted message digest are not equal; wherein said microprocessor comprises a dedicated crypto/hash unit disposed within execution logic, and wherein said crypto/hash unit generates said second message digest and said decrypted message digest, and wherein said key is exclusively accessed by said crypto/hash unit; and wherein said microprocessor further comprises a random number generator disposed within said execution logic, and wherein said random number generator generates a random number at completion of a current BIOS check, which is employed by said event detector to randomly set a number of occurrences of said event that are to occur before a following BIOS check.