Patent ID: 9548281
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate having active devices thereon; a first post-passivation interconnect over the active devices, the semiconductor substrate having a first direction of coefficient of thermal expansion mismatch and a first quadrant, wherein the first post-passivation interconnect comprises: a second post-passivation interconnect over the active devices, wherein the second post-passivation interconnect comprises: a post-passivation layer over the first post-passivation interconnect and the second post-passivation interconnect; a first opening through the post-passivation layer directly over the first landing pad, the first opening having a first dimension and a second dimension, the second dimension being less than the first dimension, wherein the first dimension and the second dimension are both in a plane parallel with a major surface of the semiconductor substrate, wherein the first dimension is aligned perpendicular to the first direction of coefficient of thermal expansion mismatch, wherein in a plan view the first landing pad extends beyond the first opening in a third direction a first distance and extends beyond the first opening in a fourth direction opposite the third direction a second distance, wherein the third direction and the fourth direction are perpendicular to a length of the first post-passivation interconnect and parallel to a width of the first post-passivation interconnect in the plan view, wherein in plan view the first landing pad extends beyond the first opening in a fifth direction a third distance and extends beyond the first opening in a sixth direction opposite the fifth direction a fourth distance, wherein the fifth direction and sixth direction are parallel to the length of the first post-passivation interconnect and perpendicular to the width of the first post-passivation interconnect in plan view, wherein the third direction and the fourth direction are perpendicular to the second dimension of the first opening, wherein a first sum of the third distance, fourth distance, and second dimension is greater than a second sum of the first distance, second distance, and first dimension; and a second opening through the post-passivation layer directly over the second landing pad, wherein the first opening and the second opening are both located in the first quadrant, the second opening having a third dimension and a fourth dimension, wherein the fourth dimension is less than the third dimension, wherein the third dimension and the fourth dimension are both in a plane parallel with the major surface of the semiconductor substrate, wherein the third dimension is not parallel with the first dimension, wherein the third dimension is aligned perpendicular to a second direction of coefficient of thermal expansion mismatch different from the first direction of coefficient of thermal expansion mismatch, wherein the first opening is filled with a first material.