Patent ID: 9595610
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A field effect transistor, comprising: a semiconductor substrate; an active pattern protruding from the semiconductor substrate; a buffer pattern interposed between the active pattern and the semiconductor substrate; a gate electrode crossing and partially covering top and side surfaces of the active pattern; a gate insulating layer interposed between the gate electrode and the active pattern; and source and drain patterns spaced apart from the buffer pattern, each of the source and drain patterns comprising an epitaxial layer and an insertion portion inserted into the active pattern at a corresponding one of both sides of the gate electrode, wherein the active pattern has a lattice constant different from that of the buffer pattern, so that the active pattern is strained by the buffer pattern, wherein the source and drain patterns have a lattice constant different from that of the active pattern, wherein the active pattern is in contact with the buffer pattern, and wherein the insertion portion of the source and drain patterns has a thickness ranging from about ⅓ to about ⅔ the thickness of the active pattern.