Patent ID: 9703361
Date: 2017-07-11
CPC Classifications: G06F,Y02D

Claim:
1. A memory control apparatus, comprising: a deciding unit configured to decide, among a first main storage apparatus and a second main storage apparatus, that the second main storage apparatus is capable of being suspended, wherein the first main storage apparatus has a first power consumption and the second main storage apparatus has a second power consumption higher than the first power consumption of the first main storage apparatus, wherein the first main storage apparatus and the second main storage apparatus are memory devices of a plurality of Central Processing Unit (CPU) cores of same performance; a power managing unit configured to suppress power supplied to the second main storage apparatus and a CPU core with smallest usage amount of the first main storage apparatus among the plurality of CPU cores of same performance, based on the deciding unit deciding that the second main storage apparatus is capable of being suspended; and a foreseeing unit configured to write moved data in the first main storage apparatus based on the power supplied to the second main storage apparatus being stopped and data written in the second main storage apparatus being moved.