Patent ID: 9570551
Date: 2017-02-14
CPC Classifications: B82Y,H01L

Claim:
1. A method of forming a semiconductor structure, said method comprising: providing an insulator structure located on a surface of a semiconductor material and containing a first end portion having a non-recessed surface, a middle portion having a recessed surface and a second end portion having said non-recessed surface, wherein a patterned structure comprising alternating layers of dielectric material nanowire pillar portions and sacrificial material nanowire portions, and capped with a hard mask material nanowire portion, is present on each of said first and second end portions of said insulator structure; forming a barrier material extending upwards from a portion of said recessed surface of said middle portion of said insulator structure; removing each sacrificial material nanowire portion from said patterned structure to provide a void; forming a III-V or germanium semiconductor nanowire in each of said voids; epitaxially growing a source/drain semiconductor material structure from exposed sidewalls of each of said III-V or germanium semiconductor nanowires; removing each hard mask material nanowire portion and each dielectric material nanowire pillar portion to provide a gate cavity; and forming a functional gate structure surrounding a portion of each of said III-V or germanium semiconductor nanowires in each gate cavity.