Patent ID: 9720833
Date: 2017-08-01
CPC Classifications: G06F

Claim:
1. A computer implemented method for providing cache coherency in a processor system comprising a first plurality of nodes, each node comprising a respective number of central processor (CP) clusters, each CP cluster comprising a respective third plurality of processors and a respective cache system, the processor system configured to perform a multi-tiered cache coherency protocol, the multi-tiered cache coherency protocol consisting of any one of local cache coherency operations within a node and global cache coherency operations between nodes, each node further comprises a storage control (SC) function, the SC function comprising an all-inclusive directory and a fabric control interface (FCI) function, the all-inclusive directory having an indication of all valid cache lines of a respective node, wherein cache coherency operations consist of any one of loading the cache line and updating, by one or more nodes of the processor system, coherency state of the cache line, the computer implemented method comprising: based on receiving a coherency request, from a selected processor, for access to a cache line by a selected processor of a selected node, the selected processor not having the requested access to the cache line in the selected processor's private cache, determining which multi-tiered cache coherency operations to perform the determining comprising: based on determining that the coherency request can be resolved by selected node alone, performing a) and b) comprising: a) performing local cache coherency operations for the cache line only at the selected node; and b) suppressing global cache coherency operation for the cache line from the selected node to all other nodes; and based on determining that the coherency request can not be resolved by the selected node alone, performing c) and d) comprising: c) performing global cache coherency operations from the selected node for the cache line by broadcasting the coherency request to other nodes; and d) based on determining at another node that the broadcast coherency request is for a cache line that is not valid in any cache of the another node, suppressing, by the another node, a local cache coherency operation at the another node for the cache line; and at each node of the plurality of nodes, designating a respective CP cluster as a local intervention master (LIM) for cache lines of the node, the LIM being a local point-of-coherency for cache lines of the respective node; designating a node of the plurality of nodes as the global intervention master (GIM), the GIM being a global point-of-coherency for cache lines for all nodes of the processor system; based on a processor storage request, by a first processor at a selected node, for specified access to a first cache line not available for the specified access in the first processor's local cache, broadcasting the processor storage request to all CP clusters of the selected node; based on the SC function of the selected node determining the requested cache line is held in a cache of the selected node, performing only a local cache coherency operation at the selected node while suppressing any global cache coherency operation to a second node, the only a local cache coherency operation consisting of aa), bb) and cc): aa) updating local coherency state of the requested cache line by the selected node; bb) providing the specified access to the requested cache line in the first processor's local cache; and cc) suppressing, by the selected node, global cache coherency operation of the requested cache line to other nodes; and based on the SC function of the selected node determining that the requested cache line is not held in a cache of the selected node, performing a global cache coherency operation consisting of dd), ee) and ff): dd) broadcasting the processor storage request by the selected node to other nodes of the processor system; ee) based on a first SC function of a first node of the processor system determining the requested cache line is held in a cache of the first node, providing the requested cache line access, by the first node, to the first processor's local cache; and ff) based on a second SC function of a second node of the processor system determining the requested cache line is not held in a cache of the second node, suppressing local cache coherency operations at the second node.