Patent ID: 9548100
Date: 2017-01-17
CPC Classifications: G11C

Claim:
1. A semiconductor memory apparatus comprising: a refresh mode selection circuit configured to generate a first refresh mode signal and a second refresh mode signal in response to an external command and a refresh control signal; a first refresh mode control circuit configured to receive a bank address and generate a first row address increase signal in response to the bank address and the first refresh mode signal; a second refresh mode control circuit configured to generate a second row address increase signal in response to the second refresh mode signal; and a row address generation circuit configured to generate a row address in response to the first and second row address increase signals, wherein the first refresh mode control circuit enables the first row address increase signal after all preset banks to be designated by the bank addresses are activated, when the first refresh mode signal is enabled, wherein the bank address comes from a memory controller and is generated randomly by the memory controller.