Patent ID: 9608735
Date: 2017-03-28
CPC Classifications: H04B,H04J,H04L

Claim:
1. A BCR-MIMO equalization system optimized for baud rate clock recovery in coherent symbol-spaced DP-QPSK Metro systems, comprising: a) a first filter connected to the X polarization path, for receiving the sampled signal from the X polarization path and filtering out a first portion of the X polarization sampled signal; b) a second filter connected to the Y polarization path, for receiving the sampled signal from the Y polarization path and filtering out a second portion of the Y polarization sampled signal; c) a delay element in said X polarization path, for delaying the sampled signal in the X polarization path to have timing alignment with said second portion; d) a delay element in said Y polarization path, for delaying the sampled signal in the Y polarization path to have timing alignment with said first portion; e) a first adder in said X polarization path for adding said second portion to the delayed signal in the X polarization path; f) a second adder in said Y polarization path for adding said first portion to the delayed signal in the Y polarization path; g) a first Timing Error Detection (TED) unit, connected to the output of said first adder, for signal timing estimation and timing synchronization of the signal in the X polarization path; h) a second Timing Error Detection (TED) unit, connected to the output of said second adder, for signal timing estimation and timing synchronization of the signal in the Y polarization path; i) a third filter connected to the output of said first adder, for reconstructing the signal received in said X polarization path; j) a fourth filter connected to the output of said second adder, for reconstructing the signal received in said Y polarization path; and k) an error correction and adaptation unit, for adapting the taps of said filters to minimize the clock timing error in each path.