Patent ID: 9720611
Date: 2017-08-01
CPC Classifications: G06F,G11C

Claim:
1. A memory device, comprising: an array of memory elements comprising discrete re-writable non-volatile two-terminal resistive memory elements disposed between word lines and subsets of bit lines; an access signal generator configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a discrete re-writable nonvolatile two-terminal resistive memory element associated with a word line and a first one of the subsets of bit lines; and a tracking signal generator configured to track a modified magnitude of the signal at a distance from an access signal generator and to apply a tracking signal to other discrete re-writable non-volatile two-terminal resistive memory elements associated with others of the subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.