Patent ID: 9646840
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate containing a front-end device, the front-end device comprising a first dummy gate in a first type metal gate transistor region, a second dummy gate in a second type metal gate transistor region, and a polysilicon gate in a polysilicon gate transistor region, wherein the first dummy gate, the second dummy gate, and the polysilicon gate are formed in a same process and have a same height; forming an interlayer dielectric layer on the semiconductor substrate; removing a portion of the first dummy gate, a portion of the second dummy gate, and a portion of the polysilicon gate so that an upper surface of remaining portions of the first dummy gate, the second dummy gate, and the polysilicon gate is below an upper surface of the interlayer dielectric layer; forming a protective layer on the remaining portions of the first dummy gate, the second dummy gate, the polysilicon gate and the interlayer dielectric layer; removing by etching a portion of the protective layer disposed on the first type metal gate transistor region and removing the remaining portion of the first dummy gate; forming a first work function metal layer in a location of the removed first dummy gate and over a remaining portion of the protective layer disposed on the second dummy gate and the polysilicon gate; forming a metal gate layer on the first work function metal layer; performing a chemical mechanical polishing (CMP) process to remove a portion of the metal gate layer and a portion of the first work function metal layer that are higher than the protective layer, wherein the CMP process comprises a slurry having a removal rate of the protective layer lower than a removal rate of the metal gate layer.