Patent ID: 9634665
Date: 2017-04-25
CPC Classifications: H03K

Claim:
1. An integrated circuit comprising: a first level shifter configured to receive a first input signal and a first power supply signal, the first level shifter configured to output a first output signal; a first inverter configured to receive the first output signal from the first level shifter, the first inverter configured to output a first inverter signal; a second level shifter configured to receive a second input signal and a second power supply signal, the second level shifter configured to output a second output signal, wherein a voltage level of the second power supply signal is different from a voltage level of the first power supply signal; a second inverter configured to receive the second output signal from the second level shifter, the second inverter configured to output a second inverter signal; and an output buffer configured to receive the first inverter signal and the second inverter signal, the output buffer configured to output a buffer output signal.