Patent ID: 9691753
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a P-type semiconductor substrate; an N-well and a P-well disposed adjacent to each other and extending along a first direction within the P-type semiconductor substrate; a first N+ doped region and a first P+ doped region extending along the first direction within the N-well and spaced away from each other along a second direction perpendicular to the first direction; a second N+ doped region and a second P+ doped region extending along the first direction within the P-well and spaced away from each other along the second direction; and a plurality of third N+ doped regions and a plurality of P+ doped regions alternatively disposed in a junction region formed between the N-well and P-well and extending along the first direction, the third N+ doped regions and the third P+ doped regions being separated from the adjacent first P+ doped region and second N+ doped region, wherein the third N+ doped regions and the third P+ doped regions form a Zener diode.