Patent ID: 9747967
Date: 2017-08-29
CPC Classifications: G11C

Claim:
1. An apparatus comprising: a memory configured to store data at physical memory addresses and to read data stored at physical memory addresses, the memory comprising: wherein said MRAM bitcells are spin transfer torque (STT) random access memory (RAM) bitcells, said control circuitry is configured to direct spin-polarized current through the ferromagnetic device of bitcells of the first subarray to change the state of bitcells of the first subarray in the first state to the second state, so that ferromagnetic devices of bitcells of the first subarray have the polarization exhibited by a bitcell in the second state; said control circuitry is further configured to direct spin-polarized current through the ferromagnetic device of first selected bitcells of the first subarray to write data into those first selected bitcells of the first subarray by changing the first selected bitcells of the first subarray from the second state back to the first state so that each first selected bitcell changed back to the first state represents one of a logical one and a logical zero of the data, and wherein said control circuitry is further configured to maintain a state of second selected bitcells of the first subarray in the second state so that each second selected bitcell maintained in the second state represents the other of a logical one and a logical zero of the data; and wherein said control circuitry is further configured to: