Patent ID: 9685953
Date: 2017-06-20
CPC Classifications: H03K

Claim:
1. A logic circuit, comprising: an asynchronous logic circuit having a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals; a synchronous logic circuit having a plurality of synchronous inputs corresponding to said plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal, wherein said synchronous logic circuit provides said clock signal as a periodic signal but prolongs a predetermined state of said clock signal while said stretch signal is active; and an asynchronous interface coupled between said asynchronous logic circuit and said synchronous logic circuit, for detecting whether metastability could occur when latching any of said plurality of said asynchronous outputs of said asynchronous logic circuit using said clock signal, and activating said stretch signal while said metastability could occur.