Patent ID: 9548131
Date: 2017-01-17
CPC Classifications: G11C

Claim:
1. A circuit for reading data from one-time programmable memory cells, each cell connected to a program word line, a read word line and a bit line, the circuit comprising: a first bias circuit and a second bias circuit, each coupled between a first higher potential and a second lower potential for providing first and second mirrored reference currents between the first higher potential and the second lower potential, the first bias circuit being coupled to a reference terminal of a differential sense amplifier and the second bias circuit being coupled to a data terminal of the differential sense amplifier, the first and second bias circuits equilibrating the differential sense amplifier in response to a control signal having a first logic state; a third bias circuit coupled between the first higher potential and the program word line for providing a limited current to the program word line; and a read word line driver circuit coupled to the read word line, and coupled to receive the control signal, whereby when the control signal is in a logic state opposite the first logic state, the memory cell is coupled to the data terminal of the differential sense amplifier and current through the memory cell is limited by the third bias circuit.