Patent ID: 9570450
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method comprising: forming a first opening in a dielectric layer which exposes a source drain region of an SRAM device and forming a second opening in the dielectric layer which exposes a source drain region of a logic device; forming a third opening in the dielectric layer which exposes a gate of the SRAM device and forming a fourth opening in the dielectric layer which exposes a gate of the logic device; forming a first sidewall spacer in the third opening and forming a second sidewall spacer in the fourth opening; recessing a portion of the first sidewall spacer in the third opening without recessing the second sidewall spacer in the fourth opening; forming a strapped contact in the first and third openings, wherein the strapped contact creates an electrical connection between the source drain region of the SRAM device and the gate of the SRAM device, wherein the electrical connection is directly above a remaining portion of the first sidewall spacer in the third opening; and forming contacts in the second and fourth openings, wherein the second sidewall spacer in the fourth opening electrically isolates the contact of the second opening from the contact of the fourth opening, wherein recessing a portion of the first sidewall spacer in the third opening without recessing the second sidewall spacer in the fourth opening further comprises deposition of a hard mask in the region of the logic device, recessing a portion of the first sidewall spacer in the third opening, and removal of the hard mask.