Patent ID: 9684743
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A non-transitory computer readable storage medium storing instructions, the instructions when executed by one or more processors cause the one or more processors to: receive, from an emulator, a plurality of interface signals, the emulator including a plurality of field-programmable gate arrays (FPGAs), the plurality of interface signals generated by tracing interfaces from the plurality of FPGAs during a first emulation of a design under test (DUT); after the first emulation of the DUT, transmit to the emulator instructions to run a second emulation of at least a portion of the DUT using a subset of FPGAs from the plurality of FPGAs and one or more interface signals from the plurality of interface signals; and receive from the emulator traced signals traced during the second emulation by running of the subset of FPGAs based on the one or more interface signals from the plurality of interface signals.