Patent ID: 9612648
Date: 2017-04-04
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A memory channel interleaving method with selective power or performance optimization, the method comprising: configuring a memory address map for at least a first memory device and a second memory device, the first memory device associated with a first memory controller and a first memory channel, the second memory device associated with a second memory controller and a second memory channel, wherein each of the first and second memory devices comprises a portion of an interleaved region and a portion of a linear region, the interleaved region comprising an interleaved address space for relatively higher performance use cases and the linear region comprising a linear address space for relatively lower power use cases; receiving, at a memory channel interleaver, memory requests from one or more clients, the memory requests comprising a preference for power savings or performance; and assigning, by the memory channel interleaver, the memory requests comprising a preference for power savings to the linear region and the memory requests comprising a preference for performance to the interleaved region, wherein assigning the memory requests comprising a preference for power savings to the linear region comprises instructing the first memory controller to write to a first address range corresponding to the portion of the linear region within the first memory device and instructing the second memory controller to transition the second memory device into a power saving mode.