Patent ID: 9722836
Date: 2017-08-01
CPC Classifications: H03M,H04L

Claim:
1. A data processing apparatus configured to map symbols received from sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream and configured to recover an estimate of source data, the data processing apparatus, comprising: a de-interleaver configured to read into a memory data symbols from the OFDM sub-carrier signals, and to read out of the memory the data symbols into the output symbol stream to effect the mapping, the read out being in a different order than the read in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals; an address generator configured to generate the set of addresses, an address being generated for each of the received data symbols to indicate the OFDM sub-carrier signal from which the received data symbol is to be mapped into the output symbol stream, the address generator including a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, and an address check circuit configured to re-generate an address when a generated address exceeds a predetermined maximum valid address; and circuitry configured to recover the estimate of the source data from the output symbol stream, wherein the predetermined maximum valid address is approximately eight thousand, and the linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R′