Patent ID: 9722494
Date: 2017-08-01
CPC Classifications: H02M,Y02B

Claim:
1. A method, comprising: delaying a first gate drive signal of a first boost converter by half a cycle length to produce a delayed signal; receiving a zero crossing detection (ZCD) signal of a second boost converter, the ZCD signal, when activated, indicating that one or more zero current conditions of the second boost converter are met; determining whether to operate in a first mode or a second mode based on a timing of activation of both the ZCD signal and the delayed signal; operating in the first mode if the ZCD signal is activated prior to activation of the delayed signal, operating in the first mode including activating a second gate drive signal of the second boost converter upon activation the delayed signal and activating the first gate drive signal upon activation of a ZCD signal of the first boost converter thereby maintaining the first boost converter as a master converter and the second boost converter as a slave converter; operating in the second mode if the delayed signal is activated prior to activation of the ZCD signal, operating in the second mode including activating the second gate drive signal upon activation of the ZCD signal of the second boost converter and activating the first gate drive signal half a cycle length after activation of the second gate drive signal thereby making the second boost converter the master converter and the first boost converter the slave converter; and adjusting an on time of the first boost converter or the second boost converter based at least in part on a time difference between activation of the ZCD signal of the second boost converter and the delayed signal.