Patent ID: 9634015
Date: 2017-04-25
CPC Classifications: G11C,H01L

Claim:
1. An antifuse-type one time programming memory cell, comprising: a well region; a first doped region, a second doped region, a third doped region and a fourth doped region formed in a surface of the well region, wherein the second doped region is completely separated from the third doped region by the well region; a gate oxide layer covering the surface of the well region; a first gate formed on the gate oxide layer and spanned over the first doped region and the second doped region, wherein the first gate is connected with a word line; a second gate formed on the gate oxide layer and spanned over the third doped region and the fourth doped region, wherein the second gate is connected with the word line; a third gate formed on the gate oxide layer and spanned over the second doped region and the third doped region, wherein the third gate is connected with an antifuse control line; and a first metal layer connected with the first doped region through a first via and connected with the fourth doped region through a second via, wherein the first metal layer is a bit line.