Patent ID: 9595091
Date: 2017-03-14
CPC Classifications: G06T

Claim:
1. A method for classification, comprising: receiving, by a processing device, a three-dimensional (3D) map of an area of a semiconductor wafer containing a location of interest; generating a 3D shape corresponding to the location of interest based on a fitting of the 3D shape using a polynomial equation to the location of interest, and wherein the 3D shape that is fitted using the polynomial equation expresses a plane component that is used to measure a slope of a topographical surface of the 3D shape in a first direction and another slope of the topographical surface of the 3D shape in a second direction; computing, by the processing device, a value for an attribute of the location of interest based on the topographical surface of the 3D shape that is fitted to the location of interest; and classifying a defect corresponding to the location of interest on the semiconductor wafer based on the value that is computed based on the topographical surface of the 3D shape that is fitted to the location of interest.