Patent ID: 9537053
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of manufacturing a III nitride semiconductor device, comprising the steps of: a step of forming a semiconductor laminate obtained by sequentially stacking a first conductivity type III nitride semiconductor layer, an active layer, and a second conductivity type III nitride semiconductor layer on a growth substrate with a lift-off layer provided therebetween; a step of partly removing the semiconductor laminate to form a plurality of grooves in a grid pattern such that the growth substrate is partly exposed at the bottom of the grooves, thereby forming a plurality of semiconductor structures having a nearly quadrangular transverse cross-sectional shape; a step of filling up alternate lines of the plurality of grooves in one direction with a filler; a step of forming a support for integrally supporting the plurality of semiconductor structures by plating; a step of forming through-holes in the support, the through-holes communicating with the filler; a step of forming gaps by removing the filler; a step of supplying an etchant to the gaps from the through-holes, thereby etching the lift-off layer from only one side of each of the semiconductor structures to remove the lift-off layer; a step of forming first and second electrodes electrically connected to the first and second conductivity-type III nitride semiconductor layers, respectively; and a singulation step for cutting the support along the plurality of grooves, wherein in the singulation step, the support is cut along at least part of the grooves other than the grooves provided with the filler, thereby manufacturing III nitride semiconductor devices in which the cut supports support respective m rows and n columns of the semiconductor structures (where m is a natural number, and n is an even number equal to or more than 2).