Patent ID: 9536941
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor layer having first and second opposing main surfaces; a first boundary trench and a second boundary trench, each of the first and second boundary trenches extending from the first main surface of the semiconductor layer; a gate pad contact disposed proximate the first main surface and defining a length direction and a width direction orthogonal to the length direction, the length and width directions being parallel to the first main surface; a plurality of pad trenches each extending from the first main surface and being disposed between the first and second boundary trenches in a direction parallel to one of the length direction or width direction defined by the gate pad contact, adjacent ones of the first boundary trench, the second boundary trench, and the plurality of pad trenches in the direction parallel to the length or width direction defined by the gate pad being separated by about 45 micrometers to about 60 micrometers; a plurality of first columns of a first conductivity type each extending along a respective sidewall of one of the first boundary trench, the second boundary trench, and the plurality of pad trenches; a plurality of second columns of a second conductivity type each disposed between and adjacent to respective ones of the plurality of first columns located between adjacent ones of the first boundary trench, the second boundary trench, and the plurality of pad trenches, the second conductivity type being opposite to the first conductivity type; a plurality of channels of the first conductivity type each extending along the first main surface from the sidewall of a respective one of the first boundary trench, the second boundary trench, and the plurality of pad trenches; a plurality of doped regions of the first conductivity type each extending from the first main surface and being disposed between adjacent ones of the first boundary trench, the second boundary trench, and the plurality of pad trenches; a plurality of pad regions each disposed proximate respective ones of the plurality of doped regions and being separated therefrom by a layer of oxide formed on the first main surface, each of the plurality of gate pad regions being electrically connected to the gate pad; and a first MOSFET cell at least partially formed in the semiconductor layer proximate the first boundary trench and a second MOSFET cell at least partially formed in the semiconductor layer proximate the second boundary trench.