Patent ID: 9659910
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor package, the method comprising: disposing a first semiconductor chip and a plurality of first bumps on a first interconnection structure layer; forming a first mold layer covering the first bumps and the first semiconductor chip; exposing top portions of the first bumps by selectively removing some portions of the first mold layer; disposing second bumps connected to the exposed first bumps; forming a second mold layer covering the second bumps; exposing top portions of the second bumps by recessing the second mold layer; and laminating a second semiconductor chip electrically connected to the second bumps, wherein removing the portion of the first mold layer comprises forming a step shape at the first mold layer by leaving a remaining region of the first mold layer which covers the first semiconductor chip, and by selectively grinding a region of the first mold layer which covers the first bumps.