Patent ID: 9711515
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor memory device, comprising: alternately stacking a plurality of first inter-layer insulating layers and first layers above a substrate; forming a first opening that penetrates a plurality of the first inter-layer insulating layers and first layers; forming a gate insulating layer and a semiconductor layer on an inner wall of the first opening; forming a second opening that penetrates a plurality of the first inter-layer insulating layers and first layers; forming a second inter-layer insulating layer on a bottom surface and an inner wall of the second opening; removing a portion covering the bottom surface of the second opening, of the second inter-layer insulating layer; forming a first silicide layer on the bottom surface of the second opening; forming a barrier metal layer on an upper surface of the first silicide layer and on a side surface of the second inter-layer insulating layer; forming a silicon layer on an upper surface and side surface of the barrier metal layer such that a crevice is formed in an upper surface of the silicon layer along the second opening; removing part of the silicon layer; and siliciding the silicon layer via the crevice to form a second silicide layer.