Patent ID: 9654115
Date: 2017-05-16
CPC Classifications: H03L,H04L

Claim:
1. A phase-locked loop circuit, comprising: a first voltage-current converter; a second voltage-current converter; a current-controlled oscillator; a frequency divider; a phase frequency detector configured to: a charge pump coupled to the phase frequency detector and configured to generate a first voltage signal according to the first error signal that is output by the phase frequency detector; a loop low-pass filter, comprising a first filter, a second filter, a third node, and a fourth node, a switch (S a mode controller coupled to the loop low-pass filter and configured to control the S wherein the first voltage-current converter is coupled to the loop low-pass filter and configured to: wherein the second voltage-current converter is coupled to the loop low-pass filter and configured to: wherein the current-controlled oscillator is configured to generate, according to received current signals, a phase-locked loop output signal whose frequency is a target frequency, wherein one end of the frequency divider is coupled to the current-controlled oscillator and the other end is coupled to the phase frequency detector, and wherein the frequency divider is configured to: