Patent ID: 9613981
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of manufacturing a vertical channel-type 3D semiconductor memory device, comprising: depositing alternating layers of at least one insulating layer and at least one electrode material layer on a substrate to form a multi-layer film; etching the multi-layer film to the substrate to form a plurality of through-holes, each of which defines a respective channel region; depositing a barrier layer, a storage layer, and a tunnel layer in sequence on an inner wall of a respective one of the plurality of through-holes to form a plurality of gate stacks; depositing and incompletely filling a channel material on a surface of the tunnel layer of a respective one of the plurality of gate stacks to form a plurality of hollow channels; forming a plurality of drains in respective contact hole regions for bit-line connection in respective top portions of the plurality of hollow channels; and forming a plurality of sources in respective contact regions between the plurality of through-holes and the substrate in respective bottom portions of the plurality of hollow channels.