Patent ID: 9693455
Date: 2017-06-27
CPC Classifications: H01L,H05K

Claim:
1. A method of manufacture of an integrated circuit packaging system comprising: forming a first metal layer directly on a copper film, including a horizontal planar top surface, of a carrier; forming an insulation layer directly on and over the first metal layer, the insulation layer having an insulation bottom surface coplanar with a metal layer bottom surface of the first metal layer, the metal layer bottom surface on the horizontal planar top surface; forming a via hole through the insulation layer for exposing the first metal layer; forming a conductive via and a second metal layer on the insulation layer, the conductive via within the via hole and directly on the first metal layer; removing the carrier for exposing the copper film; forming a post mask having post mask openings for exposing the copper film; forming copper posts having a pitch of between 15-20 micrometers (μm) directly on the side of the copper film opposite the first metal layer and the second metal layer and within the post mask openings; and attaching an interposer on the copper posts with solder pads.