Patent ID: 9679639
Date: 2017-06-13
CPC Classifications: G06F,G11C

Claim:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation or erase operation of the memory cell array; and a control logic configured to control the peripheral circuit such that a first erase control voltage applied to word lines of the memory cell array during a first erase operation of the erase operation and a second erase control voltage applied to the word lines during a second erase operation of the erase operation are different from each other, wherein the peripheral circuit comprises a voltage generator configured to generate a set erase voltage to be applied to a source line of the memory cell array during the first erase operation and normal erase voltages to be applied to the source line during the second erase operation, and wherein the set erase voltage has a longer application time than a first normal erase voltage of the normal erase voltages.