Patent ID: 9711194
Date: 2017-07-18
CPC Classifications: G06F,G11C

Claim:
1. A circuit for controlling the operation of a memory system having different types of memory, the circuit comprising: a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer comprising a block of random access memory (RAM) on a programmable logic device (PLD) coupled to the second memory to compensate for a difference in the first access time and the second access time by buffering data during a predetermined delay; and a circuit for merging output data of the first memory and delayed output data of the second memory to generate ordered output data.