Patent ID: 9575867
Date: 2017-02-21
CPC Classifications: G06F

Claim:
1. A computer system comprising: a memory comprising a definition of an instruction set architecture of a targeted processor; and a processor operably coupled to the memory and configured to perform a method comprising: analyzing the instruction set architecture of the targeted processor to generate an instruction set profile for each instruction of the instruction set architecture; ranking and ordering one or more properties of the instruction set profile for each instruction in the instruction set architecture; selecting one or more instructions for a plurality of instruction sequences based on the ranking and ordering with respect to a desired stressmark type, the desired stressmark type defining a metric representative of functionality of interest of the targeted processor; determining a combination of the instruction sequences for the targeted processor from the instruction set profile that corresponds to the desired stressmark type, wherein the combination of the instruction sequences is selected based on a configuration context of the targeted processor, an instruction sequence length, and the one or more properties defined in the instruction set profile; monitoring performance of the targeted processor with respect to the desired stressmark type while executing each of the instruction sequences; and identifying one of the instruction sequences as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.