Patent ID: 9577508
Date: 2017-02-21
CPC Classifications: G05F,H02M

Claim:
1. A low dropout (LDO) voltage regulator having a supply voltage input and a regulated voltage output, comprising: an error amplifier having an output connected to a first conductor, an N-channel pass transistor having a drain coupled to the supply voltage input, a source coupled to the regulated voltage output, and a gate coupled to the first conductor, the error amplifier having a first input coupled to a reference voltage and a second input coupled via a feedback path to the regulated voltage output, a ripple voltage signal present on the supply voltage input producing a ripple current which tends to flow into an output impedance of the error amplifier and generate a corresponding ripple voltage on the gate of the pass transistor; an N-channel cancellation transistor having a drain coupled to the supply voltage input and a source coupled to the regulated voltage output and having a gate coupled to a second conductor distinct from the first conductor, for producing an AC injection cancellation current which is a predetermined proportion of the ripple current; biasing circuitry coupled between the first conductor and the second conductor for biasing the gate of the N-channel cancellation transistor at a voltage having a predetermined relationship to a voltage on the first conductor; an AC current gain circuit; and circuitry for coupling the second conductor to an input of the AC current gain circuit, the AC current gain circuit having an output coupled to the first conductor and operating to multiply the AC injection cancellation current sufficiently to generate a ripple cancellation current substantially equal to the ripple current in a direction opposite to the ripple current to cancel the ripple current in the first conductor so as to prevent the ripple current from flowing into the output impedance of the error amplifier, wherein the power supply rejection ratio (PSRR) of the LDO regulator is improved.