Patent ID: 9558966
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A package for a semiconductor device, comprising: an integrated circuit die mounting region; a molding material disposed around the integrated circuit die mounting region; an interconnect structure disposed over the molding material and the integrated circuit die mounting region; and a protection pattern disposed over and outside the molding material in a perimeter region of the package around the interconnect structure, wherein the protection pattern comprises a first conductive feature disposed vertically within the package proximate a second conductive feature, wherein the first conductive feature and the second conductive feature inside the protection pattern are electrically isolated from conductive features outside the protection pattern, wherein the first conductive feature comprises a first width, wherein the second conductive feature comprises a second width, the second width being greater than the first width, wherein the first width and the second width are measured orthogonally to the first conductive feature disposed vertically.