Patent ID: 9698211
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A process of forming an integrated circuit, comprising the steps: forming a gate dielectric layer on a substrate; forming a gate polysilicon layer over the substrate and the gate dielectric layer; etching the gate polysilicon layer to form: forming an NSD implant mask over the substrate which: performing an NSD implant operation which implants n-type dopants into the substrate adjacent to the NMOS gate to form NSD layers and into the body region of the resistor layer; forming a PSD implant mask over the substrate which: performing a PSD implant operation which implants p-type dopants into the substrate adjacent to the PMOS gate to form PSD layers and into the body region of the resistor layer; forming metal silicide layers on the head regions of the resistor layer, on the NSD layers, and on the PSD layers; forming a PMD layer over the silicide layers; and forming contacts through the PMD layer, said contacts making electrical connection to the silicide layers on the NSD layers and to the silicide layers on the PSD layers.