Patent ID: 9716017
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor package, the method comprising: forming via holes extending from a first surface of an interposer wafer into a body of the interposer wafer; forming interconnection structures in the via holes and on the first surface of the interposer wafer, each of the interconnection structures including a through electrode portion filling one of the via holes, an external connection portion disposed on the first surface of the interposer wafer, and an extension portion connecting the through electrode portion to the external connection portion; recessing a second surface of the interposer wafer opposite to the external connection portions to expose end portions of the through electrode portions at the recessed second surface; mounting a semiconductor die on the recessed second surface of the interposer wafer to electrically connect die connection portions of the semiconductor die to the end portions of the through electrode portions; forming a protection portion covering the semiconductor die on the recessed second surface of the interposer wafer; and attaching external connection terminals to the external connection portions, wherein the external connection portion is located on the first surface of the interposer wafer to be spaced apart from the through electrode portion by a predetermined distance, and wherein the external connection terminal is spaced apart from the through electrode portion.