Patent ID: 9543305
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A reverse-conducting power semiconductor device with a wafer having a first main side and a second main side, which is arranged parallel to the first main side, the device comprising a plurality of diode cells and a plurality of gate commutated thyristor cells, wherein each gate commutated thyristor cell comprises in the order from the first to the second main side: a cathode electrode; a first cathode layer of a first conductivity type; a base layer of a second conductivity type different from the first conductivity type; a first section of a drift layer of the first conductivity type; a first anode layer of the second conductivity type; and a first anode electrode, wherein each gate commutated thyristor cell further comprises a gate electrode, which is arranged lateral to the first cathode layer and separated from the first cathode layer by the base layer, wherein the first cathode layer of each gate commutated thyristor cell includes at least three cathode layer regions, which are separated from each other by the base layer, wherein in orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped with a length in a direction along a longitudinal axis thereof and a width (w, w′) in a direction vertical to the longitudinal axis, the width (w, w′) of each cathode layer region being less than its length, wherein each diode cell comprises in the order from the first main side to the second main side: a second anode electrode; a second anode layer of the second conductivity type; a second section of the drift layer; and a second cathode layer of the first conductivity type, wherein the device comprises at least one mixed part, in which the second anode layers of the diode cells alternate with the first cathode layers of the gate commutated thyristor cells in a lateral direction so that, in the orthogonal projection onto the plane parallel to the first main side, the first cathode layer of each gate commutated thyristor cell in the mixed part is arranged between a pair of second anode layers of two diode cells neighbouring to the gate commutated thyristor cell on opposite sides of the gate commutated thyristor cell in the lateral direction, wherein the second anode layers are separated from neighbouring base layers by a separation region of the first conductivity type, wherein in the mixed part, in the orthogonal projection onto the plane parallel to the first main side, in each gate commutated thyristor cell, the width (w′) of each one of the two outer cathode layer regions is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that gate commutated thyristor cell.