Patent ID: 9691484
Date: 2017-06-27
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device, comprising: a memory cell unit including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell that are connected in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; a third word line connected to the third memory cell; a fourth word line connected to the fourth memory cell; a driver circuit configured to apply a voltage to the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell; and a first transistor including a first diffused layer and a second diffused layer, wherein the first diffused layer is connected to the first word line, and the second diffused layer is connected to the driver circuit, wherein when data is written into the first memory cell, a first voltage is applied to the first word line, a second voltage is applied to the second word line and the third word line, and a third voltage is applied to the fourth word line, wherein the first voltage is larger than both the second voltage and the third voltage, and the third voltage is larger than the second voltage, wherein the second memory cell and the third memory cell are located between the first memory cell and the fourth memory cell, and wherein the second word line and the third word line are located above a gate electrode of the first transistor.