Patent ID: 9621181
Date: 2017-04-11
CPC Classifications: H03M

Claim:
1. A digital to analog converter (DAC) with output impedance compensation, the DAC comprising: an encoding unit receiving and encoding a plurality of binary-weighted digital inputs to generate a plurality of encoded controlling signals; a current cell array comprising a plurality of conversion units that respectively receive the encoded controlling signals to generate analog output signals; a summing unit receiving the analog output signals from the current cell array and summing the analog output signals to generate an accumulated analog output signal; and a compensation unit providing a nonlinear impedance to compensate an output impedance seen from the current cell array and the summing unit of the DAC; wherein the plurality of binary-weighted digital inputs is capable of expressing an input data range; and an impedance curve of the nonlinear impedance provided by the compensation unit has a highest impedance value corresponding to a lowest input value and a highest input value of the input data range; and a lowest impedance value corresponding to a middle input value of the input data range.