Patent ID: 9628091
Date: 2017-04-18
CPC Classifications: H03D,H03K,H03L,H04L

Claim:
1. A phase detector for use in a CDR (Clock Data Recovery) circuit, wherein the CDR circuit generates a clock signal according to a data signal, comprising: a clock delay circuit, delaying the clock signal so as to generate a first delay clock signal, wherein a delay time of the clock delay circuit is adjustable according to a first control signal and a second control signal; a data delay circuit, delaying the data signal so as to generate a first delay data signal, wherein a delay time of the data delay circuit is adjustable according to the first control signal and the second control signal; a first control circuit, generating the first control signal and the second control signal according to the clock signal and the first delay clock signal; a main D flip-flop, generating a register signal according to the data signal and the clock signal; and a logic circuit, generating an up control signal and a down control signal according to the data signal, the first delay data signal, and the register signal so as to control a charge pump of the CDR circuit.