Patent ID: 9699916
Date: 2017-07-04
CPC Classifications: H05K,Y10T

Claim:
1. A method of manufacturing a wiring substrate, comprising: a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of patterning of the second insulating layer to form electrically insulative dummy portions on the first insulating layer and spaced apart from the wiring layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that at least one opening exposes both at least one connection terminal and at least one dummy portion; wherein an upper end portion of the at least one connection terminal protrudes from the third insulating layer, and a lower end portion of the at least one connection terminal is embedded in the third insulating layer, such that for the at least one connection terminal an upper edge of the at least one connection terminal is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer formed between the at least one connection terminal and an adjacent connection terminal or an adjacent dummy portion, and; wherein an upper end portion of the at least one dummy portion protrudes from the third insulating layer, and a lower end portion of the at least one dummy portion is embedded in the third insulating layer, such that for the at least one dummy portion an upper edge of the at least one dummy portion is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer formed between the at least one dummy portion and an adjacent connection terminal or an adjacent dummy portion.