Patent ID: 9691737
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate including first and second extending input/output pads; a first memory structure on the substrate and including first connecting input/output pads; a second memory structure on the first memory structure and including second connecting input/output pads; and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first connecting input/output pads of the first and second memory structures with the first and second extending input/output pads of the substrate, respectively, wherein the wiring structure includes a first wiring connecting the first connecting input/output pads of the first memory structure and the first extending input/output pad of the substrate and a second wiring connecting the first connecting input/output pads of the second memory structure and the second extending input/output pad of the substrate, and the second wiring is offset relative to the first wiring, wherein the substrate further includes an extending power pad connected to a power supply and an extending ground pad that is grounded, the first memory structure further includes a power pad and a ground pad, the wiring structure further includes a power wiring connecting the power pad and the extending power pad and a ground wiring connecting the ground pad and the extending ground pad, and the power wiring or the ground wiring are disposed between the first and second wirings.