Patent ID: 9552791
Date: 2017-01-24
CPC Classifications: G09G

Claim:
1. A display driving circuit, comprising: first through (2*n)-th buffers, n being an integer equal to or greater than two; a buffer controller configured to circularly select one of the first through (2*n)-th buffers in an order from the first buffer to the (2*n)-th buffer at each of a plurality of first time intervals, and configured to store pixel data received during the first time interval in the selected buffer; first through n-th image processing units, each of the first through n-th image processing units being coupled to two corresponding buffers among the first through (2*n)-th buffers, each of the first through n-th image processing units configured to process the pixel data, which are stored in at least one of their corresponding buffers, during each of n of the first time intervals to generate processed data when the pixel data are stored in the corresponding buffer during the first time interval; and a source driver configured to generate analog signals based on the processed data received from the first through n-th image processing units.