Patent ID: 9728479
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A multi-chip package structure, comprising: a first chip, having a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside of the chip bonding region; a circuit layer, disposed on the first chip, the circuit layer comprising a plurality of insulating layers and at least one metal layer disposed between the insulating layers, the insulating layers having at least one groove, the groove disposed between the first inner pads and the first outer pads, and the groove surrounding the first inner pads; a plurality of first conductive bumps, disposed on the first outer pads; a second chip, flipped on the chip bonding region, and the second chip having a plurality of second pads; a plurality of second conductive bumps, located between the first inner pads and the second pads, and the first inner pads being electrically connected with the second pads through the second conductive bumps, respectively; and an underfill, located between the first chip and the second chip so as to cover the second conductive bumps, wherein the insulating layers of the circuit layer comprise: