Patent ID: 9626265
Date: 2017-04-18
CPC Classifications: G01R,G06F

Claim:
1. A method for improving efficiency of cycle-reproducible debug in a multi-core environment, the method comprising: executing, by one or more computer processors, an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds; determining, by one or more computer processors, a seed from the one or more different seeds that locates a fail-condition; responsive to determining a seed from the one or more different seeds that locates the fail condition, determining, by one or more computer processors, an upper bound and a lower bound of the fail-condition; determining, by one or more computer processors, whether the fail-condition has occurred within a range of cycles executed on each of the one or more cores; responsive to a determination that the fail-condition has occurred within the range of cycles executed by at least one of the one or more cores, determining, by one or more computer processors, a lowest cycle count in the at least one of the one or more cores where the fail-condition has occurred as an upper bound; responsive to a determination that the fail-condition has not occurred within the range of cycles executed by at least one of the one or more cores, resetting, by one or more computer processors, each of the one or more cores with a higher stopping cycle; determining, by one or more computer processors, an exact cycle where the fail-condition occurs; and constructing, by one or more computer processors, a multi-cycle trace for the fail-condition.