Patent ID: 9607938
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A method of manufacture of an integrated circuit packaging system comprising: forming a dielectric core having an embedded pad, another embedded pad, a surface trace between the embedded pad and the another embedded pad, and having core sidewalls, the core sidewalls extending between a core top side of the dielectric core and a pad top surface of the embedded pad, and a portion of the core sidewalls exposed from the embedded pad; forming a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer, the top solder resist layer exposing a mounting region continuously exposing both the embedded pad and the another embedded pad, and the surface trace exposed from the dielectric core within the mounting region; forming a device interconnect on the embedded pad, the device interconnect in contact with the core sidewalls; and mounting an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.