Patent ID: 9640272
Date: 2017-05-02
CPC Classifications: G11C

Claim:
1. A control circuit for a non-volatile semiconductor memory device, adapted to control a clock generator for generating a system clock having a changeable frequency, wherein when a reset command is issued during a period that a read, a program or an erase operation is running on the non-volatile semiconductor memory device, the control circuit changes the frequency of the system clock generated by the clock generator from a first frequency which is for the system clock for a running operation mode to a second frequency that is higher than the first frequency, performs an interrupt process on the non-volatile semiconductor memory device, so as to enter a reset sequence mode from the running operation mode, performs a reset sequence process with the system clock of the second frequency during the reset sequence mode, and when the reset sequence process is finished and the non-volatile semiconductor memory device is returned to a state that is ready to receive an operation command, the control circuit changes the frequency of the system clock generated by the clock generator from the second frequency to the first frequency.