Patent ID: 9684600
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A method of dynamically optimizing memory accesses in a multiprocessor computing system, the method comprising: during execution of a plurality of processes by a plurality of physical processors in the multiprocessor computing system, performing memory reference sampling of memory locations from a shared memory being referenced by the plurality of processes, wherein each of a plurality of sampled memory references collected during memory reference sampling is associated with a latency and a physical location in the shared memory; analyzing the sampled memory references collected during memory reference sampling to identify at least one segment of memory locations in the shared memory associated with at least one sub-optimal latency; dynamically adjusting, during execution of the plurality of processes and based upon the analyzed sampled memory references, a physical processor upon which a first process of the plurality of processes that references memory locations in the at least one identified segment executes, wherein dynamically adjusting the physical processor upon which the first process executes comprises: