Patent ID: 9552964
Date: 2017-01-24
CPC Classifications: H01J,H01L

Claim:
1. A method of semiconductor device fabrication, comprising: receiving an integrated circuit (IC) layout pattern including a plurality of templates, wherein each template includes a portion of the IC layout pattern; determining a pattern density (PD) for each template of the plurality of templates, wherein the determining the PD provides a first range of pattern densities; identifying, from the plurality of templates, a first template having a first layout pattern with a first PD and a second template having a second layout pattern with a second PD less than the first PD; splitting the first template into a plurality of subset templates, wherein each subset template of the plurality of subset templates includes a portion of the first layout pattern; performing a PD uniformity (PDU) optimization to the second template; and performing multiple individual electron beam (e-beam) lithography exposure processes to a semiconductor substrate, using respective ones of the subset templates, thereby patterning the semiconductor substrate.