Patent ID: 9577011
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A fabricating method of a complementary metal oxide semiconductor transistor comprising: forming a first channel layer on a substrate; forming a bottom gate, a first source, and a first drain on the substrate, wherein the first source and the first drain are in contact with the first channel layer, and the first channel layer is formed before the first source and the first drain are formed; forming a gate insulator on the substrate to cover the bottom gate, the first source, and the first drain; forming a second channel layer on the gate insulator, wherein the second channel layer is located above the bottom gate; forming a top gate, a second source, and a second drain on the gate insulator, wherein the top gate is located above the first channel layer, and the second source and the second drain are in contact with the second channel layer; forming a passivation layer, the passivation layer covering the second channel layer, the gate insulator, the second source, the second drain, and the top gate; patterning the passivation layer to form a plurality of first contact holes in the passivation layer and the gate insulator and form a plurality of second contact holes in the passivation layer, wherein the first contact holes expose the first source and the first drain, and the second contact holes expose the second source and the second drain; and forming a plurality of first contact conductors and a plurality of second contact conductors on the passivation layer, wherein the first contact conductors are electrically connected to the first source and the first drain through the first contact holes, and the second contact conductors are electrically connected to the second source and the second drain through the second contact holes.