Patent ID: 9563369
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. A memory controller, configured to: receive memory requests from a plurality of masters via a bus fabric; determine a priority level assigned with each of the plurality of masters; calculate a bandwidth cost of a request based on information about a last issued request, the information about the last issued request being received from a memory device; determine an amount of memory data bus bandwidth consumed by each master per request on a memory data bus; apply a quality of service (QoS) logic to compute a schedule for the memory requests based on a priority class assigned to each master, the bandwidth cost of each request based on the information about the last issued request, and an amount of memory data bus bandwidth consumed by each master per request, the memory data bus bandwidth consumed by each master per request being calculated based on information about a last issued request; and based upon the schedule,