Patent ID: 9563733
Date: 2017-02-07
CPC Classifications: G06F,H01L,Y02P

Claim:
1. A cell circuit of a semiconductor device, comprising: a substrate; a number of linear-shaped diffusion fins defined to extend over the substrate in a first direction so as to extend parallel to each other, each of the number of linear-shaped diffusion fins defined to project upward from the substrate along their extent in the first direction, wherein the number of linear-shaped diffusion fins are positioned on one or more of a plurality of diffusion tracks that are virtual lines of a diffusion fin virtual grate, wherein the plurality of diffusion tracks extend in the first direction over the substrate, wherein the plurality of diffusion tracks are positioned based on a fixed diffusion track pitch, wherein the fixed diffusion track pitch corresponds to an equal spacing between adjacent side-by-side positioned ones of the plurality of diffusion tracks as measured in a second direction perpendicular to the first direction and parallel to the substrate; and a number of gate level structures defined to extend in a conformal manner over one or more of the number of linear-shaped diffusion fins, such that portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins extend in the second direction perpendicular to the first direction, wherein portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins form gate electrodes of a corresponding transistor.