Patent ID: 9584430
Date: 2017-02-28
CPC Classifications: H04L,H04W

Claim:
1. An apparatus comprising: a plurality of interconnected memory cluster units, where each of the plurality of interconnected memory cluster units is associated to a single or more levels of a hierarchical scheduling database and each of the plurality of interconnected memory cluster units is coupled to at least one co-processor; and an interface to a plurality of traffic flow queues, where the interface is used to identify one or more packets associated to a traffic flow queue selected for transmission according to a scheduling algorithm and the interface is configured to signal an eligibility state of each of the traffic flow queues of the plurality of traffic flow queues; where each of the plurality of memory cluster units or a group of the plurality of memory cluster units is coupled to an associated node co-processor configured to process topology mapping information of the hierarchical scheduling database and to process data fields mapping information of nodes of the hierarchical scheduling database.