Patent ID: 9748339
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductor substrate having a first conductive type; a semiconductor layer disposed on the semiconductor substrate, wherein the semiconductor layer has the first conductive type; a first well region disposed in a portion of the semiconductor layer, wherein the first well region has a second conductive type opposite to the first conductive type; a second well region disposed in another portion of the semiconductor layer, wherein the second well region has the second conductive type; a pair of third well regions disposed in a portion of the semiconductor layer at opposite sides of the second well region, wherein the pair of third well regions have the first conductive type, and wherein the first well region and one of the third well regions are separated by the semiconductor layer; a plurality of isolation elements disposed on the semiconductor layer, wherein the plurality of isolation elements are respectively between the third well regions and the first and second well region; a deep well region disposed in a portion of the semiconductor substrate adjacent to the semiconductor layer between the first and second well region, wherein the deep well region has the second conductive type; a first doping region disposed in the first well region, wherein the first doping region has the second conductive type; and second doping regions disposed in the third well regions, wherein the second doping regions have the first conductive type.