Patent ID: 9552928
Date: 2017-01-24
CPC Classifications: H01G

Claim:
1. A method for manufacturing a solid electrolytic capacitor, the method comprising: (a) forming grooves in opposed principal surfaces of a valve-acting metal substrate that includes a porous surface part and a non-porous body part such that bottoms of the grooves are non-porous, partitioning the opposed principal surfaces of the valve-acting metal substrate into a plurality of unit regions at the grooves, and defining a cathode layer formation part in the porous surface part for each unit region; (b) forming a first dielectric layer on surfaces of the cathode layer formation parts of the valve-acting metal substrate and on the grooves between the cathode layer formation parts; (c) sequentially forming a solid electrolyte layer and a cathode extraction layer on a surface of the first dielectric layer formed on the cathode layer formation parts of the valve-acting metal substrate so as to provide a sheet having a plurality of solid electrolytic capacitor elements corresponding to the plurality of unit regions integral with the grooves interposed therebetween; (d) cutting the sheet at the grooves of the valve-acting metal substrate; and (e) forming a second dielectric layer on cut surfaces located around the cathode layer formation parts of the valve-acting metal substrate.