Patent ID: 9691681
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method of making an integrated circuit package that contains therein a semiconductor die having a silicon side and one or more electrical connections to an electronic circuit within the semiconductor die, the method comprising: encapsulating the semiconductor die and its electrical connections in non-electrically conductive, encapsulation material; laser drilling the encapsulation material to expose one of the electrical connections within the integrated circuit package, thereby creating a via opening in an external surface of the encapsulation material to the electrical connection; electroplating or sputtering over the via opening in the encapsulation material to create a conductive routing layer from the external surface of the encapsulation material to the electrical connection; attaching a first surface of a thermally-conductive heat spreader in a thermally-conductive manner to the silicon side of the semiconductor die before the encapsulating; during the encapsulating, also encapsulating the attached heat spreader in the non-electrically conductive, encapsulation material, except for a second surface of the heat spreader, and electroplating the first surface of the heat spreader to the silicon side of the semiconductor die.