Patent ID: 9742355
Date: 2017-08-22
CPC Classifications: H03D,H03F,H03K

Claim:
1. A buffer circuit comprising: a first differential amplifier configured to generate a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal; a second differential amplifier configured to generate a first signal based on the positive differential signal and the negative differential signal; a third differential amplifier configured to generate a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal; and a mixer configured to output a signal, generated by mixing the first signal and the second signal, as an output signal, wherein the buffer circuit maintains a difference between a duty of the output signal and a duty of the input signal within a certain range by cancelling duty variations of the positive differential signal and the negative differential signal through the mixing when a level of the reference voltage signal is varied.