Patent ID: 9712172
Date: 2017-07-18
CPC Classifications: G06N,H03K

Claim:
1. A device comprising: a first clock terminal for receiving a first clock having a first phase; a second clock terminal for receiving a second clock having a second phase different from the first phase; and an array of superconducting logic cells, wherein each of the superconducting logic cells is configured to receive at least one input and provide at least one output, and wherein each of the superconducting logic cells comprises at least one Josephson junction configured to change its state based on at least one of: (1) a first biasing condition caused by the first phase of the first clock or (2) a second biasing condition caused by the second phase of the second clock, and wherein each of the superconducting logic cells is arranged in a pre-determined location in the array, and wherein a first set of the superconducting logic cells in the array of the superconducting logic cells is configured to process at least a first set of inputs during the first phase of the first clock at least in response to the first biasing condition to generate a first set of outputs and a second subset of the superconducting logic cells in the array of superconducting logic cells is configured to process at least a second set of inputs during the second phase of the second clock at least in response to the second biasing condition, and wherein the array of the superconducting cells is configured to perform at least one operation by processing at least one of the first set of inputs and the second set of inputs, and wherein the at least one operation is performed based on a connection arrangement of the array of superconducting logic cells, wherein with respect to connections with other superconducting logic cells in the array of the superconducting logic cells, each of the superconducting logic cells is connected only to adjacent superconducting logic cells in the array of the superconducting logic cells, and wherein each of the superconducting logic cells comprises a gate selected from a group consisting of an AND gate, an OR gate, and an AanB gate.