Patent ID: 9691462
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. A method of operating a magnetoresistive random access memory (MRAM) bit cell in a circuit comprising a first transistor pair having a first node therebetween and a second transistor pair having a second node therebetween, the method comprising: equalizing the first node and the second node by coupling the first node to the second node and to gates of the second transistor pair; developing a differential voltage between the first node and the second node by decoupling the first node from the second node, the gates of the second transistor pair, or both; pre-amplifying the differential voltage to generate a pre-amplified differential voltage without offset voltage by coupling the first node to the gates of the second transistor pair; and latching the pre-amplified differential voltage by decoupling the first node from the MRAM bit cell and decoupling the second node from a reference bit cell.