Patent ID: 9589803
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A field effect transistor comprising: a substrate; a gate electrode over the substrate comprising a first top surface and a sidewall, wherein the gate electrode has a first thickness; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and a portion of the S/D region; a gate dielectric layer between the substrate and the gate electrode; and a contact etch stop layer (CESL) adjacent to the spacer, wherein, the CESL over the S/D region has a second thickness, and a ratio of the first thickness to the second thickness ranges from about 1.1 to about 1.5, wherein an entire top surface of the CESL over the S/D region and over an isolation region adjoining the field effect transistor is substantially co-planar with the first top surface of the gate electrode.