Patent ID: 9575122
Date: 2017-02-21
CPC Classifications: G01R

Claim:
1. Interface circuitry comprising: (a) a control bus input of m leads, a write strobe input lead, and a scan clock input lead; (b) write strobe sequencer circuitry having a write strobe input coupled to the write strobe input lead, a clock input coupled to the scan clock input lead, a first write strobe output, and a second write strobe output; (c) a first register having m control inputs coupled to the control bus of m leads, a write strobe input coupled to the first write strobe output, and a first set of control outputs; and (d) a second register having m control inputs coupled to the control bus of m leads, a write strobe input coupled to the second write strobe output, and a second set of control outputs, in which m is an integer greater than 1.