Patent ID: 9543515
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A phase-change memory cell, comprising: a chalcogenide-based phase-change memory layer; a first electrode layer; a first interface layer between the chalcogenide-based phase-change memory layer and the first electrode layer and in contact with each of the chalcogenide-based phase-change memory layer and the first electrode layer, the first interface layer comprising a boride to provide a reduced resistance between the chalcogenide-based phase-change memory layer and the first electrode layer; a second interface layer between the chalcogenide-based phase-change memory layer and the second electrode layer and in contact with each of the chalcogenide-based phase-change memory layer and the second electrode layer, the second interface layer comprising a boride to provide a reduced resistance between the chalcogenide-based phase-change memory layer and the second electrode layer; a switching device layer comprising an ovonic threshold switch; a third electrode layer; a third interface layer between the switching device layer and the second electrode layer and in contact with each of the switching device layer and the second electrode layer; and a fourth interface layer between the switching device and the third electrode layer and in contact with each of the switching device layer and the third electrode layer.