Patent ID: 9680526
Date: 2017-06-13
CPC Classifications: G11B,H04B

Claim:
1. A phase error detector comprising: a first counter configured to frequency-divide a first clock using N (N is a natural number), and output a signal at a predetermined timing; a second counter configured to frequency-divide a second clock using M (M is a natural number), and output a signal at a predetermined timing; a comparator configured to perform phase comparison between a phase of the first clock when a value of the first counter is 0 and a phase of the second clock when a value of the second counter is 0, and perform phase comparison between a phase of the first clock when a value of the first counter is equal to a predetermined value, which is determined using N and is greater than 0 and is less than N, and a phase of the second clock when a value of the second counter is equal to a predetermined value, which is determined using M and is greater than 0 and is less than M; and a synthetic circuit configured to generate a phase error, based on comparison results of the comparator.