Patent ID: 9710415
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. A system for transferring input data to an asynchronous clock domain, the system comprising: a write address generator for receiving a write increment signal and a write clock signal, incrementing a write address count value, and generating a write address signal; a write pointer encoder, connected to the write address generator, for receiving the write address count value, encoding the write address count value using a Johnson code, and generating a write pointer; a write pointer synchronizer, connected to the write pointer encoder, for receiving a read clock signal and the write pointer, and outputting a synchronized write pointer; a write pointer validator, connected to the write pointer synchronizer, for receiving the synchronized write pointer and generating a write pointer valid signal when the synchronized write pointer conforms to a Johnson code format; a write pointer decoder, connected to the write pointer synchronizer and the write pointer validator, for receiving the synchronized write pointer and the write pointer valid signal, respectively, decoding the synchronized write pointer, and generating a synchronized write address count value; a read address generator, connected to the write pointer decoder, for receiving a read increment signal, the read clock signal, and the synchronized write address count value, incrementing a read address count value based on the read increment signal and the synchronized write address count value, and generating a read address signal; and an asynchronous first-in-first-out (FIFO) buffer, connected to the read and write address generators, for receiving the read and write address signals, respectively, storing the input data based on the write address signal, and transferring the input data to the asynchronous clock domain based on the read address signal.