Patent ID: 9710585
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. A method of performing technology mapping of a logic design to physical components in a logic synthesis phase of design of an integrated circuit, the method comprising: subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports; determining, using a processor, a location of each of one or more latches in a logic design; determining, using the processor, a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, the one or more input ports, or the one or more output ports; and obtaining the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays, wherein the technology mapping refers to selecting standard cell library elements for the physical components of the integrated circuit, the obtaining the technology mapping includes performing the determining the location of each of the one or more latches and the determining the location of each of the one or more combinational logic gates iteratively until a timing requirement is met, and physical implementation of the integrated circuit is based on the technology mapping.