Patent ID: 9654096
Date: 2017-05-16
CPC Classifications: H03K

Claim:
1. A power-on-reset circuit for a system-on-chip (SOC), the power-on-reset circuit comprising: a biased switching element having a source, a drain, and a gate, the source being connected to a supply voltage, and the drain and gate being connected to a control line; a first delay switching element having a source connected to a reduced supply voltage, a gate connected to the control line, and a drain; an inverter having an input and an output, the input of the inverter being connected to the drain of the first delay switching element, the inverter including a first CMOS inverter coupled between the supply voltage and a reference voltage; a first capacitor coupled between the inverter input and the reference voltage; and a second capacitor coupled between the inverter input and an output of the first CMOS inverter.