Patent ID: 9589937
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A semiconductor cooling method in a mixed bonding process, comprising: providing two wafers which require to be treated by a mixed bonding process, each of the wafers being provided with several metallic device structure layers therein; a heat dissipation layer is arranged in at least one of the wafers, said heat dissipation layer is arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer; wherein, material of each of said heat dissipation layers is a good conductor of heat; said heat dissipation layer, through a plurality of holes, connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer; said plurality of holes uniformly distribute in a same plane; said heat dissipation layer is composed of a plurality of parallel distributed metal wires in a same plane; and an interval between every two adjacent wires is of the same distance.