Patent ID: 9583410
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A volumetric integrated circuit manufacturing method, comprising: forming a wiring layer on an elongate chip; assembling a slab element of the elongate chip and additional elongate chips such that the wiring layer is disposed between the elongate chip and an adjacent elongate chip of the additional elongate chips; exposing the wiring layer between the elongate chip and the adjacent elongate chip of the slab element; metallizing a surface of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer; and passivating the metallized surface to hermetically seal the metallized surface, wherein the exposing comprises removing material that impedes exposure of the wiring layer from the surface of the slab element around the wiring layer, passivating the surface of the slab element and the wiring layer to form a passivation layer and removing a portion of the passivation layer at the wiring layer to expose the wiring layer through the passivation layer.