Patent ID: 9640147
Date: 2017-05-02
CPC Classifications: G09G,G11C

Claim:
1. A driving circuit of a display panel, comprising: a capacitor comprising a first electrode plate and a second electrode plate wherein the second electrode plate is connected to a signal output line; a first thin film transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is connected to the first source electrode, and the first gate electrode and the first source electrode are configured to receive a first control signal from a first signal source; a second thin film transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, wherein the first drain electrode is connected to the second source electrode and the second drain electrode is connected to the first electrode plate of the capacitor, and the second gate electrode is configured to receive a second control signal from a second signal source; a third thin film transistor comprising a third gate electrode, a third source electrode, and a third drain electrode, wherein the third gate electrode is connected to the first drain electrode, and the third drain electrode is configured to receive a first power source signal; a fourth thin film transistor comprising a fourth gate electrode, a fourth source electrode, and a fourth drain electrode, wherein the fourth gate electrode is connected to the third drain electrode, the fourth source electrode is configured to receive a second power source signal, and the fourth drain electrode is connected to the second drain electrode; a fifth thin film transistor comprising a fifth gate electrode, a fifth source electrode, and a fifth drain electrode, wherein the fifth gate electrode is configured to receive a third control signal from a third signal source, the fifth drain electrode is connected to the third drain electrode, and the fifth source electrode is configured to receive a third power source signal; a reset thin film transistor comprising a sixth gate electrode, a sixth source electrode, and a sixth drain electrode, wherein the sixth gate electrode is connected to the fifth drain electrode, the sixth drain electrode is connected to the signal output line, and the sixth source electrode is configured to receive a fourth power source signal; an output thin film transistor comprising a seventh gate electrode, a seventh source electrode, and a seventh drain electrode, wherein the seventh source electrode is configured to receive a fourth control signal from a fourth signal source, the seven gate electrode is connected to the second drain electrode, and the seventh drain electrode is connected to the signal output line; a sixth thin film transistor comprising an eighth gate electrode, an eighth source electrode, and an eighth drain electrode, wherein the eighth gate electrode is connected to the signal output line, the eighth source electrode is configured to receive a fifth power source signal, and the eighth drain electrode is connected to the sixth gate electrode; and a seventh thin film transistor comprising a ninth gate electrode, a ninth source electrode, and a ninth drain electrode, wherein the ninth gate electrode is configured receive a fifth control signal from a fifth signal source, the ninth source electrode is configured to receive the second power source signal, and the ninth drain electrode is connected to the fourth source electrode; wherein the output thin film transistor comprises a first width-to-length ratio, and the reset thin film transistor comprises a second width-to-length ratio, and the first width-to-length ratio is greater than the second width-to-length ratio.