Patent ID: 9680765
Date: 2017-06-13
CPC Classifications: G06F,H04L

Claim:
1. A processor to comprise: a router of a network-on-chip, the router to comprise a first channel reservation bank associated with an input port of a plurality of input ports of the router, and a second channel reservation bank associated with an output port of a plurality of output ports of the router, the first channel reservation bank to comprise a plurality of channel reservation slots that are each associated with a distinct circuit-switched channel of the input port and are to store direction information associated with a distinct channel reservation request, the second channel reservation bank to comprise a plurality of channel reservation slots that are each associated with a distinct circuit-switched channel of the output port, the router to: receive first and second channel reservation requests via a packet-switched network; store first information associated with the first channel reservation request in a first slot of the first channel reservation bank and store second information associated with the first channel reservation request in a first slot of the second channel reservation bank, wherein the first information uniquely identifies the output port of the plurality of output ports and the second information uniquely identifies the input port of the plurality of input ports; store information associated with the second channel reservation request in a second slot of the first channel reservation bank; establish a first portion of a first circuit-switched channel based on the first information stored in the first slot of the first channel reservation bank and establish a second portion of the first circuit-switched channel based on the second information stored in the first slot of the second channel reservation bank; and establish at least a portion of a second circuit-switched channel based on the information stored in the second slot of the first channel reservation bank.