Patent ID: 9620463
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A device, comprising: a fan-out wafer level package (FOWLP) comprising at least one conductor portion and at least one insulator portion; a first chip comprising a first plurality of contacts, the first chip positioned in direct contact with the FOWLP; a second chip comprising a second plurality of contacts, the second chip positioned in direct contact with the FOWLP, the first chip and the second chip spaced apart by a gap, and the at least one conductor portion of the FOWLP positioned directly opposite the gap between the first chip and the second chip; and a conductor shield comprising a plurality of conductor surfaces, at least one of the conductor surfaces directly connected to the at least one conductor portion of the FOWLP directly opposite the gap between the first chip and the second chip, at least one of the conductor surfaces immediately surrounding the first chip, and at least one of conductor surfaces immediately surrounding the second chip, wherein a bottom surface of the first chip including bottom surfaces of the first plurality of contacts, a bottom surface of the second chip including bottom surfaces of the second plurality of contacts, and the at least one of the conductor surfaces directly connected to the at least one conductor portion of the FOWLP directly opposite the gap between the first chip and the second chip are substantially flush with each other.