Patent ID: 9627441
Date: 2017-04-18
CPC Classifications: G11C,H01L

Claim:
1. A memory cell comprising: a first resistive switching element comprising a first high resistance state and a first low resistance state and having a first terminal and a second terminal; a second resistive switching element comprising a first high resistance state and a first low resistance state and having a first terminal and a second terminal; a field effect transistor having a first source/drain and a second source/drain, the first source/drain coupled to the first terminal of the first resistive switching element, the second source/drain coupled to the first terminal of the second resistive switching element; a first diode having a first terminal and a second terminal; and a second diode having a first terminal and a second terminal, wherein the first source/drain is coupled to the first terminal of the first diode, and wherein the second source/drain is coupled to the first terminal of the second diode.