Patent ID: 9628096
Date: 2017-04-18
CPC Classifications: H03L

Claim:
1. A determination method of a reference frequency of a fractional N-PLL circuit, comprising: calculating, for each of a plurality of reference frequencies, a detuning frequency, wherein, for a given output frequency of an oscillation unit included in the fractional N-PLL circuit, the detuning frequency is between the given output frequency and a frequency that is an integer multiple of a respective reference frequency; calculating the sum of reciprocals of a plurality of detuning frequencies, or the sum of the plurality of detuning frequencies based on the detuning frequency calculated for each of the plurality of reference frequencies; and selecting one of the plurality of reference frequencies, in order to operate the fractional N-PLL circuit, based on the sum of reciprocals of the detuning frequencies, or the sum of the detuning frequencies.