Patent ID: 9536592
Date: 2017-01-03
CPC Classifications: G11C

Claim:
1. A memory device comprising: a first transistor, a second transistor, a storage capacitor, a selection circuit, and a memory circuit, wherein a first signal is to be input to a first input terminal of the selection circuit input wherein an output terminal of the selection circuit is electrically connected to an input terminal of the memory circuit, wherein one of a source and a drain of the first transistor is electrically connected to an output terminal of the memory circuit, wherein the other of the source and the drain of the first transistor is electrically connected to one of terminals of the storage capacitor and one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a second input terminal of the selection circuit, wherein the first transistor includes an oxide semiconductor layer that includes a channel formation region, wherein the second transistor includes an oxide semiconductor layer that includes a channel formation region, wherein a second signal originating from the output terminal of the memory circuit is to be input to the second input terminal of the selection circuit through the first transistors and the second transistor, and wherein the selection circuit is configured to select the first signal or the second signal and is configured to output the selected signal to the input terminal of the memory circuit.