Patent ID: 9626319
Date: 2017-04-18
CPC Classifications: G06F

Claim:
1. An apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: determining performance capabilities of a device coupled to a Peripheral Component Interconnect Connect Interface Express (PCIe) bus, including: allocating, in response to determining that the one or more performance capabilities of a downstream device are less than the performance capabilities of the device, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the downstream device, including allocating fewer lanes in the PCIe bus for use by the device than would be allocated for the device if the allocating were performed in dependence upon the performance capabilities of the device.