Patent ID: 9659669
Date: 2017-05-23
CPC Classifications: G01R,G06F,G11B,G11C

Claim:
1. A memory device comprising: an array of memory cells configured for storing data; and a non-volatile memory (NVM) storage array configured for storing a fail address indicating a failed memory cell from the array of memory cells; a temporary fail address storage (TFAS) device, configured to temporarily store the fail address; a control unit directly coupled to the TFAS device and the NVM storage array to transfer the fail address to the NVM storage array, a decoding unit coupled to the control unit and configured to receive and decode a control signal and to generate a mode enable signal further comprising: an address buffer coupled to the TFAS device and configured to receive fail address; and a control buffer coupled to the decoding unit and configured to receive the control signal, wherein the non-volatile storage array comprises an anti-fuse array, wherein the anti-fuse array is an m×n array, wherein m and n are at least 2.