Patent ID: 9697174
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A processor that is configured to, in response to one or more instructions: load a bit vector into a first register that resides in the processor; starting at a location in the first register, search the bit vector in the first register for a first set of bits that are set to one; for each bit in the first set of bits, store a corresponding index value, of one or more of index values, in a SIMD register in the processor; wherein the SIMD register includes a series of subregisters; wherein, within the SIMD register, each corresponding index value is stored in a separate subregister of the series of subregisters; wherein, within the SIMD register, each index value represents a position, within the bit vector, of a corresponding bit that is set to one; and wherein bits in the bit vector are contiguous.