Patent ID: 9742416
Date: 2017-08-22
CPC Classifications: H03L

Claim:
1. An integrated circuit comprising: A. a reference clock signal lead; B. digitally controlled oscillator circuitry having a filtered input and a digitally controlled oscillator clock output lead; C. digital filter circuitry having a phase error signal input and a filtered output lead connected to the filtered input; D. phase detector circuitry having a reference clock input connected to the reference clock signal lead, a digitally controlled oscillator clock input connected to the digitally controlled oscillator clock output lead, and a phase error signal output lead connected to the phase error signal input, the phase detector circuitry including a first switch having an input, an output coupled to the phase error signal output lead, and a re-timed reference clock control input; E. re-timing circuitry having a reference clock input connected to the reference clock signal lead, a digitally controlled oscillator clock input directly connected to the digitally controlled oscillator clock output lead, an edge select signal input, and a re-timed reference clock signal output lead connected to the re-timed reference clock control input of the first switch; and F. edge select circuitry having an input connected to the reference clock signal lead, an input connected to the digitally controlled oscillator clock output lead, and an edge select signal output coupled to edge select signal input.