Patent ID: 9727417
Date: 2017-08-08
CPC Classifications: G06F,G11C

Claim:
1. An integrated circuit comprising: two or more addressable blocks of memory, and at least one redundant block of memory, the two or more addressable blocks of memory respectively include at least a first chunk of memory cells of a first tile and a second chunk of memory cells of a second tile; redundancy control cells; and control circuitry to access a first redundant chunk of memory cells of the at least one redundant block of memory in place of a first remapped chunk of memory cells of the two or more addressable blocks of memory, and a second redundant chunk of memory cells of the at least one redundant block of memory in place of a second remapped chunk of memory cells of the two or more addressable blocks of memory, based on information stored in the redundancy control cells, wherein the two or more addressable blocks of memory and the at least one redundant block of memory further respectively include block word lines, and chunks of memory cells respectively include: