Patent ID: 9716487
Date: 2017-07-25
CPC Classifications: H03K

Claim:
1. A three dimensional (3D) package having a latency compensation circuit to address timing delays introduced by a through silicon via (TSV), comprising: a signal TSV extending from a first die to a second die of the 3D package; a redundant TSV extending from the first die to the second die; a launched clock driving the signal TSV and the redundant TSV; a reference data signal generated at the first die, passing from the first die to the second die through the signal TSV, and subsequently passing from the second die back to the first die through the redundant TSV; an input for receiving a local clock signal and for receiving the reference data signal from the redundant TSV after the reference data signal has passed back to the first die through the redundant TSV; a timing slack sensor that outputs a digital value reflecting a delay between a clock pulse of the local clock signal and the reference data signal caused by the passage of the reference data signal through the signal TSV; a look-up table that converts the digital value into a set of control bits; and an adjustable delay line that adjusts the local clock signal based on the set of control bits.