Patent ID: 9698969
Date: 2017-07-04
CPC Classifications: H03L,H04L

Claim:
1. A half-rate clock data recovery circuit for providing a clock data signal to a data processing circuit, the half-rate clock data recovery circuit comprising: a control voltage generating circuit arranged to operably generate a control voltage; a data sampling circuit arranged to operably conduct a data sampling operation on an input data based on a data sampling clock to generate the clock data signal; an edge sampling circuit arranged to operably conduct an edge sampling operation on the input data based on an edge sampling clock to generate an edge-sampled signal; a phase detection circuit, coupled with the control voltage generating circuit, the data sampling circuit, and the edge sampling circuit, arranged to operably compare data consistency of the clock data signal and the edge-sampled signal with respect to adjacent sampling points of time so as to control the control voltage generating circuit to adjust the control voltage; a voltage-controlled oscillator, coupled with the control voltage generating circuit, arranged to operably generate the data sampling clock and the edge sampling clock according to the control voltage; an adjusting circuit, coupled with the voltage-controlled oscillator, arranged to dynamically control the voltage-controlled oscillator to configure a phase difference between the data sampling clock and the edge sampling clock to be different from 90 degrees in multiple test periods; and a control circuit, coupled with the adjusting circuit, arranged to operably instruct the adjusting circuit to respectively utilize different control value combinations to control the voltage-controlled oscillator in the multiple test periods, and to operably record multiple recovered-signal quality indicators respectively corresponding to the multiple test periods and generated by the data processing circuit; wherein after the multiple test periods, the control circuit instructs the adjusting circuit to utilize a control value combination corresponding to a best quality indicator among the multiple recovered-signal quality indicators to control the voltage-controlled oscillator so as to reduce an error rate of the clock data signal.