Patent ID: 9653151
Date: 2017-05-16
CPC Classifications: G11C,H01L

Claim:
1. An apparatus comprising: a memory array tile comprising a cross-point memory array having a plurality of word-lines, a plurality of bit-lines, and a plurality of memory cells at one or more intersections of the plurality of word-lines and the plurality of bit-lines; a decoder comprising a first plurality of inputs corresponding to a first portion of a row address, and a first plurality of outputs coupled to at least a portion of the plurality of word-lines; a multiplexor comprising a second plurality of inputs corresponding to a second portion of the row address, a third plurality of inputs coupled to at least a portion of the plurality of bit-lines, and at least one multiplexor output; and at least one memory device coupled to the at least one multiplexor output, the at least one memory device comprising an input based on at least a portion of a column address, and wherein a read access time of the at least one memory device is shorter than a read access time of a memory cell of the cross-point memory array.