Patent ID: 9570680
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method for fabricating an electronic device having a semiconductor memory unit, comprising: forming a mask pattern which is defined with hole patterns of an asymmetrical arrangement with different longitudinal and transverse intervals, over an etch target layer; and etching the etch target layer, using the mask pattern as an etch barrier, wherein the forming of the mask pattern comprises: forming a photoresist pattern with a plurality of openings which are defined by first regions where optical processing is performed and second regions where optical processing is not performed over a sacrificial layer; forming a gap filling layer to fill or cover the openings defined by the second regions of the photoresist pattern; and etching the sacrificial layer using the first regions of the photoresist pattern and the gap filling layer as etch barriers, and forming a sacrificial pattern which is defined with the hole patterns of the asymmetrical arrangement with the different longitudinal and transverse intervals.