Patent ID: 9727121
Date: 2017-08-08
CPC Classifications: G06F,H04W,Y02D

Claim:
1. A wireless communication device comprising: a plurality of processors; a plurality of memories, each of which is paired with one of the processors, and is capable of retaining data in a power saving state; a clock control circuit configured to control when a clock is to be supplied to each pair of the processor and the memory; and a power control circuit configured to control an amount of power to be supplied to each pair of the processor and the memory, wherein, in the power saving state, the clock control circuit stops supplying the clock to a pair of the processor and the memory, and the power control circuit reduces the amount of power supplied to the memory of the pair, and when returning transitioning from the power saving state to a normal power state, the power control circuit increases the amount of power supplied to the memory of the pair to a normal level, and then the clock control circuit starts supplying the clock to the memory before starting to supply of the pair, and then starts supplying the clock to the processor of the pair; wherein, when transitioning from the normal power state to the power saving state, the power control circuit reduces the amount of power supplied to the memory of the pair after the clock control circuit stops supplying the clock to the memory of the pair.