Patent ID: 9601175
Date: 2017-03-21
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A memory, comprising: a first source line; a first set of memory cells; a first plurality of bit lines; a first set of selection transistors, wherein each selection transistor of the first set of selection transistors is coupled in series with a corresponding memory cell of the first set of memory cells, wherein each selection transistor and corresponding memory cell are coupled in series between the first source line and a corresponding bit line of the first plurality of bit lines; a word line coupled to a gate of each selection transistor of the first set of selection transistors; a word line driver coupled to the word line, wherein the word line driver is configured to drive the word line to a word line voltage; circuitry coupled to the word line, wherein the circuitry is configured to isolate the word line from the word line driver after the word line is driven to the word line voltage, wherein isolating the word line produces an isolated word line; and first driver circuitry coupled to the first plurality of bit lines, the first driver circuitry configured to drive each bit line of the first plurality of bit lines to a first bit line voltage, wherein the first bit line voltage is different than the first word line voltage, and wherein driving each bit line of the first plurality of bit lines to the first bit line voltage adjusts voltage on the isolated word line to a second word line voltage.