Patent ID: 9558312
Date: 2017-01-31
CPC Classifications: G06F,H01L

Claim:
1. A method for designing a standard cell semiconductor device layout, comprising: selecting a plurality of cells having substantially similar sizes in at least one direction, said plurality of cells including first cells and identified target cells, wherein said identified target cells are configured to operate using different operational characteristics than said first cells; arranging said plurality of cells in a plurality of rows of the semiconductor device layout; placing power and ground wires over said plurality of cells; arranging first power rail lines of a first device level and extending along respective boundaries between adjacent rows of said plurality of rows; and arranging second power rail lines of a second device level, wherein said second power rail lines are not present in regions that are between said power and ground wires that do not contain at least one said identified target cell, wherein the semiconductor device layout is used to fabricate a photomask.