Patent ID: 9727359
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A system comprising: a memory; a host device; a guest device; one or more processors, in communication with the memory; a virtual machine, including a guest operating system, executing on the one or more processors; a host operating system executing on the one or more processors; and a hypervisor executing on the one or more processors to: receive, from the virtual machine, a value stored in a guest device register; responsive to receiving the value stored in the guest device register, generate, by the hypervisor, a page table including a first mapping between the value stored in the guest device register and a first address of the host operating system and a second mapping between a second address of the host operating system and a third address of a virtual machine function on the host operating system; modify, by the hypervisor, a first access status of the first mapping, wherein modifying the first access status includes rendering memory of the host device referenced by the value stored in the guest device register accessible to the virtual machine function; modify, by the hypervisor, a second access status of the second mapping, wherein modifying the second access status includes rendering the virtual machine function accessible to the virtual machine; and initialize, by the hypervisor, code on the virtual machine function to access the memory of the host device.