Patent ID: 9647109
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductor layer provided on a substrate, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, and a fourth semiconductor region of the first conductivity type, the first semiconductor region being provided on the substrate, the second semiconductor region being provided on the first semiconductor region, a first conductivity-type impurity concentration being lower in the second semiconductor region than in the first semiconductor region, the third semiconductor region being provided on the second semiconductor region, the fourth semiconductor region being provided in a surface of the third semiconductor region; a first conductive unit provided on the first semiconductor region, the first conductive unit including a fifth semiconductor region and a metal region, the fifth semiconductor region contacting the first semiconductor region, the metal region being provided on the fifth semiconductor region; a first insulating film extending in a thickness direction of the semiconductor layer from a surface of the fourth semiconductor region to the substrate, the first insulating film being adjacent to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first semiconductor region; a second insulating film extending in the thickness direction of the semiconductor layer from the surface of the fourth semiconductor region to the first semiconductor region, the second insulating film being provided between the fourth semiconductor region and the first conductive unit, between the third semiconductor region and the first conductive unit, and between the second semiconductor region and the first conductive unit; a gate electrode placed at an opposite side of the third semiconductor region; and a gate insulator film provided between the third semiconductor region and the gate electrode.