Patent ID: 9548312
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a semiconductor structure comprising a nonvolatile memory cell element and one or more electrically insulating layers covering said nonvolatile memory cell element, said nonvolatile memory cell element comprising a source region, a channel region, a drain region and a floating gate over at least a first portion of said channel region; forming a first opening in said one or more electrically insulating layers over said floating gate; after the formation of said first opening, depositing a control gate insulation layer; after the deposition of said control gate insulation layer, forming a second opening in said one or more electrically insulating layers over said drain region; and filling said first opening and said second opening with an electrically conductive material, wherein said electrically conductive material in said first opening provides a control gate of said nonvolatile memory cell element and said electrically conductive material in said second opening provides an electrical contact to said drain region.