Patent ID: 9696988
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. An upgrade processing method for a complex programmable logical device (CPLD), the method comprising: splitting a serial vector format (SVF) file into a first SVF sub-file and a second SVF sub-file, wherein the first SVF sub-file is used to instruct the CPLD to load an upgrade program of the CPLD into a flash memory of the CPLD in a background mode, lock a pin of the CPLD, load the upgrade program stored in the flash memory to a static random access memory (SRAM) of the CPLD, and pause, and wherein the second SVF-sub-file is used to instruct the CPLD to release the pin of the CPLD after the register information and the pin signal of the CPLD are restored; generating a first Versa Module Europa (VME) bus file according to the first SVF sub-file, wherein the first VME bus file is used to execute an operation of upgrading the program of the CPLD; generating a second VME bus file according to the second SVF sub-file, wherein the second VME bus file is used to execute an operation of releasing the pin of the CPLD; backing up register information and a pin signal of the CPLD; upgrading a program of the CPLD using the first SVF sub-file and the first VME bus file, wherein upgrading the program of the CPLD comprises: restoring the register information and the pin signal of the CPLD using the second SVF sub-file and the second VME bus file, wherein the restoring comprises: