Patent ID: 9727343
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A data processing apparatus comprising: processing circuitry configured to process data in one of a plurality of exception states, including at least a base level exception state and a further level exception state; a base level stack pointer register for storing a base level stack pointer indicating a location within memory of a base level stack data store; a further level stack pointer register for storing a further level stack pointer indicating a location within memory of a further level stack data store; an exception return register for storing exception return data for use when returning from the further level exception state; and stack pointer selection circuitry for selecting a current stack pointer from at least the base level stack pointer and the further level stack pointer when processing data in the further level exception state, wherein the processing circuitry is configured to use the exception return register when returning from the further level exception state, irrespective of whether the current stack pointer is the base level stack pointer or the further level stack pointer.