Patent ID: 9553606
Date: 2017-01-24
CPC Classifications: G06F,H03M

Claim:
1. A bit group-unit interleaver, comprising: a first memory configured to store a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15; a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; and a second memory configured to store the interleaved codeword corresponding to a modulator for 64-symbol mapping, wherein the interleaving is performed using the following equation using permutation order: where X wherein the permutation order corresponds to an interleaving sequence represented by the following interleaving sequence: {74 72 104 62 122 35 130 0 95 150 139 151 133 109 31 59 18 148 9 105 57 132 102 100 115 101 7 21 141 30 8 1 93 92 163 108 52 159 24 89 117 88 178 113 98 179 144 156 54 164 12 63 39 22 25 137 13 41 44 80 87 111 145 23 85 166 83 55 154 20 84 58 26 126 170 103 11 33 172 155 116 169 142 70 161 47 3 162 77 19 28 97 124 6 168 107 60 76 143 121 42 157 65 43 173 56 171 90 131 119 94 5 68 138 149 73 67 53 61 4 86 99 75 36 15 48 177 167 174 51 176 81 120 158 123 34 49 128 10 134 147 96 160 50 146 16 38 78 91 152 46 127 27 175 135 79 125 82 2 129 153 14 40 32 114 106 17 110 140 71 136 112 45 64 29 69 118 66 37 165}.