Patent ID: 9601528
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate insulating layer on the gate and the gate line; forming a pixel electrode on the gate insulating layer; and forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line, wherein the first connecting via is configured to connect a scanning signal trace to the gate line, wherein, the step of forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line comprises steps of: coating a layer of photoresist on the pixel electrode and the gate insulating layer; exposing the photoresist with a mask and developing the photoresist, such that a portion of the photoresist in a display region and on the pixel electrode is removed partially or completely, and a portion of the photoresist in the non-display region and corresponding to the gate line is removed completely; etching the gate insulating layer to form the first connecting via in a portion of the gate insulating layer in the non-display region and corresponding to the gate line; and stripping off residual photoresist.