Patent ID: 9721894
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising: forming a dielectric layer over a substrate; forming an opening in the dielectric layer, the opening having a first region, a second region and a third region, a width of the first region being greater than a width of the second region, the third region being disposed over and connecting the first and second regions; forming a first metal layer in the first to third regions; forming a second metal layer in the first and third regions; and performing a planarization operation on the first and second metal layers so that a first metal wiring by the first region, a second metal wiring by the second region and a third metal wiring by the third region connecting the first and second metal wirings are formed, wherein: a metal material of the first metal layer is different from a metal material of the second metal layer, and the first and third metal wirings include the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.