Patent ID: 9741737
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. An integrated structure, comprising: vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level; a conductively-doped semiconductor material under the select device level, and spaced from the select device level by an insulative region; a channel material extending vertically along the memory cell levels and the select device level, and extending downwardly into the conductively-doped semiconductor material; a region of the channel material that extends into the conductively-doped semiconductor material being a lower region of the channel material and having a vertical sidewall; a tunneling material, a charge-storage material and a charge-blocking material extending vertically along the channel material and being between the channel material and the vertically-stacked conductive levels; the tunneling material, charge-storage material and charge-blocking material not being along at least a portion of the vertical sidewall of said lower region of the channel material; the conductively-doped semiconductor material being directly against said portion of the vertical sidewall of the lower region of the channel material; and wherein the conductively-doped semiconductor material is a second conductively-doped semiconductor material, and is over and directly against a first conductively-doped semiconductor material; wherein the channel material extends downwardly into the first and second conductively-doped semiconductor materials, and directly contacts both of the first and second conductively-doped semiconductor materials; and wherein the first and second conductively-doped semiconductor materials are compositionally different from one another.