Patent ID: 9665281
Date: 2017-05-30
CPC Classifications: G06F

Claim:
1. A computer implemented method for cache coherency verification using ordered lists, the method comprising: maintaining, by a cache coherency verification module, a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order; determining a state of an atom in an ordered list of the plurality of ordered lists; comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache; based on the comparing, determining that there is a coherency violation in the cache, wherein the processor comprises a simultaneous multithreaded (SMT) processor, and further comprising: based on an atom corresponding to a store completing in a first ordered list of the plurality of ordered lists, inserting a new atom corresponding to the store into a second ordered list of the plurality of ordered lists via bottom insertion, wherein bottom insertion comprises: