Patent ID: 9620506
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A transistor comprising: a silicon substrate; trenches formed in the silicon substrate; an isolation layer formed on the silicon substrate between a first one of the trenches and a second one of the trenches; an epitaxial silicon region formed on a first portion of the isolation layer, the epitaxial silicon region being isolated from the substrate by the isolation layer; a raised source and drain in contact with second and third portions of the isolation layer and in contact with the epitaxial silicon region, the first portion of the isolation layer on which the epitaxial silicon region is formed being between the second and third portions of the isolation layer, the raised source and drain being isolated from the substrate by the isolation layer; and a gate stack structure in contact with the epitaxial silicon region and in contact with the raised source and drain.