Patent ID: 9595330
Date: 2017-03-14
CPC Classifications: G11C

Claim:
1. A nonvolatile content addressable memory (NVCAM), comprising: a NOR-type match line non-volatile memory array having a plurality of NVCAM cells organized in rows and columns, each NVCAM cell comprising a switching transistor; a plurality of match lines extending horizontally, each match line being connected to the NVCAM cells in a corresponding row; and a plurality of bit line pairs and common source lines extending vertically, each bit line pair being connected to the NVCAM cells in a corresponding column, each common source line being connected to the NVCAM cells in two corresponding adjacent columns; wherein the NVCAM cells in each row are arranged in cell pairs such that source electrodes of the switching transistors of cell pairs in one column are connected to form a corresponding common source line and drain electrodes of the switching transistors of cell pairs in one row are connected to form a corresponding match line.