Patent ID: 9727460
Date: 2017-08-08
CPC Classifications: G06F,H03M

Claim:
1. A method of optimizing a configuration memory of a reconfigurable processor, the method comprising: analyzing parallelism of a loop of a program code based on architecture information regarding an architecture of the reconfigurable processor and information regarding the configuration memory, the analyzing including determining a number of function units (FUs) to be activated in each cycle of the loop; scheduling groups of the FUs to be activated in each cycle of the loop based on the analyzed parallelism; generating configuration data of each cycle; selecting a memory mapping scheme from among a plurality of memory mapping schemes based on the scheduling result; and storing the generated configuration data in the configuration memory based on the selected memory mapping scheme, wherein the generated configuration data of a plurality of cycles of the loop is mapped together on a row of the configuration memory when some of the FUs are activated according to the scheduling result.