Patent ID: 9582251
Date: 2017-02-28
CPC Classifications: G06F

Claim:
1. A processing network for receiving a source code having one or more code paths that are each associated with one or more conditions and one or more assignments of the source code, the network comprising: a plurality of processing elements on a programmable microchip, wherein each of the processing elements comprise one or more instruction tables and a logic cloud including a grid of logic devices, wherein a first column of the grid receives logic cloud input and a last column of the grid transmits logic cloud output; a plurality of on-chip routers on the microchip for routing the data between the processing elements, wherein each of the on-chip routers is communicatively coupled with one or more of the processing elements; and a compiler stored on a non-transitory computer-readable memory and comprising a logic cloud mapper that, based on the grid of logic devices, assigns functions to one or more of the logic devices and routes operable connections between the one or more of the logic devices such that the logic cloud, in conjunction with the instruction tables, implement the conditions and the assignments of the code paths of the source code, wherein each function corresponds to one or more device input values and a device output value, and further wherein the logic device assigned one of the functions will output the device output value in response to inputting the device input values, wherein the device input values and the device output value are selected from the group consisting of primary inputs that are to be received from the logic cloud input, intermediate results that are to be received from one of the logic devices or primary outputs that are the logic cloud output to be transmitted to the instruction tables, wherein the logic cloud mapper determines all possible serial chains of the functions that can be formed such that: