Patent ID: 9679863
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: an interconnect substrate including, a first semiconductor die disposed adjacent to the interconnect substrate including a first surface of the first semiconductor die coplanar with a first surface of the interconnect substrate and a second surface of the first semiconductor die opposite the first surface coplanar with a second surface of the interconnect substrate opposite the first surface of the interconnect substrate; a second encapsulant deposited completely around the first semiconductor die and further around an exterior perimeter of the interconnect substrate including a first surface of the second encapsulant coplanar with the first surface of the interconnect substrate and a second surface of the second encapsulant opposite the first surface coplanar with the second surface of the interconnect substrate; a first interconnect structure formed over a first surface of the second encapsulant and electrically connected to the conductive layer of the interconnect substrate; and a second interconnect structure formed under a second surface of the second encapsulant opposite the first surface of the second encapsulant.