Patent ID: 9691793
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. An array substrate, comprising: an active region; a peripheral circuitry region disposed surrounding the active region; a plurality of scan lines; a plurality of data lines intersected with and electrically insulated from the plurality of scan lines; a plurality of pixel driving circuit units disposed at intersections between the plurality of scan lines and the plurality of data lines; a plurality of first electrodes, which are electrically connected to the plurality of pixel driving circuit units respectively, and disposed in the active region and the peripheral circuitry region of the array substrate; and a plurality of first connection lines configured to connect the pixel driving circuit units to the corresponding first electrodes respectively, wherein, size of the first electrodes are the same, and lengths of the first connection lines corresponding to the pixel driving circuit units in the same row are successively increased from the center to an edge of the array substrate and constitute a arithmetic progression.