Patent ID: 9543950
Date: 2017-01-10
CPC Classifications: H03K

Claim:
1. A programmable logic device, comprising: a plurality of first lookup tables (LUTs) configured to form a larger lookup table, each first LUT having a true output node and a complement output node; a first plurality of NMOS pass transistors coupled between the true output nodes of the first LUTs and an internal true node; a second plurality of NMOS pass transistors coupled between the complement output nodes of the first LUTs and an internal complement node; a decoder configured to decode two input signals into four decoded signals, and wherein each lookup table is configured to ground one of its true and complement output nodes responsive to processing the four decoded signals; and a pair of PMOS transistors cross-coupled between the internal true node and the internal complement node and having their sources tied to a power supply node.