Patent ID: 9645927
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. A module of cache coherence management by directory in a multiprocessor system, in which each datum stored in cache memory is associated with one state among a plurality of states, at least a first state of which indicates data sharing among a plurality of processors of the multiprocessor system, the module comprising: a storage unit configured to store a directory containing a list of cache memory addresses, each address associated with one state among a plurality of states, said one state corresponding to the state of the datum available at the address, and a processing unit configured to update said list, said processing unit being configured so as not to list in said list address lines related to a first datum associated with the first state indicating data sharing among the plurality of processors notwithstanding the first datum being currently found in the first state and so as to list in said list address lines related to second datum associated with at least a second state different than the first state.