Patent ID: 9691842
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a plurality of first semiconductor regions of a first conductivity type spaced apart along a first direction and extending in a second direction intersecting the first direction; a plurality of second semiconductor regions of a second conductivity type extending in the second direction, each second semiconductor region being between adjacent first semiconductor regions along the first direction, at least one second semiconductor region including a void having at least one outer surface having a crystal plane orientation of (100); a third semiconductor region of the second conductivity type on each second semiconductor region; a fourth semiconductor region of the first conductivity type on the third semiconductor region; and a gate electrode on each first semiconductor region and adjacent to the third semiconductor region via a gate insulation layer, wherein the at least one second semiconductor region including the void includes a first portion and a second portion that is between the first portion and the first semiconductor region, the second portion having a carrier concentration of the second conductivity type that is higher than a carrier concentration of the second conductivity type in the first portion.