Patent ID: 9742594
Date: 2017-08-22
CPC Classifications: H04L

Claim:
1. An M-PAM receiver, where M≧4, comprising: a plurality of M-PAM detectors; at least one clock generator circuit to generate a plurality of clocks, each one of the plurality of clocks to be generated to have the same clock frequency but a different clock phase, and each one of the plurality of clocks to be used in a respective different one of the plurality of M-PAM detectors; circuitry to determine a plurality of intersymbol interference (ISI) values, one for each of the plurality of clocks, by: for each clock of the plurality of clocks, sampling a signal in a respective M-PAM detector using the clock to obtain a sampled signal and determining a value representing ISI based on the sampled signal; a timing skew determination module to receive the plurality of ISI values and instruct that a clock phase of at least one of the plurality of clocks be adjusted in response to at least one of the plurality of ISI values being different from a reference ISI value; wherein M=4, and wherein a particular 4-PAM detector associated with a particular clock comprises four branches; each one of the four branches having: (i) an adjustor to adjust an input signal by a respective offset to obtain a respective adjusted signal, and (ii) a slicer to slice the respective adjusted signal using the particular clock; wherein one of the four branches is an offline branch and the remaining three branches form a data decision value.