Patent ID: 9613978
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor construction, comprising: forming vertically-stacked memory cells along a vertically-extending channel material; forming an insulative material over the channel material; forming a first semiconductor material over the insulative material; forming metal-containing material over the first semiconductor material; forming a first opening to extend through the metal-containing material and the first semiconductor material to the insulative material; forming a gate dielectric along sidewalls and a bottom of the first opening; forming a second opening through the gate dielectric at the bottom of the first opening and through the insulative material; and forming second semiconductor material within the first and second openings; a portion of the second semiconductor material within the first opening being spaced from the first semiconductor material and the metal-containing material by at least the gate dielectric and being a transistor channel region.