Patent ID: 9613714
Date: 2017-04-04
CPC Classifications: G06F,G11C,H01L,H03K,H04L,Y04S

Claim:
1. A one time programming memory cell, comprising: a selecting circuit connected with a bit line and a word line; a first antifuse storing circuit connected with a first antifuse control line and the selecting circuit; and a second antifuse storing circuit connected with a second antifuse control line and the selecting circuit, wherein during a program cycle, a select voltage is provided to the word line, a ground voltage is provided to the bit line, and a program voltage is provided to the first antifuse control line and the second antifuse control line, wherein the selecting circuit provides the ground voltage to the first antifuse storing circuit and the second antifuse storing circuit, and the program voltage is applied to both of the first antifuse storing circuit and the second antifuse storing circuit, so that a storing state of the first antifuse storing circuit or the second antifuse storing circuit is changed, wherein during a read cycle, the select voltage is provided to the word line, the ground voltage is provided to the bit line, a read voltage is provided to the first antifuse control line, and the ground voltage is provided to the second antifuse control line, so that the first antifuse storing circuit generates a first read current to the bit line, wherein the first antifuse storing circuit is judged to have a first storing state or a second storing state according to the first read current, and one bit of a random code for a physically unclonable function technology is realized according to the first storing state or the second storing state of the first antifuse storing circuit.