Patent ID: 9595534
Date: 2017-03-14
CPC Classifications: G11C,H01L

Claim:
1. A NAND flash memory device comprising: a substrate formed of a semiconducting material, the substrate having an intermediate substrate region free from any source/drain region; at least first and second vertical pillars each including a plurality of memory cells, and the second vertical pillar being adjacent to the first vertical pillar, and the first vertical pillar including a first body portion, a first bottom portion and a first top portion, and the second vertical pillar including a second body portion, a second bottom portion and a second top portion, and the first and second body portions being in contact with the substrate and comprised of first and second semiconductor films respectively, and the first and second bottom portions also being in contact with the substrate, and the intermediate substrate region of the substrate being located between the first and second bottom portions; a first gate electrode that is not a part of a memory cell, the first gate electrode surrounding the first and second bottom portions such that the first and second body portions each penetrate the first gate electrode, and the first gate electrode being located on at least the intermediate substrate region with only a gate dielectric intervening between the first gate electrode and the intermediate substrate region; and first and second source/drain regions, the first source/drain region being located at the first top portion of the first vertical pillar, the second source/drain region being located at the second top portion of the second vertical pillar.