Patent ID: 9735061
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method comprising: providing an interfacial layer along the entirety of and on an upper surface of a semiconductor substrate; forming conformally a first high-k dielectric layer along the entirety of and on the interfacial layer; forming conformally a second high-k dielectric layer and a first cap layer, respectively, along the entirety of and on the first high-k dielectric layer while the interfacial layer exists along the entirety of the upper surface of the semiconductor substrate; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap layer on the first high-k dielectric layer in the first and second regions and on the first cap layer in a third region; performing an annealing process; removing the second cap layer from all regions and the first cap layer from the third region; forming a third high-k dielectric layer over all regions; forming conformally a work-function composition layer and a barrier layer, respectively, on the third high-k dielectric layer in all regions; removing the barrier layer from the first region; and forming a gate electrode over all regions.