Patent ID: 9627089
Date: 2017-04-18
CPC Classifications: G09G,G11C

Claim:
1. A shift register, comprising: a precharge and reset module, configured to precharge or reset a pull-up module according to a start signal input via a start signal input terminal or a reset signal input via a reset signal input terminal; the pull-up module, configured to pull up a signal output by an output terminal of the shift register; a first capacitor, configured to boost a voltage of a control terminal of the pull-up module in a pull-up stage; a pull-down module, configured to pull down a signal output by the output terminal of the shift register; and a cut-off module, configured to disconnect electric connection between the precharge and reset module and the pull-up module in the pull-up stage, wherein the precharge and reset module is connected to a first power source and a second power source, the pull-up module is connected to a first clock signal terminal, a first terminal of the first capacitor is connected to the control terminal of the pull-up module, a second terminal of the first capacitor is connected to the output terminal of the shift register, the pull-down module is connected to a third power source, the cut-off module, the pull-up module and the pull-down module are connected at a first node, the pull-up module and the pull-down module are connected to the output terminal of the shift register, the cut-off module is connected between the first node and the precharge and reset module, and the pull-up module and cut-off module are also connected at a second node; and wherein the cut-off module comprises: a ninth TFT, a tenth TFT, a third capacitor and a fourth power source, a gate of the ninth TFT is connected to the fourth power source, a source of the ninth TFT is connected to the precharge and reset module, a drain of the ninth TFT and a source of the tenth TFT are connected at the second node; a gate of the tenth TFT is connected to the fourth power source, the source of the tenth TFT is connected to a first terminal of the third capacitor, and a drain of the tenth TFT is connected to the first node; and a second terminal of the third capacitor is connected to the output terminal of the shift register.