Patent ID: 9711540
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A low temperature poly-silicon (LTPS) array substrate, comprising a plurality of LTPS thin-film transistors, wherein each of the LTPS thin-film transistors comprises a substrate; a patternized light shield layer formed on the substrate; a buffering layer formed on the substrate and the patternized light shield layer; a patternized poly-silicon layer formed on the buffering layer, wherein the patternized poly-silicon layer comprises a first portion having an orthogonal projection cast on the light shield layer and a second portion extending in a direction away from the light shield layer; a gate insulation layer formed on the patternized poly-silicon layer and the buffering layer; a first metal layer formed on the gate insulation layer, the first metal layer being patternized to form a gate electrode line and a common electrode line, the common electrode line, the second portion of the poly-silicon layer that corresponds to the common electrode line, and the gate insulation layer interposed between the common electrode line and the second portion collectively forming a first storage capacitor; an insulation layer formed on the gate insulation layer and the gate electrode line and the common electrode line; a second metal layer formed on the insulation layer, the second metal layer being patternized to form a drain electrode and a source electrode, the drain electrode comprising an extension section extending therefrom, the extension section having an orthogonal projection cast on the common electrode line, the extension section of the drain electrode and the common electrode line and the insulation layer between the extension section and the common electrode line collectively forming a second storage capacitor, the second storage capacitor being arranged in parallel with the first storage capacitor; and a planarization layer formed on the insulation layer and the patternized second metal layer; wherein each of the LTPS thin-film transistors comprises multiple storage capacitors that include at least the first storage capacitor and the second storage capacitor, wherein the first storage capacitor that is formed of the gate insulation layer interposed between the common electrode line and the second portion of the poly-silicon layer and the second storage capacitor that is formed of the insulation layer interposed between the common electrode line and the extension section of the drain electrode are respectively located on opposite sides of the common electrode line; wherein the LTPS array substrate further comprises a patternized bottom transparent conductive layer formed on the planarization layer, the bottom transparent conductive layer and the extension section of the drain electrode and the planarization layer between the extension section and the bottom transparent conductive layer collectively forming a third storage capacitor, the third storage capacitor being arranged in parallel with the second storage capacitor and the first storage capacitor, wherein the third storage capacitor that is formed of the planarization layer interposed between the bottom transparent conductive layer and the extension section of the drain electrode and the second storage capacitor that is formed of the insulation layer interposed between the common electrode line and the extension section of the drain electrode are respectively located on opposite sides of the extension section of the drain electrode; wherein the LTPS array substrate further comprises a protection layer formed on the patternized bottom transparent conductive layer and a top transparent conductive layer formed on the protection layer, the top transparent conductive layer and the bottom transparent conductive layer and the protection layer between the top transparent conductive layer and the bottom transparent conductive layer collectively forming a fourth storage capacitor, the fourth storage capacitor being arranged in parallel with the third storage capacitor, the second storage capacitor, and the first storage capacitor, wherein the fourth storage capacitor that is formed of the protection layer interposed between the bottom transparent conductive layer and the top transparent conductive layer and the third storage capacitor that is formed of the planarization layer interposed between the bottom transparent conductive layer and the extension section of the drain electrode are respectively located on opposite sides of the bottom transparent conductive layer wherein the first, second, third, and fourth storages are sequentially stacked in a vertical direction, where the common electrode line is common to the first and second storage capacitors; the extension section of the drain electrode is common to the second and third storage capacitors; and the bottom transparent conductive layer is common to the third and fourth storage capacitors such that the first, second, third, and fourth storage capacitors are connected parallel to each other.