Patent ID: 9748388
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: providing a substrate comprising a major surface; forming a shallow trench isolation (STI) within the substrate; forming a first gate stack on the major surface of the substrate and a second gate stack over the STI, wherein the STI is disposed on one side of the first gate stack, and wherein a sidewall spacer abuts the second gate stack; forming a cavity distributed between the first and second gate stacks, wherein the cavity comprises one sidewall defined by the STI, one sidewall defined by the substrate, and a bottom surface defined by the substrate; epitaxially growing a strained film in the cavity; forming an opening by removing a first portion of the strained film until exposing the bottom surface of the substrate, wherein a second portion of the strained film adjoins the STI sidewall and directly underlies the sidewall spacer of the second gate stack; and epitaxially growing a SiGe layer in the opening.