Patent ID: 9679655
Date: 2017-06-13
CPC Classifications: G11C

Claim:
1. A row decoder, for a non-volatile memory device that includes a memory array having memory cells arranged in a plurality of wordlines and is configured to receive a supply voltage, the row decoder comprising: an input and pre-decoding module, configured to receive address signals and generate pre-decoded address signals at a low voltage that is in the range of the supply voltage; a processing module, configured to receive the pre-decoded address signals and to both execute a combinational logic operation and boost a voltage of the pre-decoded address signals to generate decoded address signals, wherein the processing module comprises a plurality of processing units, each processing unit comprising a decoding stage that is configured to operate at low voltage and to execute the combinational logic operation of the pre-decoded address signals, and a boosting stage that is configured to operate at high voltage and to boost the voltage of results of the combinational logic operation to generate a respective one of the decoded address signals on an output terminal; and a driving module, configured to generate biasing signals for biasing the wordlines of the memory array at a high voltage that has been boosted by the processing module to a boosted voltage that is higher than the supply voltage.