Patent ID: 9536889
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A split gate memory device, comprising: a semiconductor substrate having a source region, a drain region, and a channel region located between the source region and the drain region, further comprising a conductive plug which is coupled to the source region, wherein the conductive plug is used for applying a voltage to the source region; a first gate oxide layer located on a first portion of the source region and a first portion of the channel region; a floating gate located on the first gate oxide layer; a second gate oxide layer located on a first portion of the drain region and a second portion of the channel region, wherein the first gate oxide layer and the second gate oxide layer are located on a same surface of the semiconductor substrate; a control gate located on the second gate oxide layer; an insulating layer isolating the first gate oxide layer and the floating gate away from the second gate oxide layer and the control gate; an insulating oxide layer located on the source region; an erasing gate located on the insulating oxide layer, wherein the floating gate is disposed between the erasing gate and the control gate on the surface of the semiconductor substrate; and a tunnel insulating layer located between the erasing gate and the floating gate.