Patent ID: 9659853
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. An interposer substrate, comprising: a dielectric layer with a first surface and a second surface opposite to the first surface, wherein the dielectric layer is formed of a same material throughout the dielectric layer; a first circuit pattern embedded in the dielectric layer and disposed at the first surface of the dielectric layer; a second circuit pattern embedded in the dielectric layer and disposed at the second surface of the dielectric layer; a middle patterned conductive layer disposed within the dielectric layer and between the first circuit pattern and the second circuit pattern, wherein the middle patterned conductive layer is single layered; at least one first conductive via connecting the first circuit pattern to the middle patterned conductive layer, each of the at least one first conductive via including a first end with a first width adjacent to the first circuit pattern and a second end with a second width adjacent to the middle patterned conductive layer, wherein the first width is greater than the second width; and at least one second conductive via connecting the second circuit pattern to the middle patterned conductive layer, each of the at least one second conductive via including a third end with a third width adjacent to the second circuit pattern and a fourth end with a fourth width adjacent to the middle patterned conductive layer, wherein the third width is greater than the fourth width.