Patent ID: 9589985
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A LTPS TFT substrate, comprising: a substrate; a buffer layer on the substrate; a first poly-Si region and a second poly-Si region arrayed on the buffer layer with a space between the two regions; a first source/drain and a second source/drain disposed above the first poly-Si region and the second poly-Si region; a gate insulating layer installed on the buffer layer, the first poly-Si region and second poly-Si region; a first gate and a second gate installed on the gate insulating layer corresponding to the first poly-Si region and second poly-Si region; an interlayer dielectric layer installed on the gate insulating layer, the first gate and the second gate; wherein both sides of the first poly-Si region and the second poly-Si region are next to a heavily N-doped area, which connects to the first source/drain and the second source/drain through the via hole; a display area and a drive area, with the first poly-Si region in the display area of the LTPS TFT substrate, and the second poly-Si region in the drive area of the LTPS TFT substrate; grains of the first poly-Si region are smaller than those of the second poly-Si region, while a uniformity of the grains of the first poly-Si region is larger than that of the second poly-Si region.