Patent ID: 9576857
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method comprising: forming a silicon germanium (SiGe) strained relaxed buffer (SRB) on a silicon (Si) substrate; forming a Si layer over the SiGe SRB; forming an n-type field-effect transistor (NFET) channel and a SiGe p-type FET (PFET) channel in the Si layer and adjacent to each other; forming a silicon nitride (SiN) layer over the NFET and PFET channels; forming first and second cuts through the SiN layer, the NFET and PFET channels, respectively, and the SiGe SRB down to the Si substrate, the first and second cuts formed on opposite ends of the Si substrate and perpendicular to the NFET and PFET channels; forming fins in the SiGe SRB through the SiN layer and the NFET and PFET channels, the fins formed perpendicular to the first and second cuts; forming a first oxide layer between the fins; forming a third cut between the NFET and PFET channels down into the SiGe SRB, the third cut formed parallel to the fins, and filling the third cut with a second oxide layer; recessing the first and second oxide layers down to the SiGe SRB; and removing the SiN layer.