Patent ID: 9569215
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A system for synchronizing parallel processing of a plurality of functional processing units, comprising: a first functional processing unit, a first program instruction buffer used by the first functional processing unit, a first program counter being configured to control timing of a first stream of program instructions issued to the first functional processing unit by advancement of the first program counter, the first program counter being configured to point to a current instruction in the first program instruction buffer which is read and issued by the first functional processing unit; a second functional processing unit, a second program instruction buffer used by the second functional processing unit; and a second program counter being configured to control timing of a second stream of program instructions issued to the second functional processing unit by advancement of the second program counter; the second program counter being configured to point to a current instruction in the second program instruction buffer which is read and issued by the second functional processing unit, wherein the first functional processing unit being in communication with the second functional processing unit and configured to synchronize the issuance of the first stream of program instructions to the second stream of program instructions and the second functional processing unit being in communication with the first functional processing unit and configured to synchronize the issuance of the second stream program instructions to the first stream of program instructions, and the first and second program instruction buffers include at least one pair of wait-go instructions in which one instruction of the wait-go pair is inserted in the first program instruction stream and the other instruction of the wait-go pair is inserted in the second program instruction stream.