Patent ID: 9678812
Date: 2017-06-13
CPC Classifications: G06F

Claim:
1. A switch of a data processing system, the switch comprising: integrated circuitry, including: data buffers for buffering messages; receive data structure including a plurality of receive entries each uniquely corresponding to a receive window, wherein each of the plurality of receive entries includes addressing information for one or more mailboxes into which messages can be injected via inter-thread push communication; a send data structure including a plurality of send entries each uniquely corresponding to a send window, wherein each of the plurality of send entries includes a receive window field that identifies one or more receive windows; and switch logic that, responsive to a request to push a message referenced by an instruction of a sending thread to one or more receiving threads, accesses a send entry among the plurality of send entries selected based on a send window of the sending thread, accesses one or more of the plurality of receive entries selected based on contents of the receive window field accessed in the send entry, and pushes the message to one or more mailboxes of the one or more receiving threads utilizing the addressing information of accessed in the one or more receive entries; wherein: each of the plurality of send entries further includes an independently configurable addressing mode field; and the switch logic employs one of a plurality of different addressing modes based on a configuration of the addressing mode field of the send entry.