Patent ID: 9536625
Date: 2017-01-03
CPC Classifications: G11C

Claim:
1. A memory sensor comprising: a redundant cell that is selected by a row decoder in response to a row address; a plurality of bit lines including a selected bit line that is connected to a normal selected cell during reading, and a redundant bit line that is connected to a redundant cell during reading; a plurality of sense amplifiers that receive the plurality of bit lines and sense data on the selected bit line to generate a data output; a read delay generator, coupled between the redundant bit line and the plurality of sense amplifiers, for delaying reading of the redundant cell over the redundant bit line; wherein the plurality of sense amplifiers also generates a delayed data output by sensing data on the redundant bit line after delay by the read delay generator; a compare gate that compares the data output to the delayed data output to generate a mismatch signal; and a failure latch that receives the mismatch signal and generates a timing failure signal that indicates that the delayed data output does not match the data output, whereby the timing failure signal is generated when delayed data read from the redundant cell does not match data read from the normal selected cell.