Patent ID: 9601458
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method of fabricating a stacked semiconductor package, the method comprising: providing a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, the first package substrate having lateral first and second sides extending in first and second directions, respectively, and constituting the outer periphery of the first package substrate, and wherein the outer periphery of the first package substrate has a plurality of corners, each of the first and second sides extends to and terminates at a pair of adjacent ones of the corners, and the first side is longer than the second side; providing a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, the second package substrate having a bottom surface; and forming a stack in which the first and second semiconductor packages are juxtaposed with a top surface of the first package substrate facing the bottom surface of the second package substrate, and providing a plurality of connections between an outer peripheral region of the top surface of the first package substrate to the outside of the first semiconductor chip and a region of the bottom surface of the second package substrate aligned with the outer peripheral region in the stack, including alongside the first longer side of the first package substrate, wherein a first group of the connections is provided alongside the longer first side of the first package substrate as spaced from one another in the first direction with at least one of the connections of the first group being located alongside an outer region of the first side adjacent to said one of the corners of the first package substrate, and at least one other of the connections of the first group being located alongside a central region of the first side intermediate the corners at which the first side terminates, and the heights of the connections of the first group are varied in the first direction from the central region to the outer region of the longer first side; and subsequently heat treating the connections to fix the second semiconductor package to the first semiconductor package.