Patent ID: 9698178
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method for manufacturing an array substrate, comprising steps of: coating a photoresist onto an insulation layer comprising a gate insulation layer and an etch stop layer, wherein the gate insulation layer covers a conductive pattern and the etch stop layer covers a semiconductive pattern; exposing the photoresist to form at least a photoresist partially-reserved region corresponding to a region where a first via hole is formed, and a photoresist unreserved region corresponding to a region where a second via hole is formed; performing a first etching process so as to at least partially remove a portion of the insulation layer located at a position corresponding to the photoresist unreserved region, thereby to form an intermediate hole; and performing a second etching process, so as to form the first via hole, and form the second via hole at a position of the intermediate hole, thereby to reveal the semiconductive pattern and the conductive pattern at positions corresponding to the first via hole and the second via hole, respectively, a depth of the first via hole being less than a depth of the second via hole.