Patent ID: 9645751
Date: 2017-05-09
CPC Classifications: G06F,G11C

Claim:
1. An offline characterization system that generates, during an offline characterization phase prior to the operational lifetime of a flash memory chip, a plurality of alternative sets of read operating parameter values associated with a LUN in the flash memory chip, wherein the flash memory chip includes one or more LUNs, each LUN includes one or more blocks of flash memory and an associated set of one or more n-bit control registers, and each control register stores the value of an operating parameter associated with that LUN, the offline characterization system comprising: (a) a set of write and erase operating parameter values stored in the control registers of the flash memory chip; (b) a pattern generator that generates test pattern data to be written to and read from the one or more blocks of flash memory; (c) a flash test controller that writes the test pattern data into the one or more blocks of flash memory in accordance with the set of write and erase operating parameter values, and reads the test pattern data following a simulated retention period, wherein the retention period is simulated by baking the flash memory chip using standard accelerated temperature-testing techniques; and (d) a Vt window generator that, upon completion of the simulated retention period: