Patent ID: 9679095
Date: 2017-06-13
CPC Classifications: G06F,Y02P

Claim:
1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method of layout decomposition, the method comprising: receiving layout data for a layout design, the layout design corresponding to at least a portion of an integrated circuit, the layout data comprising mask assignment information for some layout features; deriving data of a coloring graph from the layout data, the coloring graph comprising vertices for layout features in the layout design and edges between some pairs of vertices indicating the mask assignment information; applying repeatedly a plurality of graph simplification units to the coloring graph to derive a simplified coloring graph, wherein the applying repeatedly comprises applying one graph simplification unit in the plurality of graph simplification units to a part or a whole of the coloring graph to derive a first intermediate graph, applying one or more other graph simplification units in the plurality of graph simplification units to a part or a whole of the first intermediate graph to derive a second intermediate graph, and applying the one graph simplification unit again to a part or a whole of the second intermediate graph to simplify the part or the whole of the second intermediate graph by the one graph simplification unit, and wherein the applying repeatedly continues until no further simplification is achievable or a user-defined termination condition is met; decomposing, as part of a multiple patterning lithography process, the layout design based on the simplified coloring graph to generate decomposition information; and storing the decomposition information.