Patent ID: 9601167
Date: 2017-03-21
CPC Classifications: G05F,G11C,H03K

Claim:
1. A semiconductor device, comprising: a) a first dual-gate transistor having a signal gate coupled to a first data input, and a control gate coupled to a first control signal; b) a second dual-gate transistor having a signal gate coupled to a second data input, and a control gate coupled to a second control signal, wherein the first and second dual-gate transistors are arranged in a configuration of an amplifier; and c) a calibration circuit configured to adjust the first and second control signals when enabled, and to maintain the first and second control signals when disabled, wherein the calibration circuit comprises a calibration timing controller configured to receive a clock and a calibration command signal, to count a plurality of clock cycles in response to activation of the calibration command signal, and to generate a plurality of calibration control signals in response to activation of the calibration command signal, and a calibration control circuit configured to receive a data output from the amplifier and a subset of the plurality of calibration control signals, and to generate the first and second control signals.