Patent ID: 9698800
Date: 2017-07-04
CPC Classifications: H03K,H03L

Claim:
1. A clock signal generation circuit, comprising: a phase-locked loop including a voltage-controlled oscillator, the phase-locked loop receiving an input clock signal and providing an output signal that is phase-locked to the input clock signal; and a frequency divider circuit receiving the output signal of the phase-locked loop, wherein the frequency divider circuit (i) generates a plurality of signals of various frequencies by dividing the frequency of the output signal of the phase-locked loop by selected numerical constants, and (ii) generates an output signal of the clock signal generation circuit from one of the signals of various frequencies, wherein the various frequencies include both an integer submultiple and a fractional submultiple of the frequency of the output signal of the phase-locked loop, and wherein the fractional submultiple is not an integer submultiple.