Patent ID: 9583400
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A method for fabricating a gate stack of a semiconductor device, the method comprising: forming a first dielectric layer over a channel region of the device; forming a barrier layer over the first dielectric layer; forming a first gate metal layer over the barrier layer; forming a capping layer over the first gate metal layer; removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack; depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer; depositing a scavenging layer on the first nitride layer; depositing a second nitride layer on the scavenging layer; and depositing a gate electrode material on the second nitride layer.