Patent ID: 9590079
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device having a first, second, and third region on a substrate, comprising: disposing a first gate layer over a first dielectric on the substrate; disposing a cap layer over the first gate layer; forming a plurality of memory cells in the first region, comprising, etching through the cap layer and the first gate layer in the second region to define a first transistor gate having an initial thickness substantially equal to a thickness of the cap layer and the first gate layer; forming a third doped region in the substrate adjacent to the first transistor gate; removing the cap layer; etching through the first gate layer in the third region to define a second transistor gate having a thickness substantially equal to the thickness of the first gate layer; and forming a fourth doped region in the substrate adjacent to the second transistor gate, wherein the third doped region extends deeper in the substrate than the fourth doped region, and wherein a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.