Patent ID: 9659972
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A thin film transistor array panel comprising: a substrate; a gate electrode on the substrate; a semiconductor layer on the substrate; a gate insulating layer between the gate electrode and the semiconductor layer; an etching stopper on the semiconductor layer; a source electrode and a drain electrode facing the source electrode on the substrate; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, wherein the etching stopper has a first contact hole and a second contact hole, wherein the first contact hole and the second contact hole have complementary shapes such that a combination of the first and second contact holes along a direction in which the first and second contact holes face each other on the same plane has a substantially quadrangular shape in a plan view, wherein the etching stopper comprises an etching prevention portion between the source electrode and the drain electrode, wherein a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plan view, and wherein a width of a channel portion of the semiconductor layer is greater than the shortest distance A.