Patent ID: 9735270
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. An apparatus, comprising: a substrate, the substrate comprising silicon, wherein the substrate lacks a buried insulator layer; a p-type transistor, the p-type transistor comprising: a first source region at least partially in a first recess in the substrate, at least a portion of the first source region comprising epitaxial silicon and germanium with a first lattice spacing; a first drain region at least partially in a second recess in the substrate, at least a portion of the first drain region comprising epitaxial silicon and germanium with the first lattice spacing; a third region in the substrate between the first source region and the first drain region, at least a portion of the third region comprising silicon having a second lattice spacing smaller than the first lattice spacing; a first gate dielectric region above the third region, the first gate dielectric region having a thickness between about 5 Angstroms and 30 Angstroms; and a first gate electrode above the first gate dielectric region; and an n-type transistor, the n-type transistor comprising: a second source region, the second source region being at least substantially free from germanium, the second source region having a third lattice spacing smaller than the first lattice spacing; a second drain region, the second drain region being at least substantially free from germanium, the second drain region having the third lattice spacing; a fourth region in the substrate between the second source region and the second drain region, at least a portion of the fourth region comprising silicon with the second lattice spacing; a second gate dielectric region above the fourth region; and a second gate electrode above the second gate dielectric region.