Patent ID: 9748304
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer comprising a substrate and an interconnect structure coupled to the substrate, a bottommost surface of the interconnect structure not extending below a topmost surface of the substrate, the interconnect structure comprising a plurality of insulating layers and a plurality of conductive layers, a conductive layer in a first portion of the interconnect structure being a contact pad of the interconnect structure, the contact pad contacting the topmost surface of the substrate, the contact pad having a first surface coplanar with the bottommost surface of the interconnect structure; and removing a first portion of the substrate from the first semiconductor wafer to expose the first surface of the contact pad in the first portion of the interconnect structure; and removing a second portion of the substrate from the first semiconductor wafer over a scribe line region to expose a second portion of the interconnect structure.