Patent ID: 9607680
Date: 2017-03-28
CPC Classifications: G11C,H01L

Claim:
1. A system comprising a plurality of integrated circuits, wherein at least a first integrated circuit of the plurality of integrated circuits is manufactured using a dynamic random access memory (DRAM) fabrication process, and wherein the first integrated circuit comprises: a plurality of capacitors, wherein the plurality of capacitors provide decoupling capacitance for a plurality of components implemented on the first integrated circuit, wherein the plurality of capacitors comprises a first subset of capacitors including at least two capacitors connected in series between a power supply conductor and a ground conductor and a second subset of capacitors including only single capacitors connected between the power supply conductor and the ground conductor, and wherein the plurality of components comprise logic circuits coupled to the power supply conductor and the ground conductor, and wherein the first subset provides decoupling capacitance for a first component that experiences first transient current density during use, and wherein the second subset provides decoupling capacitance for a second component that experiences second transient current density during use, and wherein the second transient current density is greater than the first transient current density; a plurality of power management units integrated into the first integrated circuit, wherein the plurality of power management units configured to provide a power supply on the power supply conductor to respective ones of the plurality of components; and one or more of the plurality of capacitors is connected in series with a switch, wherein the series connection is between the power supply conductor and the ground conductor, and wherein the switch is open, during use, in response to a defect in a corresponding capacitor of the one or more of the plurality of capacitors.