Patent ID: 9548086
Date: 2017-01-17
CPC Classifications: G05F,G06F,G11C,H01L,H02M,H03K

Claim:
1. A system, comprising: a plurality of blocks, each block comprising a different integrated circuit function and each including transistors formed therein; a bias circuit corresponding to each block and configured to receive a control value unique to the block, each bias circuit configured to generate a local body bias voltage for transistors of its block in response to the control value of the block; a collapse circuit corresponding to each block, each collapse circuit configured to couple the bodies of its transistors to a collapse voltage that tracks a power supply voltage, in response to at least one collapse enable signal for the block; and an event detect circuit corresponding to each block, each event detect circuit configured to activate the collapse enable signal of its block in response to at least one local event signal and in response to at least one global event signal; wherein the at least one local event signal is generated in the corresponding block and the at least one global event signal is generated outside of the block in response to at least one predetermined event; the blocks include a processor circuit block comprising at least one processor, a static or dynamic RAM block, and analog circuit block; and the local body bias voltage for transistors of the processor block and the local body bias voltage for transistors of the memory are generated independently.