Patent ID: 9553568
Date: 2017-01-24
CPC Classifications: G06G,H03B,H03K

Claim:
1. A frequency multiplier comprising: an input terminal; an output terminal; a first transistor having a first gate to which a radio frequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source; a second transistor having a second gate, a second source to which the radio frequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal; and a stabilizing resistor whose one end is connected to the second gate and whose other end is connected to a grounding metal directly or via a capacitor wherein no resistor exists in the path for the radio frequency signal, and wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.