Patent ID: 9647669
Date: 2017-05-09
CPC Classifications: H03K

Claim:
1. A frequency divider circuit, comprising: an integer number M delay circuits, M being a positive even integer number greater than or equal to 4, the individual delay circuits including: a coupling circuit to couple an integer number N of the delay circuits in a cascade ring configuration with individual ones of the M delay circuits coupled to receive a differential input signal from a preceding delay circuit and to provide a differential output signal to a succeeding delay circuit in the cascade ring configuration to implement a divide-by-N frequency divider, N being a positive even integer number less than or equal to M, the coupling circuit operative to couple the differential output signal of an integer number N−K of the N delay circuits to its succeeding delay circuit with a reverse polarity, and to couple the differential output signals of the remaining K delay circuits in the cascade ring configuration to their respective succeeding delay circuits with no polarity reversal, where 1≦K<N.