Patent ID: 9741624
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of forming an integrated circuit, comprising the steps of: providing a semiconductor substrate; forming a plurality of PMOS gate structures disposed proximate to each other; forming a plurality of NMOS gate structures disposed proximate to each other; forming source/drain spacers on lateral surfaces of gate offset spacers of said PMOS gate structures; forming source/drain spacers on lateral surfaces of gate offset spacers of said NMOS gate structures; removing said source/drain spacers from said PMOS gate structures and said source/drain spacers from said NMOS gate structures; after removing the source/drain spacers, forming a spacer layer over the PMOS gate structures and the NMOS gate structures; performing an anisotropic reactive ion etch (RIE) process which removes said spacer layer from top surfaces of said PMOS gate structures and said NMOS gate structures, leaving said spacer layer on lateral surfaces of said PMOS gate structures and said NMOS gate structures so as to form sloped spacers which have a height of ¼ to ¾ of a height of said PMOS gate structures and said NMOS gate structures; forming an etch stop layer over said PMOS gate structures and said sloped spacers, said etch stop layer comprising silicon nitride; and forming a PMD layer over said etch stop layer.