Patent ID: 9715920
Date: 2017-07-25
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a first wiring; a second wiring; a memory cell; and a first circuit, wherein the memory cell comprises a first transistor and a first capacitor, wherein the first transistor is configured to control a conduction state between the first wiring and a first terminal of the first capacitor, wherein the first circuit comprises a second transistor and a second capacitor, wherein the second transistor is configured to control a conduction state between the second wiring and a first terminal of the second capacitor, wherein the first circuit is configured to determine whether a first potential of the first terminal of the second capacitor is lower than a second potential, to generate a first signal and a second signal when the first potential is determined to be lower than the second potential, to turn on the second transistor in response to the second signal, and to apply a third potential to the second wiring in response to the second signal, and wherein the first signal is configured to start a refresh operation of the memory cell.