Patent ID: 9703593
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. A memory overlay apparatus comprising: an internal memory comprising a dirty bit, which is updated in response to data of a first task being changed to indicate a changed memory area; a memory management unit configured to control an external memory to selectively store the changed data of the first task; and a direct memory access (DMA) management unit configured to check the dirty bit and to move the changed data of the first task corresponding to the dirty bit between the internal memory and the external memory, in response to a context switch, wherein the DMA management unit is further configured to store a task stack area of the first task from the internal memory to the external memory wherein the task stack area of the first task comprises a memory area from an address indicated by a stack pointer register of the first task to a lowermost address to which the dirty bit is set in a stack area, wherein the DMA management unit is further configured to restore a task stack area of a second task from the external memory to the internal memory, and wherein the task stack area of the second task comprises an area from an address indicated by a stack pointer register of the second task to an address of a bottom of the stack area.