Patent ID: 9673301
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method of forming a spacer for a FinFET device, comprising: forming a layer of spacer material above a gate structure and above a fin; forming a liner layer above said layer of spacer material, said liner layer having a first portion positioned around said gate structure and a second portion positioned around said fin: forming an ion-containing region in at least a portion of said first portion of said liner layer while not forming said ion-containing region in said second portion of said liner layer; performing a liner etching process on said first and second portions of said liner layer so as to remove said second portion of said liner layer while leaving at least a portion of said first portion of said liner layer positioned adjacent said gate structure; and with said first portion of said liner layer positioned adjacent said gate structure, performing at least one spacer formation anisotropic etching process on said layer of spacer material so as to define a spacer adjacent said gate structure.