Patent ID: 9646656
Date: 2017-05-09
CPC Classifications: G11C

Claim:
1. A method for receiving commands and addresses associated with multiple memory access requests from a memory controller, the method comprising: receiving, at a dynamic random access memory (DRAM) device, a stream of addresses and commands over a single connection, wherein the stream is received from the memory controller over a period of time that is divided into a plurality of time slots, wherein the plurality of time slots follows a predetermined pattern set by the memory controller that allocates time slots across a first port of the DRAM device and a second port of the DRAM device; determining that the stream includes a first address and a first command within a first time slot that is included in the plurality of time slots and is associated with the first port of the DRAM device that is associated with a first data connection over which a first portion of the DRAM device is accessed; transmitting the first address and the first command to the first port of the DRAM device; determining that the stream includes a second address and a second command within a second time slot that is included in the plurality of time slots and is associated with the second port of the DRAM device that is associated with a second data connection over which a second portion of the DRAM device is accessed; and transmitting the second address and the second command to the second port of the DRAM device.