Patent ID: 9634662
Date: 2017-04-25
CPC Classifications: H03K

Claim:
1. A pull-up resistor circuit for an IC, comprising: a voltage source for providing a source voltage to supply-power; a voltage output for providing an output voltage for an input/output (I/O) port of the IC; a first PMOS transistor and a second PMOS transistor connected in serial to provide a pull-up resistance, wherein the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode when the source voltage is higher than the output voltage; and a control signal generator for generating a second control signal coupled to the second PMOS transistor to control a bias voltage connected to a substrate of the second PMOS transistor and a substrate of the first PMOS transistor to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode regardless of a logic level of the first control signal when the output voltage is higher than the source voltage, a value of the bias voltage being a greater of the source voltage and the output voltage, wherein: the control signal generator includes a first switch unit including a third PMOS transistor having a width-to-length ratio related to an impedance of the first switch unit, and a second switch unit including a fourth PMOS transistor and a first NMOS transistor, a gate of the fourth PMOS transistor is connected to a drain of the fourth PMOS transistor and connected to a drain of the first NMOS transistor, a source of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, a turn-on impedance of the second switch unit being higher than a turn-on impedance of the first switch unit, a gate of the first NMOS transistor is inputted with a third control signal and a signal level of the third control signal is always opposite to a signal level of the first control signal.