Patent ID: 9653127
Date: 2017-05-16
CPC Classifications: G11C

Claim:
1. An apparatus comprising: a first memory access line; a second memory access line; a memory cell coupled to the first memory access line and to the second memory access line, wherein the memory cell is configured to have a threshold voltage; memory access circuits coupled to the first and second memory access lines and configured to provide a respective voltage to the first and second memory access lines; and a control logic circuit coupled to the memory access circuits and configured to provide control signals to memory access circuits to apply a first pre-bias voltage across the memory cell by the first and second memory access lines and to further apply thereafter a second pre-bias voltage across the memory cell by the first and second memory access lines, wherein the second pre-bias voltage has a greater magnitude than the first pre-bias voltage, the first and second pre-bias voltages are below the threshold voltage, and wherein a ratio of the second pre-bias voltage and the threshold voltage are above a threshold value.