Patent ID: 9553586
Date: 2017-01-24
CPC Classifications: H01L,H03K

Claim:
1. A field programmable gate array device, comprising: a front-end-of-line portion comprising a plurality of logic blocks; a back-end-of-line portion comprising a plurality of metallization layers; and programmable interconnect points configured to define signal routing between the logic blocks and/or between other portions of the field programmable gate array device, wherein the interconnect points comprise one or more pass transistors, wherein each pass transistor is equipped with a dynamic random access memory cell, the dynamic random access memory cell comprising a select transistor connected to a select line and to a data line, and wherein the select transistor and/or the pass transistor is located in the back-end-of-line portion of the field programmable gate array device; wherein both the pass transistor and the select transistor are located in the back-end-of-line portion of the field programmable gate array device.