Patent ID: 9570402
Date: 2017-02-14
CPC Classifications: G03F,H01L

Claim:
1. An alignment key of a semiconductor device, comprising: material layers including a plurality of layers stacked on each other and formed over a semiconductor substrate; a first dummy hole and a second dummy hole passing through the material layers, wherein a width of the second dummy hole is less than of the first dummy hole; a first channel insulation layer formed inside the first dummy hole, wherein a height of an upper surface of the first channel insulation layer measured from a bottom of the first dummy hole is less than that of the first dummy hole; a second channel insulation layer formed inside the second dummy hole, wherein a height of an upper surface of the second channel insulation layer measured from a bottom of the second dummy hole is between those of the second dummy hole and the first channel insulation layer; a first capping layer formed along a side wall of an upper portion of the first dummy hole and an upper surface of the first channel insulation layer; and a second capping layer formed along a side wall of an upper portion of the second dummy hole and an upper surface of the second channel insulation layer, wherein the first capping layer formed on the upper portion of the first dummy hole is formed in a U-shape manner so that the upper portion of the first dummy hole is not completely embedded, and the second capping layer formed on the upper portion of the second dummy hole is formed in a U-shape manner so that the upper portion of the second dummy hole is completely embedded.