Patent ID: 9543320
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A method of manufacturing a three-dimensional memory structure, comprising: forming a stack of alternating layers comprising first material layers and second material layers over a substrate; forming a temporary material layer over the stack; wherein the temporary material layer has a different composition than the first material layers and second material layers; forming a memory opening through the temporary material layer and the stack; forming a memory film and a semiconductor channel in the memory opening; forming a first backside recess by removing the temporary material layer and a portion of the memory film that adjoins the temporary material layer, wherein a portion of a sidewall of the semiconductor channel is physically exposed to the first backside recess; and introducing electrical dopants through the physically exposed portion of the sidewall of the semiconductor channel and into a portion of the semiconductor channel, which is converted into a drain region.