Patent ID: 9697122
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A data processing device comprising: a plurality of data processing stages, each of which includes at least one processing element, at least one stage memory, and an event controller; and an inter-stage bus that connects between the plurality of data processing stages, and is a data write only bus, wherein the processing element in one data processing stage is connected to the stage memory in the one data processing stage via a data read only bus, wherein the processing element is connected to the inter-stage bus via a second data write only bus, wherein an external event generated at an external device and a process completion event from the processing element are input into the event controller, wherein the event controller in the one data processing stage generates a task start event with respect to the processing element in the one data processing stage according to each of the external event and the process completion event, wherein each of the plurality of data processing stages is connected to the inter-stage bus via an access point, wherein the access point includes an access table, wherein the access point stores a data write history in the access table when the processing element writes data in the stage memory in a memory access process, wherein the processing element executes an event access process indicative of a completion of the memory access process after the processing element completes to execute the memory access process to the stage memory via the access point, and wherein the access point executes another event access process for inputting the process completion event into the event controller of a data processing stage including the stage memory, in which the processing element writes data in the memory access process, based on the data write history stored in the access table when the processing element executes the event access process.