Patent ID: 9633708
Date: 2017-04-25
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a plurality of memory cells, each comprising a first MOSFET and a first MTJ serially connected thereto, arranged between one of a pair of bit lines and one of a pair of source lines, a second MOSFET and a second MTJ serially connected thereto, arranged between other of the pair of bit lines and other of the pair of source lines; a third MOSFET; and a fourth MOSFET; wherein the drain of the third MOSFET is connected to one of the pair of bit lines, the drain of the fourth MOSFET is connected to the other of the pair of bit lines, the gate of the third MOSFET is connected to the drain of the fourth MOSFET and the gate of the fourth MOSFET is connected to the drain of the third MOSFET.