Patent ID: 9619415
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. An information handling system comprising: a first processor core; a first input/output (I/O) module coupled to the first processor core via a first direct media interface; and a service processor coupled to the first I/O module via a multi-master interface; wherein the first processor core sends a first low pin count (LPC) transaction for the service processor via the first direct media interface and the multi-master interface, such that the first LPC transaction is not transmitted via an LPC bus; wherein the first LPC transaction is intercepted by a first I/O trap of the first I/O module; wherein the first I/O module is operable to generate a first system management interrupt in response to the first LPC transaction being intercepted by the first I/O trap; wherein the first system management interrupt is received by a first system management interrupt handler of the first processor core; and the first system management interrupt handler redirects the first transaction to the first direct media interface.