Patent ID: 9620288
Date: 2017-04-11
CPC Classifications: H01G

Claim:
1. A chip-component structure comprising: a multilayer capacitor including a laminated body including a plurality of dielectric layers and a plurality of internal electrodes stacked on each other, and a pair of external electrodes provided on a side surface of the laminated body and electrically connected to the internal electrodes; and an interposer including a substantially flat plate-shaped substrate, a pair of component connecting electrodes provided on a component mounting surface defining one principal surface of the substrate and joined to a respective one of the pair of external electrodes, a pair of external connection electrodes provided on a mount surface defining the other principal surface of the substrate, and a side electrode provided on a side surface of the substrate intersecting the component mounting surface and the mount surface to electrically connect a respective one of the pair of component connecting electrodes and a respective one of the pair of external connection electrodes; wherein the substrate includes a communicating portion that communicates between a space on the mount surface and a space between the component mounting surface and the multilayer capacitor; the communicating portion is defined by at least one open hole having a circular or substantially circular shape; all portions of the laminated body of the multilayer capacitor are disposed outside of the communicating portion; and the communicating portion is located between the pair of external electrodes when the multilayer capacitor and the interposer are viewed in a direction perpendicular to the principal surfaces of the substrate.