Patent ID: 9741694
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor structure comprising: providing a first semiconductor workpiece; bonding a second semiconductor workpiece to a first surface of the first semiconductor workpiece, wherein the second semiconductor workpiece includes two adjacent semiconductor dies with a gap arranged there-between; filing the gap with a dielectric material; forming an opening through the dielectric material between the adjacent semiconductor dies and into the first semiconductor workpiece; filling the opening with conductive material to form a first electrically conductive via extended into and electrically connected to the first semiconductor workpiece; bonding a third semiconductor workpiece to a second surface of the first semiconductor workpiece, the second surface being opposite to the first surface; and forming a second electrically conductive via extended into the first semiconductor workpiece and substantially aligned with the first electrically conductive via such that the first electrically conductive via connects the second electrically conductive via.