Patent ID: 9680742
Date: 2017-06-13
CPC Classifications: H04L

Claim:
1. A circuit for managing transmittal of packets, the circuit comprising: a packet descriptor manager (PDM) circuit module configured to generate a metapacket and a descriptor from a command signal, the command signal identifying a packet to be transmitted by the circuit, the metapacket including an entry stating a size of the packet; a packet scheduling engine (PSE) circuit module configured to determine an order in which to transmit the packet among a plurality of packets, the PSE determining whether to select the packet as a next packet in the order based on a time at which the metapacket is advanced from a modeled endpoint node, the time being a function of the size and a destination across a network of the packet indicated in the metapacket; and a packet engines and buffering module (PEB) circuit module configured to perform processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor, the PEB causing the processed packet to be transmitted toward the destination.