Patent ID: 9570177
Date: 2017-02-14
CPC Classifications: G06F,G11C

Claim:
1. A memory system comprising: a memory device including a plurality of memory blocks, each including a plurality of pages, wherein the plurality of pages each includes a plurality of memory cells electrically coupled to a plurality of word lines and store write data and provide read data which are requested from a host; and a controller checking a bad page among a plurality of pages in a first memory block of the memory blocks, programming dummy data in the bad page, and processing the first memory block as a normal block, wherein the controller determines a first page which is electrically coupled to the bad word line and a second page which is electrically coupled to a word line adjacent to the bad word line, among the plurality of pages in the first memory block, as bad pages, wherein the plurality of word lines include the first to Lth word lines, wherein the bad word line corresponds to a Kth word line, the word lines adjacent to the bad word line correspond to the (K−1)th word line and the (K+1)th word line, and the (K−2)th word line and the (K+2)th word line are good word lines, where K is greater than or equal to 1 and is less than or equal to L.