Patent ID: 9627520
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. An MOS transistor, comprising: a cell array with a plurality of trenches in a semiconductor body, each trench including a field electrode and a field electrode dielectric, the cell array including an edge region, wherein the edge region of the cell array includes both at least an outermost trench of the cell array and a trench of the cell array adjacent to the outermost trench; at least one cell array edge zone, the at least one cell array edge zone arranged only in the edge region of the cell array at least partially below and having an interface with at least one trench in the edge region of the cell array, wherein the cell array edge zone is spaced apart from a first side of the semiconductor body; and a plurality of transistor cells in the cell array, each transistor cell comprising a source zone, a drift zone, a body zone arranged between the source zone and the drift zone and adjoining the drift zone, a drain zone spaced apart from the body zone in a direction of a second side opposite the first side of the semiconductor body, and a gate electrode insulated from the body zone by a gate dielectric, wherein the drift zone has a first conductivity type, and the body zone and the cell array edge zone have a second conductivity type complementary to the first conductivity type, wherein the body zone is electrically connected to a source electrode, and wherein the drain zone is spaced apart from the plurality of trenches of the cell array in the direction of the second side.