Patent ID: 9535608
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. A computer-implemented method comprising: identifying two or more memory locations, wherein said two or more memory locations are not contiguous; referencing, by a memory access request, said two or more memory locations; sending said memory access request from one or more processors to a node, said memory access request comprising a single action pursuant to a memory protocol; fetching, by said node, data content from each of said two or more memory locations, wherein said node is of at least one type selected from the group consisting of: one or more additional processors, a memory controller, and a cache controller; packaging, by said node, said data content from each of said two or more memory locations into a memory package; returning said memory package from said node to said one or more processors; initiating a transaction in a transactional memory environment, wherein said two or more memory locations are used in said transaction; and wherein referencing, by the memory access request, said two or more memory locations comprises: