Patent ID: 9564336
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method of manufacturing a NOR Flash device, comprising: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; cleaning a gas pipeline containing CO connected to an etching cavity thereby preventing impurity source of Ni attached to the gas pipeline containing CO from being injected from the gas pipeline during etching the first hard mask layer; etching the first hard mask layer using CF forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer covers a bottom and a side wall of the first opening, the side wall of the first opening being an etched side surface of the first hard mask layer; etching the second hard mask layer to form a second opening using a self-aligning process, wherein a width of the second opening is smaller than a width of the first opening; and etching the first polycrystalline silicon layer to form a floating gate using the self-aligning process, wherein a width of an etched portion of the first polycrystalline silicon layer corresponds to the width of the second opening.