Patent ID: 9659632
Date: 2017-05-23
CPC Classifications: G11C,H01L

Claim:
1. A static random access memory (SRAM), comprising: a plurality of bit cells, each comprising: wherein the plurality of bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each one of the plurality of bottom tier cells is disposed under a corresponding one of the plurality of top tier cells, wherein the first inverter of each one of the top tier cells is disposed over the second inverter of a corresponding bottom tier cell, and the second inverter of the top tier cell is disposed over the first inverter of the corresponding bottom tier cell; and wherein drains of the transistors of each top tier cell of the plurality of top tier cells are disposed on a first layer of the substrate, gates of the transistors of the top tier cell are disposed on a second layer under the first layer of the substrate, sources of the transistors of the top tier cell and sources of the transistors of the corresponding bottom tier cell are disposed on a third layer under the second layer of the substrate, gates of the transistors of the corresponding bottom tier cell are disposed on a fourth layer under the third layer of the substrate, and drains of the transistors of the corresponding bottom tier cell are disposed on a fifth layer under the fourth layer of the substrate.