Patent ID: 9715922
Date: 2017-07-25
CPC Classifications: G11C

Claim:
1. A single port SRAM memory cell driven by two word lines in an asynchronous manner, wherein a plurality of the single port SRAM memory cells form a memory matrix disposed in a memory, the memory has a hold mode, a read mode and a write mode, the memory comprises a first word line, a second word line and a bit line, the single port SRAM memory cell receives a first turn-on signal transmitted by the first word line, a second turn-on signal transmitted by the second word line and write data transmitted by the bit line, and the second turn-on signal has a delay with respect to the first turn-on signal when the memory is in the write mode, the single port SRAM memory cell comprises: a first write switch, electrically connected to the first word line, wherein when the memory is in the read mode or the write mode, the first write switch is turned on by the first turn-on signal and transmits the write data transmitted from the bit line; a second write switch, electrically connected to the second word line, wherein when the memory is in the hold mode, the second write switch is turned on by the second turn-on signal, wherein when the memory is in the write mode, the second write switch is turned on by the second turn-on signal having the delay with respect to the first turn-on signal and transmits the write data derived from the bit line; and a latch, electrically connected to the first write switch and the second write switch, wherein when the memory is in the write mode and both of the first write switch and the second write switch are turned on, the latch is configured to receive and store the write data; wherein the first write switch comprises a first transistor, the second write switch comprises a second transistor, and the latch comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein the first, second, fourth and sixth transistors are N-type transistors, and the third and fifth transistors are P-type transistors, wherein each one of the first, second, third, fourth, fifth and sixth transistors has a first source/drain, a second source/drain and a gate, wherein the gate of the first transistor is electrically connected to the first word line, the first source/drain of the first transistor is electrically connected to the bit line, the second source/drain of the first transistor is electrically connected to the first source/drain of the second transistor, the second source/drain of the third transistor and the first source/drain of the fourth transistor, the gate of the second transistor is electrically connected to the second word line, the second source/drain of the second transistor is electrically connected to the gates of the fifth and sixth transistors, the gate of the third transistor is electrically connected to the gate of the fourth transistor, the second source/drain of the fifth transistor and the first source/drain of the sixth transistor, the first source/drain of the third transistor is electrically connected to a source voltage, the second source/drain of the fourth transistor is electrically connected to a reference voltage, the first source/drain of the fifth transistor is electrically connected to the source voltage, and the second source/drain of the sixth transistor is electrically connected to the reference voltage.