Patent ID: 9595942
Date: 2017-03-14
CPC Classifications: G05F,H01L,H03H

Claim:
1. A capacitor structure comprising: a substrate; a plurality of source/drain regions formed in said substrate to form an active area, the active area having an active area width; a first plurality of gates formed above said substrate, each gate of said first plurality of gates having a first gate width, said first gate width configured to be less than said active area width, each gate of said first plurality of gates formed between a pair of source/drain regions of said plurality of source/drain regions; and a second plurality of gates formed above said substrate, each gate of said second plurality of gates having a second gate width, said second gate width configured to be less than said active area width, each gate of said second plurality of gates formed between a pair of source/drain regions of said plurality of source drain regions such that said first plurality of gates interleave with said second plurality of gates.