Patent ID: 9640475
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A chip packaging structure, comprising: a chip, comprising an integrated circuit, a plurality of first bonding pads, at least two second bonding pads, and at least two connecting pads, the first bonding pads, the at least two second bonding pads and the at least two connecting pads being disposed above the integrated circuit, the at least two second bonding pads and the at least two connecting pads being separated from the integrated circuit, wherein, the at least two second bonding pads are respectively electrically connected to one of the at least two connecting pads; at least one passive component, disposed on the chip, comprising two electrodes respectively electrically connected to and adhered to one of the at least two connecting pads; and at least two first metal lines, disposed on the chip, each of the at least two first metal lines having one end electrically connected to one of the at least two second bonding pads, and one other end connected to one of the first bonding pads.