Patent ID: 9595500
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor chip having a switching element and a plurality of pads (P) electrically connected to the switching element; and a plurality of lead terminals being electrically connected to the respective pads, wherein the plurality of lead terminals includes a control terminal used for control of on/off operation of the switching element, and a main terminal into which a current flows when the switching element is in an on state, the control terminal includes a first terminal and a second terminal between which a control current flows through the semiconductor chip when the switching element is in the on state, the main terminal includes a third terminal and a fourth terminal between which a main current flows through the semiconductor chip when the switching element is in the on state, and a coupling coefficient k satisfies −3%≦k≦2%, when k is defined by where Lg is a parasitic inductance in a current path of the control current, Lo is a parasitic inductance in a current path of the main current, and Ms is a mutual inductance of the parasitic inductance Lg and the parasitic inductance Lo.