Patent ID: 9740496
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A processor, comprising: a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries that include both single instructions and a set of instructions of a trace, each entry of the plurality of entries corresponding with a computation instruction and including values of operands of the computation instruction and an output of the computation instruction, and, based on the computation instruction being one of the set of instructions of the trace, an indication of a subsequent instruction in the trace, wherein based on the computation instruction being one of the set of instructions of the trace, in at least one of the plurality of entries, the values of the operands include the output of a previous computation instruction that is a previous instruction of the set of instructions of the trace; and a functional unit configured to perform a computation based on a corresponding instruction.