Patent ID: 9564532
Date: 2017-02-07
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a substrate including a pixel region; a gate line on the substrate; a gate electrode on the substrate and connected to the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode, wherein a top layer of the source and drain electrodes includes copper or copper alloy and a bottom layer of the source and drain electrodes includes molybdenum or molybdenum-titanium alloy; an adhesion enhancing layer formed on the top layer of the source and drain electrodes; and an oxide semiconductor layer formed on the adhesion enhancing layer and the gate insulating layer disposed between the source and drain electrodes, wherein the adhesion enhancing layer is a copper-nitride layer, directly contacts both the oxide semiconductor layer and the source and drain electrodes, and is positioned between the substrate and the oxide semiconductor layer.