Patent ID: 9545003
Date: 2017-01-10
CPC Classifications: H05K

Claim:
1. A printed circuit board comprising: a first electrically conductive layer that includes a first electrically conductive region and a first antipad defined by the first electrically conductive region, the first antipad including a first dielectric region and a portion of a first electrically plated via that extends through the first dielectric region along a first direction, the first antipad having a first maximum area along a first plane that is normal to the first direction, wherein the first dielectric region is aligned with the first electrically conductive region along the first plane; a first dielectric layer disposed below the first electrically conductive layer along the first direction; a second electrically conductive layer disposed below the first dielectric layer along the first direction, the second electrically conductive layer including a second electrically conductive region and a second antipad defined by the second electrically conductive region, the second antipad having a second maximum area along a second plane that is normal to the first direction, the second maximum area less than the first maximum area; a third electrically conductive layer disposed below the second electrically conductive layer along the first direction such that no additional electrically conductive layer is disposed between the second electrically conductive layer and the third electrically conductive layer along the first direction, the third electrically conductive layer defining a third electrically conductive region and a third antipad, the third antipad having a third maximum area along a third plane that is normal to the first direction, the third maximum area substantially equal to the second maximum area; and an electrically conductive signal layer that includes one or more electrically conductive traces electrically coupled to the first electrically plated via, the electrically conductive signal layer being the only signal layer disposed between the first electrically conductive layer and the second electrically conductive layer along the first direction, wherein at least a portion of each of the second antipad and the third antipad is aligned with the portion of the first electrically plated via along the first direction.