Patent ID: 9590057
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device, the method comprising: providing a first conductor on a substrate, the first conductor having a first top surface with a first height above the substrate; providing a thin layer of metal silicide adjacent to the first conductor; providing a second conductor adjacent in direct contact with the metal silicide, the second conductor having a second top surface with a second height above the substrate and a bottom surface that interacts directly with the first top surface of the metal silicide; removing a portion of the second conductor to provide a slot therethrough, wherein the slot is defined by opposing interior sidewalls and a bottom portion, such that the bottom portion of the slot is below the first height of the first conductor and reaches the metal silicide; depositing an insulating material in the slot on top of the thin layer of metal silicide, the insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide space within the slot for a third conductor, wherein the insulating material is silicon oxide, and wherein the third conductor is a contact metal selected from a group comprising: tungsten, copper, and aluminum; filling the space within the slot with the third conductor having a fourth top surface with a fourth height above the substrate, the fourth height being equal to the second height of the second conductor without the use of lithography; and reducing parasitic capacitance in the semiconductor device, wherein parasitic capacitance is reduced by removing the portion of the second conductor and depositing the insulating material in the slot and filling the space within the slow with the third conductor.