Patent ID: 9565766
Date: 2017-02-07
CPC Classifications: H01L,H05K

Claim:
1. An integrated circuit device, comprising: a substrate having at least a portion of a dynamic random access memory (DRAM) bit cell circuitry; an interconnect layer on the substrate defining a plurality of interconnect feature spaces, each interconnect feature space of the plurality of interconnect feature spaces having a cross-sectional scale and cross-sectional shape that includes sidewalls and a bottom that is closer to the substrate than the sidewalls; one or more metal-containing interconnect features, each occupying a corresponding interconnect feature space of a first set of interconnect feature spaces of the plurality of interconnect feature spaces; and one or more capacitor features, each occupying a corresponding interconnect feature space of a second set of interconnect features spaces of the plurality of interconnect feature spaces, each of which also has the cross-sectional scale and the cross-sectional shape, each capacitor feature comprising: