Patent ID: 9627408
Date: 2017-04-18
CPC Classifications: G06F,H01L

Claim:
1. A D flip-flop cell, implemented in a double-height standard cell form, said flip-flop comprising: three rectangular power rails, including a top rail, middle rail, and bottom rail, each of the rails formed in a first metal (M0) layer, each of the rails extending uncut, horizontally across the entire cell, each of the rails having a vertical width at least twice a minimum permitted width for M0 patterning; a plurality of at least ten parallel, evenly-spaced, minimum width gate stripes, each formed in a gate (PC) layer, and each extending vertically between the top and bottom rails, adjacent gate stripes separated by a center-to-center spacing CPP; positioned vertically between the top and middle rails, one or more first-exposure M0 track(s), each of the first-exposure M0 track(s) having the minimum permitted M0 width and extending horizontally across the cell, said first-exposure M0 track(s) patterned, in part, by portion(s) of a first-exposure M0 mask (M0_color1) and, in part, by portion(s) of a first-exposure M0 cut mask (M0CUT1); positioned vertically between the top and middle rails, one or more second-exposure M0 track(s), each of the second-exposure M0 track(s) having the minimum permitted M0 width and extending horizontally across the cell, said second-exposure M0 track(s) patterned, in part, by portion(s) of a second-exposure M0 mask (M0_color2) and, in part, by portion(s) of a second-exposure M0 cut mask (M0CUT2); positioned vertically between the bottom and middle rails, one or more first-exposure M0 track(s), each of the first-exposure M0 track(s) having the minimum permitted M0 width and extending horizontally across the cell, said first-exposure M0 track(s) patterned, in part, by portion(s) of the M0_color1 mask and, in part, by portion(s) of the M0CUT1 mask; positioned vertically between the bottom and middle rails, one or more second-exposure M0 track(s), each of the second-exposure M0 track(s) having the minimum permitted M0 width and extending horizontally across the cell, said second-exposure M0 track(s) patterned, in part, by portion(s) of the M0_color2 mask and, in part, by portion(s) of the M0CUT2 mask; a plurality of vias, patterned in a V0 (via to interconnect) layer, each of said plurality of vias instantiated on an M0 track; additional patterned features, in NW (N-well), TS (trench silicide), RX (active), CA (contact to active), GO (gate open), and M1 (first-level interconnect) layers, configured to realize the D flip-flop logical behavior of the cell; characterized in that: