Patent ID: 9685451
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A nonvolatile memory device, comprising: cell strings, each including a plurality of memory cells over a substrate, wherein the plurality of memory cells are connected electrically in series in a first direction parallel to an upper surface of the substrate; channel layers, connected electrically with a first junction region and a second junction region of the cell strings in the substrate, extending in a second direction perpendicular to the upper surface of the substrate, and formed of semiconductor substance, wherein each of the channel layers includes a top surface which is parallel to the upper surface of the substrate, a bottom surface which is parallel to the upper surface of the substrate and is positioned lower than the top surface, and a side surface which connects the top surface and the bottom surface with each other between the top surface and the bottom surface; select gate electrodes, located over the cell strings, surrounding the side surfaces of the channel layers with a gate dielectric layer interposed therebetween; and conductive lines connected electrically with the top surface of each of the channel layers, wherein the channel layer, the select gate electrode and the gate dielectric layer form a select transistor, wherein the first junction region is connected electrically with the channel layer through a drain contact plug which is conductive, and the second junction region is connected electrically with the channel layer through a source contact plug which is conductive, wherein each of the drain contact plug and the source contact plug has a lower portion and an upper portion located over the lower portion in the second direction, and a width of the upper portion is larger than a width of the lower portion, wherein the memory cells comprise stack structures each including a floating gate electrode, a charge blocking layer, and a control gate electrode sequentially stacked, and wherein the upper portion of each of the drain contact plug and the source contact plug is located over the stack structures in the second direction and covers in the second direction a top surface of at least one of the stack structures, the top surface of the at least one of the stack structures is parallel to the first direction, and the lower portion of each of the drain contact plug and the source contact plug is located under the upper portion in the second direction and between the stack structures of one of the cell strings and the stack structures of another one of the cell strings in the first direction and does not cover in the second direction the top surface of the at least one of the stack structures.