Patent ID: 9711658
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first pillar-shaped semiconductor layer; a first selection gate insulating film surrounding the first pillar-shaped semiconductor layer; a first selection gate surrounding the first selection gate insulating film; a first gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer; a first contact electrode surrounding the first gate insulating film; a first bit line electrically connected to an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the first contact electrode; a second pillar-shaped semiconductor layer; a layer including a first charge storage layer and surrounding the second pillar-shaped semiconductor layer; a first control gate surrounding the layer with the first charge storage layer; a layer including a second charge storage layer, surrounding the second pillar-shaped semiconductor layer, and formed above the first control gate; a second control gate surrounding the layer with the second charge storage layer; a second gate insulating film surrounding an upper portion of the second pillar-shaped semiconductor layer; a second contact electrode surrounding the second gate insulating film and having an upper portion electrically connected to an upper portion of the second pillar-shaped semiconductor layer; a first lower internal line that connects a lower portion of the first pillar-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer and extending in a first direction; a third pillar-shaped semiconductor layer; a layer including a third charge storage layer and surrounding the third pillar-shaped semiconductor layer; a third control gate surrounding the layer with the third charge storage layer; a layer including a fourth charge storage layer, surrounding the third pillar-shaped semiconductor layer, and formed above the third control gate; a fourth control gate surrounding the layer with the fourth charge storage layer; a third gate insulating film surrounding an upper portion of the third pillar-shaped semiconductor layer; a third contact electrode surrounding the third gate insulating film and having an upper portion electrically connected to an upper portion of the third pillar-shaped semiconductor layer; a fourth pillar-shaped semiconductor layer; a second selection gate insulating film surrounding the fourth pillar-shaped semiconductor layer; a second selection gate surrounding the second selection gate insulating film; a fourth gate insulating film surrounding an upper portion of the fourth pillar-shaped semiconductor layer; a fourth contact electrode surrounding the fourth gate insulating film; a first source line electrically connected to an upper portion of the fourth pillar-shaped semiconductor layer and the fourth contact electrode; and a second lower internal line that connects a lower portion of the third pillar-shaped semiconductor layer and a lower portion of the fourth pillar-shaped semiconductor layer and extending in the first direction.