Patent ID: 9620390
Date: 2017-04-11
CPC Classifications: B81B,B81C,H01L

Claim:
1. Capping substrate for a semiconductor device, comprising a passive integrated component which is an inductance comprising a metal core and a winding comprising a combination of a plurality of via structures ( 11 ), arranged in arrays and extending through a substrate, and metal strips ( 12 ) which connect the via structures pair-wise; wherein a first via located on one side of the metal core is coupled on the upper surface by at least one metal strip to an opposing via on the opposite side of the metal core and wherein said opposing via is interconnected on a bottom surface of the substrate by at least one metal strip with a second via adjacent to the first via, such that there is essentiallya continuous formation extending between and coupling the vias, thereby producing a conductor around the metal core; wherein said via structures are coaxial metal through connections comprising at least one insulated metal through connection extending through the substrate; at least one annular metal structure circumferentially surrounding said insulated metal through connection, and located at a finite radial distance therefrom.