Patent ID: 9601525
Date: 2017-03-21
CPC Classifications: G02F,H01L

Claim:
1. A semiconductor device comprising: first, second, third and fourth transistors, a capacitor and an orientation layer; wherein the first, second, third and fourth transistors are the same conductivity type, wherein a first electrode of the capacitor is electrically connected to a gate of the first transistor, wherein the first electrode of the capacitor is electrically connected to a gate of the fourth transistor, wherein the first electrode of the capacitor is electrically connected to one of source and drain of the third transistor, wherein a second electrode of the capacitor is electrically connected to one of source and drain of the fourth transistor, wherein a gate of the second transistor is electrically connected to a first signal input terminal, wherein one of source and drain of the first transistor is electrically connected to a signal output terminal, wherein the one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor, wherein the one of source and drain of the first transistor is electrically connected to the other of source and drain of the third transistor, wherein the other of source and drain of the second transistor is electrically connected to a first power supply line, wherein the orientation layer includes a first region, and wherein the first region and a channel formation region of at least one of the first, the second, the third and the fourth transistors overlap each other.