Patent ID: 9569296
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A system comprising: multiple transmitters each having a pseudorandom binary sequence (PRBS) generator for providing a training pattern, and a selection logic for selecting either the training pattern during a training phase or regular data and passing the selection onto a plurality of serial multi-lanes; multiple receivers each having a synchronous capturing module for capturing multiple ones of the plurality of serial multi-lanes with data simultaneously, the captured data being used to calculate a PRBS distance or bit skew for each of the plurality of serial multi-lanes, where the PRBS distance with the largest latency is used as a reference to calculate a relative latency of each of the serial multi-lanes to other serial multi-lanes in the plurality of serial multi-lanes, the relative latency is used to calculate a number of shifts for at least one of a barrel shifter and word shifter in the receivers; and a bit shifter for each of the plurality of serial multi-lanes of at least one receiver, that shifts the number of data bits in a lane as a calculated relative latency to achieve alignment among each of the serial multi-lanes; wherein the transmitters and the receivers cooperate to provide bit alignment for one or more serial multi-lane asynchronous high speed data interfaces between the transmitters and receivers; wherein for the bit alignment between the receivers and the transmitters, two training patterns are provided, and represent two phases of alignment, one pattern being periodic pattern having a sequence length equal to parallel word width and another pattern being a PRBS pattern; and wherein each of the synchronous capturing modules comprise a PRBS shift register having a shift register length for capturing one or multiple parallel words simultaneously under control of capturing and shifting control logic, the number of words to capture depends on a PRBS shift register length to make sure that the captured length is no less than the shift register length, and a unique location in a bits PRBS sequence.