Patent ID: 9698051
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor chip, the method comprising: forming a plurality of through silicon vias (TSV) in a substrate that has a first surface and an opposed second surface; recessing the second surface of the substrate so that each TSV includes a protruding region that protrudes above the second surface of the substrate; forming a polymer buffer layer that covers the protruding regions of the TSVs; performing an exposure process using a phase shift mask (PSM) on the polymer buffer layer to form a polymer pattern layer that includes a completely-exposed region that is completely exposed to light during the exposure process so that the chemical properties of the completely exposed region are changed throughout the completely exposed region and a half-exposed region that is partially exposed to light during the exposure process so that the chemical properties of only a portion of the half exposed region are changed; performing a development process on the polymer pattern layer to remove portions of the polymer pattern layer whose chemical properties were changed during the exposure process; and forming a plated pad on the TSVs via an electroplating process after removing the upper portion of the polymer pattern layer so that the top surfaces of the TSVs are exposed through the polymer pattern layer, wherein an alignment mark is formed in the completely-exposed region of the polymer pattern layer.