Patent ID: 9542278
Date: 2017-01-10
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A data storage device, comprising: a flash memory, providing a storage space that is divided into a plurality of blocks with each block comprising a plurality of physical pages; and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory, wherein: the microcontroller is configured to build a physical-to-logical address mapping table in the random access memory for a run-time write block between the blocks of the flash memory; the microcontroller is further configured to allocate the random access memory to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table; and when recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller is further configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area.