Patent ID: 9638975
Date: 2017-05-02
CPC Classifications: G02F

Claim:
1. A method for manufacturing a color filter on array (COA) liquid crystal panel, comprising the following steps: (1) providing an array substrate and a glass substrate, wherein the array substrate comprises red, green, blue sub pixel zones, each of the sub pixel zones comprising a base plate, a gate terminal and a scan line arranged on the base plate, a gate insulation layer arranged on the gate terminal and covering the base plate, a semiconductor layer arranged on the gate insulation layer and corresponding to the gate terminal, source/drain terminals arranged on the gate insulation layer and respectively in connection with two ends of the semiconductor layer, a signal line arranged on the gate insulation layer and perpendicularly intersecting the scan line in a horizontal direction, and a passivation layer arranged on the source/drain terminals and covering the gate insulation layer; (2) forming a color resist layer on the passivation layer, wherein the color resist layer comprises red, green, blue color resist blocks formed to respectively correspond to the red, green, blue sub pixel zones, two of the color resist blocks that are arranged adjacent to each other in a lateral direction forming a first intersection zone therebetween, the first intersection zone being located above the signal line, two of the color resist blocks that are arranged adjacent to each other in a longitudinal direction forming a second intersection zone therebetween, the second intersection zone being located above the scan line; (3) forming a first via in the color resist layer to correspond to and be located above the source/drain terminals and forming a first pixel electrode layer on the color resist layer, wherein the first pixel electrode layer is set in engagement with the source/drain terminals through the first via; (4) forming a planarization layer on the first pixel electrode layer and forming a second via in the planarization layer; (5) depositing and patterning a second pixel electrode layer on the planarization layer, wherein the second pixel electrode layer is set in engagement with the first pixel electrode layer through the second via, the second pixel electrode layer comprising a pixel electrode block located in each of the sub pixel zones, the pixel electrode block having a lateral border located above the scan line and a longitudinal border located above the signal line; (6) forming a dot-like black matrix on the glass substrate at a location corresponding to the semiconductor layer and forming a common electrode layer on the black matrix; and (7) laminating the array substrate and the glass substrate with each other and filling therein a liquid crystal layer.