Patent ID: 9558108
Date: 2017-01-31
CPC Classifications: G06F,G11C

Claim:
1. An operating method for a memory, comprising: maintaining, for an array of memory cells including erasable blocks of memory cells in the array, status data for a plurality of sub-blocks of the erasable blocks, the status data indicating whether the sub-blocks are currently accessible and whether the sub-blocks are invalid; and in response to a request to erase a selected sub-block of a particular erasable block: determining the status data of the other sub-block or sub-blocks in the particular erasable block, and updating the status data of the selected sub-block to indicate a changed status if the status data of fewer than a pre-determined number of the other sub-block or sub-blocks of the particular erasable block indicates a same status as the changed status, and issuing an erase command to erase the particular erasable block if the status data indicate the pre-determined number of the other sub-block or sub-blocks of the particular erasable blocks is/are invalid, else the changed status of updating the status data to indicate that the selected sub-block is invalid.