Patent ID: 9590631
Date: 2017-03-07
CPC Classifications: H01L,H03K

Claim:
1. A semiconductor device comprising: a NAND decoder; and an inverter, the NAND decoder and the inverter including six transistors, each having a source, a drain, and a gate arranged in a layered manner in a direction perpendicular to a substrate, the six transistors being arranged on the substrate in a line in a first direction, each of the six transistors including the NAND decoder including the inverter including the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor being connected to each other, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor being connected to each other, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the first n-channel MOS transistor being located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, and the first n-channel MOS transistor, respectively, and being connected to one another via silicide regions to form a first output terminal, the source region of the second n-channel MOS transistor being located closer to the substrate than the silicon pillar of the second n-channel MOS transistor, the source region of the first n-channel MOS transistor being connected to the drain region of the second n-channel MOS transistor via a contact, the source regions of the first p-channel MOS transistor and the second p-channel MOS transistor being connected to a power supply line via contacts, the source region of the second n-channel MOS transistor being connected to a reference power supply line via a silicide region, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor being connected to each other and being connected to the first output terminal, the drain region of the third p-channel MOS transistor and the drain region of the third n-channel MOS transistor being connected to each other to form a second output terminal, the source region of the third p-channel MOS transistor and the source region of the third n-channel MOS transistor being respectively connected to the power supply line and the reference power supply line, the NAND decoder further including the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor, which are connected to each other, being connected to the first address signal line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor, which are connected to each other, being connected to the second address signal line, the power supply line, the reference power supply line, the first address signal line, and the second address signal line being arranged to extend in a second direction perpendicular to the first direction.