Patent ID: 9577648
Date: 2017-02-21
CPC Classifications: G06F,H03K,H03L

Claim:
1. A clock synchronization circuit, comprising: a fine phase detector including two output bits; a charge pump coupled to the two output bits; a filter coupled to an output of the charge pump; an analog-to-digital converter coupled to an output of the charge pump; a coarse phase detector including, a first variable delay circuit including an output coupled to provide the first clock signal to a first input of the fine phase detector and a first input of the coarse phase detector; and a controller including a first input coupled to a first output bit of the first flip-flop and a second output bit of second flip-flop, a second input of the controller coupled to an output of the analog-to-digital converter, and an output of the controller coupled to a control input of the first variable delay circuit, wherein the controller is configured to adjust the first variable delay circuit based on the fine phase detector when the coarse phase detector indicates that the first clock signal and second clock signal are within a fine detect window.