Patent ID: 9748251
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method comprising: obtaining an intermediate semiconductor device having a dielectric layer, a first hardmask layer, a second hardmask layer, a third hardmask layer, and a lithography stack; patterning a first set of lines in a first direction; patterning a second set of lines in the first direction between the first set of lines; etching the lithography stack to define a combination of the first and second set of lines in the third hardmask layer; depositing a second lithography stack over the second hardmask layer and the third hardmask layer; patterning a third set of lines in a second direction perpendicular to the first and second set of lines; etching the second lithography stack defining the third set of lines in the third hardmask layer, leaving an OPL above the third hardmask layer where the third set of lines was not etched; depositing a spacer over the OPL and over the second hardmask layer in the third set of lines; etching the spacer, leaving a set of vertical spacers lining the third set of lines; removing the OPL; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.