Patent ID: 9722617
Date: 2017-08-01
CPC Classifications: H03L

Claim:
1. A phase locked loop, comprising: a controllable oscillator, arranged to generate an oscillating signal; a charge pump circuit, arranged to receive a calibration signal and generate a charge pump output according to the calibration signal when the PLL operates in a calibration mode; a type II loop filter, arranged to receive the charge pump output, and generate a first control signal to the controllable oscillator according to the charge pump output; a frequency divider, arranged to receive the oscillating signal outputted from the controllable oscillator and an adjusting signal, and refer to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal; and a phase error processing circuit, arranged to receive the feedback signal and a reference signal, and output the adjusting signal based on a comparison result of the reference signal and the feedback signal, wherein the phase error processing circuit comprises: