Patent ID: 9672903
Date: 2017-06-06
CPC Classifications: B81B,B81C,G11C,H01L

Claim:
1. A static random access memory (SRAM) device comprising: a peripheral logic circuit; a plurality of two-port SRAM cells, each two-port SRAM cell comprising: a first plurality of metal lines including a write bit line, an inverse write bit line, a read bit line, a write word line landing pad, and a read word line landing pad, wherein the first plurality of metal lines is located in a first metal layer; a second plurality of metal lines including a write word line, wherein the second plurality of metal lines is located in a second metal layer; a third plurality of metal lines including a global write bit line and an inverse global write bit line, wherein the third plurality of metal lines is located in a third metal layer; and a plurality of jumper structures, each jumper structure comprising: