Patent ID: 9548315
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a memory cell region which has a plurality of first layers and a plurality of second layers stacked alternately in a first direction on the semiconductor substrate therein, and which has a memory cell disposed therein; a peripheral region disposed in at least part of a periphery of the memory cell region, the peripheral region including a first stepped structure which has the plurality of first layers and the plurality of second layers stacked alternately in the first direction therein and in which an end of a lower first layer is disposed further from the memory cell region than is an end of an upper first layer; and a second stepped structure which is disposed on the first stepped structure, which has a plurality of third layers and a plurality of fourth layers stacked alternately in the first direction therein, and in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction orthogonal to the first direction of the second stepped structure being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction orthogonal to the first direction and the second direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.