Patent ID: 9606798
Date: 2017-03-28
CPC Classifications: G06F

Claim:
1. A processor, comprising: a first comparison operation unit; a second comparison operation unit; a first operation unit; a second operation unit; a third operation unit; and a register, wherein the first comparison operation unit receives a first comparison operation signal, a first input signal, and a second input signal, performs a comparison operation indicated by the first comparison operation signal on the first input signal and the second input signal, and outputs a result of the comparison operation, the second comparison operation unit receives a second comparison operation signal, a third input signal, and a fourth input signal, performs a comparison operation indicated by the second comparison operation signal on the third input signal and the fourth input signal, and outputs a result of the comparison operation, the first operation unit receives the comparison result of the first comparison operation unit, and a value already held in the register, and outputs, as a first operation result, one of the comparison result of the first comparison operation unit, a first logical operation of the comparison result of the first comparison operation unit and the value of the register, and a second logical operation of the comparison result of the first comparison operation unit and the value of the register, the second operation unit receives the comparison result of the second comparison operation unit, and a value already held in the register, and outputs, as a second operation result, one of the comparison result of the second comparison operation unit, a first logical operation of the comparison result of the second comparison operation unit and the value of the register, and a second logical operation of the comparison result of the second comparison operation unit and the value of the register, the third operation unit receives the first operation result and the second operation result, and outputs, as an execution result, one of the first operation result, a first logical operation of the first operation result and the second operation result, and a second logical operation of the first operation result and the second operation result to the register, and the register newly holds and outputs the execution result received from the third operation unit.