Patent ID: 9679769
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A method of manufacture of an integrated circuit packaging system comprising: forming a photoimagable dielectric layer on a carrier, the photoimagable dielectric layer having a trace opening for exposing the carrier; forming a trace within the trace opening; forming an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace, and the trace having a trace recess partially filling the trace opening for mold locking with the inner solder resist layer; removing the carrier for exposing the photoimagable dielectric layer and the trace; mounting an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; forming an encapsulation directly on the integrated circuit and the inner solder resist layer; and forming an external interconnect electrically coupled to the trace and the integrated circuit.