Patent ID: 9576678
Date: 2017-02-21
CPC Classifications: G09G,G11C

Claim:
1. A method for driving a shift register group, comprising: enabling a first control signal corresponding to a first shift register; disabling the first control signal corresponding to the first shift register and enabling a clock signal corresponding to the first shift register; disabling the clock signal corresponding to the first shift register, enabling a third control signal and making the voltage of a driving node close to the voltage of the enabled first control signal; and disabling the third control signal; wherein the shift register group comprising a plurality of series-coupled shift registers each being configured to provide an output signal, each one of the plurality of shift registers comprising: wherein the third control signal of the first shift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first shift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number; and wherein the plurality of shift registers are divided into a plurality of groups each consisting of two shift registers, the two shift registers in the same group are corresponding to the same clock signal, an enable period of the clock signal corresponding to a specific group comprising the first shift register and an enable period of the clock signal corresponding to the group last the specific group partially overlap, and the enable period of the clock signal corresponding to the group last the specific group and an enable period of the clock signal corresponding to the group next the specific group do not overlap.