Patent ID: 9646921
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof, a plurality of conductive posts formed on the second conductive pads, respectively; a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, an insulating layer formed on and directly contacting the chip and the first encapsulant and having a plurality of insulating openings for exposing the conductive posts, wherein the upper surfaces of the conductive posts are coplanar with the inactive surface of the chip and the first encapsulant; and further comprising a plurality of third conductive pads formed on the second surface of the packaging substrate, and a plurality of conductive through holes formed between the second conductive pads and the third conductive pads and penetrating the packaging substrate for electrically connecting the second conductive pads and the third conductive pads.