Patent ID: 9716156
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A method for manufacturing a trenched semiconductor power device comprising: applying a trench mask for opening a plurality of trenches from a top surface of a semiconductor substrate by configuring the trench mask having a greater distance between two adjacent trenches in a termination area than an active cell area and forming a thick insulation layer covering over trench sidewalls and a bottom surface of said trenches and also simultaneously covering over the top surface of the semiconductor substrate outside of the trenches; applying an implanting-ion block mask for etching the thick insulation layer from a top part of the trenches and the trench sidewalls and also simultaneously from an area surrounding the trenches thus leaving a thick bottom insulation layer at a bottom portion of the trenches and simultaneously forming implanting-ion blocks above said top surface in a mesa area between and at a distance away from said trenches and in a middle portion between two of said trenches for blocking body implanting ions and source ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced; and the step of etching the thick insulation layer further comprises a step of forming said implanting-ion blocks in a termination area with a greater width than said implanting-ion block on said mesa area for separating body ion implanting regions to form floating body regions in said termination area thus form at least a guard ring in a trench surrounded by said floating body region in said termination area.