Patent ID: 9740431
Date: 2017-08-22
CPC Classifications: G06F,G11C

Claim:
1. A memory system comprising: a volatile memory that includes a volatile memory array, wherein during an activate operation to the volatile memory, the volatile memory is configured to read a page of volatile data from the volatile memory array and store the page of volatile data in data-store latches of the volatile memory; a non-volatile memory that includes a non-volatile memory array, wherein during an activate operation to the non-volatile memory, the non-volatile memory is configured to read a page of non-volatile data from the non-volatile memory array and store the page of non-volatile data in data-store latches of the non-volatile memory, wherein an activate latency of the non-volatile memory is longer than an activate latency of the volatile memory; a shared data bus coupled to the volatile memory and the non-volatile memory; a shared address bus coupled to the volatile memory and the non-volatile memory; and a memory controller coupled to the shared data bus and the shared address bus, wherein the memory controller includes a queue that queues memory commands received by the memory controller, wherein the memory controller is configured to categorize the memory commands into volatile and non-volatile memory accesses based on an address received with each memory command, and wherein the memory controller is configured to: