Patent ID: 9558945
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: an array chip including an exposed surface side, a three-dimensionally disposed plurality of memory cells, and a memory-side interconnection layer connected to the memory cells, the array chip not including a substrate; a circuit chip including a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit, the circuit chip being attached to the array chip with the circuit-side interconnection layer facing the memory-side interconnection layer; a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer; a pad provided in the circuit chip; and an external connection electrode reaching the pad from the exposed surface side of the array chip.