Patent ID: 9589915
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate defined with a seal ring region and a circuit region, wherein the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering on the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a conductive bump disposed over the circuit region of the substrate; a molding disposed over the passivation layer and the polymeric layer, wherein the molding and the polymeric layer surround and are in contact with the conductive bump, wherein the seal ring structure is covered by the molding.