Patent ID: 9613392
Date: 2017-04-04
CPC Classifications: G06T

Claim:
1. A method for performing graphics processing of a graphics system in an electronic device, the method comprising the steps of: configuring a configurable hardware circuit of the graphics system to be a vertex processing (VP) path in a specific processing phase, wherein the configurable hardware circuit comprises a vertex loader, a plurality of unified shaders, a culling unit, a clipping and setup unit, a unified rasterizer, a binning processor, and a shared cache that are arranged for performing tile-based rendering (TBR) operations; utilizing the VP path to perform VP-related TBR operations; configuring the configurable hardware circuit of the graphics system to be a pixel processing (PP) path in another processing phase; and utilizing the PP path to perform PP-related TBR operations; wherein the VP path and the PP path are different from each other; and in a situation where the configurable hardware circuit is configured to be the VP path, the VP path starts from a vertex buffer within the electronic device, passes through the vertex loader, the plurality of unified shaders, the culling unit, the clipping and setup unit, the unified rasterizer, and the binning processor, and reaches a bin buffer within the electronic device.