Patent ID: 9721672
Date: 2017-08-01
CPC Classifications: G11C

Claim:
1. A system, comprising: a memory array including a set of memory cells; a program circuit configured to apply one or more programming pulses to the set of memory cells and subsequent to one of the programming pulses apply one or more program verify pulses to the set of memory cells after a time delay, the one or more programming pulses includes a programming pulse at a programming voltage; and a delay circuit configured to determine the time delay between the one or more programming pulses and the one or more program verify pulses based on the programming voltage, the delay circuit configured to determine a second programming voltage different from the programming voltage to be applied to the set of memory cells and determine a second time delay between the one or more program verify pulses and the application of a second set of programming pulses to the set of memory cells based on the second programming voltage.