Patent ID: 9729149
Date: 2017-08-08
CPC Classifications: G11C,H03K

Claim:
1. A semiconductor device comprising memory cells in a memory cell array, each of the memory cells comprising: a first transistor; a second transistor; a third transistor; a capacitor; and a logic element, wherein a first terminal of the first transistor is electrically connected to an output terminal of the logic element, wherein a first terminal of the second transistor is electrically connected to a gate of the first transistor, wherein a second terminal of the first transistor is electrically connected to a terminal of the capacitor and a gate of the third transistor, wherein the logic element is configured to change a potential of the first terminal of the first transistor from a first potential into a second potential and then into a third potential when a first signal is input to an input terminal of the logic element, wherein the second potential is lower than the first potential, and wherein the third potential is higher than the first potential.