Patent ID: 9721876
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a single-layered plated interconnect layer; a first electronic component mounted to an upper face of the plated interconnect layer, the first electronic component having a first pad disposed on a lower face of the first electronic component; a second electronic component mounted to a lower face of the plated interconnect layer, the second electronic component having a second pad disposed on an upper face of the second electronic component; a first resin part covering the first electronic component and situated on an upper side of the plated interconnect layer; and a second resin part covering the second electronic component and situated on a lower side of the plated interconnect layer, wherein at least one of the first electronic component and the second electronic component is a semiconductor chip, and at least part of the first electronic component and at least part of the second electronic component face each other across the plated interconnect layer, wherein the plated interconnect layer includes a sloping portion disposed on a sloping boundary between the first resin part and the second resin part, the sloping portion sloping downward toward a periphery of the plated interconnect layer, wherein an end part of the sloping portion is bent to have a face of the end part exposed from the second resin part, and a lower surface of the second resin part is flush with the face of the end part, wherein the lower face of the first electronic component having the first pad disposed thereon faces, across a portion of the plated interconnect layer, the upper face of the second electronic component having the second pad disposed thereon, and the portion of the plated interconnect layer includes a first interconnect pad, the first interconnect pad providing an electrical connection between the first pad of the first electronic component and the second pad of the second electronic component, wherein the plated interconnect layer further includes: an interconnection having the sloping portion; and a second interconnect pad connected to the interconnection and situated on a same plane as the first interconnect pad, the second interconnect pad being electrically connected to the first electronic component or to the second electronic component, and wherein the first interconnect pad of the plated interconnect layer has no electrical connection extending outwardly beyond perimeters of the first electronic component and the second electronic component in a plan view, and is electrically connected neither to the second interconnect pad nor to the interconnection via the plated interconnect layer, and the first interconnect pad, the second interconnect pad, and the interconnection are made of a same material.