Patent ID: 9721522
Date: 2017-08-01
CPC Classifications: G02F,G09G

Claim:
1. An array substrate comprising: a plurality of pixel units defined by gate lines and data lines intersecting each other, and a charge sharing unit; wherein the gate lines are configured to input a scan signal for turning on the pixel units, the charge sharing unit comprises a plurality of control switches and a charge sharing wire, each of the control switches has one end connected with one of the data lines and another end connected with the charge sharing wire, the charge sharing wire connects at least two of the data lines; under a test mode, the charge sharing wire has one end electrically connected with a data line test port and the charge sharing wire is used to test the corresponding data line when a test signal is inputted via the data line test port; and under a display mode, the charge sharing wire electrically connects the at least two of the data lines in response to turning on the corresponding control switches when the gate lines are not inputted with a scan signal.