Patent ID: 9590059
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. An integrated circuit (IC), comprising: a semiconductor substrate including a flash memory region and a capacitor region; a flash memory cell arranged over the flash memory region and including: a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell, and a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer; and a capacitor arranged over the capacitor region and including: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and have sidewalls separated from one another by a capacitor dielectric layer, wherein the capacitor dielectric layer and control gate dielectric layer are made of the same material; and wherein uppermost surfaces of the select gate and first capacitor plate are co-planar with one another.