Patent ID: 9559671
Date: 2017-01-31
CPC Classifications: H03K

Claim:
1. A master slave storage circuit comprising: a first master portion coupled to a first master data storage node; and a first slave portion coupled to a first slave data storage node, wherein the first master portion comprises one of a first master latch or a first master capacitive element coupled to the first master data storage node and the first slave portion comprises one of a first slave latch or a first slave capacitive element coupled to the first slave data storage node, wherein if the first master portion comprises the first master latch, the first slave portion comprises the first slave capacitive element, and if the first master portion comprises the first master capacitive element, the first slave portion comprises the first slave latch; a first switch coupled to an input of the master slave storage circuit; and a second switch coupled between the first master portion and the first slave portion, wherein the first switch and second switch are closed during opposite phases of a clock signal.