Patent ID: 9553080
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method comprising: providing a device layer in each of integrated circuit (IC) chips on upper surfaces of top and bottom silicon (Si) wafers; forming, subsequent to the device layer, through-silicon vias (TSVs) extending through an upper surface of the device layer in each of the IC chips and into the bottom Si wafer; forming, subsequent to the TSVs, a dielectric layer on the upper surface of the device layer in each of the IC chips of the top and bottom Si wafers; forming a back-end-of-line (BEOL) metal layer in the dielectric layer of each of the IC chips of the top and bottom Si wafers; face-to-face bonding of opposing IC chips of the top and bottom Si wafers; dicing adjacent bonded IC chips through vertically aligned dicing lanes in the top and bottom Si wafers; planarizing the upper surface of the dielectric layer to a level of a BEOL final metal layer in each of the IC chips of the top and bottom Si wafers; and forming vias in the dielectric layer of each of the IC chips of the top and bottom Si wafers, wherein upper surfaces of the vias are coplanar with the BEOL final metal layer in each of the IC chips of the top and bottom Si wafers, wherein the face-to-face bonding of the opposing IC chips comprises: