Patent ID: 9734033
Date: 2017-08-15
CPC Classifications: G01R,G06F

Claim:
1. A computer system for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads comprising: a processor; a test generator apparatus; said processor using said test generator including test generation context controls for generating separate tests including a main test, and an irritator test for testing the multiple threads with the generated main test and each generated irritator test being completely independent; said processor using said test generator for saving the generated main test and each irritator test and randomly mixing the generated main test and each irritator test; said processor using said test generator for combining the saved generated main test and each irritator test and mixed generated main test and each irritator test, wherein the main test is not forced to be generated with any particular irritator; said processor using said test generator, implementing an unexpected exception handler for returning control of an irritator program stream to a known location and a known state at an uninterrupted instruction address in the irritator program stream; said processor using said test generator, running constrained random irritator tests, monitoring the main test and running the main test from start to finish; and said processor using said test generator, responsive to identifying the main test to complete, intervening in execution of each irritator test.