Patent ID: 9659529
Date: 2017-05-23
CPC Classifications: G09G

Claim:
1. A display apparatus comprising: a driving circuit configured to receive a pulse for an input signal and to transition a logic level of a first control signal and a logic level of a second control signal after receiving the pulse for the input signal; a first transistor that is controllable by the second control signal to electrically disconnect a data signal line from a source/drain region of a second transistor and electrically connect the data signal line to the source/drain region of the second transistor; a first switch that is controllable by the second control signal to electrically disconnect a gate of the second transistor from a different source/drain region of the second transistor and electrically connect the gate of the second transistor to the different source/drain region of the second transistor; a second switch that is controllable by the first control signal to electrically disconnect the gate of the second transistor from a first voltage line and electrically connect the gate of the second transistor to the first voltage line; and a third switch that is controllable by a third control signal to electrically disconnect the source/drain region of the second transistor from a second voltage line and electrically connect the source/drain region of the second transistor to the second voltage line, wherein an integer number of time periods exists between a leading edge of the pulse for the input signal and a trailing edge of the pulse for the input signal, the driving circuit is configured to generate the third control signal that has the integer number of time periods between a leading edge of a pulse for the third control signal and a trailing edge of the pulse for the third control signal.