Patent ID: 9741844
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor power device, comprising: a first well region having a first conductivity type disposed in a substrate having a second conductivity type opposite the first conductivity type; a gate overlapping the first well region, and vertically separated from the first well region by an insulating layer; a source region disposed at a first side of the gate; a buried layer having the second conductivity type disposed laterally in the first well region, wherein the buried layer is vertically separated from the insulating layer by at least a portion of the first well region; a drain region having the first conductivity type disposed on a second side of the gate laterally opposite the first side, and contacting the buried layer to form a p-n junction between the drain region and the buried layer; a body region having the second conductivity type disposed in the substrate at the first side of the gate; a body contact region contacting the body region; and a first isolation region disposed between the body contact region and the source region, wherein the drain region has a depth greater than the source region and is spaced apart from the substrate by the first well region, wherein the source region is disposed in the body region, the body region having a depth shallower than the drain region.