Patent ID: 9734918
Date: 2017-08-15
CPC Classifications: G09G,G11C

Claim:
1. A shift register, comprising a pull-up unit, a reset unit and a signal output, wherein, said pull-up unit is connected to said signal output and is configured to pull up an output signal, so that the output signal is at high level; said reset unit is connected to a control end of said pull-up unit and said signal output respectively, and is configured to reset the potential of the control end of said pull-up unit after said output signal is at high level, so that said output signal is at low level; and wherein said shift register further comprises a pull-down unit; said pull-down unit is connected to a control end of said pull-up unit and said signal output respectively and is configured to pull down the potential of the control end of said pull-up unit and said output signal after said reset unit has reset the potential of the control end of said pull-up unit, so that said pull-up unit switches off to control said output signal to maintain a low level, said pull-down unit comprises a dual-pull-down control module; said dual-pull-down control module comprises an eighth TFT, a ninth TFT, a tenth TFT and an eleventh TFT; said eighth TFT is configured so that the gate is connected to said signal output, the source is connected to the low level output, and the drain is connected to the source of the tenth TFT and the gate of the eleventh TFT respectively; said ninth TFT is configured so that the source is connected to the low level output, and the drain is connected to the source of said eleventh TFT; said tenth TFT is configured so that the gate and the drain are connected to a first clock signal input, and the source is connected to the gate of the eleventh TFT; and said eleventh TFT is configured so that the drain is connected to the first clock signal input.