Patent ID: 9601474
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A stackable unit for a chip scale package capable of being built-up from multiple stacked instances of the stackable unit, each stackable unit comprising: a substrate composed of a first semiconductor material; multiple chips composed of a second semiconductor material adhered to a first surface of the first semiconductor material; a first insulating layer surmounting the first surface of the first semiconductor material and the multiple chips; conductive vias through the first insulating layer in electrical communication with the first semiconductor material and the multiple chips; a first conductive pattern layer surmounting the first insulating layer and electrically connecting at least some of the conductive vias; at least one opening at a second surface of the first semiconductor material etched through an entire thickness of the first semiconductor material; an inlay of an insulating material in the at least one opening; and multiple separate conductive vias in the inlay of each single opening, each of the multiple separate conductive vias connected to a conductive via in the first insulating layer to provide an individual conductive via through an entire thickness of the stackable unit.