Patent ID: 9570176
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A nonvolatile memory device, comprising: a plurality of memory blocks including a first memory block and a second memory block, each of the plurality of memory blocks including a plurality of memory cell strings, each of the plurality of memory cell strings including a ground selection transistor and a plurality of nonvolatile memory cells that are connected in series and stacked over a substrate in a direction that is perpendicular to the substrate, each of the plurality of memory blocks having a floating body structure; a plurality of word lines including a first group of word lines and a second group of word lines, the first group of word lines being connected to the first memory block, the second group of word lines being connected to the second memory block; and a source driver configured to apply a plurality of operation voltages needed for a read or program operation to the first group of word lines and to apply a plurality of unselected block word line voltages higher than a ground voltage to the second group of word lines during the read or program operation, wherein the ground selection transistor of each of the plurality of memory cell strings of the second memory block is turned off and channels of the plurality of memory cell strings of the second memory block are electrically disconnected from the substrate while the source driver applies the plurality of unselected block word line voltages to the second group of word lines.