Patent ID: 9711525
Date: 2017-07-18
CPC Classifications: G11C,H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: forming a structure including U-shaped channel structures vertically passing through first insulating layers and first conductive layers alternately stacked on a substrate, and electrically coupled in the substrate, and a slit vertically passing through the first insulating layers and the first conductive layers formed at a center of the U-shaped channel structures; forming a first passivation layer on a lateral surface of the slit; exposing a channel layer of the U-shaped channel structures through a lower side of the slit; and filling the slit, through which the channel layer is exposed, with a second conductive layer; and performing a wet etch process by exposing the channel layer formed in a pipe region by removing a third insulating layer formed in the pipe region.