Patent ID: 9584884
Date: 2017-02-28
CPC Classifications: H04B,H04Q

Claim:
1. A monolithically integrated system-on-chip device, the device comprising: a single silicon substrate member; a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol; an input/output block provided on the substrate member and coupled to the data input/output interface, the input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block; a signal processing block provided on the substrate member and coupled to the input/output block, the signal processing block configured to the input/output block using a bi-direction bus in an intermediary protocol; a driver module provided on the substrate member and coupled to the signal processing block, the driver module coupled to the signal processing blocking using a uni-directional multi-lane bus, the driver module comprising a plurality of driver blocks; a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device comprising a plurality of redundant laser devices in optical communication with a switch, the driver interface being configured to transmit output data in either an amplitude modulation format or a combination of phase/amplitude modulation format or a phase modulation format; a receiver module comprising a TIA block provided on the substrate member and to be coupled to the silicon photonics device using a loop back signal from an optical tap coupler through an isolation switch, and configured to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface; a communication block provided on the substrate member and operably coupled to the input/output block, the signal processing block, the driver module, and the receiver block; a communication interface coupled to the communication block; a control block provided on the substrate member and coupled to the communication block; and a variable bias block configured with the control block, the variable bias block comprising a common voltage rail coupling in parallel with a plurality of voltage drop blocks respectively coupled to the plurality of driver blocks, the variable bias block being configured to selectively tune each of the plurality of redundant laser devices provided on the silicon photonics device to adjust for at least a wavelength of operation, a fabrication tolerance, and an extinction ratio; wherein the control block is configured for laser bias and power control of the silicon photonics device; wherein the control block is configured with a thermal tuning or carrier tuning device each of which is configured on the silicon photonics device; and wherein the SerDes block is configured to convert N first data streams into M second data streams.