Patent ID: 9740235
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A system of interface adapter for facilitating data communication between two data processing units driven by clocks of different frequencies, comprising: a data input for receiving data signal from a transmitting data processing unit; a data output for sending data signal to a receiving data processing unit; a clock input for receiving a global clock signal; a FIFO block for storing data, having a predefined number of storage cells, having a data input port for receiving data, having a data output port for sending data, having a first clock input port for receiving a clock signal to control FIFO write operation, having a second clock input port for receiving a clock signal to control FIFO read operation, having a status output port for outputting a status signal regarding FIFO status; a first multi-phase generator for generating a first multi-phase signal, having an input port for receiving said global clock signal, having an output port for outputting said first multi-phase signal; a second multi-phase generator for generating a second multi-phase signal, having an input port for receiving said global clock signal, having an output port for outputting said second multi-phase signal; a first TAF-DPS (Time-Average-Frequency Direct Period Synthesis) clock generator for generating a clock signal for FIFO write operation and for driving said transmitting data processing unit, having a first input port for receiving said first multi-phase signal, having a second input port for receiving a first frequency control word, having a third input port for receiving a first control signal, having an output port for outputting a first generated clock signal; a second TAF-DPS clock generator for generating a clock signal for FIFO read operation and for driving said receiving data processing unit, having a first input port for receiving said second multi-phase signal, having a second input port for receiving a second frequency control word, having a third input port for receiving a second control signal, having an output port for outputting a second generated clock signal; a write-point-controller for generating said first control signal, having an input port for receiving said status signal regarding FIFO status, having an output port for outputting said first control signal; a read-point-controller for generating said second control signal, having an input port for receiving said status signal regarding FIFO status, having an output port for outputting said second control signal; wherein said data input port of FIFO is connected to said data input; wherein said data output port of FIFO is connected to said data output; wherein said first generated clock signal is connected to the first clock input port of said FIFO block; wherein said second generated clock signal is connected to the second clock input port of said FIFO block.