Patent ID: 9601502
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A three-dimensional memory device comprising: a first alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures extending through the alternating stack, each of the memory stack structures comprising a memory film and a vertical semiconductor channel extending substantially perpendicular to a top surface of the substrate and laterally surrounded by the memory film; an array of contact via structures located within the alternating stack and laterally spaced apart along a first horizontal direction and having different heights; and a peripheral semiconductor device located in a peripheral region on the substrate; wherein: each contact via structure within the array of contact via structures is laterally surrounded by a respective insulating liner; top surfaces of the plurality of contact via structures are located within a same horizontal plane; a bottom portion of each of the plurality of contact via structures is adjoined to a respective electrically conductive layer; and each contact via structure that passes through a topmost electrically conductive layer is laterally surrounded by each electrically conductive layer that overlies the respective electrically conductive layer to which the contact via structure is adjoined.