Patent ID: 9735277
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A semiconductor structure comprising: a substrate including a substrate surface; a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall; a first thin dielectric tunnel and a second thin dielectric tunnel disposed on the first fin channel sidewall and the second fin channel sidewall, respectively, wherein each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel; an insulator layer including a first insulator layer sidewall and a second insulator layer sidewall opposing the first insulator layer sidewall, wherein the insulator layer is disposed between the substrate and the fin channel to insulate the substrate from the fin channel, and the insulator layer is narrower than the substrate, thereby exposing portions of the substrate surface for vertical epitaxial crystal growth; a gate perpendicular to the fin channel, wherein the fin channel is narrower than the gate; a spacer including a first spacer sidewall and a second spacer sidewall opposing the first spacer sidewall, wherein the first spacer sidewall and the second spacer sidewall are substantially aligned with the first insulator layer sidewall and the second insulator layer sidewall, respectively; a dielectric layer disposed between the fin channel and the gate to separate the fin channel from the gate; a source epitaxy resulting from vertical epitaxial crystal growth on at least one exposed portion of the substrate surface; and a drain epitaxy resulting from vertical epitaxial crystal growth on at least one other exposed portion of the substrate surface.