Patent ID: 9704589
Date: 2017-07-11
CPC Classifications: G11C

Claim:
1. A nonvolatile memory device comprising: a nonvolatile memory cell coupled to a bit line; a sensing circuit configured to output a sensing output signal for sensing a status of the nonvolatile memory cell based on a sensing input signal inputted to the sensing circuit through a sensing input line; and a folding circuit coupled to the bit line to output the sensing input signal having a voltage low level or a voltage high level according to a voltage level of the bit line, wherein the sensing circuit is configured to include a P-MOS transistor and an N-MOS transistor coupled in series between the supply voltage line and a ground voltage, wherein the P-MOS transistor of the sensing circuit has a gate to which an enablement signal is inputted, a source coupled to the supply voltage line, and a drain coupled to the sensing output line; and wherein the N-MOS transistor of the sensing circuit has a gate coupled to the sensing input line, a drain coupled to the sensing output line, and a source coupled to the ground voltage.