Patent ID: 9685241
Date: 2017-06-20
CPC Classifications: G11C

Claim:
1. A test circuit comprising: a control circuit that tests a memory having a plurality of data holding circuits holding data, a plurality of write ports being coupled to the plurality of data holding circuits and used for writing data to the plurality of data holding circuits, and a plurality of read ports being coupled to the plurality of data holding circuits and used for reading data held in the plurality of data holding circuits; a write port identification information holding circuit that holds write port identification information identifying any one of the plurality of write ports; a read port identification information holding circuit that holds read port identification information identifying any one of the plurality of read ports; a write port selection circuit that selects any one of the plurality of write ports based on the write port identification information; and a read port selection circuit that selects any one of the plurality of read ports based on the read port identification information, wherein the control circuit sets the write port identification information in the write port identification information holding circuit and sets the read port identification information in the read port identification information holding circuit and carries out a test on the memory via the selected write port and the selected read port.