Patent ID: 9584140
Date: 2017-02-28
CPC Classifications: G11C,H03H,H03K,H03L

Claim:
1. An apparatus comprising: a phase mixer circuit configured to receive a first input signal and a second input signal and to provide an output signal at an output node, wherein the first input signal is delayed relative to the second input signal, wherein the phase mixer circuit includes a plurality of signal drivers and the plurality of signal drivers are configured to provide the first input signal and the second input signal to an output node having a ratio based on control signals; and a base interpolation circuit configured to provide the first input signal and the second input signal having a one-to-one ratio to the output node, wherein the first input signal and the second input signal are provided to the phase mixer circuit by a coarse delay circuit; the base interpolation circuit further comprises a base driver control circuit configured to mask provision of the each of the first input signal and the second input signal having the one-to-one ratio to the output node while a delay of the coarse delay circuit is adjusted.