Patent ID: 9673083
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method, comprising: forming a fin in a semiconductor substrate, said fin comprising a lower portion and an upper portion, wherein said lower portion of said fin has tapered sidewalls and is comprised of a lower first section containing an oxidation-retarding implant region and an upper second section that is substantially free of said oxidation-retarding implant region; forming a sidewall spacer on opposite sides of said upper portion of said fin, wherein said sidewall spacers cover said upper portion of said fin but do not cover said upper second section of said lower portion of said fin; forming a first layer of insulating material adjacent said sidewall spacers and said upper second section of said lower portion of said fin; and with said first layer of insulating material in position, performing a thermal anneal process to convert the portion of said upper second section of said fin that is in contact with said first layer of insulating material into an oxide fin isolation region positioned under said fin above said lower first section of said fin.