Patent ID: 9632141
Date: 2017-04-25
CPC Classifications: G01R,G06F

Claim:
1. A method of automatic test pattern generation (ATPG) testing of a microelectronic circuit, the method comprising: generating a test program comprising a plurality of instructions to conduct ATPG testing of a plurality of clock domains of the microelectronic circuit, wherein a first clock domain of the plurality of clock domains operates on a first clock signal with a first frequency and a second clock domain of the plurality of clock domains operates on a second clock signal with a second frequency, the first frequency different from the second frequency; and transmitting a first clock domain testing instruction of the plurality of instructions from a clock control unit of the microelectronic circuit receiving the test program to a first test control circuit associated with the first clock domain, the first clock domain testing instruction comprising a first clock enable signal that initiates the first clock signal of a first clock domain component; and transmitting a second clock domain testing instruction of the plurality of instructions from the clock control unit of the microelectronic circuit receiving the test program to a second test control circuit associated with the second clock domain, the second clock domain testing instruction comprising a second clock enable signal that initiates a second clock signal of the second clock domain component, wherein the first clock domain testing instruction causes the first clock domain to undergo ATPG testing at the first frequency and the second clock domain testing instruction causes the second clock domain to begin ATPG testing at the second frequency simultaneously with the first clock domain ATPG testing.