Patent ID: 9718098
Date: 2017-08-01
CPC Classifications: B06B,B81B,B81C,G10K

Claim:
1. A method, comprising: forming a cavity in a first wafer above a complementary metal oxide semiconductor (CMOS) circuit in the first wafer by etching the cavity to an etch stop, the first wafer including a metal electrode structure disposed within an insulating layer of the first wafer, wherein forming the cavity comprises etching an upper surface down to at least a level of the insulating layer of the first wafer in which the electrode structure is disposed; directly bonding the first wafer and a second wafer to seal the cavity of the first wafer with the second wafer to form a sealed cavity, the second wafer including one or more of a silicon-on-insulator (SOI) wafer or a bulk silicon wafer having a degeneratively doped layer; and forming an ultrasonic transducer membrane from the second wafer; wherein the etch stop comprises the metal electrode structure.