Patent ID: 9613663
Date: 2017-04-04
CPC Classifications: G11C,H01L

Claim:
1. An array structure of a single-poly nonvolatile memory, the array structure comprising: a first word line; a second word line; a third word line; a first source line; a second source line; a third source line; a first erase line; a first bit line; a second bit line; a third bit line; a fourth bit line; a first MTP cell comprising a first PMOS transistor, a second PMOS transistor and a first NMOS transistor, wherein a source terminal of the first PMOS transistor is connected to the first source line, a gate terminal of the first PMOS transistor is connected to the first word line, a drain terminal of the first PMOS transistor is connected to a source terminal of the second PMOS transistor, a drain terminal of the second PMOS transistor is connected to the first bit line, a gate terminal of the second PMOS transistor is connected to a gate terminal of the first NMOS transistor, and a drain terminal and a source terminal of the first NMOS transistor are connected to the first erase line; a first OTP cell comprising a third PMOS transistor and a fourth PMOS transistor, wherein a source terminal of the third PMOS transistor is connected to the second source line, a gate terminal of the third PMOS transistor is connected to the second word line, a drain terminal of the third PMOS transistor is connected to a source terminal of the fourth PMOS transistor, a drain terminal of the fourth PMOS transistor is connected to the second bit line; a first ROM cell comprising a fifth PMOS transistor and a sixth PMOS transistor and a second NMOS transistor, wherein a source terminal of the fifth PMOS transistor is connected to the third source line, a gate terminal of the fifth PMOS transistor is connected to the third word line, a drain terminal of the fifth PMOS transistor is connected to a source terminal of the sixth PMOS transistor, a drain terminal of the sixth PMOS transistor is connected to the third bit line, a gate terminal of the sixth PMOS transistor is connected to a gate terminal of the second NMOS transistor, and a drain terminal and a source terminal of the second NMOS transistor are a floating state; and a second ROM cell comprising a seventh PMOS transistor, wherein a source terminal of the seventh PMOS transistor is connected to the third source line, a gate terminal of the seventh PMOS transistor is connected to the third word line, a drain terminal of the seventh PMOS transistor is connected to the fourth bit line.