Patent ID: 9722025
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate having a topmost surface in which is formed a planar transistor; a first multiple gate transistor fin having a topmost surface substantially level with the topmost surface of the semiconductor substrate, the first multiple gate transistor fin including a first isolation structure extending from a first sidewall of the first multiple gate transistor fin to a second sidewall of the first multiple gate transistor fin, the first isolation structure being a first distance below the topmost surface of the first multiple gate transistor fin; and a second multiple gate transistor fin having a topmost multiple gate transistor substantially level with the topmost surface of the semiconductor substrate, the second multiple gate transistor fin including a second isolation structure extending from a first sidewall of the second multiple gate transistor fin to a second sidewall of the second multiple gate transistor fin, the second isolation structure being a second distance below the topmost surface of the second multiple gate transistor fin, the second distance being greater than the first distance.