Patent ID: 9568546
Date: 2017-02-14
CPC Classifications: G01R

Claim:
1. An apparatus, comprising: at least two electrically-coupled integrated circuit (IC) chips; each IC chip comprising a signal output via which an outgoing signal is transmitted, a signal input via which an incoming data signal is received, a pass circuit to couple the signal output to the signal input during testing of the IC chip, and a delay circuit to produce a first timing signal and a second timing signal during testing of the IC chip, the second timing signal being delayed from the first timing signal according to a test parameter, the first timing signal triggering transmission of a test signal via the signal output, and the second timing signal triggering sampling of the test signal via the signal input; and each IC chip configured to be programmed to define the test parameter in a manner so as to establish the respective delay by which the respective second timing signal is delayed by the respective delay circuit from the respective first timing signal by an amount including delay corresponding to the pass circuit.