Patent ID: 9672889
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a memory bank including a plurality of word lines; a refresh operation control unit that performs a first refresh operation to a first adjacent word line group of a target word line of the plurality of word lines for at least two times, and performs a second refresh operation to a second adjacent word line group of the target word line for at least two times after the first refresh operation, in response to a smart refresh command; a normal command generation unit that generates a normal refresh command in response to a refresh command; and a smart command generation unit that counts the refresh command and generates the smart refresh command whenever the refresh command is counted a first predetermined number of times, wherein the normal refresh command is deactivated when the smart refresh command is activated, wherein the first adjacent word line group includes the (N−1) wherein the normal command generation unit counts a refresh command and generates a normal refresh command which is activated in each predetermined cycle.