Patent ID: 9685971
Date: 2017-06-20
CPC Classifications: G11C,H03M

Claim:
1. A successive comparison A/D conversion circuit, comprising: a comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains a comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the pair of first differential signals, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the pair of first differential signals by subtracting the reference signal from a third differential signal, or by adding the reference signal to the third differential signal, and outputs the generated pair of first differential signals to the pair of differential input terminals; and a control circuit which stops an operation of the differential amplification circuit in a predetermined period including a period in which the comparison circuit initiates comparison.