Patent ID: 9571050
Date: 2017-02-14
CPC Classifications: H03F

Claim:
1. A method for implementing an enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifiers (TIAs) comprising the steps of: providing a Transimpedance Amplifier (TIA) and a replica TIA by forming said TIA by an inverter and a first feedback resistor and a photo-detector input, and forming said replica TIA by a replica inverter with a second feedback resistor; providing a voltage divider formed by series connected resistors connected between a voltage rail VDD and a ground rail for generating a first set voltage level; providing a first input of said operational amplifier with said first set voltage level; providing an operational amplifier in a feedback configuration for regulating a second set voltage level at the photo-detector input of said TIA; and providing said Transimpedance Amplifier (TIA) and a replica TIA includes providing each of said TIA and replica TIA formed by a series connected P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) and said associated feedback resistor.