Patent ID: 9698241
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method of fabricating an integrated circuit comprising: forming a gate dielectric overlying a substrate; forming a base work function layer overlying the gate dielectric, wherein the base work function layer comprises tungsten, wherein the base work function layer overlies the gate dielectric in a first region and the base work function layer further overlies the gate dielectric in a second region, wherein the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region and the nFET region; forming a mask overlying the first region; exposing the second region after forming the mask; altering a work function value of the base work function layer in the second region to produce a modified work function layer in the second region; removing the mask overlying the first region; and forming a gate electrode overlying the base work function layer and the modified work function layer.