Patent ID: 9647057
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A capacitor 3D-cell formed on a silicon substrate, wherein a trench extends within the substrate from a top face of said substrate, the trench comprising at least first and second trench portions which are located on opposite lateral sides of an area of the substrate top face which is outside the trench, called not-etched area, the capacitor 3D-cell comprising: a first layer-shaped electrode disposed at least in both first and second trench portions, and forming at least one continuous first conduction path from said first trench portion to said second trench portion; a first and second dielectric-electrode (DE) structures stacked on the first layer-shaped electrode and each disposed at least in both first and second trench portions, a first contact set arranged above the substrate top face for contacting the second layer-shaped electrode, said first contact set comprising at least two electrically conductive contact pads each in electrical contact with said second layer-shaped electrode but located out of and on either lateral side of the not-etched area, so that a first one of said contact pads is closer to the first trench portion compared to the second trench portion whereas the second contact pad is closer to said second trench portion compared to said first trench portion; and a first electrically conductive track arranged above the substrate top face and connecting electrically said at least two contact pads of the first contact set to each other, so that the second conduction path between the first and second trench portions, as formed by the second layer-shaped electrode, is conductively bypassed for electricity flow by the first track through the first and second contact pads of the first contact set.