Patent ID: 9671961
Date: 2017-06-06
CPC Classifications: G06F

Claim:
1. A memory controller, comprising: an address conversion information buffer configured to store address conversion information, the address conversion information being about a correlation between a logical address and a physical address, the physical address including a number of a memory area for data writing; an address conversion section configured to convert the logical address into the physical address in accordance with the address conversion information, the logical address being included in a command issued by a host computer; an allocation information storage section configured to store allocation information, the allocation information indicating a correlation between an access size and the number of the memory area for the data writing; a memory identification section configured to output the number of the memory area for the data writing in accordance with the allocation information, the number of the memory area corresponding to the access size in the command; and a control section configured to, when the number of the memory area in the physical address is different from the number of the memory area provided by the memory identification section, perform the data writing to the memory area identified by the memory identification section.