Patent ID: 9728650
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A thin film transistor array panel, comprising: a first conductive layer including a gate electrode; a channel layer disposed over the gate electrode and insulated from; and a second conductive layer disposed over the channel layer, the second conductive layer comprising a multi-layered portion defining a source electrode and a drain electrode, wherein the multi-layered portion of the second conductive layer comprises at least: wherein each of the third and the first sub-layers comprises a metal oxide material containing indium and zinc, wherein an indium to zinc content ratio in the first sub-layer is greater than an indium to zinc content ratio in the third sub-layer, wherein the indium to zinc content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, and wherein a gap width associated there-with in the third sub-layer is wider than a gap width in the first sub-layer.