Patent ID: 9633905
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A device comprising: a semiconductor substrate; a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate; a Shallow Trench Isolation (STI) region on a side of the plurality of semiconductor fins, wherein the STI region comprises a top surface and a non-flat bottom surface, and wherein the plurality of semiconductor fins is over the top surface of the STI region; a plurality of STI regions in the semiconductor substrate; a plurality of fin extensions underlying and aligned to the plurality of semiconductor fins, wherein sidewalls of the plurality of fin extensions are in contact with sidewalls of the plurality of STI regions; and a fin extension residue having a bottom substantially level with bottom surfaces of the plurality of fin extensions, wherein the fin extension residue extends into the STI region from a bottom surface of the STI region.