Patent ID: 9685386
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A semiconductor test structure for MOSFET noise testing, comprising: a semiconductor substrate comprising a first well region having a circumference and a first conductivity type; a MOSFET device formed on the first well region, the MOSFET device having source, drain and gate electrodes; a metal shielding layer formed on the MOSFET device, the metal shielding layer being electrically isolated from the source, drain and gate electrodes of the MOSFET device and completely covering the MOSFET device and extending beyond the circumference of the first well region; and a deep well region formed in the semiconductor substrate at a bottom surface of the first well region opposite the MOSFET device, the deep well region having a second conductivity type and extending beyond the circumference of the first well region; wherein a vertical via is formed between a portion of the metal shielding layer extending beyond the first well region and a portion of the deep well region extending beyond the first well region, such that the metal shielding layer is coupled to the deep well region; the metal shielding layer is configured to be connected to a ground terminal of a testing machine during testing, and the first conductivity type and the second conductivity type are opposite conductivity types.