Patent ID: 9627048
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells, the memory cells being connected to a word line, the memory cells being connected to bit lines, respectively, and each of the memory cells being capable of storing n values (n is a natural number equal to or larger than 3); and a control circuit which controls potentials of the word line and the bit lines according to input data and writes data to the memory cells, wherein the control circuit executes first to k-th write sequences (k is a natural number equal to or larger than 2) for the memory cells, each write sequence including a plurality of program operations and a plurality of verify operations for verifying threshold voltages of the memory cells, the program operations and the verify operations being repeated alternately, data being written to the memory cells together, and each of the memory cells being set to one of the n values in the write sequences, the control circuit raises a program voltage in increments of ΔVpgm in the program operations, threshold distributions in the first to k-th write sequences get narrower in order, and ΔVpgm in the first k-th write sequences fulfill the following expression: ΔVpgm in the first write sequence>ΔVpgm in the second write sequence>ΔVpgm in the k-th write sequence.