Patent ID: 9634089
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method for improving electrical signal isolation between adjacent devices situated in a top semiconductor layer, said method comprising: fabricating a gate and a protection mask on said top semiconductor layer, said top semiconductor layer situated over a base oxide layer, and said base oxide layer situated over a handle wafer; applying an inert implant through said top semiconductor layer and said base oxide layer, and into a top surface of said handle wafer, while protecting a region of said top semiconductor layer situated under and substantially aligned with said gate so as to amorphize said top surface of said handle wafer, thereby reducing carrier mobility in said handle wafer to improve electrical signal isolation between said adjacent devices situated in said top semiconductor layer; wherein said inert implant is applied to an entire top surface of said top semiconductor layer except said region situated under and substantially aligned with said gate, and produces damaged regions within said top semiconductor layer.