Patent ID: 9559836
Date: 2017-01-31
CPC Classifications: H04L

Claim:
1. A clock data recovery circuit comprising: a phase detector that detects a phase difference between a recovery clock and an input signal and outputs a phase difference signal indicating the phase difference; a loop filter that generates a phase control signal based on the phase difference signal; and a phase shifter that controls a phase of the recovery clock based on the phase control signal, wherein the loop filter comprises: a first path that has an input side to which the phase difference signal is input, determines a loop gain that sets a speed of adjusting the phase of the recovery clock to the phase of the input signal, and has an output side from which a first output value is output, a subtractor that is provided on the input side on the first path and receives the phase difference signal as one input; a second path that receives the phase difference signal and determines a frequency tracking gain that sets a speed of adjusting a frequency of the recovery clock to a frequency of the input signal; and a compensator that gives a negative feedback from the output side to the input side of the first path by giving an output to another input of the subtractor on the first path and compensates for a phase delay of an output of the phase detector due to a delay amount of the loop filter.