Patent ID: 9535327
Date: 2017-01-03
CPC Classifications: G03F,H01L

Claim:
1. A method for fabricating a semiconductor device, comprising: dividing a pattern region of a desired pattern that is to be formed on a semiconductor substrate into a plurality of sub-regions, the pattern region defining a region on the semiconductor substrate to form the desired pattern; calculating combination conditions including a shape of illumination light for transferring and a mask pattern obtained by correcting a partial pattern in the sub-region of the desired pattern formed on a mask used during the transferring for each of the plurality of sub-regions, using correlation data among shape of the illumination light, and a pattern shape of a mask pattern to make a dimension error of the partial pattern of each of the plurality of sub-regions smaller than a threshold when transferred to the semiconductor substrate; and forming the desired pattern by making multiple exposures on the semiconductor substrate in such a way that the partial patterns of the sub-regions are sequentially transferred by the transferring the mask pattern to the semiconductor substrate coated with a resist using the combination conditions calculated for each of the sub-regions and then the semiconductor substrate is developed.