Patent ID: 9536585
Date: 2017-01-03
CPC Classifications: G11C

Claim:
1. An improved SRAM memory cell based on a DICE structure comprising the following structure: an inverter structure for latch of logic level states, comprising a first inverter structure, a second inverter structure, a third inverter structure, and a fourth inverter structure; wherein the first inverter structure is formed through arranging a first PMOS transistor (P the second inverter structure is formed through arranging a second PMOS transistor (P the third inverter structure is formed through arranging a third PMOS transistor (P the fourth inverter structure is formed through arranging a fourth PMOS transistor (P the first storage node (A) is connected with the gate electrodes of the second PMOS transistor and the fourth NMOS transistor; the second storage node (B) is connected with the gate electrodes of the first PMOS transistor and the third NMOS transistor; the third storage node (C) is connected with the gate electrodes of the fourth PMOS transistor and the second NMOS transistor; and the fourth storage node (D) is connected with the gate electrodes of the third PMOS transistor and the first NMOS transistor; a transmission structure, for transmitting logic level states stored in storage nodes and information from bit lines or bit bar lines, consisting of a fifth NMOS transistor (N