Patent ID: 9628333
Date: 2017-04-18
CPC Classifications: G06F,H04L,Y02D

Claim:
1. A dual chipset network interface controller (‘NIC’) comprising: a high performance media access control chipset including at least one processor and an offload engine for processing of an entire protocol stack; a low performance media access control chipset including at least one processor, wherein the at least one processor of the high performance media access control chipset executes computer program instructions at a faster rate than the at least one processor of the low performance media access control chipset; control logic for determining an amount of network traffic being processed by the NIC; control logic for determining whether the amount of network traffic being processed by the NIC exceeds a predetermined threshold; control logic for, responsive to determining that the amount of network traffic being processed by the NIC exceeds a predetermined threshold, configuring the NIC to utilize the high performance media access control chipset for data communications operations; and control logic for, responsive to determining that the amount of network traffic being processed by the NIC does not exceed the predetermined threshold, configuring the NIC to utilize the low performance media access control chipset for data communications operations.