Patent ID: 9666306
Date: 2017-05-30
CPC Classifications: G11C

Claim:
1. A method for accessing a semiconductor memory device having hierarchically structured bit lines comprising: receiving address information; determining whether the address information corresponds to stored defective address information; and if the address information does not correspond to the stored defective address information: activating a first word line corresponding to the address information in a first memory mat, activating a plurality of local switches to connect a plurality of local bit lines to a plurality of global bit lines in the first memory mat, and activating a plurality of sense amplifiers connected to the global bit lines in the first memory mat; if the address information corresponds to the stored defective address information: activating a redundant word line in a second memory mat, activating a plurality of local switches to connect a plurality of local bit lines to a plurality of global bit lines in the second memory mat, and activating a plurality of sense amplifiers connected to the global bit lines in the second memory mat.