Patent ID: 9590058
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method for forming a split gate memory cell structure using a semiconductor substrate, the method comprising: forming a gate stack over the semiconductor substrate, wherein the gate stack has a conductive portion with a top surface and a dielectric portion having a bottom surface on the top surface of the conductive portion, the gate stack having a first sidewall along a side of the conductive portion and a side of the dielectric portion; forming a charge storage layer over the substrate including over the gate stack and along the first sidewall; forming a conductive layer over the charge storage layer; etching the conductive layer to leave a first conductive spacer along the first sidewall, wherein a top of the first conductive spacer is above the top surface of the conductive portion and below the top of the dielectric portion; forming a first sidewall spacer from a lower surface of the first conductive spacer to a first height below the top of the first conductive spacer and a second sidewall spacer along the first sidewall between the top of the first conductive spacer and the top surface of the dielectric portion wherein a portion of the second sidewall spacer is directly above the conductive spacer; and siliciding the first conductive spacer between the first sidewall spacer and the second sidewall spacer.