Patent ID: 9633958
Date: 2017-04-25
CPC Classifications: H01J,H01L

Claim:
1. A method comprising: providing a substrate having a circuit region and a pixel region, wherein the circuit region includes a bonding pad disposed over an interconnect structure and the pixel region includes an insulating layer having a base electrode embedded in the insulating layer; forming an etch-stop-layer (ESL) over the bonding pad in a first region such that the bonding pad is covered by the ESL; forming a pixel well in a second region that extends through the insulating layer to expose the base electrode; forming an anti-charging layer over the bonding pad and along sidewalls of the pixel well, wherein the bonding pad is covered by the ESL during the forming of the anti-charging layer over the bonding pad; and removing the anti-charging layer over the bonding pad, wherein after removing the anti-charging layer over the bonding pad, the bonding pad remains covered by the ESL.