Patent ID: 9548134
Date: 2017-01-17
CPC Classifications: G11C

Claim:
1. A semiconductor integrated circuit device, comprising: a first circuit block configured to receive data from a plurality of data I/O (input/output) lines and output test data in a test mode; and a second circuit block configured to connect the plurality of data I/O lines and the first circuit block, output the data of the plurality of data I/O lines in a normal mode and output the test data provided from the first circuit block in the test mode, wherein the first circuit block is configured to be connected to the plurality of data I/O lines, multiplex the data of the plurality of data I/O lines and output the multiplexed data as the test data in response to column addresses, and wherein the second circuit block comprises an output unit transmit the test data to selected pads of I/O pads in the test mode.