Patent ID: 9691708
Date: 2017-06-27
CPC Classifications: G06K,H01L

Claim:
1. A semiconductor package comprising: a molded semiconductor device comprising a first die; a first redistribution layer, disposed on a first side of the molded semiconductor device; a second redistribution layer, disposed on a second side of the molded semiconductor device opposite to the first side, wherein the second redistribution layer comprises a patterned metal layer having an interconnection circuit portion electrically connected to the first die and a metal ring surrounding the interconnection circuit portion and separating from the interconnection circuit portion; and a plurality of through interlayer vias (TIVs), connected to a portion of the metal ring and located under the metal ring, the through interlayer vias extending through the molded semiconductor device to be electrically connected to the first redistribution layer and the second redistribution layer.