Patent ID: 9588893
Date: 2017-03-07
CPC Classifications: G06F

Claim:
1. A computer hardware device that includes a plurality of components to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache, the plurality of components comprising: a first group of components, included in the plurality of components, receives a non-transactional store address and a first data; a second group of components, included in the plurality of components, maps the non-transactional store address to a first cache line template in a store buffer, wherein the non-transactional store address is mapped to a first cache line template in the store buffer by a free list; a third group of components, included in the plurality of components, merges the first data into the first cache line template according to a non-transactional store policy; a fourth group of components, included in the plurality of components, receives a thread-specific transactional store address and a second data; a fifth group of components, included in the plurality of components, maps the thread-specific transactional store address to a second cache line template in the store buffer; a sixth group of components, included in the plurality of components, merge the second data into a second cache line template, according to a transactional store policy; a seventh group of components, included in the plurality of components, write-back a copy of a cache line template that is in the store buffer to a cache; and an eighth group of components, included in the plurality of components, invalidate a contents of a third cache line template, wherein the invalidation frees the third cache line template from a store address mapping.