Patent ID: 9722537
Date: 2017-08-01
CPC Classifications: G04F,H03B,H03J,H03K,H03L,H03M

Claim:
1. A cyclic digital to time converter circuit and time to digital converter (DTC-TDC) circuit for use in an all digital phase locked loop (ADPLL) circuit, comprising: a plurality of controllable delay elements configured in a cyclic sequential chain configuration wherein an output of said chain is connected to its input; a phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a starting delay element in said chain, a first number of delay elements in said chain beginning at said starting delay element to function as a digital to time converter (DTC) and a second number of different delay elements following said DTC in said chain to function as a time to digital converter (TDC); and wherein the elements used for said DTC and said TDC are dynamically selected.