Patent ID: 9601073
Date: 2017-03-21
CPC Classifications: G09G,G11C

Claim:
1. A shift register comprising: a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, each of the plurality of stages including an output buffer unit for forwarding the scan pulse and an output control unit for controlling an output from the output buffer unit, wherein the output control unit provided to an nth stage includes: a first switching device configured to connect a high potential voltage line to a first node when the first switching device is turned on in response to a start pulse or a scan pulse from a (n−1)th stage, a second switching device configured to connect the first node to a low potential voltage line when the second switching device is turned on in response to a scan pulse from a (n+1)th stage, a third switching device configured to connect the first node to the low potential voltage line when the third switching device is turned on in response to a signal state of a second node, and, and a fourth switching device configured to connect a first AC power line to the second node when the fourth switching device is turned on according to a first AC voltage from the first AC power line, wherein at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof being smaller than a second area at which the gate electrode overlaps with a second electrode thereof, wherein a clock pulse is applied to the first electrode, wherein the at least one of the plurality of switching device includes: a plurality of sub-first electrodes formed parallel to one another, and having first ends and second ends, a connecting first electrode connecting the plurality of sub-first electrodes at the first ends of the plurality of sub-first electrodes, a plurality of sub-second electrodes formed parallel to one another, and having first ends and second ends, and a connecting second electrode connecting the plurality of sub-second electrodes at the first ends of the plurality of sub-second electrodes, and wherein: the connecting second electrode, the plurality of sub-first electrodes and sub-second electrodes, and the second ends of the plurality of sub-first electrodes overlap with the gate electrode, and the second ends of the plurality of sub-second electrodes and the connecting first electrode do not overlap the gate electrode.