Patent ID: 9741439
Date: 2017-08-22
CPC Classifications: G11C

Claim:
1. A memory controller for controlling a memory device, the memory controller being provided outside the memory device, the memory device including input/output terminals capable of connecting the memory controller and a memory cell array including a plurality of blocks, one of the blocks including a plurality of string units which include a plurality of strings, each of the strings including a plurality of memory cells connected in series and stacked in a first direction crossing a semiconductor substrate, the plurality of string units including a first string unit and a second string unit, the first string unit including plural first strings serially connected by a first interconnection transistor and selected by a first select transistor, the second string unit including plural second strings serially connected by a second interconnection transistor and selected by a second select transistor, a gate of the first select transistor being electrically isolated from a gate of the second select transistor, and a gate of the first interconnection transistor being electrically isolated from a gate of the second interconnection transistor, the memory controller comprising a first memory, wherein the memory controller is configured to read information of defective string units from the memory device after power on, the first memory stores the information of defective string units, the memory controller is configured to access a first address corresponding to the first string unit in a write operation or a read operation when the information does not include the first address, and the memory controller is configured not to access a second address corresponding to the second string unit in a write operation or a read operation when the information includes the second address.