Patent ID: 9728578
Date: 2017-08-08
CPC Classifications: H01L,H04N

Claim:
1. A pixel arrangement, comprising: at least one photodiode; at least one reset transistor configured to be controlled by a reset signal and coupled in use to a reset input voltage; a transfer gate transistor for each photodiode configured to transfer charge from the photodiode to a sense node, said transfer gate transistor having a control terminal configured to be controlled by a transfer gate voltage, and at least one source follower transistor configured to be controlled by the voltage on the sense node and coupled in use to a source follower voltage; and at least one capacitance coupled between the sense node and the control terminal of the transfer gate transistor; wherein during a read operation, the transfer gate voltage transitions from a first voltage level for controlling the transfer gate transistor to be turned off to a second voltage level and stays at that second voltage level for a first time period causing a voltage of said sense node to increase without turning on said transfer gate transistor to transfer charge from the photodiode to the sense node, and then the transfer gate voltage further transitions, after the first time period, from the second voltage level to a third voltage level for controlling the transfer gate transistor to be turned on and stays at that third voltage level for a second time period causing the transfer gate transistor to transfer charge from the photodiode to the sense node; and wherein the second voltage level is between the first and third voltage levels; and at least one read transistor configured to be controlled by a read voltage; wherein during said read operation, the read voltage causes the read transistor to be turned on during a read time period which includes a first sampling period where the sense node is sampled while the transfer gate voltage is at the second voltage level and a second sampling period where the sense node is sampled after the transfer gate voltage is at the third voltage level.