Patent ID: 9698100
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method of fabricating an integrated circuit, comprising: providing a substrate having a first conductive feature in a first dielectric material layer; selectively etching the first conductive feature, thereby forming a recessed trench on the first conductive feature; forming an etch stop layer on the first dielectric material layer, on the first conductive feature and sidewalls of the recessed trench; forming a second dielectric material layer on the etch stop layer; forming a first patterned mask layer on the second dielectric material layer; removing a first portion of the second dielectric material layer through the first patterned mask layer to form a first trench extending through the second dielectric material layer, wherein a bottom surface of the first trench is defined by a second portion of the second dielectric material layer; removing the first patterned mask layer; after removing the first patterned mask layer, removing the second portion of the second dielectric material layer from within the first trench such that the first trench is extended to at least the etch stop layer; and forming a second conductive feature in the extended first trench, wherein the second conductive feature is electrically connected with the first conductive feature.