Patent ID: 9645827
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. An apparatus for reducing replays in an out-of-order processor, the apparatus comprising: a first reservation station, configured to dispatch a first load micro instruction, and configured to detect and indicate on a hold bus if said first load micro instruction is a specified load micro instruction directed to retrieve an operand from one of a plurality of prescribed resources other than on-core cache memory; a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after a first number of clock cycles following dispatch of said first load micro instruction, and if it is indicated on said hold bus that said first load micro instruction is said specified load micro instruction, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has retrieved said operand; and said plurality of prescribed resources, comprising: