Patent ID: 9543230
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: first interlayer insulating layers and first conductive patterns, which are alternately stacked, the first conductive patterns comprising word lines and at least one upper select line stacked over the word lines; a second interlayer insulating layer over the first interlayer insulating layers and the first conductive patterns, the first interlayer insulating layer including a lower insulating layer between the word lines and the upper select line and an upper insulating layer between the upper select line and the second interlayer insulating layer; channel structures passing through the word lines, the upper select line and the first interlayer insulating layers without passing through the second interlayer insulating layer; contact plugs connected to the channel structures and formed on the channel structures, respectively, wherein the contact plugs pass through the second interlayer insulating layer; and a slit passing through the second interlayer insulating layer, the first interlayer insulating layers and the first conductive patterns to divide the first interlayer insulating layers and the first conductive patterns into stack structures; wherein the slit extends to a same height as the top surfaces of the contact plugs, and further comprising: a third interlayer insulating layer formed on the second interlayer insulating layer to cover the contact plugs; a source line connected to a first contact plug of the contact plugs through the third interlayer insulating layer and that extends in the same direction as the first conductive pattern; a fourth interlayer insulating layer formed on the third interlayer insulating layer; a drain contact plug connected to a second contact plug of the contact plugs through the fourth interlayer insulating layer and the third interlayer insulating layer; and a bit line formed on the drain contact plug.