Patent ID: 9654143
Date: 2017-05-16
CPC Classifications: G06F,H03M

Claim:
1. An apparatus comprising: a storage structure in which to store 128 data bits of a plurality of 128-bit data values, four parity bits of a plurality of 4-bit party values, and eight error correction code (ECC) bits of a plurality of 8-bit ECC values, each parity value corresponding to one of the plurality of the data value, a first bit of each parity value corresponding to a first quadrant of the corresponding data value, wherein the first quadrant of the corresponding data value is interleaved with a second quadrant of the corresponding data value, wherein a second bit each parity value corresponds to the second quadrant of the corresponding data value, each ECC value corresponding to one of the plurality of data values, wherein a first ECC bit, a second ECC bit, and a third ECC bit of each ECC value are assigned to first data bit of the first quadrant, wherein the second ECC bit, the third ECC bit, and fourth ECC bit of each ECC value are assigned to the first data bit of the second quadrant, wherein the third ECC bit, the fourth ECC bit, and a fifth ECC bit of each ECC value are assigned to the first data bit of a third quadrant of the corresponding data value, and wherein the fourth ECC bit, the fifth ECC bit, and a sixth ECC bit of each ECC value are assigned to the first data bit of a fourth quadrant of the corresponding data value; a parity checker to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value; an ECC checker to be activated to generate a syndrome only if the parity checker detects the parity error; and an error corrector to detect and, if the parity error corresponds to an error in a single data value bit or two physically consecutive data value bits, correct the error in the data value using the syndrome.