Patent ID: 9553094
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate on which a first region and a second region are defined; first and second gate structures arranged on the first and second regions, respectively; and a capping layer covering the first and second gate structures, wherein the first gate structure includes a first interface layer arranged on the substrate, a first high-k dielectric layer arranged on the first interface layer, a first diffusion layer arranged on the first high-k dielectric layer, a first barrier layer arranged on the first diffusion layer, a first work function adjustment layer arranged on the first barrier layer, a third barrier layer arranged on the first work function adjustment layer, and a gate metal arranged on the first work function adjustment layer, and wherein the second gate structure includes a second interface layer arranged on the substrate, a second high-k dielectric layer arranged on the second interface layer, a second diffusion layer arranged on the second high-k dielectric layer, a second barrier layer arranged on the second diffusion layer, a second work function adjustment layer arranged on the second barrier layer, a third work function adjustment layer arranged on the second work function adjustment layer, and a fourth barrier layer arranged on the third work function adjustment layer.