Patent ID: 9576630
Date: 2017-02-21
CPC Classifications: G11C

Claim:
1. A memory device, comprising: a plurality of banks including a first bank and a second bank, each bank including a plurality of memory locations; at least a first address port configured to receive a first address corresponding to a first read operation on a rising edge of a timing clock, and further configured to receive a second address corresponding to a second read operation on a falling edge of the timing clock, the first read operation and the second read operation being received by the first address port on consecutive edges of a same cycle of the timing clock, the first address corresponding to a first location in the first bank, and the second address corresponding to a second location in the second bank; and at least two read/write data ports, each configured to transfer read or write data for storage in one of the banks, and output read data from one of the banks, wherein each of the at least two read/write data ports is configured to provide a read data path and a write data path to each bank of the plurality of banks via a plurality of read/write circuits and access circuits coupled between the plurality of banks and the at least two read/write data ports, each access circuit and read/write circuit being configured to enable reading data values from a bank to the at least two read/write data ports, and being further configured to enable writing data values from the at least two read/write data ports to the bank, wherein the plurality of read/write circuits and access circuits are controlled by control signals identifying read and write pulse signals for each of the at least two read/write data ports, and wherein the at least two read/write data ports and the first address port are controlled by the same timing clock.