Patent ID: 9640252
Date: 2017-05-02
CPC Classifications: G11C,H01L

Claim:
1. A method of operating a flash memory unit, wherein the flash memory unit comprises a first split-gate flash memory unit and a second split-gate flash memory unit, wherein each of the first split-gate flash memory unit and the second split-gate flash memory unit comprises a source, a drain, a first control gate, a word line gate and a second control gate, the source of the first split-gate flash memory unit is connected with a first bit line, the source of the second split-gate flash memory unit is connected with a second bit line, the drain of the first split-gate flash memory unit is connected with the drain of the second split-gate flash memory unit and a third bit line, the first control gate of the first split-gate flash memory unit is connected with the first control gate of the second split-gate flash memory unit and a first control gate line, the second control gate of the first split-gate flash memory unit is connected with the second control gate of the second split-gate flash memory unit and a second control gate line, and the word line gate of the first split-gate flash memory unit is connected with the word line gate of the second split-gate flash memory unit and a word line, and wherein the method comprises: