Patent ID: 9748336
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: forming a gate structure on an upper surface of a semiconductor substrate, the semiconductor substrate including first and second active regions adjacent to opposing sides of the gate structure; epitaxially growing an in-situ doped semiconductor material from an upper surface of the first and second active regions to form a first conductive layer of the dual-layer source/drain regions; and epitaxially growing an in-situ doped heterojunction material from an upper surface of the first conductive layer to form a second conductive layer of the dual-layer source/drain regions, the second conductive layer having a facet shape; and annealing the first and second dual-layer source/drain regions such that the first dopants diffuse into the first and second active regions, respectively, to form first and second extension regions, wherein the first extension region extends completely beneath the first dual-layer source/drain region and the second extension region extends completely beneath the second dual-layer source/drain region, and the first and second extension regions each have sharp uniform junctions that are overlapped with respect to the gate structure.