Patent ID: 9703162
Date: 2017-07-11
CPC Classifications: G02F,H01L

Claim:
1. A substrate comprising: a base substrate, a plurality of gate lines located on the base substrate and arranged in parallel, a first insulating layer that covers the gate lines, a plurality of data lines located on the first insulating layer and perpendicular to the gate lines, a second insulating layer that covers the data lines, and pixel electrodes located in sub-pixel areas enclosed by the data lines and the gate lines; wherein the substrate further comprises: polarizing films that cover the pixel electrodes, projections of the polarizing films corresponding to the pixel electrodes; and first auxiliary gate lines arranged on the second insulating layer and parallel to the gate lines, projections of the first auxiliary gate lines corresponding to the gate lines, at least two portions on each of the first auxiliary gate lines are electrically connected with at least two corresponding portions on a corresponding gate line through at least two via holes that penetrate the first insulating layer and the second insulating layer; wherein the first auxiliary gate lines and the polarizing films are formed by performing a same patterning process to a same layer of transparent conductive material; or, the substrate further comprises: polarizing films that cover the pixel electrodes, projections of the polarizing films corresponding to the pixel electrode; and first auxiliary data lines arranged on the second insulating layer and parallel to the data lines, projections of the first auxiliary data lines corresponding to the data lines, at least two portions on each of the first auxiliary data lines are electrically connected with at least two corresponding portions on a corresponding data line through at least two via holes that penetrate the second insulating layer; wherein the first auxiliary data lines and the polarizing films are formed by performing a same patterning process to a same layer of transparent conductive material.