Patent ID: 9659666
Date: 2017-05-23
CPC Classifications: G11C

Claim:
1. A method of operating a memory system, comprising: determining that a portion of a first sub-block of a first block along a first regular column is defective, where the memory system includes a memory circuit that includes an array having a plurality of blocks, each block having a plurality of individually selectable sub-blocks of a plurality of non-volatile memory cells spanned by a plurality of access columns and where each sub-block of a block is selectable by a common select signal independently of other sub-blocks of the block, and wherein each access column is formed of a plurality of N adjacent bit lines along which the memory cells of the sub-blocks are connectable to sensing circuitry, the access columns including a plurality of regular columns and one or more redundancy columns; and in response to determining that the portion of the first sub-block along the first regular column is defective, remapping the portion of the first sub-block along the first regular column to a portion of the first sub-block along a first redundancy column, wherein neither a portion of sub-blocks of the first block other than the first sub-block along the first regular column nor a portion of blocks other than the first block along the first regular column are remapped in response thereto.