Patent ID: 9595567
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a first insulating film having a first surface; a second insulating film having a second surface; a first interconnection provided between the first insulating film and the second insulating film; a second interconnection facing the first surface and the second surface, and intersecting with the first interconnection; a third interconnection facing the first surface and the second surface, and intersecting with the first interconnection; a first variable resistance layer having a third surface, the first variable resistance layer being provided between the first interconnection and the second interconnection; and a second variable resistance layer having a fourth surface, the second variable resistance layer being provided between the first interconnection and the third interconnection, wherein the third surface is arranged at a farther position from the second interconnection than positions of both the first surface and the second surface, wherein the fourth face is arranged at a farther position from the third interconnection than positions of both the first surface and the second surface.