Patent ID: 9647445
Date: 2017-05-09
CPC Classifications: H02H

Claim:
1. An apparatus that is configured to prevent current overload at a transistor that is used in a DC-DC converter circuit, the apparatus comprising: a protection circuit that determines when the current flowing through the transistor exceeds a predetermined threshold and when the current exceeds the predetermined threshold, the protection circuit configured to deactivate the transistor, the deactivating of the transistor being effective to significantly reduce one or more of the frequency of operation and current of the DC-DC converter circuit, the deactivating of the transistor limiting the current that flows through the transistor, the limiting of the current being effective to prevent damage to the transistor in an over-current condition, the protection circuit comprising an amplifier which amplifies a value corresponding to current in the transistor, a comparator having a first input coupled to an output of the amplifier and a second input coupled to a predetermined reference voltage, and a latch having a first input coupled to an output of the comparator and a second input; a time-off circuit having an RC network with at least one capacitor and at least one resistor parallel connected to each other, a comparator having a first input coupled to the RC network, a second input coupled to a predetermined reference voltage and an output; and a channel memory latch circuit having a first input coupled to the output of the comparator of the time-off circuit, a second input coupled to an output of the latch of the protection circuit, and an output coupled to a control terminal of the transistor such that the transistor is maintained in a deactivated state by the channel memory latch circuit, the output of the channel memory latch further coupled to the time-off circuit for charging the at least one capacitor of the RC network and allowing the at least one capacitor of the RC network to discharge, the transistor is maintained in the deactivated state by the channel memory latch until the time-off circuit sets the channel memory latch and the latch of the protection circuit a period of time following deactivation of the transistor, the period of time being based on an RC delay corresponding to the RC network, the transistor being deactivated being additionally effective to prevent damage to the transistor from an over current condition.