Patent ID: 9697135
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A method for managing address translations in a multi-processor computer system, the method comprising: in response to detecting a hit in a translation lookaside buffer of a processor unit for a virtual address corresponding to an instruction, determining whether an entry corresponding to the hit will be purged from the translation lookaside buffer based, at least in part, on an indication of a change to a page table, determining whether the instruction entered an instruction pipeline of the processor unit after the processor unit received the indication of the change to the page table, allowing the hit in the translation lookaside buffer in response to determining that the instruction entered a pipeline before the processor unit received the indication of the change to the page table, suppressing the hit in the translation lookaside buffer, by forming new translation lookaside buffer entries in response to determining that the instruction entered the pipeline after the processor unit received the indication of the change to the page table, where in the new translation lookaside buffer entries are formed without purging the translation lookaside buffer, and after suppressing the hit, blocking translation in the page table for address translation of the virtual address corresponding to the instruction from the virtual address into a physical address in response to determining that the entry will be purged based, at least in part, on the indication of the change to the page table.