Patent ID: 9570150
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A memory device comprising: first to Nth cell blocks where N is a natural number greater than 2; first to (N−1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block, where K is a natural number from 1 to N−1; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein the one or more first outermost bit line sense amplifiers drive the first node with a first drivability and drive the bit line of the first cell block with a second drivability which is different from the first drivability; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein the one or more second outer most bit line sense amplifiers drive the second node with the first drivability and drive the bit line of the Nth cell block with the second drivability, wherein the first outermost bit line sense amplifier comprises: