Patent ID: 9735202
Date: 2017-08-15
CPC Classifications: G11C,H01L

Claim:
1. A method for fabricating a portion of a memory array, comprising: forming an alternating stack of word line layers and dielectric layers, the alternating stack of word line layers and dielectric layers includes a first dielectric layer arranged above a first word line layer; etching a memory hole extending through the first dielectric layer and the first word line layer; recessing a portion of the first word line layer arranged below a portion of the first dielectric layer subsequent to etching the memory hole; depositing a layer of amorphous silicon within a first region of the recessed portion of the first word line layer arranged below the portion of the first dielectric layer; depositing a layer of titanium oxide within a second region of the recessed portion of the first word line layer arranged below the portion of the first dielectric layer; and filling at least a portion of the memory hole with a conducting material subsequent to depositing the layer of amorphous silicon and the layer of titanium oxide.