Patent ID: 9684591
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A system comprising: a plurality of storage devices, each of which includes one or more flash memory chips and a device controller coupled to the flash memory chips, and the plurality of storage devices include a first storage device storing old data and a second storage device storing old parity corresponding to the old data; and a processor coupled to the storage devices, wherein: a first device controller in the first storage device is configured to generate intermediate parity based on the old data and new data, while the first device controller maintains a valid status of the new data and the old data, the processor is configured to send the intermediate parity in accordance with issuing a parity-update-write command to the second storage device, a second device controller in the second storage device is configured to receive the intermediate parity and to generate new parity based on the old parity and the intermediate parity, the processor is configured to issue an unmap-old-data command for invalidating the old data to the first storage device when a completion response regarding the parity-update write command is received from the second storage device, and the first device controller in the first storage device is configured to invalidate the old data when the unmap-old-data command is received from the processor.