Patent ID: 9652299
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. An information processing apparatus that includes a plurality of nodes, each of the nodes comprising: a CPU (Central Processing Unit) that includes a plurality of hardware threads, a first hardware thread among the plurality of hardware threads being configured to execute a first process and control a state of the first process between a first state and a second state in the first hardware thread, the first state indicating a running state and the second state indicating a stop state, and a second hardware thread in another CPU being configured to execute a second process which generates data that is required by the first process; a memory unit that stores therein a first identification information that identifies the first hardware thread wherein the first hardware thread stores the first identification information into the memory unit and transmits second identification information that identifies the first hardware thread to the second hardware thread prior to the first hardware thread executing the first process, the first hardware thread subsequently shifting the state of the first process from the first state to the second state to wait for completion of the second process when it is determined that the first process needs the data generated by the second process in order to continue execution; a receiving unit that receives the second identification information, from the second hardware thread wherein the second hardware thread executes the second process, generating and storing the data into a shared memory unit that is shared with the first hardware thread, and transmits the second identification information back to the first hardware thread upon completing the second process; and a plurality of output units that are respectively provided for the plurality of hardware threads, wherein an output unit corresponding to the first hardware thread outputs to the first hardware thread a control signal that shifts the state of the first process from the second state to the first state without invoking a process executed by an operating system, upon the second identification information received by the receiving unit matching the first identification information stored in the memory unit, the first hardware thread resuming execution of the first process, by acquiring the data stored in the shared memory unit, in response to the state of the first process shifting from the second state to the first state.