Patent ID: 9584108
Date: 2017-02-28
CPC Classifications: H03K

Claim:
1. An apparatus for managing clock duty cycle comprising: a Duty Cycle Control Circuit (DCCC) for receiving at least an input clock signal and generating an output clock signal with adjustable duty cycle; a first Low-Pass Filter with Pull-Up Resistor (LPFPR) for receiving the output clock signal with adjustable duty cycle and simultaneously averaging and raising the common mode of the output thereof; a frequency divider for generating a signal with a 50% duty cycle; a second LPFPR for receiving the generated signal with 50% duty cycle and simultaneously averaging and raising the common mode of the output thereof; and an OPAMP for receiving the outputs of the first and second LPFPRs for generating an equivalent reference signal to be fed to the DCCC as a control input, thereby facilitating correction of the duty cycle of the input clock signal.