Patent ID: 9659622
Date: 2017-05-23
CPC Classifications: G11C

Claim:
1. Non-volatile memory (NVM) circuitry comprising: a non-volatile (NV) element coupled to a first current electrode of a force path transistor and to a first current electrode of a sense path transistor, wherein a second current electrode of the force path transistor is coupled to a first force node and a second current electrode of the sense path transistor is coupled to a first sense node; a reference cell coupled to a first current electrode of a reference force path transistor and to a first current electrode of a reference sense path transistor, wherein a second current electrode of the reference force path transistor is coupled a second force node and a second current electrode of the reference sense path transistor is coupled to a second sense node; a first capacitive element having a first electrode and having a second electrode coupled to a first input of an amplifier stage; and a second capacitive element having a first electrode and having a second electrode coupled to a second input of the amplifier stage, wherein the NVM circuitry is configured to, during a first phase of a sensing operation, couple the first sense node to the first electrode of the first capacitive element and couple the second sense node to the first electrode of the second capacitive element, and during a second phase of the sensing operation, couple the first sense node to the first electrode of the second capacitive element and couple the second sense node to the first electrode of the first capacitive element.