Patent ID: 9601185
Date: 2017-03-21
CPC Classifications: G11C,H01L

Claim:
1. A system, comprising: a semiconductor substrate; a random access memory defined in the semiconductor substrate; a logic controller defined in the semiconductor substrate adjacent the random access memory, and configured to decode addresses of memory cells of the random access memory and to perform read/write control for the random access memory; the semiconductor substrate having, for the random access memory and the logic controller, an active upper layer comprising: wherein the second highly doped terminals are coupled to a common power supply dedicated to the random access memory, within the random access memory; wherein the upper doping well is coupled to a second substrate power supply dedicated to the logic controller, within the logic controller; wherein the second high doped terminals are coupled to an other power supply, within the logic controller; an electrically conducting path coupling the upper doping well of the random access memory and the logic controller so that the common power supply and the second substrate power supply are merged; and a switching unit configured to selectively electrically short the common power supply, second substrate power supply, and the other power supply to one another and to the second highly doped terminals of the logic controller; wherein the system is configured to implement at least one radio communication mode, an operation of the at least one radio communication mode being inactive when the switching unit is not coupling the second highly doped terminals of the logic controller and the upper doping well of the logic controller.