Patent ID: 9582632
Date: 2017-02-28
CPC Classifications: G06F

Claim:
1. A wiring topology display method, comprising: obtaining layout information indicating positions of components included in a target circuit and a position of wiring that couples the components; dividing, by a computer, first wiring included in the target circuit into first pieces of partial wiring, under a condition, based on the layout information, and generating partial wiring information indicating the first pieces of partial wiring; identifying, for each of the first pieces of partial wiring, a first length of the partial wiring and a first angle of the partial wiring for a vector of a space indicated by the layout information based on orientation of each of the first pieces of partial wiring; identifying, from among the first pieces of partial wiring, one or more combinations of second pieces of partial wiring based on the first length and the first angle, the second pieces of partial wiring having second lengths which are a certain length or more, second angles which are different by a certain angle, and a distance between the second pieces of partial wiring which is a certain distance or less; identifying, from among the one or more combinations, a group having the combination including pieces of identical partial wiring; and symbolizing third pieces of partial wiring at both ends of the group and fourth pieces of partial wiring between the third pieces of partial wiring.