Patent ID: 9634130
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed above the first semiconductor layer; a first trench formed in a surface of the second semiconductor layer, the first trench being shaped with a stripe; a gate electrode formed in the first trench with an insulator film interposed between the gate electrode and the first trench; a third semiconductor layer of the first conductivity type formed selectively between two first trenches in an extending direction of the two first trenches, in a checkered pattern layout; a fourth semiconductor layer of the second conductivity type formed selectively in a surface of the third semiconductor layer, in a checkered pattern layout; an emitter electrode in contact with the third semiconductor layer and the fourth semiconductor layer; a collector electrode in contact with the first semiconductor layer; and a second trench formed between the two first trenches in the extending direction of the two first trenches, and the second trench being formed between two third semiconductor layers, such that the two third semiconductor layers are disposed between a first part of the two first trenches, and the second trench is disposed between a second part of the two first trenches, the semiconductor device further comprising a first electrical conductor buried in the second trench with an insulator film interposed between the first electrical conductor and the second trench, the first electrical conductor being spaced apart from the gate electrode.