Patent ID: 9672036
Date: 2017-06-06
CPC Classifications: G06F

Claim:
1. A processor comprising: a completion mask register comprising a first plurality of data fields, wherein each of the first plurality of data fields in the completion mask register corresponds to a multiple of a stride length from a beginning address for a corresponding data element in a memory, wherein for each data field of the first plurality of data fields in the completion mask register, a first value indicates the corresponding element has not yet been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded from the memory, and wherein the beginning address is initialized to zero minus the stride length responsive to the beginning address starting at zero; a decode stage to decode a first instruction specifying the completion mask register, the stride length and a set of load operations corresponding to one or more of the first plurality of data fields; and one or more execution units, responsive to the decoded first instruction, to: wherein the values of the data fields in the completion mask register are maintained after a fault of the memory, the values in the completion mask register used to resume the loading and storing of the corresponding data elements from the memory that have not yet been loaded according to the values of the completion mask register.