Patent ID: 9703696
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. A method, comprising: receiving, via a computer processor, a request for allocating one or more data blocks of a programmable logic design of an integrated circuit to physical memory of the integrated circuit; when the request comprise an indication of one or more particular physical memory areas of a total set of physical memory areas of the integrated circuit to allocate the one or more data blocks to: determining, via the computer processor, whether the request can or cannot be granted for allocating the one or more data blocks to the one or more particular physical memory areas; and when the request can be granted, binding, via the processor, the one or more data blocks to the one or more particular physical memory areas according to the request; otherwise, when the request does not comprise the indication of the one or more particular physical memory areas of the total set of physical memory areas of the integrated circuit to allocate the one or more data blocks to: organizing the physical memory in a manner that provides fine interleaving.