Patent ID: 9690889
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A computer-implemented static timing analysis method for determining an expected timing of a signal path of an integrated circuit design, the method comprising: obtaining, by a computer, a circuit representation defining the integrated circuit design; determining, by the computer, a timing derate for a target cell on the signal path, wherein the timing derate is read from a derate table, the timing derate representing variation in a propagation delay through the target cell for a default design condition surrounding the target cell; determining, by the computer, an expected design condition surrounding the target cell in the integrated circuit design; determining, by the computer, a derate adjustment factor based on the expected design condition of the target cell; adjusting, by the computer, the timing derate read from the derate table using the derate adjustment factor to generate an adjusted timing derate; determining, by the computer, the expected timing of the signal path based on the adjusted timing derate for the target cell; and updating, by the computer, the circuit representation to modify the integrated circuit design when a timing violation is detected; wherein the adjusted timing derate D D D  α is the derate adjustment factor, and D