Patent ID: 9711229
Date: 2017-07-18
CPC Classifications: G11C,H01L

Claim:
1. An apparatus, comprising: a first NAND string including a first memory cell transistor in series with a first select transistor, a gate of the first memory cell transistor connected to a first word line, the first select transistor connected to a first bit line; a second NAND string including a second memory cell transistor in series with a second select transistor, a gate of the second memory cell transistor connected to a second word line physically shorted to the first word line, the second select transistor connected to the first bit line; and a control circuit configured to set the first bit line to a selected bit line voltage at a first point in time during a memory operation, the control circuit configured to set a gate of the first select transistor to a first voltage at the first point in time and set a gate of the second select transistor to a second voltage different from the first voltage at the first point in time.