Patent ID: 9613580
Date: 2017-04-04
CPC Classifications: G09G

Claim:
1. A display device, comprising: a liquid crystal panel; a gate drive circuit, configured to provide a gate drive signal to the liquid crystal panel; a data drive circuit, configured to provide a data drive signal to the liquid crystal panel; and a timing controller, configured to receive a frame of an input signal comprising an odd-field signal and an even-field signal, to provide a data control signal and a data signal to the data drive circuit, and to provide a gate control signal to the gate drive circuit, wherein the gate control signal comprises an output enable (OE) signal and a gate scanning clock (GCK) signal, wherein in a period of the data signal in one line, the GCK signal comprises two clock pulses having a first clock pulse and a second clock pulse, and the OE signal comprises one pulse signal; wherein in scanning the odd field, at a first time period corresponding to the first clock pulse of the two clock pulses of the GCK signal, the gate drive circuit outputs the gate drive signal in a high potential to drive one of odd-line gate buses, and at a second time period corresponding to the second clock pulse of the two clock pulses of the GCK signal, the gate drive circuit outputs the gate drive signal in a low potential to drive one of even-line gate buses; and wherein in scanning the even field, at the first time period, the gate drive circuit outputs the gate drive signal in the low potential to drive one of the odd-line gate buses, and at the second time period, the gate drive circuit outputs the gate drive signal in the high potential to drive one of the even-line gate buses.