Patent ID: 9614007
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A memory array, comprising: a first memory cell; a second memory cell directly adjacent to the first memory cell along a lateral direction, and vertically offset relative to the first memory cell; first and second wordlines over a substrate, the first and second word lines being at a common elevation with the first memory cell being disposed over the first word line and the second memory cell being disposed over the second wordline; and a bitline extending across the first and second memory cells and being electrically coupled to the first and second memory cells; the first memory cell being in a first vertical stack having a conductive extension material between the first memory cell and the bitline; the second memory cell being in a second vertical stack lacking a conductive extension between the second memory cell and the bitline, the second vertical stack comprising a first electrode material over and spaced from the second wordline, a programmable material over the first electrode material and an upper electrode material over the programmable material and in physical contact with the bitline.