Patent ID: 9601164
Date: 2017-03-21
CPC Classifications: G11C,H01L

Claim:
1. An array structure of a single-poly nonvolatile memory, the array structure comprising: a first word line; a second word line; a first source line; a second source line; a first erase line; a first bit line; a second bit line; a first MTP cell comprising a first PMOS transistor, a second PMOS transistor and a first NMOS transistor, wherein a source terminal of the first PMOS transistor is connected to the first source line, a gate terminal of the first PMOS transistor is connected to the first word line, a drain terminal of the first PMOS transistor is connected to a source terminal of the second PMOS transistor, a drain terminal of the second PMOS transistor is connected to the first bit line, a gate terminal of the second PMOS transistor is connected to a gate terminal of the first NMOS transistor, and a drain terminal and a source terminal of the first NMOS transistor are connected to the first erase line; and a first OTP cell comprising a third PMOS transistor and a fourth PMOS transistor, wherein a source terminal of the third PMOS transistor is connected to the second source line, a gate terminal of the third PMOS transistor is connected to the second word line, a drain terminal of the third PMOS transistor is connected to a source terminal of the fourth PMOS transistor, a drain terminal of the fourth PMOS transistor is connected to the second bit line, and a gate terminal of the fourth PMOS transistor is a floating state.