Patent ID: 9734097
Date: 2017-08-15
CPC Classifications: G06F,G11C

Claim:
1. An apparatus, comprising: a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase, the memory further configured to provide information indicating that the memory is not available to perform the command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform the command responsive, at least in part, to receiving the command after the variable latency period, wherein the information is indicative of a remaining length of the variable latency period and the remaining length is one of a relatively short, normal, or long period of time, wherein the memory is further configured to receive or provide data associated with the command only when the memory is available to perform the command.