Patent ID: 9727162
Date: 2017-08-08
CPC Classifications: G06F,G09G

Claim:
1. A GOA driving circuit applied for a flat panel display device, comprising: a front-stage circuit comprising a plurality of cascade-connected GOA driving subunits; a middle-stage circuit comprising two cascade-connected GOA driving subunits, wherein an input terminal of a former stage of the GOA driving subunits in the middle-stage circuit is electrically connected to an output terminal of a last stage of the plurality of GOA driving subunits in the front-stage circuit; a rear-stage circuit comprising a plurality of cascade-connected GOA driving subunits, wherein an input terminal of a first stage of the plurality of GOA driving subunits in the rear-stage circuit is electrically connected to an output terminal of a latter stage of the GOA driving subunits in the middle-stage circuit; wherein the GOA driving subunits in the front-stage circuit, the middle-stage circuit and the rear-stage circuit are configured for receiving a first clock signal and a second clock signal to sequentially generate corresponding gate driving signals respectively, an interruption period is set in the first clock signal and the second clock signal to generate an interruption between the sequentially generated gate driving signals, and the flat panel display device is configured for performing a touch detection operation in the interruption period; the interruption period is greater than a time of one pulse signal and less than a time of one frame image; wherein the first clock signal and the second clock signal each comprise a first period, the interruption period, a restore period and a second period; in the first period, the first clock signal and the second clock signal respectively output pulse signals with just opposite polarities, the GOA driving subunits in the front-stage circuit of the GOA driving circuit sequentially output a part of the sequentially generated gate driving signals to drive a part of gate lines of the flat panel display device respectively; in the interruption period, the first clock signal is maintained at a first logic and the second clock signal is maintained at a second logic, a polarity of the first logic and a polarity of the second logic are opposite; and in the interruption period, the middle-stage circuit and the rear-stage circuit of the GOA driving circuit stop outputting of gate driving signal; in the restore period, the first clock signal is maintained at the second logic, the second clock signal outputs one second logic signal and one first logic signal, and the middle-stage circuit of the GOA driving circuit restores to output succeeding two gate driving signals; in the second period, the first clock signal and the second clock signal respectively output pulse signals with just opposite polarities, the rear-stage circuit of the GOA driving circuit outputs the remaining of the sequentially generated gate driving signals.