Patent ID: 9612909
Date: 2017-04-04
CPC Classifications: G06F

Claim:
1. A computer system, comprising: an interrupt controller to notify a bus error occurrence; and a multithreaded processor, wherein the multithreaded processor includes: wherein virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's; wherein, when notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU and stops other virtual VCPUs regardless of an execution sequence settled in the schedule register, wherein the first virtual CPU changes the execution sequence before the bus reinitialization so as to operate only the first virtual CPU and a second virtual CPU using a device not coupled to a bus where an error occurred, wherein the first virtual CPU requests a third virtual CPU after bus reinitialization, using a device coupled to a bus causing an error, to reinitialize a device to be used and restores the execution sequence to an original state, and wherein the third virtual CPU reinitializes a device to be used.