Patent ID: 9590107
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method for forming integrated circuits comprising the steps of: forming a stack comprising a temporary layer and a channel layer on a substrate inside a trench in a field dielectric material; removing portions of the field dielectric material to expose sides of a channel portion of the temporary layer and sides of a channel portion of the channel layer; removing the channel portion of the temporary layer to form a tunnel below the channel portion of the channel layer; filling the tunnel and volumes vacated by removing portions of the field dielectric material with a sacrificial material; removing a respective portion of the temporary layer and a respective portion of the channel layer in the trench on each side and in spaced relation to the sacrificial material in the tunnel and the channel portion of the channel layer to define empty source/drain volumes; replacing the temporary layer in the trench between the empty source/drain volumes and the sacrificial material in the tunnel with spacer features; forming source/drain features inside the source/drain volumes; removing the sacrificial material; and forming gate dielectric layers and a gate feature surrounding at least a portion of the channel portion of the channel layer.