Patent ID: 9576667
Date: 2017-02-21
CPC Classifications: G11C

Claim:
1. An apparatus, comprising: a memory block including a plurality of subblocks of memory cells, each of the plurality of subblocks of memory cells including a plurality of access line groups coupled in series in a string of memory cells; a control unit configured to program a first access line group of each subblock of the plurality of subblocks during a program operation and to program a second access line group of each subblock of the plurality of subblocks that is coupled in series with the first access line group of the same subblock during the program operation responsive to completing the programming of the first access line group of each of the plurality of subblocks, wherein the control unit is further configured to program a first memory cell of the first access line group of a subblock of the plurality of subblocks a first number of times and to program a second memory cell of the first access line group of the subblock of the plurality of subblocks a second number of times different than the first number, and wherein the control unit is further configured to program the second memory cell the second number of times responsive to programming a third memory cell adjacent the second memory cell.