Patent ID: 9601545
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method of forming an integrated chip, comprising: forming one or more lower metal interconnect structures within a dielectric layer over a substrate; forming a plurality of MIM (metal-insulator-metal) structures over the one or more lower metal interconnect structures, wherein the plurality of MIM structures respectively comprise a lower electrode separated from an upper electrode by a first dielectric layer; forming one or more upper metal interconnect structures over the plurality of MIM structures, wherein the one or more lower metal interconnect structures or the one or more upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection; forming a plurality of RRAM cells concurrent with forming the plurality of MIM structures, wherein the plurality of RRAM cells are formed in an embedded memory region laterally separated from a decoupling region comprising the plurality of MIM structures, wherein the plurality of RRAM cells respectively comprise a second lower electrode separated from a second upper electrode by a second dielectric layer; and wherein the lower electrode is a same material as the second lower electrode, the upper electrode is a same material as the second upper electrode, and the first dielectric layer is a same material as the second dielectric layer.