Patent ID: 9558069
Date: 2017-01-31
CPC Classifications: G06F,G11C

Claim:
1. A method of failure mapping, performed by one or both of a processor located in a storage node or a processor located in a non-volatile solid-state storage of the storage node, comprising: distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are coupled as a storage cluster, wherein each of the plurality of storage nodes has a corresponding non-volatile solid-state storage with flash memory and wherein the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable; mapping physical addresses of defects in the flash memory, on a basis of one of per flash package, per flash die, per flash plane, per flash block, per flash page, or per physical memory address; and mapping around the defects in the flash memory during accesses to the user data.