Patent ID: 9679649
Date: 2017-06-13
CPC Classifications: G11C

Claim:
1. A content addressable memory comprising at least one CAM cell comprising: first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data; and a detection circuit coupled to a first supply voltage rail of the first and second inverters and adapted to detect a CAM hit or miss based on the voltage level on said first supply voltage rail following the activation of the first or second transistor.