Patent ID: 9640478
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate including an upper surface and a plurality of active semiconductor elements; a low dielectric film wiring line laminated structure portion which is provided on the upper surface of the semiconductor substrate, and which has a laminated structure including a plurality of low dielectric films and a plurality of wiring lines, each of the low dielectric films having a relative dielectric constant of 3.0 or lower, and at least one of said plurality of low dielectric films including a porous type film; a passivation film made of an inorganic material and formed on an upper surface of the low dielectric film wiring line laminated structure portion; and an organic resin layer including an upper portion which directly contacts with and covers an upper surface of , and a side peripheral portion which directly contacts with and covers a side peripheral surface of the low dielectric film wiring line laminated structure portion, the organic resin layer protecting at least one of the low dielectric films of the low dielectric film wiring line laminated structure portion from peeling off from an under layer or the upper surface of semiconductor substrate, wherein the under layer is formed by another one of the low dielectric films, wherein the low dielectric films of the low dielectric film wiring line laminated structure portion, the passivation film, and the upper portion of the organic resin layer respectively include a plurality of through openings for an electric connection of the active semiconductor elements, and wherein a side peripheral surface of the passivation film is located inward from the side peripheral surface of the low dielectric film wiring line laminated structure portion.