Patent ID: 9704449
Date: 2017-07-11
CPC Classifications: G09G

Claim:
1. A gate driving circuit comprising m stages (where m is an integer of 4 or greater), each of which outputs a gate signal and is sequentially connected in a cascade arrangement, the gate driving circuit comprising: an (m−1)-th stage configured to externally receive a first dummy signal for a first time period to control a turn-off; an m-th stage configured to externally receive a second dummy signal for the first time period to control the turn-off; an (m−2)-th stage configured to receive an m-th carry signal for a second time period from the m-th stage and externally receive the second dummy signal for the second time period to control the turn-off; and an (m−3)-th stage configured to receive an (m−1)-th carry signal for the second time period from the (m−1)-th stage and externally receive the first dummy signal for the first time period to control the turn-off, wherein the first time period is longer than the second time period.