Patent ID: 9543934
Date: 2017-01-10
CPC Classifications: G06F,H03K,H03L

Claim:
1. A method comprising: inputting respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks, each clocked circuit block having a respective clock input port; determining by a computer processor, a plurality of solution sets, each solution set including a multiplier value and an associated set of values of divisors, wherein: determining respective sets of clocked error values for the plurality of solution sets, each set of clocked error values including for each clocked circuit block a respective clocked error value that is a function of the respective requested frequency value of the clocked circuit block, the oscillator frequency, the multiplier value, and the value of the divisor corresponding to the clocked circuit block; determining for each solution set, a respective solution-set-error value as a function of the respective sets of clocked error values; selecting one of the solution sets having a respective solution-set-error value that is less than the respective solution-set-error value of each other of the solution sets; and storing the one solution set in a computer-readable storage device.