Patent ID: 9594661
Date: 2017-03-14
CPC Classifications: G06F

Claim:
1. A computer-implemented method for idle time accumulation in a computer system comprising a configuration that comprises a plurality of cores and an operating system (OS)-image configurable between a single thread (ST) mode and a multithreading (MT) mode in a logical partition, the MT mode supporting multiple threads on shared resources per core simultaneously, the method comprising: executing a query instruction on an initiating core of the plurality of cores, the executing comprising: based on determining that the logical partition is in the ST mode, determining an MT-disabled missed opportunity value as a sum of the total-dispatch times for all of the cores within the logical partition scaled by one less than a maximum number of threads supported per core by hardware of the computer system; and based on determining that the logical partition is in the MT mode, determining an MT-enabled missed opportunity value as a sum of the multithreading idle time values for all of the cores within the logical partition.