Patent ID: 9632958
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A system for migrating at least one stash transaction between a plurality of processor cores, wherein each of the plurality of processor cores includes a cache register, the system comprising: a main memory, for storing a plurality of data frames and an input/output memory management unit (IOMMU) mapping table that includes a mapping between a logical input/output (I/O) device number (LIODN) corresponding to an I/O device and a corresponding stash transaction destination identification (ID), wherein the stash transaction destination ID includes a cache register ID associated with a cache register of one of the processor cores of the plurality of processor cores; a first I/O device, connected to the main memory, for generating the plurality of data frames and initiating direct memory access (DMA) transactions for storing the plurality of data frames in the main memory, and generating a stash transaction request corresponding to each data frame of the plurality of data frames; a queue manager, connected to the first I/O device, for receiving and storing a first stash transaction request corresponding to a first data frame of the plurality of data frames, generating a first stash transaction command based on the first stash transaction request, and re-generating the first stash transaction command when a stash replay command is received; a stash transaction migration management unit (STMMU), connected to the main memory and the queue manager, for determining a first processor core ID of a first processor core that executes a first thread associated with the first I/O device when the first thread is scheduled-out from the first processor core, determining a second processor core ID of a second processor core that executes the first thread after the first thread is scheduled-in, comparing the first and second processor core IDs, updating a stash transaction destination ID field of the IOMMU mapping table corresponding to the first I/O device when the first and second processor core IDs are different by replacing a first stash transaction destination ID with a second stash transaction destination ID, and generating the stash replay command when the first and second processor core IDs are different, wherein the first stash transaction destination ID includes a first cache register ID associated with a cache register of the first processor core and the second stash transaction destination ID includes a second cache register ID associated with a cache register of the second processor core; and an IOMMU, connected to the main memory, the first I/O device, the queue manager, and the plurality of processor cores, for validating the DMA transactions initiated by the first I/O device using a LIODN associated with the first I/O device, and determining a stash destination for the first stash transaction command received from the queue manager by accessing the IOMMU mapping table, wherein the IOMMU determines the cache register of the first processor core as the stash destination for the first data frame before the first thread is scheduled-out from the first processor core and the cache register of the second processor core as the stash destination for the first data frame when the first thread is scheduled-in to the second processor core and the stash replay command is generated.