Patent ID: 9536793
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method comprising: providing a substrate including adjacent transistor regions; forming adjacent fin structures, spaced from each other, each over a different transistor region and including a fin and a hardmask over the fin; forming a gate dielectric and metal spacer consecutively on each side of each fin structure; forming a liner on exposed surfaces of the hardmask, the gate dielectric and metal spacer of each fin structure, and the substrate; forming an interlayer dielectric (ILD) filling spaces between the fin structures and coplanar with an upper surface of the liner over each fin structure; removing the liner over the fin structures; removing the hardmask and recessing the liners, the gate dielectrics and metal spacers of each fin structure creating cavities in the ILD; forming a low-k spacer on sidewalls of and over the metal spacers and liners in each cavity; forming a top source/drain (S/D) structure over the gate dielectric and fin in each cavity; and forming a top S/D contact over each top S/D structure.