Patent ID: 9608088
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A process of forming an integrated circuit, comprising: forming an extended drain MOS transistor including: forming an extended drain in a substrate, said extended drain including a drift region with alternating field gap drift regions and active gap regions, and said drift region abuts a channel region of said extended drain MOS transistor; forming field oxide elements in said extended drain adjacent to said field gap drift regions and opposite from said channel region, such that said extended drain extends below said field oxide elements; forming a gate dielectric layer on said substrate over said channel region and said drift region; forming a gate on said gate dielectric layer over said channel region, said gate including field plates over said field gap drift regions and extending onto said field oxide elements; and forming a drain contact diffused region in said extended drain, the drain contact diffused region having a higher doping concentration than said extended drain, the drain contact diffused region abutting said active gap regions and interleaving with said field oxide elements.