Patent ID: 9721886
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; an additional patterned RDL line, included in the RDL, having two additional RDL sidewalls; additional protective sidewalls directly contacting the two additional RDL sidewalls; an additional seed layer including the material and coplanar with the seed layer; and an additional barrier layer coplanar with the barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width; wherein (a) the additional RDL has an additional RDL line width orthogonal to and extending between the two additional RDL sidewalls, and (b) the additional seed and barrier layers each include a width parallel to and wider than the additional RDL line width.