Patent ID: 9666270
Date: 2017-05-30
CPC Classifications: G06F,G11C

Claim:
1. A nonvolatile memory system comprising: a nonvolatile memory device including a multi-level cell which stores M-bit data, M being an integer equal to or greater than 3, at a time and M number of latches for respectively storing M-bit data on a single bit basis; and a controller suitable for sequentially latching M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputting the latched M-bit data in the M number of latches during a second half read period, wherein the M number of latches comprise: a main latch suitable for latching each of the M-bit data to be inputted/outputted to/from the multi-level cell; a cache latch suitable for latching each of the M-bit data to be inputted/outputted to/from an input/output circuit; and M minus 2 number of auxiliary latches electrically suitable for latching one of bits of the M-bit data latched in the main latch or the cache latch, wherein, during the first half read period, the controller sequentially latches each of M-bit data into the main latch on a single bit basis, and latches each of the M-bit data, which is previously latched in the main latch, into one of the cache latch and the M minus 2 number of auxiliary latches, and wherein the controller sequentially outputs the latched M-bit data in the M number of latches during the second half read period after all M-bit data are latched in the M number of latches.