Patent ID: 9543153
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. An integrated circuit (IC) comprising: a semiconductor on-insulator (SOI) substrate region made up of a handle substrate region, an insulating layer arranged over the handle substrate region, and a semiconductor layer arranged over the insulating layer; a recess extending downward from an upper surface of the semiconductor layer and terminating in the handle substrate region, thereby defining a recessed handle substrate surface and sidewalls extending upwardly from the recessed handle substrate surface to meet the upper surface of the semiconductor layer; a first semiconductor device disposed on the recessed handle substrate surface, the first semiconductor device including a first gate having a lowermost gate surface which is arranged at a first height below a second height of a lowermost surface of the insulating layer; and a second semiconductor device disposed on the upper surface of the semiconductor layer.