Patent ID: 9703966
Date: 2017-07-11
CPC Classifications: G06F,G09C,H04L

Claim:
1. Data processing apparatus comprising: a single instruction multiple data register file; and single instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; wherein said single instruction multiple data processing circuitry is configured to be controlled by a first further program instruction and a second further program instruction to perform a further processing operation upon an input digest data value to generate an output digest data value, the first further program instruction being operable to generate, in dependence on said input digest data value, a first output operand representative of a first portion of the output digest data value, the second further program instruction being operable to generate, in dependence on said input digest data value, a second output operand representative of a remaining portion of the output digest data value, wherein the input digest data value comprises a sequence of data elements held within said single instruction multiple data register file, said first portion and said remaining portion of the output digest data value being dependent upon all data elements within said sequence of data elements, wherein said first portion and said remaining portion represent portions of different significance within the output digest data value, and wherein said further processing operation is an iterative processing operation consuming successive words of data and at least portions of intermediate hash values to generate an output hash value.