Patent ID: 9666272
Date: 2017-05-30
CPC Classifications: G11C

Claim:
1. A resistive change element array comprising: a plurality of word lines; a plurality of bit lines; a plurality of reference bit lines; a plurality of resistive change elements, wherein each resistive change element has a first terminal and a second terminal and wherein said first terminal of each resistive change element is in electrical communication with a word line and said second terminal of each resistive change element is in electrical communication with a bit line; a plurality of resistive reference elements, wherein each resistive reference element has a first terminal and a second terminal and wherein said first terminal of each resistive reference element is in electrical communication with a word line and said second terminal of each resistive reference element is in electrical communication with a reference bit line; a memory operation circuit operably coupled to said plurality of word lines, said plurality of bit lines, and said plurality of reference bit lines, said memory operation circuit including circuitry capable of providing a discharge current through at least one selected resistive change element and a discharge current through at least one selected resistive reference element; wherein each of said resistive change elements is adjustable between a first non-volatile resistive state and a second non-volatile resistive state responsive to electrical stimuli applied to said plurality of word lines and said plurality of bit lines; wherein each of said resistive change elements has a fixed electrical resistance value that is less than said first non-volatile resistive stat and greater than said second non-volatile resistive state.