Patent ID: 9691669
Date: 2017-06-27
CPC Classifications: G01B,G01R,H01L

Claim:
1. A method of determining a thickness of a fully depleted silicon-on-insulator layer disposed in a CMOS integrated circuit, the method comprising the steps of: providing, during fabrication of the CMOS integrated circuit, at least one test circuit, the at least one test circuit including an isolated fully depleted silicon-on-insulator layer disposed above an isolated buried oxide layer, wherein a desired thickness of the isolated fully depleted silicon-on-insulator layer and a desired thickness of the isolated buried oxide layer on the at least one test circuit is representative of, respectively, a thickness of the isolated fully depleted silicon-on-insulator layer and a thickness of the isolated buried oxide layer on the CMOS integrated circuit; measuring a total capacitance of the at least one test circuit that also includes a gate dielectric disposed above the isolated fully depleted silicon-on-insulator layer to obtain a total capacitance measurement; measuring a gate dielectric capacitance of the at least one test circuit that also includes a gate dielectric disposed above the isolated fully depleted silicon-on-insulator layer to obtain a gate dielectric capacitance measurement; measuring the buried oxide capacitance of the at least one test circuit to obtain a buried oxide capacitance measurement; calculating a fully depleted silicon-on-insulator layer capacitance based upon the gate dielectric capacitance measurement, the buried oxide capacitance measurement and the total capacitance measurement; and determining the thickness of a fully depleted silicon-on-insulator layer using the fully depleted silicon-on-insulator layer capacitance.