Patent ID: 9607564
Date: 2017-03-28
CPC Classifications: G09G

Claim:
1. A clock generator circuit of a liquid crystal display panel, comprising: a charge sharing switch unit, having an output end, the charge sharing switch unit being electrically coupled between a plurality of data lines and a plurality of pixel units, the charge sharing switch unit being configured to receive a first control signal and output, through the output end thereof, a first-polarity voltage according to the first control signal, wherein the first-polarity voltage is constituted by voltages of a plurality of first-polarity display data transmitted on the data lines; a first capacitor, having a first end and a second end, the first end of the first capacitor being electrically coupled to the output end of the charge sharing switch unit and the second end of the first capacitor being electrically coupled to a first low voltage level; a first switch, having a first end and a second end, the first end of the first switch being electrically coupled to the first end of the first capacitor and the second end of the first switch being electrically coupled to an output end of the clock generator circuit; a second switch, having a first end and a second end, the first end of the second switch being electrically coupled to a high voltage level and the second end of the second switch being electrically coupled to the output end of the clock generator circuit; a third switch, having a first end and a second end, the first end of the third switch being electrically coupled to the first low voltage level and the second end of the third switch being electrically coupled to the output end of the clock generator circuit; and a fourth switch, having a first end and a second end, the first end of the fourth switch being electrically coupled to a second low voltage level and the second end of the fourth switch being electrically coupled to the output end of the clock generator circuit, wherein, the output end of the clock generator circuit is used to output a clock signal.