Patent ID: 9637810
Date: 2017-05-02
CPC Classifications: C22C,C23C,H01L

Claim:
1. A device, comprising: a substrate, wherein the substrate comprises a silicon fin; a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen; a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen; a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material; an NMOS metal gate electrode above the second dielectric material and between the pair of gate spacers, wherein the NMOS metal gate electrode comprises: a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant; a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; and a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer.