Patent ID: 9568941
Date: 2017-02-14
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A memory controller comprising: a clock scaler configured to receive a first clock signal, a first frequency control signal, and a second frequency control signal and configured to generate a second clock signal based on the first clock signal, the first frequency control signal, and the second frequency control signal, a frequency of the second clock signal being configured to increase based on the first frequency control signal, and the frequency of the second clock signal being configured to decrease based on the second frequency control signal; a bus component configured to operate based on the second clock signal and to generate a level signal corresponding to a current operating state of the bus component; and a level monitor configured to generate the first frequency control signal and the second frequency control signal based on the level signal, a result of comparison between a first reference time and a time period during which a value of the level signal is greater than a first threshold value, and a result of comparison between a second reference time and a time period during which the value of the level signal is less than a second threshold value.