Patent ID: 9680470
Date: 2017-06-13
CPC Classifications: G11C,H01L,H03K

Claim:
1. A digital logic circuit, comprising: a plurality of MOSFET transistors coupled by way of a plurality of controllable current paths to at least a first and second logic node to produce a predefined logic function: wherein the plurality of transistors includes at least one precharge transistor that couples a precharge node to the first logic node in response to a first clock signal; wherein the plurality of transistors includes at least one evaluation transistor that couples a discharge node to the second logic node in response to a second clock signal; wherein the plurality of transistors are configured to selectively couple an output node to the first or second logic node in response to at least one input signal, the plurality of transistors having gates coupled to receive at least one input signal and source-drain paths coupled to the at least one output node; wherein each of the plurality of transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region.