Patent ID: 9633213
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A system comprising: A. processor circuitry having data leads and debug/profile data leads; B. test interface circuitry having processor debug/profile leads coupled to the debug/profile leads of the processor circuitry and having memory debug/profile leads; C. memory circuitry having data leads coupled with the data leads of the processor circuitry and having debug/profile data leads coupled with the memory debug/profile leads, the memory circuitry including a data portion and a data page attribute table portion for the data portion, the page attribute table portion including a non-secure bit and an emulation bit; D. secure emulation logic having an input coupled to the non-secure bit, an input coupled to the emulation bit and a secure emulation enable output; and E. gating circuitry having a first input coupled with the a secure emulation enable output, a second input coupled with the data portion, and an output coupled with the memory debug/profile leads; the memory circuitry including first cache memory having a data portion for cached data, cached data tag information, and a cached data page attribute table for the cached data, and a program portion for cached program instructions, cached program tag information, and a cached program page attribute table for the cached program instructions.