Patent ID: 9691489
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. A nonvolatile semiconductor memory device comprising: a memory cell array which comprises: a memory string having a plurality of memory cells connected in series, each of the memory cells being configured programmable to plural written states from an erased state, the plural written states including a state assigned to a lowest threshold voltage distribution among the plural written states; a first select transistor connected to one end of the memory string; a second select transistor connected to the other end of the memory string; a bit line connected to the memory string via the first select transistor; a source line connected to the memory string via the second select transistor; and a word line connected to a control gate electrode of each of the memory cells; and a control circuit configured to apply a reading voltage to the control gate electrode of a selected memory cell in the memory string to determine whether the selected memory cell is conductive or not, and thereby execute data reading of the selected memory cell, the control circuit being configured capable of: