Patent ID: 9666257
Date: 2017-05-30
CPC Classifications: G11C

Claim:
1. An apparatus comprising: an array of magnetoresistive (MRAM) bitcells having first and second rows of MRAM bitcells wherein each bitcell includes a ferromagnetic device having a polarization which in a first bit value storage state is one of parallel and anti-parallel polarization and in a second bit value storage state is the other of parallel and anti-parallel polarization; and control circuitry configured to access a bitcell of the first row wherein said access generates a first magnetic field and wherein said control circuitry is further configured to mitigate a first magnetic field of the first row to maintain a bit value storage state of a bitcell of the second row wherein said control circuitry configured to mitigate a first magnetic field includes a detector configured to detect repeated access to the first row and a driver configured to suspend access to the first row in response to said detection, wherein a first magnetic field of the first row is mitigated in response to said detection to maintain a bit value storage state of a bitcell of the second row.