Patent ID: 9553199
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate; a source/drain electrode stack over the substrate, wherein the source/drain electrode stack comprises a first source/drain electrode, a second source/drain electrode, and a dielectric layer interposed between the first source/drain electrode and the second source/drain electrode; a source/channel/drain layer disposed on a first sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material, wherein a top surface of the source/channel/drain layer faces away from the substrate, wherein a portion of the top surface of the source/channel/drain layer extends below a top surface of the first source/drain electrode and away from the first sidewall of the source/drain electrode stack, and wherein the portion of the top surface of the source/channel/drain layer is parallel to a major surface of the substrate; and a gate stack over the source/channel/drain layer.