Patent ID: 9575112
Date: 2017-02-21
CPC Classifications: G01R

Claim:
1. A test system comprising: a row decoder configured to activate one of first through M-th row signals, where M is a positive integer, based on a plurality of row input signals; a column decoder configured to activate one of first through N-th column signals, where N is a positive integer, based on a plurality of column input signals; a row test controller configured to output first through N-th column output signals, which are activated, when a row test enable signal is activated and output the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated; and a test circuit including first through M-th row test blocks, each of which includes first through N-th test units, wherein the first through M-th row test blocks correspond to the first through M-th row signals, respectively, and wherein the test circuit simultaneously performs a short test of the first through N-th test units included in a row test block, which corresponds to activated row signal among the first through M-th row signals, based on first and second test signals and the first through N-th column output signals when the row test enable signal is activated.