Patent ID: 9696837
Date: 2017-07-04
CPC Classifications: G02F,G06F,H01L

Claim:
1. A display panel, comprising: a plurality of common signal lines on a substrate; a lower planarization layer on the plurality of common signal lines; a plurality of gate lines and a plurality of data lines on the lower planarization layer, the plurality of gate lines extended in a first direction and the plurality of data lines extended in a second direction to define a matrix of pixel regions; an array of thin-film transistors provided on the lower planarization layer electrically coupled with the plurality of gate lines and the plurality of data lines; a plurality of bypass lines on the lower planarization layer extended in the first direction, each of the bypass lines having one or more first arched portions and one or more second arched portions of which the first arched portion and the second arched portion are curved in opposite directions from each other; an upper planarization layer on the array of thin-film transistors and the plurality of bypass lines; and a plurality of transparent electrode blocks on the upper planarization layer, each transparent electrode block connected to at least one of the common signal lines via at least one of the plurality of bypass lines.