Patent ID: 9641269
Date: 2017-05-02
CPC Classifications: H04J

Claim:
1. A packet transmission device, comprising: a first monitoring control board including a first clock, a first processor, and first circuits, the first circuits being configured to detect a first pulse per second (PPS) signal of the first clock; a second monitoring control board including a second clock, a second processor, and second circuits, the second circuits being configured to detect a second PPS signal of the second clock; and an interface (IF) board including a third processor configured to transmit and receive a synchronization packet to and from an external time source device; wherein the first processor is configured to synchronize the first clock with the external time source device in accordance with time information of the synchronization packet; the second processor is configured to synchronize the second clock with the first clock, the first and second monitoring control boards are configured as a redundant configuration in which one of the first and second monitoring control boards is operated in an active mode and the other one of the first and second monitoring control boards is operated in a standby mode; when the second monitoring control board is operated in the standby mode, the second circuits obtain a phase difference between the first PPS signal and the second PPS signal, the phase difference indicating a pulse number of a clock signal of a period from a rising edge of the first PPS signal to a rising edge of the second PPS signal, and the second processor synchronizes the second clock with the first clock of the first monitoring control board in the active mode by adjusting the second clock in accordance with the phase difference between the first clock and the second clock obtained by the second circuits; and when a failure occurs in the first monitoring control board that is operating in the active mode, the second processor of the second monitoring control board which has been operating in the standby mode, causes the second monitoring control board to operate in the active mode by using the second clock that has been adjusted in accordance with the phase difference obtained by the second circuits.