Patent ID: 9559204
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor body formed from a first semiconductor material; a first gate electrode disposed over an upper surface of the semiconductor body; a first sidewall spacer disposed along a first sidewall of the first gate electrode; a first region of a second semiconductor material embedded within the semiconductor body, the first region of the second semiconductor material adjacent the first sidewall spacer and laterally spaced from an isolation region by a first distance, wherein the first region is aligned with the first sidewall spacer, and wherein the first region comprises a sidewall contacting a portion of a sidewall of the first sidewall spacer; a second gate electrode disposed over the upper surface of the semiconductor body; a second sidewall spacer disposed along a second sidewall of the second gate electrode, wherein the second sidewall spacer is the nearest sidewall spacer to the first sidewall spacer along a direction from the first gate electrode to the second gate electrode; a second region of a third semiconductor material embedded within the semiconductor body, the second region of the third semiconductor material adjacent the second sidewall spacer and laterally spaced from the isolation region by a second distance, wherein the isolation region is the only isolation region disposed between the first region and the second region, wherein the first distance and the second distance are different, wherein the second region is aligned with the second sidewall spacer, and wherein the second region comprises a sidewall contacting a portion of a sidewall of the second sidewall spacer; a third sidewall spacer disposed along a third sidewall of the first gate electrode, the third sidewall spacer separated from the first sidewall spacer by the first gate electrode; a fourth sidewall spacer disposed along a fourth sidewall of the second gate electrode, the fourth sidewall spacer separated from the second sidewall spacer by the second gate electrode; a third region of the second semiconductor material embedded within the semiconductor body, the third region of the second semiconductor material adjacent the third sidewall spacer and laterally spaced from a second isolation region by the first distance, wherein the third region is aligned with the third sidewall spacer, and wherein the third region comprises a sidewall contacting a portion of a sidewall of the third sidewall spacer; and a fourth region of the third semiconductor material embedded within the semiconductor body, the fourth region of the third semiconductor material adjacent the fourth sidewall spacer and laterally spaced from a third isolation region by the second distance, wherein the fourth region is aligned with the fourth sidewall spacer, and wherein the fourth region comprises a sidewall contacting a portion of a sidewall of the fourth sidewall spacer.