Patent ID: 9570115
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A memory device comprising: a first plurality of memory cells, which includes a first memory cell; a first word line, which is electrically connected to each memory cell of the first plurality of memory cells and is configured to transmit a first control signal for controlling electrical connections in the first plurality of memory cells; a first bit line, which is electrically connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is electrically connected to the first bit line; a first source line, which is electrically connected to the first memory cell, wherein the first control signal is configured to control whether the first bit line is electrically connected to the first source line; a second plurality of memory cells, which includes a second memory cell; a second word line, which is electrically connected to each memory cell of the second plurality of memory cells and is configured to transmit a second control signal for controlling electrical connections in the second plurality of memory cells; a second bit line, which is electrically connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is electrically connected to the second bit line; a second source line, which is electrically connected to the second memory cell, wherein the second control signal is configured to control whether the second bit line is electrically connected to the second source line; and a sense amplifier, wherein a first input terminal of the sense amplifier is electrically connected to a second terminal of the first transistor, and wherein a second input terminal of the sense amplifier is electrically connected to a second terminal of the second transistor.