Patent ID: 9710588
Date: 2017-07-18
CPC Classifications: G03F,G06F,G21K

Claim:
1. A method of generating a modified layout based on an original layout, the method comprising: determining a first set of width bias values of an i-th set of layout patterns according to a first type width variation, the original layout having N sets of layout patterns corresponding to N masks, the i-th set of layout patterns having an i-th mask assignment corresponding to an i-th mask of the N masks, an order index i being an integer from 1 to N, and N being an integer greater than 1; determining a second set of width bias values of the i-th set of layout patterns of the original layout according to a second type width variation; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.