Patent ID: 9742679
Date: 2017-08-22
CPC Classifications: H04L

Claim:
1. A rate limiter, comprising: an input node configured to receive input values; a history memory, coupled to the input node, configured to store the input values during a time window defined by a current time and a predefined time interval; a counter memory, coupled to the input node and the history memory, configured to aggregate counter values for different values of the input values during the time window; and control logic, coupled to the counter memory, configured to: compare a counter value to predefined threshold value; and selectively set an error value based on the comparison; wherein the history memory includes a ring buffer; wherein an in-pointer point to a storage element at a head of the ring buffer where a next-received input value is stored with an associated timestamp; and wherein an out-pointer point to another storage element at a tail of the ring buffer where another input value and another associated timestamp are stored and are removed when the other timestamp moves out of the time window.