Patent ID: 9639473
Date: 2017-05-02
CPC Classifications: G06F

Claim:
1. A system operative to prevent a controller from automatically writing to a cache memory, comprising: a compute element; a memory operative to store data sets; a cache memory associated with the compute element and operative to cache the data sets in conjunction with the memory; and a controller operative to transfer data sets automatically from a data source to the cache memory, in which the data sets transferred are associated with specific addresses in the memory, thereby facilitating later updating of the data sets from the cache memory to the specific addresses in the memory, wherein: the system is configured to disable caching by the cache memory of at least the specific addresses in the memory, while still enabling caching by the cache memory of other addresses in the memory; the controller is configured, as a result of said disablement, to refrain from said transferring of data sets automatically from the data source to the cache memory, and instead, transfer the data sets from the data source to the specific addresses in the memory; and the compute element is configured to: (i) determine that the data sets are now needed for processing, and should therefore be cached in the cache memory, and (ii) cause the system, as a result of said determination, to copy the data sets from the specific addresses in the memory to the other addresses in the memory, thereby now allowing the caching and processing of the data sets.