Patent ID: 9741918
Date: 2017-08-22
CPC Classifications: G11C,H01L

Claim:
1. A planarized integrated circuit on a substrate, comprising: a series of planarized layers comprising at least two layers, formed successively on the substrate, each respective layer comprising: an electrically conductive via layer, patterned into a set of vias which define a set of vertically extending structures which electrically interconnect with conductive structures of an adjacent layer; an electrically conductive layer, formed by deposition over, and adjacent to, the electrically conductive via layer patterned into the set of vias, the electrically conductive layer-being patterned into a set of wires by removal of portions of the electrically conductive layer surrounding the set of wires, with the set of vertically extending structures extending above the set of wires which do not overly the set of vias; a first insulating layer formed over the electrically conductive via layer and the electrically conductive layer which is etched using an anisotropic etch process, to maintain a nonplanar raised Caldera pattern surrounding edges of the set of wires; and a second insulating layer formed over the set of wires and the set of vias, formed over the first insulating layer having the maintained raised Caldera pattern surrounding edges of the set of wires, to produce a conformal coating, which is etched using an anisotropic etch process, to maintain conformally coated raised Caldera pattern surrounding edges of the set of wires, and raised Caldera pattern surrounding edges of the set of vias, the second insulating layer being planarized to expose upper portions of the set of vertically extending structures, and remove the conformally coated raised Caldera pattern surrounding edges of the set of wires and the raised Caldera pattern surrounding edges of the set of vias, wherein the conformally coated raised Caldera pattern is independent of the set of vertically extending structures, wherein the electrically conductive layer, electrically conductive via layer, first insulating layer and second planarized insulating layer being formed as a four layer stack which is planarized once, such that upper portions of the set of vertically extending structures are exposed through the planarized second insulating layer, and wherein the electrically conductive via layer of a respective planarized layer is formed over exposed upper portions of the set of vertically extending structures of a respectively lower planarized layer.