Patent ID: 9678899
Date: 2017-06-13
CPC Classifications: G06F

Claim:
1. A memory protection unit, arranged to: receive a memory access signal comprising at least one instruction memory region, IMR, indication, the at least one IMR indication comprising an indication of a region of memory from which the memory access instruction was fetched, execution of said memory access instruction having resulted in the generation of the received memory access signal; compare the at least one IMR indication for the received memory access signal to at least one permitted memory region, PMR, indication for a target address of the received memory access signal and output a hit signal when the target address corresponds to a PMR; determine whether a memory access being attempted by the memory access signal is permitted based at least partly on the comparison of the at least one IMR indication for the received memory access signal to the at least one PMR indication for the target address of the received memory access signal and output an access violation signal when the attempted memory access of the memory access signal is not permitted; and determine whether the memory access signal, for a permitted memory access, is further permitted based at least partly on a comparison of a process ID for the memory access to permitted process ID(s) for an access type and bus master privilege level.