Patent ID: 9706642
Date: 2017-07-11
CPC Classifications: H01P,H05K,Y02P

Claim:
1. A substrate, comprising: a first metal layer including a first trace and a second trace; a second metal layer including a ground plane; a dielectric layer arranged between the first and second metal layers; a first solder pad and a second solder pad connected to the first trace and the second trace respectively; and a first cutout and a second cutout in the ground plane corresponding with the first solder pad and the second solder pad respectively, wherein a length of the second trace is shorter than a length of the first trace, wherein an open area of the second cutout is less than an open area of the first cutout, wherein the ground plane is a single-layer ground plane, and wherein the second cutout includes a second perimeter that is substantially the same as a first perimeter of the first cutout, and the second cutout includes patterned metal interior to the second cutout.