Patent ID: 9576102
Date: 2017-02-21
CPC Classifications: G06F

Claim:
1. A method for managing time constraints in a circuit, the method comprising: creating an initial placement design in a circuit; determining, by one or more processors, based on the created initial placement design whether a first criteria is met, wherein the first criteria comprises a design parameter at a first predefined threshold; in response to determining that the first criteria is met, initiating, by one or more processors, a first checkpoint procedure, wherein the first checkpoint procedure comprises a two-pass flow, in which: in response to determining that a first criteria is not met, performing, by one or more processors, an intermediate placement design; determining, by one or more processors, whether a second criteria is met based on the intermediate placement design, wherein the second criteria comprises a second predefined threshold; in response to determining that the second criteria is met, initiating, by one or more processors, a second checkpoint procedure, wherein the second checkpoint procedure comprises: