Patent ID: 9666511
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: a lead frame with a die pad; a first chip arranged over and bonded to the die pad, wherein the first chip comprises a first device with a first operating voltage, and wherein the first chip further comprises a bulk semiconductor substrate within which the first device is arranged; a bonding layer arranged between the die pad and the first chip, wherein the bonding layer directly bonds the first chip to the die pad; a second chip arranged over and bonded to the die pad spaced from the first chip, wherein the second chip comprises a second device with a second operating voltage greater than the first operating voltage; a dielectric layer arranged between the die pad and the second device, wherein a bottom surface of the dielectric layer is spaced over the die pad by a semiconductor layer, wherein the second chip further comprises a semiconductor-on-insulator (SOI) substrate, wherein the SOI substrate comprises the semiconductor layer and an additional semiconductor layer respectively under and over the dielectric layer, and wherein the second device is arranged in the additional semiconductor layer; and an additional bonding layer arranged between the die pad and the second chip, wherein the additional bonding layer directly bonds the second chip to the die pad.