Patent ID: 9646667
Date: 2017-05-09
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a first active area provided in a semiconductor substrate and extending in a first direction; a second active area provided in the semiconductor substrate and extending from an end of the first active area in a second direction intersecting the first direction; a first select transistor comprising a first drain region provided in the first active area and a first source region provided in an intersection region of the first and second active areas; a second select transistor comprising a second drain region provided in the second active area and sharing the first source region; a first word line coupled to gates of the first and second select transistors; first and second variable resistance elements coupled to the first and second drain regions, respectively; a first bit line coupled to the first variable resistance element; a second bit line coupled to the second variable resistance element; and a first source line coupled to the first source region.