Patent ID: 9588172
Date: 2017-03-07
CPC Classifications: G01R

Claim:
1. A device comprising: a first circuit; and a second circuit comprising: wherein the second circuit is configured to generate a signal for testing operation of the first circuit and configured to operate as a memory of the first circuit, wherein each of the plurality of fourth circuits comprises a first inverter and a second inverter, the second inverter comprising an input terminal electrically connected to an output terminal of the first inverter and an output terminal electrically connected to an input terminal of the first inverter, wherein each of the plurality of fourth circuit is configured to store a first data and configured to store a second data, wherein the fifth circuit is configured to write the first data to the plurality of fourth circuits, wherein the fifth circuit is configured to write the second data to the plurality of fourth circuits and read the second data from the plurality of fourth circuits, wherein the first data is to control conduction between the plurality of third circuits, wherein each of the plurality of fourth circuits comprises a first transistor and a second transistor, wherein one of a source and a drain of the first transistor and a gate of the second transistor are electrically connected to the input terminal of the first inverter, and wherein the first transistor includes a first channel formation region in an oxide semiconductor layer.