Patent ID: 9704922
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor memory device, comprising: forming a laminated body where interlayer insulating films and conducting layers are laminated in alternation above a semiconductor substrate; dividing the laminated body by a plurality of first trenches whose longitudinal direction is a first direction, the first trenches being arranged in a second direction intersecting with the first direction; forming sacrificial films in the first trenches, the sacrificial films being formed at predetermined intervals in the first direction; forming insulating layers in the first trenches at predetermined intervals in the first direction so as to embed a void portion between the sacrificial films; removing the sacrificial films; forming a variable resistance layer along a lateral face of the laminated body and lateral faces of the insulating layers, the lateral face of the laminated body and the lateral faces of the insulating layers being at a position where the sacrificial films had been removed; and forming conducting layers along lateral faces of the variable resistance layer.