Patent ID: 9679650
Date: 2017-06-13
CPC Classifications: G11C,H01L

Claim:
1. An apparatus comprising: first and second units of vertically arranged strings of memory cells, each unit including multiple tiers of semiconductor material, each tier including an access line of at least one memory cell; and a first drive transistor selectively coupled to the access line of a first tier of the first unit through a first decoder transistor, and selectively coupled to the access line of a first tier of the second unit through a second decoder transistor, wherein each tier of the multiple tiers of the first and second units includes the access line of at least one memory cell and a channel of a decoder transistor, and wherein the channel of the decoder transistor of each of the multiple tiers of the first unit of memory cells is coupled to the channel of the decoder transistor of a corresponding tier of the second unit of memory cells.