Patent ID: 9702936
Date: 2017-07-11
CPC Classifications: G01R

Claim:
1. A system for concurrently testing a plurality of semiconductor components, the system comprising: a plurality of testers, each including a processor and a memory configured to store and execute control signals for completing testing of one of the plurality of semiconductor components, a tester side docking board, and a tester communication port; a handler having a plurality of test sites, each of which is configured to receive one of the plurality of semiconductor components, a handler side docking board, and a handler communication port; and a controller located externally from the plurality of testers and the handler and in communication with each of the plurality of testers and the handler through the tester and handler communication ports, wherein communication between each of the plurality of testers and the handler occurs through the controller, and each of the plurality of testers is connected, via the tester side docking board, to a corresponding one of the plurality of semiconductor components through the handler side docking board, wherein the controller is configured to format the control signals received from each of the plurality of testers for sending to the handler; and wherein the controller is configured to format feedback signals received from the handler for sending to one or more of the plurality of testers.