Patent ID: 9582634
Date: 2017-02-28
CPC Classifications: G06F

Claim:
1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of paths, each path comprising a plurality of nodes representing IC components comprising clocked elements and computational elements, the method comprising: optimizing the timing performance of the IC design by retiming a set of paths, the retiming comprising skewing clock signals to a set of clocked elements by more than a clock period without changing a position of any clocked element relative to a position of the computational elements in the set of paths; performing simulation on the optimized IC design; providing a result of the simulation as a clock skew scheduled design of the IC design; mapping the clock skew scheduled design into a retimed design by removing a first clocked element from the IC design and adding a second clocked element to the IC design; and implementing the IC design using the retimed IC design.