Patent ID: 9589928
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a die pad having an upper surface and a lower surface; an integrated circuit attached on the upper surface of the die pad; a plurality of first package type leads surrounding the die pad, wherein each of the plurality of first package type leads is electrically connected to the integrated circuit with first bond wires; a plurality of second package type leads that surround the first package type leads, wherein the second package type leads have proximal ends that are positioned above the plurality of first package type leads, wherein the proximal ends of the second package type leads are electrically connected to the integrated circuit with second bond wires, and wherein the second package type leads are of a different lead type than the first package type leads; and a mold cap that at least partially covers the die pad, the integrated circuit, the plurality of first and second package type leads, and the first and second bond wires; a pre-molded portion for positioning the first package type leads and supporting the second package type leads over the first package type leads, wherein the pre-molded portion includes a structure located between leads of the plurality of first package type leads and leads of the plurality of second package type leads in a direction orthogonal to the upper surface of the die pad, wherein the structure is formed separately from the mold cap.