Patent ID: 9627396
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate; a stack on the substrate, the stack including gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, the gate electrodes and the insulating layers extending in a first direction parallel to a top surface of the substrate; a first row of channel structures penetrating the stack, the channel structures in the first row being arranged spaced apart from each other in the first direction; and a second row of channel structures penetrating the stack, the channel structures in the second row being arranged spaced apart from each other in the first direction, the first sidewall including first recessed portions and first protruding portions, each of the first protruding portions being defined by an adjacent pair of the first recessed portions, each of the first recessed portions recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row, each of the first recessed portions recessed beyond a virtual line connecting outermost points of the channel structures of the first row, when viewed in a plan view, and each of the outermost points facing each of the first protruding portions, when viewed in a plan view.