Patent ID: 9535701
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. A method of controlling a pipelined processor having a plurality of serially connected processing stages including a first stage and a branch evaluation stage, wherein one of the processing stages other than the branch evaluation stage is a prediction stage that supplies branch source information for making branch predictions, wherein the pipelined processor is operatively coupled to a memory that comprises a plurality of addressable storage locations, each storage location being for storing one unit of data, the method comprising: for each one of a plurality of sequentially occurring cycles: wherein: the pipelined processor executes instructions from an instruction set that includes a branch instruction; each branch instruction is associated with a set of branch delay slots whose size can be greater than or equal to zero and whose size can be different from one instance of a branch instruction to another; the executed branch fetch mode comprises producing the memory address by evaluating a branch instruction loaded in the branch evaluation stage of the pipelined processor; the predicted fetch mode comprises: the sequential fetch mode comprises producing the memory address as a memory address that is a sequentially next occurring address after a present address.