Patent ID: 9559043
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A leadframe for stacking a plurality of levels of electronic devices, comprising a plurality of leads each having an interconnect area, wherein said plurality of leads are grouped so that interconnect areas of each group of said leads have a height corresponding to one level of electronic devices and are soldered to conductive bumps of said one level of electronic devices, leads of different groups are coplanar at bottoms in a plane perpendicular to a first direction along which said electronic devices are stacked said leads comprise a first group of leads for a lowermost level of electronic devices, to an m-th group of leads for a topmost level of electronic devices, where m is a natural number larger than 2, and interconnect areas of an n-th group of leads surround interconnect areas of said first to an (n−1)-th groups of leads, where n is any natural number larger than 1 and smaller than m.