Patent ID: 9570456
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor integrated device, comprising: a substrate, having a capacitor region and a memory cell region; at least one shallow trench isolation disposed in the substrate; a memory cell device disposed on the at least one shallow trench isolation in the memory cell region, wherein the memory cell device comprises a tunneling oxide layer, a floating gate, an oxide-nitride-oxide layer, and a control gate sequentially stacked on the at least one shallow trench isolation, and the tunneling oxide layer is disposed between the floating gate and the at least one shallow trench isolation in a projection direction perpendicular to the substrate; and a poly-insulator-poly capacitor disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts a pad oxide layer disposed on the at least one shallow trench isolation, and the poly-insulator-poly capacitor comprises a bottom electrode, another oxide-nitride-oxide layer and a top electrode, wherein the bottom electrode comprises a plurality of holes and a portion of the oxide-nitride-oxide layer of the poly-insulator-poly capacitor is filled in the holes and does not directly contact the at least one shallow trench isolation in the capacitor region.