Patent ID: 9536784
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of forming through silicon vias (TSVs) on an integrated circuit (IC) chip wafer, said method comprising: forming a through silicon via (TSV) pattern identifying a plurality of TSV locations on the surface of an IC chip wafer, said IC chip wafer including one or more IC chip die, each IC die including a plurality of circuits on a silicon substrate and a stack of wiring layers on said silicon substrate above said plurality of circuits, said surface being the surface of the top wiring layer of said stack; etching said TSV pattern through said stack, a cup shaped through hole being opened through said stack to said silicon substrate at each TSV pattern location, the etched said stack forming a TSV hard mask open (HMO) for said silicon substrate; and etching via through holes through said silicon substrate masked by said HMO.