Patent ID: 9535101
Date: 2017-01-03
CPC Classifications: G01R,H02H,H02M

Claim:
1. A reverse current detector circuit for a DCDC converter, the reverse current detector circuit comprising: a sensing input connected to a reverse-current sensing node of the DCDC converter; a timing control output of a timing control circuit arranged for controlling a current-flow sequence timing of the DCDC converter; a flip-flop circuit providing to the timing control circuit the direction of a residual current at said reverse-current sensing node; a logic gate having a gate output connected to a data input of the flip-flop circuit; a first gate input connected to the sensing input; a second gate input receiving an input gating signal; a first timing control input receiving a first timing control signal of the DCDC converter; a first delay means for providing a first delayed timing signal by delaying the first timing control signal by a first delay period; an up-down counter forming said timing control circuit, wherein the logic gate is configured and connected such that, while the input gating signal has a first logic value, the logic state of the gate output depends on the first gate input and, when the input gating signal has a second logic value, a logic gate circuit is in a powered-down state such that the logic state of the gate output is independent of the first gate input, and wherein the up-down counter is clocked by the first delayed timing signal to increment a count value if the gate output is in a first gate output logic state when the up-down counter is clocked by the first delayed timing signal changing to a first clocking logic state, and to decrement the count value if the gate output is in a second gate output logic state when the up-down counter is clocked by the first delayed timing signal changing to the first clocking logic state.