Patent ID: 9613855
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of forming an MIS contact structure on an integrated circuit product comprising first and second transistors of opposite types, comprising: forming first and second contact openings in at least one layer of insulating material, said first contact opening exposing a portion of a first source/drain (S/D) region of said first transistor, said second contact opening exposing a portion of a second S/D region of said second transistor; performing a plurality of conformal deposition processes to form first, second and third layers of material within each of said first and second contact openings wherein: forming an implant masking layer that masks said first contact opening while leaving said second contact opening exposed for further processing; performing a contact ion implantation process through said implant masking layer to form a contact ion implant region comprising a contact ion that is positioned at least partially in at least one of said first, second or third layers of material positioned within said second contact opening; removing said implant masking layer; forming a fourth layer of material comprising a conductive material above said third layer in both said first and second contact openings such that said fourth layer overfills said first and second contact openings; and performing at least one process operation to remove portions of said first, second, third and fourth layers of material positioned outside of said first and second contact openings to define a first MIS contact structure positioned in said first contact opening and a second MIS contact structure positioned in said second contact opening.