Patent ID: 9740404
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A control apparatus configured to control a plurality of processors, corresponding to a plurality of storage areas that are arranged at an interface, for accessing the storage areas, the apparatus comprising: a memory storing respective load information for each of the plurality of processors; an update unit configured to, upon receiving an input of a command sequence including two or more commands, wherein each of the two or more commands is to be output to a storage area, update the load information for each processor based on a load applied by a command currently being executed to the storage area corresponding to the processor; a determination unit configured to determine whether two consecutive commands of the command sequence are of a same type and whether respective addresses for accessing the storage areas of the consecutive commands have continuity, a selection unit configured to: if the determination unit determines that the two consecutive commands of the command sequence are of the same type and respective addresses for accessing the storage areas of the two consecutive commands have continuity, select a processor, of the plurality of processors, as an allocation destination of a second command, that is immediately after a first command of the two consecutive commands, that is a same processor as previously selected for the first command, and if the determination unit determines that the two consecutive commands of the command sequence are not of the same type or respective addresses for accessing the storage areas of the two consecutive commands do not have continuity, select a processor, of the plurality of processors, as an allocation destination of the second command based on the load information of the plurality of processors; and an output unit configured to output the second command to the processor selected by the selection unit.