Patent ID: 9613893
Date: 2017-04-04
CPC Classifications: C23C,C25D,H01L,H05K

Claim:
1. A wiring substrate, comprising: a first outermost conductor layer; a first outermost insulating layer formed on the first outermost conductor layer such that the first outermost insulating layer is covering the first outermost conductor layer; a second outermost conductor layer formed on an opposite side of the first outermost conductor layer; a second outermost insulating layer formed on the second outermost conductor layer such that the second outermost insulating layer is covering the second outermost conductor layer; and a built-in interposer device configured to connect a plurality of electronic components to be mounted in an electronic component mounting region of the second outermost insulating layer, wherein the first outermost insulating layer has a plurality of first openings such that the plurality of first openings is exposing a plurality of first conductor pads comprising a plurality of portions of the first outermost conductor layer, respectively, the second outermost insulating layer has a plurality of second openings such that the plurality of second openings is exposing a plurality of second conductor pads comprising a plurality of portions of the second outermost conductor layer, respectively, each of the first conductor pads has a first plating layer formed in a respective one of the first openings such that the first plating layer is recessed with respect to an outer surface of the first outermost insulating layer, each of the second conductor pads has a second plating layer formed in a respective one of the second openings such that the second plating layer is formed flush with an outer surface of the second outermost insulating layer or has a bump shape protruding from the outer surface of the second outermost insulating layer, and the plurality of second conductor pads includes a plurality of the second conductor pads positioned to connect the electronic components through the built-in interposer device and a plurality of the second conductor pads positioned to connect one of the electronic components.