Patent ID: 9564897
Date: 2017-02-07
CPC Classifications: G01S,G06F,H03K

Claim:
1. An integrated clock gating cell, comprising: a logic gate, including a first input to receive an unbuffered enable signal (E), a second input to receive a scan test enable signal (SE), and an output that generates an inverted enable signal (EN); a first transmission gate, including a first terminal for receiving E, a second terminal for receiving SE, a third terminal for receiving EN, a fourth terminal, and a fifth terminal; a second transmission gate, including a first terminal connected to the fourth terminal of the first transmission gate, a second terminal connected to the fifth terminal of the first transmission gate, a third terminal for receiving a clock signal (CK), a fourth terminal for receiving an enabled and inverted clock signal (ECKN), and a fifth terminal; and a first transistor, including a first terminal connected to a power supply voltage (VDD), a second terminal connected to the output of the logic gate, and a third terminal connected to the fourth terminal of the first transmission gate; a second transistor, including a first terminal connected to the fifth terminal of the first transmission gate, a second terminal connected to VDD, and a third terminal; and a latch, including a first terminal connected to the fifth terminal of the second transmission gate, a second terminal connected to the third terminal of the second transistor, and a third terminal.