Patent ID: 9607708
Date: 2017-03-28
CPC Classifications: G11C

Claim:
1. An electrically erasable flash memory, comprising: a plurality of data storage elements configured to store a plurality of data bits, each of said plurality of data bits having a data state; a reference storage element in addition to said plurality of storage elements configured to store a reference; and a voltage sensing circuit selectively coupled to individual ones of said plurality data storage elements and said reference storage element and said voltage sensing circuit being configured to bias said individual ones of said plurality of data storage elements and said reference storage element with a bias resistance and to read said data state of said individual ones of said plurality of data bits stored in said plurality of data storage elements; wherein an output of said reference from said reference storage element provides an indication that data read out from said plurality of storage elements is valid; wherein each of said plurality of data storage elements has a performance margin; wherein said voltage sensing circuit is configured to selectively bias said plurality of data storage elements with said bias being at least one of a read bias and a margin bias; and wherein, when said voltage sensing circuit biases said individual one of said plurality of data storage elements with said margin bias, said individual one of said plurality of data storage elements induces a response indicative of said performance margin of said individual one of said plurality of data storage elements.