Patent ID: 9741573
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method for fabricating a NAND flash memory, comprising: providing a semiconductor substrate having an isolation material layer formed on the semiconductor substrate, a selection gate material layer formed on the isolation material layer, and a plurality of alternately stacked gate dielectric material layers and control gate material layers formed on the selection gate material layer; forming a hard mask layer having a plurality of openings on a surface of the uppermost control gate material layer; forming a stacked gate structure on the semiconductor substrate, wherein the stacked gate structure includes a selection gate on the semiconductor substrate and control gates on the selection gate, and a width of the stacked gate structure is the same as a width of the hard mask layer on a top surface of the stacked gate structure; isolating the selection gate and the control gates by a gate dielectric layer; forming a notch between the adjacent stacked gate structures; removing a part of a width of the selection gate and a part of a width of the control gates by using the hard mask layer as a mask to perform a back-etching process onto the stacked gate structure, such that a spacing between the adjacent selection gates and a spacing between the adjacent control gates can be larger than a spacing between the adjacent hard mask layers and a spacing between the adjacent gate dielectric layers; and performing a deposition process to form a dielectric layer filling the notch, wherein air gaps are formed in the dielectric layer between the adjacent selection gates and between the adjacent control gates.