Patent ID: 9588178
Date: 2017-03-07
CPC Classifications: G01R,G06F,H03K

Claim:
1. An integrated circuit comprising: (a) a data input bus, a data output bus, a serial data input, and a serial data output; (b) a multiplexer having a first input connected to the data input bus, a second input connected to the serial data input, a third input, an output, a first control input, and a second control input; (c) a first flip-flop having an input connected to the output of the multiplexer, a clock input, and having an output connected to the data output bus and connected to the third input of the multiplexer; (d) controller circuitry having a first control output coupled to the first control input of the multiplexer, a second control output coupled to the second control input of the multiplexer, and a control clock output coupled to the clock input of the first flip-flop; (e) a delay circuit having an input coupled to the control clock output and having a delay clock output; and (f) a second flip-flop having an input coupled to the output of the first flip-flop, a clock input coupled to the delay clock output, and an output coupled to the serial data output.