Patent ID: 9584120
Date: 2017-02-28
CPC Classifications: G01R,G06F,H03K

Claim:
1. A circuit, comprising: a scan path comprising a chain of scan flip flops configured to shift a test vector to selected core circuitry under test from a plurality of core circuits, the test vector selected from a vector set, in which a summation of gains corresponding to faults detected by the vector is maximum; multiplexer circuitry of the selected core circuitry under test coupled to an input of the scan path, the multiplexer circuitry including an enable input and configured to output a logical ‘1’ to a scan path input to shift the test vector to the selected core circuitry under test upon assertion of the enable input; and control circuitry coupled to the plurality of core circuits and configured to deassert an enable input to non-selected core circuits when testing the selected core circuitry under test to cause multiplexer circuitry of the non-selected core circuits to input a logical ‘0’ to each of a chain of scan flip flops of the non-selected core circuits.