Patent ID: 9704873
Date: 2017-07-11
CPC Classifications: G06F,G11C,H01L

Claim:
1. A semiconductor device comprising: a memory cell, including: a first conductivity type first transistor coupled between a first voltage and a first node; a second conductivity type first transistor coupled between the first node and a second voltage; a second conductivity type second transistor coupled between the first node and the second voltage in parallel with the second conductivity type first transistor; a first conductivity type second transistor coupled between the first voltage and a second node; a second conductivity type third transistor coupled between the second node and the second voltage; a second conductivity type fourth transistor coupled between the second node and the second voltage in parallel with the second conductivity type third transistor; a second conductivity type fifth transistor coupled between the first node and a first bit line; and a second conductivity type sixth transistor coupled between the second node and a second bit line, wherein the second conductivity type first transistor, the second conductivity type fourth transistor and the second conductivity type fifth transistor are disposed in a first active region, wherein the first conductivity type first transistor and the first conductivity type second transistor are disposed in a second active region, wherein the second conductivity type second transistor, the second conductivity type third transistor, and the second conductivity type sixth transistor are disposed in a third active region, wherein the first active region is formed on a first P-well, wherein the third active region is formed on a second P-well, and wherein the second active region is formed on a first N-well which is disposed between the first P-well and the second P-well, wherein a first gate wiring extends in a first direction over the first, second, and third active regions, wherein a second gate wiring extends in the first direction over the first, second, and third active regions, wherein a third gate wiring extends in the first direction over both the first active region and the N-well, and wherein a fourth gate wiring extends in the first direction over both the third active region and the N-well.