Patent ID: 9588179
Date: 2017-03-07
CPC Classifications: G01R

Claim:
1. A computer implemented method for masking scan chains in a test circuit of an integrated circuit, the method comprising: generating, by a computer, a test pattern including a plurality of input values for detecting a primary fault representing a fault for which an initial subset of input values in the test pattern is generated, at least one secondary fault representing a fault detectable by specifying input values other than the initial subset of input values, and at least one tertiary fault representing a fault detectable by the test pattern specified with the input values for the primary and the at least one secondary fault; responsive to a condition not being met, generating first mask data configured to mask a first subset of scan chains to increase a total number of detectable primary, secondary, and tertiary faults associated with the test pattern; and responsive to the condition being met, generating second mask data configured to mask a second subset of scan chains to protect the primary fault associated with the test pattern.