Patent ID: 9705515
Date: 2017-07-11
CPC Classifications: H03L

Claim:
1. A digital phase locked loop (PLL), comprising: a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code; a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code from a phase control unit; a time to digital converter (TDC) configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal outputted from the phase modulation unit; an error detection unit configured to generate a delay code required to compensate for a phase shift error occurring in the phase interpolation in response to the phase control code and the error code; a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal to the TDC; and a first decoder configured to control the delay unit in response to the delay code.