Patent ID: 9570039
Date: 2017-02-14
CPC Classifications: G09G

Claim:
1. A display device, comprising: a timing control circuit comprising: a data driving circuit receiving the first clock embedded training data, performing a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of the first clock signal, and receiving the first clock embedded image data, and the data driving circuit receiving the second clock embedded training data, performing a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of the second clock signal, and receiving the second clock embedded image data; wherein the clock embedded control circuit also generates a first clock training control signal according to the reference clock signal and a second clock training control signal according to the reference clock signal, the encode circuit embeds the first clock signal into the first training data to obtain a first clock embedded training data under the controls of the first clock training control signal, the encode circuit also embeds the second clock signal into the second training data to obtain a second clock embedded training data under the controls of the second clock training control signal; the clock embedded control circuit outputs the first clock training control signal and the second clock training control signal alternately.