Patent ID: 9711616
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A method for making a dual-channel field effect transistor (FET) device having increased amplifier linearity comprising: providing a channel layer within a channel, wherein the channel layer has a top surface which is entirely planar; depositing a barrier layer on the top surface of the channel layer, wherein: depositing a gate electrode on the barrier layer along the channel; wherein the first regions have a first pinch-off voltage and the second regions have a second pinch-off voltage which is larger than the first pinch-off voltage, such that the first and second regions are configured to turn on at different points on a drain current—gate voltage transfer curve when a gate voltage applied to the gate electrode is swept from negative to positive, whereby linearity of the transfer curve is increased as a function of the gate voltage, wherein a periodicity of the alternating first and second regions is smaller than a length of the channel.