Patent ID: 9607984
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate having first and second opposing major surfaces; a plurality of first active regions in the substrate adjacent the first major surface, wherein the first active regions and the substrate form a first transistor; a plurality of second active regions in the substrate adjacent the first major surface, wherein the second active regions and the substrate form a second transistor, wherein the plurality of first active regions and the plurality of second active regions are interleaved and arranged in an alternating pattern; a plurality of gate trench structures within the plurality of first active regions and the plurality of second active regions; a plurality of first conductive layers coupled to the plurality of first active regions adjacent the first major surface; a plurality of second conductive layers coupled to the plurality of second active regions adjacent the first major surface; a first conductive electrode electrically coupling the plurality of first conductive layers together; wherein the first conductive electrode and the plurality of first conductive layers are configured in a comb-like pattern; a second conductive electrode electrically coupling the plurality of second conductive layers together; wherein the second conductive electrode and the plurality of second conductive layers are configured in a comb-like pattern; and wherein the plurality of first conductive layers and the plurality of second conductive layers are interleaved and arranged in the alternating pattern.