Patent ID: 9583938
Date: 2017-02-28
CPC Classifications: H01L,H02H

Claim:
1. An electrostatic discharge (ESD) protection device to manage leakage current, the ESD protection device comprising: a first N-channel field-effect transistor (NFET) configured to, in response to receiving a power good (PGOOD) signal at a gate terminal of the first NFET, draw a gate terminal of an ESD clamp device to a bias voltage less than ground, the ESD clamp device configured to, in response to the gate terminal of the ESD clamp device being drawn to the bias voltage less than ground, allow a first leakage current to flow through the ESD clamp device, the ESD clamp device further configured to, in response to the gate terminal of the ESD clamp device being drawn to ground, allow a second leakage current to flow through the ESD clamp device, the first leakage current being less than the second leakage current; an inverter configured to, in response to receiving the PGOOD signal at an input of the inverter, drive an inverted copy of the PGOOD signal (PGOOD_N) to an enable input of a gated inverter; and the gated inverter, the gated inverter including an output coupled to the gate terminal of the ESD clamp device, the gated inverter further including a second NFET, the second NFET having a source terminal connected to ground, the second NFET further having a drain terminal connected to a source terminal of a third NFET, and the second NFET further having a gate terminal connected to the enable input of the gated inverter, the second NFET configured to, in response to receiving the PGOOD_N signal, inhibit the output of the gated inverter from drawing the gate terminal of the ESD clamp device to ground.