Patent ID: 9741731
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A 3D stacked semiconductor structure, comprising: a plurality of stacks formed on an identical surface of a substrate and disposed parallel to each other, and one of the stacks at least comprising a plurality of multi-layered pillars and a gate covering sidewalls of the multi-layered pillars, and each of the multi-layered pillars comprising a plurality of insulating layers and a plurality of semiconductor layers arranged alternately, wherein the multi-layered pillars in each of the stacks arranged along a first direction; a plurality of semiconductor strips extending along a second direction, and the semiconductor strips at an identical level connecting one of the semiconductor layers of the multi-layered pillars of different stacks at the identical level, wherein the second direction is perpendicular to the first direction, and the first direction and the second direction are parallel to the identical surface of the substrate; a plurality of pad structures electrically connected to the semiconductor strips, wherein the semiconductor strips at the identical level are electrically coupled together by one of the pad structures; a dielectric layer formed on the stacks; a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer and over the stacks, and the MOS layer comprising a plurality of MOS structures electrically connected to the conductive plugs respectively, each of the MOS structures comprising: a patterned polysilicon layer formed on the dielectric layer; a patterned oxide layer formed on the patterned polysilicon layer; a gate oxide (GOX) covering sidewalls of the patterned polysilicon layer; and an island gate formed on the patterned oxide layer to cover the patterned oxide layer and the gate oxide, wherein the patterned polysilicon layer shielded by the island gate is undoped polysilicon, and the MOS structures are electrically connected to the conductive plugs through heavily doped polysilicon portions of the patterned polysilicon layers; wherein the conductive plugs are respectively connected to the different pad structures, and the MOS structures respectively connected to the conductive plugs function as layer-selectors.