Patent ID: 9577789
Date: 2017-02-21
CPC Classifications: H04L,H04N

Claim:
1. A frequency deinterleaving and time deinterleaving circuit, configured to perform a frequency deinterleaving operation and a time deinterleaving operation on an interleaved signal by using a first memory and a second memory, the circuit adapted for multiple digital video standards, the circuit comprising: a frequency deinterleaving control module, configured to generate a first access index according to a setting value; a time deinterleaving control module, configured to generate a second access index according to the setting value; a first address generating unit, configured to generate a first access address according to the first access index; and a second address generating unit, configured to generate a second access address according to the second access index; wherein, the setting value corresponds to a digital video standard of the interleaved signal; the first memory is accessed for temporary data of the frequency deinterleaving operation according to the first access address, and the second memory is accessed for temporary data of the time deinterleaving operation according to the second access address, wherein the time deinterleaving control module further comprises a convolution operation unit and a row-column operation unit, and the time deinterleaving control module selects one of the convolution operation unit and the row-column operation unit according to the setting value.