Patent ID: 9691490
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of cell strings arranged in a row direction and a column direction, wherein the cell strings include a first plurality of normal memory cells, a second plurality of dummy memory cells, drain select transistors, and source select transistors in a stacked configuration over a substrate; a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells; and a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells, wherein the second plurality of dummy memory cells include a second plurality of drain dummy memory cells electrically coupled to bit lines through the drain select transistors, and a second plurality of source dummy memory cells electrically coupled to a common source line through the source select transistors, wherein the first plurality of normal memory cells are electrically coupled between the drain dummy memory cells and the source dummy memory cells, and wherein a first bad memory cell included in a first cell string among the cell strings and coupled to a first normal word line is replaced with a first dummy memory cell included in the first cell string and coupled to a first dummy word line, and a second bad memory cell included in the first cell string and coupled to a second normal word line is replaced with a second dummy memory cell included in second cell string and coupled to the first dummy word line.