Patent ID: 9634879
Date: 2017-04-25
CPC Classifications: H04L

Claim:
1. A demodulator apparatus comprising: a plurality of antennas; a memory; and a processor coupled to the plurality of antennas and the memory, wherein the processor executes a process comprising: receiving signal via each of the plurality of antennas; applying lattice reduction to a channel response matrix calculated by using the received signal; applying linear detection to the received signal in lattice-reduced basis using a lattice-reduced channel response matrix; first calculating an expectation of a symbol in the lattice-reduced basis; inversely transforming the expectation of the symbol from the lattice-reduced basis into an original basis; second calculating soft-decision data by performing interference cancellation method in inversely transformed expectation of the symbol in the original basis; and outputting bits obtained by performing an error correcting decoding process using the soft-decision data.