Patent ID: 9634674
Date: 2017-04-25
CPC Classifications: H03L,H04B,H04L

Claim:
1. A semiconductor device comprising: a phase locked loop (PLL) that receives a reference clock and derives candidate clocks from the reference clock, wherein each one of the candidate clocks has a different phase; a multiplexer that receives the candidate clocks and selects a first selected clock from among the candidate clocks in response to a first control value and selects a second selected clock from among the candidate clocks, different from the first selected clock, in response to a second control value; a phase difference detector that detects a phase difference between the reference clock and the first selected clock; a phase difference controller generates the second control value in response to the detected phase difference; a variable delay line that generates a transmission clock in response to the second selected clock; and a driver that provides transmission data synchronously with the transmission clock.