Patent ID: 9582287
Date: 2017-02-28
CPC Classifications: G06F

Claim:
1. An apparatus comprising: a plurality of cores; a shared core extension logic coupled with each of the plurality of cores, the shared core extension logic having shared data processing logic that is to be shared by each of the plurality of cores at a given time; and instruction execution logic, for each of the cores, that in response to a shared core extension call instruction, is to call the shared core extension logic to have data processing performed by the shared data processing logic, on behalf of a corresponding core, wherein an instruction execution logic, for a given core of the plurality of cores, in response to the shared core extension call instruction which is to be provided from a given thread that is to be running on the given core, is to call the shared core extension logic to have the data processing performed by the shared data processing logic, while the given thread is to continue to run on the given core.