Patent ID: 9685213
Date: 2017-06-20
CPC Classifications: G06F,G11C,H01L,H04L

Claim:
1. A method comprising: providing current to a memory cell of a plurality of memory cells of a non-volatile random access memory (NVRAM) device, wherein the plurality of memory cells is coupled to a plurality of bit lines forming a bit line node with parasitic capacitance, each memory cell comprising a switch device that requires a level of a holding current to maintain an on-state of the memory cell, wherein providing current includes providing a bit line voltage at a first level to the bit line node, to select the memory cell; and increasing the bit line voltage provided to the bit line node from the first level to a second level, to cause the current to pass through the memory cell, to achieve a set point of the memory cell; and providing a current pulse with a profile that changes over time from the set point to the holding current level, in response to a discharge of the bit line node parasitic capacitance through the memory cell after the current set point is achieved, including, subsequent to the increase of the bit line voltage from the first level to the second level, disconnecting voltage supply from the bit line node, to cause the bit line node parasitic capacitance to discharge through the memory cell, and to cause the current passing through the memory cell to decrease over time, to reach the holding current level that keeps the memory cell in the on-state.