Patent ID: 9666140
Date: 2017-05-30
CPC Classifications: G06K,G09G

Claim:
1. A display device performing pause drive which alternates between a drive period and a pause period in predetermined cycles, comprising: a plurality of scanning signal lines and a plurality of data signal lines crossing the scanning signal lines; a plurality of pixel forming portions arranged in a matrix corresponding to respective crossings of the scanning signal lines and the data signal lines; a scanning signal line driver circuit including a shift register to sequentially output active scanning signals to the scanning signal lines by sequentially setting a plurality of cascaded unit circuits having a first state and a second state to the first state; a data signal line driver circuit to apply image signals to the data signal lines and thereby writing the image signals to the pixel forming portions that are connected to scanning signal lines being selected; a power supply circuit including a first voltage generation portion to generate a high-level voltage and a second voltage generation portion to generate a low-level voltage; a display control circuit, in accordance with a first control signal and image data, to generate a second control signal and a third control signal, the first control signal and the image data being externally transmitted, the second control signal controlling the operation of the scanning signal line driver circuit, the third control signal controlling the operation of the data signal line driver circuit; and a level shifter to output the second control signal provided by the display control circuit to the scanning signal line driver circuit after adjusting the level of the second control signal in accordance with the high-level voltage provided by the first voltage generation portion and the low-level voltage provided by the second voltage generation portion, wherein, each of the unit circuits includes a plurality of nodes and a plurality of thin-film, transistors connected to the nodes at gate terminals, the nodes set in a floating state during the pause period, the level shifter outputs the active scanning signals, such that the scanning signal line driver circuit applies the active scanning signals sequentially to the scanning signal lines, during the drive period, and then provides an active clear signal generated on the basis of the high-level voltage and the low-level voltage, simultaneously to the unit circuits, thereby setting voltages of the nodes to a reference voltage before a transition to the pause period, the level shifter provides the second control signal to the scanning signal line driver circuit during the pause period, the second control signal being a low-level signal generated on the basis of the high-level and the low-level voltages respectively provided by the first and the second voltage generation portions, and the level shifter generates the active clear signal in predetermined cycles during the pause period, and provides the active clear signal simultaneously to the unit circuits, thereby setting the voltages of the nodes to the reference voltage.