Patent ID: 9704858
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. An integrated device comprising: a semiconductor well formed in an epitaxial layer, wherein said epitaxial layer comprises a first type of semiconductor, and said semiconductor well comprises a second type of semiconductor that is different from said first type of semiconductor; a first guard ring formed in said epitaxial layer and surrounding said semiconductor well, wherein said first guard ring comprises said second type of semiconductor; an insulating layer formed atop said first guard ring; and a plurality of gate electrodes formed on a top surface of said insulating layer, overlapping said first guard ring and surrounding said semiconductor well, wherein said gate electrodes comprise a first gate electrode and a second gate electrode separated by a gap, wherein said first gate electrode comprises a first side wall above said first guard ring and facing said gap, wherein said second gate electrode comprises a second side wall above said first guard ring and facing said gap, wherein said gap is formed between said first and second side walls above said first guard ring, wherein said gap is shaped so that a first intersecting line between said top surface and said first side wall partially overlaps a first area of said top surface above said first guard ring, and wherein said first area is defined by a second intersecting line between said top surface and said second side wall and by a straight line through said gap and between a first point of said second intersecting line and a second point of said second intersecting line.