Patent ID: 9595345
Date: 2017-03-14
CPC Classifications: G11C

Claim:
1. An apparatus, comprising: a memory cell; a sense circuit connected to the memory cell via a bit line; a control circuit, the control circuit configured to perform a program operation for the memory cell to program the memory cell to a target data state and selectively test the memory cell using the sense circuit during the program operation, the selective testing includes charging the bit line; and a processor connected to the sense circuit, the processor configured to make a determination that the target data state matches one data state of a set of predetermined data states and, in response to the determination, cause the sense circuit to perform the selective testing of the memory cell relative to each data state of the set of predetermined data states, and cause the sense circuit to not charge the bit line during selective testing of another memory cell relative to a data state which is not in the set of predetermined data states.