Patent ID: 9543303
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A dual-well complementary metal oxide semiconductor (CMOS) device, comprising: a substrate, including a top surface and a bottom surface opposite to the top surface in a vertical direction; an epitaxial layer, which is formed on and connects at least a portion of the top surface of the substrate, the epitaxial layer including an epitaxial top surface opposite to the top surface in the vertical direction; an isolation region, which is formed on the epitaxial layer, and configured to define an NMOS device region and a PMOS device region in the epitaxial layer; a first P-type well (P-well), which is formed in the NMOS device region of the epitaxial layer and located under the epitaxial top surface in the vertical direction; a P-type body region, which is formed on the first P-well in the epitaxial layer, and is located between the first P-well and the epitaxial top surface in the vertical direction; a first N-type well (N-well), which is formed in the NMOS device region of the epitaxial layer and located under the epitaxial top surface in the vertical direction, and connects the first P-well in a lateral direction, to form a first PN junction between the first N-well and the first P-well; a first gate, which is formed in the NMOS device region, and is stacked on and connects the epitaxial top surface in the vertical direction; a first P-type lightly doped diffusion (PLDD) region, which is formed on the first P-well in the epitaxial layer, and is located between the epitaxial top surface and the first P-well in the vertical direction; a first N-type lightly doped diffusion (NLDD) region, which is formed on the first N-well in the epitaxial layer, and is located between the epitaxial top surface and the first N-well in the vertical direction; an N-type source, which is formed on the first P-well in the epitaxial layer, and is located between the epitaxial top surface and the first P-well in the vertical direction, wherein the N-type source connects the P-type body region and the first PLDD region in the lateral direction; an N-type drain, which is formed on the first N-well in the epitaxial layer, and is located between the epitaxial top surface and the first N-well in the vertical direction, wherein the N-type drain connects the first NLDD region in the lateral direction; a second N-type well (N-well), which is formed in the PMOS device region of the epitaxial layer and located under the epitaxial top surface in the vertical direction; an N-type body region, which is formed on the second N-well in the epitaxial layer, and is located between the second N-well and the epitaxial top surface in the vertical direction; a second P-type well (P-well), which is formed in the PMOS device region of the epitaxial layer and located under the epitaxial top surface in the vertical direction, and connects the second N-well in the lateral direction, to form a second PN junction between the second N-well and the second P-well; a second gate, which is formed in the PMOS device region, and is stacked on and connects the epitaxial top surface in the vertical direction; a second N-type lightly doped diffusion (NLDD) region, which is formed on the second N-well in the epitaxial layer, and is located between the epitaxial top surface and the second N-well in the vertical direction; a second P-type lightly doped diffusion (PLDD) region, which is formed on the second P-well in the epitaxial layer, and is located between the epitaxial top surface and the second P-well in the vertical direction; a P-type source, which is formed on the second N-well in the epitaxial layer, and is located between the epitaxial top surface and the second N-well in the vertical direction, wherein the P-type source connects the N-type body region and the second NLDD region in the lateral direction; a P-type drain, which is formed on the second P-well in the epitaxial layer, and is located between the epitaxial top surface and the second P-well in the vertical direction, wherein the P-type drain connects the second PLDD region in the lateral direction; and a separation region, which is connected between the PMOS device region and the NMOS device region, for separating the PMOS device region and the NMOS device region, wherein a depth of the separation region, which is measured from the epitaxial top surface downward, is not smaller than a depth of any of the first P-well, the first N-well, the second N-type well, and the second P-well; wherein, the first PN junction is located between the first PLDD region and the first NLDD region; wherein, the second PN junction is located between the second PLDD region and the second NLDD region.