Patent ID: 9536484
Date: 2017-01-03
CPC Classifications: G02F,G09G

Claim:
1. A liquid crystal array substrate, comprising a plurality of pixels arranged in array mode, each pixel comprises a main region, a first sub-region, and a second sub-region; wherein, the main region comprises a first thin film transistor (TFT), the first sub-region comprises a second TFT, and the second sub-region comprises a third TFT; gates of the first TFT, the second TFT, and the third TFT of each pixel are connected to a first scan line, a source of the first TFT is connected to a first data line, a drain of the first TFT is connected to one corresponding pixel electrode; sources of the second TFT and the third TFT are connected to a second data line, drains of the second TFT and the third TFT are respectively connected to corresponding pixel electrodes; wherein, each pixel further comprises a fourth TFT, a gate of the fourth TFT is connected to a second scan line, a source of the fourth TFT is coupled to the drain of the second TFT, and a drain of the fourth TFT is electrically connected to the drain of the third TFT, wherein the main region, the first sub-region, and the third region of the pixel both comprises a liquid crystal capacitor and a storage capacitor, the liquid crystal capacitor is formed by one corresponding pixel electrode, a common electrode, and a liquid crystal layer located between the pixel electrode and the common electrode; the storage capacitor is formed by one corresponding pixel electrode, a storage electrode, and a dielectric layer located between the pixel electrode and the storage electrode; the common electrode is connected to a first common voltage terminal, the storage electrode is connected to a second common voltage terminal, wherein the first sub-region further comprises a first sharing capacitor and a second sharing capacitor; the first sharing capacitor and the second sharing capacitor are connected between the drain of the second TFT and ground in series; the source of the fourth TFT is connected to a connection node of the first sharing capacitor and the second sharing capacitor and then is coupled to the drain of the second TFT via the first sharing capacitor.