Patent ID: 9709630
Date: 2017-07-18
CPC Classifications: G01R,H01J

Claim:
1. An integrated circuit die comprising: A. a first surface having parallel test input contacts, a test data input contact, test control input contacts, a test data output contact, and parallel test input and output contacts; B. a second surface opposite the first surface, the second surface having parallel test output contacts, a test data output contact, test control output contacts, a test data input contact, and parallel test input and output contacts; C. a test control port having leads coupled to the first surface test data input, test control input, and test data output contacts, to the second surface test data output, test control output, and test data input contacts, and having control outputs; D. parallel scan circuitry having parallel test inputs coupled to the second surface parallel test input contacts, a control input coupled to a control output of the test control port and parallel test outputs; E. comparator circuitry having inputs coupled to the parallel test outputs of the parallel scan circuitry, input and output leads coupled to the parallel test input and output contact points of the first and second surfaces, a control input connected to a control output of the test control port, and a fail output; F. first coupling circuitry having inputs coupled to the parallel test outputs of the parallel scan circuitry, a control input coupled to a control output of the test control port, and outputs coupled to the parallel test output contacts of the second surface; and G. second coupling circuitry having inputs coupled to the parallel test input contacts of the first surface, a control input coupled to a control output of the test control port, and outputs coupled to the parallel test output contacts of the second surface.