Patent ID: 9617143
Date: 2017-04-11
CPC Classifications: B81B,B81C,H01L

Claim:
1. A method of forming a semiconductor device comprising: bonding a capping wafer and a base wafer to form a wafer package, the base wafer comprising a plurality of chip package portions, the capping wafer comprising a plurality of isolation trenches, and each isolation trench of the plurality of isolation trenches being configured to substantially align with a corresponding chip package portion of the plurality of chip package portions; separating the wafer package into a plurality of chip packages, each chip package of the plurality of chip packages comprising at least one chip package portion of the plurality of chip package portions; forming a plurality of communication openings in the capping wafer, the plurality of communication openings comprising a first pair of communication openings configured to substantially align a first chip package portion of the plurality of chip package portions, and a second pair of communication openings configured to substantially align with a second chip package portion of the plurality of chip package portions; depositing a dielectric material in the plurality of communication openings; and forming the plurality of isolation trenches between the pairs of communication openings.