Patent ID: 9569211
Date: 2017-02-14
CPC Classifications: G06F,G11C

Claim:
1. A method for vector processor predication in an active memory device that includes memory and a processing element, the method comprising: setting one or more mask bits in a vector mask register in the processing element; applying the one or more mask bits by the processing element to predicate operation of an arithmetic logic unit or a load-store unit in the processing element associated with at least one of a plurality of sub-instructions; performing a compare of operands in the processing element using predication of a compare instruction to perform less than a maximum supported number of comparisons in parallel based on the one or more mask bits; storing compare results of the compare instruction as mask bit values of the vector mask register; analyzing a compare instruction syntax bit of the compare instruction to select between performing an OR-reduction and an AND-reduction on the mask bit values stored in response to performing less than the maximum supported number of comparisons in parallel by the predication of the compare instruction; reducing the mask bit values to a summary condition by performing a logical OR combination of the compare results based on determining that the OR-reduction is selected by the compare instruction syntax bit; reducing the mask bit values to the summary condition by performing a logical AND combination of the compare results based on determining that the AND-reduction is selected by the compare instruction syntax bit; writing the summary condition to a condition register; and using the summary condition of the condition register to determine a branch direction of a conditional branch instruction in the processing element.