Patent ID: 9673142
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor chip including a first main surface, a plurality of electrodes arranged on the first main surface, a first circuit electrically connected with one or more of the electrodes, a power supply potential supply section for supplying a power supply potential to the first circuit, and a reference potential supply section for supplying a reference potential to the first circuit; a wiring substrate including a first surface over which the semiconductor chip is mounted, a plurality of first terminals arranged on the first surface, a second surface opposite to the first surface, a plurality of second terminals arranged on the second surface, a plurality of wirings electrically connecting the first terminals with the second terminals, a third terminal arranged on the first surface and electrically connected with the power supply potential supply section of the semiconductor chip, a fourth terminal electrically connected with the third terminal, a first wiring electrically connecting the third terminal with the fourth terminal, a fifth terminal arranged on the first surface and electrically connected with the reference potential supply section of the semiconductor chip, a sixth terminal electrically connected with the fifth terminal, and a second wiring electrically connecting the fifth terminal with the sixth terminal; and a plurality of conductive members connecting the plurality of first terminals, the third terminal and the fifth terminal with the plurality of electrodes, respectively, wherein the fourth terminal is arranged closer to a periphery of the wiring substrate than the third terminal, wherein the sixth terminal is arranged closer to the periphery of the wiring substrate than the fifth terminal, and wherein the second wiring is extended along the first wiring.