Patent ID: 9640550
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming a stacked structure including a semiconductor pattern, and first material layers and second material layers stacked alternately to surround the semiconductor pattern; forming a slit passing through the stacked structure; forming first openings by removing the first material layers through the slit; forming a first barrier layer in the first openings and the slit; forming a third material layer in the first openings and the slit where the first barrier layer is formed, wherein the third material layer has an etch selectivity with respect to the first barrier layer and includes seams located in the first openings; forming sacrificial patterns filling the seams; forming second openings by partially etching the first barrier layer, the third material layer, and the sacrificial patterns formed in the first openings; and forming conductive patterns in the second openings.