Patent ID: 9614046
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate that includes a host substrate, a channel, an upper surface, and a lower surface; an active area proximate the upper surface of the semiconductor substrate; a substrate opening in the semiconductor substrate wherein a bottom of the substrate opening is defined by a recessed surface of the semiconductor substrate; a thermally conductive layer disposed over the semiconductor substrate and over the channel that contacts the recessed surface of the semiconductor substrate and extends between the recessed surface of the semiconductor substrate and a portion of the semiconductor substrate within the active area, the thermally conductive layer comprising a substantially electrically insulating layer within the active area; a through wafer via within the semiconductor substrate that includes a sidewall that extends from the lower surface of the semiconductor substrate to the recessed surface; and a high thermal conductivity backside layer in contact with the sidewall of the through wafer via.