Patent ID: 9601590
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method for fabricating a transistor, comprising: forming an isolation layer that defines an active region in a substrate; forming a trench extending across the active region and the isolation layer; forming a fin region by recessing the isolation layer, after the forming of the trench; forming a lower buried gate electrode that includes a high work-function barrier layer disposed on a bottom and sidewalls of the trench and fills a portion of the trench; forming an upper buried gate electrode over the lower buried gate electrode, wherein the upper buried gate electrode includes a low work-function barrier layer and fills a portion of the trench; forming a capping layer over the upper buried gate electrode; and forming a source region and a drain region that are spaced apart from each other by the trench in the substrate and each have a depth overlapping with the low work-function barrier layer.