Patent ID: 9672298
Date: 2017-06-06
CPC Classifications: G06F

Claim:
1. A processor configured to execute versioned store instructions of a first thread within a first mode of operation, wherein the first mode is a debugging mode in which retirement control circuitry included in the processor is configured to: retire, from an ordering unit, each versioned store instruction in the first thread only after a respective version comparison has been performed, wherein the comparison is between version information included in that versioned store instruction and version information stored at a target location of that versioned store instruction; and suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction of the first thread until the oldest versioned store instruction has retired; wherein the processor is further configured to execute versioned store instructions of a given thread within a second mode of operation, wherein the second mode is a disrupting mode in which: the retirement control circuitry is configured to retire at least one outstanding versioned store instruction before a version comparison has been performed for the at least one outstanding versioned store instruction; the processor is configured to perform the version comparison, between version information included in the at least one versioned store instruction and version information stored at a target location of the at least one versioned store instruction, subsequent to retirement of the at least one outstanding versioned store instruction; and instructions younger than the at least one versioned store instruction are allowed to commit results to the architectural state of the processor before the version comparison has been performed.