Patent ID: 9660692
Date: 2017-05-23
CPC Classifications: H04B,H04J

Claim:
1. An apparatus for performing a double correlation function on a received signal and a plurality of predetermined chip codes from a communication standard, the apparatus comprising: a first plurality of logic gates configured as a multiplier unit operable to receive a signal sampled at a predetermined sampling frequency, and to perform predetermined multiplication operations on the input signal in accordance with the correlation function; a first memory unit operable to receive and store multiplication values from the first plurality of logic gates; a second memory unit having stored therein values from predetermined multiplication operations performed on the plurality of chip codes in accordance with the correlation function; and a second plurality of logic gates configured as an adder unit to receive multiplication values outputted from the first memory unit and the second memory unit and to sum the multiplication values from the first memory unit taking into account the multiplication values from the second memory unit; and a sign selection unit configured to assign a positive or negative sign to each value from the first plurality of logic gates dependent on the sign of an associated value stored in the second memory unit.