Patent ID: 9734899
Date: 2017-08-15
CPC Classifications: G11C,H01L

Claim:
1. A non-volatile semiconductor memory device comprising: a memory cell capable of reading a status of multi-bit data to be written when a plurality of read voltages are applied to a control gate of the memory cell, among the plurality of read voltages include a first read voltage, a second read voltage, and a third read voltage increasing in this order; and a control circuit configured to control a voltage applied to the control gate of the memory cell, wherein the control circuit performs a first read operation and a second read operation between two program operations of applying a write voltage used to write multi-bit data to the memory cell to the control gate of the memory cell in continuous cycles, and wherein the control circuit performs the first read operation while a voltage between the first read voltage and the second read voltage is applied to the control gate of the memory cell and the second read operation while a voltage between the first read voltage and the second read voltage is applied to the control gate of the memory cell.