Patent ID: 9594647
Date: 2017-03-14
CPC Classifications: G06F,G11C

Claim:
1. A method for out-of-synchronization and out-of-order detection in a memory system, the method comprising: receiving a plurality of frames on two or more channels of the memory system at a memory control unit; identifying, by the memory control unit, an alignment logic input in each of the received frames, the alignment logic input comprising a multiple-input shift register value generated by one of a plurality of memory buffer chips and one or more of a data tag and a done tag, wherein the multiple-input shift register value is derived from periodic refresh timer events to determine that corresponding buffer refresh intervals are running synchronously with each other; generating, by the memory control unit, a summarized input to alignment logic for each of the two or more channels of the received frames based on the alignment logic input, wherein generating the summarized input comprises writing the alignment logic input to a multiple-input shift register and selecting a single bit output of the multiple-input shift register as the summarized input; adjusting, by the memory control unit, a timing alignment of the summarized input for each of the two or more channels of the received frames based on a skew value per channel; comparing each of the timing adjusted summarized inputs; and based on a mismatch between at least two of the timing adjusted summarized inputs, asserting a miscompare signal by the memory control unit, wherein the mismatch of the at least two of the timing adjusted summarized inputs is detected as out-of-order, and the mismatch of the at least two of the timing adjusted summarized inputs based on the multiple-input shift register value generated by one of the memory buffer chips is detected as out-of-synchronization.