Patent ID: 9576855
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device, the method comprising: providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor; forming an oxide layer directly on the IO regions of the substrate; forming an interfacial layer on the substrate in regions for the nFET core and pFET core and directly on the oxide layer in the regions for the nFET IO and pFET IO; depositing a high-k (HK) dielectric layer on the interfacial layer; depositing a first capping layer of a first material on the HK dielectric layer; depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer; depositing a work function (WF) metal layer on the second capping layer; depositing a polysilicon layer on the WF metal layer; and forming gate stacks on the regions of the substrate.