Patent ID: 9602142
Date: 2017-03-21
CPC Classifications: H03M,H04L

Claim:
1. A parity bits generation apparatus comprising: determination circuitry which, in operation, determines, based on a first sequence length of data bits and on a coding rate, a second sequence length of parity bits, and determines, based on the determined second sequence length of the parity bits, a third sequence length of predefined data bits from which a part of the parity bits are generated; encoder circuitry including one or more shift registers and control circuitry which, in operation, encodes a first combined sequence of the data bits and the predefined data bits to the parity bits, using a low density parity check convolutional code (LDPC-CC); addition circuitry which, in operation, adds information regarding the coding rate and information regarding the first sequence length of the data bits to a second combined sequence of the data bits and the parity bits; and modulation circuitry which, in operation, modulates the second combined sequence in which the information has been added, to transmit.