Patent ID: 9711567
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A process for fabricating an integrated circuit comprising a field-effect transistor and a memory cell of OxRam type, the process comprising: providing a substrate comprising a semiconductor layer, the substrate being equipped with first and second dummy gates and with an encapsulation layer in which said dummy gates are positioned, at least the first dummy gate being formed on the semiconductor layer of the substrate; removing the first and second dummy gates in order to make first and second grooves in said encapsulation layer; simultaneously depositing a gate insulating layer at least in the bottom of the first groove and on a side wall of the second groove; and forming a gate electrode of said field-effect transistor in the first groove on top of said gate insulating layer, forming source and drain electrodes of said transistor on either side of said gate electrode, and forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove.