Patent ID: 9685976
Date: 2017-06-20
CPC Classifications: H03M

Claim:
1. A K-Delta-1-Sigma (KD1S) Modulator Switched Capacitor Delta Sigma Modulator providing multiple feedback paths, comprising a KD1S modulator, one or more offset clocks, a clock generator, analog circuitry, a baseband filter, a main path switched capacitor filter, and one or more output latches for one or more analog paths, wherein each path samples the data with the one or more offset clocks such that the equivalent sampling rate of the Delta Sigma Modulator is the number of paths multiplied by the base sampling rate of each path, wherein the clock generator has an input word that specifies a number of paths (M) to be disabled, and wherein the analog paths are adjusted for the disabled paths and the summing circuit for all paths.