Patent ID: 9748261
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of fabricating a memory device, the method comprising: alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate, the sacrificial layers including first sacrificial layers and a second sacrificial layer, the second sacrificial layer being on an uppermost first sacrificial layer of the first sacrificial layers, a thickness of the second sacrificial layer in a first direction being greater than a thickness of each of the first sacrificial layers in the first direction; forming a channel hole by etching the insulating layers and the sacrificial layers, the channel hole exposing a partial region of the substrate; forming a channel structure in the channel hole; forming an opening by etching the insulating layers and the sacrificial layers, the opening exposing a portion of the substrate; forming a plurality of side openings by removing the sacrificial layers through the opening, the side openings including first side openings and a second side opening; forming gate electrodes that fill the first side openings; and forming a blocking layer that fills the second side opening, wherein at least one of the insulating layers is interposed between the blocking layer and the gate electrodes.