Patent ID: 9548743
Date: 2017-01-17
CPC Classifications: G06F,H03K,H03L

Claim:
1. An integrated circuit (IC), comprising: a plurality of shift registers, wherein each shift register of the plurality of shift registers comprises at least a first input terminal and a second input terminal; a multiplexer controller that activates a subset of the plurality of shift registers within the plurality of shift registers according to a fractional divisional factor; a pattern controller that generates a pattern control signal that is transmitted to the plurality of shift registers, wherein the pattern control signal causes the fractional divisional factor to be applied to a frequency of an input signal, the pattern control signal comprises a first array of bits and a second array of bits, the first input terminal of each shift register receives a corresponding bit from the first array of bits, and the second input terminal of each shift register receives a corresponding bit from the second array of bits; and a strobe generator that generates a trigger signal that triggers the pattern controller to transmit the pattern control signal to the plurality of shift registers, wherein the corresponding bit from the first array of bits acts to set the each shift register responsive to the trigger signal, and wherein the corresponding bit from the second array of bits acts to clear the each shift register responsive to the trigger signal.