Patent ID: 9645895
Date: 2017-05-09
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A data storage device, comprising: a flash memory including multi-level cells and single-level cells, wherein the flash memory is divided into a plurality of blocks with each block comprising a plurality of pages; and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory, wherein: the microcontroller is configured to establish a first physical-to-logical address mapping table in the random access memory for a first run-time write block between the blocks of the flash memory, and the first run-time write block contains multi-level cells; the microcontroller is further configured to establish a second physical-to-logical address mapping table in the random access memory for a second run-time write block between the blocks of the flash memory, and the second run-time write block contains single-level cells; in response to data that was previously stored in the first run-time write block with mapping information in the first physical-to-logical address mapping table, but not yet uploaded to the flash memory, being updated into the second run-time write block, the microcontroller is configured to update a logical-to-physical address mapping table located in the flash memory in accordance with the first physical-to-logical address mapping table.