Patent ID: 9740061
Date: 2017-08-22
CPC Classifications: G02F,H01L

Claim:
1. An array substrate comprising: a base substrate; gate lines and data lines disposed on the base substrate; a sub-pixel region on the base substrate in which a first electrode and a second electrode are provided, one of the first electrode and the second electrode being a common electrode, the other being a pixel electrode; an insulating layer between the first electrode and the second electrode; wherein the sub-pixel region comprises right opposite overlapping regions between the first electrode and the second electrode that are disposed in different layers and non-right opposite overlapping regions; and hollowed-out regions are provided at least in regions of the insulating layer that correspond to the non-right opposite overlapping regions; the insulating layer is further located between the gate lines and the data lines and in regions corresponding to regions where the gate lines and the data lines overlap right oppositely, and no insulating layer is provided in regions between the gate lines and the first electrode and the second electrode; and/or no insulating layer is provided in regions between the data lines and the first electrode and the second electrode.