Patent ID: 9703910
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. A computer program product for implementing power down processing including control path power adjustment, the computer program product comprising: a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising: receiving, by a power down engine, chip layout data corresponding to a chip design; determining a confluence point of a data path and a control path in the chip layout data, wherein the confluence point is where the data path and the control path logically intercept each other; determining the presence of a positive slack window in the control path of the confluence point; powering up the control path to reduce the positive slack window; performing power down processing on the output data path of the confluence point, wherein the power down processing is not performed on the control path; determining an amount of additional power savings achieved by the power down processing in the data path; and based on the determined amount of additional power savings being less than an amount of the power up in the control path, undoing the power up in the control path.