Patent ID: 9690158
Date: 2017-06-27
CPC Classifications: G02F

Claim:
1. An array substrate, comprising a plurality of data lines and a plurality of gate lines which are provided to intersect each other, wherein: the data lines are provided in parallel and the gate lines are provided in parallel, and the data lines and the gate lines vertically intersect to divide the array substrate into a plurality of pixel units each having a pixel electrode provided therein; the pixel electrode comprises a sub-pixel electrode comprising a root portion and a branch portion group connected to the root portion, the branch portion group consisting of a plurality of branch portions, adjacent ones of which are separated by slits; the branch portion group partially overlaps the data lines and/or the gate lines; each of the pixel electrodes comprises one or more sub-pixel electrodes, in the case where there are a plurality of sub-pixel electrodes in each of the electrodes, the plurality of sub-pixel electrodes are provided in a direction parallel to the data lines; and the slits in at least one of the sub-pixel electrodes in each of the pixel electrodes and the slits in sub-pixel electrodes adjacent to the sub-pixel electrodes are provided in a staggered manner, the sub-pixel electrodes and the adjacent sub-pixel electrodes being defined by the same gate lines and different data lines.