Patent ID: 9704832
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. An assembly comprising: a first power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface, wherein a peripheral edge separation diffusion region extends from the first substantially planar semiconductor surface to the second substantially planar semiconductor surface along a side edge of the first power semiconductor device die, wherein the peripheral edge separation diffusion region of the first power semiconductor device die is a P type semiconductor region that is doped at least in part with aluminum, and wherein a metal feature covers and makes electrical contact with the peripheral edge separation diffusion region at the first substantially planar semiconductor surface of the first power semiconductor device die; and a second power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface, wherein a peripheral edge separation diffusion region extends from the first substantially planar semiconductor surface to the second substantially planar semiconductor surface along a side edge of the second power semiconductor device die, wherein the peripheral edge separation diffusion region of the second power semiconductor device die is a P type semiconductor region that is doped at least in part with aluminum, wherein the second power semiconductor device die is bonded to the first power semiconductor device die such that the metal feature is electrically coupled within the assembly through the peripheral edge separation diffusion region of the first power semiconductor device die to the peripheral edge separation diffusion region of the second power semiconductor device die.