Patent ID: 9673300
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: forming an isolation region defining a fin active region on a substrate; forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region; forming a first interlayer insulating layer between the sacrificial field gate pattern and the sacrificial fin gate pattern; forming a field gate cut zone comprising a first recess exposing a surface of the isolation region by removing a first portion of the sacrificial field gate pattern and a fin active cut zone comprising a second recess exposing a surface of the fin active region by removing a first portion of the sacrificial fin gate pattern; forming a fin active recess by removing the fin active region exposed in the second recess of the fin active cut zone; forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively; forming a field gate electrode opening by removing a second portion of the sacrificial field gate pattern and forming a fin gate electrode opening by removing a second portion of the sacrificial fin gate pattern; and forming a field gate pattern in the field gate electrode opening and forming a fin gate pattern in the fin gate electrode opening.