Patent ID: 9569577
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A method for testing an integrated circuit (IC) design with an electronic design automation (EDA) tool, the EDA tool including a processor coupled to a memory in which the IC design is stored, wherein the IC design includes one or more IP blocks that include one or more mixed-signal modules, the method comprising: (a) the EDA tool selecting an IP block for testing; (b) the EDA tool selecting an analog output node of the IP block for the testing; (c) the EDA tool selecting a set of one or more input nodes for the testing; (d) for each input node of the set, the EDA tool providing a plurality of excitation signals, wherein at least two excitation signals of the plurality have different frequencies; and (e) for each provided excitation signal, the EDA tool determining the output node's noise sensitivity by relating the provided excitation signal to a corresponding output signal at the output node, wherein: