Patent ID: 9735032
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method of fabricating a BGA carrier, the method comprising: combining a conductive portion and a molded dielectric portion, the dielectric portion including a top surface, a bottom surface and an inner surface, the inner surface intersecting said top surface and said bottom surface, the inner surface forming a cavity for receiving a semiconductor die; selectively bonding the semiconductor die to a top surface of the conductive portion via a plurality of flip chip joints at locations on a bottom surface of the semiconductor die located within the cavity; selectively etching part of the conductive portion to form connection paths; and applying solder resist selectively to a bottom surface of the conductive portion in accordance with a predetermined shape to define areas of the conductive portion as BGA pads exposed at the bottom surface of the conductive portion; wherein the BGA pads include at least one first BGA pad exposed at the bottom surface of the conductive portion in a portion located within the cavity; the BGA pads include at least one second BGA pad exposed at the bottom surface of the conductive portion in a portion located outside of the cavity; and the connection paths join the flip chip joints to the at least one first BGA pad at the locations on the bottom surface of the semiconductor die located within the cavity.