Patent ID: 9716110
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A method for manufacturing an array substrate, the array substrate comprising a gate electrode, an active layer, a source electrode, a drain electrode and a pixel electrode, the method comprising: Step 1: depositing a gate metal film on a base substrate, and forming a first pattern including the gate electrode by a first patterning process; Step 2: depositing a gate insulating film, a first transparent conductive film, a source/drain metal film and a doped a-Si film sequentially on the base substrate with the first pattern, and forming a second pattern including the pixel electrode, the source electrode, the drain electrode and a doped semiconductor layer by a second patterning process; Step 3: depositing an a-Si film on the base substrate with the second pattern, and forming a third pattern including a TFT channel, the semiconductor layer and a gate insulating layer via-hole by a third patterning process, the gate insulating layer via-hole being arranged at a position corresponding to the gate electrode; Step 4: depositing a passivation layer film on the base substrate with the third pattern, and forming a fourth pattern including a passivation layer via-hole by a fourth patterning process, the passivation layer via-hole being arranged at a position corresponding to the gate insulating layer via-hole; and Step 5: depositing a second transparent conductive film on the base substrate with the fourth pattern, and forming a fifth pattern including an electrical connector by a fifth patterning process, at least a portion of the electrical connector being located within the passivation layer via-hole and the gate insulating layer via-hole and configured to electrically connect the gate electrode, the source electrode and the drain electrode which are arranged at the peripheral region, wherein the array substrate comprises a display region and a peripheral region around the display region, a portion of the gate electrode is located at the display region, the other portion of the gate electrode is located at the peripheral region, and the gate insulating layer via-hole is arranged above the gate electrode at the peripheral region.