Patent ID: 9640243
Date: 2017-05-02
CPC Classifications: G11C,H01L

Claim:
1. A method for selecting a semiconductor chip in a stack of semiconductor chips interconnected by through lines comprising: receiving a first plurality of selection signals at a first plurality of first terminals located on a first surface of the semiconductor chip; connecting each of the first terminals to a selected one of a first plurality of second terminals located on a second surface of the semiconductor chip and aligned with the first plurality of first terminals, wherein said second terminals are not aligned with the first terminals to which they are connected; generating an internal signal based on a selected one of the first plurality of selection signals received on a predetermined one of the first plurality of first terminals; receiving a second plurality of selection signals at a second plurality of third terminals located on the first surface of the semiconductor chip; connecting each of the third terminals to a selected one of a second plurality of fourth terminals located on a second surface of the semiconductor chip and aligned with the second plurality of third terminals, wherein said fourth terminals are not aligned with the third terminals to which they are connected; and generating an additional internal signal based on a selected one of the second plurality of selection signals received on a predetermined one of the second plurality of third terminals.