Patent ID: 9564527
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming, on one side of a semiconductor substrate having conductivity, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type; forming an opening part by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; forming a gate insulating film inside the opening part; forming a gate electrode inside the opening part via the gate insulating film; forming a source electrode on the third semiconductor layer; forming a drain electrode including an exposed surface and connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and forming a fourth electrode on the another side of the semiconductor substrate at a part corresponding to the source electrode; wherein the gate electrode extends in a direction that perpendicularly intersects the exposed surface of the drain electrode, wherein the source electrode is formed on both sides of the gate electrode in a horizontal direction, so that the gate electrode is interposed therebetween, wherein the drain electrode has a contact surface in electrical, physical contact with the semiconductor substrate, and wherein the contact surface of the drain electrode is nonexistent directly below the source electrode in a thickness direction of the semiconductor substrate.