Patent ID: 9633936
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a substrate; a first conductive trace disposed on the substrate; a second conductive trace disposed on the substrate a conductive pillar bump disposed on the first conductive trace; a first conductive structure disposed between the first conductive trace and the conductive pillar bump or between the first conductive trace and the substrate; a semiconductor die disposed over the first conductive trace, wherein the conductive pillar bump connects to the semiconductor die; a second conductive structure disposed overlapping a portion of the first conductive trace, wherein the portion of the first conductive trace is away from the conductive pillar bump; and a solder resistance layer disposed on the substrate, the solder resistance layer having an extending portion covering a portion of the second conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the second conductive trace.