Patent ID: 9600024
Date: 2017-03-21
CPC Classifications: G06F

Claim:
1. A control method for a clock signal for a CPU contained in a CMOS circuit, the method comprising: when a load current for operating the CMOS circuit is enabled, generating a first clock signal correspondingly; in a first time period beginning from when the load current for the CMOS circuit is enabled, selectively gating cycles of the first clock signal to generate a second clock signal at a steady frequency until transients in the second clock signal have settled, wherein the second clock signal has a clock rate less than a clock rate of the first clock signal; and in a second time period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal; wherein the second clock signal is continuously input to the CMOS circuit during the first time period and the second time period.