Patent ID: 9627253
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method of fabricating semiconductor device, comprising: forming a first interlayer dielectric layer comprising a first open part over a substrate; forming a first contact plug to fill the first open part and forming a bit line structure comprising a bit line over the first contact plug; forming a second interlayer dielectric layer over a resultant structure including the bit line structure; forming a second open part of a hole-shaped structure which has sidewalls provided by the second interlayer dielectric layer and the bit line structure, by etching the second interlayer dielectric layer; sequentially forming a first sacrificial spacer, a capping support layer, and a second sacrificial spacer over the sidewalls of the second open part; forming a second contact plug to partially fill the second open part; forming a first air gap surrounding the second contact plug by removing the second sacrificial spacer; forming a third interlayer dielectric layer over a resultant structure including the second contact plug; forming a third open part to partially expose the second contact plug and the first sacrificial spacer by etching the third interlayer dielectric layer; forming a second air gap surrounding the second contact plug by removing the first sacrificial spacer; and forming a third contact plug to fill the third open part.