Patent ID: 9559110
Date: 2017-01-31
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising at least one memory cell, wherein each memory cell of the memory device comprises: a stack including a first dielectric region, a second dielectric region that is spaced from the first dielectric region, and a charge storage region configured to trap electrical charges and contacting the first dielectric region and the second dielectric region; a p-doped region comprising a p-doped semiconductor material and contacting a first horizontal surface of the stack; and an n-doped region comprising an n-doped semiconductor material, wherein: at least one of the p-doped region and the n-doped region is in physical contact with the first dielectric region; each memory cell of the memory device comprises a semiconductor device including a p-n junction between the p-doped region and the n-doped region; each semiconductor device comprises a diode; and each memory device further comprises: an anode contact in physical contact with one of the second dielectric region of the memory device and a node of the diode of the memory device that does not contact the stack; and a cathode contact in physical contact with another of the second dielectric region of the memory device and the node of the diode of the memory device that does not contact the stack, wherein at least one of the p-doped region and the n-doped region is in physical contact with the first dielectric region.