Patent ID: 9589005
Date: 2017-03-07
CPC Classifications: G06F

Claim:
1. A method performed by a combination of electronic circuitry components for storing a decision tree, the method comprising: storing at least first nodes and second nodes of the decision tree within a memory, wherein the first nodes include a first parent node and first remaining nodes that descend from the first parent node, and wherein the second nodes include a second parent node and second remaining nodes that descend from the second parent node; grouping the first nodes into a first packed node stored in first physically contiguous locations of the memory, wherein the first nodes are sequenced in the first physically contiguous locations according to respective depth levels of the first nodes within the decision tree; and grouping the second nodes into a second packed node stored in second physically contiguous locations of the memory, wherein the second nodes are sequenced in the second physically contiguous locations according to respective depth levels of the second nodes within the decision tree; wherein the first packed node has a first set of local addresses for linking the first parent node through first pointers to the first remaining nodes, and wherein the second packed node has a second set of local addresses for linking the second parent node through second pointers to the second remaining nodes.