Patent ID: 9721647
Date: 2017-08-01
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a memory array which include a plurality of memory cells arranged in a matrix; word lines which are provided and correspond respectively to rows of the memory array; word line drivers which are coupled to ends of the word lines, and activate the word lines by coupling the ends of the word lines to a first power source, when a corresponding row is selected; and assist drivers which are coupled to other ends of the word lines, and couple the other ends of the word lines to the first power source in accordance with a voltage of the other ends of the word lines, wherein each of the assist drivers includes a PMOS transistor provided between a power source and the other end of a corresponding word line, wherein each of the assist drivers includes a NAND circuit, having one input coupled to the other end of the word line, another input receiving a control signal pulse, and an output coupled to a gate of the PMOS transistor, wherein a signal wiring is arranged on an outside of the memory array, in a direction horizontal to a substrate where the semiconductor device is implemented, wherein the control signal pulse is transmitted through the signal wiring, and wherein the control signal pulse is commonly shared by a plurality of assist drivers coupled to the other ends of their corresponding word lines.