Patent ID: 9712170
Date: 2017-07-18
CPC Classifications: G06F,H03K

Claim:
1. A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, the first voltage domain having a first supply voltage and the second voltage domain having a second supply voltage, comprising: an input node to receive an input signal provided by the first circuit; a first output node to output a level-shifted output signal, corresponding with the input signal, to the second circuit; a first latch for storing the input signal in the first voltage domain, wherein the first latch has a first node and a second node, wherein the input node is selectively coupled to the first node; a second latch for storing the input signal in the second voltage domain, wherein the second latch has a third node and a fourth node, wherein the first output node is coupled to the fourth node; a first switching element serially coupled between the first node and the third node, wherein the first switching element is closed when a voltage at the second node is high, wherein the first switching element, when closed, provides a path to transfer a low voltage at the first node to the third node; a second switching element serially coupled between the second node and the fourth node, wherein the second switching element is closed when a voltage at the first node is high, wherein the second switching element, when closed, provides a path to transfer a low voltage at the second node to the fourth node; a first N-channel metal oxide semiconductor (NFET) transistor serially connected between the first node and ground; a second NFET transistor serially connected between the third node ground, wherein a gate of the first NFET transistor and a gate of the second NFET transistor connected to a RESET control signal; a third NFET transistor serially connected between the second node and ground; and a fourth NFET transistor serially connected between the fourth node and ground, wherein a gate of the third NFET transistor and a gate of the fourth NFET transistor connected to a SET control signal.