Patent ID: 9575115
Date: 2017-02-21
CPC Classifications: G01R,H01L

Claim:
1. A method of sorting integrated circuit devices, said method comprising: manufacturing said integrated circuit devices on a wafer according to an integrated circuit design using manufacturing equipment, said integrated circuit design producing identically designed integrated circuit devices that perform differently based on manufacturing process variations, said identically designed integrated circuit devices being for use in a range of environmental conditions, to satisfy needs of different customers; performing testing on said identically designed integrated circuit devices using testing equipment to produce test results; individually predicting environmental maximums for each identically designed integrated circuit device of said identically designed integrated circuit devices using a computerized device operatively connected to said testing equipment, said environmental maximums corresponding to said environmental conditions that must not be exceeded for each said identically designed integrated circuit device to perform above a given failure rate; assigning each said identically designed integrated circuit device at least one grade based on said environmental maximums predicted for each said identically designed integrated circuit device, using said computerized device; and sorting each of said identically designed integrated circuit devices to satisfy needs of different customers, based on said at least one grade assigned to each said identically designed integrated circuit device, using said computerized device based on said predicted environmental maximums.