Patent ID: 9666723
Date: 2017-05-30
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising a memory cell, the memory cell comprising a transistor and a capacitor, wherein the transistor comprises: an oxide semiconductor film comprising: a source electrode layer and a drain electrode layer over the oxide semiconductor film; a gate electrode layer over the oxide semiconductor film; and a gate insulating film between the oxide semiconductor film and the gate electrode layer, wherein the capacitor comprises one of the pair of the first regions and one of the pair of second regions, wherein the one of the pair of first regions of the capacitor functions as a dielectric of the capacitor, wherein the one of the pair of first regions and the one of the pair of second regions are stacked, and the other of the pair of first regions and the other of the pair of second regions are stacked, wherein a resistance value of the pair of first regions is higher than a resistance value of the pair of second regions, and wherein the oxide semiconductor film comprises a carrier concentration being less than or equal to 1×10