Patent ID: 9570300
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor structure, said method comprising: providing a first semiconductor material of a first lattice constant, said first semiconductor material having a surface containing at least one recessed region and non-recessed regions adjoining said at least one recessed region; forming a second semiconductor material of a second lattice constant that is different from said first lattice constant on said surface of said first semiconductor material, wherein said second semiconductor material is strained; converting said second semiconductor material that is strained into a strain relaxed buffer layer, said strain relaxed buffer layer containing misfit dislocation defects and threading dislocation defects; and annealing said strain relaxed buffer layer to propagate and amass said misfit dislocation defects and threading dislocation defects at a sidewall of each of said non-recessed regions of said first semiconductor material, wherein said annealing forms a first region located in said strain relaxed buffer layer that is located directly above said at least one recessed region of said first semiconductor material, while forming second regions that are located directly above each non-recessed region of said first semiconductor material, wherein each first region has a first threading dislocation defect density and each second region has a second threading dislocation defect density that is greater than said first threading dislocation defect density.