Patent ID: 9659662
Date: 2017-05-23
CPC Classifications: G11C

Claim:
1. A method of erasing a nonvolatile memory device comprising a plurality of memory blocks formed in a direction perpendicular to a substrate, each memory block having a plurality of strings connected to a bit line, and an address decoder configured to select a memory block of the plurality of memory blocks, the method comprising: selecting a memory block of the plurality memory blocks to be erased using a power supply voltage for turning on a first ground pass transistor corresponding to the selected memory block; unselecting a remaining memory block of the plurality of memory blocks, other than the selected memory block, using a negative voltage for turning off a second ground pass transistor corresponding to the unselected memory block; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block, wherein the address decoder comprises: