Patent ID: 9589611
Date: 2017-03-07
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a memory cell array; and a column driver, wherein the memory cell array includes: wherein the plurality of memory cells are each electrically connected to the write word line, the read word line, the write bit line, the read bit line, and the source line, wherein the plurality of memory cells each include a retention node, a first transistor, a second transistor, and a capacitor, wherein the first transistor includes a gate electrically connected to the write word line, a first terminal electrically connected to the write bit line, and a second terminal electrically connected to the retention node, wherein the second transistor includes a gate electrically connected to the retention node, a first terminal electrically connected to the source line, and a second terminal electrically connected to the read bit line, wherein the capacitor includes a first terminal electrically connected to the retention node and a second terminal electrically connected to the read word line, wherein, in the column driver, a sense amplifier is provided for each column, wherein the sense amplifier includes a first node and a second node for retaining complementary data, wherein the sense amplifier is configured to amplify first data, retain the amplified first data, and retain second data, wherein the first data is data read from the memory cell to the read bit line, wherein the second data is data written to the memory cell in a write target column, wherein the column driver is configured to control input of the second data to the sense amplifier in the write target column, control electrical continuity between the first node and the read bit line to input the first data to the sense amplifier, and control electrical continuity between the second node and the write bit line to write retention data of the sense amplifier to the write bit line, and wherein the retention data is the first data or the second data.