Patent ID: 9651617
Date: 2017-05-16
CPC Classifications: G01R,G06F,G11C

Claim:
1. In a memory, a method comprising: arranging a plurality of addresses of a memory array as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array; selecting a current location in the matrix, wherein a column of the current location corresponds to a destination address of a memory transition, wherein the destination addresses identifies a candidate row of the matrix which corresponds to the destination address, wherein the candidate row is different from a row of the current location; determining a next location that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row; recording the next location; and performing a read access to an address of the memory array corresponding to a row of the next location.