Patent ID: 9673963
Date: 2017-06-06
CPC Classifications: H04L

Claim:
1. A method for generating a data signal and a clock signal, the method comprising: receiving an input data signal transmitted without a reference clock signal; generating, by a clock regeneration loop and based on the input data signal, an output reference clock signal having an adjustable clock frequency that matches a data rate of the input data signal; generating, by a data detection loop and based on the input data signal, a phase offset control signal for adjusting a phase of a clock signal that samples the input data signal; generating, by the data detection loop and based on the phase offset control signal, a sampled input data signal; storing, by an elastic buffer, an overflowing portion or an under-flowing portion of the sampled input data signal resulting from a frequency difference between the output reference clock signal and the sampled input data signal; and generating, by the elastic buffer and based on the stored overflowing portion or the under-flowing portion of the sampled input data signal, an output data signal that aligns with the output reference clock signal, wherein the data detection loop includes a delay locked loop, a phase interpolator, and a phase detector, wherein generating the phase offset control signal further comprises: