Patent ID: 9690213
Date: 2017-06-27
CPC Classifications: B82Y,G03F,H01J

Claim:
1. A linear stacked stage, comprising: a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis at a first selected speed, the first upper fast stage configured to secure the first plurality of wafers; a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis at a second selected speed, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and a carrier stage configured to translate the first upper fast stage and the second upper fast stage along a second axis substantially orthogonal to the first axis at a third selected speed, the first upper fast stage and the second upper fast stage disposed on the surface of the carrier stage, wherein the first upper fast stage, the second upper fast stage and the carrier stage are configured to scan one or more wafers of at least one of the first plurality of wafers or the second plurality of wafers under a plurality of electron columns, wherein the third selected speed of the carrier stage is slower than the first selected speed of the first upper fast stage and the second selected speed of the second upper fast stage.