Patent ID: 9614069
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of fabricating a multi-layer semiconductor structure for use in a III-Nitride (III-N) semiconductor device, comprising: forming a channel layer comprising a first III-N material for providing electrical conduction; forming a barrier layer comprising a second III-N material above the channel layer, forming a pair of ohmic recesses by patterning and etching of the barrier layer; depositing a pair of ohmic electrodes in the pair of ohmic recesses respectively; forming a gate recess by patterning and etching of the barrier layer, wherein the gate recess is positioned in-between the pair of ohmic recesses; depositing a first filler layer covering a bottom of the gate recess, wherein the first filler layer comprises a first insulating material; recessing a recess through the first filler layer, wherein a length of the recess through the first filler layer is smaller than that of the gate recess, to form a first filler element at a bottom of the gate recess; and depositing a gate electrode in the gate recess, wherein the gate electrode is stepped by the first filler element to form a bottom stem and a bottom step within the gate recess.