Patent ID: 9741734
Date: 2017-08-22
CPC Classifications: G11C,H01L

Claim:
1. A memory device, comprising: a contact region; a source select gate (SGS) layer disposed on the contact region; a tiered stack of semiconductor layers disposed on the SGS layer; a drain select gate (SGD) layer disposed on the tiered stack of semiconductor layers; a nitride isolation layer disposed on the SGD layer; an oxide isolation layer disposed on the nitride isolation layer; a central pillar extending from within the contact region to a position along an edge of the nitride isolation layer; a T-plug disposed on the central pillar and extending to a top surface of the oxide isolation layer, the T-plug further extending across a proximal portion of a top surface of the nitride isolation layer surrounding the central pillar; and an electrical contact disposed on the T-plug such that the T-plug protects against electrical shorting from the electrical contact to the SGD layer.