Patent ID: 9672900
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A semiconductor device comprising: a plurality of static memory cells arranged in rows and columns, each memory cell including access transistors, drive transistors and load transistors and for storing data therein; a plurality of word lines, arranged corresponding to the respective memory cell rows, each coupled to gates of the access transistors in the corresponding memory cells in a corresponding memory cell row; a plurality of word line drivers coupled to the plurality of word lines, respectively, for driving one of the plurality of word lines to a selected state according to a word line select signal; a plurality of pairs of data lines, arranged corresponding to the respective memory cell columns, each coupled to source-drain paths of the access transistors in the corresponding memory cells in a corresponding memory cell column; a plurality of power supply lines, arranged individually and corresponding to the respective memory cell columns, each coupled to cell power supply nodes of the memory cells in a corresponding column; read assist circuitry for lowering a voltage level of the corresponding word line arranged corresponding to the memory cells in a selected row in data reading; and write assist circuitry for lowering a voltage level of the corresponding power supply line arranged corresponding to the memory cells in a selected column in data writing wherein the read assist circuitry includes pull-down transistors that have the same layout as the access transistors.