Patent ID: 9619327
Date: 2017-04-11
CPC Classifications: G11C,H03M

Claim:
1. An operation method of a flash memory system including a controller, a memory device, and a host, the operation method comprising: obtaining first syndrome values by performing a first syndrome operation to a codeword provided from the memory device; obtaining locations of errors and the number of the locations of errors, which are included in codeword, based on the first syndrome values; error-correcting the codeword by flipping bit values of error bits of the codeword based on the locations of errors to generate an error-corrected codeword; obtaining second syndrome values by performing a second syndrome operation to the error-corrected codeword; determining whether an error is found in the error-corrected codeword based on the second syndrome values; changing the first syndrome values when it is determined that no error is found in the error-corrected codeword and providing the error-corrected codeword and a success flag to the host; and restoring the error-corrected codeword to the codeword by re-flipping the flipped bit values when it is determined that an error is found in the error-corrected codeword and providing the restored codeword to the host.