Patent ID: 9748144
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: providing a substrate having a first semiconductor structure, a second semiconductor structure, a contact etch stop layer (CESL) covering the first semiconductor structure and the second semiconductor structure, an inter-layer dielectric (ILD) layer covering the CESL, wherein the first semiconductor structure comprises a first dummy gate, a first nitride mask on the first dummy gate, and a first oxide mask on the first nitride mask, wherein the second semiconductor structure comprises a second dummy gate, a second nitride mask on the second dummy gate, and a second oxide mask on the second nitride mask; performing a first planarization process to remove a first portion of the ILD layer, thereby exposing a top surface of the CESL; then removing a portion of the CESL, a second portion of the ILD layer, the first oxide mask, and the second oxide mask to expose the first nitride mask and the second nitride mask; then removing a third portion of the ILD layer to form a recess in the remaining ILD layer between the first semiconductor structure and the second semiconductor structure; then forming a hard mask layer on the remaining first nitride mask, the remaining second nitride mask and the remaining ILD layer, wherein the hard mask layer fills up the recess; then performing a second planarization process to remove a portion of the hard mask layer, the remaining first nitride mask and the remaining second nitride mask, thereby exposing a top surface of the first dummy gate and a top surface of the second dummy gate, wherein a remaining portion of the hard mask layer covers a top surface of the remaining ILD layer between the first semiconductor structure and the second semiconductor structure; then removing the first dummy gate and the second dummy gate to form a first gate trench and a second gate trench; and then forming a first metal gate in the first gate trench and a second metal gate in the second gate trench.