Patent ID: 9619236
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. An apparatus comprising: a decoder to decode a first instruction with a first immediate operand into a decoded first instruction, a second instruction with a second immediate operand into a decoded second instruction, a third instruction with a third immediate operand into a decoded third instruction, and a fourth instruction with a fourth immediate operand into a decoded fourth instruction; instruction execution circuitry to execute: masking layer circuitry to mask the first resultant vector of said first instruction and the third resultant vector of the third instruction at a first resultant vector granularity specified by the first immediate operand and the third immediate operand, respectively, and mask the second resultant vector of said second instruction and the fourth resultant vector of the fourth instruction at a second resultant vector granularity specified by the second immediate operand and the fourth immediate operand, respectively.