Patent ID: 9721835
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method for forming an electrical interconnect structure, comprising: patterning a dielectric substrate to form a trench feature, a via feature, or combinations thereof; lining the patterned dielectric layer with a conductive liner layer; forming a metal interconnect layer on the conductive liner layer, wherein the metal interconnect layer is W and alloys thereof; forming a metal stress locking layer directly on the metal interconnect layer to lock stress and extend an elastic region of the metal during annealing so that relaxation by surface diffusion is reduced, wherein the metal stress locking layer is a metal and cobalt or the metal and a cobalt-containing material, wherein the metal is selected from the group consisting of Al, Ni, Au, Ag, Rh, Fe, and alloys thereof and further comprises; annealing the metal interconnect layer at an elevated temperature for a period of time effective to recrystallize the metal interconnect layer; removing the metal stress locking layer; and removing portions of the metal interconnect layer and the conductive liner layer apart from the trench and/or via features.