Patent ID: 9582419
Date: 2017-02-28
CPC Classifications: G06F,Y02D

Claim:
1. A data processing device comprising: a plurality of storage circuits configured to store a plurality of data elements of b bits in an interleaved manner; and first instruction execution circuitry including a plurality of lanes, configured to be able to individually access each of said plurality of storage circuits and to receive into said plurality of lanes one of the set of (a) and (b): (a) a subset of said plurality of data elements, and (b) y bits of each of said plurality of data elements, and wherein the first instruction execution circuitry is further configured to execute a common instruction on each of said plurality of lanes; wherein b is greater than y and is an integer multiple of y; wherein each of said plurality of storage circuits is configured to store a group of bits from each of said data elements, the group of bits comprising at most y bits, wherein the respective groups of bits stored in the same one of said storage circuits comprise at least one group of bits corresponding to a first subset of bit positions of a corresponding data element and at least one group of bits corresponding to a second subset of bit positions of a different corresponding data element, wherein the second subset of bit positions is different than the first subset of bit positions; wherein each of said plurality of storage circuits is configured to store at most y/b of said plurality of data elements; and wherein said plurality of storage circuits comprise no more than b/y storage circuits.