Patent ID: 9575105
Date: 2017-02-21
CPC Classifications: A61B,G01R

Claim:
1. A circuit to measure impedance in the time domain, the circuit comprising: an analog input signal generator that generates an analog input signal; a measurement path that comprises a device under test and generates a measurement signal in response to the analog input signal; a calibration path that generates a calibration signal in response to the analog input signal; a sampling circuit selectively coupled to the measurement path and the calibration path to generate respective first and second circuit responses; a clock signal to synchronize a start of the analog input signal generation with the at least one of the measurement signal and the calibration signal; and a digital baseband quadrature sampling receiver coupled to the sampling circuit, the digital baseband quadrature sampling receiver down-converts the first and second circuit responses to generate a quadrature signal that comprises in-phase and quadrature components and eliminates terms associated with path components common to the first and second response to determine a complex impedance for the device under test at a predetermined testing frequency.