Patent ID: 9653394
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend longitudinally in a first direction, one first line of the first lines connected, through a via contact, to a first conductive area selected from the plurality of conductive areas; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend longitudinally in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line; and at least one source/drain area formed in an active area of the substrate and at least one gate formed on the active area, and wherein the plurality of conductive areas comprise at least one first contact that is connected to the at least one source/drain area and at least one second contact that is connected to the at least one gate.