Patent ID: 9685396
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A semiconductor die arrangement comprising: a first die including at least one semiconductor device; a second die including at least one semiconductor device; and a lead frame receiving the first die and comprising one or more lead fingers, wherein the second die is mounted on one of the lead fingers and electrically connected to a plurality of further elements by a plurality of bond wires on the one of the lead fingers, wherein a first further element includes a terminal of the semiconductor device of the first die and a second further element includes a terminal of a further die stacked upon the first die, wherein the semiconductor device of the first die comprises a triac having a gate terminal and two anode terminals, wherein the semiconductor device of the second die comprises a diode having a first terminal and a second terminal, the first terminal electrically connected to the lead finger, wherein the semiconductor device of the further die comprises a thyristor or silicon-controlled rectifier (SCR) stacked upon and electrically connected to one of the two anode terminals of the triac, and wherein a bondwire electrically connects the gate terminal of the triac to the second terminal of the diode.