Patent ID: 9673795
Date: 2017-06-06
CPC Classifications: H03K,H03L,H04L

Claim:
1. An integrated circuit associated with a clock generator providing a local clock signal, comprising: a data sampler, configured to provide a plurality of signal samples at a speed that is twice a symbol rate according to the local clock signal and an inverted local clock signal, the signal samples comprising a first symbol sample and a second symbol sample, the second symbol sample being later than the first symbol sample by one symbol period, the signal samples further comprising an interpolated sample between the first and second symbol samples; and a digital logic circuit, configured to compare the first symbol sample with the interpolated sample to generate pre phase correction data, and to compare the second symbol sample with the interpolated sample to generate post phase correction data, wherein the pre phase correction data is generated earlier than the post phase correction data; wherein, the local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.