Patent ID: 9722629
Date: 2017-08-01
CPC Classifications: H03M

Claim:
1. An apparatus for conversion of a floating point representation to a signed integer representation, the floating point representation including a sign, an exponent, and a mantissa, the apparatus comprising: shift conditioning circuitry configured to generate a shift control signal based at least in part on the exponent; two's complement circuitry configured to operate at least partially in parallel with the shift conditioning circuitry, the two's complement circuitry configured to generate a pre-shift output, the pre-shift output corresponding to a representation, in two's complement format, of the sign and the mantissa; and shift execution circuitry configured to shift the pre-shift output by a number of bit positions specified at least in part by the shift control signal; wherein the shift execution circuitry outputs the signed integer representation under a predefined condition; wherein the exponent is expressed using E bits, and wherein the shift conditioning circuitry is further configured to generate the shift control signal based on a scaling factor input and an exponent bias value, the exponent bias value equal to 2 E−1 −1, the shift conditioning circuitry comprising: an inverter configured to operate on a most significant bit of the exponent to provide a modified exponent value, the modified exponent value corresponding to the exponent having the most significant bit thereof inverted; and an adder configured to receive the scaling factor input and the modified exponent value as summand inputs and to provide the shift control signal as output, the adder configured to receive an external carry input of logical ‘1’.