Patent ID: 9646758
Date: 2017-05-09
CPC Classifications: H01F,H01L

Claim:
1. A method of fabricating integrated circuit (IC) devices, comprising: forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area, wherein the top interconnecting elements are formed concurrently with the top inductor structure; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area, wherein the bottom interconnecting elements are formed concurrently with the bottom inductor structure; forming a mask over each of the top and bottom inductor structures; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; removing the mask; and connecting the top and bottom interconnecting elements to each other.