Patent ID: 9608649
Date: 2017-03-28
CPC Classifications: H03L,H04B,H04L

Claim:
1. An analog phase-locked loop (PLL) comprising: a voltage controlled oscillator (VCO); a frequency divider having its input connected to an output of the VCO; a first phase detector arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and to provide an output signal on an output of the first phase detector based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump connected to the output of the first phase detector and arranged to output a charge per detected phase difference based on the output signal on the output of the first phase detector; an analog loop filter connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO; a second phase detector arranged to detect a signed integer number of cycles in phase difference between the output signal of the frequency divider and the reference frequency signal and to provide an output signal on an output of the second phase detector based on the signed integer number of cycles in phase difference; and a second charge pump connected to the output of the second phase detector and arranged to provide a charge per detected phase difference, based on the output of the second phase detector, to the loop filter.