Patent ID: 9660032
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a substrate; forming a strain relaxed buffer on a surface of the substrate, the strain relaxed buffer having a bottom surface disposed on the surface of the substrate and an opposite top surface, the strain relaxed buffer being formed to comprise of a plurality of pairs of layers, where a given pair of layers is composed of a layer of Si forming a plurality of transistor devices above the top surface of the strain relaxed buffer; and forming at least one contact through the top surface of the strain relaxed buffer and partially through a thickness of the strain relaxed buffer, the at least one contact being disposed transverse to a side of a fin of at least one transistor of the plurality of transistor devices, the at least one contact being thermally coupled to at least one of the plurality of the Si layers for conducting heat out of the strain relaxed buffer via the at least one of the plurality of Si layers.