Patent ID: 9711566
Date: 2017-07-18
CPC Classifications: G11C,H01L

Claim:
1. A method of forming an integrated circuit device comprising: forming a first metal layer, wherein the first metal layer is patterned to support connections with magnetoresistive devices and logic devices; forming the magnetoresistive devices over the first metal layer, wherein the magnetoresistive devices are electrically coupled to respective portions of the first metal layer, wherein each magnetoresistive device has a magnetoresistive device height, wherein the magnetoresistive device height is less than or equal to a height of a second metal layer added to a height of a first interlayer dielectric layer; forming the first interlayer dielectric layer over the first metal layer; forming first-level vias in the first interlayer dielectric layer, wherein the first-level vias provide electrical connections between the second metal layer and the first metal layer; forming the second metal layer over the first-level vias, wherein the second metal layer is pattered to support connections to the logic devices; forming a second interlayer dielectric layer over the second metal layer and the magnetoresistive devices; forming second-level vias within the second interlayer dielectric layer, wherein a first portion of the second level vias provides electrical connections between a third metal layer and the second metal layer, and wherein a second portion of the second-level vias provides electrical connections between the third metal layer and a top portion of each of the magnetoresistive devices; and forming the third metal layer over the second level vias, wherein the third metal layer is patterned to support connections to the magnetoresistive devices and the logic devices.