Patent ID: 9647539
Date: 2017-05-09
CPC Classifications: G06F,H02M

Claim:
1. A charge pump for use in a touch panel, comprising a chip, a package substrate and a circuit board, wherein: said chip comprises a clock generator, a first clock terminal and a second clock terminal respectively and electrically coupled to said clock generator, a transistor set, an input terminal set comprising a first input end and at least three second input ends, a load circuit and an output terminal, said transistor set comprising a first transistor and at least three second transistors respectively and electrically coupled to said first input end and said at least three second input ends of said input terminal set, said at least three second input ends being arranged into two rows subject to odd number and even number, each said second input end of odd number being disposed adjacent to said first clock terminal, each said second input end of even number being disposed remote from said first clock terminal, said first transistor of said transistor set being electrically coupled to said first input end by a straightly extended trace, said at least three second transistors being arranged into rows subject to odd number and even number and respectively electrically coupled to said at least three second input ends by respective traces, each two adjacent said second transistors being electrically coupled to one another with the last said second transistor electrically coupled to said load circuit, said load circuit being electrically coupled to a touch panel; said package substrate carries said package substrate, comprising a first clock pin, a second clock pin and an external pin set, said first clock pin and said second clock pin being respectively electrically coupled to said first clock terminal and said second clock terminal of said chip, said external pin set comprising a first external pin located at one side and at least three second external pins located at an opposite side, said at least three second external pins being arranged in two rows subject to odd number and even number, said first external pin being electrically coupled to said first input end of said chip, said at least three second external pins being respectively electrically coupled to said at least three second input ends of said chip; said circuit board carries said package substrate, comprising a capacitor set, a first circuit, a second circuit and a logic high/low power supply, said capacitor set comprising at least three capacitors arranged in two rows subject to odd number and even number, said logic high/low power supply being electrically coupled to said first external pin of said package substrate, said first circuit and said second circuit being adapted for electrically coupling the two rows of said at least three said second external pins to the two rows of said at least three capacitors, the odd number said capacitor being electrically coupled to said first clock pin of said package substrate by said first circuit, the even number said capacitors being electrically coupled to said second clock pin of said package substrate by said second circuit.