Patent ID: 9588572
Date: 2017-03-07
CPC Classifications: G06F,Y02D

Claim:
1. A microprocessor, comprising: a plurality of processing cores, each comprising a respective interrupt request input; a control unit, configured to receive a respective synchronization request from each of the plurality of processing cores; wherein the control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores; and wherein each of the respective synchronization requests comprises a value written by the processing core, wherein the value written by each of the plurality of processing cores includes an indicator that indicates whether or not the value includes a sleep state, wherein the control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores and all of the indicators indicate the value includes a sleep state.