Patent ID: 9711223
Date: 2017-07-18
CPC Classifications: G11C

Claim:
1. A method comprising: applying a first voltage to a first line of a device during a memory operation performed on a first plurality of non-volatile memory cells and a second plurality of non-volatile memory cells of the device, the first plurality of non-volatile memory cells arranged in a first string, the second plurality of non-volatile memory cells arranged in a second string, wherein the first plurality of non-volatile memory cells are coupled to the first line through a base of a first bipolar junction transistor of the device, the second plurality of nonvolatile memory cells are coupled to the first line through a base of a second bipolar junction transistor of the device, the first plurality of non-volatile memory cells coupled between the first line and a second line, the second plurality of non-volatile memory cells coupled between the first line and the second line, and wherein the second line includes a data line and the first line includes a source line; and applying a second voltage to the base of each of the first and second bipolar junction transistors during the memory operation, wherein the memory operation includes an erase operation.