Patent ID: 9686034
Date: 2017-06-20
CPC Classifications: H04J,H04L

Claim:
1. A method of providing a path delay asymmetry for time synchronization between a master clock at a first client node and a slave clock at a second client node, the method comprising: receiving, at a path delay asymmetry calculation element, a determined forward mapping delay incurred as a result of mapping a first time protocol signal carrying time protocol data of the master clock onto a first transmission signal for transmission across a server communications network to the second client node; receiving, at the path delay asymmetry calculation element, a determined reverse mapping delay incurred as a result of mapping a second time protocol signal carrying time protocol data of the slave clock onto a second transmission signal for transmission across the server communications network to the first client node; receiving, at the path delay asymmetry calculation element, a determined forward forward error correction (FEC) delay incurred as a result of applying FEC to the first transmission signal; receiving, at the path delay asymmetry calculation element, a determined reverse FEC delay incurred as a result of applying FEC to the second transmission signal; at the path delay asymmetry calculation element, calculating a path delay asymmetry in dependence on the forward mapping delay, the reverse mapping delay, the forward FEC delay and the reverse FEC delay; and providing the calculated path delay asymmetry to a time protocol client at the second client node.