Patent ID: 9666267
Date: 2017-05-30
CPC Classifications: G11C,H01L

Claim:
1. A method of adjusting threshold voltage in a memory device comprising: providing a static random access memory (SRAM) device comprising at least two p-type pull up transistors, at least two n-type pull down transistors, a first pass gate transistor and a second pass gate transistor on a substrate, wherein the at least two p-type pull up transistors and the at least two n-type pull down transistors provide a storage cell, and the first and the second pass gate transistors provide an access to the storage cell, and wherein the at least two p-type pull up transistors and the at least two n-type pull down transistors overlie a charge storage element present in a dielectric layer of the substrate; measuring a test electrical property of at least one of the at least two p-type pull up transistors and the at least two n-type pull down transistors; and applying at least one of a voltage to a bit line (BL) that is electrically connected to source/drain regions of the first pass gate transistor, a voltage to a bit line complement (BLC) that is electrically connected to source/drain regions of the second pass gate transistor, a voltage to a word line (WL) that is electrically connected to gate structures of the first and the second pass gate transistors, a positive supply voltage to at least one of the at least two p-type pull up transistors and a negative supply voltage to at least one of the at least two n-type pull down transistors, and a voltage to the substrate, wherein a charge is collected in the charge storage element of the dielectric layer for a time period that adjusts the test electrical property of the at least one of the at least two p-type pull up transistors and the at least two n-type pull down transistors towards a target electrical property.