Patent ID: 9589892
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method of forming an interconnect structure, the method comprising: forming a contact layer over a substrate; forming a dielectric layer over the contact layer; forming an opening through the dielectric layer to an exposed portion of the contact layer; forming an alloy layer along sidewalls of the opening and the exposed portion of the contact layer, wherein the alloy layer comprises a main metal and an additive metal, and a ratio of the additive metal to the main metal is from about 0.01 atomic percent to about 25 atomic percent; forming a glue layer over the alloy layer; performing a thermal treatment to form a silicide layer, the alloy layer over and in contact with the silicide layer, the silicide layer adjacent the exposed portion of the contact layer, wherein the thermal treatment further forms a barrier layer interposed between the dielectric layer and the alloy layer, wherein the barrier layer comprises manganese oxide (MnO forming a conductive plug over the glue layer in the opening.