Patent ID: 9714980
Date: 2017-07-25
CPC Classifications: G01R

Claim:
1. An integrated circuit comprising: a differential data input buffer having differential inputs and an output; a differential data output buffer having an input and differential outputs; a differential clock input buffer having differential inputs and a clock output; parallel scan paths having stimulus data inputs, response data outputs, and a control input; a test stimulus data register having a serial input coupled to the data input buffer output, a serial header output, parallel outputs coupled to the stimulus data inputs, and a control input; a test command register having a serial input coupled to the header output, a command output, and a control input; a test response data register having parallel inputs coupled to the response data outputs, a serial output coupled to the data output buffer input, and a control input; a test controller having a scan clock input coupled to the clock output, a command input coupled to the command output, and control outputs coupled to the control inputs.