Patent ID: 9618997
Date: 2017-04-11
CPC Classifications: G06F,Y02D

Claim:
1. A processor comprising: a plurality of cores to independently execute instructions; and a power controller coupled to the plurality of cores to control a frequency at which the processor is to operate, the power controller to limit a maximum operating frequency of the processor to less than a configured maximum operating frequency, wherein the power controller is to analyze a plurality of power state change events in which a change in a number of active cores of the plurality of cores occurs during an evaluation interval to determine, for each of N-core turbo frequencies, a number of frequency transitions if the processor was to operate at the N-core turbo frequency at occurrence of the plurality of power state change events, select one of the N-core turbo frequencies to be the maximum operating frequency for a next operating interval based at least in part on the number of frequency transitions, and control the plurality of cores to operate at no higher than the selected N-core turbo frequency for the next operating interval.