Patent ID: 9734949
Date: 2017-08-15
CPC Classifications: H01G,H01L,Y10T

Claim:
1. A method of fabricating a capacitor, the method comprising: alternately forming N planar conductors with N−1 dielectrics on a substrate thereby forming a stacked body, N being a natural number greater than 2; removing portions of the stacked body to progressively uncover respective portions on at least N−1 of each of opposite ends of the N planar conductive layers, the respective portions on each of the N−1 planar conductive layers formed such that overlying remaining ones of the N planar conductive layers or the N−1 dielectric material layers do not cover the respective portions of a lower one of the N planar conductive layers, at least some of the N planar conductive layers to electrically couple contacts formed starting at respective ones of the N planar conductive layers in a direction substantially normal to the respective ones of the N planar conductive layers at only one or both ends, thereby avoiding locating contacts at a point intermediary between the ends of respective ones of the N planar conductive layers; and forming a first contact, a second contact, and a third contact each electrically coupled to a first planar conductive layer, a second planar conductive layer, and a third planar conductive layer of the N planar conductors, the first contact being disposed on a first lateral side of a first end upper surface portion of the first planar conductive layer, the second contact being disposed on a second lateral side of the first end upper surface portion of the second planar conductive layer, and the third contact being disposed on a first lateral side of the first end upper surface portion of the third planar conductive layer, the first contact and the third contact being formed to be directly coupled to a first contact electrode, and the second contact being formed to be directly coupled to a second contact electrode coplanar with the first contact electrode.