Patent ID: 9748235
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of forming a gate stack for an integrated circuit structure, the method comprising: forming an oxide nitridation layer over the set of fins; after the forming of the oxide nitridation layer, forming a layer having a high dielectric constant over the set of fins; after the forming of the oxide nitridation layer, forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species to tune a work function of the first work function metal; removing a portion of the implanted first work function metal from over the first fin such a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species to tune a work function of the second work function metal; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.