Patent ID: 9653345
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor structure, comprising: forming an inter metal dielectric (IMD) layer on a semiconductor substrate; forming a patterned hard mask layer on the IMD layer; forming a first aperture in the IMD layer; forming a first barrier layer on the patterned hard mask layer and a surface of the first aperture; forming a first patterned resist on the first barrier layer; forming a first bottom anti-reflection coating (BARC) on the first barrier layer before the step of forming first patterned resist, wherein the first aperture is filled with the first barrier layer and the first BARC, and the first patterned resist is formed on the first BARC; and performing an etching process to form a second aperture in the IMD layer by using the first patterned resist as a mask, wherein the second aperture is separated from the first aperture.