Patent ID: 9658398
Date: 2017-05-23
CPC Classifications: G02B,Y10T

Claim:
1. A method of for aligning two substrates comprising at least one patterned waveguide layer implementing photonic waveguides, wherein a length from one edge of one substrate to an opposing edge of the one substrate has an associated manufacturing tolerance, and wherein the method comprises: patterning a waveguide path such that a waveguide forms a non-orthogonal intersection with one edge of the substrate on which the waveguide resides; further patterning the waveguide path such that the waveguide forms substantially the same non-orthogonal angle with the opposite edge of the substrate, wherein the two edges are substantially parallel and wherein the waveguide path is substantially mirror-symmetrical in shape relative to a line at or near the center of the waveguide path; and providing a lateral offset during substrate-to-substrate bonding in order to compensate for misalignment in optical coupling which occurs as a result of the manufacturing tolerance in a given geometric dimension of the substrate; wherein the two substrates are a chip and a package, respectively, and wherein the package contains a recessed cavity which receives the chip; and wherein the recessed cavity comprises staircase features and the patterned waveguide layer comprises pedestal features, wherein the rise and run of the staircase features are matched to the pedestal features such that misalignment in optical coupling due to a given geometric dimensional tolerance of at least one of the two substrates is compensated when a portion of the pedestal features are pushed substantially flush against a portion of the staircase features.