Patent ID: 9543953
Date: 2017-01-10
CPC Classifications: G11C,H01L,H03K

Claim:
1. A semiconductor device comprising: a first circuit node supplied with a first signal changing between first and second logic levels; a second circuit node supplied with a second signal changing between the first and second logic levels; a third circuit node; a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level; a fourth circuit node supplied with a voltage level being close to or the same as the second logic level; and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level, the first transistor being configured as a floating body type in which a body between a source and a drain is in an electrically floating state; a fifth circuit node supplied with a third signal changing between the first and second logic levels; a third transistor having a gate electrically connected to the fifth circuit node and a source-drain path electrically connected in series with the first transistor between the second and third circuit nodes, the third transistor rendered conductive when the third signal is at the second logic level; and a fourth transistor having a gate electrically connected to the fifth circuit node and a source-drain path electrically connected in parallel with the second transistor between the third and fourth circuit nodes, the third transistor rendered conductive when the third signal is at the first logic level, the third transistor being configured as the floating body type.