Patent ID: 9606407
Date: 2017-03-28
CPC Classifications: G02F,H01L

Claim:
1. A display panel, comprising: a thin film transistor substrate, comprising: a substrate; a thin film transistor disposed on the substrate and having a drain; a first insulating layer disposed on the drain and having a first via above the drain: a planarization layer disposed on the first insulating layer and having a second via above the drain, wherein the first via and the second via are partially overlapped to form an overlap portion; a second insulating layer disposed on the planarization layer; and a pixel electrode layer disposed on the second insulating layer, and the pixel electrode layer disposed in the overlap portion to connect to the drain, wherein the second via has a first edge and a second edge, a portion of the pixel electrode layer is disposed on the first edge and in contact with the planarization layer, and a portion of the pixel electrode layer is disposed on the second edge and in contact with the second insulating layer; and an opposite substrate disposed opposite to the thin film transistor substrate, wherein an area of the overlap portion is between 4 square microns and 49 square microns.