Patent ID: 9665430
Date: 2017-05-30
CPC Classifications: G06F,G11C,H03M,H04L

Claim:
1. An electrically erasable programmable memory device comprising: a first receiver to receive a write command and a first error detection code from a controller; a plurality of second receivers to receive write data and a second error detection code from a controller, the second error detection code encoded by the controller in connection with the write data, wherein the plurality of second receivers are operable to receive the write data in accordance with one of a plurality of modes, a first mode including data comprising symbols respectively transferred on rising and falling edges per clock cycle of a clock signal, and a second mode including data transferred with one symbol per clock cycle; and a logic circuit, coupled to the plurality of receivers, to determine, using the second error detection code, if the received write data contains at least one error; and wherein the memory device is to wherein the plurality of second receivers are to receive the write data using the first mode and re-receive the write data using the second mode.