Patent ID: 9735253
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor device, the method comprising: forming a semiconductor structure on a bottom doped region on a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin; forming a liner on the gate and the semiconductor fin; forming a dielectric layer on the liner; removing portions of the liner to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer; forming a recessed opening by recessing portions of the liner from the exposed sidewall of the dielectric layer; and forming a top epitaxy region on the exposed top surface and sidewalls of the semiconductor fin and the exposed sidewall of the dielectric layer, an extension of the top epitaxy region filling the recessed opening, said top epitaxy region confined between portions of the liner.