Patent ID: 9640517
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A stacked electronic package, comprising: a substrate; a semiconductor die coupled to a first portion of an upper surface of the substrate, the semiconductor die comprising an integrated circuit; a discrete electronic component coupled to a second portion of the upper surface of the substrate, the discrete electronic component being separate from the semiconductor die, and the first portion of the upper surface of the substrate being different from the second portion of the upper surface; conductive straps each having sides, a top, and a bottom opposite the top, each conductive strap coupled along the bottom to the upper surface of the substrate and spaced from the semiconductor die and the discrete electronic component, a first one of the conductive straps disposed on a first side of the semiconductor die and a second one of the conductive straps disposed on a second side of the semiconductor die opposite the first side, each conductive strap being separate from others of the conductive straps and a length of at least one of the sides [of each conductive strap being greater than a width of at least another one of the sides; an encapsulant extending over the semiconductor die, the discrete electronic component, and the upper surface of the substrate and covering side surfaces of the substrate and the sides of the conductive straps; and a discrete passive electronic component disposed over the semiconductor die and the discrete electronic component, each conductive strap coupled along the top to a terminal of the discrete passive electronic component, each conductive strap extending between the substrate and the discrete passive electronic component without extending over the semiconductor die and the discrete electronic component, and each conductive strap including a cutout along the bottom.