Patent ID: 9741820
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method for fabricating a p-channel metal-oxide-semiconductor (PMOS) transistor, comprising: forming a dummy gate structure on a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure; forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate; and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer and performing a UV curing process after forming each of the first and second etching stop layers, wherein the intermediate layer is formed by a plasma-enhanced chemical vapor deposition process using a process gas containing NCO, N2 SiF, and SiH wherein the intermediate layer is formed by the plasma-enhanced chemical vapor deposition process using process parameters including: a flow rate of N20 in a range of 9000 sccm to 12000 sccm; a flow rate of N2 in a range of 5000 sccm to 10000 sccm; a flow rate of SiF4 in a range of 800 sccm to 1200 sccm; a flow rate of SiH4 in a range of 800 sccm to 1000 sccm; a pressure in the deposition chamber in a range of 2 torr to 4 torr; an RF power in a range of 1500 W to 2000 W; a deposition temperature in a range of 300° C. to 500° C.; and a deposition time in a range of 5 s to 100 s.