Patent ID: 9559005
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method of forming a packaged semiconductor device, comprising: receiving a wafer comprising a first die region, a second die region and a scribe line region between the first die region and the second die region, wherein the wafer comprises an interconnect structure on a semiconductor substrate, a plurality of contact pads on the interconnect structure, a passivation layer on the interconnect structure and overlying the plurality of contact pads, a protection layer on the passivation layer, the protection layer having an opening in the scribe line region exposing a top surface of the passivation layer, a plurality of post-passivation interconnect (PPI) structures on the protection layer and electrically connected to the plurality of contact pads, and at least one bump physically contacting at least one of the plurality of PPI structures; performing a first cutting process on the wafer to form a groove passing through the passivation layer, the interconnect structure and a portion of the semiconductor substrate on the scribe line region, wherein a portion of the top surface of the passivation layer remains exposed after the first cutting process; after performing the first cutting process, forming a molding compound layer on a frontside of the wafer to cover the protection layer and the PPI structures and fill the groove and surround the at least one bump, the at least one bump being present prior to forming the molding compound, the at least one bump protruding from the molding compound layer after forming the molding compound layer; performing a grinding process on a backside of the wafer to thin down the semiconductor substrate; and performing a second cutting process on the wafer to separate the first die region from the second die region, wherein the second cutting process cuts through the molding compound layer in the groove and the semiconductor substrate underlying the groove.