Patent ID: 9716087
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. An electrostatic discharge (ESD) protection semiconductor device, comprising: a substrate; a first well formed in the substrate, and the first well comprising a first conductivity type; a second well formed in the substrate and spaced apart from the first well, the second well comprising a second conductivity type, and the second conductivity type being complementary to the first conductivity type; a gate formed on the substrate and positioned in between the first well and the second well; a drain region formed in the first well and a source region formed in the second well, and the drain region and the source region comprising the first conductivity type; a first doped region formed in the first well and adjacent to the drain region, and the first doped region comprising the second conductivity type; and a second doped region formed in the first well and in between the first doped region and the gate, the second doped region being spaced apart from both the first doped region and the gate, and the second doped region comprising the second conductivity type.