Patent ID: 9576977
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming a stacked structure including interlayer insulating layers and sacrificial layers that are stacked alternately and penetrated by a hole, wherein the sacrificial layers include first oxidized regions surrounding the hole and non-oxidized regions surrounding the first oxidized regions, wherein the sacrificial layers extend farther toward the hole than the interlayer insulating layers; forming a base layer along a sidewall of the hole, wherein the base layer includes protrusions formed over the interlayer insulating layers and depressions formed over the sacrificial layers; removing the non-oxidized regions of the sacrificial layers to expose the first oxidized regions of the sacrificial layers; partially etching the first oxidized regions of the sacrificial layers to expose edges of the protrusions of the base layer; forming second oxidized regions by oxidizing the edges of the protrusions of the base layer to a predetermined thickness; exposing the depressions of the base layer and the edges of the protrusions of the base layer by removing the second oxidized regions of the base layer and the first oxidized regions of the sacrificial layers; and forming blocking insulation patterns by oxidizing the edges of the protrusions of the base layer and the depressions of the base layer.