Patent ID: 9607700
Date: 2017-03-28
CPC Classifications: G11C

Claim:
1. A method of operating a non-volatile memory device including a memory cell array including a plurality of memory cells vertically stacked on a substrate and configured to respectively store n-bit data, and a page buffer configured to write data in parallel in m memory cells of the plurality of memory cells, wherein the page buffer comprises m latch modules, each of which comprises n latches including an input latch, and each of m and n is an integer equal to or greater than 2, the method of operating the non-volatile memory device comprising: applying at least one pulse to a first cell group of the memory cell array to write first data stored in the m latch modules to the first cell group; releasing m input latches of the m latch modules based on states of memory cells of the first cell group, which are changed according to the at least one pulse; and transmitting second data to be written to a second cell group of the memory cell array in units of m-bit data to the m input latches; wherein releasing of the m input latches comprises dumping data stored in the input latch of each of the m latch modules to another latch of the n latches.