Patent ID: 9741812
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor structure comprising: source/drain regions present on opposite sides of at least one gate structure located over a channel region of a semiconductor fin; interlevel dielectric (ILD) portions overlying the at least one gate structure; and source/drain contact structures located within source/drain contact trenches that are laterally surrounded by the ILD portions, wherein each of the source/drain contact structures comprises a first contact conductor portion located at a bottom portion of one of the source/drain contact trenches and contacting one of the source/drain regions, and a second contact conductor portion overlying the first contact conductor portion, wherein the first contact conductor portion comprises a first metal and the second contact conductor portion comprises a second metal having a lower electromigration resistance and a lower electrical resistance than the first metal, and wherein each of the source/drain contact structures further comprises an elemental metal liner located over sidewalls of each of the source/drain contact trenches and a metal nitride liner located over the elemental metal liner and a bottom surface of each of the source/drain contact trenches, wherein the first contact conductor portion is surrounded by the metal nitride liner and wherein each of the source/drain contact structures further comprises a contact liner located over the metal nitride liner and a top surface of the first contact conductor portion, and an adhesion layer portion located over the contact liner, wherein the second contact conductor portion is surrounded by the adhesion layer.