Patent ID: 9638951
Date: 2017-05-02
CPC Classifications: G02B,G02F,G09G

Claim:
1. A liquid crystal panel comprising a color filter substrate and an array substrate disposed oppositely thereto, wherein the color filter substrate comprises a plurality of color filter pixel units, each of the color filter pixel units comprises six color filter sub-pixel units, the six color filter sub-pixel units being two diamond shaped color filter sub-pixel units and four isosceles triangle shaped color filter sub-pixel units and each of the six color filter sub-pixel units having a single color; every two isosceles triangle shaped color filter sub-pixel units are arranged into a sub-pixel column along a longitudinal direction with their vertex angles opposite to each other, and two sub-pixel columns are parallel to each other; the two diamond shaped color filter sub-pixel units and the two sub-pixel columns are disposed alternately in a horizontal direction; and colors of the diamond color filter sub-pixel units and the isosceles triangle shaped color filter sub-pixel units at least comprise red, blue and green, the array substrate comprises a plurality of array pixel units, each of the array pixel units comprises six array sub-pixel units, each of the six array sub-pixel units having a single color, and the six array sub-pixel units being two diamond shaped array sub-pixel units and four isosceles triangle shaped array sub-pixel units and, which correspond to locations of the six color filter sub-pixel units of one color filter pixel unit in the color filter substrate and each of which comprises a thin film transistor and a pixel electrode, each of the array pixel units is driven by a first gate line, a second gate line, and a first data line, a second data line, and a third data line, and each of the first, second, third data lines is electrically connected with two of the six array sub-pixel units, and each of the first and second gate lines is coupled with three of the six array sub-pixel units, wherein the first gate line is electrically connected with gates of thin film transistors of three of the six array sub-pixel units, the second gate line is electrically connected with gates of thin film transistors of other three of the six array sub-pixel units, the first data line is electrically connected with sources of two of the six array sub-pixel units, the second data line is electrically connected with sources of other two of the six array sub-pixel units, and the third data line is electrically connected with sources of remaining two of the six array sub-pixel units.