Patent ID: 9595587
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A method for fabricating a transistor device, the method comprising: a) forming a plurality of trenches in a semiconductor substrate, each trench in the plurality being lined with an insulating material along sidewalls inside each trench in the plurality; b) forming a bottom electrode in lower portions of each trench in the plurality; c) forming a top electrode in upper portions of each trench in the plurality, wherein the top electrode is separated from the bottom electrode by an inter-electrode insulating layer; and d) forming a plurality of contact structures, each contact structure in the plurality of contact structures being formed in a corresponding trench in the plurality of trenches in an area outside of an active region of the device, wherein each contact structure in the plurality of contact structures penetrates through an opening in a portion of the top electrode in the corresponding trench of the plurality of trenches and through an opening in a corresponding portion of the inter-electrode insulating layer beneath the top electrode in the corresponding trench of the plurality of trenches to reach the bottom electrode in the corresponding trench of the plurality of trenches, and wherein each contact structure in the plurality of contact structures is filled with a conductive material and provides electrical connection between the bottom electrode formed in the corresponding trench in the plurality of trenches and the top electrode formed in the corresponding trench in the plurality of trenches.