Patent ID: 9710323
Date: 2017-07-18
CPC Classifications: G06F,G11C

Claim:
1. A memory module comprising: multiple dynamic random access memory (DRAM) devices to store data; an address and command (ADD/CMD) signal line coupled to the DRAM devices and capable to couple to a memory controller, wherein the ADD/CMD signal line is capable to be driven with a command signal from the memory controller when coupled; and an error alert signal line coupled to the DRAM devices and capable to couple to the memory controller, one or more of the DRAM devices capable to drive an error alert signal on the error alert signal line in response to an error detection, wherein a DRAM device to be closest to the memory controller along a physical routing of the ADD/CMD signal line is to be farthest from the memory controller along a physical routing of the error alert signal line, and a DRAM device to be farthest from the memory controller along the physical routing of the ADD/CMD signal line is to be closest to the memory controller along the physical routing of the error alert signal line.