Patent ID: 9601566
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate; first and second semiconductor layers stacked in a vertical direction on a substrate, wherein the first semiconductor layer has a lateral recess relative to the second semiconductor layer; an isolation layer formed on the substrate, having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and a gate stack formed on the isolation layer and intersecting the fin, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer, wherein said portion of the isolation layer has a first surface extending in the vertical direction and facing and contiguous to the first semiconductor layer, and also a second surface, opposite to the first surface, extending in the vertical direction and facing and contiguous to the gate dielectric layer.