Patent ID: 9600392
Date: 2017-03-21
CPC Classifications: G06F,Y02D

Claim:
1. A system for tracking pipelined activity during off-core memory accesses, comprising: at least one processor core comprising at least one execution unit; at least one counter operative to track a number of cycles in which the at least one execution unit of the at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising a plurality of cycles, the at least one counter operative to track the number of cycles on at least one multi-cycle execution unit from among the at least one execution unit that requires more than one cycle to complete execution of at least one operation; and a controller for evaluating an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions tracked in the at least one counter during the interval.