Patent ID: 9654101
Date: 2017-05-16
CPC Classifications: H03K

Claim:
1. An integrated circuit comprising: a first power rail; a second power rail; a load power rail; a first set of transistors including first transistors that are coupled between the first power rail and the load power rail, each first transistor disposed in one of multiple power-multiplexer tiles, the power-multiplexer tiles configured in a chained arrangement; a second set of transistors including second transistors that are coupled between the second power rail and the load power rail, each second transistor disposed in one of the power-multiplexer tiles; and power-multiplexer circuitry configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors in a first direction along the chained arrangement and then sequentially turning on the second transistors of the second set of transistors in a second direction along the chained arrangement, the second direction opposite the first direction, and configured to switch access to power for the load power rail from the second power rail to the first power rail by sequentially turning off the second transistors of the second set of transistors in the first direction along the chained arrangement and then sequentially turning on the first transistors of the first set of transistors in the second direction along the chained arrangement.