Patent ID: 9741724
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of forming an integrated circuit, comprising the steps of: forming a plurality of well regions in a SRAM of said integrated circuit, said well regions alternating with substrate regions in SRAM cell regions of said SRAM; forming active areas in said SRAM, including at least one active area in a strap row of said SRAM, and active areas in a first SRAM cell region adjacent to said strap row and active areas in a second SRAM cell region adjacent to said strap row opposite from said first SRAM cell region, in which said at least one active area in said strap row is one of a well tie to an instance of said well regions or a substrate tap to an instance of said substrate regions; forming a photolithographic pattern on said integrated circuit, said photolithographic pattern including a periodic pattern of alternating lines and spaces in said first SRAM cell region, said second SRAM cell region and said strap row, so that said periodic pattern of alternating lines and spaces is continuous across said strap row, and a difference between a pitch length of said periodic pattern in said strap row and a pitch length of said periodic pattern in said first SRAM cell region and in said second SRAM cell region is within 10 percent.