Patent ID: 9741610
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure comprising a bottom layer of dielectric material with one or more metal-filled vias therethrough situated therein, the bottom layer of dielectric material being situated on a structure for the one or more underlying semiconductor devices, the starting metallization structure further comprising a first protective layer over the bottom layer, and a top layer of dielectric material over the first protective layer; forming a sacrificial layer of amorphous silicon over the top layer of dielectric material; forming a second protective layer over the sacrificial layer, the second protective layer comprising a metal nitride; forming at least one via through each layer above the one or more metal-filled vias to expose the metal of the one or more metal-filled vias; selectively removing a remainder of the second protective layer after forming the at least one via; and removing the sacrificial layer of amorphous silicon.