Patent ID: 9538645
Date: 2017-01-03
CPC Classifications: C03C,H05K

Claim:
1. A multilayer wiring substrate comprising: a plurality of insulating layers, each insulating layer comprising a glass ceramic; a plurality of internal conductor layers formed between the insulating layers; via conductors that penetrate through the insulating layers and that mutually connect the internal conductor layers in different layer locations; and surface conductor layers formed on an outer surfaces in a lamination direction of the insulating layers; wherein the insulating layers within a range of a predetermined thickness from the outer surface on which the surface conductor layer is formed are defined as outside insulating layers and the insulating layers located inward of the outside insulating layers are defined as inside insulating layers; wherein a first aspect ratio representing an oblateness and sphericity of an external filler contained in the outside insulating layers is larger than a second aspect ratio representing an oblateness and sphericity of an internal filler contained in the inside insulating layers; and wherein a thermal expansion coefficient of the outside insulating layers is smaller than a thermal expansion coefficient of the inside insulating layers.