Patent ID: 9727415
Date: 2017-08-08
CPC Classifications: G06F,G11C,H03M

Claim:
1. A configuration structure of a block memory, wherein the configuration structure comprises: a first port, a second port, an Error Checking and Correcting (ECC) module, and a First Input First Output (FIFO) module; wherein the first port includes a first clock terminal, a first clock enable terminal, a first write enable terminal, a first data input terminal, and a first address input terminal, wherein the read width and the write width of the first port have different values, and the read width of the first port is equal to the write width of the first port multiplied by the Nth power of two; wherein when the number of the read address of the first port is different from that of the write address of the first port, the number of address lines of the first address input terminal meets the bigger one of the number of read address of the first port and the number of write address of the first port, wherein the second port includes a second clock terminal, a second clock enable terminal, a second write enable terminal, a second data input terminal, and a second address input terminal, wherein the read width and the write width of the second port have different values, and the read width of the second port is equal to the write width of the second port multiplied by the Nth power of two, wherein when the number of the read address of the second port is different from that of the write address of the second port, the number of address lines of the second address input terminal meets the bigger one of the number of read address of the second port and the number of write address of the second port, wherein N is an integer, wherein the read width of the first port and the read width of the second port have different values, and the write width of the first port and the write width of the second port have different values, wherein when a first data is written into the first data input terminal, according to the bits of the first data, the control signal of the first write enable terminal controls the first data to be written into the block memory bit-wisely; wherein when a second data is written into the second data input terminal, according to the bits of the second data, the control signal of the second write enable terminal controls the second data to be written into the block memory bit-wisely; wherein the ECC module includes an ECC encoder and an ECC decoder, when the first data is written into the first data input terminal, the ECC encoder generates a check bit for the first data, which check bit is written into the block register via a first parity data input terminal of the first port, wherein when reading the first data, the ECC decoder gets the first data and the check bit from the block memory, and generates a single bit error and a double bit error; and wherein the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock of the block memory synchronous or asynchronous with and the write clock of the block memory.