Patent ID: 9652579
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A computer implemented method for implementing DRC (design rule check) clean parallel fills in electronic designs, comprising: identifying, at a design traversal module including or coupled with at least one micro-processor of a computing system, a first shape and one or more neighboring shapes of the first shape by searching design data of a region of a layout of an electronic design; classifying the first shape and the one or more neighboring shapes by examining respective characteristics of the first shape and the one or more neighboring shapes to categorize the first shape and the one or more neighboring shapes into one or more classes of a plurality of classes based in part or in whole upon one or more criteria; implementing one or more parallel fill shapes for at least one shape of the first shape and the one or more neighboring shapes by aggregating the one or more parallel fill shapes to the at least one shape based in part or in whole upon the one or more classes while satisfying one or more design rules, wherein a parallel fill shape of the one or more parallel fill shapes is implemented on the at least one shape along a direction parallel to one edge of the at least one shape; and performing one or more post-layout operations on the layout including the one or more parallel fill shapes by preparing the layout for manufacturing.