Patent ID: 9721849
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method of forming an integrated circuit, comprising the steps of: providing a substrate comprising a p-type semiconductor material, said substrate including an area for an NMOS transistor, an area for a PMOS transistor, an area for an isolated n-channel DEMOS transistor, and an area for an isolated vertical PNP transistor; concurrently forming a first shallow n-type well surrounding said isolated n-channel DEMOS transistor, a second shallow n-type well surrounding said isolated vertical PNP transistor, and third shallow n-type well providing a body region for said PMOS transistor of said integrated circuit; concurrently forming a first deep n-type well underlying said isolated n-channel DEMOS transistor and a second deep n-type well underlying said isolated vertical PNP transistor, so that said first shallow n-type well connects with said first deep n-type well so as to isolate said isolated n-channel DEMOS transistor from said p-type semiconductor material of said substrate, and said second shallow n-type well connects with said second deep n-type well so as to isolate said isolated vertical PNP transistor from said p-type semiconductor material of said substrate; concurrently forming a first upper n-type layer providing an extended drain of said isolated n-channel DEMOS transistor and a second upper n-type layer providing a base of said isolated vertical PNP transistor; and concurrently forming a first lower p-type layer below said first upper n-type layer and a second lower p-type layer below said second upper n-type layer, said second lower p-type layer providing a collector of said isolated vertical PNP transistor.