Patent ID: 9589964
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: sequentially forming an etch-target layer and a middle mold layer on a substrate; forming a first upper mold pattern on the middle mold layer that has a top surface that is a first height above a bottom surface of the substrate; forming a second upper mold pattern on the middle mold layer that has a top surface at a second height above the bottom surface of the substrate that is different from the first height; etching the middle mold layer using the first and second upper mold patterns as an etch mask to form respective first and second middle mold patterns; forming a third middle mold pattern between the first and second middle mold patterns; and etching the etch-target layer using the first to third middle mold patterns as an etch mask to form conductive patterns.