Patent ID: 9633857
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method, comprising: providing a semiconductor structure comprising a trench isolation structure, said trench isolation structure comprising a first electrically insulating material; forming a trench capping layer over said trench isolation structure, said trench capping layer comprising a second electrically insulating material that is different from said first electrically insulating material; forming a gate stack over said semiconductor structure, said gate stack comprising a layer of a high-k material and a layer of a gate electrode material; patterning said gate stack, wherein a gate structure having a first portion over a first portion of said trench capping layer is formed, said patterning of said gate stack exposing a second portion of said trench capping layer adjacent said gate structure; and forming a sidewall spacer adjacent said gate structure, a portion of said sidewall spacer being formed on said exposed second portion of said trench capping layer.