Patent ID: 9734751
Date: 2017-08-15
CPC Classifications: G09G,H03K

Claim:
1. An inverter, comprising: a first transistor, wherein a gate electrode of the first transistor is electrically connected with an initial signal input terminal for receiving an initial signal, and a source electrode of the first transistor is electrically connected with a second clock signal input terminal for receiving a second clock signal; a second transistor, wherein a drain electrode of the second transistor is electrically connected, via a first capacitor, with a first clock signal input terminal for receiving a first clock signal; a third transistor, wherein a gate electrode of the third transistor is electrically connected with the second clock signal input terminal for receiving the second clock signal, a source electrode of the third transistor is electrically connected with the drain electrode of the second transistor, and a drain electrode of the third transistor is electrically connected with a second electrical level signal input terminal for receiving a second electrical level signal; a fourth transistor, wherein a gate electrode of the fourth transistor is electrically connected with the initial signal input terminal, a source electrode of the fourth transistor is electrically connected with a first electrical level signal input terminal, and a drain electrode of the fourth transistor is electrically connected with an output terminal for outputting an output signal; a fifth transistor, wherein a source electrode of the fifth transistor is electrically connected with the output terminal, and a drain electrode of the fifth transistor is electrically connected with the second electrical level signal input terminal; a sixth transistor, wherein a gate electrode of the sixth transistor is electrically connected with the first clock signal input terminal for receiving the first clock signal, a drain electrode of the sixth transistor is electrically connected with a gate electrode of the fifth transistor and is electrically connected with the output terminal via a second capacitor, and a source electrode of the sixth transistor is electrically connected with a drain electrode of the first transistor; wherein a gate electrode of the second transistor is controlled in such a way to prevent reverse conduction of the second transistor, the second capacitor is configured to maintain an electrical potential at the gate electrode of the fifth transistor, and the initial signal and the output signal are inverse to each other.