Patent ID: 9535851
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. A transactional memory, comprising: a memory; and interface and decoding circuit that receives a command onto the transactional memory via a bus, wherein the command includes an incoming address and a “Do Address Translation” (DAT) bit, wherein if the command is a command to access the memory and the DAT bit is set then the interface and decoding circuit performs address translation on the incoming address by deleting certain bits and shifting other bits of the incoming address thereby generating a translated address so that the transactional memory uses the translated address to access the memory, whereas if the DAT bit is not set then the interface and decoding circuit does not perform address translation but rather the transactional memory uses the incoming address to access the memory, and wherein the transactional memory is not a processor that fetches instructions.