Patent ID: 9640244
Date: 2017-05-02
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A method comprising: performing a plurality of calibrations of a memory subsystem at each of a plurality of operating points, wherein each of the plurality of calibrations includes calibrating a delay of a data strobe signal conveyed from a memory controller to a memory in the memory subsystem, and further includes calibrating a reference voltage used to distinguish between a logic one and a logic zero; saving calibration state data for each of the plurality of calibrations, wherein each calibration state includes the delay of the data strobe signal and the reference voltage for the corresponding one of the plurality of operating points; responsive to changing to a given one of the plurality of operating points, setting the delay of the data strobe signal and the reference voltage to respective values of the calibration state corresponding to the given one of the plurality of operating points; and performing a next calibration subsequent to changing to the given one of the plurality of operating points, wherein the next calibration comprises calibrating a subset of the plurality of parameters for which calibration was performed during each of the plurality of calibrations.