Patent ID: 9704973
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method, comprising: forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in said substrate, said plurality of first trenches exposing sidewalls of said plurality of initial fins; after defining said plurality of initial fins, completely filling each of said plurality of first trenches with a masking material, said masking material completely covering said exposed sidewalls of said plurality of initial fins; removing at least one, but less than all, of said plurality of initial fins while said masking material is present in said plurality of first trenches; after removing said at least one of said plurality of initial fins, forming a fin protection layer on at least said sidewalls of the remaining initial fins; with said fin protection layer in position, performing an etching process to extend a depth of said first trenches to thereby define a plurality of final trenches with a final trench depth, wherein said final trenches define a plurality of final fin structures that each comprise an initial fin; removing said fin protection layer; and forming a recessed layer of insulating material in said final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of said final fin structures.