Patent ID: 9535860
Date: 2017-01-03
CPC Classifications: G06F,Y02D

Claim:
1. An apparatus comprising: a fabric coupled between a plurality of intellectual property (IP) blocks of a semiconductor device and a memory controller, the fabric configured to provide global timing information to at least some of the plurality of IP blocks and receive a plurality of memory requests from the plurality of IP blocks, wherein the fabric is configured to receive a memory request of the plurality of memory requests from a first IP block of the plurality of IP blocks, the memory request having a plurality of fields including a deadline field to provide a deadline value based at least in part on the global timing information, the deadline value communicated by the first IP block to indicate a maximum latency before completion of the memory request, the maximum latency determined by the first IP block and wherein the fabric is configured to arbitrate between the plurality of memory requests based at least in part on the deadline value included in the deadline field of the memory request.