Patent ID: 9704780
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method of making a semiconductor device, comprising: providing a carrier; disposing a semiconductor die on the carrier; disposing a modular interconnect unit on the carrier with a first side surface of the modular interconnect unit adjacent to a first side surface of the semiconductor die and a second side surface of the modular interconnect unit adjacent to a second side surface of the semiconductor die, wherein the modular interconnect unit includes a plurality of conductive vias oriented in an L-shape; depositing an encapsulant extending from the first side surface of the modular interconnect unit to the first side surface of the semiconductor die and from the second side surface of the modular interconnect unit to the second side surface of the semiconductor die; forming a first insulating layer over the encapsulant, semiconductor die, and modular interconnect unit; forming a plurality of openings through the first insulating layer and encapsulant to expose the conductive vias of the modular interconnect units; providing a semiconductor component; forming a plurality of contact pads on the semiconductor component oriented in an L-shape; forming a second insulating layer over the semiconductor component around the contact pads; and disposing the semiconductor component over the semiconductor die and modular interconnect unit with the first insulating layer directly contacting the second insulating layer and including a plurality of conductive bumps extending through the openings in the encapsulant and first insulating layer from the contact pads of the semiconductor component to the conductive vias of the modular interconnect unit, wherein the semiconductor component includes a first side surface completely outside a footprint of the semiconductor die adjacent to the first side surface of the semiconductor die, a second side surface of the semiconductor component completely outside the footprint of the semiconductor die adjacent to the second side surface of the semiconductor die, and a third side surface of the semiconductor component extending directly over the footprint of the semiconductor die.