Patent ID: 9679803
Date: 2017-06-13
CPC Classifications: G03F,H01L

Claim:
1. A method for forming an integrated circuit (IC) structure, comprising: providing a semiconductor structure including a substrate, a dielectric layer formed over the substrate, and a hard mask region formed over the dielectric layer; forming a first photoresist layer over the hard mask region; performing a first lithography exposure using a photomask to form a first resist pattern in the first photoresist layer, wherein the photomask includes a first mask feature and a second mask feature, and the first resist pattern is formed from the first mask feature; transferring the first resist pattern to the hard mask region, thereby forming a first trench; forming a second photoresist layer over the hard mask region; and performing a second lithography exposure using the photomask to form a second resist pattern, wherein the second resist pattern is formed from both the first mask feature and the second mask feature and overlaps the first trench from a top view.