Patent ID: 9685948
Date: 2017-06-20
CPC Classifications: G09G,H03K

Claim:
1. A display device comprising: a display unit including a plurality of gate lines and a gate driver, wherein the gate driver includes a plurality of stages configured to output a gate signal to a corresponding gate line from among the plurality of gate lines, wherein the gate driver further includes: a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including a terminal connected to the first node and another terminal connected to an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied; a fifth transistor, wherein an input terminal and a control terminal of the fifth transistor are connected and applied with an output signal of a previous stage or a scan start signal, and wherein an output terminal of the fifth transistor is connected to the first node; a sixth transistor including an input terminal connected to the first node, a control terminal connected to the second node, and an output terminal to which the low voltage is applied; and a seventh transistor including an input terminal and a control terminal to which the clock signal is applied, and an output terminal connected to the second node, wherein a voltage at the first node increases from the low voltage to a high voltage while the first capacitor is charged, according to an output signal of a previous stage, wherein the voltage at the first node is boosted up from the high voltage to a boosted up voltage by the first capacitor according to an output signal of a current stage, and a voltage of the second node is changed to the low voltage according to the boosted up voltage that is applied to the control terminal of the third transistor, wherein the fourth transistor is switched according to an output signal of a next stage, and the voltage at the first node is decreased from the boosted up voltage to the low voltage through the fourth transistor, wherein the first capacitor is precharged by the output signal of the previous stage or the scan start signal at a first time, and wherein the first capacitor is boosted up by a high level of the clock signal at a second time that is subsequent to the first time.