Patent ID: 9640255
Date: 2017-05-02
CPC Classifications: G11C

Claim:
1. A semiconductor device comprising: a memory element comprising: wherein the first data holding portion is electrically connected to a first bit line through a first transistor, wherein the second data holding portion is electrically connected to a first inverted bit line through a second transistor, wherein a first word line is electrically connected to each of a gate of the first transistor and a gate of the second transistor, wherein the third data holding portion is electrically connected to the second data holding portion through a third transistor, wherein the fourth data holding portion is electrically connected to the first data holding portion through a fourth transistor, wherein a second word line is electrically connected to each of a gate of the third transistor and a gate of the fourth transistor, wherein the third data holding portion is electrically connected to one electrode of a first capacitor, wherein the fourth data holding portion is electrically connected to one electrode of a second capacitor, wherein the other electrode of the first capacitor is electrically connected to a first power supply line, wherein the other electrode of the second capacitor is electrically connected to the first power supply line, wherein the third transistor and the fourth transistor are configured to be turned off when data is written to the first data holding portion, wherein the third transistor and the fourth transistor are configured to be turned on just after the data is written to the first data holding portion, and wherein each of the third transistor and the fourth transistor comprises an oxide semiconductor layer comprising a channel formation region comprising indium.