Patent ID: 9614028
Date: 2017-04-04
CPC Classifications: H01L,H03K

Claim:
1. A semiconductor device comprising: first and second charge-carrier emission structures on first and second opposed faces of a semiconductor die; first and second semiconductor control regions which are located on said first and second faces respectively, and are each positioned to control emission of first-polarity charge-carriers from said first and said second emission structures respectively; a first field-limiting ring structure, on said first face, which laterally surrounds said first emission structure; a second field-limiting ring structure, on said second face, which laterally surrounds said second emission structure; wherein said first emission structure and said first control region collectively include at least three doping components, including shallow p-type and n-type components, which each have the same spatial profile as, and are electrically equivalent to, a corresponding respective doping component of said second field-limiting ring structure, and also includes at least one other doping component which does not have the same profile as any component of said second field-limiting ring structure; and wherein said second emission structure and said second control region collectively include at least three doping components, including shallow p-type and n-type components, which each have the same spatial profile as, and are electrically equivalent to, a corresponding respective doping component of said first field-limiting ring structure, and also includes at least one other doping component which does not have the same profile as any component of said first field-limiting ring structure; whereby said field-limiting ring structures, in combination, smooth lateral voltage profiles between said emission structures and an edge of the die; wherein the shallow p-type and n-type components of the field-limiting ring structures are electrically connected through a local metallization portion which is not connected to said emission structures nor said control regions, and wherein said local metallization is capacitively coupled to some, but not all, of the portion of the semiconductor die which laterally separates adjacent ones of said field-limiting ring structures.