Patent ID: 9716153
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A charge trap memory device, comprising: a layer of semiconducting material on an insulating layer on a surface of a substrate; a source region, a drain region, and a channel region electrically connecting the source region and drain region formed in the layer of semiconducting material, wherein the insulating layer separates the channel from the substrate; a tunnel dielectric layer disposed above the substrate over the channel region; and a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed above the first nitride layer, and a second deuterated layer disposed above the second nitride layer, wherein the second nitride layer comprises a, deuterium-free trap-dense, oxygen-lean nitride layer and includes a majority of charge traps distributed in the multi-layer charge-trapping region, and the first nitride layer comprises a substantially trap-free oxygen-rich nitride layer.