Patent ID: 9666516
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. An electronic package, comprising: a dielectric layer; a conformal masking layer disposed on at least a portion of the dielectric layer, wherein the conformal masking layer comprises an electrically conductive material; a routing layer disposed on at least a portion of the conformal masking layer, wherein the routing layer comprises a plurality of electrical traces; a micro-via disposed at least in part in the conformal masking layer, the dielectric layer, and the routing layer, wherein at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via, and wherein the conformal masking layer is configured to define a size of the micro-via; a semiconductor die coupled to the micro-via, wherein at least a portion of the conformal masking layer is disposed between the micro-via and a contact pad of the semiconductor die, wherein the routing layer provides an electrical connection between the micro-via and the conformal masking layer, and wherein the conformal masking layer and the routing layer together form a routing interconnect for the electronic package; and other vias electrically coupled to the micro-via using one or more of the plurality of electrical traces of the routing layer.