Patent ID: 9666593
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a stack comprising alternating word line layers and dielectric layers; a memory hole extending vertically in the stack; a channel material extending in the memory hole; an oxide extending in the memory hole around the channel material; and a charge-trapping layer extending in the memory hole around the oxide, the charge-trapping layer is continuous and extends across multiple memory cells and comprises portions which are adjacent to the word line layers and portions which are adjacent to the dielectric layers, the portions of the charge-trapping layer which are adjacent to the word line layers comprise silicon-rich silicon oxynitride and the portions of the charge-trapping layer which are adjacent to the dielectric layers comprise oxygen-rich silicon oxynitride, wherein in the silicon-rich silicon oxynitride, an atomic percentage of silicon exceeds an atomic percentage of oxygen and an atomic percentage of nitrogen and in the oxygen-rich silicon oxynitride, an atomic percentage of oxygen exceeds an atomic percentage of silicon and an atomic percentage of nitrogen.