Patent ID: 9632954
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A memory controller for managing access to one or more memory devices, comprising: a bus interface for receiving memory access operations from a bus; a memory access queue for queuing multiple ones of the memory access operations in an order of their receipt; a re-order queue for queuing other multiple ones of the memory access operations, and from which the memory access operations are performed out-of-order; a memory device interface for issuing accesses to the one or more memory devices in response to the memory access operations; and a control logic for controlling the bus interface, the memory access queue, the memory device interface and the re-order queue such that an address specified by a given memory access operation in the memory access queue is compared to determine whether a high latency maintenance operation is being performed in a region of the one or more memory devices that includes the address, and responsive to determining that no high latency maintenance operation is being performed in the region of memory that includes the address, the control logic transfers the memory access operation to the re-order queue, and responsive to determining that a high latency maintenance operation is being performed in the region of memory that includes the address, rejects the transferring of the memory access operation to the re-order queue, whereby transfer of the memory access operation will be retried at a subsequent time.