Patent ID: 9542315
Date: 2017-01-10
CPC Classifications: G06F

Claim:
1. A storage circuit, including: multiple storage tiles corresponding to a single level of storage access that provides for arbitrary access to any one of the multiple storage tiles, wherein values stored within the storage circuit are associated with unique corresponding ones of the multiple storage tiles, and wherein a particular one of the multiple storage tiles is a front-most tile having an interface connection at which responses to read access requests directed at any of the multiple storage tiles are provided to a requesting device from a storage within the front-most tile; and control logic for accessing the values within the multiple storage tiles, wherein the control logic moves the values among the multiple storage tiles according to a placement heuristic in response to an access to one of the multiple storage tiles while maintaining the uniqueness of the values within the multiple storage tiles to move a requested value to the front-most tile, and wherein the control logic further moves the values among the multiple storage tiles according to a global clock, whereby multiple move-to-front operations are simultaneously maintained in-progress among the multiple storage tiles.