Patent ID: 9548351
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A structure comprising: at least one SOI (semiconductor-on-insulator) transistor situated in a silicon layer over a buried oxide layer, said buried oxide layer having a thickness greater than a thickness of the silicon layer and overlying a bulk substrate, the at least one SOI transistor having a source and a drain in contact with the buried oxide layer; and a field control ring formed in the silicon layer, above said buried oxide layer and surrounding said at least one SOI transistor, said field control ring coupled to a bias voltage of non-zero voltage to provide a charge to the field control ring to generate an electrical field that creates a resistive surface portion on said bulk substrate underlying said field control ring, wherein a width of said field control ring is greater than said thickness of said buried oxide layer by a factor of between 3.0 and about 10.0.