Patent ID: 9646901
Date: 2017-05-09
CPC Classifications: G01R,H01L,H05K

Claim:
1. A semiconductor device, comprising: a semiconductor chip including a main surface, and a pad formed over the main surface; a first insulating layer formed over the main surface of the semiconductor chip; a wiring formed over the first insulating layer; and a bump electrode formed on a part of the wiring, wherein the pad is located closer than the bump electrode to a peripheral portion of the semiconductor chip, wherein a probe mark is formed in a first area of a surface of the pad, wherein the first insulating layer has an opening, wherein a second area of the surface of the pad is exposed from the opening of the first insulating layer, wherein the first area is located closer than the second area to a central portion of the semiconductor chip, wherein the wiring is connected with the pad in the second area but not in the first area, and wherein the wiring is led from the second area to the central portion of the semiconductor chip such that the wiring does not overlap with the probe mark in a plan view.