Patent ID: 9691776
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A nonvolatile memory device comprising: a well formed in a substrate; an isolation layer formed in the substrate and defining an active region and a well tap of the well, the active region and the well tap being separated from each other and having a bar shape with a major-axis direction of the well tap and a major-axis direction of the active region crossing each other: a control plug formed over the isolation layer to overlap the isolation layer; a floating gate formed over the substrate and comprising a plurality of fingers adjacent to the control plug with a gap provided therebetween, wherein the plurality of fingers are formed over the isolation layer to overlap the isolation layer; and a charge blocking layer formed on sidewalls of the floating gate so as to fill the gap, wherein the control plug comprises: a first control plug formed between the plurality of fingers and having sidewalls facing inner walls of the fingers; and plurality of separated second control plugs formed outside the floating gate and having sidewalls facing outer walls of the fingers, and wherein the control plug and the fingers are positioned between the active region and the well tap; wherein a part of the floating gate is extended over the active region from the plurality of fingers over the isolation layer having the same major-axis direction of the well tap and a select gate formed over the active region having the same major-axis direction of the well tap.