Patent ID: 9558836
Date: 2017-01-31
CPC Classifications: G11C

Claim:
1. A sense amplifier for a memory circuit, comprising: a latch circuit, including a first latch node in which a value latched therein is held; an intermediate circuit, including a first node selectively connected to one or more bit lines and a second node connected to the latch circuit; bit line selection circuitry connected to the first node, whereby the first node is selectively connected to one or more bit lines; a first switch connected to the latch circuit and the second node, whereby the first latch node is connected to the second node when the first switch is on and isolate the latch circuit from the second node when the first switch is off; a second switch, whereby the latch circuit is connected to a data bus; a third switch whereby the second node is connected to a second latch node of the latch circuit that holds the inverse of said value held in the latch circuit; and a fourth switch whereby the second node is directly connected to ground.