Patent ID: 9613816
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device, the method comprising: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate; measuring a width of the gate to obtain a measured width of the gate; depositing a dielectric layer covering the gate; measuring a thickness of the dielectric layer to obtain a measured thickness of the dielectric layer; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer, wherein determining the trim time of the dielectric layer is conducted by calculating the model: (the measured thickness of the dielectric layer-the target width of the spacer)+n(the measured width of the gate-the target width of the gate)=(a trim rate of the dielectric layer)×(the determined trim time)+b, wherein n is less than 1, and b represents a control offset value.