Patent ID: 9678593
Date: 2017-06-13
CPC Classifications: G06F

Claim:
1. A gate on array (GOAL circuit applied to a liquid crystal display device, the liquid display device comprising a plurality of scanning lines, the GOA circuit comprising (M) cascaded GOA units, wherein an (N)th level GOA unit is controlled to charge an (N)th level scanning line accordingly, and the GOA circuit is used to process a first screen scanning procedure and a second screen scanning procedure to detect a touch signal, M being greater than (N+1), the (N)th level GOA unit comprising: a signal transfer circuit, used to receive a rearward scanning signal and a forward scanning signal, and connected with an (N−1)st gate signal point and an (N+1)st gate signal point; an inverting amplifier circuit, connected with the signal transfer circuit and an (N)th gate signal point, and used to receive a first clock signal; a signal reset circuit, connected with the inverting amplifier circuit and a constant high voltage, and used to receive a reset signal; and an inverting logistic circuit, connected with the signal reset circuit, the inverting amplifier circuit, the (N)th gate signal point, and the (N)th level scanning line, wherein, when the first screen scanning procedure is processed, the GOA circuit scans from the 1st level GOA unit to the (X)th level GOA unit, when the GOA circuit receives the touch signal, a touch point scanning procedure is entered, and when the forward scanning signal is changed from a low potential to a high potential and the rearward scanning signal is changed from a high potential to a low potential, the second screen scanning procedure is entered, M, N and X being positive integers, and wherein the inverting amplifier circuit comprises: a first inverting amplifier, comprising a first input terminal connected with the output terminal of the second transmission gate; a first inverter, comprising an output terminal connected with a second input terminal of the first inverting amplifier, and an input terminal receiving the first clock signal; and a second inverting amplifier, comprising an output terminal connected with an output terminal of the first inverting amplifier, a first input terminal connected with the output terminal of the second transmission gate, a second input terminal receiving the first clock signal, and a third input terminal connected with a third input terminal of the first inverting amplifier and the (N)th gate signal point.