Patent ID: 9646930
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor chip, comprising: a substrate having at least one front-end-of-line (FEOL) device; a back-end-of-line (BEOL) comprising a metal pad; at least one first contact plug contacting the at least one FEOL device; at least one second contact plug underneath the metal pad and in electrical contact therewith, wherein the at least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device; and a through substrate via (TSV) formed through the substrate and in electrical contact with the at least one second contact plug at a location laterally between adjacent ones of shallow trench isolation (STI) regions formed at a front side of the substrate, wherein the TSV vertically extends through the STI regions and is filled with a conductive material that is different from the at least one second contact plug.