Patent ID: 9585621
Date: 2017-03-07
CPC Classifications: A61B

Claim:
1. A technique for real-time removal of power line interference (PLI) in electrocardiographic (ECG) devices with sampling rate sf set equal to an integer multiple of the nominal power line frequency (NPLF, given by pf=60 or 50 Hz) in a range from 240 Hz to 6*pf Hz, the technique comprising the following steps performed in each of said ECG devices after every sampling: (a) storing into a part of the ECG device memory a current sample obtained by analog-to-digital conversion of the treated ECG signal as x(1) in a First-In-First-Out (FIFO) buffer of 16-bit integers x(j), where j=1, . . . ,nx, nx=2*k−1+sf/5 and k=sf/pf is 4, 5 or 6, computing a 32-bit difference d(.)=x(1)−x(1+k) of phased with the NPLF ECG samples x(1) and x(1+k) for said k=4, 5 or 6 in said FIFO buffer x(j) and storing said d(.) as d(1) in a FIFO buffer of 32-bit integers d(j) with j=1 , . . . ,4; (b) filtering ECG samples x(1), . . . ,x(4*k−3) with said k=4, 5 or 6 in said FIFO buffer x(j) by a series of two identical band-pass PLI filters that are based on double moving average and have scaled-up to obviate fractional numbers impulse responses [−1, −2, . . . , −(k−1), k (c) determining a 64-bit integer error e(.)=(3*d(1)−4*d(2)−d(3)+2*d(4)) (d) determining a maximum mf of smoothed errors f(ff), . . . ,f(nj) in said FIFO buffer f(j), computing a ranged from 1 to 1000 integer weight w(.)=(mf+1000*da)/(mf+da), where da is parameter that for said ECG devices with analog-to-digital converters of 11- or 12-bit resolution over a 10 mV range is experimentally adjusted to da=3000, and storing said w(.) and its 64-bit integer product v(.) with a current output value of said band-pass PLI filters as w( (e) estimating PLI by weighted LS parabolic approximating that uses a pair of current sub-series [w(