Patent ID: 9748349
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate; a gate structure on the substrate, wherein a bottom surface of the gate structure is even with a top surface of the substrate; a source/drain region adjacent to two sides of the gate structure; an interlayer dielectric (ILD) layer around the gate structure; a first dielectric layer on top of the ILD layer; a first contact plug in the ILD layer and contacting the first dielectric layer and the source/drain region directly; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and contacting the first contact plug and the gate structure directly, wherein the second contact plug is disposed on top of the gate structure and the source/drain region; and a spacer on the first dielectric layer and between the second contact plug and the second dielectric layer; wherein a bottom surface of the first dielectric layer contacts a top surface of the ILD layer and a top surface of the gate structure directly.