Patent ID: 9691695
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A three-dimensional Integrated Circuit (3D-IC), comprising: a first tier device that includes: a first substrate and a first interconnect structure formed over the first substrate; a second tier device coupled to the first tier device, wherein the second tier device includes: a second substrate, a doped region formed in the second substrate, a dummy gate formed over the second substrate, and a second interconnect structure formed over the second substrate, wherein the dummy gate is electrically floating, and wherein the dummy gate is located between two neighboring circuits of the second tier device but is not a part of either of the two circuits; and an inter-tier via extending through the second substrate; wherein: the inter-tier via has a first end and a second end opposite the first end; the first end of the inter-tier via is coupled to the first interconnect structure; and the second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.