Patent ID: 9697125
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. At a data processing device comprising a plurality of processor cores, a shared cache, and a memory including a plurality of memory banks and a plurality of row buffers, each of the plurality of row buffers associated with a corresponding one of the plurality of memory banks, a method comprising: replacing cache lines at the shared cache, such that a subset of the cache lines associated with threads having a spatial locality higher than a first threshold, wherein the spatial locality is a predicted likelihood that an access request for a thread, if the thread were the only thread executing at a data processing device, would result in a row buffer hit, if the access request were provided to memory, are assigned a higher replacement priority than a subset of the cache lines associated with threads having a temporal locality higher than a second threshold, wherein the temporal locality is a predicted likelihood that an access request for a thread, if the thread were the only thread executing at the data processing device, would result in a cache hit at the shared cache, if the access request were provided to memory, and wherein replacing cache lines comprises storing data at the cache lines.