Patent ID: 9606781
Date: 2017-03-28
CPC Classifications: G06F

Claim:
1. A processing network comprising: a processing circuit having a programmable parser including one or more parsing engines that parse data packets received by the processing circuit; and a parser compiler stored on a non-transitory computer-readable memory and communicatively coupled with each of the parsing engines, wherein the parser compiler is configured to generate values based on a parser configuration file that when programmed into a memory associated with each of the parsing engines enables the parsing engines to identify each of a set of different combinations of packet headers represented by the parser configuration file, wherein the memory associated with each of the parsing engines comprises ternary content-addressable memory paired with static random-access memory, and further wherein the parsing engines identify the combination of packet headers of one of the data packets based on a first portion of the values stored in the ternary content-addressable memory that indicate the combination of packet header of the one of the data packets and determine what actions to perform with the one of the data packets based on a second portion of the values stored in the static random-access memory paired with the ternary content-addressable memory that indicate the actions to perform with the one of the data packets.