Patent ID: 9548302
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A semiconductor integrated circuit comprising: a substrate having a plurality of first isolation structures and at least a second isolation structure formed therein, and a depth of the first isolation structures being smaller than a depth of the second isolation structure; a multi-gate transistor device formed on the substrate, the multi-gate transistor device further comprising: a lateral-diffusion metal-oxide-semiconductor (LDMOS) device, the LDMOS device comprising at least one second fin structure and at least a second gate electrode formed on the substrate and covering a portion of one first isolation structure, the LDMOS device being electrically isolated from the multi-gate transistor device by the second isolation structure, and a width of the second fin structure of the LDMOS device being larger than a width of the first fin structures of the multi-gate transistor device, a top surface of the first isolation structure in the LDMOS device being higher than a top surface of the second isolation structure.