Patent ID: 9741722
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor structure comprising: forming semiconductor fins on a substrate, wherein each of said semiconductor fins is laterally bound by a pair of lengthwise sidewalls and a pair of widthwise sidewalls; forming trench capacitors within said substrate, forming a gate structure straddling one of said semiconductor fins, said gate structure comprising a gate dielectric and a gate electrode contacting said gate dielectric; forming a dummy gate structure between two of said semiconductor fins including said one of said semiconductor fins and between two of said trench capacitors, wherein said dummy gate structure laterally extends along a same direction as said gate structure and includes dielectric surfaces contacting a widthwise sidewall of said one of said semiconductor fins and a widthwise sidewall of another of said semiconductor fins and contacting a sidewall of one of said trench capacitors and a sidewall of another of said trench capacitors.