Patent ID: 9667300
Date: 2017-05-30
CPC Classifications: H03L,H04B

Claim:
1. A frequency synthesizer, comprising: a reference frequency scaler configured to generate a first reference frequency and a second reference frequency; and a phase locked loop (PLL) coupled to the reference frequency scaler, the PLL configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot that alternates with the first timeslot; wherein the PLL comprises a loop filter that includes: a first switch coupled in series to a first capacitor and configured to close during the first timeslot and to open during the second timeslot, without discharging a total charge of the first capacitor during the second timeslot; a second switch coupled in series to a second capacitor and configured to open during the first timeslot and to close during the second timeslot, without discharging a total charge of the second capacitor during the first timeslot and a third capacitor coupled in parallel to the first capacitor; wherein: the first and second switches are coupled in parallel to one another; and the first and second capacitors are coupled in parallel to one another through the first and second switches respectively.