Patent ID: 9621485
Date: 2017-04-11
CPC Classifications: H04L

Claim:
1. A shared interface circuit, comprising: a shared socket, having a slot, a reference terminal, a control terminal, a signal receiving terminal and a signal outputting terminal; a multiplexer, having a first input terminal, a second input terminal and a third input terminal, wherein the first input terminal is arranged to be selectively coupled to a first-interface pin of a processor according to a control signal, the second input terminal is arranged to be selectively coupled to a second-interface transfer pin of the processor according to the control signal, and the third input terminal is arranged to be selectively coupled to a second-interface receive pin and the first-interface pin of the processor according to the control signal; a level shifter circuit, arranged to convert signals on the second input terminal of the multiplexer from a first voltage level to a second voltage level and convert signals on the signal receiving terminal of the shared socket from the second voltage level to the first voltage level, wherein the level shifter circuit is further arranged to selectively transmit the converted signals on the control terminal input terminal of the multiplexer to the signal outputting terminal of the shared socket according to the control signal, and selectively transmit the converted signals on the signal receiving terminal of the shared socket to the third input terminal of the multiplexer according to the control signal; a power supply circuit arranged to selectively couple a first power source to the signal outputting terminal according to the control signal; and a switch circuit, arranged to selectively couple the signal receiving terminal of the shared socket to the third input terminal of the multiplexer according to the control signal.