Patent ID: 9627514
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: forming an active fin structure and an isolation region on a substrate; forming a plurality of epitaxial layers on the active fin structure; forming a plurality of first metal gate electrodes on the active fin structure, wherein each of the first metal gate electrodes and each of the epitaxial layers are alternately disposed in a first direction on the active fin structure; forming a plurality of ILD patterns on the plurality of epitaxial layers, wherein each of the plurality of ILD patterns is extended in a second direction crossing the first direction; forming a plurality of sacrificial spacer patterns on the plurality of first metal gate electrodes, wherein each of the plurality of sacrificial spacer patterns covers a corresponding first metal gate electrode of the plurality of first metal gate electrodes; forming a plurality of self-aligned contact holes and a plurality of sacrificial spacers by removing the plurality of ILD patterns, wherein each of the plurality of self-aligned contact holes exposes a corresponding epitaxial layer disposed under each of the plurality of ILD patterns; forming a plurality of source/drain electrodes in the plurality of self-aligned contact holes; and replacing the plurality of sacrificial spacers with a plurality of air spacers.