Patent ID: 9559125
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. An array substrate including a substrate and data lines and scan lines arranged on the substrate, the data lines and the scan lines define a plurality of pixel regions, a thin film transistor is arranged in each of the plurality of pixel regions, the thin film transistor includes a gate electrode, a source electrode, a drain electrode, and an active region, the gate electrode is arranged above the active region, the source electrode and the drain electrode are arranged at two opposite sides of the active region respectively, a light shielding metal layer is further arranged in each of the plurality of pixel regions, wherein the light shielding metal layer and the data lines are arranged along a direction parallel to a surface of the substrate in a same layer on the substrate and are arranged with an interval therebetween on the substrate, the data lines are arranged under the active region, the light shielding metal layer is arranged under the active region and at least partially overlaps with the active region in a projection direction, the data line is close to the source electrode and does not overlap with the active region at least partially in the projection direction.