Patent ID: 9715931
Date: 2017-07-25
CPC Classifications: G11C

Claim:
1. A writing method of a resistive memory apparatus, comprising: receiving a logic data, determining a logic level of the logic data and selecting a resistive memory cell; and providing a set signal to the resistive memory cell, or providing a reset signal to the resistive memory cell in a writing period according to the logic level of the logic data, wherein the set signal comprises a first set pulse and a second set pulse having a polarity opposite to a polarity of the first set pulse, the reset signal comprises a first reset pulse and a second reset pulse having a polarity opposite to a polarity of the first reset pulse, and the first set pulse, the second set pulse, the first reset pulse, and the second reset pulse are configured to be applied to place the selected resistive memory cell in a desired state, wherein an absolute value of a pulse amplitude of the first set pulse is less than an absolute value of a pulse amplitude of the second set pulse, and an absolute value of a pulse amplitude of the first reset pulse is less than an absolute value of a pulse amplitude of the second reset pulse.