Patent ID: 9548448
Date: 2017-01-17
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device comprising: a plurality of first level contacts arranged in a square array with columns directed along a first direction and rows directed along a second direction that is substantially perpendicular to said first direction, said square array of said plurality of first level contacts having every third and fourth rows vacant along said first direction, thereby forming multiple contact regions separated by multiple vacant regions along said first direction with each of said multiple contact regions comprising a first row and a second row of said first level contacts; a first and second plurality of second level contacts formed on top of said first level contacts and electrically connected thereto, said second plurality of second level contacts having elongated shape extending into said vacant regions adjacent thereto along said first direction; and a first and second plurality of memory elements formed on top of said first and second plurality of second level contacts, respectively, wherein said first and second plurality of memory elements are arranged to have a greater center-to-center spacing between two closest neighbors than said first level contacts.