Patent ID: 9652315
Date: 2017-05-16
CPC Classifications: G06F,G11C

Claim:
1. A processor system comprising: a multi-core processing resource (MCPR) including one or more processors, the one or more processors including a first processor partition and at least one second processor partition, the first processor partition including a first health monitor configured to run on the first processor partition, the at least one second processor partition including at least one second health monitor configured to run on the at least one second processor partition; at least one system memory coupled to the one or more processors, the at least one system memory including at least at least one system-on-a-chip (SoC) module coupled to the MCPR, the at least one SoC module including at least one error register; the at least one hypervisor of the MCPR coupled to the one or more processors and configured to define the first portion, the at least one second portion, and the at least one third portion; and at least one error detector coupled to the at least one system memory and to the SoC module, the first health monitor configured to pass at least one of a first memory address, a second memory address, and a third memory address to the at least one error detector; the at least one error detector configured to