Patent ID: 9673225
Date: 2017-06-06
CPC Classifications: G02F,G09G,H01L

Claim:
1. An array substrate comprising a driver IC and pixel units, each port of the driver IC being connected to a plurality of pixel units through a connecting structure, each connecting structure comprising a connecting line connected between a port of the driver IC and a plurality of pixel units, and at least some of the connecting structures also comprise resistance regulating units for changing total resistance values of the connecting structures, wherein, one end of the connecting line is directly connected to a port of the driver IC and the other end of the connecting line is connected to one of the plurality of pixel units, and wherein the resistance regulating units are connected in parallel with parts of the respective connecting lines, wherein the resistance regulating units are resistance lines, the connecting lines and the resistance lines are located in two directly adjacent layers, and the connecting lines and the resistance lines are connected with each other by way of an interfacial physical contact,