Patent ID: 9571045
Date: 2017-02-14
CPC Classifications: G01S,G06F,H03F,H03G

Claim:
1. A circuit for implementing an enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifiers (TIAs) comprising: a transimpedance amplifier (TIA) including a photo-detector, and the TIA being formed by a first TIA inverter and a second TIA inverter; said first TIA inverter having an input from a cathode side of said photo-detector and said second TIA inverter with an input from an anode side of said photo-detector; a replica TIA being formed by two replica inverters, a respective output of said respective replica inverters coupled to a respective input to of a first operational amplifier and a second operational amplifier; and said first operational amplifier and said second operational amplifier in a feedback configuration for respectively biasing a set voltage level at said cathode side photo-detector input to said first TIA inverter and at said anode side photo-detector input of said second TIA inverter.