Patent ID: 9666243
Date: 2017-05-30
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a cross-point memory array comprising a plurality of row lines, a plurality of column lines and a plurality of memory cells arranged in rows and columns, each memory cell comprising a non-volatile programmable resistive element coupled between a corresponding one of the row lines and a corresponding one of the column lines; a current supply circuit adapted to supply a programming current to a selected one of the row lines during a programming operation to change the resistive state of a selected memory cell coupled between the selected row line and a selected one of the column lines; a leakage current detection circuit coupled to the plurality of column lines except the selected column line and adapted to detect leakage currents during said programming operation; and a current limit generation circuit adapted to generate a current limit based on the sum of the leakage currents and on a reference current, and to supply said current limit to the current supply circuit to limit said programming current.