Patent ID: 9646970
Date: 2017-05-09
CPC Classifications: H01L,Y10S

Claim:
1. A semiconductor structure, comprising: a semiconductor substrate comprising an N well region having a first semiconductor fin and a second semiconductor fin protruding therefrom, the first semiconductor fin spaced apart from the second semiconductor fin; a trench isolation layer disposed on the semiconductor substrate between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer; a gate dielectric layer disposed on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins; a p type metal gate layer disposed over the gate dielectric layer over the first semiconductor fin, over the second semiconductor fin and over the trench isolation layer, wherein the p type metal gate layer is continuous between the first and second semiconductor fins; and an n type metal gate layer disposed over the p type metal gate layer over the first semiconductor fin, over the second semiconductor fin and over the trench isolation layer, wherein the n type metal gate layer is continuous between the first and second semiconductor fins.