Patent ID: 9659654
Date: 2017-05-23
CPC Classifications: G11C,H01L

Claim:
1. A method to prevent loss of data of a transistor-based memory unit, which comprises a bulk, a source (S) and a drain (D) formed on said bulk, a channel in communication between said source (S) and said drain (D), and a first tunnel oxide (TO), a floating gate (FG), a second tunnel oxide (TO) and a control gate (CG) stacked up on said channel in a proper order in such a manner that said first tunnel oxide (TO) is formed between said bulk and one side of said floating gate (FG) and said second tunnel oxide (TO) is formed between an opposite side of said floating gate (FG) and said control gate (CG), the method to prevent loss of data in said memory unit comprising the steps of: (i) erasing said floating gate (FG); (ii) using a weak electric field lower than normal writing to inject a small amount of electrons into said floating gate (FG); (iii) enabling the said small amount of electrons to remain in said floating gate (FG) so as to keep said channel between said source (S) and said drain (D) of said transistor electrically conducted; (iv) enabling the said small amount of electrons in said floating gate (FG) to repel against electrons in said first tunnel oxide (TO) and said second tunnel oxide (TO) so as to avoid electron accumulation in said first tunnel oxide (TO) and said second tunnel oxide (TO) and to allow normal data access to said floating gate (FG); (v) using an electric field of a normal write to inject electrons in said floating gate (FG) to prevent channel conduction between said source (S) and said drain (D) of said transistor and to allow writing data into said floating gate (FG).