Patent ID: 9537505
Date: 2017-01-03
CPC Classifications: H03K,H03M,H04L

Claim:
1. A data processing apparatus, comprising: an inputting circuit that receives a serial data formed of a sequence of serial data blocks of N bits (N is a natural number greater than 2) and including a clock bit; a first retrieving circuit that retrieves and obtains a data of K bits (K is a natural number greater than N, K>N) from each of the serial data blocks as a first retrieved data; a second retrieving circuit that retrieves and obtains a data of L bits (L is a difference between N and K, L=K−N) from each of the serial data blocks as a second retrieved data; a clock determining circuit that determines whether the clock bit is included in one of the first retrieved data and the second retrieved data; a first serial parallel converting circuit that performs parallel conversion to one of the first retrieved data and the second retrieved data that includes the clock bit according to a determination result of the clock determining portion so that the first serial parallel converting circuit obtains a first parallel data; a second serial parallel converting circuit that performs parallel conversion to the other one of the first retrieved data and the second retrieved data that does not include the clock bit according to the determination result of the clock determining portion so that the second serial parallel converting circuit obtains a second parallel data; and a combining circuit that combines the first parallel data and the second parallel data to output a parallel data of N bits.