Patent ID: 9666265
Date: 2017-05-30
CPC Classifications: G11C,H03K,H03L

Claim:
1. A semiconductor device comprising: a pulse generation circuit that generates a pulse train; a first variable delay circuit; a selector that is provided in a previous stage of the first variable delay circuit and outputs one of a pulse outputted from the pulse generation circuit and an output pulse from the first variable delay circuit to the first variable delay circuit; and a control circuit that controls the selector and the first variable delay circuit, wherein the control circuit adjusts a delay amount of the first variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from the pulse generation circuit passes through the first variable delay circuit N times and a second pulse outputted from the pulse generation circuit, wherein the second pulse is a pulse generated at a time subsequent to the first pulse, and wherein N is a natural number not smaller than 2.