Patent ID: 9728632
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first semiconductor well region having a first conductivity type; a conductively doped buried layer located below, and continuous with, the first semiconductor well region, wherein the conductively doped buried layer has the first conductivity type; a metal via plug that extends through the first semiconductor well region and into the conductively doped buried layer; a metal liner layer located between the metal via plug and the first semiconductor well region, wherein the metal liner layer contacts the first semiconductor well region; a plurality of body regions located in the first semiconductor well region, wherein the plurality of body regions have a second conductivity type, opposite the first conductivity type; a contact region located in each of the body regions, wherein each contact region has the second conductivity type; one or more source regions located in each of the body regions, wherein each of the one or more source regions has the first conductivity type; and a polysilicon gate electrode that includes a plurality of polygonal openings.