Patent ID: 9568890
Date: 2017-02-14
CPC Classifications: H03K,H03L,H03M

Claim:
1. An all-digital delay locked loop circuit based on a time-to-digital converter, the loop circuit comprising: a phase inversion locking control circuit for determining whether or not to use a phase inversion locking algorithm by detecting a phase difference between an input clock and an output clock and outputting the input clock or an inverted input clock; and a phase synchronization unit connected to an output terminal of the phase inversion locking control circuit to receive an output signal of the phase inversion locking control circuit and a control signal and perform phase synchronization, wherein the phase synchronization unit includes a digital control delay line for receiving the input clock or the inverted input clock output from the phase inversion locking control circuit and reducing a phase error between the input clock and the output clock, wherein the digital control delay line includes: a coarse digital delay line for removing the phase error based on the time-to-digital converter by searching for a coarse lock point by comparing output of each unit and the input clock; and a fine digital delay line for removing the phase error through a binary search of comparing the input clock and the output clock.