Patent ID: 9551736
Date: 2017-01-24
CPC Classifications: G01N,G01R

Claim:
1. An electrical conductance measurement system comprising: a field effect transistor including an electrically-conducting gate that is disposed on an electrically-insulating surface of a substrate and that includes a narrowed gate region having a width corresponding to a one-dimensional inversion channel, the gate being connected to a voltage source bias providing a one-dimensional inversion channel in the substrate under the narrowed gate region, the transistor further including a source and a drain that are together in a circuit connected to measure electrical current through the inversion channel; and an electrically-conductive element disposed on the electrically-insulating surface of the substrate at a location at which the element is capacitively coupled to the transistor, with a midpoint of the element aligned with about a midpoint of the narrowed gate region, the element being connected to a first electrically-conductive contact pad and a second electrically-conductive contact pad that are together in a circuit connected to apply a changing voltage across the element, each of the first and second electrically-conductive contact pads being laterally spaced from the midpoint of the element by a distance of at least about three times a screening length of the element, with the screening length given in SI units as (K∈