Patent ID: 9548318
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method comprising: providing a polysilicon dummy gate electrode between spacers and extending over a contact area of a back-plate (BP), an active area of a transistor, and a shallow trench isolation (STI) region therebetween; providing an interlayer dielectric (ILD) surrounding the spacers and polysilicon dummy gate electrode; removing the polysilicon dummy gate electrode creating a cavity between the spacers; forming a high-k dielectric layer and a work function (WF) metal layer in the cavity; removing a section of the WF metal layer, high-k dielectric layer, and STI region exposing an upper surface of the BP; filling the cavity with a metal forming a replacement metal gate (RMG) electrode; and planarizing the metal down to an upper surface of the spacers.