Patent ID: 9633729
Date: 2017-04-25
CPC Classifications: G11C,H01L

Claim:
1. A method of operating a non-volatile memory cell, the memory cell comprising: a coupling device formed on a first well; a read device electrically connected to the coupling device; a floating gate device formed on a second well; a program device electrically connected to the floating gate device and formed on the second well; and an erase device formed on a third well; wherein the coupling device, the floating gate device and the erase device are coupled by a common floating gate, a gate of the coupling device is a first part of the common floating gate, a gate of the floating gate device is a second part of the common floating gate, a gate of the erase device is a third part of the common floating gate formed on the third well, a first terminal of the read device is electrically coupled to a first bit line, a gate of the read device is electrically coupled to a first word line, a first terminal of the program device is electrically coupled to a second bit line, a gate of the program device is electrically coupled to a second word line, a first terminal of the coupling device is coupled to the read device and a second terminal of the coupling device is electrically coupled to a source line, and a first terminal of the erase device is electrically coupled to an erase line; the method comprising: deactivating the read device and injecting electrons into the second part of the common floating gate during a program operation; deactivating the read device and ejecting electrons from the third part of the common floating gate during an erase operation; activating the read device and the coupling device and deactivating the program device during a read operation; and during a program inhibit operation: applying a voltage in a range from 0V to 25V to the first well, the source line, and the erase line; and