Patent ID: 9728642
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first strained semiconductor fin on a strained semiconductor substrate having first and second ends and a fin length therebetween, wherein the first strained semiconductor fin is strained along the fin length; a second strained semiconductor fin on the strained semiconductor substrate having first and second ends and a fin length therebetween, wherein the second strained semiconductor fin is strained along the fin length, the second strained semiconductor fin having a longitudinal axis that is substantially collinear with a longitudinal axis of the first strained semiconductor fin; a first gate stack arranged over the first strained semiconductor fin, wherein the first gate stack is operative to substantially maintain the strain in the first semiconductor fin, wherein the first gate stack includes a first layer of amorphous silicon, a second layer of amorphous silicon, and a spacer is arranged along sidewalls of the first gate stack, wherein substantially maintaining the strain in the first semiconductor fin includes providing the first amorphous silicon layer on a fin prior to cutting the fin to form the first and second strained semiconductor fins; and a second gate stack arranged over the second strained semiconductor fin, wherein the second gate stack is operative to substantially maintain the strain in the second semiconductor fin, wherein the strained semiconductor substrate defines the first and second strained semiconductor fins.