Patent ID: 9728273
Date: 2017-08-08
CPC Classifications: G11C

Claim:
1. A method for testing embedded memory in a field-programmable gate array (FPGA) device, the embedded memory having an at-speed configuration frequency, the method comprising: (a) performing a number of write operations to write sets of configuration data into the embedded memory to configure the FPGA device; (b) performing at least one read operation after each write operation to read back the previous written set of configuration data from the embedded memory as read-back data, wherein each of the write and read operations are performed at a frequency greater than the at-speed configuration frequency; (c) comparing the read-back data to the configuration data to detect an embedded memory testing error; wherein the method is performed by a memory-testing engine of the FPGA separate from the embedded memory, separate from a programmable logic fabric of the FPGA, and connected to the embedded memory by a hardwired data bus; and wherein the memory-testing engine is implemented in a configuration bitstream engine of the FPGA device.