Patent ID: 9654127
Date: 2017-05-16
CPC Classifications: H03M

Claim:
1. A method for adaptively regulating a coding mode for a successive-approximation-register analog-to-digital converter (SAR ADC), said SAR ADC comprising at least one capacitor array, a comparator, a SAR control logic circuit and a digital correction circuit, said capacitor array comprising N switching capacitors and M redundant capacitors that are connected in parallel, said SAR control logic circuit being configured to correspondingly analyze a digital bit sequence sequentially according to an output result of said comparator, and said method comprising: (a) enabling said digital correction circuit to detect the number of comparison cycles completed by said SAR control logic circuit with respect to an analog signal as a first detected value so that said digital correction circuit acquires said digital bit sequence correspondingly analyzed by said SAR control logic circuit; (b) enabling said digital correction circuit to determine whether said first detected value is equal to (N+M), and enabling said digital correction circuit to determine whether said first detected value is larger than or equal to a pre-determined threshold value if said first detected value is not equal to (N+M); and (c) enabling said digital correction circuit to regulate a coding rule so that said digital correction circuit provides a digital output code corresponding to said analog signal according to said regulated coding rule if said first detected value is larger than or equal to said pre-determined threshold value; wherein N is a positive integer larger than 1, and M is a positive integer larger than 1.