Patent ID: 9721930
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor package, comprising: a first semiconductor chip stacked on a package substrate, the first semiconductor chip including a first surface facing the package substrate and a second surface opposite to the first surface; a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a third surface facing the second surface of the first semiconductor chip and a fourth surface opposite to the third surface; and an integral adhesive structure, the integral adhesive structure substantially filling a first space between the package substrate and the first semiconductor chip and a second space between the first and second semiconductor chips, wherein the integral adhesive structure includes an extension protruding from outer sidewalls of the first and second semiconductor chips, wherein the extension has one continuously convex sidewall between a level of the first surface to a top surface of the extension, wherein the top surface of the extension is disposed at a lower level than the fourth surface, and wherein the top surface of the extension is rounded such that an upper portion of the extension adjacent to the second semiconductor chip has a width decreasing in a direction away from the package substrate.