Patent ID: 9607667
Date: 2017-03-28
CPC Classifications: G11C

Claim:
1. A memory device comprising: a plurality of channels that include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable; shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels; one or more path switch circuits that are arranged among the plurality of channels and control a connection relation of the shared global input/output lines according to a path control signal; and a path control circuit that generates the path control signal, wherein, in response to an internal operation command for instructing data transfer from one of the plurality of channels to another of the plurality of channels, the path control circuit generates the path control signal for electrically coupling the shared global input/output lines between the one of the plurality of channels and another of the plurality of channels.