Patent ID: 9704880
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method of fabricating a multi-semiconductor device layer structure, the method comprising: providing a first wafer comprising first channel material bonded to a first buried oxide layer; fabricating a first semiconductor device layer from the first channel material, the first semiconductor device layer comprising a patterned top surface and a fin structure protruding from the first buried oxide layer; fabricating a single blanket layer comprising insulator material over the patterned surface and in contact with the first buried oxide layer, wherein the single blanket layer is one layer of a single, uniform material composition; providing a second wafer comprising second channel material bonded to a second buried oxide layer; bonding the second buried oxide layer to the single blanket layer; fabricating a second semiconductor device layer from the second channel material after bonding the second buried oxide layer to the single blanket layer; and interconnecting a feature of the first semiconductor device layer with a feature of the second semiconductor device layer.