Patent ID: 9652241
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A data processing apparatus comprising a processor configured to operate under control of program code comprising instructions selected from an instruction set, wherein the instruction set comprises instructions having both short and long instruction encodings, wherein a short instruction encoding takes up less memory than a long instruction encoding and each short instruction encoding having a corresponding long instruction encoding, the apparatus further comprising: a predefined addressable memory providing a predefined memory space, which forms a sub-portion of a larger addressable memory providing a larger memory space; and a memory management unit for accessing program code and data anywhere within the larger memory space, wherein the apparatus is configured to operate in one of two operating configurations, each of the two operating configurations of the apparatus specifying an instruction encoding to be used for accessing memory within the predefined memory space and within the larger memory space: a first operating configuration (a near mode) in which the short instruction encodings are selected, in preference over their respective corresponding long instruction encodings to encode memory access instructions for performing near accesses to data within the predefined memory space; and a second operating configuration (a far mode) in which the short instruction encodings are selected, in preference over their respective corresponding long instruction encodings to encode memory access instructions for performing far accesses within the larger memory space; wherein said short instruction encodings are interpreted differently for each of the two operating configurations of said apparatus.