Patent ID: 9559051
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method for forming an electronic structure comprising the steps of: providing an electronic substrate having a dielectric layer, a conductive layer below the dielectric layer, a via opening in the dielectric layer extending through the dielectric layer to the conductive layer at a bottom thereof, and a liner layer covering side walls of the via opening and the conductive layer at the bottom of the via opening; depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom, the amorphous silicon extending substantially over the entire via opening while leaving a void within the via opening; anisotropically etching the amorphous silicon extending substantially over the via opening and on the via opening bottom and etching the liner layer on the via opening bottom, while leaving a layer of amorphous silicon over the dielectric layer and the via opening side walls; and removing the layer of amorphous silicon to form a via opening having a substantially open-bottom liner.