Patent ID: 9702933
Date: 2017-07-11
CPC Classifications: G01R,G06F

Claim:
1. A method for concurrent interconnection diagnostics in a hardware-based emulation system, comprising: (a) generating a test pattern on a pattern generator of a first emulation chip of the hardware-based emulation system, the test pattern capable of use in testing an interconnection between the first emulation chip and a second emulation chip of the hardware-based emulation system; (b) selecting the test pattern for transmission across the interconnection, wherein the test pattern is selected when the interconnection is not used for emulating at least a portion of a hardware design; (c) encoding the test pattern on a serializer/deserializer of the first emulation chip, the serializer/deserializer serializing data of the test pattern; (d) transmitting the test pattern that has been serialized across the interconnection not used for emulating at least a portion of the hardware design; (e) receiving the test pattern that has been serialized on a serializer/deserializer of the second emulation chip; deserializing the test pattern that has been serialized by the serializer/deserializer of the first emulation chip; (g) checking the test pattern to determine whether the second emulation chip received the test pattern without error thereby determining whether that has been an interconnection failure; (h) implementing at least a portion of a hardware design on either the first emulation chip or the second emulation chip while performing steps (a)-(g).