Patent ID: 9673389
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A memory device comprising: a first interconnect group in which a plurality of first interconnects is stacked, the first interconnect group including a plurality of first regions in which the first interconnects are formed along a first direction, and a second region in which a plurality of first contact plugs are formed on the first interconnects; a plurality of second interconnects formed along a second direction different from the first direction, the first interconnects being stacked along the second direction; and a memory cell including a variable-resistance-layer which is formed on a side surface of one of the second interconnects and is coupled with one of the first interconnects, wherein in the second region, the first interconnect group includes a step portion, and the step portion includes a plurality of terraces, adjacent terraces have different heights from each other by at least twice a distance between upper surfaces of two layers of the first interconnects which are included in the first interconnects and are adjacent in the second direction, and the plurality of terraces of the second region of the first interconnect group are arranged along a third direction perpendicular to the first and second directions in at least two rows, the at least two rows being apart from each other with a separator interposed between the at least two rows, and the separator is higher than any one of the plurality of the terraces in height, wherein a width of each of the terraces at a shorter side is larger than a width of each of the first interconnects in the first regions.