Patent ID: 9608658
Date: 2017-03-28
CPC Classifications: H03M

Claim:
1. An analog-to-digital converter (ADC) comprising: a plurality of successive approximation register (SAR) ADC circuits, each associated with a different voltage range segment of a voltage range for the ADC, each SAR ADC circuit being configured to: logic configured to generate a digital output of the ADC based on one or more of the digital signals, representative of the voltage level of the analog signal, output by one or more of the plurality of SAR ADC circuits and the respective voltage range segment associated with each of the one or more of the plurality of SAR ADC circuits, wherein a first SAR ADC circuit of the plurality of SAR ADC circuits is deactivated based on whether the voltage level of the analog signal is less than or greater than a voltage threshold within one of the segments associated with a second SAR ADC circuit of the plurality of SAR ADC circuits.