Patent ID: 9536038
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. An Integrated Circuit (IC) product produced by a process of: generating path delays for a plurality of paths in an IC design specification; sorting the path delays and selecting a top M % of paths sorted by maximum path delay; examining the top M % of paths to locate converging paths; generating converging path delays for the converging paths; finding a minimum converging path delay for each of the top M % of paths; sorting the minimum converging paths delays and selecting a top N % of the top M % of paths having largest minimum converging path delays; identifying the top N % of the top M % of paths as Functional Critical Paths (FCP); adding a functional critical path timing sensor to an output of each FCP; adding a voltage controller that controls a local power-supply voltage to the plurality of paths and to the functional critical path timing sensors; connecting FCP timing-failure outputs of the functional critical path timing sensors to inputs of the voltage controller, wherein the voltage controller is for increasing the local power-supply voltage when a FCP timing-failure output is activated, and for decreasing the local power-supply voltage when no FCP timing-failure output has been activated for a period of time; writing images of the IC product to a plurality of photomasks, the images including images of the functional critical path timing sensors connected to identified FCP's; and using the plurality of photomasks to print the images onto a semiconductor substrate during steps in an IC manufacturing process to build a plurality of dice of the IC product onto the semiconductor substrate, whereby the IC product has added circuitry for sensing of timing-failures of selected paths to control the local power-supply voltage to compensate for timing failures.