Patent ID: 9589998
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A manufacturing method of a thin film transistor array panel, comprising: forming a gate line on a substrate, the substrate comprising a wiring part and a channel part; forming a gate insulating layer covering the gate line; forming an oxide semiconductor layer, a first metal layer, and a second metal layer on the gate insulating layer; forming a first photo resist pattern having an opening disposed at a portion corresponding to the channel part on the second metal layer; forming a data wiring layer comprising a barrier layer and a main wiring layer disposed on the barrier layer by etching the first metal layer and the second metal layer together using the first photo resist pattern as a mask; removing the first photo resist pattern; forming a second photo resist pattern covering the data wiring layer and a portion of the oxide semiconductor layer corresponding to the channel part; and etching the oxide semiconductor layer using the second photo resist pattern as a mask.