Patent ID: 9711500
Date: 2017-07-18
CPC Classifications: H01L,H03K

Claim:
1. A multi-chip device, including: a plurality of stacked semiconductor devices including a top semiconductor device and a bottom semiconductor device; a plurality of external electrical connections formed on the bottom of the multi-chip device, the bottom semiconductor device is disposed between the plurality of external electrical connections and the top semiconductor device; the top semiconductor device includes a first circuit; the bottom semiconductor device includes a first through via and a first electrostatic discharge (ESD) protection circuit electrically connected to a first one of the plurality of external electrical connections; and the first through via provides an electrical connection through the bottom semiconductor device from a first surface to an opposite surface of the bottom semiconductor device and between the first one of the plurality of external electrical connections and a first terminal of the first circuit wherein the first terminal of the first circuit being free of an electrical connection to an ESD protection circuit formed on the top semiconductor device.