Patent ID: 9640522
Date: 2017-05-02
CPC Classifications: G06F,H01L

Claim:
1. A metal oxide semiconductor (MOS) device including a plurality of regions, the MOS device comprising: a first plurality of p-type MOS (pMOS) transistors and a first plurality of n-type MOS (nMOS) transistors in a first region of the device, each of the first plurality of pMOS transistors and each of the first plurality of nMOS transistors having fins, the first plurality of pMOS transistors including a first pMOS transistor having a first pMOS transistor gate, a first pMOS transistor source, and a first pMOS transistor drain, the first plurality of nMOS transistors including a first nMOS transistor having a first nMOS transistor gate, a first nMOS transistor source, and a first nMOS transistor drain, the first pMOS transistor gate and the first nMOS transistor gate being formed by a first gate interconnect extending in a first direction across the device; and a second plurality of unutilized pMOS transistors and a second plurality of unutilized nMOS transistors in a second region of the device, the second region being adjacent to the first region, each of the second plurality of unutilized pMOS transistors and each of the second plurality of unutilized nMOS transistors having fins, fins of the first plurality of pMOS transistors and the first plurality of nMOS transistors in the first region being disconnected from fins of the second plurality of unutilized pMOS transistors and the second plurality of unutilized nMOS transistors in the second region.