Patent ID: 9748285
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A manufacture method of a dual gate oxide semiconductor TFT substrate, comprising steps of: step 1, providing a substrate, and deposing a first metal layer on the substrate, and implementing pattern process to the first metal layer with a first photo process to form a first bottom gate and a second bottom gate; and deposing a bottom gate isolation layer on the first bottom gate, the second bottom gate and the substrate; step 2, deposing a color resist layer on the bottom gate isolation layer, and sequentially implementing pattern processes to the color resist layer with second, third and fourth photo processes respectively to form red/green/blue color resist layers; then, deposing a first flat layer on the red/green/blue color resist layers, and implementing pattern process to the first flat layer with a fifth photo process to form first flat layers respectively covering the red/green/blue color resist layers; implementing plasma treatment to the bottom gate isolation layer; step 3, deposing an oxide semiconductor layer on the bottom gate isolation layer and the first flat layers, and coating a photoresist layer on the oxide semiconductor layer, and employing a halftone mask to implement a sixth photo process: first, implementing exposure, development to the photoresist layer to obtain a first photoresist layer, a second photoresist layer, a third photoresist layer covering the oxide semiconductor layer respectively above the first bottom gate, the second bottom gate and the first flat layers; a thickness of two side areas of the first photoresist layer, a thickness of two side areas of the second photoresist layer and a thickness of the third photoresist layer are smaller than a thickness of a middle area of the first photoresist layer and a thickness of a middle area of the second photoresist layer; employing the first photoresist layer, the second photoresist layer, and the third photoresist layer to implement etching the oxide semiconductor layer for patterning the oxide semiconductor layer to respectively obtain a first oxide semiconductor layer, a second oxide semiconductor layer and a third oxide semiconductor layer respectively above the first bottom gate, the second bottom gate and the first flat layers; step 4, first, removing the two side areas of the first photoresist layer, the two side areas of the second photoresist layer and the third photoresist layer; employing the remaining middle area of the first photoresist layer and the remaining middle area of the second photoresist layer as being a mask layer to implement ion doping to the two side areas of the first oxide semiconductor layer, the two side areas of the second oxide semiconductor layer and the third oxide semiconductor layer, to transform the two side areas of the first oxide semiconductor layer and the two side areas of the second oxide semiconductor layer to be a conductor, and to transform the third oxide semiconductor layer to be an oxide conductor layer; then, removing the remaining middle area of the first photoresist layer and the remaining middle area of the second photoresist layer; step 5, deposing a top gate isolation layer on the first oxide semiconductor layer, the second oxide semiconductor layer, the oxide conductor layer and the bottom gate isolation layer, and implementing pattern process to the top gate isolation layer and the bottom gate isolation layer at the same time with a seventh photo process, to respectively form first via holes above the two side areas of the first oxide semiconductor layer, second via holes above the two side areas of the second oxide semiconductor layer, a third via hole above the oxide conductor layer and a fourth via hole between the first bottom gate and the second bottom gate to expose one side of the first bottom gate; step 6, deposing second, third metal layers on the top gate isolation layer, and implementing pattern process to the second, third metal layers with an eighth photo process, to respectively obtain a first top gate above the first oxide semiconductor layer, a first source and a first drain at two sides of the first top gate, a second top gate above the second oxide semiconductor layer and a second source and a second drain at two sides of the second top gate; the first source and the first drain respectively contact with the two side areas of the first oxide semiconductor layer through the first via holes, and the second source and the second drain respectively contact with the two side areas of the second oxide semiconductor layer through the second via holes, and the first source contacts with the oxide conductor layer through the third via hole and the second source contacts with the first bottom gate through the fourth via hole; step 7, deposing a passivation layer on the first top gate, the first source, the first drain, the second top gate, the second source, the second drain and the top gate isolation layer; step 8, deposing a second flat layer on the passivation layer, and implementing patterning process to the second flat layer, the passivation layer and the top gate isolation layer at the same time with a ninth photo process to obtain a fifth via hole above the oxide conductor layer to expose a portion of the oxide conductor layer to define a shape of a light emitting layer; the first bottom gate, the first oxide semiconductor layer, the first source, the first drain and the first top gate construct a first dual gate TFT, and the second bottom gate, the second oxide semiconductor layer, the second source, the second drain and the second top gate construct a second dual gate TFT; the oxide conductor layer constructs an anode of an OLED.