Patent ID: 9686762
Date: 2017-06-20
CPC Classifications: H03K,H04W

Claim:
1. A method of multiplexing low frequency clocks from at least one clock transmitter to at least one clock receiver to reduce interface count, said method comprising acts of: receiving the low frequency clocks from the at least one clock transmitter; generating a system frame signal from a system clock signal; mapping the low frequency clocks with the system frame signal by transmitting a first low frequency clock of the low frequency clocks in a first clock period coinciding with the system frame signal and subsequent low frequency clocks in corresponding subsequent clock periods; repeating the mapping of the low frequency clocks with the system frame signal after a predetermined time interval, wherein width of the system frame signal is one clock pulse; sending the low frequency clocks to a CLKMUX logic; generating selection signals, using said system frame and system clock signals, in a Mux selection logic, coupled to the CLKMUX logic, and sending the selection signals to the CLKMUX logic; multiplexing the low frequency clocks in the CLKMUX logic using the selection signals; transmitting the multiplexed clocks to a CLKDEMUX logic using an interface having a reduced interface count; de-multiplexing the clocks in the CLKDEMUX logic using said selection signals; sending the de-multiplexed clocks to a SELECT LOGIC for selecting at least one low frequency clock; filtering jitter caused in the low frequency clock; and distributing filtered clock by CLKSINK logic to various devices in the network element.