Patent ID: 9564903
Date: 2017-02-07
CPC Classifications: H01L,H03K

Claim:
1. A semiconductor die having: a logic unit having a plurality of inputs/outputs; a plurality of pads whereby electrical connections can be made to the die; and a multiplexer arranged between the inputs/outputs and the pads, the multiplexer being operable in a first mode in which the mutliplexer maps a first number of the inputs/outputs to a first number of the pads consisting of all used pads in the first mode with a first median spacing between each one of the pads of the first number of the pads disposed on a same side of the die, and the multiplexer being operable in a second mode in which the mutliplexer maps a second number of the inputs/outputs to a second number of pads consisting of all used pads in the second mode, the second number of pads being a first subset of the first number of the pads, with a second median spacing between each one of the pads of the second number of the pads disposed on the same side of the die, wherein the first number of the input/outputs is larger than the second number of the input/outputs and the first median spacing is smaller than the second median spacing.