Patent ID: 9638549
Date: 2017-05-02
CPC Classifications: G01D,G06K,G11C,H01L

Claim:
1. An integrated capacitance sensing module, comprising: a silicon substrate, wherein an embedded memory and a sensing circuit are constructed in the silicon substrate and fabricated at the same time; a first interlayer dielectric layer covering the silicon substrate; plural conducting layers formed over the first interlayer dielectric layer; a shielding layer formed over the plural conducting layers; a second interlayer dielectric layer covering the shielding layer; a lower sensing electrode layer formed over the second interlayer dielectric layer; a third interlayer dielectric layer formed over the lower sensing electrode layer; an upper sensing electrode layer formed over the third interlayer dielectric layer; and a protective coating layer covering the upper sensing electrode layer, wherein the upper sensing electrode layer and the lower sensing electrode layer are electrically connected with the sensing circuit through the conducting layers; wherein the embedded memory is a nonvolatile memory and the embedded memory comprises: a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the first p-type doped region and a second p-type doped region are constructed in a N-well region of the silicon substrate, the N-well region is connected to a N-well voltage, the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is constructed in the N-well region of the silicon substrate, and the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a first n-type doped region connected to an erase line voltage and a first P-well region connected to a P-well voltage, and the first n-type doped region is constructed in the first P-well region of the silicon substrate; and wherein the embedded memory further comprises: a first NMOS transistor comprising a first gate structure, a second n-type doped region, and a third n-type doped region, wherein the second n-type doped region and the third n-type doped region are constructed in a second P-well region of the silicon substrate; a first NMOS capacitor comprising a second gate structure and the third n-type doped region; and a second NMOS capacitor comprising a third gate structure and the third n-type doped region.