Patent ID: 9660054
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method comprising: forming a dummy gate stack over a channel region in a substrate; forming a first silicon nitride spacer over a source region in the substrate, the source region having a first doping type, the first silicon nitride spacer extending along a first sidewall of the dummy gate stack; forming a second silicon nitride spacer over a drain region in the substrate, the drain region having a second doping type, the second silicon nitride spacer extending along a second sidewall of the dummy gate stack, the second sidewall of the dummy gate stack being opposite of the first sidewall of the dummy gate stack; removing the dummy gate stack; forming a low temperature nitride layer over the first silicon nitride spacer, the second silicon nitride spacer and the channel region; implanting germanium ions in the low temperature nitride layer in a direction forming an acute angle with a top surface of the low temperature nitride layer; removing germanium-implanted portions of the low temperature nitride layer to form an asymmetric low temperature nitride spacer over a first portion of the channel region; and implanting ions of the second doping type in a second portion of the channel region unprotected by the asymmetric low temperature nitride spacer to form a pocket.