Patent ID: 9653490
Date: 2017-05-16
CPC Classifications: G02F,G09G,G11C,H01L,H03K

Claim:
1. A semiconductor device comprising: a first transistor, a second transistor, a third transistor, and a fourth transistor; and a first wiring and a second wiring, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same conductivity type, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the first transistor and a gate of the third transistor are electrically connected to the first wiring, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the source and the drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to the second wiring, wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, and wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor.