Patent ID: 9684053
Date: 2017-06-20
CPC Classifications: G01R

Claim:
1. A wafer for testing that tests a probe card, the probe card including a plurality of probe terminals, each probe terminal capable of being connected to a terminal of a device under test, the wafer for testing comprising: a plurality of terminals; at least three specified terminals among the plurality of terminals aligned in a first direction; and a plurality of connection wires, each of which electrically connects a corresponding specified terminal among the at least three specified terminals to a corresponding terminal among the plurality of terminals that is not a specified terminal; wherein each of the plurality of connection wires has a first end that is connected to the corresponding specified terminal and is capable of being connected with a specified probe terminal among the plurality of probe terminals and a second end that is connected to the corresponding terminal and is capable of being connected with another probe terminal among the plurality of probe terminals, such that the specified probe terminal can be connected one-to-one with each other probe terminal among the plurality of probe terminals; and wherein the first ends of the plurality of connection wires are aligned in the first direction, such that the specified probe terminal can be sequentially connected to the first end of each of the plurality of connection wires, by moving the wafer for testing relative to the probe card parallel to the first direction.