Patent ID: 9620063
Date: 2017-04-11
CPC Classifications: G09G

Claim:
1. A gate driver comprising a plurality of stages, one of which comprising: a first input circuit configured to apply a first input signal to a first node; a first gate signal circuit configured to generate a first logic level in response to a voltage of the first node; a second gate signal circuit configured to generate a second logic level in response to a second input signal; an inverting circuit configured to invert the voltage of the first node in response to a clock signal and the voltage of the first node, the inverting circuit further configured to apply the inverted voltage to a second node; a first emission signal circuit configured to generate a first voltage in response to a voltage of the second node; a second emission signal circuit configured to generate a second voltage in response to the voltage of the first node; and a charging circuit including a first capacitor, the first capacitor having a first electrode connected to the second node and a second electrode connected to a second voltage terminal providing the second voltage.