Patent ID: 9614058
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A device, comprising: a substrate fin formed in a bulk semiconductor substrate comprising a first semiconductor material having a crystalline structure; a second semiconductor material positioned above said substrate fin; an upper fin structure positioned on and in contact with said second semiconductor material, said upper fin structure comprising a third semiconductor material that is different from said second semiconductor material; a layer of insulating material disposed on said substrate and covering sidewalls of said substrate fin, said second semiconductor material, and only a portion of sidewalls of said upper fin structure; and a gate structure positioned above said layer of insulating material and around at least a portion of said upper fin structure, wherein a portion of said second semiconductor material extends along a length of said substrate fin and below said gate structure, and said gate structure contacts said upper fin structure without contacting a portion of said second semiconductor material disposed below said gate structure.