Patent ID: 9575833
Date: 2017-02-21
CPC Classifications: G06F,G11C,H03M

Claim:
1. An operating method of a memory controller, comprising: performing a soft read operation to read data stored in a semiconductor memory device using a soft read voltage; performing a soft decision ECC decoding operation to the read data based on a first log likelihood ratio (LLR) value; and performing the soft decision ECC decoding operation to the read data based on a second LLR value when the soft decision ECC decoding operation based on the first LLR value fails, wherein the first and second LLR values are selected between a default LLR value and an updated LLR value, and wherein the updated LLR value is generated on a basis of numbers of error bits and non-error bits of the read data, which are obtained through the soft decision ECC decoding operation to the read data.