Patent ID: 9672910
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A memory system for storing data in a plurality N of memory chips, the memory system comprising: a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M, the M memory chips including M data link chip transceivers, wherein each of the M memory chips includes a single one of the M data link chip transceivers, and wherein the N memory chips are grouped into the K sets of memory chips according to a first process; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets, the data link interface including an interface transceiver that is assigned to couple any one of the grouped K sets of memory chips to any one of the L signal processing engines within the one signal processing unit based on one or more of the M memory chips within the grouped set sensing the availability status of one of the L processing engines according to a second process that follows the first process, the interface transceiver transmitting data to a first one of the data link chip transceivers and receiving data from a second one of the data link chip transceivers, and the first one of the data link chip transceivers transmitting data to the second one of the data link chip transceivers, wherein the interface transceiver, the first one of the data link chip transceivers, and the second one of the data link chip transceivers form a reconfigurable ring network with the one of the L processing engines determined to be available according to the second process, wherein N is an integer value greater than or equal to 4, K is an integer value greater than or equal to 2, L is an integer value greater than or equal to 2, and M is an integer value greater than or equal to 2 and less than N.