Patent ID: 9583622
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor structure, comprising: a) providing a substrate, and sequentially forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; b) forming a doped region of the stress layer arranged in a specific position in the stress layer according to a type of a semiconductor device to be formed; c) sequentially forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that penetrates the nitride layer, the oxide layer, the SOI layer and the buried oxide layer and stops on an upper surface of the stress layer, where the first trench exposes at least part of the doped region of the stress layer; d) forming a cavity by etching through the first trench to remove the doped region of the stress layer; e) forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back the polycrystalline silicon; and f) forming an isolation region by filling the second trench.