Patent ID: 9558308
Date: 2017-01-31
CPC Classifications: G06F

Claim:
1. A method, comprising: inputting, by a computing device, a behavioral representation of a design for an integrated circuit, wherein the behavioral representation comprises a register transfer level (RTL) description of a 1×N building block; generating, by the computing device, a physical design representation based on the behavioral representation, wherein the physical design representation comprises one of a flat netlist, a hierarchical netlist, or a flattened netlist; and generating, by the computing device and via a 1×N compiler, a gate-level representation of the integrated circuit design based on the physical design representation, wherein the generating comprises converting the physical design representation into one or more 1×N building blocks and compiling the 1×N building blocks, via the 1×N compiler, into the gate-level representation.