Patent ID: 9601354
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method for making integrated circuits using a semiconductor substrate, the method comprising: etching a first pad opening to a first depth into a plurality of build-up layers including interlayer dielectric layers and metal layers that are over the semiconductor substrate; depositing a conductive layer over the plurality of build-up layers, including over the first pad opening and along sidewalls of the first pad opening; and etching the conductive layer to leave a remaining portion of the conductive layer over the first pad opening, along the sidewalls of the first pad opening, and extending over a portion of a top surface of the plurality of build-up layers to form a first bond pad within the first pad opening; wherein the first depth is located at a transition layer of the plurality of build-up layers and the transition layer comprises an isolation dielectric layer, an interconnect structure is exposed in a first sidewall of the first pad opening, and the conductive layer is conformal deposited over the first pad opening, including over the isolation dielectric layer within the first pad opening and along the sidewalls of the first pad opening, to form a connection with the interconnect structure.