Patent ID: 9720036
Date: 2017-08-01
CPC Classifications: G01R,G06F

Claim:
1. A system-on-chip (SoC), comprising: a functional bus for communication of data and control signals; at least one processor coupled to the functional bus; a memory coupled to the functional bus; and a debug module coupled to the functional bus, wherein the debug module receives trace data for each interval of an error checking session; generates a compact signature as a function of the received trace data, compares the compact signature to an expected signature for that interval to identify whether or not the interval contains at least one erroneous trace signal; and if the interval contains the at least one erroneous trace signal, provides the interval of the at least one erroneous trace signal for storing in the memory via the functional bus; and if the interval does not contain the at least one erroneous trace signal, the debug module does not store the interval of trace data in the memory, wherein the debug module comprises: