Patent ID: 9679964
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A completed semiconductor construction, comprising: a semiconductor base comprising a memory array region and a peripheral region adjacent the memory array region; semiconductor material of the semiconductor base within the peripheral region being patterned into two relatively wide mesas spaced from one another by an intervening region comprising at least one relatively narrow dummy feature projection having opposing sidewalls within the intervening region and having no electrical function, each of the two relatively wide mesas having a sidewall within the intervening region; the relatively narrow dummy feature projection having a width along a cross-section of X and the relatively wide mesas having widths along the cross-section of at least about 3X; at least some of the semiconductor material within the mesas being conductively-doped; and intervening material within the intervening region, the intervening material being in direct physical contact with both of the mesa sidewalls and all the dummy feature projection sidewalls within the intervening region.