Patent ID: 9653335
Date: 2017-05-16
CPC Classifications: C08G,C09J,H01L,Y10T

Claim:
1. A wafer processing laminate comprising a support, a temporary adhesive layer on the support, and a wafer laid contiguous to the temporary adhesive layer, the wafer having a circuit-forming front surface and a back surface to be processed, said temporary adhesive layer including a first temporary bond layer (A) of thermoplastic organosiloxane polymer which is releasably bonded to the front surface of the wafer and a second temporary bond layer (B) of thermosetting modified siloxane polymer which is laid contiguous to the first temporary bond layer and releasably bonded to and in direct contact with the support, wherein the first temporary bond layer (A) comprises a non-reactive organopolysiloxane consisting of 99.000 to 99.999 mol % of difunctional siloxane units of R the second temporary bond layer (B) is a single cured layer of a composition comprising 100 parts by weight of a thermosetting modified siloxane polymer which is a silphenylene-containing polymer comprising recurring units of general formula (1) and having a weight average molecular weight of 3,000 to 500,000 or an epoxy-containing silicone polymer comprising recurring units of general formula (2) and having a weight average molecular weight of 3,000 to 500,000, and 0.1 to 50 parts by weight of a crosslinker which is selected from the group consisting of an amino condensate modified with formalin or formalin-alcohol, a melamine resin, a urea resin, a phenol compound having on average at least two methylol or alkoxymethylol groups per molecule, and an epoxy compound having on average at least two epoxy groups per molecule, wherein R wherein Z is a divalent organic group selected from: n is 0 or 1, R wherein R X is a divalent organic group having general formula (3): wherein Z is a divalent organic group selected from: n is 0 or 1, R Y is a divalent organic group having general formula (4): wherein V is a divalent organic group selected from: p is 0 or 1, R the thickness of the first temporary bond layer (A) is in the range of 0.1 to 10 μm, the second temporary bond layer (B) is deposited such that the cured thickness is in the range of 10 to 200 μm, the support is selected from the group consisting of silicon wafers, glass substrates, and quartz wafers, the second temporary bond layer (B) being directly bonded to the silicon, glass, or quartz surface of the support, and the wafer is a semiconductor wafer.