Patent ID: 9564575
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. An integrated circuit comprising a magnetic random access memory (MRAM) structure, wherein the MRAM structure comprises: a bottom electrode that has a bottom electrode width in a width direction and comprises bottom electrode sidewalls that extend in a sidewall direction that is perpendicular to the width direction; a fixed layer overlying the bottom electrode, wherein the fixed layer has a fixed layer width in the width direction that is substantially equal to the bottom electrode width in the width direction and comprises fixed layer sidewalls that extend in the sidewall direction; a free layer overlying a central area of the fixed layer, wherein the free layer has a free layer width in the width direction that is narrower than the bottom electrode width in the width direction and comprises free layer sidewalls that extend in the sidewall direction; a top electrode overlying the free layer, wherein the top electrode has a top electrode width in the width direction that is substantially equal to the free layer width in the width direction and comprises top electrode sidewalls that extend in the sidewall direction; a first encapsulation layer disposed along the free layer sidewalls and the top electrode sidewalls, wherein the first encapsulation layer overlies lateral areas of the fixed layer, and wherein the lateral areas of the fixed layer are adjacent to the central area of the fixed layer; a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls; a first tunnel barrier layer disposed between the fixed layer and the free layer, wherein the first tunnel barrier layer has a first tunnel barrier layer width in the width direction that is substantially equal to the bottom electrode width in the width direction, wherein the first tunnel barrier layer comprises first tunnel barrier layer sidewalls that extend in the sidewall direction, and wherein the second encapsulation layer is disposed along the first tunnel barrier layer sidewalls; and a second tunnel barrier layer disposed between the free layer and the top electrode, wherein the second tunnel barrier layer has a second tunnel barrier layer width in the width direction that is substantially equal to the free layer width in the width direction, wherein the second tunnel barrier layer comprises second tunnel barrier layer sidewalls that extend in the sidewall direction, and wherein the first encapsulation layer is disposed along the second tunnel barrier layer sidewalls.