Patent ID: 9690747
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A method for operating a processor having an array of data processing cells controlled by a controlling unit, the method comprising: the controlling unit providing subapplications to a plurality of data processing cells by pre-loading the subapplications into a cache, wherein a subapplication comprises one or more processing instructions to be executed by an Arithmetic Logic Unit (ALU) of a data processing cell; each data processing cell processing the subapplication provided to it; a memory being configured as Last-In-First-Out (LIFO); the control unit using a Ready/Acknowledge protocol generated by the array of data processing cells for writing into the memory; the control unit using a Request/Acknowledge protocol generated by the array of data processing cells for reading from the memory; the control unit configuring interconnection and operating modes of the array of data processing cells and the memory; a data processing cell sending a trigger to the controlling unit upon finishing processing the subapplication provided to it; in response to receiving trigger, the controlling unit supplying another subapplication to the processing cell sending the trigger while the other cells continue processing; and in response to receiving said another subapplication, the receiving data processing cell processing data using the one or more new processing instructions of the another subapplication.