Patent ID: 9705512
Date: 2017-07-11
CPC Classifications: H03L

Claim:
1. A circuit comprising: a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal; a timing detection circuit configured to receive the third clock and the fourth clock and output a timing error signal; a filtering circuit configure to receive the timing error signal and output an oscillator control signal; a controllable oscillator configured to receive the oscillator control signal and output a fifth clock; a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor; a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor; and a calibration circuit configured to receive the timing error signal and the noise cancellation signal and output the gain control signal.