Patent ID: 9552171
Date: 2017-01-24
CPC Classifications: G06F,G11C

Claim:
1. A method, comprising: for a non-volatile memory circuit having a plurality of blocks formed according to a NAND type architecture in which memory cells of a block are formed along a plurality of word lines and in which the word lines of a block are written in sequence from a first end to a second end thereof, maintaining, for blocks in which one or more but less than all of the word lines have been written, first and second read counts, where the first read count tracks the cumulative number of reads for all word lines of the corresponding block, where the second read count tracks the cumulative number of reads to one or more of the last word lines in the write sequence of the corresponding block that is written at the time at which the read is performed, and wherein the first and second read counts are reset after an erase operation to the corresponding block; and in response to either of the first or second read counts of a block reaching a respective first or second count threshold, marking the corresponding block for a data relocation operation.