Patent ID: 9583501
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A semiconductor chip comprising: a tri-gate nonvolatile memory cell including: a base of a memory transistor in a first region of a substrate, the base of the memory transistor including a channel formed in a surface of the substrate, a tunnel layer overlying the channel, the tunnel layer comprising a thermal oxide formed by oxidizing the surface of the substrate at a first temperature, and a nitride layer overlying the tunnel layer; a base of a first metal oxide semiconductor (MOS) transistor in a second region of the substrate, the base of the first MOS transistor including a channel in the surface of substrate; a base of a second MOS transistor in the second region of the substrate, the base of the second MOS transistor including a channel in the surface of substrate; a first shared diffusion region in the surface of substrate between the channel of the first MOS transistor and the channel of the memory transistor, and wherein the first MOS transistor is coupled to the memory transistor through the first shared diffusion region; a second shared diffusion region in the surface of substrate between the channel of the second MOS transistor and the channel of the memory transistor, and wherein the second MOS transistor is coupled to the memory transistor through the second shared diffusion region; and further comprising a low temperature plasma oxide formed at a second temperature lower than the first temperature overlying the nitride layer and the surface of the substrate in the first region and the second region, the plasma oxide forming a top oxide layer overlying the nitride layer in the first region of the substrate and gate oxide layers overlying the surface of substrate in the second region of the substrate.