Patent ID: 9735775
Date: 2017-08-15
CPC Classifications: H01L,H03K

Claim:
1. A semiconductor integrated circuit comprising: a first electrode line in a line wiring layer; a first internal line in a layer different from the line wiring layer; a first switch configured to provide an electrical connection and disconnection between the first electrode line and the first internal line, the first switch is in a first switch arrangement region of the semiconductor integrated circuit; a first buffer circuit electrically connected to the first switch, the first buffer circuit is in a first buffer circuit arrangement region of the semiconductor integrated circuit; a second switch configured to provide an electrical connection and disconnection between a second electrode line and a second internal line, the second switch is in a second switch arrangement region of the semiconductor integrated circuit; and a second buffer circuit electrically connected to the second switch, the second buffer circuit is in a second buffer circuit arrangement region of the semiconductor integrated circuit, wherein the first buffer circuit arrangement region is disposed outside the first switch arrangement region, wherein the second buffer circuit arrangement region is disposed outside the second switch arrangement region and the first switch includes a first group of switch transistors and a second group of the switch transistors, a first control line being configured to control the first group and a second control line being configured to control the second group.