Patent ID: 9715415
Date: 2017-07-25
CPC Classifications: G06F

Claim:
1. A computer-implemented method of improving thread execution speed within a multi-processor system, the method comprising: generating a plurality of threads to schedule for execution on a plurality of processors of the multi-processor system, the plurality of processors including at least a first processor and a second processor, each processor having a plurality of individual cores; initially assigning at least one thread to the first processor for execution on a core of the first processor; determining a core utilization rate for each of the other threads being scheduled; identifying whether any of the other threads being scheduled for execution on the first processor has a core utilization rate greater than a pre-established core utilization rate threshold; in response to identifying a specific other thread assigned to the first processor having a core utilization rate that is greater than the pre-established core utilization rate threshold, re-assigning execution of the specific other thread from the first processor to the second processor, whereby the re-assigned other thread is able to execute on the second processor at a greater execution rate than the pre-established core utilization rate threshold; counting a total number of threads that have core utilization rates above or greater than the pre-established thread core utilization rate threshold; determining if the counted number of threads are less than a lower threshold number or greater than an upper threshold number; and in response to the counted number of threads being less than the lower threshold number or greater than the upper threshold number and not being less than a predetermined number of threads, maintaining a current processor assignments for the threads.