Patent ID: 9553200
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device comprising the steps of: forming a base insulating film; forming an oxide semiconductor layer over the base insulating film; forming a gate insulating layer over the oxide semiconductor layer; forming a gate electrode layer to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween; forming a first insulating layer to cover the gate insulating layer and the gate electrode layer; introducing an impurity element through the first insulating layer to form a pair of impurity regions in the oxide semiconductor layer; forming a second insulating layer over the first insulating layer; etching the first insulating layer and the second insulating layer to form a sidewall insulating layer in contact with a side surface of the gate electrode layer; forming a conductive layer over the oxide semiconductor layer, the sidewall insulating layer, the gate electrode layer, and the base insulating film; etching the conductive layer, wherein an etched conductive layer covers the oxide semiconductor layer, the sidewall insulating layer, and the gate electrode layer; and polishing the etched conductive layer to remove the etched conductive layer that overlaps with the gate electrode layer, thereby forming a source electrode layer and a drain electrode layer.