Patent ID: 9548944
Date: 2017-01-17
CPC Classifications: H04L

Claim:
1. An apparatus comprising: a plurality of switch stages arranged in sequential stages; a first switch stage connected to a plurality of inputs, the first switch stage having a plurality of first switches configured to operate with a first timing signal, the first timing signal having a first frequency; a second switch stage having a plurality of second switches configured to operate with the first timing signal, the plurality of second switches being more than the plurality of first switches and each of the plurality of second switches connected to each of the plurality of first switches; a third switch stage having a plurality of third switches configured to operate with a second timing signal having a second frequency, each of the plurality of third switches connected to each of the plurality of second switches and wherein the second frequency is higher than the first frequency by a factor equal to a number of switches in the first switch stage divided by a sum of the number of switches in the first stage and a number of the plurality of inputs; a fourth switch stage having a plurality of fourth switches configured to operate with the first timing signal, the plurality of fourth switches being more than the plurality of third switches and each of the plurality of fourth switches connected to each of the plurality of third switches; a fifth switch stage connected to a plurality of outputs, the fifth switch stage having a plurality of fifth switches configured to operate with the first timing signal and each of the plurality of fifth switches connected to each of the plurality of fourth switches; and a control element configured to control each of the plurality of switch stages for routing a signal from one of the plurality of inputs to one of the plurality of outputs.