Patent ID: 9589536
Date: 2017-03-07
CPC Classifications: G06F,G09G,H03K

Claim:
1. A gate controlling unit, comprising: a gate driving subunit configured for driving a gate line; a first reset subunit configured for resetting the gate driving subunit after the gate driving subunit finishes driving the gate line; and a suspension and resumption subunit configured for controlling the gate driving subunit to suspend and resume the gate driving subunit, wherein the gate driving subunit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, a first clock signal input terminal, a second clock signal input terminal, a first trigger signal input terminal, a second trigger signal input terminal, a first level signal input terminal, a second level signal input terminal and an output terminal; a gate electrode of the first transistor is electrically connected with the first trigger signal input terminal, a drain electrode of the first transistor is electrically connected with the first level signal input terminal, and a source electrode of the first transistor is electrically connected with a first node; a gate electrode of the second transistor is electrically connected with a drain electrode of the third transistor, a drain electrode of the second transistor is electrically connected with the first node, and a source electrode of the second transistor is electrically connected with the second level signal input terminal; a gate electrode of the third transistor is electrically connected with the second trigger signal input terminal, and a source electrode of the third transistor is electrically connected with a second node; a gate electrode of the fourth transistor is electrically connected with the second trigger signal input terminal, a drain electrode of the fourth transistor is electrically connected with a gate electrode of the fifth transistor, and a source electrode of the fourth transistor is electrically connected with the first node; a drain electrode of the fifth transistor is electrically connected with the second node, and a source electrode of the fifth transistor is electrically connected with the second level signal input terminal; a gate electrode of the sixth transistor is electrically connected with the second trigger signal input terminal, a drain electrode of the sixth transistor is electrically connected with the first node, and a source electrode of the sixth transistor is electrically connected with a gate electrode of the seventh transistor; a drain electrode of the seventh transistor is electrically connected with the first clock signal input terminal, and a source electrode of the seventh transistor is electrically connected with the output terminal; a gate electrode of the eighth transistor is electrically connected with the second node, a drain electrode of the eighth transistor is electrically connected with the output terminal, and a source electrode of the eighth transistor is electrically connected with the second level signal input terminal; a gate electrode of the ninth transistor is electrically connected with the second clock signal input terminal, a drain electrode of the ninth transistor is electrically connected with the output terminal, and a source electrode of the ninth transistor is electrically connected with the second level signal input terminal; a first plate of the first capacitor is electrically connected with the first node, and a second plate of the first capacitor is electrically connected with the output terminal; and a first plate of the second capacitor is electrically connected with the first clock signal input terminal, and a second plate of the second capacitor is electrically connected with the second node.