Patent ID: 9679909
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A method for manufacturing an integrated circuit, the method comprising: providing a semiconductor substrate having a memory cell region and a capacitor region, wherein the capacitor region includes one or more sacrificial shallow trench isolation (STI) regions; performing a first etch into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions; implanting dopants into regions of the semiconductor substrate lining the one or more trenches; after implanting the dopants, forming a dielectric layer, a conductive layer, and a hard mask layer stacked in that order over the semiconductor substrate and filling the one or more trenches; and performing a second etch into the hard mask layer, the conductive layer, and the dielectric layer to form a memory cell stack of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region, wherein the memory cell stack includes a select gate.