Patent ID: 9729146
Date: 2017-08-08
CPC Classifications: G09G,G11C,H03K

Claim:
1. A gate driving circuit, comprising: first through (N)th stages connected to each other, the first through (N)th stages being configured to output first through (N)th gate output signals, respectively, where N is an integer greater than 1, wherein an (M)th stage of the first through (N)th stages, where M is an integer which is larger than or equal to 1, and less than or equal to N, comprises: a pull-up control part configured to apply a second node signal applied to a second node to a first node and to generate a first node signal of the first node in response to the second node signal, the second node being provided with a carry signal of an (M−1)th stage or a vertical start signal; a pull-up part configured to output a clock signal as an (M)th gate output signal in response to the first node signal; a carry holding part configured to apply the (M)th gate output signal to the second node in response to the (M)th gate output signal; a carry part configured to output the clock signal as an (M)th carry signal in response to the first node signal; and a first pull-down part configured to pull down the (M)th gate output signal to a first off voltage in response to a carry signal of an (M+1)th stage, wherein the carry holding part includes a carry holding transistor and the carry holding transistor includes a control electrode to which the (M)th gate output signal is applied, an input electrode to which the (M)th gate output signal is applied, and an output electrode connected to the second node, wherein the pull-up control part includes a first pull-up control transistor and a second pull-up control transistor that are connected to each other in series, wherein an output electrode of the first pull-up control transistor is exclusively connected to an input electrode of the second pull-up control transistor, and wherein a control electrode of the first pull-up control transistor and a control electrode of the second pull-up control transistor are configured to receive the (M)th gate output signal from the carry holding part.