Patent ID: 9660020
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A laterally diffused metal oxide semiconductor (LDMOS) integrated circuit structure comprising: a p-type semiconductor substrate; an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate; a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate; an n-type reduced surface field region disposed over and in contact with the p-type implant layer; first and second p-type body wells disposed on opposite lateral sides of the p-type implant layer and opposite lateral sides of the n-type reduced surface field region, wherein the first and second p-type body wells are separated and spaced apart from one another by the n-type reduced surface field region; first and second shallow trench isolation structures disposed within the n-type reduced surface field region; and first and second gate structures, wherein the first gate structure is disposed partially over and in physical contact with the first p-type body well, partially over and in physical contact with the n-type surface field region, and partially over and in physical contact with the first shallow trench isolation structure, and wherein the second gate structure is disposed partially over and in physical contact with the second p-type body well, partially over and in physical contact with the n-type surface field region, and partially over and in physical contact with the second shallow trench isolation region.