Patent ID: 9735130
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A chip package comprising: a first integrated circuit die; at least one second integrated circuit die disposed over the first integrated circuit die; and a lid disposed over lateral portions of the first integrated circuit die and at least partially surrounding the at least one second integrated circuit die, the lid having inclined sidewalls spaced apart from and facing the at least one second integrated circuit die, the lid continuously extending laterally from the inclined sidewalls to a vertical outer edge of the lid, wherein no portion of the lid is disposed over the at least one second integrated circuit die, a top surface of an uppermost die of the at least one second integrated circuit die has a first distance to a top surface of the first integrated circuit die, a topmost surface of the lid has a second distance to the top surface of the first integrated circuit die, the first distance being larger than the second distance, and the first distance and the second distance are measured in a direction orthogonal to a plane formed by the top surface of the uppermost die of the at least one second integrated circuit die.