Patent ID: 9741728
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method for manufacturing an embedded flash memory device, the method comprising: forming a pair of gate stacks spaced over a semiconductor substrate, wherein the gate stacks include floating gates and control gates arranged over the floating gates; forming a polysilicon layer over the gate stacks and the semiconductor substrate; performing an etch back of regions of the polysilicon layer lining the gate stacks to below top surfaces of the gate stacks, while peripheral regions of the polysilicon layer are masked, to form an erase gate between the gate stacks; forming hard masks over the erase gate, word line regions of the remaining polysilicon layer, and logic gate regions of the remaining polysilicon layer; performing an etch through regions of the remaining polysilicon layer unmasked by the hard masks to form word lines and logic gates; and forming an interlayer dielectric (ILD) layer, and contacts extending through the ILD layer, over the gate stacks, the erase gate, the word lines, and the logic gates.