Patent ID: 9620514
Date: 2017-04-11
CPC Classifications: G11C,H01L

Claim:
1. A memory device, comprising: a substrate having a major surface; a stack of alternating layers comprising insulating layers and control gate electrodes located over the substrate; memory openings continuously extending from a topmost layer of the stack of alternating layers down to the major surface of the substrate, wherein each of the memory openings includes a respective memory stack structure extending through the stack of alternating layers, wherein sidewalls of the stack of alternating layers that physically contact the memory stack structures consist of concave sidewalls, wherein each of the memory stack structures comprises a plurality of memory cells arranged in a string extending in a first direction substantially perpendicular to the major surface of the substrate in a plurality of device levels, wherein each of the plurality of memory cells is positioned in a respective one of the plurality of device levels above the substrate; at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells; at least one second select gate electrode located above the plurality of memory cells; a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface; a first charge storage element located on a first side of the semiconductor channel; and a second charge storage element located on a second side of the semiconductor channel and located at a same level as the first charge storage element, wherein the second charge storage element is electrically isolated from the first charge storage element, and located at a same level as the first charge storage element.