Patent ID: 9614507
Date: 2017-04-04
CPC Classifications: H01L,H03K

Claim:
1. A method for providing a programmable delay circuit, comprising: forming a first stage comprising a first hybrid fin field effect transistor (finFET), the first hybrid finFET comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins; and forming a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET, the second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins, wherein the first default FET and the second default FET each receive a gate voltage from a power supply rail of the programmable delay circuit.