Patent ID: 9690646
Date: 2017-06-27
CPC Classifications: G06F,H03M,H04L

Claim:
1. A device, comprising: a pair of serializer/deserializers implemented in semiconductor circuitry with a serial communication line therebetween, that together include a SerDes lane; and an error detection system associated with the SerDes lane, the error detection system detecting when the SerDes lane is invalid, wherein the error detection system includes determining a hash code of a packet of data in the SerDes lane at a transmit side of the SerDes lane, sending the determined hash code along with the associated packet of data to a receive side of the SerDes lane, calculating a hash code of the received packet of data in the SerDes lane at the receive side of the SerDes lane, and comparing the calculated hash code to the sent hash code and determining the presence or absence of errors based on the comparison; wherein the device is configurable to allow for a user to optionally select or deselect for the transmit side of the SerDes lane to reset the SerDes lane upon receiving a communication from the receive side of the SerDes lane that the SerDes lane is invalid.