Patent ID: 9627500
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate having a memory cell area and a logic area; a first active area and a second active area in the memory cell area on the substrate; a third active area in the logic area on the substrate; an insulating layer on the substrate, the insulating layer configured to cover the first, second and third active areas; a first gate electrode configured to pass through the insulating layer, cover a side surface of the first active area, and cross the first active area, the first gate electrode including, a second gate electrode configured to pass through the insulating layer, cover a side surface of the second active area, and cross the second active area, the second gate electrode including, a third gate electrode configured to pass through the insulating layer, cover a side surface of the third active area, and cross the third active area, the third gate electrode having a width smaller than the first gate electrode and the second gate electrode and not having the first and second conductive layers, the third gate electrode including,