Patent ID: 9641161
Date: 2017-05-02
CPC Classifications: G01R,H01L,H03K

Claim:
1. A flip-flop disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate, the flip-flop comprising: master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region; scan mux input circuitry operably coupled to an input of the master switch circuitry, the scan mux input circuitry being made up of a second plurality of devices that are circumscribed by a scan mux perimeter which resides within the flip-flop region and which is non-overlapping with the master switch perimeter; and slave switch circuitry operably coupled to an output of the master switch circuitry, the slave switch circuitry being made up of a third plurality of devices that are circumscribed by a slave switch perimeter; the slave switch perimeter residing within the flip-flop region and being non-overlapping with both the master switch perimeter and the scan mux perimeter.