Patent ID: 9640548
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method for fabricating a non-volatile memory device, comprising: forming a first gate electrode layer and a first sacrificial layer over a substrate; forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer and the first sacrificial layer; forming a pair of first channel holes that expose the first sacrificial layer by penetrating through the stacked structure; forming a second channel hole by removing the exposed first sacrificial layer so that the pair of first channel holes and the second channel hole are connected to each other to form a U-shape hole; forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes; forming a channel layer in the first and second channel holes; removing the second sacrificial layers; and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer, wherein the inter-layer dielectric layers and the second sacrificial layers are formed of materials which are not oxidized during the forming of the oxide layer so that the oxide layer is formed only on the surface of the first gate electrode layer exposed through the first and second channel holes.