Patent ID: 9727475
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A processor comprising: a plurality of cores to execute instructions and process data; first snoop hardware logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop hardware logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC; wherein the first set of core valid bits identify cache lines which are stored both in the NI LLC and in L1 caches of cores identified by the core valid bits.