Patent ID: 9748970
Date: 2017-08-29
CPC Classifications: H03M

Claim:
1. A built-in-self-test (BIST) circuit connected to a sigma-delta modulator (SDM) for testing the SDM, wherein the SDM receives an SDM input signal from a processor and generates an SDM output signal based on the SDM input signal, wherein the BIST circuit receives the SDM output signal from the SDM and receives the SDM input signal from the processor, and wherein the SDM output signal includes a set of bit signals including first and second bit signals, the BIST circuit comprising: an averaging circuit that receives the set of bit signals, calculates an average value of a sum of the set of bit signals, and generates an average SDM signal, wherein a voltage level of the average SDM signal is equal to the average value of the sum of the set of bit signals; a reference signal generator that receives the SDM input signal and generates a reference SDM signal based on the SDM input signal; and a comparison circuit connected to the averaging circuit and the reference signal generator for (i) receiving the average SDM signal and the reference SDM signal, respectively, (ii) comparing the voltage level of the average SDM signal with a voltage level of the reference SDM signal, and (iii) generating a test output signal based on a threshold value and a difference between the voltage levels of the average SDM signal and the reference SDM signal.