Patent ID: 9660082
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. An integrated circuit transistor structure, comprising: a semiconductor substrate; a gate disposed on the semiconductor substrate and sidewall spacers abutting the gate; a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, wherein the first SiGe layer has a Ge concentration greater than 50 percent, and a Si concentration of greater than 0%, and the first SiGe layer is continuous across the source area or the drain area and extends under a portion of the gate and under the sidewall spacers; a second SiGe layer under the first SiGe layer, wherein the second SiGe layer has a lower Ge concentration than the first SiGe layer, wherein the second SiGe layer extends under the gate; and a channel between the source area and the drain area, wherein the channel comprises SiGe and the Ge concentration of the second SiGe layer is higher than a Ge concentration of SiGe in the channel wherein the integrated circuit transistor structure is a planar transistor structure.