Patent ID: 9659133
Date: 2017-05-23
CPC Classifications: G06F

Claim:
1. A method of making a semiconductor device, the method comprising: placing a plurality of circuit elements, by at least one processor, in a layout for the semiconductor device, the plurality of circuit elements having a plurality of pins; generating a layer assignment for assigning a plurality of interconnections to corresponding conductive layers of the semiconductor device, wherein the plurality of interconnections is free from routing in the layout during the generation of the layer assignment; routing, after generating the layer assignment, the plurality of interconnections in the layout in accordance with the layer assignment, wherein the plurality of interconnections couple corresponding pairs of pins among the plurality of pins; determining whether the plurality of routed interconnections satisfies a set of constraints, wherein determining whether the plurality of routed interconnects satisfies the set of constraints is performed independent of a function of the plurality of circuit elements, and whether routed interconnections of the plurality of routed interconnects overlap is a constraint of the set of constraints; and manufacturing the semiconductor device incorporating the layer assignment.