Patent ID: 9601216
Date: 2017-03-21
CPC Classifications: G06F,G11C

Claim:
1. A semiconductor device comprising: a first cell array including a plurality of memory cells; a plurality of redundancy cell arrays each including a plurality of spare memory cells for replacing one or more defective memory cells in the first cell array, the plurality of redundancy cell arrays comprising a first redundancy cell array and a second redundancy cell array; a plurality of fuse portions each configured to store a failed address corresponding to the one or more defective memory cells, the plurality of fuse portions including a first fuse portion and a second fuse portion; and a redundancy select controller configured to selectively assign each one of the fuse portions to each one of the redundancy cell arrays, respectively, the redundancy select controller configured to modify a first assignment of the first fuse portion to the first redundancy cell array and the second fuse portion to the second redundancy cell array to a second assignment of the first fuse portion to the second redundancy cell array and the second fuse portion to the first redundancy cell array.