Patent ID: 9627392
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. An integrated circuit (IC), comprising: a semiconductor substrate made up of a memory array region and a boundary region surrounding the memory array region; a plurality of shallow trench isolation (STI) regions disposed within the memory array region, wherein the STI regions have upper STI surfaces which are higher than a planar upper surface of the semiconductor substrate so as to define recesses between upper portions of neighboring STI regions; a plurality of floating gates filling the recesses between neighboring STI regions within the memory array region; a hard mask disposed on a first STI region of the plurality of the STI regions; a control gate layer disposed over an upper surface of the floating gates and stepping upwards to extend over an edge of the hard mask over the first STI region; and a control gate spacer disposed along a sidewall of the control gate layer and having a lower surface that abuts an upper surface of the hard mask.