Patent ID: 9716080
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A thin fan-out multi-chip stacked package structure, comprising: a chip stack formed by stacking a plurality of chips, wherein each of the chips has an active surface and at least one electrode located on the active surface, at least one electrode of a first chip is not covered by a second chip, and an active surface of the second chip is not stacked or covered by other chips in the chip stack; a dummy spacer disposed on the active surface of the second chip, wherein at least one electrode of the second chip is not covered by the dummy spacer; a plurality of bonding wires, wherein each of the bonding wires has a bonding thread and a vertical wire segment, and the bonding threads of the bonding wires are bonded to the electrodes of the chips and are integrally connected to the corresponding vertical wire segment; an encapsulant encapsulating the chip stack and the bonding wires, wherein the encapsulant has a flat surface, and a plurality of polished cross-sectional surfaces of the bonding wires and the dummy spacer are coplanarly exposed by the flat surface; and a redistribution layer structure formed on the flat surface, wherein the redistribution layer structure comprises a plurality of fan-out circuits, a first passivation layer, and a second passivation layer, the first passivation layer covers the flat surface and the dummy spacer while exposing the polished cross-sectional surfaces, the fan-out circuits are formed on the first passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires via openings of the first passivation layer, and the second passivation layer is formed on the first passivation layer and covers the fan-out circuits.