Patent ID: 9595585
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: forming a PMOS region and an NMOS region in a semiconductor substrate; forming a dummy gate structure in each of the PMOS region and NMOS region; forming a gate hard mask layer overlying top portions and sidewalls of each of the dummy gate structures; forming silicon carbon (SiC) regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the NMOS region; after forming the silicon carbon regions in the NMOS regions, forming silicon germanium (SiGe) regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the PMOS region; and while retaining the hard mask layer on top of the dummy gate in the PMOS region, performing ion implant to form source/drain regions in the NMOS region and the PMOS region, respectively.