Patent ID: 9610044
Date: 2017-04-04
CPC Classifications: A61B,H01L,H03F

Claim:
1. A method for compensating a capacitance mismatch between input lines of an instrumentation amplifier, the method comprising: operating a plurality of MOS capacitors of a variable capacitor circuit in a cut-off region in which an equivalent capacitance of each MOS capacitor remains substantially constant for variations of a first voltage signal, wherein each MOS capacitor is implemented by a MOS transistor with a gate terminal connected to the first voltage signal and a drain terminal shorted with a source terminal and connected to a second voltage signal, wherein the MOS capacitors are connected in parallel through the gate terminal connected to the first voltage signal, and wherein operating the plurality of MOS capacitors includes restricting the second voltage signal to two voltage values lying within the cut-off region; and changing the equivalent capacitance of the variable capacitor circuit so as to balance parasitic loads on both input lines, wherein changing the equivalent capacitance comprises controlling the second voltage signal between the two voltage values such that the equivalent capacitance is controllably adjustable within a subfemtoFarad range.