Patent ID: 9639417
Date: 2017-05-02
CPC Classifications: G06F

Claim:
1. A storage control apparatus comprising: a cache memory: and a processor, wherein the cache memory includes an error detection information storage area and a data storage area different from the error detection information storage area, and wherein the processor performs a procedure including generating error detection information for each data block as a unit of access to data to be written in a disk drive device and storing the error detection information in the error detection information storage area, storing the data in the data storage area on a data block basis, storing the error detection information read from the error detection information storage area in a meta-information storage area of the disk drive device, the meta-information storage area being for storing meta information, storing the data read from the data storage area in a user data storage area of the disk drive device, the user data storage area being different from the meta-information storage area and being for storing user data, and performing error detection on said each data block according to the error detection information read from the meta-information storage area and the data read from the user data storage area.