Patent ID: 9659956
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method of manufacturing a three-dimensional memory device, comprising: forming, from bottom to top, a bottom dielectric layer, a bottom sacrificial material layer, and an alternating stack of insulating layers and spacer material layers over a semiconductor substrate; forming a memory opening through the alternating stack, the bottom sacrificial material layer, and the bottom dielectric layer; forming an epitaxial channel portion and a memory stack structure in the memory opening; forming a backside contact trench through the alternating stack, the bottom sacrificial material layer, and the bottom dielectric layer; forming a first backside recess by removing the bottom sacrificial material layer selective to the insulating layers, the spacer material layers, and the bottom dielectric layer; forming a semiconductor oxide layer underneath the bottom dielectric layer and around a material of the epitaxial channel portion; forming second backside recesses by removing the spacer material layers selective to the insulating layers, the bottom dielectric layer, and the semiconductor oxide layer; and forming electrically conductive layers in the first and second backside recesses.