Patent ID: 9619232
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. A method of facilitating processing within a processing environment, the method comprising: predicting that a selected instruction is to execute in a pipelined processor, the pipelined processor having a plurality of stages of processing including an execute stage, and the selected instruction having a first privilege level and one or more other instructions executing in the pipelined processor having a second privilege level different from the first privilege level; based on predicting the selected instruction is to execute, predicting an entry address for the selected instruction and operating state associated therewith, the entry address indicating a location at which an instruction is to be fetched based on the selected instruction, and the operating state comprising a privilege level for the instruction at the entry address; storing the predicted operating state in a data structure coupled to a decode unit of the processing environment; based on predicting the entry address, fetching the instruction at the entry address prior to the selected instruction reaching the execute stage; and initiating decoding of the fetched instruction based on the predicted operating state, the decode unit to decode the fetched instruction based on the predicted operating state.