Patent ID: 9728495
Date: 2017-08-08
CPC Classifications: G11C,H01L

Claim:
1. A stacked microelectronic assembly, comprising: first and second microelectronic packages arranged in a stacked configuration, each of the microelectronic packages having: a lower package face and an upper package face opposite the lower package face, lower terminals at the lower package face, and upper terminals at the upper package face; a microelectronic element having memory storage array function and contacts at an element face thereof; and conductive interconnects each electrically connecting at least one lower terminal with at least one upper terminal, at least some of the conductive interconnects electrically connected with the contacts of the microelectronic element, the conductive interconnects including: first conductive interconnects configured to carry address information, second conductive interconnects configured to carry data information to and from the microelectronic elements, and no connect conductive interconnects that are electrically insulated from the microelectronic element within the respective microelectronic package, wherein each of the first conductive interconnects of the first microelectronic package overlies and is electrically connected with a corresponding one of the first conductive interconnects of the second microelectronic package having the same signal assignment, and wherein each second conductive interconnect of the first microelectronic package overlies and is electrically connected with a no-connect conductive interconnect of the second microelectronic package, and each second conductive interconnect of the second microelectronic package underlies and is electrically connected with a no-connect conductive interconnect of the first microelectronic package.