Patent ID: 9583399
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate; patterning the stacked structure into a fin structure; forming a sacrificial gate structure over the fin structure such that the sacrificial gate structure covers a part of the fin structure while remaining parts of the fin structure remain exposed, the remaining parts being source/drain regions and the part of the fin structure covered by the sacrificial gate structure being a channel region; removing the second semiconductor layers in the source/drain regions of the fin structure, such that the first semiconductor layers in the source/drain regions are exposed and are spaced apart from each other; recessing the second semiconductor layers in the channel region in a second direction perpendicular to the first direction toward inside the sacrificial gate structure; forming epitaxial source/drain structures on the exposed first semiconductor layers in the source/drain regions so that the epitaxial source/drain structures wrap around each of the exposed first semiconductor layers in the source/drain regions; removing the sacrificial gate structure to expose the channel region of the fin structure; removing the second semiconductor layers in the exposed channel region of the fin structure after removing the sacrificial gate structure so that the first semiconductor layers in the channel region are exposed; and forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in the channel region.