Patent ID: 9640559
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A low temperature poly-silicon (LTPS) array substrate, comprising: a first substrate having a first surface and a second surface opposite to the first surface; a first conductive layer and a second conductive layer over the first surface of the substrate, wherein the first and second conductive layers are insulated from each other and at least one of the first and second conductive layers comprises an opaque material; a polysilicon layer above the first and second conductive layers, wherein the polysilicon layer is shielded from backlight radiation from the substrate side by the opaque first or second conductive layer; an interlayer insulating layer above the polysilicon layer; and a metal layer on the interlayer insulating layer, wherein the metal layer comprises a source and a drain, wherein the source and the drain is each electrically connected with the polysilicon layer through a first via, wherein one of the source and the drain is electrically connected with the first conductive layer through a second via, and wherein the first conductive layer is disposed above the second conductive layer and the second conductive layer covers the entire first surface of the substrate.