Patent ID: 9595609
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a heavily doped semiconductor substrate of a first conductivity type; a buffer layer of the first conductivity type formed on the semiconductor substrate; a semiconductor layer of a second conductivity type formed on the buffer layer, the semiconductor layer comprising a plurality of trenches formed in the semiconductor layer, the trenches extending close to, up to, or into the buffer layer, the trenches forming mesas in the semiconductor layer; a first thin semiconductor region of the first conductivity type formed near the trench sidewall surface of the mesas; second thin semiconductor regions of the second conductivity type formed near the trench sidewall surface of the mesas and formed sandwiching the first thin semiconductor region; an epitaxial layer formed on the trench sidewall surfaces of the mesas; and a first dielectric layer formed in the trenches, the first dielectric layer filling at least part of the trenches, wherein the first thin semiconductor region has a first thickness and a first doping concentration, the second thin semiconductor regions having a second thickness and a second doping concentration, and the mesa of the semiconductor layer having a third thickness and a third doping concentration, the first, second and third thicknesses and the first, second and third doping concentrations being selected to achieve charge balance in operation.