Patent ID: 9685400
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A chip package comprising: a semiconductor substrate including a plurality of through-hole vias, the semiconductor substrate having a first area and a second area on a surface of the semiconductor substrate; a first semiconductor chip disposed on the first area of the surface of the semiconductor substrate; a plurality of second semiconductor chips disposed on the second area of the surface of the semiconductor substrate, the plurality of second semiconductor chips being stacked on one another; a plurality of interconnections penetrating through at least one chip among the plurality of second semiconductor chips, the plurality of interconnections being configured to electrically connect at least two chips among the plurality of second semiconductor chips; a first bonding pad disposed on the first semiconductor chip; and a second bonding pad disposed on one of the plurality of second semiconductor chips, wherein the first semiconductor chip is not penetrated by a penetrating interconnection.