Patent ID: 9576975
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A monolithic three-dimensional memory device, comprising: a vertically repeating stack of unit layer stacks, each unit layer stack comprising an electrically conductive layer, a lower silicon oxide material layer overlying the electrically conductive layer, a dielectric fill material region overlying the lower silicon oxide material layer, and an upper silicon oxide material layer overlying the dielectric fill material region; a semiconductor channel extending through the vertically repeating stack, at least one end portion of the semiconductor channel extending substantially perpendicular to a top surface of a substrate; charge storage regions that are located at each level of the electrically conductive layers, laterally surrounding the semiconductor channel, and vertically spaced from one another; a tunneling dielectric laterally surrounding the semiconductor channel, wherein an inner sidewall of each charge storage region contacts a respective portion of an outer sidewall of the tunneling dielectric; and a continuous blocking dielectric layer that contacts each lower silicon oxide material layer, each upper silicon oxide material layer, and each dielectric fill material region, each charge storage region, and the tunneling dielectric, wherein: the continuous blocking dielectric layer comprises: the plurality of laterally recessed portions comprises a silicon oxynitride in which an atomic concentration of nitrogen atoms is greater than 0.1%; and the plurality of laterally protruding portions comprises a silicon oxide material in which an atomic concentration of nitrogen atoms is less than 100 parts per million.