Patent ID: 9600023
Date: 2017-03-21
CPC Classifications: G06F

Claim:
1. A method for providing a timestamp in a real-time system, the real-time system comprising an FPGA and a CPU, which cooperate with one another, and at least one register in the FPGA, wherein the at least one register contains a system time, the method comprising: providing a CPU counter, the counter being driven by a clock signal generated by a clock generator of the CPU; providing a synchronization counter in the CPU, the synchronization counter being driven by the clock signal generated by the clock generator of the CPU; reading, by a real-time application in the CPU, the CPU counter to provide the system time to the real-time application; querying, by the real-time application, the synchronization counter to provide a counter value to the real-time application; and when the counter value output by the synchronization counter corresponds to less than a predetermined time period since the last synchronization of the CPU counter with the system time, providing a timestamp in the real-time system that is based on the CPU counter, and when the counter value output by the synchronization counter corresponds to more than a predetermined time period since the last synchronization of the CPU counter with the system time, synchronizing the CPU counter with the system time and providing a timestamp in the real-time system that is based on the CPU counter, wherein, interrupts are disabled during processing of the real-time application.