Patent ID: 9548372
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device, comprising: providing a substrate with a first region and a second region, wherein a first dummy poly gate and a second dummy poly gate are formed in the first region and the second region respectively; removing the first dummy poly gate and the second dummy poly gate to form a first trench and a second trench; forming a gate dielectric multi-layer on the first region and the second region, wherein the gate dielectric multi-layer includes a high-k capping layer; forming an etch stop layer on the gate dielectric multi-layer; forming a sacrificial layer on the etch stop layer, wherein the sacrificial layer is formed from titanium nitride and has a predetermined crystalline orientation ratio of [200] to [111]; performing a thermal treatment using tungsten hexafluoride on the sacrificial layer on the first region, thereby enabling the high-k capping layer on the first region to have a fluorine concentration substantially in a range from 1 at % to 10 at %; removing the sacrificial layer to expose the etch stop layer; forming a first-type work function metallic layer on the etch stop layer on the first region; forming a second-type work function metallic layer on the etch stop layer on the second region and on the first-type work function metallic layer; forming a barrier layer on the second-type work function metallic layer; and forming a silicide layer on the barrier layer.