Patent ID: 9685233
Date: 2017-06-20
CPC Classifications: G11C,H01L

Claim:
1. A method of operating a multiple bits per cell memory, comprising: storing a data set for programming a plurality of multi-level memory cells, the data set including for multi-level memory cells in the plurality of multi-level memory cells corresponding multi-bit codes indicating one of a plurality of program states or an inhibit state, where the plurality of program states correspond to a corresponding plurality of program level targets for the multi-level memory cells; and executing a plurality of program cycles for the plurality of multi-level memory cells to program the plurality of multi-level memory cells to program states in the plurality of program states, wherein a program cycle in the plurality of program cycles includes: wherein the plurality of multi-level memory cells are configured in a plurality of stacked layers, including grouping multi-level memory cells into a plurality of groups, where a first group of memory cells includes a first set of layers and a second group of memory cells includes a second set of layers; wherein the memory includes a plurality of pages of memory cells, and a page includes memory cells coupled to a set of N bit lines and to a set of M word lines, the plurality of multi-level memory cells includes memory cells in a selected page coupled in common to one word line, and the multi-level memory cells in respective stacked layers in the plurality of stacked layers are connected to bit lines in the set of N bit lines; and including programming a page of memory cells by performing said storing and said executing for successive pluralities of multi-level memory cells, in an order that includes selecting the page, selecting memory cells in the selected page in the first group, and then selecting in sequence each word line in the page, and then selecting memory cells in the selected page in the second group, and then selecting in sequence each word line in the page.