Patent ID: 9614027
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A high voltage device comprising: a substrate having a device region, the device region having a planar top surface with a length and a width direction, wherein first and second opposing width sides of the device region are along a channel width direction and first and second opposing length sides are along a channel length direction; an isolation region surrounding the opposing width and length sides of the device region, wherein isolation edges abut the opposing width and length sides of the device region; a transistor disposed in the device region, wherein the transistor includes a gate with first and second gate sidewalls, the gate includes a gate electrode over a gate dielectric, the gate is disposed on the top surface of the device region between first and second source/drain (S/D) regions, the first S/D region is adjacent to the first gate sidewall and the second S/D region is adjacent to the second gate sidewall, wherein top surfaces of the first and second S/D regions are co-planar with the top surface of the device region, the first S/D region is subject to a high voltage; and a silicide block disposed over a portion of the gate and over at least a portion of the first S/D region, the silicide block leaves a remaining portion of the gate uncovered while covering at least portions of isolation edges abutting the length sides of the device region adjacent and proximate to the first gate sidewall, the silicide block prevents formation of silicide over the silicide block, which includes at least portions of isolation edges abutting the length sides of the device region adjacent and proximate to the first gate sidewall.