Patent ID: 9575806
Date: 2017-02-21
CPC Classifications: G06F,Y02D

Claim:
1. An apparatus comprising: a plurality of thread processors of a multi-core processor to run a plurality of threads; a first memory controller directly coupled to a first thread processor and indirectly coupled to at least a second thread processor via a first set of one or more intervening thread processors, the first memory controller to provide access to a first memory; a second memory controller directly coupled to a third thread processor and indirectly coupled to at least a fourth thread processor via one or more intervening thread processors to provide access to a second memory; a memory controller access monitor unit coupled with the second thread processor of the plurality of thread processors, the memory controller access monitor unit to monitor proportions of memory accesses, of a thread of the plurality of threads that is to run on the second thread processor, to both the first memory and the second memory, wherein the thread is to access the first memory via the first set of the one or more intervening thread processors and the first memory controller, wherein the thread is to access the second memory via at least the third thread processor and the second memory controller; and a thread processor selector unit coupled with the memory controller access monitor unit, the thread processor selector unit to select a destination thread processor of the plurality of thread processors of the multi-core processor based on the monitored proportions of memory accesses by the thread to both the first memory and the second memory and at least a queueing delay associated with accessing the first memory, wherein the queueing delay is to incorporate one or more queueing delays for hops through the first set of the one or more intervening thread processors and is to incorporate a queueing delay within the first memory controller; and a thread migration initiation unit coupled with the memory controller access monitor unit, the thread migration initiation unit to initiate migration of the thread to the destination thread processor of the plurality of thread processors of the multi-core processor.