Patent ID: 9728621
Date: 2017-08-08
CPC Classifications: B82Y,H01L

Claim:
1. A method of forming features of a semiconductor device, the method comprising: providing a semiconductor substrate; forming a layered fin overlying the semiconductor substrate, wherein the layered fin comprises a plurality of sacrificial layers and a plurality of semiconductor layers, wherein two adjacent semiconductor layers of the plurality of sacrificial layers are separated by a sacrificial layer of the plurality of sacrificial layers; forming a gate over the layered fin; forming a capping layer on the gate; forming a spacer surrounding a sidewall of the gate; removing the sacrificial layers to provide a structure in which the two adjacent semiconductor layers are separated by a gap; forming an insulator in the gap; and forming source and drain regions located on the layered fin; wherein the insulator comprises a high-K dielectric material surrounded by a low-K dielectric material; wherein the high-K dielectric material and the low-K dielectric material are in contact with the two adjacent semiconductor layers; wherein forming the insulator in the gap comprises: