Patent ID: 9680637
Date: 2017-06-13
CPC Classifications: G06F,H04L

Claim:
1. A monolithic integrated circuit (IC) secure hashing device comprising: a plurality of registers comprising a mode register configured to store a mode of operation value; and a processor integrated with said plurality of registers and configured to receive a message, select a given secure hash algorithm (SHA) variant based upon the mode of operation value, process the message using the given SHA variant from among a plurality of different SHA variants, the plurality of different SHA variants being based upon corresponding different block sizes of bits, and cooperate with said plurality of registers for selecting the different block sizes of bits for the plurality of different SHA variants and for controlling SHA processing of the message; said processor comprising a message schedule generator configured to generate values for each round of SHA processing, a round counter cooperating with said message schedule generator and configured to count the rounds of SHA processing, and circuitry coupled to said message schedule generator and said plurality of registers, and configured to coordinate the SHA processing of the message, said circuitry comprising a finite state machine.