Patent ID: 9652574
Date: 2017-05-16
CPC Classifications: G03F,G06F,H01L,Y02P

Claim:
1. A method of optimizing a pattern density in a circuit layout design, comprising: (a) employing a computer to generate a first fill region in a first layer of a circuit layout design; (b) employing a computer to generate a second fill region in a second layer of the circuit layout design, the second layer being different than the first layer; (c) employing a computer to generate a pattern of representations of a multilayer fill structure, the representations including (d) employing a computer to determine a target density for a window of the circuit layout design, the window including a first portion in the first layer of the circuit layout design and a second portion in the second layer of the circuit layout design; (e) selecting representations of the multilayer fill structure from the pattern to be added to the circuit layout design, for changing a density for the window to approach the determined target density; and (f) adding the selected representations of the multilayer fill structure to the circuit layout design.