Patent ID: 9632138
Date: 2017-04-25
CPC Classifications: G01R

Claim:
1. An integrated circuit chip comprising: system circuitry configured to perform a function, the system circuitry comprising a plurality of sub-circuits configured to perform the function by performing concurrent actions; debugging circuitry configured to detect one or more errors in the system circuitry's performance of the function, the debugging circuitry comprising variability circuitry; wherein the debugging circuitry is configured to functionally test the system circuitry by: at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function, wherein the relative timing of the concurrent actions is altered by applying an error to one or more of the concurrent actions; and where one or more errors are found, recording the one or more errors.