Patent ID: 9536610
Date: 2017-01-03
CPC Classifications: G06F,G11C

Claim:
1. A nonvolatile semiconductor memory device comprising: a plurality of memory cells or a plurality of memory cell units each including a plurality of memory cells; a memory cell array including the plurality of memory cells or the plurality of memory cell units being arranged to form an array; a plurality of first latch circuits configured to latch data read from the plurality of memory cells or the plurality of memory cell units; wherein a first operation is performed in response to an input of a first command or an input of a first command sequence, and after the input of the first command or the input of the first command sequence, a first ready/busy signal goes from a ready state to a busy state in a first timing, and then the first ready/busy signal goes from a busy state to a ready state in a second timing before the first operation is completed, the first operation includes an operation in which data stored in at least a portion of the plurality of memory cells or the plurality of memory cell units are read and latched in the plurality of first latch circuits; wherein a second operation is performed in response to an input of a second command or an input of a second command sequence, and after the input of the second command or the input of the second command sequence, the first ready/busy signal goes from a ready state to a busy state in a third timing, and then the first ready/busy signal is kept to a busy state until the first operation is completed, the second operation includes an operation in which data stored in at least a portion of the plurality of memory cells or the plurality of memory cell units are read and latched in the plurality of first latch circuits; and wherein the first command is different from the second command, and the first command sequence is different from the second command sequence.