Patent ID: 9627443
Date: 2017-04-18
CPC Classifications: G11C,H01L

Claim:
1. A memory device, comprising: a semiconductor stack comprising multiple layers arranged in sequence substantially along a first dimension; a memory cell formed within a subset of the semiconductor stack, and comprising a patterned top electrode, a resistive switching layer and a patterned bottom electrode formed of respective ones of the multiple layers of the semiconductor stack and arranged in sequence along a direction, wherein the direction forms a forty five degree or larger angle to the first dimension at least near the subset of the semiconductor stack; wherein the bottom electrode layer comprises a top surface and an additional surface, the additional surface is located at the subset of the semiconductor stack and forms the forty five degree or larger angle to the first dimension; wherein the bottom electrode layer forms a bitline of the memory device and serves as the bottom electrode for the memory cell and serves as a second bottom electrode for at least one additional memory cell of the memory device; and wherein the top electrode layer forms a wordline of the memory device and serves as the top electrode for the memory cell and serves as a second top electrode for at least one additional memory cell of the memory device.