Patent ID: 9626264
Date: 2017-04-18
CPC Classifications: G01R,G06F,G11C

Claim:
1. A memory device test apparatus of performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU), comprising: a comparison test unit connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test, wherein the PCIe switch includes at least two or more downstream ports, each of the downstream ports being respectively connected to each of memory devices having the same lane bandwidth, and wherein a PCI lane bandwidth of the comparison test unit is the same as the sum of all lane bandwidths of all the memory devices mounted in the PCIe switch, and the comparison test unit maintains the bandwidth required for testing each of the memory devices.