Patent ID: 9697165
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A server system, comprising: a first motherboard having at least one first processor module and at least one first memory module, wherein the at least one first processor module is electrically coupled to the at least one first memory module by way of a memory transmission channel; a second motherboard having at least one second processor module and at least one second memory module, wherein the at least one second processor module is electrically coupled to the at least one second memory module by way of a memory transmission channel; a first back plate having at least one first peripheral component interconnect express (PCIE) switch chip and at least one second PCIE switch chip, wherein the at least one first PCIE switch chip is electrically coupled to the at least one second PCIE switch chip by way of a plurality of PCIE transmission channels; wherein the at least one first processor module is electrically coupled to the at least one first PCIE switch chip by way of the PCIE transmission channels, the at least one second processor module is electrically coupled to the at least one second PCIE switch chip by way of the PCIE transmission channels, the at least one first processor module converts memory data of the at least one first memory module into PCIE packet data to be transmitted to the at least one second processor module via the at least one first PCIE switch chip and the at least one second PCIE switch chip sequentially, and the at least one second processor module transforms the received PCIE packet data into memory data of the at least one second memory module for synchronizing the memory data of the at least one first memory module of the first motherboard with the memory data of the at least one second memory module of the second motherboard; a third motherboard having at least one third processor module and at least one third memory module, wherein the at least one third processor module is electrically coupled to the at least one third memory module by way of the memory transmission channel; a second back plate having at least one third PCIE switch chip and at least one fourth PCIE switch chip, wherein the at least one third PCIE switch chip is electrically coupled to the at least one fourth PCIE switch chip by way of the PCIE transmission channel; and a third back plate having at least one fifth PCIE switch chip and at least one sixth PCIE switch chip, wherein the at least one fifth PCIE switch chip is electrically coupled to the at least one sixth PCIE switch chip by way of the PCIE transmission channel; wherein the at least one first processor module is electrically coupled to the at least one third PCIE switch chip by way of the PCIE transmission channel, the at least one third processor module is electrically coupled to the at least one fourth PCIE switch chip by way of the PCIE transmission channel, the at least one first processor module converts the memory data of the at least one first memory module into PCIE packet data to be transmitted to the at least one third processor module via the at least one third PCIE switch chip and the at least one fourth PCIE switch chip sequentially, and the at least one third processor module transforms the received PCIE packet data into the memory data of the at least one third memory module for synchronizing the memory data of the at least one first memory module of the first motherboard with the memory data of the at least one third memory module of the third motherboard; and wherein the at least one second processor module is electrically coupled to the at least one fifth PCIE switch chip by way of the PCIE transmission channel, the at least one third processor module is electrically coupled to the at least one sixth PCIE switch chip by way of the PCIE transmission channel, the at least one second processor module converts the memory data of the at least one second memory module into PCIE packet data to be transmitted to the at least one third processor module via the at least one fifth PCIE switch chip and the at least one sixth PCIE switch chip sequentially, and the at least one third processor module transforms the received PCIE packet data into the memory data of the at least one third memory module for synchronizing the memory data of the at least one second memory module of the second motherboard with the memory data of the at least one third memory module of the third motherboard.