Patent ID: 9711645
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device comprising: forming a structure comprising a plurality of fins, which are disposed in parallel with each other to define respective channel regions, a single gate disposed over the respective channel regions of each of the plurality of fins, and a spacer, the spacer being disposed around and over the single gate and around and over respective outwardly facing sidewalls and respective upwardly facing surfaces of respective portions of each of the plurality of fins proximate to the single gate; applying an annealing process to the structure to shrink each of the plurality of fins in: side-to-side directions defined along a longitudinal axis of the single gate to create respective gaps between the respective outwardly facing sidewalls of each of the plurality of fins and complementary inwardly facing sidewalls of the spacer, and a vertical direction to create respective gaps between the respective upwardly facing surfaces of each of the plurality of fins and complementary downwardly facing surfaces of the spacer; and growing an epitaxial semiconductor layer in the respective gaps between the spacer and each of the plurality of fins.