Patent ID: 9575834
Date: 2017-02-21
CPC Classifications: G06F

Claim:
1. A system, comprising: a hardware processor and logic integrated with and/or executable by the hardware processor, the logic being configured to: a first binary sequence generator configured to create a binary sequence comprising a plurality of bonus bits, wherein a total length of the binary sequence is equal to or greater than the predetermined maximum burst size, and wherein the first binary sequence generator comprises a patterned read only memory (ROM) storing values, the ROM being configured for access according to a predetermined pattern to access the values; and a first parity module configured to provide a parity calculation prior to passing the plurality of data elements to the input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element, wherein meta data is included in the parity calculation to produce the parity bit.