Patent ID: 9716116
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A thin-film transistor (TFT) array substrate, comprising a backing plate, a buffer layer formed on the backing plate, a plurality of TFTs formed on the buffer layer and arranged in an array, a planarization layer formed on the TFTs, a common electrode formed on the planarization layer, a protection layer formed on the common electrode, and a patterned pixel electrode formed on the protection layer; the TFTs each comprising a poly-silicon semiconductor layer formed on the buffer layer, a gate insulation layer set on and covering the poly-silicon semiconductor layer, a gate electrode formed on the gate insulation layer and located above the poly-silicon semiconductor layer, an interlayer insulation layer set on and covering the gate electrode and the gate insulation layer, and a source electrode and a drain electrode formed on the interlayer insulation layer; the pixel electrode being electrically connected to the drain electrode; the drain electrode overlapping a portion of a horizontal projection of the common electrode; the drain electrode and the common electrode constituting a first storage capacitor, the pixel electrode and the common electrode constituting a second storage capacitor, the first storage capacitor and the second storage capacitor being connected in parallel to form a storage capacitor; wherein the drain electrode, the common electrode, and the pixel electrode are arranged such that the drain electrode and the pixel electrode are respectively on two opposite sides of common electrode, where the drain electrode faces a first one of the two opposite sides of the common electrode to collectively form the first storage capacitor and the pixel electrode faces a second one of the two opposite sides of the common electrode to collectively form the second storage capacitor.