Patent ID: 9606142
Date: 2017-03-28
CPC Classifications: G01R,H01L

Claim:
1. A method comprising: obtaining a structure comprising a test probe substrate including a top surface, one or more contact locations, and electrical conductors within the substrate, the contact locations being electrically connected to one or more of the electrical conductors; forming a first dielectric layer over the top surface of the substrate; forming a plurality of first openings within the first dielectric layer, thereby exposing a plurality of the contact locations; mapping three dimensional coordinates of the contact locations; storing the mapped coordinates electronically in a memory device; comparing the stored coordinates to a set of predetermined coordinate positions; determining a set of stored coordinates that do not match the set of predetermined coordinate positions; forming lateral extensions of one or more of the first openings within the first dielectric layer; depositing an electrically conductive material within the first openings and lateral extensions; depositing a second dielectric layer over the first dielectric layer; forming a plurality of second openings within the second dielectric layer, one or more of the second openings communicating with the lateral extensions; depositing an additional electrically conductive material within the second openings to form an array of electrical contact regions electrically connected to the contact locations, and planarizing the second dielectric layer; wherein at least the step of forming the lateral extensions is performed using the set of stored coordinates that do not match the set of predetermined coordinate positions.