Patent ID: 9741829
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device including a Fin FET, the method comprising: forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer; forming a source/drain structure in the fin structure; after forming the source/drain structure in the fin structure, forming a gate structure over a part of the fin structure, the gate structure extending in a second direction perpendicular to the first direction; forming an interlayer dielectric layer over the fin structure, the source/drain structure and the gate structure; forming a contact hole in the interlayer dielectric layer so as to expose the source/drain structure; directly depositing a cap layer including silicon phosphide, by using a silicon containing gas and a phosphorous containing gas, on a bottom surface and sidewalls of the contact hole and on an entire upper surface of the interlayer dielectric layer; and forming a contact metal layer over the cap layer.