Patent ID: 9646976
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a barrier layer disposed over a contact and a first dielectric, the barrier layer comprising a pre-patterned barrier structure that is electrically conductive, wherein the pre-patterned barrier structure is formed by a first patterning, disposed over the contact and includes a first length, wherein the barrier layer further comprises at least one first hydrogen barrier structure disposed besides the pre-patterned barrier structure, wherein the at least one first hydrogen barrier structure is in contact with at least one sidewall of the pre-patterned barrier structure; and a patterned ferro-stack including a second length disposed at least partially over the pre-patterned barrier structure, wherein the patterned ferro-stack is formed by a second patterning and coupled electrically to the contact via the pre-patterned barrier structure.