Patent ID: 9570376
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A chip package comprising: a first substrate having at least one circuit layer formed on a first surface thereof; a first die mounted on a second surface of the first substrate, opposite from the first surface; an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly being affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate; and a second substrate positioned on a side of the first die opposite from the first substrate so as to position the first die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.