Patent ID: 9553168
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor memory device, the method comprising: alternately stacking interlayer insulation layers and sacrificial layers over a semiconductor substrate; forming channel holes vertically passing through the interlayer insulation layers and the sacrificial layers; forming memory layers along surfaces of the channel holes; forming channel layers in the channel holes including the memory layers; forming a trench between the channel holes by etching a portion of the interlayer insulation layers and the sacrificial layers after forming the channel layers; forming recesses between the interlayer insulation layers by removing the sacrificial layers after forming the trench; forming seed films over surfaces of the recesses and on surfaces of the interlayer insulation layers; forming sacrificial patterns in the recesses after forming the seed films; forming seed patterns in the recesses by etching the seed films exposed between the sacrificial patterns using the sacrificial patterns as an etching barrier; and growing metal layers from the seed patterns in the recesses.