Patent ID: 9576880
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A structure, comprising: a via interconnect in a dielectric material comprising a liner and a conductive material; an upper wiring layer in the dielectric material and in alignment with the via interconnect, the upper wiring layer comprising a liner and the conductive material; a diffusion blocking liner embedded within the conductive material over the via interconnect and below the liner of the upper wiring layer which is located such that void formation due to electromigration or stress migration is prevented in the via interconnect; and a seed layer on the liner of the upper wiring layer, wherein the diffusion blocking liner is devoid of the seed layer, and the via interconnect and the upper wiring layer are a dual damascene structure, and the via interconnect partially fills a via of the dual damascene structure such that the diffusion blocking liner is embedded within the conductive material at a top portion of the partially filled via.