Patent ID: 9698231
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate; a tunnel insulation pattern on the substrate; a charge storage pattern on the tunnel insulation pattern, the charge storage pattern comprising a width in a direction that is substantially perpendicular from a direction of the charge storage pattern to the substrate; a dielectric pattern on the charge storage pattern, the dielectric pattern comprising a width in the direction that is substantially perpendicular from the direction of the charge storage pattern to the substrate, the width of the dielectric pattern being less than a width of the charge storage pattern; a control gate on the dielectric pattern, the control gate comprising a width in the direction that is substantially perpendicular from the direction of the charge storage pattern to the substrate, the width of the control gate being greater than the width of the dielectric pattern; a metal-containing gate on the control gate; and a capping layer being on a sidewall of the metal-containing gate and extending from a sidewall of the control gate, the capping layer comprising a conductive material.