Patent ID: 9747215
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. A stride reference prefetcher for a processor, comprising: access logic that detects successive load requests to cache lines of a page of memory, that determines a stride value between each of said successive load requests and that determines a minimum stride value, and that updates an access history vector which identifies each cache line of said page of memory that has been accessed; a stride mask logic that provides a stride mask vector based on said minimum stride value; count logic that filters said access history vector with said stride mask vector to determine a positive access count and a negative access count; arbitration logic that triggers a prefetch operation when either one of said positive access count and said negative access count meets a trigger threshold and that indicates a direction of memory accesses based on a relative size of said positive access count and said negative access count; and a prefetcher that performs said prefetch operation using a prefetch address when triggered by said arbitration logic, wherein said prefetcher determines said prefetch address by combining a load request address and said minimum stride value in a direction indicated by said arbitration logic.