Patent ID: 9692403
Date: 2017-06-27
CPC Classifications: H03K

Claim:
1. A clock generator, comprising: a duty cycle correction circuit, comprising: wherein the controller is configured to: apply the delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of the different version of the clock signal and measure the time during which the different version of the clock signal is low; compare the time during which the different version of the clock signal is low to the time during which the different version of the clock signal is high; and generate the digital value to reduce duration of a longer of the time during which the different version of the clock signal is low and the time during which the different version of the clock signal is high; a multiplexer configured to selectably route a non-inverted version of the clock signal and an inverted version of the clock signal to the first programmable delay element for measurement of the time during which the different version of the clock signal is high and the time during which the different version of the clock signal is low.