Patent ID: 9698086
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A chip package, comprising: a leadframe comprising a die pad and a plurality of lead fingers; wherein the lead fingers extend out of the chip package; at least a first chip comprising an active surface and a second surface opposite the active surface, the second surface of the first chip being attached to the die pad, the active surface of the at least first chip being bonded to a surface of one or more of the lead fingers via a first set of wire bonds, wherein the at least first chip includes a power MOS transistor; a second chip bonded to one or more of the lead fingers; a heat slug attached to the second chip; and an encapsulation material encapsulating the die pad, the at least first chip, the second chip, and the first set of wire bonds; wherein the die pad is exposed on a first surface of the chip package, configured to externally dissipate heat, and the heat slug is exposed on a second surface of the chip package opposite the first surface, configured to externally dissipate heat.