Patent ID: 9570324
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of manufacturing a package system, the method comprising: forming a first interconnect structure over a first surface of a first substrate; forming at least one first through silicon via (TSV) structure in the first substrate; disposing the first substrate over a carrier with the first surface facing the carrier; depositing a molding compound material over the carrier and around the first substrate; forming at least one through via in the molding compound material, wherein the at least one through via is offset from the first substrate in a direction parallel to the first surface; forming a second interconnect structure over a second surface of the first substrate; removing the carrier to expose the first interconnect structure over the first surface of the first substrate; and disposing a first integrated circuit over the first surface of the first substrate, the first integrated circuit being electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.