Patent ID: 9612929
Date: 2017-04-04
CPC Classifications: G06F

Claim:
1. A method, comprising: generating a test case for a plurality of processors, wherein the test case comprises streams of instructions; allocating at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line; pairing a first subset of the streams of instructions of the generated test case; scheduling the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors, wherein a first subset of the streams of instructions is executed by a first one or more processors of the plurality of processors; and re-scheduling the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors, wherein the first subset of the streams of instructions is re-scheduled for execution by a second one or more processors of the plurality of processors without waiting for any other processors except the first one or more processors to finish executing the first subset of the streams of instructions.