Patent ID: 9716171
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising a first gate insulator formed on a semiconductor substrate; a second gate insulator formed on the semiconductor substrate, the second gate insulator being thicker than the first gate insulator; a first gate conductive layer formed on the first gate insulator; a second gate conductive layer formed on the second gate insulator; a first spacer, comprising a first bottom insulating layer, a first middle insulating layer overlying the first bottom insulating layer, and a first upper insulating layer overlying the first middle insulating layer, the first spacer formed beside the first gate conductive layer; and a second spacer, comprising a second bottom insulating layer, a second middle insulating layer overlying the second bottom insulating layer and a second upper insulating layer overlying the second middle insulating layer, the second spacer formed beside the second gate conductive layer, wherein a horizontal length of the first spacer in contact with a surface of the semiconductor substrate is different than a horizontal length of the second spacer in contact with a surface of the semiconductor substrate, wherein an end point of the second upper insulating layer is aligned with an end point of the second bottom insulating layer and the second middle insulating layer, and wherein a cross sectional area of the second upper insulating layer is larger than a cross sectional area of the first upper insulating layer.