Patent ID: 9632126
Date: 2017-04-25
CPC Classifications: G01R

Claim:
1. A circuit for measuring a leakage current in a semiconductor integrated circuit, comprising: a system on chip (SoC), including a multi-mode self-test circuit, wherein the self-test circuit includes transistor or functional block current leakage measurement circuitry, including: an operational amplifier configured to receive a reference voltage at a non-inverted input terminal and a feedback voltage at an inverted input terminal connected to a feedback node, and to amplify a difference between the reference voltage and the feedback voltage; a first PMOS transistor having a gate to which an output voltage of the operational amplifier is applied, a source connected to a first supply voltage, and a drain connected to the feedback node; a first switch connected between the feedback node and a circuit block to be tested; a second PMOS transistor having a gate connected to the gate of the first PMOS transistor, and a source connected to the first supply voltage; a resistor connected between a drain of the second PMOS transistor and a ground voltage; and an analog-to-digital (A/D) converter configured to perform an A/D conversion on a first voltage signal measured from the resistor to generate output data, further comprising: a second switch connected between a source of the first NMOS transistor and the ground voltage; a third switch having a first terminal connected to a first terminal of the first switch, a second terminal connected to the ground voltage, and a third terminal connected to a gate of the first NMOS transistor; a fourth switch having a first terminal connected to the first terminal of the first switch, a second terminal connected to the ground voltage, and a third terminal connected to a drain of the first NMOS transistor; a fifth switch connected between a drain of the third PMOS transistor and the ground voltage; a sixth switch having a first terminal connected to the first terminal of the first switch, a second terminal connected to a second supply voltage, and a third terminal connected to a gate of the third PMOS transistor; a seventh switch having the first terminal connected to the first terminal of the first switch, a second terminal connected to the second supply voltage, and a third terminal connected to a source of the third PMOS transistor; and an eighth switch having a first terminal connected to the first terminal of the first switch, a second terminal connected to the second supply voltage, and a third terminal connected to a bulk of the third PMOS transistor.