Patent ID: 9747402
Date: 2017-08-29
CPC Classifications: G06F,H01L

Claim:
1. A method comprising: determining candidate cells of a half-pitch technology in an integrated circuit cell library, each of the candidate cells having one or more features; determining a first design rule selected from the group consisting of an odd-number-only rule and an even-number-only rule; selecting a first group of cells from the candidate cells, with the first group of cells being compliant with the first design rule; and placing the first group of cells into a first row of an integrated circuit such that cells of the first group of cells are immediately adjacent to neighboring cells, the first row having a row layout; modifying the row layout of the first row upon determining that an immediately adjacent pair of cells forms a Go path, the modifying the row layout comprising inserting a buffer between immediately adjacent pair of cells to eliminate the Go path; wherein Go paths in the first group of cells represent first distances between adjacent pairs of features that are less than a minimum spacing allowed by the half-pitch technology; wherein double-patterning full traces in the first group of cells represent Go paths contiguously traversing from a VDD line to a VSS line; wherein the odd-number-only rule requires that each double-patterning full trace traversing cells in the first group of cells have only an odd number of Go paths between the VDD line and the VSS line; and wherein the even-number-only rule requires that each double-patterning full trace traversing cells in the first group of cells have only an even number of Go paths between the VDD line and the VSS line.