Patent ID: 9711195
Date: 2017-07-18
CPC Classifications: G11C

Claim:
1. A semiconductor device comprising: a first chip including a first external signal-inputting circuit, first to third signal-transmitting circuits, a first command-delaying circuit, a fourth signal-transmitting circuit and a first address-latching circuit, the first external signal-inputting circuit configured to receive and output an external clock, an external command and an external address, the first to third signal-transmitting circuits configured to output signals outputted from the first external signal-inputting circuit as a first internal clock, a first internal command and a first internal address based on a master enabling signal, the first command-delaying circuit configured to delay the first internal command for a period of the first internal clock, the fourth signal-transmitting circuit configured to output a signal outputted from the first command-delaying circuit as a first delay command based on the master enabling signal, and the first address-latching circuit configured to latch the first internal address based on the first internal command and to output a latched signal as a first latch address based on the first delay command; a second chip including a second external signal-inputting circuit, fifth to seventh signal-transmitting circuits, a second command-delaying circuit, an eighth signal-transmitting circuit and a second address-latching circuit, the fifth to seventh signal-transmitting circuits configured to output signals outputted from the second external signal-inputting circuit as a second internal clock, a second internal command and a second internal address based on the master enabling signal, the second command-delaying circuit configured to delay the second internal command for a period of the second internal clock, the eighth signal-transmitting circuit configured to output a signal outputted from the second command-delaying circuit as a second delay command based on the master enabling signal, and the second address-latching circuit configured to latch the second internal address based on the second internal command and to output a latched signal as a second latch address based on the second delay command; and a plurality of through silicon vias (TSV) configured to transmit the first internal address, the first internal command and the first delay command of the first chip to the second chip as the second internal address, the second internal command and the second delay command.