Patent ID: 9594560
Date: 2017-03-14
CPC Classifications: G06F,Y02D

Claim:
1. A processor comprising: a first logic to calculate a scalability value for a domain of the processor based at least in part on an active state residency of the domain, a stall duration of the domain and memory bandwidth information of the domain, and to determine an operating frequency update for the domain based on a current operating frequency of the domain and the scalability value, wherein the domain includes an active state residency counter to count a number of cycles of an evaluation time interval in which the domain is in an active state, a stall counter to count a number of cycles of the evaluation time interval in which the domain is in a stall state in which execution units of the domain are waiting for a memory transaction to complete to make forward progress and a plurality of memory bandwidth counters to count a number of transactions between the domain and a system memory coupled to the processor, the first logic to determine the active state residency based on a value of the active state residency counter and to determine the stall duration based on a value of the stall counter, and to calculate the scalability value according to: wherein C0_residency_time is a value of the active state residency counter, memory_stalled_time is a value of the stall counter, memory_read_bandwidth and memory_write_bandwidth are values of the plurality of memory bandwidth counters and A, B, C and D are coefficients selected based on a workload executed in the processor.