Patent ID: 9748953
Date: 2017-08-29
CPC Classifications: G11C,H03K

Claim:
1. A memory module comprising: a command/address (CA) register disposed at a central portion of a circuit board having a first edge and an opposing second edge, the CA register configured to receive an external CA signal and to provide a first internal CA signal and a second internal CA signal responsive to the external CA signal; a plurality of memory devices arranged on the circuit board in a first row and a second row adjacent to the first row in a first direction, wherein the first and second rows extend in a second direction between the first and second edges; a first internal CA transmission line extending from the CA register towards the second edge, and then proximate the second edge, extending back towards the first edge to traverse the first row in its entirety in a fly-by, daisy-chain topology and configured to communicate the first internal CA signal to each of the memory devices in the first row; a second internal CA transmission line extending from the CA register towards the second edge, and then proximate the second edge, extending back towards the first edge to traverse the second row in its entirety in a fly-by, daisy-chain topology and configured to communicate the second internal CA signal to each of the memory devices in the second row; and a module resistor unit configured to terminate the first and second internal CA transmission lines, the module resistor unit comprising a termination resistor having a first end connected to a termination voltage and a second end connected to both the first and second internal CA transmission lines, wherein a resistance of the termination resistor is half of a termination resistance required to terminate only one of the first and second internal CA transmission lines.