Patent ID: 9721650
Date: 2017-08-01
CPC Classifications: G11C

Claim:
1. A memory, comprising: a memory core having a plurality of memory cells; a first write assist circuit including write and boost logic, the first write assist configured to assist writing to a first group of the plurality of memory cells of the memory core; and a second write assist circuit including write and boost logic, the second write assist configured to assist writing to a second group of the plurality of memory cells of the memory core, wherein the first write assist circuit and the second write assist circuit are located on opposite sides of the memory core and wherein the first write assist circuit and the second write assist circuit are operatively coupled to a bitline, the first write assist circuit configured to boost voltage applied to the bitline to write to one of the plurality of memory cells from the first group and the second write assist circuit configured to boost voltage applied to the bitline to write to the one of the plurality of memory cells from the second group.