Patent ID: 9591753
Date: 2017-03-07
CPC Classifications: H05K

Claim:
1. A circuit board, comprising: a substrate; a patterned copper layer, disposed on the substrate and exposing a portion of the substrate; a phosphorous-containing electroless plating palladium layer, disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%; an electroless plating palladium layer, disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is at least 99% or more; and an immersion plating gold layer, disposed on the electroless plating palladium layer.