Patent ID: 9548311
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A non-volatile semiconductor memory, comprising: a substrate; a plurality of non-volatile storage elements arranged into rows and columns above a surface of the substrate, each non-volatile storage element including a suspended charge storage region having a bottom surface separated from the surface of the substrate by a void; a plurality of isolation regions formed in the substrate between a plurality of active areas of the substrate; a plurality of support pillars formed in each isolation region; a plurality of dielectric strips including a dielectric strip formed for each row of non-volatile storage elements, each dielectric strip having a lower surface coupled to an upper surface of a support pillar in each isolation region; and a plurality of control gates including a control gate formed over each row of non-volatile storage elements, each control gate being separated from underlying charge storage regions of the row by the dielectric strip for the row.