Patent ID: 9652236
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A processor, comprising circuitry to: execute a first instruction and a second instruction, the first instruction ordered before the second instruction, the first instruction including a reference to a first logical register assigned to a first physical register, the second instruction including a reference to a second logical register assigned to a second physical register; determine whether the second instruction is data-independent of the first instruction; reassign the second physical register to another logical register before retirement of the first instruction based upon the determination whether the second instruction is data-independent of the first instruction; execute one or more checkpoint instructions including references to one or more checkpoint logical registers assigned to one or more checkpoint physical registers, the checkpoint instructions ordered before the first instruction; and determine whether the second physical register is unequal to each of the checkpoint physical registers; wherein reassigning the second physical register to another logical register before retirement of the first instruction is based upon the determination whether the second physical register is unequal to each of the checkpoint physical registers.