Patent ID: 9569354
Date: 2017-02-14
CPC Classifications: G06F,G11C

Claim:
1. A system, comprising: a first memory section; and a second memory section, the system configured to emulate an electrically erasable programmable read-only memory if data is to be stored with high endurance, wherein the first memory section comprises a plurality of storage locations configured to store the data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment of the plurality of data segments stored in the first memory section to a logical address of the data segment, wherein the system is configured to erase all data segments stored in a particular row or a particular column of the first memory section and marked for erasing as soon as the number of data segments marked for erasing in the particular row or the particular column of the first memory section reaches a predetermined threshold.