Patent ID: 9569210
Date: 2017-02-14
CPC Classifications: G06F,H04L

Claim:
1. A hardware processor comprising: multiple mix logic circuitry sections arranged in parallel and each section comprising: permute logic circuitry including parallel inputs coupled to the first and second outputs of each section of the multiple mix logic circuitry to simultaneously receive the first result and the second result from the each section without passage through an additional mix logic circuitry section, and a plurality of parallel output sets, each set to output results of a permute operation on the first result and the second result from a corresponding section according to the hashing algorithm; and control circuitry to couple a first output and a second output of each set to the first input and the second input of each corresponding section of the multiple mix logic circuitry sections, without passage through an additional mix logic circuitry section, wherein the multiple mix logic circuitry sections and permute logic circuitry calculate a hash output value based on input operand data, the first and second results from each section, and the results of the permute operation using less clock cycles in response to the parallel arrangement than otherwise using a serial pipelined arrangement.