Patent ID: 9705620
Date: 2017-07-11
CPC Classifications: G06F,H04J,H04L

Claim:
1. A host integrated circuit, comprising: a clock source; a memory controller; a plurality of endpoints, each endpoint including a first-in-first-out (FIFO) buffer configured to store data words received from the memory controller, wherein each endpoint includes a modulo-n destination counter configured to increment a destination count responsive to a clock signal received from the clock source, wherein n is a positive integer, and wherein each endpoint includes a logic circuit configured to compare the destination count to a source count associated with a first-in one of the data words in the endpoint's FIFO buffer, and wherein the endpoint's FIFO buffer is configured to retrieve the first-in data word responsive to the clock signal received from the clock source when the comparison indicates that a sufficient delay has occurred since the endpoint's FIFO buffer stored the first-in data word, and wherein the clock source, the memory controller, and the plurality of endpoints are integrated onto a semiconductor die, and wherein the endpoints are located on an edge portion of the semiconductor die and the source clock is located closer to the plurality of endpoints on the semiconductor die than to the memory controller.