Patent ID: 9563549
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. A hybrid address mapping method for a system including a host and a data storage device, the data storage device including a memory controller directly connected to the host, a buffer memory, and a nonvolatile memory (NVM), the address mapping method comprising: communicating write data having consecutive logical addresses from the host to the memory controller and storing the write data in a buffer memory, wherein all the logical addresses of the write data are consecutive with one another; using the memory controller, determining whether the write data includes a super sequential block (SSB) and a residual portion in addition to the SSB; upon determining that the write data includes the SSB and the residual portion, using a block mapping mode to map a first logical address among the logical addresses associated with the SSB to a corresponding first physical address, while also using a page mapping mode to map a second logical address among the logical addresses associated with a residual portion of the write data excluding write data in the SSB to a corresponding second physical address; writing the SSB of the write data to the NVM using the block mapping mode; and writing the residual portion of the write data to the NVM using the page mapping mode, wherein the SSB is written such that pages of the SSB are interleaved in a plurality of memory blocks of the NVM using at least two channels.