Patent ID: 9543224
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor package, the method comprising: encapsulating a semiconductor die with a molding compound, wherein a surface of contact pads of the die are coplanar with a surface of the molding compound; applying a seed layer on the die and the molding compound, wherein the seed layer is applied on the surface of the molding compound that is coplanar with the surface of the contact pads on each of the semiconductor dies; applying a resist layer on the seed layer; exposing a first portion of the resist layer, wherein the first portion includes a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL; and exposing a second portion of the resist layer, wherein the second portion includes the second area of the resist layer that includes the electrical communications pathway, wherein the exposed portions of the resist layer are exposed using one or more patterning tools, and the one or more patterning tools include at least one or more lithography tools.