Patent ID: 9536883
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A dual anti-fuse structure comprising: a first channel in a common semiconductor fin adjacent to a first programmable gate comprising a first gate dielectric; a second channel in said common semiconductor fin adjacent to a second programmable gate comprising a second gate dielectric physically separate from said first gate dielectric; a first anti-fuse formed between said first channel and said first programmable gate, said first anti-fuse including a first source and a first drain situated in said common semiconductor fin; and a second anti-fuse formed between said second channel and said second programmable gate, said second anti-fuse including a second source and a second drain situated in said common semiconductor fin, wherein a region of the common semiconductor fin between the first gate dielectric and the second gate dielectric is doped differently from other portions of the common semiconductor fin.