Patent ID: 9627092
Date: 2017-04-18
CPC Classifications: G06F,G11C

Claim:
1. A semiconductor device comprising: a memory core including a data cell region and a parity cell region; a parity calculation logic configured for generating a parity from data received by the parity calculation logic; and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region; and wherein a size of a first data input to the semiconductor device by a write command to the semiconductor device or output from the semiconductor device by a read command to the semiconductor device is smaller than a size of a second data received by the parity calculation logic to generate a first parity, and wherein the second data includes the first data and a third data read from the data cell region before generating the first parity.