Patent ID: 9564221
Date: 2017-02-07
CPC Classifications: G11C,H01L

Claim:
1. A non-volatile memory device comprising: a substrate; a plurality of semiconductor poles formed on the substrate to extend vertically with respect to the substrate; a NAND string having a plurality of memory cells stacked on the substrate along a sidewall of one of the plurality of semiconductor poles, the plurality of memory cells arranged in series, and at least one pair of first selection transistors at a first end of the NAND string adjacent to the plurality of memory cells; a plurality of word lines coupled to the plurality of memory cells of the NAND string; and a first selection line commonly coupled to the at least one pair of first selection transistors of the NAND string, wherein the plurality of memory cells comprise control gate electrodes on the sidewall of the one of the semiconductor poles, and the at least one pair of first selection transistors comprises first gate electrodes on the sidewall of the one of the semiconductor poles, wherein a gate length of each of the control gate electrodes and a gate length of each of the first gate electrodes are substantially equal.