Patent ID: 9614368
Date: 2017-04-04
CPC Classifications: H01L,H02H

Claim:
1. An electrostatic discharge (ESD) protection circuit, comprising: a high power supply rail (VDD) and a low power supply rail (VSS); an active shunt transistor coupled between VDD and VSS, the active shunt transistor including a gate; a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor; and a triggering transistor connected to a gate of the sensing transistor and, upon occurrence of an ESD stress event on the I/O pad, the triggering transistor is to turn ON thereby causing the sensing transistor to turn ON; wherein, if the ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.