Patent ID: 9734103
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. An Information Handling System (IHS), comprising: a plurality of Central Processing Unit (CPU) circuits, wherein each of the CPU circuits comprises a core and at least one of: a memory controller or an input/output (I/O) lane; and a Basic Input/Output System (BIOS) coupled to the plurality of CPU circuits, the BIOS having program instructions stored thereon that, upon execution by the IHS, cause the IHS to: identify a memory controller or I/O lane of a first CPU circuit as belonging to a second CPU circuit; identify the first CPU circuit as not having any cores; and create or modify an Advanced Configuration and Power Interface (ACPI) System Locality Information Table (SLIT) to identify a memory controller of the first CPU circuit as being a remote memory coupled to the second CPU circuit.