Patent ID: 9673820
Date: 2017-06-06
CPC Classifications: H03K

Claim:
1. A chip, comprising: input terminals, a chip interface and chip modules that differ from the chip interface; wherein the chip interface comprises an asynchronous monitor, logic, a sampling unit, a delay unit and a controller; wherein the asynchronous monitor is configured to detect a change in a state of input signals conveyed over the input terminals and to generate a first pulse; wherein the delay unit is configured to generate, at a first delay period after a reception of the first pulse, a first sampling pulse; wherein the logic is configured to decode the input signals, to provide output signals that are indicative of configurations of the chip modules; wherein the sampling unit is configured to sample, in response to the first sampling pulse, a state of the input signals to provide a first sampled state of the input signals; wherein the delay unit is configured to generate, at a second delay period after the generation of the first sampling pulse, a second sampling pulse; wherein the sampling unit is configured to sample, in response to the second sampling pulse, (i) the state of the input signals to provide a second sampled state of the input signals, and (ii) a state of the output signals to provide a first sampled state of the output signals; wherein the controller is configured to (i) compare between the first sampled state of the input signals and the second sampled state of the input signals; and (ii) output the sampled state of the output signals only when the first sampled state of the input signals equals the second sampled state of the input signals.