Patent ID: 9583195
Date: 2017-02-28
CPC Classifications: G11C,H01L

Claim:
1. A method comprising: applying a first voltage potential to a control gate buried below a channel region of a memory cell; applying a second voltage potential to the control gate buried below the channel region, wherein the second voltage potential has a polarity opposite to the polarity of the first voltage potential; storing an electric charge at a storage region of the memory cell below the channel region responsive to the first voltage potential, wherein the storage region is disposed below the channel region and above the control gate, and wherein the storage region is laterally encapsulated by a first well region having a first width and the control gate is laterally encapsulated by a second well region disposed below the first well region and having a second width that is less than the first width; and discharging the electric charge in the storage region stored below the channel region responsive to the second voltage potential.