Patent ID: 9602095
Date: 2017-03-21
CPC Classifications: G06F,H03K,H04L

Claim:
1. A multiplexer circuit which loads N data segments (N is an integer of N<M) led by one of M data segments (M is an integer equal to or larger than two) from a first register storing the M data segments to a second register, the multiplexer circuit comprising: an intermediate register interposed between the first register and the second register and configured to temporarily store L data segments (L is an integer of N<L<M) including the N data segments among the M data segments; a first selection circuit including a plurality of 2:1 multiplexers each of which selectively switches and outputs one data segment from two data segments, and configured to cause each of the 2:1 multiplexers in the first selection circuit to selectively switch and output the data segment to load the L data segments among the M data segments from the first register to the intermediate register; and a second selection circuit including a plurality of 2:1 multiplexers each of which selectively switches and outputs one data segment from two data segments, and configured to cause each of the 2:1 multiplexers in the first selection circuit to selectively switch and output the data segment to load the N data segments among the L data segments from the intermediate register to the second register, wherein the first selection circuit and the second selection circuit are designed based on a value of L for minimizing a circuit amount of the first selection circuit and the second selection circuit, which is calculated according to values of the M and the N.