Patent ID: 9667267
Date: 2017-05-30
CPC Classifications: H03M

Claim:
1. A dither circuit for high-resolution analog-to-digital converters (ADCs), wherein comprising a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit; wherein said settable pseudorandom sequence generator works to generate settable pseudorandom sequence signals uncorrelated to analog input signal Vi, of which n-bit signal is taken as digital dither signal Dd and n is no larger than quantization bit N of the ADC; the digital dither signal Dd is output to said trimmable digital-to-analog conversion circuit and said dither elimination circuit; said trimming module is used to determine certain values of trim signals X said trimmable digital-to-analog conversion circuit is under the control of the trim signals X said dither introduced circuit is used to receive the analog dither signal Ad and analog input signal Vi, then output analog signals to the ADC to be quantized; said dither elimination circuit works to receive digital dither signal Dd and remove dither signals from the output of analog-to-digital converter in ways that obtain the final output DOUT; said settable pseudorandom sequence generator features a signal generation control module being used to set the generated pseudorandom sequence signals.