Patent ID: 9594623
Date: 2017-03-14
CPC Classifications: G06F

Claim:
1. A system on chip (SoC), comprising: multiple functional units; a memory unit comprising a program region and a log region; a processing unit for executing program code and arranged to perform an update operation in response to an update request received or generated by the processing unit, wherein the update operation comprises appending an update enabling record to a sequence of update records in the log region, writing new program code to the program region, and appending an update completion record to the sequence of update records in the log region; a memory control unit connected between the memory unit and the processing unit, for controlling access to the memory unit; and a fault collection unit arranged to assert a fault flag in response to a fault occurring in the SoC, wherein the multiple functional units are connected to the fault collection unit, each one of the multiple functional units configured to signal a fault of the respective functional unit to the fault collection unit; wherein the memory control unit is further connected to the fault collection unit and arranged to disable write access to the log region in response to the fault flag being asserted.