Patent ID: 9608063
Date: 2017-03-28
CPC Classifications: B82Y,H01L

Claim:
1. A method comprising: obtaining a first structure including a base substrate, a plurality of gate structures on the base substrate, sidewall spacers on the gate structures, a plurality of semiconductor fin structures on the base substrate, and a plurality of gaps between the gate structures and the fin structures, and a plurality of vertically stacked nanowires extending through the gate structures, the fin structures and the spacers, each fin structure including an alternating sequence of first and second semiconductor layers comprised respectively of first and second semiconductor materials, the second semiconductor layers being integral with the nanowires, the fin structures being positioned between pairs of the gate structures and parallel to the gate structures, and the nanowires having portions extending within the gaps between the gate structures and the fin structures; chopping the portions of the nanowires within the gaps, and epitaxially growing source/drain regions between the gate structures such that the source/drain regions contact the nanowires extending through the gate structures and the second semiconductor layers of the fin structure.