Patent ID: 9679988
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A method of making an integrated circuit, the method comprising: forming a high k dielectric material layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric material layer; patterning the polysilicon layer to form a polysilicon feature for a passive device; forming an inter-level dielectric (ILD) layer on the semiconductor substrate; removing a portion of the ILD layer to expose the polysilicon feature, wherein removing the portion of the ILD layer to expose the polysilicon feature includes performing a chemical mechanical polishing (CMP) process to etch back the ILD layer to expose the polysilicon feature; and forming a plurality of electrodes embedded in the polysilicon feature, wherein the forming of the plurality of electrodes includes applying an ion implantation process to the polysilicon feature to form the plurality of electrodes.