Patent ID: 9607543
Date: 2017-03-28
CPC Classifications: G09G

Claim:
1. A driving circuit, comprising: at least two driving units arranged in an array and coupled with each other, a first driving unit of the at least two driving units utilized to receive at least one second sub signal of a second driving signal set which is generated by a second driving unit, and to generate a first driving signal set, wherein the second driving unit is a driving unit except the first driving unit in the at least two the driving units; wherein the driving unit comprises: the control unit comprising a first stage transmission signal input terminal, a second stage transmission signal input terminal, a first switch control signal input terminal, a second switch control signal input terminal, and a first stage transmission signal output terminal; the control unit further comprising: the stage transmission signal latch unit comprising a first clock signal input terminal, a third stage transmission signal input terminal, and a latch signal output terminal; the stage transmission signal latch unit further comprising: