Patent ID: 9606891
Date: 2017-03-28
CPC Classifications: G06F,H04L

Claim:
1. An apparatus for tracing data from a data bus in a first clock domain to a trace array in a second clock domain, said apparatus comprising: a change detector to detect a change of the data on the data bus in the first clock domain, the first clock domain operating at a first clock frequency; a trigger responsive to the change detector to send a trigger pulse from the first clock domain to the second clock domain signaling new data available on the data bus, and the trigger pulse being provided to the second clock domain unsynchronized to the second clock domain, the second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency; a pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse from the first clock domain to the second clock frequency of the second clock domain by a meta-stability latch; and a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.