Patent ID: 9679923
Date: 2017-06-13
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a base substrate; and a gate electrode, a gate insulating layer and an active layer arranged on the base substrate in a laminated way, the array substrate further comprising: a passivation layer arranged on the active layer; and a source electrode, a drain electrode, a first electrode and a second electrode arranged on the passivation layer and on a same layer, wherein a first via hole is arranged in the passivation layer, and the first via hole comprises two sloped lateral faces arranged opposite to each other, the first electrode at least partially covers one lateral face of the first via hole, the second electrode at least partially covers the other lateral face of the first via hole, the second electrode is electrically connected to a common electrode lead; and wherein a second via hole is further arranged in the passivation layer, the source electrode and the drain electrode are connected to the active layer through the second via hole, and the first electrode is electrically connected to the source electrode or the drain electrode.