Patent ID: 9589884
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. An integrated circuit device comprising: a first semiconductor substrate; a first transistor set at least partially positioned in the first semiconductor substrate; a first dielectric layer overlapping the first semiconductor substrate and covering a gate electrode of the first transistor set; a first interconnect member at least partially positioned in the first dielectric layer and electrically connected to a terminal of the first transistor set; a second semiconductor substrate; a second transistor set at least partially positioned in the second semiconductor substrate; a second dielectric layer connected to the first dielectric layer, positioned between the first dielectric layer and the second semiconductor substrate, and covering a gate electrode of the second transistor set, wherein the first dielectric layer is positioned between the second dielectric layer and the first semiconductor substrate; a second interconnect member at least partially positioned in the second dielectric layer and electrically connected to a terminal of the second transistor set; a third dielectric layer, wherein the first semiconductor substrate is positioned between the third dielectric layer and the first dielectric layer; a third interconnect member extending through the third dielectric layer and electrically connected to the first interconnect member; a fourth interconnect member extending through the third dielectric layer and electrically connected to the second interconnect member; a fourth dielectric layer overlapping the third dielectric layer, wherein the third dielectric layer is positioned between the fourth dielectric layer and the first semiconductor substrate; and a first passive device at least partially positioned in the fourth dielectric layer.