Patent ID: 9667962
Date: 2017-05-30
CPC Classifications: H04N

Claim:
1. A method of operation within an integrated circuit device having a plurality of processing lanes, the method comprising: determining a first number of packed data words among one or more first packed data words associated with a first processing lane of the plurality of processing lanes; associating the first number of packed data words with a first used field of the first processing lane, wherein the first used field indicates the first number of packed data words in the first processing lane; determining a second number of packed data words among one or more second packed data words associated with a second processing lane of the plurality of processing lanes; associating the second number of packed data words with a second used field of the second processing lane, wherein the second used field indicates the second number of packed data words in the second processing lane; generating a first sub-stream of data, including the one or more first packed data words, in the first processing lane of the plurality of processing lanes; generating a second sub-stream of data, including the one or more second packed data words, in the second processing lane of the plurality of processing lanes, wherein the first and second sub-streams are of variable lengths; and outputting at least the first and second sub-streams as a single bitstream, wherein said outputting at least the first and second sub-streams includes: