Patent ID: 9589974
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A nonvolatile semiconductor memory device comprising: a semiconductor layer provided in a memory cell region and a peripheral region at a periphery of the memory cell region; an interlayer insulating film provided above the semiconductor layer; a plurality of element separating regions separating the semiconductor layer into a plurality of semiconductor regions in the memory cell region; a gate electrode provided on one of the plurality of semiconductor regions via a gate insulating film in the memory cell region; a plurality of first contact electrodes extending in a first direction from the semiconductor layer toward the interlayer insulating film in the memory cell region, and one of the first contact electrodes being connected to the one of the plurality of semiconductor regions in the memory cell region; a plurality of first wiring layers extending in a second direction crossing the first direction in the memory cell region, and one of the first wiring layer layers being connected to an upper end of the one of the first contact electrodes in the memory cell region; a second contact electrode extending in the first direction from the semiconductor layer toward the interlayer insulating film in the peripheral region, and the second contact electrode being connected to the one of the plurality of semiconductor regions in the peripheral cell region; and a second wiring layer extending in a third direction crossing the first direction in the peripheral region, the second wiring layer being electrically connected to an upper end of the second contact electrode in the peripheral cell region, the second wiring layer having an upper end higher than the upper end of the first contact electrodes, the second wiring layer having a lower end lower than the upper end of the first electrodes, wherein a ratio of a first width of a first wiring layer lower end of the one of the first wiring layers cut perpendicularly through the first wiring layer lower end to a second width of a first contact electrode upper end of the one of the first contact electrodes cut perpendicularly through the first contact electrode upper end is smaller than a ratio of a third width of a second wiring layer lower end of the second wiring layer cut perpendicularly through the second wiring layer lower end to a fourth width of a second contact upper end of the second contact electrode cut perpendicularly through the second contact upper end.