Patent ID: 9704982
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a Group III nitride semiconductor lamination structure including a hetero-junction; an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure; a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion; a gate electrode formed on the gate insulating film in the gate opening portion; a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and a conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the conductive layer electrically connected to the source electrode.