Patent ID: 9575860
Date: 2017-02-21
CPC Classifications: G06F,G11C

Claim:
1. A method for testing functionality of memory blocks of at least one random access memory (RAM) circuit, comprising: receiving, by a testing circuit, a signal to initiate the testing, the testing circuit connected, via a bus, to a processor and the at least one RAM circuit, the at least one RAM circuit including at least a first memory block of the memory blocks; determining, by the testing circuit, that the bus is not reserved; reserving, by the testing circuit, the bus, the reserving including: reading, by the testing circuit, first application data from the first memory block to the testing circuit via the bus; storing, by the testing circuit, the first application data to a memory associated with the testing circuit; writing, by the testing circuit, at least one first data pattern to the first memory block via the bus; reading, by the testing circuit, at least one second data pattern from the first memory block via the bus; verifying, by the testing circuit, functionality of the at least one RAM circuit based on the at least one first data pattern and the at least one second data pattern; writing, by the testing circuit, the first application data from the memory associated with the testing circuit to the first memory block via the bus, if the verifying indicates the functionality of the first memory block of the at least one RAM; and releasing, by the testing circuit, the bus for use by the processor prior to testing a second memory block of the memory blocks of the at least one RAM circuit.