Patent ID: 9646958
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: a boundary region comprising an input/output circuit; a core area comprising functional elements of the integrated circuit located exclusively in the core area, the boundary region and the core area defining an edge separating, in plan view, the boundary region and the core area; a plurality of transistors disposed in the core area and adjacent to the edge, the plurality of transistors being functional elements of the integrated circuit; and a plurality of first gate dummy structures disposed in the boundary region and adjacent to the edge, wherein each transistor of the plurality of transistors comprises a channel having a channel width direction substantially perpendicular to the edge, each channel of the plurality of transistors is aligned with a corresponding first gate dummy structure of the plurality of first gate dummy structures along the channel width direction without an intervening dummy structure therebetween, each element of the boundary region adjacent the edge is a first gate dummy structure of the plurality of first gate dummy structures; and a plurality of second gate dummy structures, wherein an entirety of each second gate dummy structure of the plurality of second gate dummy structures is farther from the edge than each first gate dummy structure of the plurality of first gate dummy structures, and each second gate dummy structure of the plurality of second gate dummy structures and each first gate dummy structure of the plurality of first gate dummy structures is aligned with a channel of a corresponding transistor of the plurality of transistors in an alternating fashion.