Patent ID: 9727674
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A method of operating a computerized simulator including a memory that stores instructions and a processor that executes the instructions, while compensating for delay from at least one of digital-to-analog signal conversion and analog-to-digital signal conversion for synchronizing digital and analog signals, the method comprising: generating, using the processor of the computerized simulator, a standard delay format (SDF) file and one of a rising time and a falling time of an analog signal in the digital-to-analog signal conversion or the analog-to-digital signal conversion, using a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and generating an event to be used in a simulation, using a first driving cell according to a compensated interconnect delay description.