Patent ID: 9614550
Date: 2017-04-04
CPC Classifications: H03M

Claim:
1. A circuit for parallel BCH coding, comprising: a plurality of P input branches, wherein P is a number indicative of a degree of parallelism, each of said input branches including: a register; and a Galois field adder connected to said P input branches and said register; wherein input sequences {m(p−1), m(p−2), . . . , m(0)} in a current period in sequence corresponding to output upper bits of a previous period of said register separately are input to each of the P XOR gates, an output of each of the P XOR gates is output to a corresponding one of P selectors, P constant-multinomials {(x wherein an output of the previous period of said register is shifted in P bits towards the upper bits to serve as a second output; wherein the first and second outputs are summed in the Galois field adder, and the sum is output to said register to serve as an output of the current period of said register; wherein a specific number of operations are performed on said P input branches, said Galois field adder and said register to obtain final code output; and wherein said specific number is determined by a length K, wherein K is a number indicative of length of input information data and the degree of parallelism P, and said specific number is the minimum integer not less than K/P.