Patent ID: 9558805
Date: 2017-01-31
CPC Classifications: G11C

Claim:
1. A memory module, comprising: a memory device including a plurality of memory cell rows; and a control circuit configured to group the plurality of memory cell rows into a plurality of groups according to a data retention time of each of the plurality of the memory cell rows, set a plurality of refresh time regions according to the number of the groups, the plurality of refresh time regions being periodically repeated, and refresh the plurality of groups during each of the plurality of refresh time regions, wherein when a filter table corresponds to a predetermined refresh time region of the plurality of refresh time regions, a first group whose address does not match an address stored in the filter table is not refreshed during the predetermined refresh time region, wherein the refresh time regions include first through k-th refresh time regions based on the data retention time, and the control circuit is configured to generate a refresh enable signal that refreshes all of the memory cell rows in all of the groups when a refresh time region signal indicates the first refresh time region, wherein k is an integer equal to or greater than two.