Patent ID: 9711484
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: a semiconductor die having a major surface and including a conductive pad disposed adjacent and overlapping the major surface, the conductive pad having a first bonding surface spaced apart from the major surface and a sidewall bonding surface extending from the first bonding surface toward the major surface; a lead including a first region adjacent the semiconductor die and a second region laterally extending away from the first region, wherein the first region has a lead sidewall surface laterally spaced inward from the sidewall bonding surface of the conductive pad, and wherein the first region of the lead faces and overlaps the first bonding surface of the conductive pad; a conductive layer affixed to the first bonding surface of the conductive pad, affixed to the sidewall bonding surface of the conductive pad, affixed to the first region, and affixed to the lead sidewall surface thereby electrically connecting the conductive pad to the lead, wherein a first portion of the conductive layer is interposed between the first bonding surface of the conductive pad and the first region of the lead; and an encapsulant covering the semiconductor die and at least portions of the lead, wherein: the first region of the lead is thinner than the second region of the lead; the first region includes a first region first surface and a first region second surface opposite to the first region first surface; the lead sidewall surface extends between the first region first surface and the first region second surface; the second region includes a second region first surface contiguous with the first region first surface and a second region second surface opposite to the second region first surface; the conductive layer comprises a continuous conductive layer affixed to the first region first surface, the lead sidewall surface, the first region second surface, and the second region second surface; the continuous conductive layer affixed to the first region second surface is covered by the encapsulant; and the continuous conductive layer affixed to the second region second surface is exposed to the outside of the encapsulant.