Patent ID: 9613970
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A semiconductor nonvolatile memory element, comprising: a semiconductor substrate; a well region of a first conductivity type formed in the semiconductor substrate; a heavily doped source region and a first heavily doped drain region which are formed in the well region so as to be apart from each other, and each of which contains high-concentration impurities of a second conductivity type; a first gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region so as to be adjacent to the heavily doped source region; a second gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region so as to be adjacent to the first heavily doped drain region; a second heavily doped drain region of the second conductivity type formed apart from the heavily doped source region, the second heavily doped drain region including a region under the second gate insulating film and being formed in a region that overlaps the first heavily doped drain region; a first lightly doped drain region of the second conductivity type formed apart from the heavily doped source region, the first lightly doped drain region including a region under the first gate insulating film and the region under the second gate insulating film and being formed in a region that overlaps the first heavily doped drain region and the second heavily doped drain region; a channel impurity region of the second conductivity type formed under the first gate insulating film between the heavily doped source region and the first lightly doped drain region; a floating gate electrode that is made of polycrystalline silicon containing high-concentration impurities, and is formed on the first gate insulating film and the second gate insulating film; a third gate insulating film formed on the floating gate electrode; and a control gate electrode that is made of polycrystalline silicon containing high-concentration impurities, formed on the third gate insulating film, wherein the second gate insulating film has a thickness that is larger than a thickness of the first gate insulating film, and wherein the well region includes the heavily doped source region, the first heavily doped drain region, the second heavily doped drain region, the first lightly doped drain region, and the channel impurity region, and is formed to a depth that is larger than depths of the heavily doped source region, the first heavily doped drain region, the second heavily doped drain region, the first lightly doped drain region, and the channel impurity region.