Patent ID: 9659119
Date: 2017-05-23
CPC Classifications: G06F

Claim:
1. A design method for adjusting clock skews, the method comprising: generating, by a clock generator, a clock signal; supplying, by a plurality of clock buffers, the clock signal to a plurality of circuit sections that operate in synchronization with the clock signal; separating, by a processor, each of triangular-wave currents which flow through the plurality of circuit sections into a plurality of frequency components; setting skew values of the clock signal which reaches the plurality of circuit sections; and performing, by the processor, by changing the skew values, repetition of calculating a combined amplitude by combining, with respect to each of the frequency components, corresponding ones of the frequency components of the triangular-wave currents which flow through the plurality of circuit sections and finding dependence of the combined amplitude on a skew, wherein a skew value at the time of a first combined amplitude calculated by combining the frequency components of the triangular-wave currents corresponding to a frequency component to be suppressed among the plurality of frequency components being smaller than a first value is selected to design a clock tree; wherein the processor obtains plural harmonic frequencies by separating the triangular-wave currents which flow through the circuit sections, selects a target frequency having overlapping frequency bands in a same time period, from among the plural harmonic frequencies, and combines a sine-wave of the triangular-wave currents according to the target frequency.