Patent ID: 9620244
Date: 2017-04-11
CPC Classifications: G11C

Claim:
1. A computer-implemented method comprising: checking one or more memory cells for a malfunction; creating a relational data structure comprising a plurality of interlinked nodes and a root node such that each test parameter configuration of a set of test parameter configurations for which a malfunction has been detected is represented by a path, wherein test parameters associated with the test parameter configurations are assigned to one or more nodes of the plurality of interlinked nodes of the path according to a defined order starting from the root node, wherein each path is assigned a detected bit fail count for the path's respective test parameter configuration; combining one or more segments of the relational data structure according to a predefined rule for obtaining one or more test groups; creating a representation of the bit fail counts of the respective test groups; applying a filter to the relational data structure including the test groups in order to identify test parameter configurations categories to be further analyzed; storing, for each test parameter configurations for which a malfunction is detected, a bit fail map comprising information about a spatial distribution pattern of the malfunctioning memory cells; and determining a spatial distribution pattern of memory cells to be further analyzed using the parameter configuration categories to be further analyzed and the bit fail map.