Patent ID: 9652228
Date: 2017-05-16
CPC Classifications: G06F,G11C

Claim:
1. A non-volatile memory device, comprising: a memory core to store data, the data being output from the memory core according to an external clock signal; an input buffer to receive the external clock signal and to provide an input clock signal; a synchronization circuit to receive the input clock signal and to provide an output clock signal, the synchronization circuit synchronizing the output clock signal to the external clock signal, the synchronization circuit including a delay circuit; a data strobe output buffer to receive the output clock signal and to provide a data strobe signal indicating the data output from the memory core is available for access, the data strobe signal having a signal delay configurable relative to the external clock signal; a clocked circuit element coupled to the memory core to receive the data output from the memory core and the output clock signal and to output the data in synchronism with the output clock signal; and a delay control circuit to provide a delay control signal to the delay circuit, the delay circuit being responsive to the delay control signal, to modify the signal delay of the data strobe signal.