Patent ID: 9608610
Date: 2017-03-28
CPC Classifications: G06F,H03K,H03L

Claim:
1. A method of controlling a clock signal having an operating frequency that is generated by a clock source associated with a microprocessor device, the method comprising: applying the clock signal to an input of at least one delay element having a non-linear capacitive load coupled to an output of the at least one delay element; applying a first bias voltage to an input of the non-linear capacitive load and generating a first capacitance; applying a first delay to the received clock signal propagating through the at least one delay element based on the generated first capacitance and a first output resistance corresponding to the at least one delay element; decreasing the first bias voltage to the input of the non-linear capacitive load and generating a reduced first capacitance during a voltage droop occurring on a supply voltage of the microprocessor; increasing the first delay to the received clock signal propagating through the at least one delay element during the voltage droop based on the reduced first capacitance and an increase in the first output resistance; generating a frequency correction signal based on the increasing of the delay to the received clock signal; and applying the frequency correction signal to the clock source for reducing the operating frequency and maintaining a frequency guardband for the clock signal during the voltage droop.