Patent ID: 9564195
Date: 2017-02-07
CPC Classifications: G11C

Claim:
1. An address comparator circuit, comprising: a first determination unit suitable for activating a first control signal when a first address corresponding to a previous read command is identical with a second address corresponding to a current read command; a second determination unit suitable for activating a second control signal when the previous and current read commands are consecutively inputted to the address comparator circuit with an interval of a specific number of clock cycles or less; and a blocking signal generation unit suitable for generating a blocking signal that blocks data transmission between a memory array and an external device based on the first and the second control signals when the first address is identical with the second address, wherein the blocking signal is deactivated when a flag signal is activated even though the first address is identical with the second address, the flag signal being activated when the interval of the consecutive previous and current read commands exceeds the specific number of clock cycles.