Patent ID: 9659604
Date: 2017-05-23
CPC Classifications: G11C

Claim:
1. A memory system comprising: a multi-time programmable (MTP) bit cell array, with each multi-time programmable bit cell of the array comprising: a wordline conductor (WL) programmable for activating MTP bit memory cell, each of the first, second and third FET transistors of each the MTP bit memory cell including a respective gate terminal for connection with the wordline conductor (WL) element; a sense amplifier for sensing received signals; a multiplexor for selecting one out of many data output signals, the multiplexor responsive to control signals for activating the first switch device and third switch device to enable sensing, by the sensing amplifier, of voltage values representing a first stored information bit on the first bit line (True) conductor and first complement bit line conductor, or responsive to control signals for activating the second switch and fourth switch devices to enable sensing, by the sensing amplifier, of voltage values representing a second stored information bit on the second bit line (True) conductor and second complement bit line conductor.