Patent ID: 9608611
Date: 2017-03-28
CPC Classifications: H03K

Claim:
1. A phase interpolator implemented in an integrated circuit to derive a clock signal, the phase interpolator comprising: a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; a second active inductor load coupled to the second output node, wherein each of the first active inductor load and the second active inductor load comprises a load transistor and a resistor coupled between a gate and a current node of the load transistor; and for each of the first active inductor load and the second active inductor load, a capacitor coupled between a reference voltage and the date of the load transistor.