Patent ID: 9564434
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate; a first semiconductor layer; a second semiconductor layer, the first and second semiconductor layers patterned, the first and second semiconductor layers sequentially formed on the substrate; an isolation layer formed on the substrate, wherein the isolation layer has a top surface located between top and bottom surfaces of the first semiconductor layer to define a fin comprising the patterned first and second semiconductor layers and the length dimension of the fin extending in a first direction above the isolation layer; and a gate stack formed on the isolation layer and the length dimension of the gate stack extending in a second direction crossing the first direction to intersect the length dimension of the fin, wherein the first semiconductor layer is recessed relative to the second semiconductor layer so as to define a lateral recess, the length dimension of the lateral recess extending in the second direction, and the semiconductor device further comprises a body spacer formed in the lateral recess.