Patent ID: 9659599
Date: 2017-05-23
CPC Classifications: G11C,H01L

Claim:
1. A multiple port memory cell for a data storage device, the multiple port memory cell comprising: a diffusion layer of a semiconductor stack having a plurality of transistors; a first metallization layer of the semiconductor stack having a first conductor connected to a first transistor from among the plurality of transistors, the first conductor representing a write port of the multiple port memory cell; a second metallization layer of the semiconductor stack, disposed above the first metallization layer, having a second conductor connected to a second transistor from among the plurality of transistors, the second conductor representing a first read port of the multiple port memory cell; and a third metallization layer of the semiconductor stack, disposed above the second metallization layer, having a third conductor connected to a third transistor from among the plurality of transistors, the third conductor representing a second read port of the multiple port memory cell.