Patent ID: 9570199
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A method of memory module testing comprising: accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic; determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range; determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range; and accessing the first memory module with a second stress test in response to determining that the first traffic-to-temperature parameter is outside the first traffic-to-temperature range.