Patent ID: 9564522
Date: 2017-02-07
CPC Classifications: B82Y,H01L

Claim:
1. A method of fabricating a nanowire semiconductor device, the method comprising: forming a plurality of vertically stacked nanowires above a substrate, each of the nanowires comprising a discrete channel region disposed in the nanowire; forming a gate electrode stack surrounding the discrete channel regions of the plurality of vertically stacked nanowires; forming a pair of non-discrete source and drain regions on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires, each of the non-discrete source and drain regions having an uppermost surface, sidewall surfaces and a bottommost surface; and subsequent to forming the pair of non-discrete source and drain regions, forming a first conductive contact on and continuous around the uppermost surface, the sidewall surfaces and the bottommost surface of the non-discrete source region, and forming a second conductive contact on and continuous around the uppermost surface, the sidewall surfaces and the bottommost surface of the non-discrete drain region.