Patent ID: 9726691
Date: 2017-08-08
CPC Classifications: G01R,H01L

Claim:
1. A method for electrically testing an integrated circuit (IC), comprising: forming a plurality of through substrate vias (TSV) through an entire thickness of the integrated circuit (IC) chip, each TSV electrically connecting a first surface of the IC chip to a second surface on an opposite side of the IC chip, wherein an individual solder connection formed on the second surface of the IC chip connects to a corresponding individual TSV of said plurality via a respective conductor; forming a respective pattern of micro-solder connections around a respective TSV on the first surface of the IC chip, each said respective pattern of micro-solder connections of the first surface sharing an assigned common power/ground signal grid or input/output signal grid with the corresponding TSV, wherein a center of an individual micro-solder connection in the pattern is separated from a center of another individual micro-solder connection by a distance of approximately 62 μm, and wherein the respective pattern of micro-solder connections allows the IC chip to be electrically tested by directly contacting the micro-solder connections with a single electrical probe tip without the need for a testing interposer, wherein the single electrical probe tip comprises: