Patent ID: 9734268
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. A system to implement an integrated circuit design, the system comprising: a memory configured to store a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries; and a processor configured to identify candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, to select redistribution cycle boundaries among the candidate cycle boundaries, to generate a modified timing database based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and to perform power recovery using the modified timing database to reduce power at one of more of the redistribution cycle boundaries; and a physical implementation of the integrated circuit design resulting from the power recovery using the modified timing database.