Patent ID: 9653623
Date: 2017-05-16
CPC Classifications: H01L,Y02P

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: forming a first conductive pattern structure in a first insulating interlayer formed on a first substrate, a portion of the first conductive pattern structure protruding upwardly from the first insulating interlayer; forming a first bonding insulation layer pattern on the first insulating interlayer, the first bonding insulation layer pattern covering the portion of the first conductive pattern structure protruding from the first insulating interlayer; forming a first recess on the first bonding insulation layer pattern; forming a first adhesive pattern containing a polymer to fill the first recess; forming a second conductive pattern structure in a second insulating interlayer formed on a second substrate, a portion of the second conductive pattern structure protruding upwardly from the second insulating interlayer; forming a second bonding insulation layer pattern on the second insulating interlayer, the second bonding insulation layer pattern covering the portion of the second conductive pattern structure protruding from the second insulating interlayer; forming a second recess on the second bonding insulation layer pattern; forming a second adhesive pattern containing a polymer to fill the second recess; and melting adhesive in the first adhesive pattern and the second adhesive pattern; and bonding the first and second substrates with each other so that the first conductive pattern structure and the second conductive pattern structure are in contact with each other.