Patent ID: 9570170
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A memory device comprising: a memory cell array comprising a plurality of memory cells arranged respectively in regions where a plurality of first signal lines cross a plurality of second signal lines; and a decoder comprising a plurality of line selection switch units connected respectively to the plurality of first signal lines; wherein each of the plurality of line selection switch units applies a bias voltage to a first signal line corresponding to each of the plurality of line selection switch units in response selectively to a first switching signal and a second switching signal, and wherein a first switch operating in response to the first switching signal and a second switch operating in response to the second switching signal, the first switch and the second switch are first conductive type transistors, and wherein the first switch is turned on in response to a first voltage of the first switching signal and the second switch is turned on in response to a second voltage of the first switching signal, voltage levels of the first voltage and the second voltage being different from each other.