Patent ID: 9576661
Date: 2017-02-21
CPC Classifications: G11C

Claim:
1. A memory device, comprising: an SRAM cell that stores a logic state; a first MTJ having a first terminal and a second terminal coupled to a storing node; a second MTJ having a first terminal and a second terminal, wherein the first terminal of the second MTJ is coupled to the storing node, and wherein the first and second MTJs are characterized as being programmed to a first resistance state by flowing current from the first terminal to the second terminal and to a second resistance state, different from the first resistance state, by flowing current from the second terminal to the first terminal; a storing circuit coupled to the storing node, the SRAM cell, and a non-volatile word line, wherein the storing circuit couples the logic state of the SRAM cell to the storing node during a store mode, wherein the storing circuit comprises: wherein, during the store mode, the logic state of the SRAM cell is stored in the first and second MTJs by applying a storing voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity during a first time period of a store operation and a second polarity during a second time period of the store operation.