Patent ID: 9612841
Date: 2017-04-04
CPC Classifications: G06F

Claim:
1. A method involving an intelligent packet data register file, wherein the intelligent packet data register file comprises a plurality of slice portions, the method comprising: (a) storing bytes of packet data in a packet buffer memory; (b) supplying a start byte value and a number of bytes required value B to each of the slice portions, wherein the number of bytes required value B indicates a number of bytes of the packet data that is required for execution of an instruction on a processor of which the intelligent packet data register file is a part, and wherein the start byte value is a byte number of a first byte of the bytes of packet data required for execution of the instruction; (c) determining, in each slice portion, a number of bytes that the slice portion is responsible for supplying to an execute stage of the processor so that the processor can successfully execute the instruction; (d) determining, in each slice portion, based at least in part upon the start byte value and the number of bytes required value B, whether the slice portion is storing all the bytes that the slice portion is responsible for supplying to the execute stage; (e) issuing, from each slice portion, a fetch request to fetch any bytes that the slice portion is responsible for supplying as determined in (c) but that the slice portion is not storing as determined in (d), wherein any fetch request issued in (e) is communicated to the packet buffer memory, wherein the slice portions make the determinations of (c) and (d) independently of one another, and wherein the slice portions issue fetch requests independently of one another; (f) merging any valid bytes of packet data output from the slice portions into a single value that includes all the valid bytes as output by all the slice portions, and supplying the single value at one time to the execute stage; and (g) using the single value in the execute stage to complete execution of the instruction, wherein each slice portion can store at most A bytes of packet data, and wherein the number of bytes required value B can be less than A, equal to A, or more than A depending on the instruction being executed, wherein steps (a) through (q) are performed by a processor integrated circuit.