Patent ID: 9542251
Date: 2017-01-10
CPC Classifications: G06F,H04L

Claim:
1. An apparatus, comprising: a communication bridge device including a bus interface circuit configured to couple to a service processor via a serial bus and first and second sideband signal lines for the serial bus, wherein the serial bus is a low pin count bus that has less than 10 signal lines, wherein the serial bus includes a set of address/data signal lines, a clock signal line, a reset signal line, and a cycle delimiter signal line, and wherein the serial bus is compatible with an Industry Standard Architecture (ISA) bus; wherein the bus interface circuit is further configured to use the first and second sideband signal lines to communicate error information in response to detecting an error condition on the serial bus, wherein the bus interface circuit is configured to communicate parity error information on the first and second sideband signal lines in response to detecting a parity error condition on the serial bus; and wherein the communication bridge device is configured to convey at least a portion of the parity error information during an addressing portion of a response to a bus transaction corresponding to address bits that are unused by the response to the bus transaction.