Patent ID: 9715572
Date: 2017-07-25
CPC Classifications: G06F

Claim:
1. A method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, the method comprising: providing, using a processor, boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the plurality of macros being part of a unit and the boundary conditions provided to each of the plurality of macros including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros; performing macro-level physical synthesis at each of the plurality of macros of the unit; providing feedback to the unit level controller at a hierarchical level of the unit corresponding with the plurality of macros based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks; performing pin placement at the unit level controller at the hierarchical level of the unit based on the proposed new locations in the feedback from each of the plurality of macros to determine locations for the movable pins; and iteratively performing the providing the boundary conditions, the performing the macro-level physical synthesis, the providing the feedback, and the performing the pin placement at the hierarchical level of the unit, and indicating different ones of the pins as the movable pins at each iteration, wherein the performing the pin placement is performed in a physical implementation of the chip design in an integrated circuit following the last iteration.