Patent ID: 9548750
Date: 2017-01-17
CPC Classifications: G04F,H03L,H03M

Claim:
1. A circuit comprising: a controllable oscillator configured to generate an output signal based on a control signal; an input signal processing circuit configured to receive a reference signal and generate a sequence of digital values indicating a phase relation between the reference signal and the output signal or a signal derived from the output signal; a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, wherein each processed value is based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values; and a noise cancellation circuit coupled between the input signal processing circuit and the controllable oscillator and configured to compensate a phase shift caused by a switching of the divider, wherein the noise cancellation circuit comprises a digital integrator configured to integrate values indicative of an incremental phase shift to obtain a value indicative of an over-all phase shift.