Patent ID: 9589636
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A device comprising: a plurality of non-volatile memory elements connected in series, wherein a first of the non-volatile memory elements is connected to a reference node, the plurality of non-volatile memory elements being operable to: a first conducting element configured to connect the reference node to a charged bit line when the device is in the second mode and disconnect the reference node to the charged bit line when the device is in the first mode: and a second conducting element to connect a voltage source to a first terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element during a write operation, the second conducting element to apply, at least in part, a first programming signal across the first and second terminals of the first non-volatile memory element and apply, at least in part, a second programming signal across the first and second terminals of the second non-volatile memory element during the write operation.