Patent ID: 9741819
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method for fabricating a transistor comprising: providing a dummy gate on a substrate; forming an interlayer dielectric layer on the substrate and sidewall surfaces of the dummy gate, wherein the interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate; forming a mask layer on the top surface of the interlayer dielectric layer; using the mask layer as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom; and removing the trench footing by applying a dry etching process; wherein the dry etching process is a synchronized pulse etching process using a source power and a bias power, and the source power and the bias power in a pulse mode have a same frequency and a same phase.