Patent ID: 9698088
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: a first substrate; a first semiconductor chip mounted on the first substrate; a second substrate disposed on the first substrate, the second substrate including a central portion and a peripheral portion around the central portion; a plurality of first connection members attached to the peripheral portion of the second substrate and configured to electrically connect the first and second substrates; and a plurality of second connection members attached to the peripheral portion of the second substrate and configured to electrically connect the first and second substrates, wherein the first semiconductor chip is under the central portion of the second substrate, wherein only the first connection members are adjacent to a side of the central portion, wherein only the second connection members are adjacent to a vertex of the central portion, wherein each of the first connection members includes a first supporter and a first fusion conductive layer surrounding the first supporter, and wherein each of the second connection members consists of a uniform conductive material.