Patent ID: 9741641
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a die pad that includes a first main surface and a second main surface located on an opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that includes a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on an opposite side of the surface, and is mounted on a chip mounting area of the first main surface of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire so that a part of the lead and the second main surface of the die pad are exposed at least partially, wherein on the second main surface of the die pad, a stepped part that ranges to a side surface of the die pad and a groove part arranged along the stepped part of the second main surface of the die pad are provided in a plan view, and wherein, in a cross section view, a depth of the groove part is deeper than a depth of the stepped part in a thickness direction of the die pad.