Patent ID: 9721828
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A process of forming an integrated circuit, comprising the steps: providing a partially processed integrated circuit wafer with shallow trench isolation (STI) trenches wherein the STI trenches lie between active geometries and wherein the active geometries are covered with a silicon nitride layer; loading the partially processed integrated circuit wafer into an oxide CVD deposition chamber with a sequential sputter CVD deposition/sputter etch/sputter CVD deposition process capability; turning on oxide deposition gases and stabilizing a temperature and pressure wherein the oxide deposition gases include SiH4, O2, and H2 and a carrier gas; turning on a plasma and depositing a first layer of STI oxide with a substrate bias turned off; turning on the substrate bias and filling the STI trenches with a first portion of a second layer of STI oxide; turning off the SiH turning on the SiH repeating the steps of depositing the second layer of STI oxide and sputter etching until the shallow trench isolation trenches are filled with the second layer of STI dielectric; turning off the substrate bias and depositing a third layer of STI oxide wherein the third layer of STI oxide is a capping layer on the second layer of STI oxide; after depositing the third layer of STI oxide, removing the wafer from the CVD chamber; and planarizing the first, second, and third layers of STI oxide using chemical mechanical polish to remove the first, second and third layers of STI oxide from the silicon nitride layer and forming a planar surface on the integrated circuit.