Patent ID: 9727464
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A computer system for providing cache coherency in a processor system comprising: a first plurality of communicatively coupled nodes, each node comprising a respective number of communicatively coupled central processor (CP) clusters, each CP cluster comprising a respective third plurality of processors communicatively coupled to a respective cache system, the processor system configured to perform a multi-tiered cache coherency protocol, the multi-tiered cache coherency protocol consisting of any one of local cache coherency operations within a node, and global cache coherency operations between nodes, each node further comprises a storage control (SC) function, the SC function comprising an all-inclusive directory and a fabric control interface (FCI) function, the all-inclusive directory having an indication of all valid cache lines of a respective node, wherein cache coherency operations consist of any one of loading the cache line and updating, by one or more nodes of the processor system, coherency state of the cache line, the computer system comprising: based on receiving a coherency request, from a selected processor, for access to a cache line by a selected processor of a selected node, the selected processor not having the requested access to the cache line in the selected processor's private cache, determining which multi-tiered cache coherency operations to perform the determining comprising: based on determining that the coherency request can be resolved by the selected node alone, performing a) and b) comprising: a) performing local cache coherency operations for the cache line only at the selected node; and b) suppressing global cache coherency operation for the cache line from the selected node to all other nodes; and based on determining that the coherency request can not be resolved by the selected node alone, performing c) and d) comprising: c) performing global cache coherency operations from the selected node for the cache line by broadcasting the coherency request to other nodes; and d) based on determining at another node that the broadcast coherency request is for a cache line that is not valid in any cache of the another node, suppressing, by the another node, a local cache coherency operation at the another node for the cache line; and based on a respective CP cluster of a node having most recently installed a respective cache line, designating the respective CP cluster as a local intervention master (LIM) for cache lines of the node, the LIM being a local point-of-coherency for cache lines of the respective node; and based on a node having most recently installed a respective cache line, designating an SC function at a node of the plurality of nodes as the global intervention master (GIM), the GIM being a global point-of-coherency for cache lines for all nodes of the processor system.