Patent ID: 9703164
Date: 2017-07-11
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising a data line and a gate line arranged crossly, a thin film transistor being arranged in vicinity of a cross position of the data line and the gate line, the thin film transistor comprising a gate and a source, the gate being connected with the gate line; wherein the source is connected with the data line, wherein an orthographic projection of the source on a base substrate of the array substrate partly overlaps with an orthographic projection of the gate on the base substrate of the array substrate, and wherein the orthographic projection of the source on the base substrate of the array substrate is in a U shape, wherein the U shape comprises two end portions and a middle portion located between the two end portions, wherein the two end portions overlap with the orthographic projection of the gate on the base substrate of the array substrate; and wherein the middle portion does not overlap with the orthographic projection of the gate on the base substrate of the array substrate.