Patent ID: 9542101
Date: 2017-01-10
CPC Classifications: G06F

Claim:
1. A data storage system, comprising: a cache memory; and a controller comprising processing logic that is configurable to define and manage data transfers to and from at least one logical volume to be exposed to a host device, the data transfers as managed by the controller including data aligned for a single write operation to a stride in a defined array of N solid state storage modules, where N is a positive integer that is greater than or equal to 2, each stride comprising a set of two or more arranged stripes and being capable of being transferred by the controller to the N solid state storage modules in a single write operation, each stripe comprising data bits and parity bits generated from the data bits, the defined array having a specifically-defined layout in which the stripes are distributed across the N solid state storage modules in a manner dictated by the layout, wherein the data to be transferred by the controller is collected in the cache memory until the data present in the cache memory meets or exceeds the storage capacity of the stride, and wherein when the data present in the cache memory meets or exceeds the storage capacity of the stride, the controller causes the data present in the cache memory to be transferred to the N solid storage modules in a single write operation in accordance with the specifically-defined layout of the defined array.