Patent ID: 9583512
Date: 2017-02-28
CPC Classifications: G02F,H01L

Claim:
1. An array substrate comprising: a plurality of data lines and a plurality of first gate lines, wherein a plurality of first pixel units and a plurality of second pixel units are both formed by intersecting the plurality of data lines with the plurality of first gate lines which are electrically insulated from the data lines; and a plurality of second gate lines disposed parallel to the plurality of data lines, wherein the plurality of second gate lines are electrically connected to the first gate lines, respectively; wherein a first TFT is disposed in each one of the first pixel units, and a second TFT is disposed in each one of the second pixel units, the first TFT and the second TFT each comprise a gate, a second electrode, a first electrode and an active layer, and the second gate lines, the data lines, as well as a metal layer in which the first electrode and the second electrode are disposed, are arranged in the same layer; wherein the first electrode of the first TFT is disposed at one side of the second gate line, the gate and the second electrode of the first TFT are disposed at the other side of the second gate line, a projection of the second gate line on the active layer of the first TFT is partly overlapped with the active layer of the first TFT, the gate, the first electrode, the second electrode and the active layer of the second TFTs are disposed at the same side of the second gate line, and each one of the first electrodes of the first TFT and the second TFT is electrically connected to the adjacent data line.