Patent ID: 9640549
Date: 2017-05-02
CPC Classifications: G11C,H01L

Claim:
1. A vertical memory device, comprising: a substrate; a plurality of channels extending in a first direction which is vertical to a top surface of the substrate; a plurality of gate lines stacked in the first direction to be spaced apart from each other and extending in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels, wherein the plurality of gate lines form a stepped structure in which, for a plurality of vertical levels, all gate lines of a first set of consecutive gate lines at a first vertical level are shorter than all gate lines of a second set of consecutive gate lines at a second vertical level lower than the first vertical level, the second set of consecutive gate lines vertically overlapping the first set of consecutive gate lines; a plurality of gate line cut patterns extending in the second direction between neighboring gate lines of the plurality of gate lines; a connecting portion which connects a group of consecutive gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of consecutive gate lines extend, and including connecting pieces between gate lines of the group of gate lines, wherein the gate line cut patterns are blocked by the connecting pieces in the stepped structure; and a contact connected to the group of gate lines and adjacent to the connecting portion, wherein the connecting portion is inside outermost ends of all gate lines of the group of consecutive gate lines in the second direction and is integral with the group of consecutive gate lines.