Patent ID: 9543438
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: providing a substrate having a semiconductor fin extending from the substrate; forming a first gate structure over the semiconductor fin; forming a recess in the semiconductor fin adjacent the first gate structure; epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three sequentially and selectively grown layers, each of the at least three sequentially and selectively grown layers comprising a first dopant, each of the at least three sequentially and selectively grown layers having a dopant concentration; increasing the dopant concentration of a first subset of the at least three sequentially and selectively grown layers, the increasing comprising co-implanting the first subset of the strained material stack with second dopants comprising boron, germanium, indium, tin, or a combination thereof; forming a metal layer on the strained material stack; and locally annealing the metal layer and the strained material stack at a higher temperature than the substrate and the first gate structure to form a metal-silicide layer.