Patent ID: 9742386
Date: 2017-08-22
CPC Classifications: H03K

Claim:
1. A circuit comprising: a first pulse generator configured to generate a first pulse responsive to a rising edge of a first clock signal; a second pulse generator configured to generate a second pulse responsive to a rising edge of a second clock signal, wherein the second clock signal has a phase opposite that of the first clock signal, wherein the first clock signal is an input clock signal, and wherein the circuit further includes a plurality of delay elements, wherein at least a first subset of the plurality of delay elements is coupled between an input to the first pulse generator and an input to the second pulse generator and is configured to provide a total delay of one half of one cycle of the first clock signal in order to produce the second clock signal; a clock generation circuit configured to generate an output clock signal by setting an output clock node to a first state responsive to generation of the first pulse and setting the output clock node to a second state responsive to generation of the second pulse; wherein the clock generation circuit includes: wherein the circuit further comprises a second subset of the plurality of delay elements coupled between the input to the second pulse generator and a phase detector and configured to produce a third clock signal that is a version of the first clock signal delayed by a full cycle, wherein the phase detector is coupled to receive the first and third clock signals and configured to adjust a delay provided by each of the plurality of delay elements based on any phase difference between the first and third clock signals.