Patent ID: 9673231
Date: 2017-06-06
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a thin film transistor; a passivation layer, covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; a via-hole conductive layer, covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode, and a reflectivity of the via-hole conductive layer being lower than a reflectivity of the drain electrode; and a pixel electrode, connected with the drain electrode through the via-hole conductive layer, wherein the array substrate further comprises gate lines, data lines and pixel units defined by the gate lines and the data lines intersecting with each other, and wherein the via-hole conductive layer is provided at the via hole so that no portions of the via-hole conductive layer extend into a display region of each of the pixel units.