Patent ID: 9582277
Date: 2017-02-28
CPC Classifications: G06F

Claim:
1. A method of executing instructions in a processor, the method comprising: receiving an instruction including a first register address; selecting one of a plurality of register entries of a first register using the first register address; determining a second register address based at least in part on a first value stored at the first register address, wherein determining the second register address includes accessing the selected one of the plurality of register entries to obtain the first value; and selectively predicating the instruction based at least in part on a second value stored at the second register address, including addressing a second register using the first value to obtain the second value from the second register, wherein selectively predicating the instruction includes communicating a predication enable signal to an execution unit of the processor, the predication enable signal indicating to predicate the instruction, and wherein the predication enable signal is based on the second value stored at the second register address.