Patent ID: 9552891
Date: 2017-01-24
CPC Classifications: G09G,G11C

Claim:
1. A display panel comprising: a plurality of gate lines; a plurality of data lines crossing the plurality of gate lines; a plurality of pixels connected to the plurality of gate lines and the plurality of data lines; and a plurality of stages respectively connected to the plurality of gate lines and an integrated gate driver, wherein each of the plurality of stages comprises: a first node; a second node; a pull-up driver including an output terminal of the each of the plurality of stages, connected to the first node, and which outputs a gate-on voltage; an output pull-down unit connected to the second node and which pulls down the output terminal of the each of the plurality of stages, the output pull-down unit having a first transistor including a control terminal directly connected to the second node, an input terminal connected to the output terminal of the each of the plurality of stages, and an output terminal connected to a voltage input terminal of the each of the plurality of stages to receive a low voltage; a reset unit connected to the second node and which changes a voltage of the second node into a low voltage based on a voltage of the output terminal of the each of the plurality of stages; a first node pull-up unit connected to the first node and which changes the first node into a high voltage based on a gate-on voltage output from a previous stage of the each of the plurality of stages; a first node pull-down unit which is connected to the first node and the second node and changes the voltage of the first node into the low voltage based on the voltage of the second node, the first node pull-down unit having two transistors each having a control terminal directly connected to the second node, an input terminal of one of the two transistors is directly connected to an output terminal of the other of the two transistors, and a first node reset unit connected to the first node and which changes the voltage of the first node into the low voltage based on the gate-on voltage output from a subsequent stage of the each of the plurality of stages, wherein the first transistor of the output pull-down unit is different from the two transistors of the first node pull-down unit.