Patent ID: 9565542
Date: 2017-02-07
CPC Classifications: H04W

Claim:
1. An apparatus comprising: a processor; and memory coupled to the processor, the memory comprising executable instructions that when executed by the processor cause the processor to effectuate operations comprising: receiving a first plurality of locations of a device, the first plurality of locations of the device determined by a first location determination mechanism; receiving a respective first plurality of determination times at which each location of the first plurality of locations was determined; receiving a second plurality of locations of the device, the second plurality of locations being determined via a second location determination mechanism; receiving a respective second plurality of determination times at which each location of the second plurality of locations as determined; determining a first location from the first plurality of locations having a determination time that is approximately the same as a second location from the second plurality of locations; and determining a difference between the first location and the second location.