Patent ID: 9548280
Date: 2017-01-17
CPC Classifications: H01L,H05K

Claim:
1. A semiconductor device package, comprising: a solder ball pad formed on a first dielectric layer, the solder ball pad having a central pad portion, a perimeter, and an edge about the perimeter, the central pad portion defining and encircling a solder ball mounting area situated inward from the edge about the perimeter, and a recessed portion within the central pad portion at an end of the solder ball pad; and a second dielectric layer formed over the solder ball pad including the perimeter, edge and the central pad portion encircling the solder ball mounting area; wherein the perimeter of the solder ball pad comprises a plurality of outwardly extending protrusions extending about the perimeter up to the recessed portion, the protrusions configured to lock the solder ball pad including the edge and the central pad portion encircling the solder ball mounting area to the second dielectric layer to inhibit delamination of the second dielectric layer therefrom, including at least a first protrusion and a second protrusion adjacent to the first protrusion, the first protrusion and the second protrusion spaced apart at a distance to confine delamination of the second dielectric layer from the solder ball pad to an area between the first protrusion and the second protrusion, each of the protrusions having a first surface, a second surface and a distal end, wherein the distal ends of each of the protrusions are not interconnected to each other; and the second dielectric layer completely covers the plurality of protrusions, the entire perimeter of the solder ball pad including the edge, and the central pad portion of the solder ball pad encircling the solder ball mounting area but not the solder ball mounting area.