Patent ID: 9639654
Date: 2017-05-02
CPC Classifications: G06F

Claim:
1. A method of managing virtual boundaries to enable lock-free concurrent region optimization, the method comprising: receiving a model of an integrated circuit (‘IC’); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region, including: assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; optimizing, by each thread in parallel and without locking any of the objects in any of the regions, the assigned region, including optimizing all portions of the assigned region other than the boundary objects; creating a new region that includes objects previously included in two or more of the plurality of regions, wherein at least one of the boundary objects in each of the two or more of the plurality of regions become non-boundary objects in the new region, including unfreezing data on the boundary objects that become non-boundary objects; and optimizing the new region.