Patent ID: 9608091
Date: 2017-03-28
CPC Classifications: G11C,H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a main surface, the main surface including a first region for a MISFET of a memory cell and a second region for a capacitive element; (b) forming a first conductor film over the main surface of the semiconductor substrate in the first and second regions via a first insulation film; (c) after the step (b), patterning the first conductor film to form a first gate electrode of the MISFET in the first region and a first electrode of the capacitive element in the second region, the first electrode having a first pattern and a second pattern which are opposed to each other in a sectional view; (d) after the step (c), forming a second insulation film so as to cover a side surface of the first gate electrode of the MISFET and side surfaces of the first and second patterns of the first electrode; and (e) after the step (d), forming a second conductor film over the main surface of the semiconductor substrate in the first and second regions, thereby to form a second gate electrode of the MISFET on a surface of the second insulation film and a second electrode of the capacitive element at a space between the first and the second patterns with the second insulation film in the sectional view.