Patent ID: 9584145
Date: 2017-02-28
CPC Classifications: H03M

Claim:
1. A circuit for compensating for mismatch in a plurality of channels of a time-interleaved analog-to-digital converter, each channel of the plurality of channels comprising: an analog-to-digital converter circuit configured to receive an analog input signal and to generate a digital value associated with the analog input signal; a subtractor circuit configured to receive the digital value generated at an output of the analog-to-digital converter circuit; a memory element configured to receive an output of the subtractor circuit; and an accumulator circuit coupled to the memory element, wherein the accumulator circuit generates, for a channel of the plurality of channels, an average value representing an offset voltage that is subtracted from the digital value generated at the output of the analog-to-digital converter circuit by the subtractor circuit; and wherein the subtractor circuit receives the average value representing the offset voltage for the channel.