Patent ID: 9691882
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor structure comprising: a first semiconductor material portion located on a first region of a substrate and including a first source region, a first drain region, and a first body region, and a second semiconductor material portion located on a second region of said substrate and including a second source region, a second drain region, and a second body region, wherein said first semiconductor material portion has a lateral dimension greater than a lateral dimension of said second semiconductor material portion; a first gate stack structure located over said first body region and a second gate stack structure located over said second body region, said first gate stack structure having a height less than a height of said second gate stack structure; a planarization dielectric layer overlying said first and second semiconductor material portions and laterally surrounding said first gate stack structure and said second gate stack structure; a contact-level dielectric layer located on the planarization dielectric layer, wherein a bottommost surface of the contact-level dielectric layer that is in direct contact with a topmost surface of said first gate stack structure and a topmost surface of said planarization dielectric layer in said first region is lower than a bottommost surface of the contact-level dielectric layer that is in direct contact with a topmost surface of said second gate stack structure and a topmost surface of said planarization dielectric layer in said second region; a contact via structure having an upper portion and a lower portion and located in a contact via cavity, wherein the upper portion of the contact via structure is embedded in said contact-level dielectric layer, wherein the lower portion of the contact via structure is embedded in said planarization dielectric layer, wherein an edge of the upper portion of the contact via structure is aligned with an edge of the lower portion of the contact via structure, and wherein a top surface of the upper portion of the contact via structure is coplanar with a top surface of the contact-level dielectric layer; and a carbon-containing metal semiconductor alloy portion underlying said contact via structure and contacting one of said first source region, said first drain region, said second source region, and said second drain region, wherein said first source region, said first drain region, said second source region, and said second drain region are substantially free of carbon and wherein a volume of said carbon-containing metal semiconductor alloy portion extends within a lower portion of said contact via cavity.