Patent ID: 9601178
Date: 2017-03-21
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a first driver circuit comprising a first transistor; a second driver circuit comprising a second transistor; and a cell array over the first driver circuit and the second driver circuit, wherein the cell array comprises a first region comprising a first cell, a second region comprising a second cell, a third region comprising a third cell, and a fourth region comprising a fourth cell, wherein the first cell, the second cell, the third cell, and the fourth cell each comprise a third transistor and a capacitor electrically connected to the third transistor, wherein a gate of the third transistor of the first cell and a gate of the third transistor of the second cell are electrically connected to a first word line, wherein a gate of the third transistor of the third cell and a gate of the third transistor of the fourth cell are electrically connected to a second word line, wherein one of a source and a drain of the third transistor of the first cell and one of a source and a drain of the third transistor of the third cell are electrically connected to a first data line wherein one of a source and a drain of the third transistor of the second cell and one of a source and a drain of the third transistor of the fourth cell are electrically connected to a second data line, wherein an insulating film is over the first driver circuit and the second driver circuit and under the cell array, wherein the insulating film comprises a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole, wherein the first contact hole is between the first region and the second region when seen from a top view, wherein the second contact hole is between the third region and the fourth region when seen from the top view, wherein the third contact hole is between the first region and the third region when seen from the top view, wherein the fourth contact hole is between the second region and the fourth region when seen from the top view, wherein a first wiring electrically connected to the first driver circuit is in contact with the first word line through the first contact hole, wherein a second wiring electrically connected to the first driver circuit is in contact with the second word line through the second contact hole, wherein a third wiring electrically connected to the second driver circuit is in contact with the first data line through the third contact hole, wherein a fourth wiring electrically connected to the second driver circuit is in contact with the second data line through the fourth contact hole, and wherein the third transistor comprises an oxide semiconductor film comprising a channel formation region.