Patent ID: 9727254
Date: 2017-08-08
CPC Classifications: G06F,G11C

Claim:
1. A method of calibrating communication over a command/address bus of a memory device, comprising: receiving a clock signal over a clock signal line; receiving a calibration enabling command through command/address terminals at a first rising edge of the clock signal, wherein the command/address terminals comprise CA receiving a first command/address signal through at least some of the command/address terminals at a second rising edge of the clock signal and generating first information in response to the receiving of the first command/address signal, wherein a signal element of the first command/address signal received by a first command/address terminal and the second rising edge of the clock signal have a first phase difference; transmitting the first information through a first set of data terminals; receiving a second command/address signal through the at least some of the command/address terminals at a third rising edge of the clock signal and generating second information in response to receiving the second command/address signal, wherein a signal element of the second command/address signal received by the first command/address terminal and the third rising edge of the clock signal have a second phase difference; and transmitting the second information through the first set of data terminals, wherein the first phase difference and the second phase difference are different from each other.