Patent ID: 9711210
Date: 2017-07-18
CPC Classifications: G06F,G11C,H01L

Claim:
1. A memory circuit comprising: a plurality of p-channel multiple-gate Metal-Oxide-Semiconductor (MOS) transistors; a p-channel source connection that connects the source terminals of said p-channel multiple-gate MOS transistors; a plurality of n-channel multiple-gate MOS transistors; an n-channel source connection that connects the source terminals of said n-channel multiple-gate MOS transistors; a volatile memory device that comprises part of said p-channel multiple-gate MOS transistors and part of said n-channel multiple-gate MOS transistors; and a power saving mode control circuit that controls voltage differences (Vps−Vns), where the voltage difference (Vps−Vns) is the voltage difference between the voltage (Vps) on the p-channel source connection, and the voltage (Vns) on the n-channel source connection; wherein the power saving mode control circuit is able to control the memory circuit to operate in a power saving mode where the voltage differences (Vps−Vns) is set at a value that the volatile memory device can hold its state, and that the standby leakage current flowing from the p-channel source connection to the n-channel source connection of the electrical circuit under said power saving mode is reduced by at least 80% relative to the standby leakage current flowing from the p-channel source connection to the n-channel source connection of the same memory circuit at normal operation mode, where “normal operation mode” is defined as the operation condition when the voltage differences (Vps−Vns) are set at standard operational voltage and when the substrate bias voltages of the n-channel multiple-gate transistors and the substrate bias voltages of the p-channel multiple-gate transistors are all set to zero.