Patent ID: 9659826
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor device, the method comprising: forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region; forming a tensile strained semiconductor layer on the relaxed semiconductor layer; forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region; forming a first gate in the n-type region and a second gate in the p-type region; and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate, the second set of source/drain features being deeper than the first set of source/drain features, wherein a channel length between the first set of source/drain features is greater than a channel length between the second set of source/drain features.