Patent ID: 9736011
Date: 2017-08-15
CPC Classifications: G06F,H04L

Claim:
1. An apparatus comprising: at least one processor to be comprised in at least one server, the at least one server being at least one of a plurality of servers to be used to implement, at least in part, at least one software defined networking environment, the at least one processor being to control, at least in part, data plane processing and control plane processing of switch circuitry to be comprised in the at least one server, the at least one processor including at least one last level cache memory to be involved in at least one data transfer that involves at least one component of the at least one server, the at least one data transfer being capable of being carried out in a manner that by-passes involvement of system memory in the at least one server, the switch circuitry to be communicatively coupled to the at least one processor and to at least one node via communication links, the switch circuitry including packet switch circuitry, direct memory access (DMA) controller circuitry, and interfaces, the at least one processor being to select, at least in part, parameters related to the packet switch circuitry, the DMA controller circuitry, and the interfaces so as to select, at least in part, (1) data sizes, line rates, duplex/simplex manner of communication, and memory coherent/non-coherent type of interconnects to be used by the packet switch circuitry, the DMA controller circuitry, and the interfaces, (2) at least one communication protocol to be used by the links, and (3) whether the at least one data transfer is to be carried out indirectly via the system memory or the at least one data transfer is to be carried out via directly accessing the last level cache memory, the switch circuitry being to forward, at least in part, via at least one of the links at least one packet received by the switch circuitry; wherein: