Patent ID: 9733307
Date: 2017-08-15
CPC Classifications: G01R

Claim:
1. A method of scanning of an integrated circuit comprising one or more chiplets to isolate one or more fault locations, comprising: providing, by a pervasive of the integrated circuit, an input to the one or more chiplets, each of the one or more chiplets comprising a pervasive satellite, at least one multiplexer, and one or more latches; scanning, by each pervasive satellite of the one or more chiplets, data based on the input via the at least one multiplexer into the one or more latches to produce scan data for each of the one or more chiplets; and comparing, by the pervasive of the integrated circuit, the scan data of each of the one or more chiplets to expectant data stored on the pervasive to isolate the one or more fault locations, wherein the scanning of the data is executed in parallel across the one or more chiplets, wherein the scan data comprises scan signals produces by a clock of the integrated circuit, and wherein the clock generates high frequency noise or a low to middle frequency noise configurable by customizing the data.