Patent ID: 9741855
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate comprising an upper surface; a gate structure over the substrate; a spacer along a sidewall of the gate structure; and a semiconductor layer disposed adjacent to the sidewall of the gate structure and disposed in a recess that extends below the upper surface of the substrate, wherein the semiconductor layer in the recess comprises a first sidewall that directly contacts the spacer and has a linear shape and a second sidewall that directly contacts the first sidewall and has a linear shape, and the first and second sidewalls are slanted with respect to the upper surface of the substrate, wherein the semiconductor layer in the recess comprises a first portion that is bounded by the first sidewall and has a width increasing with a depth of the recess and a second portion that is bounded by the second sidewall and has a width decreasing with the depth of the recess, and wherein an interface between the spacer and the first portion of the semiconductor layer is not below the upper surface of the substrate.