Patent ID: 9639366
Date: 2017-05-02
CPC Classifications: G06F,G06T,G09G,Y02D

Claim:
1. A computer-implemented method for managing buffer table entries, the method comprising: binding a plurality of shader registers to a first buffer table entry included in a buffer table, wherein each shader register included in the plurality of shader registers stores an index to the first buffer table entry included in the buffer table; for each shader register included in the plurality of shader registers, processing at least one tile included in a plurality of tiles by: determining, by a cache controller, that none of the shader registers included in the plurality of shader registers is still bound to the first buffer table entry; in response to determining that none of the shader registers is still bound, causing a release packet to be inserted into an instruction stream transmitted to a tiling unit; determining, by the tiling unit, that a last tile included in the plurality of tiles has been processed; in response to determining that the last tile has been processed, transmitting the release packet to a specified processing unit in a screen-space pipeline; and causing the first buffer table entry to be released in response to the specified processing unit receiving the release packet.