Patent ID: 9600018
Date: 2017-03-21
CPC Classifications: G06F

Claim:
1. A circuit, comprising: a plurality of clock groups including a first clock group, the first clock group including: a plurality of programmable flip-flops; and a controller, wherein the controller is configured to select at least one of the programmable flip-flops for choosing a sub-set of the plurality of clock groups including at least the first clock group for which clocks are to be stopped first during a clock stop process, and to generate an alternative clock signal and initiate the clock stop process of the circuit by sending an alternative mode signal to the first synchronizer, wherein the first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain, and wherein the first synchronizer is further configured to output, to a select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock domain, wherein the select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer for the clock of the first clock domain and an alternative mode clock input of the first clock multiplexer for the alternative clock signal generated by the controller.