Patent ID: 9608005
Date: 2017-03-28
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first memory circuit; and a second memory circuit comprising: wherein one of the first source and the first drain of the first transistor is electrically connected to a first node, wherein the other of the first source and the first drain of the first transistor is electrically connected to a second node, wherein the second gate of the second transistor is electrically connected to the second node, wherein one of the second source and the second drain of the second transistor is directly connected to one of the pair of the second electrodes of the second capacitor, wherein one of the third source and the third drain of the third transistor is electrically connected to one of the fourth source and the fourth drain of the fourth transistor and one of the pair of the first electrodes of the first capacitor, wherein the other of the fourth source and the fourth drain of the fourth transistor is directly connected to the one of the second source and the second drain of the second transistor, wherein the other of the fourth source and the fourth drain of the fourth transistor is electrically connected to a third node, and wherein each of the first transistor and the second transistor comprises a channel formation region provided in an oxide semiconductor layer.