Patent ID: 9582420
Date: 2017-02-28
CPC Classifications: G06F

Claim:
1. A computer system for mapping an address for memory access in a memory system into a combination address comprising a memory bank identifier and a memory bank internal address indicative of an address within said memory bank, said memory system being adapted for storing data in a plurality of memory banks in an interleaved fashion, the computer system comprising: one or more computer processors, one or more computer-readable storage media, and program instructions stored on one or more of the computer-readable storage media for execution by at least one of the one or more processors, the program instructions comprising: program instructions to partition said address for memory access into a first portion, and a second portion; program instructions to determine said memory bank identifier by performing a look-up operation in a look-up matrix, wherein: a look-up matrix row is determined by the value of the first portion; and a look-up matrix column is determined by the value of a binary number with two or more bits formed by applying a parity function to two or more respective sub-portions of the second portion; and program instructions to derive said memory bank internal address based on said second portion of said address for memory access.