Patent ID: 9543359
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A method for a semiconductor device having a plurality of memory devices formed between intersections of a first plurality of electrodes and a second plurality of electrodes, the method comprising: applying a read threshold voltage across a first electrode from the first plurality of electrodes and a second electrode from the second plurality of electrodes, to thereby change a resistance state of a non-linear element in a first memory device that is coupled to the first electrode and the second electrode, from a high resistance state to a low resistance state, wherein the read threshold voltage is greater than a threshold voltage associated with the non-linear element, and wherein the read threshold voltage is less than a program threshold voltage associated with a first memory cell in the first memory device; applying a read voltage across the first electrode and the second electrode to thereby promote a first current flow through the first memory device, wherein the read voltage: determining a resistance state associated with the first memory cell of the first memory device in response to the first current flow.