Patent ID: 9673787
Date: 2017-06-06
CPC Classifications: H03K

Claim:
1. Data retention circuitry comprising: a first power rail; a second power rail; a flip-flop including a master portion and a slave portion, the master portion coupled to the first power rail for a regular operational mode and for a retention operational mode, the flip-flop further including isolation circuitry configured to isolate the master portion from the slave portion for the retention operational mode; power multiplexing circuitry configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode; and power collapse circuitry including clamping circuitry configured to clamp a clock signal responsive to an active state of a retention signal to produce a controlled clock signal; wherein the power collapse circuitry is configured to establish a retention state of the isolation circuitry to prevent the master portion from changing slave data stored by the slave portion for the retention operational mode and to provide the controlled clock signal to the isolation circuitry to establish the retention state of the isolation circuitry to prevent the master portion from changing the slave data stored by the slave portion for the retention operational mode.