Patent ID: 9640279
Date: 2017-05-02
CPC Classifications: G11C

Claim:
1. A memory controller for use in a system-on-chip architecture connected to a memory formed by a plurality of stacked memory integrated circuit dies, the memory controller comprising an interface configured for coupling with the memory through a physical interface circuit, the memory controller including a built-in self-test system for testing the memory for defects and repair of the memory, said built-in self-test system including a self-test state machine sending data to the memory and reading data from the memory in sequential testing steps to detect defective portions of the memory, said sequential testing steps retrieved from a testing step lookup table according to a manufacturer testing specification defined for a memory type of a memory integrated circuit die being tested, said built-in self-test system accessing a nonvolatile memory having a multiplicity of repair steps contained within a repair step lookup table stored therein for repair of memory integrated circuit dies, a plurality of manufacturer-specified repair procedures each defined for a different memory type and each defining select ones of said multiplicity of stored repair steps, said built-in self-test system selecting repair steps from said multiplicity of stored repair steps, said built-in self-test system including a repair state machine executing said selected repair steps to substitute defective memory portions of the memory identified by the testing with redundant portions thereof, said selection being made according to a manufacturer specification defined for the memory type of a memory integrated circuit die containing said identified defective memory portions.