Patent ID: 9620218
Date: 2017-04-11
CPC Classifications: G11C,H01L

Claim:
1. A memory system comprising: a circuit board including a first signal lines, a second signal lines, and a third signal line, the first signal lines, the second signal lines, and the third signal line being electrically separated from each other; a memory package provided on the circuit board, the memory package including a first memory chip, a second memory chip, a plurality of first terminals for receiving a first command and a first address, a second terminal for receiving a chip enable signal, a plurality of third terminals for receiving a second command and a second address and a fourth terminal for receiving the chip enable signal, each of the first and second memory chips including a non-volatile memory cell array, the first memory chip including a plurality of fifth terminals electrically connected to the plurality of first terminals and a sixth terminal electrically connected to the second terminal, the second memory chip including a plurality of seventh terminals electrically connected to the plurality of third terminals and an eighth terminal electrically connected to the fourth terminal; and a controller circuit provided on the circuit board, the controller circuit sending the first command and the first address to the fifth terminals via the first signal lines and the first terminals, the controller circuit sending the second command and the second address to the seventh terminals via the second signal lines and the third terminals, the controller circuit sending the chip enable signal to the sixth and eighth terminal via the third signal line and second and fourth terminals, wherein: the first memory chip stores first information for distinguishing the first memory chip from the second memory chip; the second memory chip stores second information for distinguishing the second memory chip from the first memory chip; and the first memory chip operates in accordance with the first command if the first address matches the first information and the chip enable signal is asserted.