Patent ID: 9589979
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a plurality of stacks of horizontal active lines that comprise portions of layers of material in a plurality of levels, the portions of the layers forming the horizontal active lines having sides defined by rows and columns of holes in an array of holes that penetrate the layers of material; a buttress including a plurality of insulating posts extending vertically between horizontal active lines in the plurality of stacks, each insulating post in the plurality of insulating posts being disposed between and recessed away from perimeters of adjacent holes in two columns and two rows of the array; a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines disposed between the rows of holes in the array of holes; and a memory film between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices.