Patent ID: 9646985
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method of manufacturing a three-dimensional (3-D) non-volatile memory device, the method comprising: forming an interlayer insulating layer; forming a channel layer on the interlayer insulating layer, wherein a memory cell region, a well region and a source region interposed therebetween are defined in the channel layer; selectively doping impurities into the well region of the channel layer so that the well region and the memory cell region include the same type of impurities, and the well region has a higher impurity concentration than the memory cell region; repeating the forming of the interlayer insulating layer, the forming of the channel layer and the doping of the impurities to form a stacked structure so that well regions of stacked channel layers overlap each other in a stacking direction; etching the stacked structure to form channel structures each including channel layers and interlayer insulating layers stacked alternately, wherein the channel layers include well regions, respectively; and forming a well pickup line directly contacting each of the well regions of the channel layers and extending in a direction crossing the channel structures.