Patent ID: 9576919
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method of making a plurality semiconductor packages, comprising: forming a plurality of redistribution layer (RDL) traces comprising a thickness greater than 8 μm disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die, and further forming the plurality of RDL traces as fan-in structures for each of the plurality of semiconductor die within a footprint of each of their respective semiconductor die; disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces; forming a via through the encapsulant material to expose at least one of the plurality of RDL traces; forming an electrical interconnect structure disposed within the via and coupled to the at least one RDL trace; forming a ball grid array (BGA) pad between the RDL and the electrical interconnect structure; and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.