Patent ID: 9542265
Date: 2017-01-10
CPC Classifications: G06F,G11B,H03M,H04L

Claim:
1. A system for decoding a headerized sub data set (SDS), the system comprising: a processor and logic integrated with and/or executable by the processor, the logic including: logic configured to decode a header from a headerized SDS to obtain a SDS; logic configured to perform an error check on the header; logic configured to erase row parity associated with the header from the SDS to indicate that C1 row parity is unknown when the header fails the error check; logic configured to perform C1 and C2 decoding on the SDS in a number of iterations based on a number of interleaves in each row of the SDS; logic configured to overwrite a number of columns of the SDS with successfully decoded C2 codewords; logic configured to overwrite a number of rows of the SDS with successfully decoded C1 codewords; logic configured to erase a number of C1 and/or C2 codewords of the SDS; logic configured to maintain remaining rows and/or columns of the SDS as uncorrected; and logic configured to output the SDS when all rows of the SDS include only C1 codewords and all columns of the SDS include only C2 codewords.