Patent ID: 9594859
Date: 2017-03-14
CPC Classifications: G06F

Claim:
1. A system for parallelizing software in computer-aided design (CAD) software that designs a netlist describing a logic design for an integrated circuit, the system comprising: computing equipment having a plurality of processors, wherein the plurality of processors form a plurality of groupings of logic elements that are identified by the netlist for the logic design in parallel, wherein each grouping in the plurality of groupings comprises a subset of the logic elements identified by the netlist, wherein logic elements within a first grouping in the plurality of groupings are placed in a first portion of the logic design, wherein logic elements within a second grouping in the plurality of groupings are concurrently placed in a second portion of the logic design that is different from the first portion of the logic design, wherein the computer-aided design software generates a bitstream based on the netlist, and wherein the integrated circuit implements the logic design when loaded with the bitstream.