Patent ID: 9659829
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A computer program product for forming a CMOS structure, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to: provide a hot SOI substrate; P++ dope the SOI; mask a first region of the SOI; etch the SOI, and epitaxy the SOI from substrate seed; remove STI area on the SOI; form a hardmask on the SOI; form a fin pattern on the SOI; utilize CMP to process first dielectric removal; reveal recess and fin after material removal; fill and remove a second dielectric utilizing CMP; reveal recess and fin after second dielectric removal; fill and recess the first and second dielectrics to form a stack of dielectrics; deposit a spacer as a liner over the CMOS structure; form a sidewall from the spacer; form and RIE a dielectric stack; block a PFET area; strip a dielectric, Epitaxially grow III-V material on sidewalls of the CMOS structure; use RIE to remove unwanted III-V material; block a NFET area, strip second dielectric, and epitaxially grow the Ge on a sidewall of the CMOS structure; remove unwanted Ge using RIE; etch the hardmask using RIE on the fins; strip the spacer hardmask; fabricate a FET, create gates and hardmask using CMP; form spacers, mask nFETs and S/D pFET epitaxy, mask pFET, and S/D nFET epitaxy, deposit inter-level dielectric followed by CMP; strip the gate and oxide, remove first dielectric to suspend nanowires; and utilize high-K work function metal gate formation, and metal gate fill.