Patent ID: 9653695
Date: 2017-05-16
CPC Classifications: B82Y,H01L,Y10S

Claim:
1. A method of making a transistor device, the method comprising: forming an array of fin structures, the array of fin structures being arranged on a substrate and each having a pair of layers, the pair of layers comprising a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; wrapping a gate around carbon nanotubes (CNTs) between the fin structures to suspend the CNTs in the gate, the CNTs contacting a side surface of the second isoelectric point material in the fin structures; and forming source and drain contacts over the fin structures; wherein the CNTs are arranged in a substantially vertical array or a non-vertical tapered array within the gate, and the gate comprises a metal gate material separated from the source and drain contacts by a gate spacer and a gate dielectric material.