Patent ID: 9607565
Date: 2017-03-28
CPC Classifications: G09G

Claim:
1. A display device comprising: a display panel; a level shifter shifting a start pulse, an initialization pulse, and N-phase shift clocks, N being an integer equal to or greater than 2, to a predetermined voltage; and a gate shift register comprising stages respectively connected to scan lines of the display panel and shifting the start pulse in response to the N-phase shift clocks within a driving period defined by the start pulse to sequentially output a scan pulse, wherein the stages are simultaneously reset in response to the initialization pulse and the N-phase shift clocks within an initialization period preceding the driving period, wherein the initialization period comprises a main initialization period when the initialization pulse is maintained at a turn-on level, and a sub-initialization period when the initialization pulse is maintained at a turn-off level, and wherein the N-phase shift clocks are simultaneously input with a turn-on level that is later in time than the turn-on level of the initialization pulse by a predetermined length of time which is a number greater than 0, within the main initialization period.