Patent ID: 9679515
Date: 2017-06-13
CPC Classifications: G06F,G09G,H05B

Claim:
1. A Light-Emitting Diode (LED) driving circuit, comprising a driving control circuit and a constant current channel group circuit, wherein the driving control circuit comprises: a logic control circuit and a clock delay circuit, wherein the logic control circuit is connected with the constant current channel group circuit, and is configured to control an ordered switching-on or switching-off of the constant current channel group circuit by virtue of a data control signal; and the clock delay circuit is connected with the logic control circuit, and is configured to acquire a timing control signal synchronous with the data control signal, and output the timing control signal to another LED driving circuit; wherein the timing control signal comprises: a shift pulse signal; an input end of the driving control circuit comprises: a shift pulse input port; an output end of the driving control circuit comprises: a shift pulse output port, wherein the clock delay circuit comprises a shift delay input port, a clock delay sub-circuit and a delay output port, wherein the shift delay input port is connected with the shift pulse input and is configured to receive the shift pulse signal; the clock delay sub-circuit is connected between the shift delay input port and the logic control circuit, and is configured to perform delaying processing on the shift pulse signal to acquire a shift pulse signal synchronous with the data control signal by virtue of delay data generated by the clock delay sub-circuit; and the delay output port is connected between the clock delay sub-circuit and the shift pulse output port, and is configured to output the shift pulse signal; wherein the clock delay circuit comprises: a reading device, wherein an input end of the reading device is connected with the logic control circuit, and is configured to read the delay data in a delay table of the logic control circuit; and an output end of the reading device is connected with the clock delay sub-circuit, and is configured to transmit the delay data to the clock delay sub-circuit.