Patent ID: 9741607
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device having a via, the method comprising: forming an inter-metal dielectric layer on a first portion of a conductive bottom substrate layer, wherein the first portion of the conductive bottom substrate layer is isolated from surrounding portions of the conductive bottom substrate layer; photo patterning a via mask onto the inter-metal dielectric layer; etching the inter-metal dielectric layer to define an open via area to the first portion of the conductive bottom substrate layer, wherein a portion of the inter-metal dielectric layer remains around the open via area with the first portion of the conductive bottom there below; depositing a conductive via material in the open via area adjacent the first portion of the conductive bottom substrate layer; removing conductive via material remaining above the inter-metal dielectric layer; and forming a conductive top layer on the inter-metal dielectric layer and the conductive via material, wherein photo patterning the via mask onto the inter-metal dielectric layer comprises photo patterning the via mask with a via area mask open ratio of at least 90%.