Patent ID: 9747965
Date: 2017-08-29
CPC Classifications: G11C

Claim:
1. An adaptive trimming circuit within a magnetic memory device for adaptive trimming of a reference signal applied to at least one sense amplifier for improving a read margin in sensing data during a read operation, comprising: a trim one-time programmable memory array formed of a plurality of one-time programmable memory cells that are programmed with trim data representing magnitudes of a plurality of offset trim signals that modifies a plurality of reference signal levels applied to a plurality of sense amplifiers connected for sensing data present in an array of magnetic memory cells; a plurality of trim bit lines connected such that each bit line is connected to a column of the one-time programmable memory cells for transferring a programming trim signal to selected one-time programmable memory cells for programming the selected one-time programmable memory cells with the trim data and reading the trim data from the selected one-time programmable memory cells; a trim bit line decoder connected to the plurality of trim bit lines for selecting and biasing the trim bit lines for programming and reading the selected one-time programmable memory cells of the trim one-time programmable memory array; and a plurality of sense amplifier trimming circuits connected such that each sense amplifier trimming circuit is in communication with the trim bit line decoder for receiving trim data transferred from the trim one-time programmable memory array wherein each sense amplifier trimming circuit decodes the trim data to determine the magnitude of offset trim signal that is applied to adjust the reference signal to improve the read margin of the plurality of sense amplifiers.