Patent ID: 9648345
Date: 2017-05-09
CPC Classifications: H03K,H04N

Claim:
1. A device, comprising: a video compression processor communicatively coupled to a direct memory access engine and including a search engine configured to search window pixels within a portion of a video frame to yield search window pixel data; a direct memory access engine configured to, in response to initiation of a subpixel interpolation operation of an application process executed by an array of programmable objects, route the search window pixel data from a memory to the video compression processor via a first bus of two multi-bit periphery buses supporting first data flow in a first direction and a second bus of the two multi-bit periphery buses supporting second data flow in a second direction; and party line communication circuitry configured to, in response to initiation of an integer search operation of the application process, route the search window pixel data from the memory to the video compression processor via multiple channels using a programmable object of the programmable objects at a higher transfer rate relative to the direct memory access engine, wherein the party line communication circuitry is further configured to transfer at least a portion of the search widow pixel data via the multiple channels during a single clock cycle.