Patent ID: 9576676
Date: 2017-02-21
CPC Classifications: G11C

Claim:
1. A semiconductor device comprising: an electric fuse circuit including a first plurality of first electric fuses arranged in a matrix and a plurality of second electric fuses arranged in one column in a column direction and each allocated to one or a plurality of rows of the first plurality of first electric fuses arranged in the matrix, the first plurality of first electric fuses being configured to be used as data bits, and the plurality of second electric fuses being used as polarity bits; and a write circuit configured to selectively pass a first current through the first plurality of first electric fuses and the plurality of second electric fuses and thereby write data in the electric fuse circuit, the write circuit being configured to divide all write data into a plurality of pieces of the write data based on a number of the first electric fuses included in the one or the plurality of rows as a division unit, and to perform one of a first process and a second process on each of the plurality of pieces of the write data, the write circuit being configured to perform the first process when a number of write bits included in the write data is larger than a value obtained by dividing a total number of bits in the write data by 2 and to perform the second process when the number of the write bits included in the write data is not larger than the value obtained by dividing the total number of the bits in the write data by 2, the first process including writing of an inverted write data in a second plurality of first electric fuses, and including writing of an inversion data in one of the plurality of second electric fuses included in the electric fuse circuit, the second plurality of first electric fuses being part of the first plurality of first electric fuses included in the electric fuse circuit, the inverted write data being inverted data of the write data, and the inversion data representing inversion, the second process including writing the write data in a third plurality of first electric fuses and including writing non-inversion data in one of the plurality of second electric fuses included in the electric fuse circuit, the third plurality of first electric fuses being part of the first plurality of first electric fuses included in the electric fuse circuit, and the non-inversion data representing non-inversion.