Patent ID: 9601198
Date: 2017-03-21
CPC Classifications: G11C

Claim:
1. A memory circuit comprising: a bistable circuit configured to write data; a nonvolatile element configured to store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit configured to store data written in the bistable circuit into the nonvolatile element in a nonvolatile manner and cut off a power supply to the bistable circuit when it is determined that a period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and store no data written in the bistable circuit into the nonvolatile element in a nonvolatile manner and make a supply voltage for the bistable circuit lower than a voltage during a period to read data from or write data into the bistable circuit when it is determined that the period not to read or write data is shorter than the predetermined time period.