Patent ID: 9640659
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, ones of the plurality of fin active regions extending parallel to each other in a first direction, wherein the plurality of fin active regions comprise forming a sacrificial gate layer on the semiconductor substrate having the isolation region; forming a plurality of hard mask lines on the sacrificial gate layer, wherein the plurality of hard mask lines comprise forming a gate cut mask comprising a plurality of gate cut openings on the semiconductor substrate having the hard mask lines, wherein the plurality of gate cut openings comprise a first gate cut opening, a second gate cut opening, and an edge gate cut opening, wherein etching the hard mask lines using the gate cut mask as an etch mask to form hard mask patterns; and removing the gate cut mask.