Patent ID: 9576934
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a through via formed to penetrate a semiconductor substrate; a first buffer circuit and a second buffer circuit; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed directly in an upper portion of the through via, a direction from the semiconductor substrate to the wiring forming layer being an upward direction, and the connecting wiring portion being formed on a chip inner end face which is an end face of the through via, and facing the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; a second path connecting the second buffer circuit and the through via; a first via connecting line formed directly on the connecting wiring portion in the upper portion of the through via to connect the first path to the through via; and a second via connecting line formed directly on the connecting wiring portion in the upper portion of the through via to connect the second path to the through via, wherein each of the first buffer circuit and the second buffer circuit comprises a transistor and the transistor of the first buffer circuit and the transistor of the second buffer circuit are simultaneously in a conduction state, wherein the first path and the second path are electrically connected via the connecting wiring portion, the first via connecting line and the second via connecting line, and the first via connecting line and the second via connecting line do not directly contact each other in the upper portion of the through via.