Patent ID: 9559097
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method of fabricating a non-isolated transistor, the method comprising: forming a device separating region of the transistor in a semiconductor substrate, the substrate having a first conductivity type, the device separating region having a second conductivity type and defining an active area of the transistor, the second conductivity type being different from the first conductivity type; the device separating regions extending in a vertical orientation in the substrate but not across the active area in a lateral orientation to isolate the active area; forming a body region of the transistor in the active area, the body region having the first conductivity type; and forming source and drain regions of the transistor in the active area, the source region being situated on the body region, the source and drain regions having the second conductivity type; wherein a spacing is defined between the device separating region and the body region to establish a first breakdown voltage lower than a second breakdown voltage in a conduction path between the source and drain regions.