Patent ID: 9653597
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A trench field-effect transistor (trench FET) utilizing a trench situated within a semiconductor substrate of a first conductivity type, said trench including first and second sidewalls and a bottom, an entirety of said first and second sidewalls tapering into a bottom portion which includes said bottom, wherein a bottom trench width measured from said first sidewall to said second sidewall across said bottom of said trench is less than or approximately equal to two-thirds (⅔) of an uppermost width between said first and second sidewalls, thereby substantially reducing gate to drain charge of said trench FET, said bottom portion being surrounded by a bottom implanted region in a drift region, said bottom implanted region having a higher dopant concentration than said substrate, said trench FET further comprising a substantially uniform gate dielectric formed in said trench, a gate electrode formed within said trench and over said gate dielectric, and said semiconductor substrate is doped to form a channel region of a second conductivity type, a source region of said first conductivity type in said semiconductor substrate adjacent said trench, wherein said source region has a depth of less than approximately 0.15 microns, and wherein a channel length of said trench FET is less than or approximately equal to 0.3 microns, wherein said substantially uniform gate dielectric, said gate electrode and said semiconductor substrate have a coplanar top surface, wherein a top surface of said source region is completely covered by a dielectric material separate from said gate dielectric.