Patent ID: 9747209
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. A method for cache-level memory management in a system on a chip (“SoC”), the method comprising: for each of one or more clients, determining eligibility for hashing transaction traffic; for each of the one or more clients that is determined to be eligible for hashing transaction traffic, selecting a customized hashing algorithm; for each of the one or more clients that is determined to be eligible for hashing transaction traffic, applying its customized hashing algorithm to read and write transactions associated with a low level cache; and for each of the one or more clients determined to be eligible for hashing transaction traffic, directing hashed read and write transactions from the low level cache to a memory controller associated with a multi-bank memory device accessible by all of the one or more clients, wherein the hashed read and write transactions are fulfilled from different banks of the multi-bank memory device.