Patent ID: 9698124
Date: 2017-07-04
CPC Classifications: H01L,H05K

Claim:
1. A method of making an embedded, vertically integrated circuit package comprising: providing a substrate with a first patterned conductor layer defining conductive bond pads; mounting a plurality of first components on the substrate; wire bonding said first components to the bond pads of the first patterned conductor layer with bonding wires; laminating a first series of support layers, each with a plurality of cut-outs corresponding to locations of a respective one of the first components to form a solid first stack containing cavities accommodating the first components and the bonding wires associated with said first components; laminating additional support layers without cut-outs over the first series of layers to complete the first stack; forming a second patterned conductor layer defining conductive bond pads on a top surface of the first stack; mounting a plurality of second components on the top surface of the first stack; wire bonding said second components to the bond pads of the second patterned conductor layer with bonding wires; laminating a second series of support layers, each with a plurality of cut-outs corresponding to locations of a respective one of said second components to form a solid second stack containing cavities accommodating the second components and the bonding wires associated with said second components; and forming vertical conductive pathways across the package for providing connections between vertically spaced elements of said package.