Patent ID: 9735989
Date: 2017-08-15
CPC Classifications: H03F,H04B,H04L

Claim:
1. An equalizer, comprising: a differential input comprising a first input and a second input; a differential output comprising a first output and a second output; a first inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to V a second inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to V a first resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the first inductor; a second resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the second inductor; a first cascode comprising a first upper transistor and a first lower transistor, wherein a drain of the first upper transistor is coupled to the lower terminal of the first resistor and the first output, wherein a gate of the first upper transistor is cross-coupled to the lower terminal of the second inductor, wherein a source of the first upper transistor is coupled to a drain of the first lower transistor, and wherein a gate of the first lower transistor is coupled to the first input; a second cascode comprising a second upper transistor and a second lower transistor, wherein a drain of the second upper transistor is coupled to the lower terminal of the second resistor and the second output, wherein a gate of the second upper transistor is cross-coupled to the lower terminal of the first inductor, wherein a source of the second upper transistor is coupled to a drain of the second lower transistor, and wherein a gate of the second lower transistor is coupled to the second input; a first current source coupled between a source of the first lower transistor and ground; and a second current source coupled between a source of the second lower transistor and ground.