Patent ID: 9627036
Date: 2017-04-18
CPC Classifications: G11C,H01L

Claim:
1. A static random access memory layout structure, comprising: a semiconductor substrate, comprising: a first gate line crossing the first active region and the second active region and extending to cover an end of the third active region; a second gate line crossing the third active region and the fourth active region and extending to cover an end of the second active region, wherein the first gate line and the second gate line extend along the second direction respectively and are parallel to each other; a first slot contact plug disposed between the first gate line and the second gate line and crossing the first active region and the second active region; a second slot contact plug disposed between the first gate line and the second gate line and crossing the third active region and the fourth active region, wherein the first slot contact plug and the second slot contact plug are arranged along the second direction and disposed between the first gate line and the second gate line; a first metal-zero interconnect disposed on the first slot contact plug and the second gate line and electrically connecting the first slot contact plug to the second gate line, wherein the first slot contact plug and the first metal-zero interconnect cross each other; a second metal-zero interconnect disposed on the second slot contact plug and the first gate line and electrically connecting the second slot contact plug to the first gate line, wherein the second slot contact plug and the second metal-zero interconnect cross each other; and a fifth gate line and a fifth metal-zero interconnect, wherein the fifth gate line is symmetric to the first gate line with respect to the second direction, and the fifth metal-zero interconnect is symmetric to the second metal-zero interconnect with respect to the second direction, and wherein the second metal-zero interconnect and the fifth metal-zero interconnect have a fourth gap therebetween, the first gate line and the fifth gate line have a fifth gap therebetween, and the fourth gap is smaller than the fifth gap.