Patent ID: 9558804
Date: 2017-01-31
CPC Classifications: G11C,H01L

Claim:
1. A method of erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality of FeFET memory cells, each FeFET comprising a gate stack, a source, a drain, a channel and a bulk substrate region, wherein the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel, the method comprising: applying first and second voltages to the source and drain regions, respectively, of at least one FeFET memory cell of the plurality of FeFET memory cells, wherein the first and second voltages are configured to generate a substantially uniform electric field between the channel and gate in order to generate a substantially uniform change in a polarization of the ferroelectric layer of the at least one FeFET memory cell; and applying third and fourth voltages to the gate and bulk substrate regions, respectively, of the at least one FeFET memory cell during said applying of the first and second voltages to the source and drain regions of the at least one FeFET memory cell to cause erasure of the at least one FeFET memory cell, wherein the third voltage is one of a ground state or a voltage of opposite voltage polarity to the first and second voltages, and wherein the fourth voltage is one of a ground state or a voltage of a same voltage polarity to the first and second voltages and lower in absolute value than the first and second voltages.