Patent ID: 9548088
Date: 2017-01-17
CPC Classifications: G11C

Claim:
1. A memory device comprising: a memory core having addressable memory elements; a read path for accessing the addressable memory elements, the read path defined between an address input port and a data output port of the memory core; a plurality of pipeline stages located in the read path, an end pipeline stage and another end pipeline stage of the plurality of pipeline stages defining end boundaries of the plurality of pipeline stages in the read path, wherein the end pipeline stage is configured to provide read data read from the memory core to the data output port, and wherein the other end pipeline stage receives addressing information identifying the addressable memory elements from which the read data is stored; and a plurality of delay elements corresponding to the plurality of pipeline stages, respectively, each delay element having a configurable delay, wherein the delay element corresponding to the end pipeline stage is configured to generate an asynchronous signal used to latch the read data at the end pipeline stage independent of a system clock signal, and wherein the delay element corresponding to the other end pipeline stage is configured to generate an asynchronous signal used to latch the addressing information.