Patent ID: 9673106
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate including an active fin and an isolation layer thereon; a first gate structure on the active fin, the first gate structure including a first gate insulation layer pattern and a first metal pattern, and the first metal pattern having a first conductivity type and being disposed on the first gate insulation layer pattern; a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type; and first source/drain regions at upper portions of the active fin adjacent to opposite sidewalls of the first gate structure, the first source/drain regions including impurities having a second conductivity type different from the first conductivity type, wherein the first gate structure, the first channel region, and the first source/drain regions define a first transistor, the first transistor being electrically connected to an input part or to an output part of a logic circuit to switch the logic circuit.