Patent ID: 9589837
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method for manufacturing a fuse device, comprising: forming a first dielectric layer on a substrate, forming a second dielectric layer on the first dielectric layer, and forming a third dielectric layer on the second dielectric layer; forming, by a first etching process, a first via hole in the second dielectric layer and the third dielectric layer; forming a fourth dielectric layer on the third dielectric layer, wherein a first portion of the fourth dielectric layer is formed on sidewalls of the first via hole, a second portion of the fourth dielectric layer is formed on a bottom surface of the first via hole, and third portions of the fourth dielectric layer are formed on top surfaces of the third dielectric layer external to the first via hole, and wherein the fourth dielectric layer is completely filled and formed conformally on the third dielectric layer; removing, by a second etching process, the second and third portions of the fourth dielectric layer; forming, by a third etching process, a second via hole in the first dielectric layer using the first portion of the fourth dielectric layer as an etching barrier layer, wherein the second via hole extends through the first dielectric layer to a surface of the substrate; filling the second via hole with an electrode material; and forming, by a polishing process, a first electrode, wherein the first electrode is embedded in the first dielectric layer.