Patent ID: 9740456
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. Galois-field reduction circuitry for reducing a Galois-field expansion value using an irreducible polynomial, the Galois-field reduction circuitry comprising: a plurality of memories, each for storing a predetermined value, wherein precalculated in-field values corresponding to predefined Galois-field expansion values having a single ‘1’ in an out-of-field bit are determined based on said irreducible polynomial and said predefined Galois-field expansion values, wherein each of the predetermined values is determined based on one or more of said precalculated in-field values, and wherein out-of-field bits of said expansion value address said plurality of memories to output one or more of said predetermined values; and exclusive-OR circuitry for combining output of said plurality of memories with in-field bits of said expansion value.