Patent ID: 9641315
Date: 2017-05-02
CPC Classifications: H03K,H03L,H04L

Claim:
1. A method for implementing a hybrid phase locked loop (HPLL) combining a digital phase locked loop (DPLL) with an analog phase locked loop (APLL) in order to maintain a preprogrammed phase and frequency transfer function between a reference clock and an output clock; wherein the HPLL method comprises the steps of: controlling operations of the HPLL by utilizing the DPLL comprising a frame phase detector (FPD) and a programmable control unit (PCU); producing the output clock by utilizing the APLL comprising a phase synthesizer (PS) and an analog phase detector (APD) and a voltage controlled oscillator, wherein a first input of the PS and a first input of the APD are connected to the output clock and a second input of the APD is connected to an output of the PS; wherein the FPD measures digital phase errors between the output clock and the reference clock; wherein the PCU uses the digital phase errors for producing control signals applied to a second input of the PS; wherein the PS uses the control signals to insert phase differences, between the first APD input and the second APD input, needed for implementing the preprogrammed phase and frequency transfer function.