Patent ID: 9576613
Date: 2017-02-21
CPC Classifications: G11C

Claim:
1. A semiconductor device comprising: a semiconductor substrate; a test circuit array region on the semiconductor substrate; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region; transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction; source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors; and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to corresponding drain electrodes of the transistors, wherein each of the source lines and the drain lines comprises: wherein different first pad portions of the source and drain lines are disposed in the pad region at different distances from the first side of the test circuit array region.