Patent ID: 9740454
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. An integrated circuit, comprising: a first circuit clocked by a first clock; a second circuit clocked by a second clock, wherein the second clock and the first clock are configured to operate at different frequencies; a control queue coupled to receive an element of control information outputted from the first circuit, and to be read by the second circuit; a data queue coupled to receive an element of data outputted from the first circuit, wherein the element of control information and element of data are pipelined and offset from each other by a pre-set number of clock events of the first clock; and a counter operable to be initialized to an initial value and to be updated during subsequent clocking; wherein the second circuit is configured to read the element of control information from the control queue responsive to the value of the counter reaching a pre-determined value, and to read the element of data from the data queue after the pre-set number of clock events have occurred for the second clock after the control information is read.