Patent ID: 9652582
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A method comprising: initiating, using one or more processors of an electronic design automation (EDA) computing device, a timing analysis for an integrated circuit design; accessing, by the one or more processors, timing constraints for a plurality of instances of a master-clone block of the integrated circuit design, each instance of the master-clone block comprising a master block structure; identifying, by the one or more processors, a first set of timing constraints for a first block of the plurality of instances of the master-clone block, wherein the first set of timing constraints is based on a first placement of the first block within the integrated circuit design; identifying, by the one or more processors, a second set of timing constraints for a second block of the plurality of instances of the master-clone block; and optimizing, by the one or more processors, the integrated circuit design based on the timing analysis using the first set of timing constraints and the second set of timing constraints.