Patent ID: 9735381
Date: 2017-08-15
CPC Classifications: G02F,H01L

Claim:
1. A thin film transistor array, comprising: a plurality of thin film transistors positioned in a matrix, each of the thin film transistors including a substrate; a gate electrode formed on the substrate; a gate insulation layer formed on the gate electrode; a source electrode formed on the gate insulation layer; a drain electrode formed on the gate insulation layer; a pixel electrode formed on the gate insulation layer and connected to the source electrode and the drain electrode; a semiconductor layer formed between the source electrode and the drain electrode; an interlayer insulation film covering the source electrode, the drain electrode, the semiconductor layer and a portion of the pixel electrode; and an upper pixel electrode formed on the interlayer insulation film and connected to the pixel electrode, wherein the interlayer insulation film has at least one concave portion and at least one via hole portion.