Patent ID: 9691819
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A vertical transistor comprising: a pillar vertically extending from a substrate and including a source, a channel region, and a drain, wherein the channel region extends between the source and the drain; a gate formed over an outer surface of the pillar and overlapping the channel region; and a first electric field-buffering region formed in the pillar to occupy one portion of an outer surface of the channel region, wherein the first electric field-buffering region is formed of a material having a band gap different from that of the pillar and different from a material for forming the pillar, wherein the first electric field-buffering region is formed at a boundary portion between the drain and the channel region to have an annular shape, and wherein the first electric field-buffering region overlaps a first edge portion of the gate.