Patent ID: 9660640
Date: 2017-05-23
CPC Classifications: H01L,H03K

Claim:
1. A circuit comprising: an electronic component package comprising at first lead, a second lead, and a third lead; a III-N device encased in the electronic component package, the III-N device comprising a depletion mode III-N transistor and an enhancement mode transistor, the depletion mode III-N transistor comprising a first drain, a first gate, and a first source, the enhancement mode transistor comprising a second drain, a second gate, and a second source, the first gate of the depletion mode III-N transistor and the second source of the enhancement mode transistor each coupled to the first lead, and the first drain coupled to the third lead; a gate driver coupled to the second lead of the electronic component package; and a ferrite bead encased in the electronic component package and coupled between the second gate of the enhancement mode transistor and the second lead; wherein the first source of the depletion mode III-N transistor is coupled to the second drain of the enhancement mode transistor.