Patent ID: 9697098
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A test unit comprising: a memory; and at least one processor in communication with the memory, wherein the at least one processor is configured to perform a method comprising: receiving, while the test unit is in a first hardware operating state, a request, from a test platform, for input data; determining, in response to the receiving the request, that retrieving the input data requires the test unit to be in a second hardware operating state; identifying, in response to the determining, a first transition path between the first hardware operating state and the second hardware operating state and a second transition path between the first hardware operating state and the second hardware operating state, wherein the first transition path includes a transition from the first hardware operating state to a third hardware operating state and a transition from the third hardware operating state to the second hardware operating state, and wherein the second transition path includes a transition from the first hardware operating state to a fourth hardware operating state and a transition from the fourth hardware operating state to the second hardware operating state; evaluating, based on a set of criteria, the first transition path and the second transition path; selecting, based on the evaluating, the first transition path over the second transition path; transitioning, in response to the determining, the test unit from the first hardware operating state to the second operating hardware state, wherein the transitioning from the first hardware operating state to the second operating hardware state is via the first transition path; retrieving, while test unit is in the second hardware operating state, the input data; and transmitting the input data to the test platform.