Patent ID: 9627022
Date: 2017-04-18
CPC Classifications: G06F,G11C

Claim:
1. A memory device comprising: global control circuitry configured to receive a clock signal for the memory device, the memory device being configured to perform a double memory access in response to a single edge of the clock signal, and a plurality of banks, each bank having associated local bank control circuitry, wherein the memory device is further configured to generate a first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access in response to the single edge of the clock signal, wherein the global control circuitry is further configured to generate a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and wherein a local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal, and wherein the local bank control circuitry of the second bank is further configured to generate a first edge of the second internal clock pulse in dependence on a reset signal generated by the local bank control circuitry of the second bank and without dependence on signals generated by local bank control circuitry of banks of the plurality of banks which are not the second bank, if the comparison signal indicates that the first bank indicated matches the second bank indicated.