Patent ID: 9553091
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A semiconductor structure, comprising: a first high-voltage MOS device region, including: a first well; a first light-doping region disposed in a part of the first well, wherein a conductive type of the first well and a conductive type of the first light-doping region are opposite; a first gate stack on a part of the first well and a part of the first light-doping region; spacers on sidewalls of the first gate stack; and a plurality of first heavy-doping regions in the first well and the first light-doping region at two sides of the first gate stack, wherein a conductive type of the plurality of the first heavy-doping regions and the conductive type of the first well are the same, and each of the plurality of the first heavy-doping regions has an edge aligning to an outer side of the spacers; wherein the first light-doping region between the first well and one of the plurality of the first heavy-doping regions in the first light-doping region is a channel region of the first high-voltage MOS device region, and wherein the first well is disposed in a substrate, the conductive type of the first well and a conductive type of the substrate are the same, and the first high-voltage MOS device region further includes a deep well disposed between the first well and the substrate, and a conductive type of the deep well and the conductive type of the first well are different.