Patent ID: 9552865
Date: 2017-01-24
CPC Classifications: G06F,G11C

Claim:
1. A memory controller to control the operation of a dynamic random access memory (DRAM), the DRAM being among a plurality of DRAMs that receive a clock signal that is routed to the DRAMs in a flyby configuration, such that each DRAM of the plurality of DRAMs receives the clock signal in sequence, the memory controller comprising: a circuit to transmit the clock signal to the DRAM; a circuit to transmit a strobe signal to the DRAM, the strobe signal to convey phase information to the DRAM for sampling data associated with the strobe signal; and calibration logic to, in a calibration mode of operation, align at the DRAM, arrival of the strobe signal with arrival of the clock signal, based on feedback received from the DRAM, wherein the calibration logic delays the strobe signal as a delayed strobe such that it arrives at the DRAM at an edge transition of the clock signal, the calibration logic to further adjust the delayed strobe by iteratively writing first data using the delayed strobe to a specific location in the DRAM, reading back second data from the specific location in which the first data was written, and selectively adjusting the delayed strobe based on whether the second data matches the first data; and an interface port to transmit the first data, receive the second data, and to receive the feedback from the DRAM.