Patent ID: 9583059
Date: 2017-02-28
CPC Classifications: G09G,H03K

Claim:
1. A level shift circuit, comprising: a first level non-inverting input terminal, a first level inverting input terminal, a second level non-inverting output terminal, a second level inverting output terminal, a level state transferring unit and a second level driving unit; wherein, the level state transferring unit receives a first level input through the first level non-inverting input terminal and the first level inverting input terminal, and transfers a state of the input first level to the second level driving unit; the second level driving unit outputs a second level of a corresponding state to the second level non-inverting output terminal and the second level inverting output terminal according to the input state of the first level, and the first level is not equal to the second level, wherein, the level state transferring unit comprises: a first signal non-inverting input unit, which is configured to receive a non-inverted level signal input through the first level non-inverting input terminal and output a level signal having the same phase; a first signal inverting input unit, which is configured to receive an inverted level signal input through the first level inverting input terminal and output a level signal having the same phase; and a first state interlocking unit, which is configured to receive the level signals output from the first signal non-inverting input unit and the first signal inverting input unit, maintain states of the level signals unchanged through an interlocking structure, and output the level signals in forms of a non-inverted level signal and an inverted level signal, respectively.