Patent ID: 9665347
Date: 2017-05-30
CPC Classifications: G06F,H03M

Claim:
1. An apparatus comprising: processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a floating-point value comprising an alternative representation of said binary value; the processing circuitry comprising: exponent determining circuitry to determine an exponent of the floating-point value based on a position of a most significant non-sign bit within the plurality of data elements and a significance of the data element comprising the most significant non-sign bit; and significand determining circuitry to perform a significand generation operation to generate a partial significand value for at least one of the plurality of data elements, and to form a significand of the floating-point value based on the partial significand value generated for said at least one data element.