Patent ID: 9685369
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method of fabricating a field effect transistor, the method comprising: forming a gate structure over a substrate, the gate structure comprising sidewalls and a top surface; forming spacers adjacent opposing sidewalls of the gate structure; forming a first contact etch stop layer (CESL) over the spacers and extending along a surface of the substrate; forming a second CESL over at least a portion of the top surface of the gate structure; forming an interlayer dielectric layer over the first CESL and the second CESL; forming a gate contact extending through the interlayer dielectric layer; and forming a source contact and a drain contact extending through the interlayer dielectric layer and the first CESL, wherein there is no silicide region on the substrate, and a distance between an edge of the source contact and a corresponding edge of the second CESL is about 1 nm to about 10 nm.