Patent ID: 9589905
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: a substrate; a chip disposed over a top surface of the substrate; an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip; a ground pad disposed in the substrate to contact a bottom surface of the substrate; a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad; a first bonding pad contacting the top surface of the substrate, the first bonding pad being electrically coupled to both a first portion of the EMI shielding layer and the chip; a second bonding pad contacting the top surface of the substrate, the second bonding pad electrically coupled to a second portion of the EMI shielding layer; a first interconnection line that electrically couples the first bonding pad to the ground pad; a second interconnection line that electrically couples the second bonding pad to the test pad; and a third bonding pad electrically coupled to the chip via a first bonding wire and electrically coupled to the first bonding pad through a third interconnection line disposed in the substrate, wherein the ground pad is electrically coupled to both the first portion of the EMI shielding layer, via the first interconnection line and the first bonding pad, and the chip, via the first interconnection line, the first bonding pad, the third interconnection line, the third bonding pad, and the first bonding wire, wherein the test pad is electrically coupled to the second portion of the EMI shielding layer via the second interconnection line and the second bonding pad, wherein a loop circuit, which includes the first interconnection line, the first bonding pad, the EMI shielding layer, the second bonding pad, and the second interconnection line, is created between the ground pad and the test pad, such that an electrical open/short state between the EMI shielding layer and the ground pad is tested using the loop circuit, wherein the semiconductor package further comprises: at least one additional test pad disposed in the substrate to contact the bottom surface of the substrate and electrically coupled to a portion of the EMI shielding layer different from the first and second portions; and at least one additional ground pad disposed in the substrate to contact the bottom surface of the substrate and electrically coupled to both the EMI shielding layer and the chip, and wherein the test pads and the ground pads are disposed along two different edges of the bottom surface of the substrate, respectively.