Patent ID: 9627315
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductor substrate; and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another, each interconnection layer including a real interconnection and a dummy interconnection covered with an insulative film; wherein the plurality of interconnection layers includes a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view.