Patent ID: 9697143
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A system, comprising: a memory system configured for access by a plurality of computer processing units; a lock bit configured in a translation table of the memory system, the lock bit supporting both address lock shared and address lock exclusive functions; a backing bit and an invalid bit configured in a segment table entry of the memory system; and a storage manager of an operating system, the storage manager configured to obtain exclusive access to an entry in a dynamic address translation (DAT) table either by obtaining an address space lock exclusive or obtaining an address space lock shared, and setting the lock bit in a DAT entry, wherein when a lock is held on a segment corresponding to the segment table entry, a location field of the segment table entry is based at least in part on respective values of the backing bit and the invalid bit such that: when the invalid bit is 0 and the backing bit is 0, the location field of the segment table entry holds a real address of a page table frame; when the invalid bit is 0 and the backing bit is 1, the location field of the segment table entry holds a real address of 1 MB frame; and when the invalid bit is 1 and the backing bit is 1, the location field of the segment table entry holds a real address of 1 MB page in an auxiliary storage location.