Patent ID: 9634011
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a first impurity region and a second impurity region formed in the substrate separated from each other by the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer, wherein the dielectric work function adjusting liner is formed over the lower portion of the trench without overlapping with the first and the second impurity region.