Patent ID: 9711592
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A diode, comprising: a p-type semiconductor substrate; an n-type semiconductor layer on the p-type semiconductor substrate; a p-type isolation region surrounding a predetermined region of the n-type semiconductor layer on the p-type semiconductor substrate; a p-type anode region and a plurality of n-type cathode regions in a diode formation region, which is within the predetermined region in a surface layer of the n-type semiconductor layer; a p-type guard ring in a region between the diode formation region of the surface layer of the n-type semiconductor layer and the p-type isolation region, the p-type guard ring being electrically connected to the plurality of n-type cathode regions; an n-type buried layer across the p-type semiconductor substrate and the n-type semiconductor layer within the predetermined region; and an n-type collector wall in the n-type semiconductor layer, wherein a transistor for reducing a leakage current is formed by the p-type anode region, the p-type guard ring, and an n-type semiconductor between the p-type anode region and the p-type guard ring, wherein the n-type buried layer has an impurity concentration higher than an impurity concentration of the n-type semiconductor layer, wherein the n-type collector wall stands on the n-type buried layer toward a surface of the n-type semiconductor layer to surround the predetermined region of the n-type semiconductor layer, and has an impurity concentration higher than the impurity concentration of the n-type semiconductor layer, wherein the p-type guard ring surrounds the diode formation region in a region between the n-type collector wall and the p-type isolation region, and wherein the n-type semiconductor comprises the n-type semiconductor layer and the n-type collector wall.