Patent ID: 9712182
Date: 2017-07-18
CPC Classifications: H03M

Claim:
1. A digital to analog conversion circuit, DAC, comprising: a number of serializing lanes, each serializing lane comprising at least two bit inputs, and each serializing lane being configured to output the two bit inputs serially via a serialized output port at a predetermined first clock rate, a number of non-serializing lanes, each non-serializing lane comprising at least two bit inputs and each non-serializing lane being configured to output the two bit inputs in parallel each via a separate parallel output port, at a second clock rate, which is half the clock rate of the first clock rate, and a current switching network comprising a bit input port for every one of the serialized output ports and for every one of the parallel output ports and being configured to produce a output current, based on the signals received via the bit input ports.