Patent ID: 9646702
Date: 2017-05-09
CPC Classifications: G11C

Claim:
1. A method of operating a memory device, the method comprising: biasing a data line to a first potential, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells; biasing a source to a second potential, where the source is coupled to a second end of the first string of memory cells and to a second end of the second string of memory cells; deactivating a select gate coupled between the first end of the second string of memory cells and the data line by biasing a control gate of the select gate to a third potential where the first potential is greater than the third potential; and performing a programming operation on a selected memory cell of the first string of memory cells by applying a programming potential to a control gate of the selected memory cell concurrently with biasing the data line to the first potential and biasing the source to the second potential and while the select gate is deactivated to increase a threshold voltage of the selected memory cell; wherein the first potential is greater than the second potential.