Patent ID: 9564214
Date: 2017-02-07
CPC Classifications: G11C,H01L

Claim:
1. A memory device, comprising: a controller; a first electrode and a second electrode connected to the controller; and a variable resistance layer provided between the first electrode and the second electrode, the variable resistance layer including a chalcogenide compound including a grain boundary, the variable resistance layer having the controller configured to be able to perform wherein the controller is configured to be able to perform the third operation after the first operation is performed a first number of times, a fourth operation of applying a fourth voltage between the first electrode and the second electrode having the interposed variable resistance layer after the third operation is Performed a second number of times, the fourth voltage being higher than the third voltage, a fifth operation of applying a fifth voltage between the first electrode and the second electrode having the interposed variable resistance layer determined to not have the first structure in the second operation, the fifth voltage being higher than the second voltage and lower than the third voltage, a sixth operation of applying a sixth voltage between the first electrode and the second electrode and determining whether or not the variable resistance layer has the first structure, the sixth voltage being lower than the first voltage, the third operation after the fifth operation is performed a third number of times, and the third operation after the first operation and the fifth operation are performed a fourth number of times.