Patent ID: 9627507
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, the method comprising: receiving a substrate; forming a poly gate stack on the substrate; performing a dopant implant to the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate to form a first doped feature and a second doped feature in the substrate, the first doped feature formed in the substrate proximate a first side of the poly gate stack and the second doped feature formed in the substrate proximate an opposing second side of the poly gate stack without extending under the poly gate stack; after performing the dopant implant to the substrate, forming a first spacer on the first side of the poly gate stack and a second spacer on the opposing second side of the poly gate stack, wherein after forming the first and second spacers the first doped feature extends within the substrate under the first spacer and the second doped feature does not extend within the substrate under the second spacer; etching first and second source/drain (S/D) regions in the substrate, wherein the first and second S/D regions are asymmetric with respect to the poly gate stack, wherein etching the first and second S/D regions includes removing a portion of the first doped feature to form a first recess and removing a portion of the second doped feature to form a second recess, wherein after removing the portion of the first doped feature to form the first recess another portion of the first doped feature remains extending within the substrate under the first spacer; depositing a first strained S/D layer into the first recess and a second strained S/D layer into the second recess, wherein the closest distance between a portion of the first strained S/D layer and the second strained S/D layer is less than the closest distance between the another portion of the first doped feature and the second strained S/D layer, the portion of the first strained S/D layer being disposed within the substrate directly under the poly gate stack; removing the poly gate stack from the substrate; and forming a high-k metal gate using a gate-last process where the poly gate stack was removed.