Patent ID: 9666481
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A method of forming an M1 metal line in an integrated circuit, the method comprising: depositing a SiCN etch stop layer over a substrate; depositing a dielectric layer of low dielectric constant on the substrate; patterning the dielectric layer based on desired dimensions for the M1 metal line; etching a trench based on the pattern, wherein a dimension of the trench corresponds to the desired dimensions for the M1 metal line, and wherein the trench does not include a seed layer; and depositing a material for the M1 metal line in the trench, wherein the dimensions for the M1 metal line include a height smaller than a height for a M1 metal line formed of Copper, and a length of the M1 metal line is smaller than a minimum allowable length of a M1 metal line formed of Copper, wherein the material for the reduced height M1 metal line comprises Tungsten (W), Molybdenum (Mo), Ruthenium (Ru), or a combination thereof.