Patent ID: 9720014
Date: 2017-08-01
CPC Classifications: G01R

Claim:
1. A semiconductor evaluation apparatus that evaluates a plurality of vertical semiconductor devices provided in a semiconductor wafer, said vertical semiconductor devices each including a front surface electrode and a back surface electrode respectively provided on a front surface and a back surface of said semiconductor wafer, said semiconductor evaluation apparatus comprising: a semiconductor wafer holding portion that holds said semiconductor wafer; a front surface probe that is electrically connected to said front surface electrode in a case of being in contact with said front surface electrode on said semiconductor wafer held by said semiconductor wafer holding portion; a back surface connecting portion that is electrically connected to said back surface electrode in a case of being in contact with said back surface electrode on said semiconductor wafer held by said semiconductor wafer holding portion; a back surface potential lead-out portion that has one end portion disposed in a side of said back surface of said semiconductor wafer held by said semiconductor wafer holding portion and electrically connected to said back surface connecting portion and that has the other end portion disposed in a side of said front surface of said semiconductor wafer held by said semiconductor wafer holding portion and electrically connected to said one end portion; and an evaluation unit that passes current through said front surface electrode and said back surface electrode via said front surface probe and said other end portion of said back surface potential lead-out portion, respectively, to evaluate electrical characteristics of said vertical semiconductor devices, wherein said semiconductor wafer and said semiconductor wafer holding portion that holds said semiconductor wafer, or said front surface probe, said back surface connecting portion, and said back surface potential lead-out portion are movable in an in-plane direction of said semiconductor wafer, and in a case where said semiconductor wafer and said semiconductor wafer holding portion that holds said semiconductor wafer, or said front surface probe, said back surface connecting portion, and said back surface potential lead-out portion are moved in said in-plane direction, one of said semiconductor wafer and a portion of said back surface potential lead-out portion located in said in-plane direction from said semiconductor wafer is fixed close to the outside of a movement region of the other.