Patent ID: 9595964
Date: 2017-03-14
CPC Classifications: H01L,H03K

Claim:
1. A semiconductor device comprising: a first wiring and a second wiring; a logic block electrically connected to the first wiring and the second wiring; and a wiring selection circuit provided at an intersection of the first wiring and the second wiring, wherein the wiring selection circuit comprises first transistor to fourth transistors each comprising a first terminal, a second terminal, and a gate, wherein the first terminal and the second terminal of the first transistor are electrically connected to the first wiring and the second wiring, respectively, wherein the first terminal and the second terminal of the third transistor are electrically connected to the first terminal of the first transistor and the second terminal of the first transistor, respectively, wherein the second terminal of the second transistor is electrically connected to the gate of the first transistor, wherein the gate of the second transistor is electrically connected to the gate of the fourth transistor so that a same signal is applied to the gate of the second transistor and to the gate of the fourth transistor, wherein the second terminal of the fourth transistor is electrically connected to the gate of the third transistor, and wherein a channel formation region of the second transistor and a channel formation region of the fourth transistor each comprises an oxide semiconductor.