Patent ID: 9728405
Date: 2017-08-08
CPC Classifications: B82Y,H01L

Claim:
1. A semiconductor device, comprising: at least two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device; a dielectric structure entirely filling a space extending between the at least two semiconductor nanowires and which is in contact with the at least two semiconductor nanowires; and a gate dielectric and a gate covering at least a first of the at least two semiconductor nanowires, sidewalls of the two semiconductor nanowires, and sidewalls of the dielectric structure when the at least two semiconductor nanowires are superimposed one on top of the other, or covering a part of the upper faces of the at least two semiconductor nanowires and a part of an upper face of the dielectric structure when the at least two semiconductor nanowires are arranged next to one another, wherein the dielectric structure comprises at least one portion of dielectric material with a relative permittivity greater than or equal to 20, and wherein the at least two semiconductor nanowires are arranged next to one another such that a part of the dielectric structure is arranged under the at least two semiconductor nanowires and between the at least two semiconductor nanowires.