Patent ID: 9704592
Date: 2017-07-11
CPC Classifications: G11C

Claim:
1. A semiconductor storage device, comprising: a plurality of bit lines; a plurality of select gate lines that intersect with the plurality of bit lines; a plurality of memory cells that each include a p-channel memory transistor, with the plurality of memory cells each disposed so as to correspond to respective portions of intersection between the plurality of bit lines and the plurality of select gate lines; a source line that is connected to each of the memory transistors, and that is applied with a first specific potential when reading data stored in the memory cells; a plurality of p-channel charging transistors that are respectively connected to the plurality of bit lines; a charging line that is connected to each of the plurality of charging transistors, and that is applied with a second specific potential when reading data stored in the memory cells; and a controller that places each of the charging transistors in an ON state prior to current, corresponding to data stored in a read target memory cell of the plurality of memory cells on which data reading is to be performed, flowing in a read target bit line that is one of the plurality of bit lines and that corresponds to the read target memory cell, the controller placing a charging transistor connected to the read target bit line in an OFF state when a current corresponding to data stored in the read target memory cell flows in the read target bit line.