Patent ID: 9570000
Date: 2017-02-14
CPC Classifications: G09G

Claim:
1. A pixel circuit comprising a driving transistor, a first storage capacitor, a collecting unit, a writing unit and a light-emitting unit; wherein, a source of the driving transistor is connected with an input terminal for a power supply voltage; a first terminal of the first storage capacitor is connected with a gate of the driving transistor; the collecting unit is connected with an input terminal for a first scan signal, an input terminal for a controllable low voltage, the driving transistor, the first terminal of the first storage capacitor, the writing unit and the light-emitting unit, respectively, and is used for collecting a threshold voltage of the driving transistor and storing the threshold voltage into the first storage capacitor, under the control of the first scan signal; the writing unit is connected with an input terminal for a second scan signal, an input terminal for a data voltage, the input terminal for the controllable low voltage, a second terminal of the first storage capacitor and the collecting unit, respectively, and is used for storing the data voltage inputted from the input terminal for the data voltage under the control of the second scan signal; and the light-emitting unit is connected with an input terminal for a light-emitting control signal, a drain of the driving transistor and the collecting unit, respectively, and is used for emitting lights driven by the data voltage and a voltage inputted from the input terminal for the controllable low voltage, under the control of the light-emitting control signal, wherein the collecting unit comprises: a second transistor, a fourth transistor and a fifth transistor; a source of the second transistor is connected with the drain of the driving transistor, a gate of the second transistor is connected with the input terminal for the first scan signal, and a drain of the second transistor is connected with the gate of the driving transistor; a source of the fourth transistor is connected with the second terminal of the first storage capacitor, a gate of the fourth transistor is connected with the input terminal for the first scan signal, and a drain of the fourth transistor is connected with the input terminal for the controllable low voltage; and a gate of the fifth transistor is connected with the input terminal for the first scan signal, and a drain of the fifth transistor is connected with the input terminal for the controllable low voltage; and wherein the writing unit comprises: a third transistor and a second storage capacitor; a source of the third transistor is connected with the second terminal of the first storage capacitor, a first terminal of the second storage capacitor, the source of the fourth transistor, respectively, a gate of the third transistor is connected with the input terminal for the second scan signal, and a drain of the third transistor is connected with the input terminal for the data voltage; and a second terminal of the second storage capacitor is connected with the input terminal for the controllable low voltage.