Patent ID: 9653577
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A method of forming a lateral power MOS transistor, comprising providing a substrate doped with a first dopant type having a well thereon doped a second dopant type with a semiconductor surface doped said second dopant type on said well; forming dielectric isolation regions at least partially in said semiconductor surface having gaps defining a first active area in a first dielectric gap region (first MOAT) and a second active area in a second dielectric gap region (second MOAT); forming a buried drift layer (BDL) doped said first dopant type having a diluted BDL portion (DBDL) including a plurality of dilution stripes, comprising: forming a drain comprising a plurality of drain fingers having drain fingertips in said second MOAT interdigitated with a source comprising a plurality of source fingers having source fingertips in said first MOAT each doped said second dopant type; wherein said DBDL is within a fingertip drift region (FDR) associated with at least one of said drain fingertips (drain FDR) and said source fingertips (source FDR) between said first MOAT and said second MOAT, and forming at least a first gate stack on said semiconductor surface between said source and said drain.