Patent ID: 9536777
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method comprising: bonding a first semiconductor chip on a second semiconductor chip, wherein: depositing a first hard mask layer over a non-bonding side of the first semiconductor chip; depositing a second hard mask layer over the first hard mask layer; patterning the first hard mask layer and the second hard mask layer to form a hard mask pattern; after patterning the first hard mask layer and the second hard mask layer to form the hard mask pattern, etching the first substrate using the first hard mask layer and the second hard mask layer as a first mask; removing the entire second hard mask layer; etching the plurality of first inter-metal dielectric layers and the plurality of second inter-metal dielectric layers to form a plurality of openings, wherein the first hard mask layer is used as a second mask to form a first opening of the plurality of openings in an upper portion of the plurality of first inter-metal dielectric layers and the plurality of first interconnect structures are used as a third mask to form a second opening of the plurality of openings in a lower portion of the plurality of first inter-metal dielectric layers and an upper portion of the plurality of second inter-metal dielectric layers; and plating a conductive material in the plurality of openings.