Patent ID: 9654277
Date: 2017-05-16
CPC Classifications: G06F,H04J,H04L

Claim:
1. A clock generation apparatus, comprising: a clock determination unit which determines whether a cycle shift time between a first clock signal and a second clock signal satisfies a predetermined condition; and a clock switching unit which switches said first clock signal and said second clock signal based on determination of said clock determination unit; a clock bus to which an active system clock signal is outputted, wherein said clock switching unit carries out switching so as to make one clock signal among said first clock signal and said second clock signal be said active system clock signal to be outputted to outside, and the other clock signal be a stand-by system clock signal to be restrained inside, wherein said clock determination unit determines that a clock signal outputted to said clock bus can be switched when, as said predetermined condition, a first condition that said cycle shift time is equal to or more than a period from a setup start time to a hold end time of a signal specified for said clock bus and a second condition that said cycle shift time exists before a next setup start time are satisfied together.