Patent ID: 9647009
Date: 2017-05-09
CPC Classifications: G02F,H01L

Claim:
1. A thin-film transistor (TFT) array substrate structure, comprising: a backing plate, a patterned metal light-shielding layer formed on the backing plate, a first insulation layer covering on the patterned metal light-shielding layer, a plurality of TFTs formed on the first insulation layer and arranged in an array, a planarization layer covering the TFTs, a common electrode formed on the planarization layer, a protection layer covering on the common electrode, and a patterned pixel electrode formed on the protection layer; the TFTs each comprising a semiconductor layer formed on the first insulation layer, a gate insulation layer covering on the semiconductor layer, a gate electrode arranged on the gate insulation layer and located above the semiconductor layer, an interlayer dielectric layer formed on the gate electrode and the gate insulation layer, and a source electrode and a drain electrode formed on the interlayer dielectric layer; the patterned metal light-shielding layer comprising a plurality of metal light-shielding blocks arranged in an array and a narrowed metal strip connected between two adjacent ones of the metal light-shielding blocks, each of the metal light-shielding blocks being arranged to correspond to and located under one of the semiconductor layers; the metal light-shielding layer and the common electrode being both connected to and receiving a common voltage signal, the pixel electrode being set in engagement with the drain electrode of the TFT; wherein for each of the TFTs, the pixel electrode has a portion overlapping the common electrode to form first storage capacitor and the metal light-shielding layer has a portion overlapping the drain electrode and the pixel electrode to form a second storage capacitor, the first storage capacitor and the second storage capacitor being connected in parallel.