Patent ID: 9564355
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method of forming an integrated circuit structure, the method comprising: forming a plurality of conductive lines in a first dielectric layer over a substrate, upper surfaces of the conductive lines being level with upper surfaces of the first dielectric layer, a first conductive line of the plurality of conductive lines being wider than a second conductive line of the plurality of conductive lines; after forming the conductive lines, forming a mask over the first conductive line, the second conductive line being exposed; after forming the mask, removing portions of the first dielectric layer to form an air gap adjacent opposing sides of the second conductive line, the air gap being an only air gap interposed between the first conductive line and the second conductive line; forming a second dielectric layer over the plurality of conductive lines, an uppermost boundary of the air gap being below a bottommost surface of the second dielectric layer; and forming a via connecting to the first conductive line while no via connects directly to the second conductive line having the air gap adjacent thereto.