Patent ID: 9685937
Date: 2017-06-20
CPC Classifications: H03K

Claim:
1. A CMOS pulse shrinking or stretching method comprising: providing a plurality of odd combination positions and a plurality of even combination positions on a basic element sequence which is formed from a series of basic elements; providing a plurality of homogeneous logic elements and at least one odd-positioned inhomogeneous logic element or at least one even-positioned inhomogeneous logic element for forming a pulse shrinking or stretching device; serially connecting the at least one odd-positioned inhomogeneous logic element at an associated odd combination position or serially connecting the at least one even-positioned inhomogeneous logic element at an associated even combination position to form the pulse shrinking and stretching device; and utilizing the at least one odd-positioned inhomogeneous logic element to stretch a pulse signal or utilizing the at least one even-positioned inhomogeneous logic element to shrink the pulse signal, wherein the at least one odd-positioned inhomogeneous logic element and the at least one even-positioned inhomogeneous logic element are arranged together to provide a neutralizer or a neutralizing function of pulse shrinking and stretching.