Patent ID: 9685449
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A dynamic memory structure, comprising: a substrate; a first strip semiconductor material disposed on said substrate and extending along a first direction; a gate standing astride said first strip semiconductor material, extending along a second direction and dividing said first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between said gate and said first strip semiconductor material; a first capacitor unit disposed on said substrate and comprising said first source terminal serving as a bottom electrode, a second dielectric layer covering said first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering said second dielectric layer to serve as a top electrode; a second strip semiconductor material disposed on said substrate and extending along said first direction, wherein said gate stands astride both said first strip semiconductor material and said second strip semiconductor material to divide said second strip semiconductor material into a second source terminal, a second drain terminal and a second channel region; said first dielectric layer sandwiched between said gate and said second strip semiconductor material; wherein a first thickness of the first dielectric layer on top surface of the first and second strip semiconductor materials is different from a second thickness of the first dielectric layer on the sidewalls of the first and second strip semiconductor material; a second capacitor unit disposed on said substrate and comprising said second source terminal serving as said bottom electrode, said second dielectric layer covering said second source terminal to serve as a second capacitor dielectric layer and said capacitor metal layer covering said second dielectric layer to serve as a second top electrode, wherein said first source terminal and said second source terminal are arranged in a staggered arrangement and said gate stands astride said first strip semiconductor material and said second semiconductor material according to shapes of said first strip semiconductor material and said second semiconductor material.