Patent ID: 9634025
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method of forming vertically-stacked memory cells, comprising: forming a first insulative material over a stack of alternating dielectric levels and conductive levels; forming a first opening through the first insulative material and through the stack of alternating dielectric levels and conductive levels; forming cavities extending into the conductive levels along sidewalls of the first opening; forming a silicon nitride liner within the first opening and extending into the cavities; forming a second insulative material over the silicon nitride liner and over the first insulative material, the second insulative material covering the first opening and not extending downwardly into the first opening to an uppermost level of the stack, a remaining portion of the first opening being beneath the second insulative material; forming select gate material over the second insulative material; forming a second opening the through the select gate material and the second insulative material, and to the remaining portion of the first opening, the first and second openings joining with one another and together forming a third opening; and after forming the third opening: