Patent ID: 9564419
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A semiconductor package structure, comprising: a substrate; a first chip disposed on the substrate, the first chip having a first landing area; a first dielectric layer disposed on the first chip; a dielectric encapsulation layer encapsulating the first chip and the first dielectric layer; a plurality of first vias penetrating through the dielectric encapsulation layer and the first dielectric layer, the plurality of first vias connecting to the first landing area of the first chip; a second chip disposed between the substrate and the first chip, the second chip having a second landing area which is not covered by the first chip; a second dielectric layer disposed between the second chip and the first chip, wherein the dielectric encapsulation layer further encapsulating the second chip and the second dielectric layer; and at least one second via penetrating through the dielectric encapsulation layer and the second dielectric layer, the at least one second via connecting to the second landing area of the second chip, wherein a number of the at least one second via is less than a number of the plurality of first vias.