Patent ID: 9548663
Date: 2017-01-17
CPC Classifications: H02M

Claim:
1. A circuitry for adjusting output voltage, which is set between an input voltage source and an internal device, comprising an output voltage converter, a first switching transistor, a second switching transistor, a third switching transistor, a logic operator, and a signal controller; wherein the output voltage converter comprises an input coil for coupling the input voltage source, and a first output coil, a second output coil and a third output coil on a secondary side; wherein the third output coil is set between the first output coil and the second output coil, and is connected in series with the first output coil and the second output coil; a voltage output terminal of the first output coil is coupled to a drain of the first switching transistor; a voltage output terminal of the second output coil is coupled to a drain of the second switching transistor; a voltage output terminal of the third output coil is coupled to a drain of the third switching transistor; the signal controller comprises a first level signal output terminal coupled to a gate of the first switching transistor, a second level signal output terminal coupled to a gate of the second switching transistor, and the input terminal coupled to the terminal of the internal device; according to a comparison made between the activating voltage of the internal device and the preset first voltage threshold and the preset second voltage threshold, the signal controller outputs the first level signal from the first level signal output terminal and outputs the second level signal from the second level signal output terminal; the logic operator comprises a first terminal coupled to the first level signal output terminal, a second terminal coupled to the second level signal output terminal, and a third terminal coupled to a gate of the third switching transistor; or the logic operator comprises the first terminal coupled to the second level signal output terminal, the second terminal coupled to the first level signal output terminal, and the third terminal coupled to the gate of the third switching transistor; according to a level of the first level signal and a level of the second level signal, the logic operator determines a level of the third level signal output to the third switching transistor from the third terminal; wherein when the first level signal and the second level signal both are high level signals or low level signals, the third level signal is the high level signal; when the first level signal is the low level signal and the second level signal is the high level signal, or the first level signal is the high level signal and the second level signal is the low level signal, the third level signal is the low level signal; a source of the first switching transistor is coupled to another terminal of the internal device, and the first switching transistor establishes or disconnects a conduction between the internal device and the first output coil in accordance to the level of the first level signal output from the first level signal output terminal, wherein an output voltage of the first output coil is output to the internal device when the conduction between the internal device and the first output coil is established; a source of the second switching transistor is coupled to the another terminal of the internal device, and the second switching transistor establishes or disconnects a conduction between the internal device and the second output coil in accordance to the level of the second level signal output from the second level signal output terminal, wherein a superimposed output voltage generated by superimposing the output voltages of the first output coil, the second output coil and the third output coil is output to the internal device when the conduction between the internal device and the second output coil is established; a source of the third switching transistor is coupled to the another terminal of the internal device, and the third switching transistor establishes or disconnects a conduction between the internal device and the third output coil in accordance to the level of the third level signal output from the logic operator, wherein a superimposed output voltage generated by superimposing the output voltages of the first output coil and the third output coil is output to the internal device when the conduction between the internal device and the third output coil is established.