Patent ID: 9576101
Date: 2017-02-21
CPC Classifications: G06F

Claim:
1. A method for designing an integrated circuit that satisfies time constraints using a processor-based design tool, the method comprising: generating an initial integrated circuit design using a cell library of component cells and the design tool, wherein at least a first component cell in the initial integrated circuit design is part of a first subset of component cells having a same function and a same footprint; performing a timing analysis on the initial integrated circuit design; determining that the initial integrated circuit design does not satisfy the time constraints; generating a modified integrated circuit design using the design tool by replacing the first component cell with a replacement component cell that (i) is part of the first subset of component cells and (ii) has a timing characteristic such that the modified integrated circuit design satisfies the time constraints, wherein the timing characteristics of the first component cell and the replacement component cell differ based on different capacitive coupling; performing the timing analysis on the modified integrated circuit design; determining whether the modified integrated circuit design satisfies the time constraints for the integrated circuit; and fabricating an integrated circuit using the modified integrated circuit design, wherein one of the first and replacement component cells is a faster component cell and the other is a slower component cell, and the slower component cell has stronger capacitive coupling than the faster component cell.