Patent ID: 9619395
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. An information processing device comprising: a main control circuit including a central arithmetic processor that executes at least first processing through at least one first program; a sub-control circuit that executes second processing independently of the first processing; a primary storage circuit that is accessible by the central arithmetic processor; and a secondary storage circuit that is accessible by the central arithmetic processor and that has an access speed to and from the central arithmetic processor that is slower than that of the primary storage circuit, wherein the first processing and the second processing are executed at a start-up time, the secondary storage circuit stores a second program used for third processing, the third processing is executed once the first processing and the second processing are both complete, the main control circuit further includes: the main control circuit determines whether or not the second processing is complete at a completion time of the first processing, when determining that the second processing is complete at a completion time of the first processing, the main control circuit reads the second program into the primary storage circuit from the secondary storage circuit via the cache memory and executes the third processing, and when determining that the second processing is not yet complete at a completion time of the first processing, the main control circuit causes the caching controller to