Patent ID: 9559059
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method, comprising: forming an opening in at least one layer of insulating material positioned above a metal contact that is conductively coupled to a transistor device so as to thereby expose at least a portion of said metal contact; performing a selective deposition process to selectively form a metal layer in said opening and on said metal contact, wherein said metal layer is not formed on a substantial portion of sidewalls of said opening during said selective deposition process; after selectively forming said metal layer on said metal contact, performing at least one anneal process to cause movement of a material of said metal layer; after performing said at least one anneal process, depositing at least one conductive material above said selectively formed metal layer so as to over-fill said opening; and performing at least one planarization process so as to remove excess materials positioned outside of said opening and thereby define a conductive via that is positioned in said opening and conductively coupled to said metal contact.