Patent ID: 9704772
Date: 2017-07-11
CPC Classifications: G01L,G06F,G06K,H01L,H05K

Claim:
1. A chip package, comprising: a chip having a substrate, a conducting pad, and a sensing device, wherein the substrate has a side surface, a first surface, and a second surface opposite to the first surface, and the side surface is connected to the first and second surfaces, and the conducting pad and the sensing device are located on the first surface, and the conducting pad protrudes from the side surface; a dam layer located on the first surface and surrounding the sensing device, wherein the dam layer has a top surface facing away from the first surface, and the top surface is exposed; a permanent adhesive layer covering the second surface, the side surface, and the conducting pad that protrudes the side surface; a support, wherein the permanent adhesive layer is between the support and the substrate, and a sidewall of the permanent adhesive layer is adjacent to a sidewall of the conducting pad and a sidewall of the support; a buffer layer located on the support; a redistribution layer located on the buffer layer and on the sidewall of the support, the sidewall of the permanent adhesive layer, and the sidewall of the conducting pad, and extending into the dam layer and not passing through the top surface of the dam layer; a passivation layer covering the redistribution layer, the buffer layer, and the conducting pad, wherein the passivation layer has an opening to expose the redistribution layer; and a conducting structure located on the redistribution layer that is in the opening of the passivation layer.