Patent ID: 9704871
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A device comprising: a semiconductor substrate having a main surface; a first wordline buried in the semiconductor substrate; a first bitline buried in the semiconductor substrate between the first wordline and the main surface of the semiconductor substrate; a first transistor including a gate, a source and a drain; the gate being electrically connected to the first wordline, and one of the source and drain being electrically connected to the first bitline; a first memory element formed over the main surface of the semiconductor substrate and electrically connected to the other of the source and drain; a bitline trench provided over the first wordline, wherein the first bitline is buried in the bitline trench; and wherein each of the bitline trench and the first bitline has a snake shape pattern and elongates in a direction substantially vertical to a first direction in which the first wordline elongates.