Patent ID: 9659136
Date: 2017-05-23
CPC Classifications: G01R,G06F,G11C

Claim:
1. A method for identifying a candidate physical defect region including a physical defect in a failing semiconductor device, the method comprising: receiving plural electrical test mismatch results reported for one or more scan chains of the failing semiconductor device; at a failure analysis computing device, generating a physical representation of a portion of the failing semiconductor device, the physical representation including a mapping of physical layout to provide location information for physical instantiations of circuit cells represented as polygon areas and physical interconnections linking the polygon areas, each circuit cell represented as a polygon area including logic circuitry that performs logical operations; identifying for each electrical test mismatch result a suspect logical region and interconnections that are electrically connected with the scan chain and correspond to the electrical test mismatch result; identifying the candidate physical defect region as one or more of a polygon area and an interconnection, the candidate physical defect region corresponding to an overlap of one or more polygon areas and interconnections in the suspect logical regions of the plural electrical test mismatch results; and displaying the candidate physical defect region as one or more of a polygon area and an interconnection in the physical representation of a portion of the failing semiconductor device.