Patent ID: 9620526
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A bottom gate channel etched thin film transistor using an oxide semiconductor layer for a channel layer, the thin film transistor being manufactured in the steps of: forming an Al-based metal film on a substrate including a gate electrode interconnection, a gate insulating film covering the gate electrode interconnection, and an oxide semiconductor layer to be a channel layer formed on the gate electrode interconnection through the gate insulating film; forming a hard mask film on the Al-based metal film; forming a resist pattern having a pattern for forming a source electrode interconnection and a drain electrode interconnection on the hard mask film; forming a first hard mask layer corresponding to a source electrode interconnection pattern for etching the hard mask film using the resist pattern for a mask and a second hard mask layer corresponding to a drain electrode interconnection pattern; after forming the first hard mask layer and the second hard mask layer, first ashing for removing the resist pattern; after the first ashing, dry etching the Al-based metal film using the first hard mask layer and the second hard mask layer for masks with a chlorine gas, forming the source electrode interconnection and the drain electrode interconnection, and exposing the oxide semiconductor layer; second ashing for removing a residual chlorine gas component after the dry etching; and forming a protective insulating film so as to cover a side wall of the source electrode interconnection, a surface of the oxide semiconductor layer, and a side wall of the drain electrode interconnection.