Patent ID: 9680527
Date: 2017-06-13
CPC Classifications: H03K,H04B

Claim:
1. A 10BASE-T Ethernet interface circuit complying with Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard for Ethernet, the interface circuit comprising: a field programmable gate array (FPGA), wherein the FPGA includes a physical layer interface module configured to exchange data with a media access controller (MAC); a transmitter circuit connected to the FPGA and configured to receive a transmission signal from the physical layer interface module, wherein the transmitter circuit comprises: a receiver circuit connected to the FPGA and configured to send a difference indication signal to the physical layer interface module, wherein the receiver circuit comprises: a transformer connected to the transmitter circuit and the receiver circuit, wherein the transformer is configured to: wherein the transmission signal comprises a positive and negative component; and