Patent ID: 9575541
Date: 2017-02-21
CPC Classifications: G06F,Y02D

Claim:
1. A microprocessor, comprising: a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource; wherein a first core of the plurality of processing cores is configured to: wherein each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction; wherein the architecturally-visible storage resource comprises an x86 architecture memory type range register (MTRR); wherein the MTRR comprises an x86 architecture variable range MTRR comprising a base register and a mask register, wherein the mask register includes a valid bit; wherein the first core, in response to encountering the architectural instruction, is further configured to: wherein to update the value, each of the plurality of processing cores updates both the base register and the mask register if the flag is set, and otherwise update only the base register or mask register as specified by the architectural instruction.