Patent ID: 9601168
Date: 2017-03-21
CPC Classifications: G11C

Claim:
1. An apparatus comprising: a plurality of data lines configured to provide respective signals within a plurality of memory cells, a data line of the plurality of data lines being divided into a plurality of data line segments; and a bidirectional buffer interposed in the data line and connecting two data line segments of the plurality of data line segments to each other, the bidirectional buffer configured to bi-directionally provide data between the two data line segments, wherein the bidirectional buffer is configured, responsive to receiving a first data signal indicative of a precharge mode, to decouple the two data line segments from each other by disabling a first transistor coupled to a first of the two data line segments and disabling a second transistor coupled to a second of the two data line segments, wherein the bidirectional buffer is configured, responsive to receiving a second data signal indicative of an operation mode, to couple the first of the two data line segments to the second of the two data line segments by enabling the first transistor and enabling a third transistor via the enabled first transistor, and wherein the third transistor is coupled to the second data line segment.