Patent ID: 9691341
Date: 2017-06-27
CPC Classifications: G09G

Claim:
1. A data driver comprising: a shift register configured to generate latch control signals based on a horizontal start signal and a data clock signal; a data latch configured to store parallel image data based on the latch control signals and to output the parallel image data based on a data load signal; a digital-to-analog converter configured to generate first data voltages and second data voltages based on the parallel image data and a polarity control signal, wherein each of the first data voltages has a positive polarity and each of the second data voltages has a negative polarity; a control signal output circuit configured to output a first output control signal and a second output control signal based on the polarity control signal, wherein a phase of the second output control signal is different from a phase of the first output control signal; and an output buffer configured to output the first data voltages based on the first output control signal and to output the second data voltages based on the second output control signal, wherein, during a single horizontal period, the phase of the first output control signal leads the phase of the second output control signal by a first period, and phases of the first data voltages lead phases of the second data voltages by the first period, and wherein a high level of the first output control signal partially overlaps a high level of the second output control signal.