Patent ID: 9640444
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, the method comprising: forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole over the first gate electrode, the first sub contact hole not exposing a first top surface of the first gate electrode and not exposing a second top surface of the second gate electrode, wherein the first sub contact hole is positioned between the PMOSFET region and the NMOSFET region when viewed in a plan view, and wherein the first sub contact hole is not positioned directly over the PMOSFET region and not positioned directly over the NMOSFET region; and after the first sub contact hole is formed over the first gate electrode, patterning the interlayered insulating layer to form a first gate contact hole and to expose the second top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.