Patent ID: 9547475
Date: 2017-01-17
CPC Classifications: G06F

Claim:
1. A random number generating circuit comprising: first to N-th oscillating circuits (N is a natural number equal to 2 or greater); first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency; first to N-th exclusive OR circuits; (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock; an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits; and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency, wherein the output of the i-th exclusive OR circuit is the exclusive OR of i-th feedback output of a subsequent circuit of the first to N-th exclusive OR circuits and the output of the i-th latch circuit (i is one of 1 to N), the second frequency is equal to or lower than the first frequency, each of the first to N-th oscillating circuits includes a NOR circuit into which a first control signal is input and an exclusive OR circuit into which a second control signal and the output of the NOR circuit are input and which outputs an oscillating signal, and the oscillating signal is input into the NOR circuit as a feedback signal.