Patent ID: 9543029
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A non-volatile semiconductor memory device comprising: a memory cell; a bit line electrically connected to the memory cell; a sense amplifier electrically connected to the bit line, the sense amplifier including a latch unit configured to hold data read from the memory cell and transmitted through the bit line and a first node, a first transistor having a first end electrically connected to the latch unit and a second end electrically connected to the first node, a second transistor having a first end electrically connected to the first node and a second end electrically connected to the bit line, a third transistor having a first end electrically connected to a second node between the first end of the first transistor and the latch unit; and a control unit that controls the sense amplifier during a read operation, to charge the second node to a first voltage by turning on the first transistor for a period of time, and then, while the first transistor is in an off state, charge the first node to a second voltage, turn on the second transistor after charging the first node to the second voltage, and turn on the third transistor after turning on the second transistor.