Patent ID: 9535834
Date: 2017-01-03
CPC Classifications: G06F,G11C

Claim:
1. An electronic device including a semiconductor memory unit, wherein the semiconductor memory unit comprises: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit, wherein the first cell array includes a plurality of first storage cells each having a variable resistance element and being selected when a corresponding word line is activated among the plurality of word lines, and a first reference resistance element having a first resistance value and being arranged adjacent to the word line driving unit; a second cell array arranged at the other side of the word line driving unit, wherein the second cell array includes a plurality of second storage cells, each having a variable resistance element and being selected when a corresponding word line is activated among the plurality of word lines, and a second reference resistance element having a second resistance value and being arranged adjacent to the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit for reading data of first storage cells selected among the plurality of first storage cells based on the bias voltage; and a second read control unit for reading data of second storage cells selected among the plurality of second storage cells based on the bias voltage, wherein the first and second read control units generate a reference current based on the bias voltage, compares the currents flowing through the selected first and second storage cells with the reference current to read the data of the selected first and second storage cells.