Patent ID: 9627376
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: first and second memory cells and adjacent to each other with no intervening memory cell on a substrate, wherein each of the first and second memory cells have an odd number of active fins; at least one active base and a shallow trench isolation sequentially laminated at a boundary between the first and second memory cells; first and second active fins on respective sides of the shallow trench isolation, the first and second active fins projecting from the active base; a gate electrode; and at least one deep trench isolation on one side of the active base, wherein the first active fin is in the first memory cell and the second active fin is in the second memory cell, wherein the first and second active fins extend in a first direction along the boundary between the first and second memory cells, and wherein the gate electrode extends from the first and second active fins in a second direction that crosses the first direction, wherein the first and second memory cells are symmetrically arranged with respect to each other relative to the boundary.