Patent ID: 9728635
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method of fabricating a vertical field effect transistor (VFET), the method comprising: forming a doped layer on a substrate; forming a base layer on the doped layer; forming fin hard masks above the base layer, wherein a space between two of the fin hard masks is different than a second space between two others of the fin hard masks; forming uniform spacers adjacent to each side of each of the fin hard masks above the base layer, wherein a width dimension of each of the uniform spacers is substantially the same; filling first gaps between the uniform spacers with oxide prior to removing the uniform spacers, wherein the removing the uniform spacers leaves second gaps of substantially the same width on each side of each of the fin hard masks; and performing an etch in the second gaps to form a plurality of fins below the fin hard masks, wherein a height dimension of each of the plurality of fins is substantially the same and a space between two of the plurality of fins is different than a second space between two others of the plurality of fins.