Patent ID: 9740494
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. An instruction issue circuit, comprising: an instruction queue operable to store a plurality of instructions so that the plurality of instructions are ordered in accordance with an instruction execution priority, wherein the instruction queue further comprises a plurality of queue entries operable to store the plurality of instructions, wherein each queue entry of the plurality of queue entries is configured to store a different corresponding instruction of the plurality of instructions so that each different corresponding instruction of the plurality of instructions includes one or more register fields, each of the one or more register fields identifies a register among a plurality of registers so that a register value stored by the register is used as an operand of the different corresponding instruction of the plurality of instructions; a ready generation circuit operably associated with the instruction queue to generate a plurality of ready signals, wherein the ready generation circuit is configured to: a plurality of group blocks for generating a plurality of group outputs, each group block of the plurality of group blocks being operable to: a global instruction block configured to: a shifter that is configured to generate a plurality of one-hot outputs in response to the global grant output, wherein each one-hot output of the plurality of one-hot outputs indicates in which of the plurality of queue entries each of a residual set of the plurality of instructions is to be stored once the global set of the plurality of instructions has been issued for execution and thereby maintain the instruction execution priority of the plurality of instructions.