Patent ID: 9535121
Date: 2017-01-03
CPC Classifications: G01R

Claim:
1. An apparatus comprising: functional circuitry for performing functional operations; and test logic coupled to the functional circuitry to enhance timing delay fault coverage for the functional circuitry with at-speed test sequences, the test logic includes a plurality of partitions of scan flip-flops and an independent partition scan enable input signal for each partition for enabling or disabling each partition; wherein the plurality of partitions are arranged in scan chains configured with alternate or adjacent flip-flops selected from first and second partitions, the test logic configured to enable the first partition and disable the second partition during a first test sequence and to disable the first partition and enable the second partition during a second test sequence, the test logic configured to enable scanning in second test data from one of the first and second partitions into the other of the first and second partitions while the other of the first and second partitions outputs first test data to a portion of the functional circuitry.