Patent ID: 9553684
Date: 2017-01-24
CPC Classifications: H04J

Claim:
1. A data frame generation circuit, comprising: an input terminal configured to receive client signals; a storage configured to store a signal count range; and a processor configured to: generate a first data frame by storing the client signals from the input terminal in the first data frame in accordance with a system clock; output the first data frame including the client signals and a first signal count of the client signals included in the first data frame; compare the first signal count to a signal count range; and change a frequency of the system clock such that a second signal count of the client signals, which is included in a second data frame to be generated after generating the first data frame by storing the client signals from the input terminal in the second data frame in accordance with a changed system clock, is not within the signal count range when detecting that the first signal count falls within the signal count range, wherein the processor is configured to set a first difference between the first signal count and the second signal count so that the first difference becomes greater than a second difference between an upper limit value and a lower limit value of the signal count range.