Patent ID: 9646952
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A microelectronic package, comprising: a microelectronic interposer having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface; at least one microelectronic device attached to the microelectronic interposer first surface; an encapsulation material disposed over the at least one microelectronic device and the microelectronic interposer, wherein the encapsulation material includes at least one side which is substantially planar to the at least one microelectronic interposer side and wherein the at least one encapsulation material side and the at least one microelectronic interposer side comprise a microelectronic package side; and at least one exposed debug access port formed proximate the least one of the microelectronic package side and the microelectronic interposer second surface, wherein the exposed debug access port is electrically connected to the at least one microelectronic device.