Patent ID: 9679876
Date: 2017-06-13
CPC Classifications: G06F,G11C,H01L,H05K,Y02P

Claim:
1. A microelectronic package configured to be joined with contacts of a single component external to the microelectronic package, comprising: a substrate having first and second opposed surfaces and substrate contacts exposed at the first surface, the substrate defining first, second, third, and fourth peripheral edges; at least two stacks of semiconductor chips joined with the substrate in an area bounded by the first, second, third and fourth peripheral edges, each stack of semiconductor chips including an upper semiconductor chip and a lower semiconductor chip, the stacks of semiconductor chips being spaced apart from one another in a horizontal direction parallel to the first surface of the substrate, each semiconductor chip having a front face facing away from the first surface, a rear face opposite the front face, and contacts at the front face, the front face of each of the lower semiconductor chips being arranged parallel to the first surface, the rear face of each of the upper semiconductor chips at least partially overlying the front face of the lower semiconductor chip in its stack, and the semiconductor chips together configured to predominantly provide memory storage array function; conductive structure extending above the front faces electrically connecting element contacts of each of the semiconductor chips of the at least two stacks of semiconductor chips with the substrate contacts; and a plurality of terminals exposed at the second surface and electrically connected with the substrate contacts, the terminals including first and second groups of data terminals, each of the first and second groups having at least eight data terminals disposed on first and second opposite sides of an axis, respectively, wherein each of the data terminals of the first and second groups are configured to carry data signals for read and write access to random access addressable memory locations of a memory storage array within one or more of the semiconductor chips, and the data terminals of the first group have modulo-X symmetry about the axis with the second group of the data terminals, wherein X is an integer, wherein X is greater than two.