Patent ID: 9564460
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A manufacturing method of a thin film transistor, comprising: sequentially forming a pattern of gate, a gate insulation layer film, an active layer film and an ohmic contact layer film on a substrate; forming a first etching resist module, which covers a channel region to be formed, on the ohmic contact layer film; forming a source and drain metallic layer film on the substrate formed with the first etching resist module; forming a pattern comprising a source and drain in the source and drain metallic layer film by wet etching process through shielding the active layer film and the ohmic contact layer film positioned within the channel region to be formed, by use of the first etching resist module; and forming a pattern of an ohmic contact layer in the ohmic contact layer film and forming a pattern of the active layer in the active layer film, by dry etching process.