Patent ID: 9666588
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A method for forming floating gate transistors, said method comprising: forming a dielectric layer over a substrate, said dielectric layer including oxide portions and nitride portions, said nitride portions and oxide portions having coplanar upper surfaces; recessing said oxide portions in a first region that includes said nitride portions such that said nitride portions protrude above recessed oxide portions in said first region; and thereafter, removing sections of said nitride portions to form openings in said first region, wherein each said opening comprises a two-tiered opening with a central portion having a bottom terrace and an upper terrace adjacent said central portion; forming floating gate electrodes by depositing polysilicon that fills said openings in said dielectric layer, each said opening having a bottom including a tunnel oxide disposed over a substrate; forming a recess in each said floating gate electrode, each said recess including sidewalls and a bottom surface within said floating gate electrode; forming a floating gate dielectric layer along said sidewalls and said bottom surface of each of said recesses; and forming a control gate electrode on said floating gate dielectric layer and filling each of said recesses.