Patent ID: 9612750
Date: 2017-04-04
CPC Classifications: G06F,G11C

Claim:
1. A memory apparatus comprising: a first autonomous memory device; a second autonomous memory device physically coupled to the first autonomous memory device, at least one of the first and second autonomous memory devices including a scratch pad memory port to couple a memory that is external to the first and second autonomous memory devices, each of the first and second autonomous memory devices including a configuration routing table to keep track of other autonomous memory devices in the memory apparatus, the configuration routing table to store latency cost based on location of an autonomous memory device among the autonomous memory devices communicating with another autonomous memory device among the autonomous memory devices, wherein the first autonomous memory device is configured to initiate instructions to disperse portions of a database to the second autonomous memory device; and a controller having a condition monitoring block to monitor bus traffic between the first and second autonomous memory devices.