Patent ID: 9627274
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method of forming a FinFET device, comprising: forming a first sacrificial layer comprising amorphous silicon or polysilicon material around a fin in a lateral space between a plurality of laterally spaced apart gate structures that are positioned around said fin; forming a first layer of material adjacent said plurality of laterally spaced apart gate structures; performing a first selective etching process to remove said first sacrificial layer selectively relative to said plurality of laterally spaced apart gate structures, said first layer of material and said fin so as to expose said fin in said lateral space; forming an epi semiconductor material on said exposed portion of said fin; forming a second layer of a sacrificial material between said laterally spaced apart gate structures and above said epi semiconductor material; performing at least one second etching process to selectively remove said second layer of sacrificial material relative to at least said first layer of material to thereby define a source/drain contact opening that exposes said epi semiconductor material; and performing at least on process operation to form a self-aligned trench conductive source/drain contact structure in said source/drain contact opening that is conductively coupled to said epi semiconductor material.