Patent ID: 9625526
Date: 2017-04-18
CPC Classifications: G01R,G06F

Claim:
1. Processing logic circuit for use in a computing system, wherein the processing logic circuit has a State Retention Power Gating logic circuit having at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state, said processing logic circuit comprising: a memory coupled to the State Retention Power Gating logic circuit and operable to store a collected state information about the at least a portion of the processing logic circuit; and a further logic circuit coupled to the memory and operable to rearrange the collected state information data for scan chains shorter than a longest scan chain within the at least a portion of the processing logic circuit, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.