Patent ID: 9620203
Date: 2017-04-11
CPC Classifications: G11C

Claim:
1. A semiconductor integrated circuit comprising: a memory cell including first and second electrodes and a resistance change film therebetween, the resistance change film being reversibly changeable between first and second resistive states; and a control circuit controlling a potential difference between the first and second electrodes, wherein the control circuit reversibly changes the memory cell to the first resistive state by applying a first potential to the first electrode and by applying a second potential smaller than the first potential to the second electrode, the control circuit reversibly changes the memory cell to the second resistive state by applying a third potential to the first electrode and by applying a fourth potential smaller than the third potential to the second electrode, and the control circuit irreversibly fixes the memory cell to a third resistive state by applying a fifth potential to the first electrode and by applying a sixth potential greater than the fifth potential to the second electrode.