Patent ID: 9727471
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A processor comprising: an instruction fetch unit to fetch an instruction of an instruction set of the processor, the instruction having a format that includes a first parameter to indicate a source memory address, a second parameter to indicate a different destination memory address which is different than the source memory address, and a third parameter to specify a memory hierarchy level for the destination memory address; and an execution unit to perform the instruction, wherein the execution unit to perform the instruction is to: perform a first operation to read data from the source memory address into a buffer of the processor without allocating a cache memory line to store the data; and perform a second operation to allocate a cache memory line at the destination memory address, and to store the data from the buffer of the processor to the allocated cache memory line, wherein the cache memory line is to be allocated in a cache memory that is to be based at least in part on the memory hierarchy level that is to be specified by the third parameter of the instruction.