Patent ID: 9620469
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a contact pad over a substrate; a passivation layer over the substrate and a first portion of the contact pad, wherein a second portion of the contact pad is exposed through an opening; a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad; and a bump over the post-passivation interconnect layer and outside of the opening, wherein the bump has an inner portion and a diffusion barrier region enclosing an entirety of the inner portion, the diffusion barrier region physically insulates the inner portion of the bump from the post-passivation interconnect layer while electrically connecting the inner portion of the bump to the post-passivation interconnect layer, the inner portion of the bump is made of a metal material, and the diffusion barrier region of the bump is made of the metal material doped with a dopant.