Patent ID: 9659946
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a pair of spaced apart conductive floating gates that include inner sidewalls that face each other, wherein the floating gates are disposed over and insulated from a substrate of first conductivity type; a pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, wherein each of the control gates includes opposing inner and outer sidewalls, and wherein the inner sidewalls of the control gates face each other; a pair of first spacers of insulation material extending along the inner sidewalls of the control gates and disposed over the floating gates, wherein the inner sidewalls of the floating gates are aligned with side surfaces of the pair of first spacers; a pair of second spacers of insulation material each extending along one of the first spacers and along the inner sidewall of one of the floating gates; a trench formed into the substrate having sidewalls that are aligned with side surfaces of the pair of second spacers; silicon carbon disposed in the trench; and material implanted into the silicon carbon forming a first region therein having a second conductivity type.