Patent ID: 9595579
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A structure for a filed effect transistor (FET) comprising: a deep n-type well in a substrate; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region at least partially within the shallow n-type well, the STI region including: a plurality of first sections within the deep n-type well, each of the plurality of first sections being laterally separated from an adjacent first section by a respective portion of the deep n-type well, and a second section within the shallow n-type well and contacting each of the plurality of first sections, wherein the second section overlies and extends laterally beyond each of the plurality of first sections, wherein the second section includes a lower surface contacting and overlying the deep n-type well, and a gate region disposed directly over portions of all the plurality of the first sections.