Patent ID: 9570180
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a first block including a first memory string that includes a first memory cell transistor and a first select transistor; a second block including a second memory string that includes a second memory cell transistor and a second select transistor; a first select gate line that is electrically connected to a gate of the first select transistor; and a second select gate line that is electrically connected to a gate of the second select transistor, wherein during writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.