Patent ID: 9536808
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a conductive bottom substrate layer; an inter-metal dielectric layer disposed on the conductive bottom substrate layer, wherein the inter-metal dielectric layer defines a via with the conductive bottom substrate layer and surrounded by the inter-metal dielectric layer, wherein the via comprises a conductive via material in contact with a portion of the conductive bottom substrate layer; and a conductive top layer disposed on the inter-metal dielectric layer and the conductive via material, wherein the portion of the conductive bottom substrate layer in contact with the conductive via material is isolated from adjacent portions of the conductive bottom substrate layer, wherein the portion of the conductive bottom substrate layer in contact with the conductive via material is larger than the via, thereby providing an inter-metal dielectric boundary around the entire via above the portion of the conductive bottom substrate layer in contact with the conductive via material, and wherein the via has a via area mask open ratio of at least 90% to a via mask to define the via.