Patent ID: 9553176
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: forming a first conductive layer on a substrate, the first conductive layer comprising a gate and a first electrode; forming a first insulating layer to cover the first conductive layer; forming a semiconductor layer on the first insulating layer, the semiconductor layer comprising an active layer and an etching stop layer; forming a second insulating layer on the semiconductor layer; patterning the second insulating layer to form a first opening, a second opening and a third opening, the first opening and the second opening exposing the active layer, and the third opening exposing the etching stop layer; forming a protecting auxiliary layer comprising a first protecting pattern layer located on the active layer and a second protecting pattern layer located on the etching stop layer, wherein the first opening, the second opening pass through the first protecting pattern layer, and the third opening pass through the second protecting pattern layer, each of side-walls of the first protecting pattern layer is respectively aligned with one of side-walls of the active layer, and each of side-walls of the second protecting pattern layer is respectively aligned with one of side-walls of the etching stop layer, and wherein the protecting auxiliary layer and the second insulating layer have different patterns; and forming a second conductive layer on the second insulating layer, the second conductive layer comprising a source, a drain and a second electrode, the source and the drain contacting with the active layer and the first protecting pattern layer through the first opening and the second opening, and the second electrode contacting with the etching stop layer and the second protecting pattern layer through the third opening.