Patent ID: 9711396
Date: 2017-07-18
CPC Classifications: C23C,H01L

Claim:
1. A method of forming a metal-insulator-semiconductor (MIS) source/drain contact structure on a source/drain region of a substrate surface, the method comprising: providing a substrate comprising a source/drain region comprising a semiconductor surface; depositing a metal chalcogenide thin film directly over the source/drain region; and depositing a metal layer over the metal chalcogenide thin film to thereby form the metal-insulator-semiconductor (MIS) source/drain contact structure; wherein the metal chalcogenide thin film comprises at least one of the following: BeS, MgS, CaS, SrS, BaS, NiS, ZnS, CdS, InS, BeSe, MgSe, CaSe, SrSe, BaSe, NiSe, ZnSe, CdSe, InSe, BeTe, MgTe, CaTe, SrTe, BaTe, NiTe, ZnTe, CdTe, and InTe; and wherein the MIS source/drain contact structure has a Schottky barrier height (SBH) of less than 0.11 eV.