Patent ID: 9552455
Date: 2017-01-24
CPC Classifications: G06F

Claim:
1. A method of designing and analyzing CMOS digital circuitry based on a characterization of a CMOS design cell library, the method comprising: a) determining electromigration current limits of design cells of said CMOS design cell library without including device-level self-heating effects; b) determining a thermal resistivity of the design cells based on data provided by said CMOS design cell library for the design cells; c) determine temperature changes for the design cells for a specified voltage based on the determined electromigration current limits and the determined thermal resistivity; d) computing a universal scaling curve of allowance reduction of electromigration current limits due to device level self heating effects as a function of temperature changes; and e) applying the computed universal scaling curve to the determined temperature changes to determine reductions to said electromigration current limits of said design cells due to said self heating effects.