Patent ID: 9639640
Date: 2017-05-02
CPC Classifications: G06F

Claim:
1. A method of generating delay values for circuit elements in a clock network of a programmable IC, comprising: determining from a specification of the programmable IC, respective locations of a plurality of clock test buffers and a plurality of test delay circuits on the programmable IC; determining with a computer processor for each clock resource in the clock network, different possible contexts of the clock resource, wherein each context specifies a combination of possible types of circuit elements of the programmable IC that are configurable for use with the clock resource; selecting circuit elements of the programmable IC of the possible types from the different contexts; generating configuration data for implementation of respective ring oscillator circuits that include the selected circuit elements on the programmable IC, wherein each ring oscillator circuit includes one of the selected circuit elements coupled between one of the plurality of clock test buffers and one of the plurality of test delay circuits; configuring the programmable IC with the configuration data that specifies the respective ring oscillator circuits including the selected circuit elements; operating the programmable IC with the respective ring oscillator circuits and determining respective delay values of the selected circuit elements from respective maximum frequencies of the ring oscillator circuits; and storing the delay values in association with identifiers of the selected circuit elements in a memory arrangement.