Patent ID: 9620527
Date: 2017-04-11
CPC Classifications: G02F,H01L

Claim:
1. An array substrate comprising: a base substrate, and a gate line and a data line which are provided on the base substrate to be intersected with each other, wherein the gate line and the data line define a pixel unit, the pixel unit is provided with a thin film transistor therein, the thin film transistor includes a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode, the gate insulation layer includes a first gate insulation portion and a second gate insulation portion, the gate electrode is located between the first gate insulation portion and the second gate insulation portion, the second gate insulation portion is located between the gate electrode and the active layer; a conductive pad located at an intersection position of the gate line and the data line; and a first via corresponding to the conductive pad provided in the gate insulation layer at both sides of the gate line, wherein the data line is connected to the conductive pad through the first via, wherein, in a direction perpendicular to base substrate, the gate line and the data line are disposed in different layers and overlapped with each other, the conductive pad and the source electrode are disposed in different layers, and the first gate insulation portion is located between the gate line and the conductive pad.