Patent ID: 9740557
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A pipelined Error Correction Code (ECC) memory access method, in which a plurality of transactions are overlapped in time, comprising: while in a normal mode, processing a memory transaction by speculatively comparing a set of tags retrieved from a tag RAM with a portion of an address supplied with the memory transaction, and initializing a speculative read from a cache location associated with a tag from the set that matched to the portion of the address, while an ECC operation is being performed for the set of tags; while in an error condition mode, processing a memory transaction by first completing an ECC operation on a set of tags retrieved from the tag RAM for that memory transaction and then initiating a comparison using tag data resulting from the ECC operation with a portion of an address supplied with the memory transaction and reading a cache location associated with a tag from the set that matched to the portion of the address; entering the error condition mode, in response to an ECC operation indicating a correctable error in a set of tags for a memory transaction being processed; and resetting to the normal mode in response to detecting a gap of at least a predetermined size between memory transactions of said plurality of transactions; wherein reading from the cache is processed as though a tag used in the read was corrected regardless of whether any tag error was corrected when the ECC operation was performed.