Patent ID: 9690650
Date: 2017-06-27
CPC Classifications: G06F,G11B,G11C

Claim:
1. A device comprising: a memory array storing data and error correcting codes ECCs corresponding to the data, the memory array including a plurality of data lines for page mode operations; an input/output data path; a multi-level buffer structure between the memory array and the input/output data path, wherein the buffer structure includes a first page buffer having storage cells connected to respective data lines in the plurality of data lines, a second page buffer connected through a first bidirectional data path to the storage cells in the first page buffer, and a third buffer connected through a second bidirectional data path to the second page buffer and to the input/output data path, the second page buffer and the third buffer including storage cells, the first page buffer and the second page buffer having respective widths of at least one page width; and control logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations, wherein the third buffer comprises a first memory unit coupled to the second page buffer by a storage bus and a second memory unit coupled to the second page buffer by said storage bus or by a second storage bus, and including logic to move data from the second page buffer to one of the first memory unit and the second memory unit, while moving data from another of the first memory unit and the second memory unit to the input/output data path.