Patent ID: 9627360
Date: 2017-04-18
CPC Classifications: G01R,G11C,H01L,H05K,Y10T

Claim:
1. An electronic device comprising: a printed circuit board (PCB) including: a substrate; a plurality of external pads configured to be coupled to external devices; a plurality of first-type terminal pads formed on a first surface of the substrate; a plurality of second-type terminal pads formed on the first surface of the substrate; a plurality of bypass pads for testing an electric circuit of the semiconductor device; a plurality of first-type circuit patterns configured to electrically connect the plurality of first-type terminal pads and the plurality of external pads; a plurality of second-type circuit patterns configured to electrically connect the plurality of second-type terminal pads and the plurality of bypass pads; and a solder resist layer covering the plurality of bypass pads, an entire bottom surface of the solder resist layer being flat, the bottom surface not contacting the substrate; a first memory chip disposed on the substrate and including a first portion and a second portion, the first memory chip including a first chip pad on the second portion; a logic chip stacked on the first portion of the first memory chip and including a second chip pad that is connected to a third chip pad through a bonding wire, the third chip pad being disposed on the substrate; and a row of passive devices disposed on the substrate, wherein the logic chip is not stacked on the second portion of the first memory chip, the solder resist layer covers an entire first portion of a second surface of the substrate, the second surface of the substrate being opposite to the first surface of the substrate, the first portion of the second surface of the substrate being a remaining portion other than a second portion of the second surface of the substrate, the second portion of the second surface of the substrate being a portion between a first edge of the second surface of the substrate and first ends of the plurality of external pads, second ends of the plurality of external pads being disposed along the first edge of the second surface of the substrate and being opposite ends to the first ends of the plurality of external pads, a first thickness of a third portion of the solder resist layer is different from a second thickness of a fourth portion of the solder resist layer, the third portion of the solder resist layer being a portion directly below which the plurality of bypass pads are disposed, the fourth portion of the solder resist layer being a remaining portion other than the third portion of the solder resist layer, the first thickness of the third portion of the solder resist layer is between the plurality of bypass pads and the bottom surface of the solder resist layer, and the second thickness of the fourth portion of the solder resist layer is between the second surface of the substrate and the bottom surface of the solder resist layer.