Patent ID: 9613689
Date: 2017-04-04
CPC Classifications: G11C,H01L

Claim:
1. A three-dimensional memory device comprising: an alternating stack of word lines and insulating layers; a plurality of gate lines; a plurality of global bit lines; a plurality of local bit lines vertically extending through the alternating stack, wherein each local bit line of the plurality of local bit lines contacts a respective one of the plurality of gate lines and a respective one of the plurality of global bit lines; a plurality of memory elements located at each overlap region between the word lines and the local bit lines; a plurality of diodes, wherein each of the plurality of diodes is located in electrical series between each of the local bit lines and the respective one of the plurality of gate lines; and a plurality of selector elements, wherein each of the plurality of selector elements is located in electrical series between each of the local bit lines and the respective one of the plurality of global bit lines, and wherein the plurality of selector elements comprise a material that provides a conductivity change of at least one order of magnitude upon application of a voltage.