Patent ID: 9653576
Date: 2017-05-16
CPC Classifications: B82Y,H01L

Claim:
1. A method of forming a nanowire transistor on a substrate, the method comprising: forming a guide opening in a mask layer disposed over a dielectric layer disposed over a doped semiconductor layer disposed over a substrate; depositing a directed self-assembly (DSA) material into the guide opening; segregating the DSA material into a first interior polymer region and a second interior polymer region, the first interior polymer region and the second interior polymer region completely surrounded by an exterior polymer region within the guide opening; removing the first interior polymer region and the second interior polymer region selectively to the exterior polymer region to form a first opening and a second opening; forming a first trench and a second trench in the dielectric layer and the doped semiconductor layer, wherein the first trench and the second trench are defined by the first opening and the second opening, respectively; removing the mask layer and a peripheral portion of the dielectric layer beneath the mask layer to form an annular portion of the dielectric layer surrounding the first trench and the second trench; removing the exterior polymer region; forming a first source/drain semiconductor material in the first trench and in the second trench; forming a channel semiconductor material on the first source/drain semiconductor material in the first trench and in the second trench; forming a second source/drain semiconductor material on the channel semiconductor material in the first trench and in the second trench; removing at least a portion of the annular portion of the dielectric layer surrounding the first trench and the second trench to form a gate trench surrounding the channel semiconductor material; and forming a gate electrode in the gate trench.