Patent ID: 9666532
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A memory device on a substrate, comprising: a stack of conductive layers, each of the layers being oriented parallel to the substrate; a plurality of parallel bit line conductors parallel to the substrate; a plurality of pillars oriented orthogonally to the substrate; a plurality of memory cells located at cross-points between the pillars and the conductive layers, wherein the pillars in the plurality of pillars are arranged on a regular grid in which rows are oriented orthogonally to the bit line conductors, the regular grid having a unit cell of four of the pillars A, B, C and D located at vertices of a parallelogram, a plurality of string select lines oriented parallel to the substrate, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective select gate of the pillar, and each intersection of one of the string select lines and one of the bit line conductors uniquely identifying a single one of the pillars in the plurality, wherein the string select lines comprise rectangles having a long dimension oriented orthogonally to the bit line conductors, wherein the plurality of bit line conductors are orthogonal to a direction from pillar A to pillar D, wherein a center-to-center distance between pillar A and pillar B is not equal to a center-to-center distance between pillar A and pillar D, and wherein a particular one of the string select lines has a short dimension which is sufficiently large that the particular string select line intersects at least three of the rows of pillars.