Patent ID: 9697874
Date: 2017-07-04
CPC Classifications: G11C,H01L

Claim:
1. An integrated circuit, comprising: a substrate comprising a plurality of metal oxide semiconductor (MOS) devices formed at least in part within the substrate; a set of layers overlying the substrate and the MOS devices and facilitating electrical interconnection of two or more of the plurality of MOS devices, the set of layers comprising at least two layers; a first array of two-terminal memory devices formed among a first subset of the set of layers, wherein the first array of two-terminal memory devices is formed in a one-transistor, multiple-resistor (1TnR, where n is an integer greater than 1) array architecture; and a second array of two-terminal memory devices formed among a second subset of the set of layers, wherein the second array of two-terminal memory devices is formed in a one-transistor, one-resistor (1T1R) array architecture, and wherein the first array of two-terminal memory devices and the second array of two-terminal memory devices share a common layer.