Patent ID: 9583485
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A method for forming a fin field effect transistor (FinFET) device structure, comprising: forming a fin structure over a substrate, wherein the substrate comprises a first region and a second region; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an inter-layer dielectric (ILD) structure over the substrate and adjacent to the first dummy gate structure and the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first trench and a second trench in the ILD structure; forming a first gate structure in the first trench and a second gate structure in the second trench, wherein the first gate structure comprises a first work function layer, and the second gate structure comprises a second work function layer; performing a first plasma operation on the first work function layer and the s_econd work function layer for a first period of time; and performing a second plasma operation at zero bias power on the first work function layer and the second work function layer for a second period of time such that after performing the first plasma operation and the second plasma operation, the first work function layer has a first height, and the second work function layer has a second height, and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm.