Patent ID: 9588840
Date: 2017-03-07
CPC Classifications: G06F

Claim:
1. A method of operating a memory device, the method comprising: receiving a masked write command and an address signal; generating, in response to the masked write command, an internal read command during a write latency associated with the masked write command; receiving a plurality of pieces of masked write data after expiration of the write latency; reading, in response to the internal read command, a plurality of pieces of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal and the plurality of memory cells being configured to store the plurality of pieces of masked write data; performing error detection and correction on the plurality of pieces of data; generating an internal write command after input of a last piece of masked write data among the plurality of pieces of masked write data; and storing, in response to the internal write command, the plurality of pieces of masked write data in the plurality of memory cells.