Patent ID: 9735110
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate; a first etching stopper film formed on the semiconductor substrate; a first wiring layer formed on the first etching stopper film; a first trench being within the first etching stopper film and the first wiring layer; a diffusion preventing/etching stopper film; an interlayer dielectric film formed on the diffusion preventing/etching stopper film, the interlayer dielectric film having a multilayer structure including compressive stress layers made of SiO a second etching stopper film formed on the interlayer dielectric film; a second wiring layer formed on the second etching stopper film; a second trench being within the second etching stopper film and the second wiring layer, the second trench opposed to the first trench through the interlayer dielectric film; a first wire disposed in the first trench; and a second wire disposed in the second trench; and a plurality of vias, provided in via holes passing through the interlayer dielectric film, for electrically connecting the first wire and the second wire with each other, wherein the first wire and the second wire each have an outermost diameter larger than that of the vias.