Patent ID: 9569278
Date: 2017-02-14
CPC Classifications: G06F,Y02D

Claim:
1. A multi-core processor comprising: a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power, for a same applied operating frequency and supply voltage, than the first plurality of cores; and power management hardware to, from an initial state where the first plurality of cores and the second plurality of cores are enabled, disable an additional core of the first plurality of cores for each continued drop in demand below a next lower threshold without disabling any of the second plurality of cores until the first plurality of cores is disabled, disable an additional core of the second plurality of cores for each continued drop in demand below a next lower threshold until one core of the second plurality of cores remains enabled, and lower at least one of an operating frequency and a supply voltage of the one core of the second plurality of cores as demand drops below a next lower threshold.