Patent ID: 9583156
Date: 2017-02-28
CPC Classifications: G11C

Claim:
1. A selected gate (SG) driver circuit used in a memory circuit, comprising: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor, wherein: a gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor; a source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor; a source electrode of the first PMOS transistor is connected to a gate electrode of the second PMOS transistor; and a logic high voltage level is connected to a source electrode of the second PMOS transistor.