Patent ID: 9704355
Date: 2017-07-11
CPC Classifications: G06Q,G07G

Claim:
1. A device comprising: an input device with an input device user data connection to an input device controller; a multiplexer with a multiplexer control input port, a multiplexer data input port communicatively coupled to the input device controller, a first data output port, and a second data output port; a secure processor with: (i) a control output port communicatively coupled to the multiplexer control input port; and (ii) a secure processor data input port communicatively coupled to the first data output port; a tamper sensor processing circuit integrated on the same integrated circuit as the secure processor; a second processor with a second processor data input port communicatively coupled to the second data output port; a first memory: (i) associated with operation of the secure processor; (ii) storing a first injected digital public-key certificate; and (iii) integrated on a single integrated circuit with the secure processor; and a second memory: (i) associated with operation of the second processor; and (ii) storing a second injected digital public-key certificate; wherein the first injected digital public-key certificate and the second injected digital public-key certificate define a bonded pair of certificates forming a persistent identity for the secure processor and the second processor; the first memory comprising processor executable instructions which when executed by the secure processor cause the secure processor to: authenticate the secure processor and the second processor to a server by sending the first injected digital public-key certificate and the second injected digital public-key certificate to the server; and obtain financial encryption keys from the server based on the authentication of the bonded pair of certificates; wherein the tamper sensor processing circuit clears the first memory if tampering is detected; wherein the input device controller and second processor are not on the same integrated circuit as the secure processor; wherein the multiplexer is configurable between a first state and a second state; wherein the multiplexer data input port is communicatively coupled to the first data output port through the multiplexer when a current state of the multiplexer is the first state; wherein the multiplexer data input port is communicatively coupled to the second data output port through the multiplexer when the current state of the multiplexer is the second state; wherein the current state of the multiplexer is exclusively controlled by the secure processor via the control output port; wherein the secure processor and the multiplexer are located on the single integrated circuit; wherein the multiplexer is a block of circuitry on the single integrated circuit; and wherein the control output port and the multiplexer control input port are connected via interconnects in the single integrated circuit.