Patent ID: 9679865
Date: 2017-06-13
CPC Classifications: H01L,H05K,Y02P

Claim:
1. A semiconductor package, comprising: a substrate including: a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for coupling the first semiconductor chip with the first electrode; and a second connection member for coupling the second semiconductor chip with the second electrode.