Patent ID: 9698120
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A package process, comprising: providing a carrier board having an adhesive layer configured thereon; configuring a plurality of first semiconductor devices on the adhesive layer, wherein the plurality of the first semiconductor devices is separated from one another and fixed on the carrier board through the adhesive layer; forming a first molding compound on the carrier board to cover one or more sidewalls of each of the plurality of the first semiconductor devices and to fill first gaps between the plurality of the first semiconductor devices so as to form a chip array board comprising the first semiconductor devices and the molding compound; forming a plurality of first underfills, on the plurality of the first semiconductor devices respectively, wherein each of the plurality of the first underfills covers the corresponding first semiconductor device and a portion of the first molding compound surrounding the corresponding first semiconductor device; flip-chip bonding a plurality of second semiconductor devices to the plurality of the first semiconductor devices respectively, each of the plurality of the second semiconductor devices is flip-chip bonded to the corresponding first semiconductor device by a plurality of second conductive bumps of each of the plurality of the second semiconductor devices passing through the corresponding first underfill; forming a second molding compound on the chip array board to at least cover one or more sidewalls of each of the plurality of the second semiconductor devices and to fill second gaps between the plurality of the second semiconductor devices; separating the chip array board from the adhesive layer; and forming a plurality of chip package units, wherein each of the plurality of the chip package units includes at least one of the plurality of the first semiconductor devices and at least one of the plurality of the second semiconductor devices.