Patent ID: 9601491
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A vertical semiconductor device comprising: a first semiconductor material for a first of one of a source region and a drain region and an epitaxial fin channel atop a first channel interface portion of a surface the first semiconductor material; an isolation region adjacent to the first semiconductor material; a first spacer contacting a surface of the first semiconductor material, wherein the first spacer comprises an outer spacer portion and an inner spacer portion, wherein the inner spacer portion is present between the outer spacer portion and the epitaxial fin channel, wherein the first spacer does not extend over the isolation region that is adjacent to the first semiconductor material; a gate structure present atop the first spacer and is in direct contact with the epitaxial fin channel; and a second semiconductor material for a second of one of the source region and the drain in contact with a second channel interface portion of the epitaxial fin channel.