Patent ID: 9576957
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A semiconductor structure fabrication method comprising: forming first lower source/drain (S/D) regions within or upon a first active area of a semiconductor substrate; forming second lower S/D regions within or upon a second active area of the semiconductor substrate; forming a first replacement metal gate (RMG) structure upon the first active area of the semiconductor substrate between the first lower S/D regions; forming a second RMG structure upon the second active area of the semiconductor substrate between the second lower S/D regions; forming first raised S/D regions upon the first lower S/D regions adjacent to the first RMG structure; forming second raised S/D regions upon the second lower S/D regions adjacent to the RMG structure; forming first self-aligned contacts upon the first raised S/D regions; capping the first self-aligned contacts, and; forming second self-aligned contacts upon the second raised S/D regions.