Patent ID: 9589868
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a leadframe and a substrate; the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; the leadframe comprising copper, or other metal or metal alloy, having high electrical conductivity and thermal conductivity, the leadframe being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die; the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of one side of the leadframe by low inductance connections to form an interposer sub-assembly; source, drain and gate leads of the leadframe extending laterally and vertically from the GaN die to provide source, drain and gate contact surfaces, coplanar with the die-attach surface of the GaN die, for electrical interconnections to respective coplanar contact areas of the substrate; and the die-attach between the back-side surface of the GaN die and the respective source, drain and gate interconnections comprising a layer of interconnect material which is electrically and thermally conductive.