Patent ID: 9647693
Date: 2017-05-09
CPC Classifications: G06F,H03M

Claim:
1. A data processing apparatus comprising: a processor; a memory; a parity/ECC encoder circuit disposed in a signal path for writing write data of a plurality of bits from the processor to the memory and including a parity generating circuit; and a parity/ECC decoder circuit disposed in a signal path for reading read data from the memory to the processor and including a parity check unit, wherein the parity generating circuit generates a parity comprising a plurality of parity bits from the write data and writes the parity together with the write data into the memory, each of the bits configuring the write data is configured to contribute to generation of at least two parity bits in the parity, and wherein the parity check unit is configured so as to be able to detect presence/absence of an error of one bit or two bits in the read data and the parity of the bits read from the memory.