Patent ID: 9704819
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A power electronic package, comprising: a first substrate having a patterned inner surface that includes a first conductive region; a second substrate oppositely disposed from the first substrate and having a patterned inner surface that includes a second conductive region; a plurality of chips sandwiched between the first substrate and the second substrate and each of the chips having a top surface and a bottom surface; a first plurality of solder blocks disposed between the top surface of the chips and the first conductive region of the first substrate; a second plurality of solder blocks disposed between the bottom surface of the chips and the second conductive region of the second substrate; and at least three spacers each having a first end that contacts the first substrate, a second end that contacts the second substrate, and a height that is based on a height of the chips, on a height of the first plurality of solder blocks, and on a height of the second plurality of solder blocks such that the height variation of the power electronic package is controlled by the spacers; wherein the first substrate includes a ceramic layer sandwiched between two electrically conductive layers and the second substrate includes a ceramic layer sandwiched between two electrically conductive layers.