Patent ID: 9614081
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A semiconductor device including a first region of a semiconductor substrate and a second region of the semiconductor substrate, comprising: a first gate insulating film of a first NMOS transistor formed over the first region; a first gate electrode of the first NMOS transistor formed over the first gate insulating film; a first source region and a first drain region of the first NMOS transistor formed in the first region; a first channel region of the first NMOS transistor formed in the first region, formed under the first gate electrode and formed between the first source region and the first drain region; a second gate insulating film of a second NMOS transistor formed over the second region; a second gate electrode of the second NMOS transistor formed over the second gate insulating film; a second source region and a second drain region of the second NMOS transistor formed in the second region; a second channel region of the second NMOS transistor formed in the second region, formed under the second gate electrode and formed between the second source region and the second drain region, wherein a mass number of n-type dopant included in the first gate electrode, the first source region and the first drain region is larger than a mass number of n-type dopant included in the second gate electrode, the second source region and the second drain region.