Patent ID: 9703905
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. A method for simulating multiple processors in parallel, the method comprising: mapping, by a scheduler, debug interface information of at least one processor requiring debugging onto the scheduler by assigning an address of a debug interface of the processor requiring debugging to an interface pointer of the scheduler, creating, by the scheduler, at least one slave thread according to a configuration file by using a master thread, and determining at least one first processor corresponding to the master thread and at least one second processor corresponding to the at least one slave thread, wherein the at least one first processor corresponding to the master thread comprise the at least one processor requiring debugging, invoking, by the scheduler, by using the master thread and the at least one slave thread via a first execute interface, the at least one first and second processors to execute a corresponding instruction; debugging the processor requiring debugging by using the master thread via the debug interface of the processor requiring debugging, wherein the first execute interface registers with the scheduler through the at least one first and second processors; and delivering, by the scheduler, by using the master thread and the at least one slave thread via a first cycle interface, a cycle parameter to the at least one first and second processors, so as to control the scheduler to synchronously invoke, by using the master thread and the at least one slave thread, the at least one first and second processors, wherein the first cycle interface registers with the scheduler through the at least one first and second processors.