Patent ID: 9697118
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A memory controller, connected to a plurality of cores and a first memory segment, wherein the plurality of cores include first and second cores and the first memory segment includes first and second memory banks, and wherein the memory controller receives first and second access requests from the first core and a third access request from the second core, wherein the second access request is consecutive to the first access request, and wherein the first through third access requests include first through third sets of address least significant bits (LSBs), respectively, the memory controller comprising: a first address decoder that is connected to the first and second cores, receives the first through third access requests, and selects the first memory bank based on the first and third sets of address LSBs and the second memory bank based on the second set of address LSBs; a first system bus that is connected to the first address decoder, receives the first through third access requests, and routes the first and third access requests to the first memory bank in a first sequence and the second access request to the second memory bank, wherein the first sequence indicates an order of predetermined priority levels of the first and second cores; a first arbiter, connected to the first system bus and the first memory bank, that receives the first and third access requests in the first sequence, wherein the first arbiter comprises: a second arbiter, connected to the first system bus and the second memory bank, that receives the second access request in a second access cycle, and provides the first core access to the second memory bank, wherein the second access cycle is consecutive to the first access cycle.