Patent ID: 9620214
Date: 2017-04-11
CPC Classifications: G11C

Claim:
1. A content addressable memory comprising: a plurality of entries each having a plurality of content addressable memory cells; a plurality of match lines, arranged corresponding to the respective entries, each coupled to the content addressable memory cells in a corresponding entry; a search data bus coupled in parallel to the entries and transferring search data commonly to the respective entries; a plurality of match amplifiers, coupled to the respective match lines, each including an amplifier circuit for comparing a voltage on a corresponding match line with a reference voltage to produce a signal indicating a result of comparison, a precharge circuit for precharging the corresponding match line to a precharge voltage level after completion of an amplifying operation of said amplifier circuit, and a pull-up current supply circuit for supplying a current having a restricted current value to the corresponding match line when said precharge circuit is inactive; and a current generating circuit including a replica entry having a same construction as a match line discharging path of the entry and having a plurality of replica cells replicating a state having the content addressable memory cell of one bit made conductive in each entry, a replica match line coupled to the plurality of replica cells, and a current supply for supplying a current to said replica match line, wherein the pull-up current supply circuit is connected between the corresponding match line and a power supply voltage node, and wherein said pull-up current supply circuit includes a transistor element passing a mirror current of the current supplied by said current supply to the corresponding match line.