Patent ID: 9582190
Date: 2017-02-28
CPC Classifications: G06F,G06Q,G07F

Claim:
1. An integrated circuit for a smart card, the integrated circuit comprising: a power interface to introduce electrical power to the integrated circuit; memory cells to store data signals; a write engine coupled to the memory cells, wherein the write engine is configured to write a first indication that indicates a characteristic of a first memory cell before a power-down period to a second memory cell and to write a second indication that indicates the characteristic of the first memory cell after the power-down period to a third memory cell; a read engine coupled to the memory cells, wherein the read engine is configured to read the second memory cell and to read the third memory cell; and time management logic coupled to the memory cells, wherein the time management logic is configured to determine a time lapse based on a change between the first indication read from the second memory cell and the second indication read from the third memory cell.