Patent ID: 9576866
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A method for fabricating an array substrate, the method comprising the following steps: 1) forming a thin film transistor, a pixel electrode, and a test electrode on a substrate, the thin film transistor including an active layer, a gate electrode, a source electrode and a drain electrode, the pixel electrode being connected to the drain electrode of the thin film transistor, the test electrode being formed on the active layer, and the test electrode being electrically insulated from the gate electrode, the source electrode and the drain electrode; 2) forming a passivation layer on the substrate subjected to step 1), the passivation layer covering the test electrode, the active layer, the source electrode, the drain electrode and the pixel electrode; and 3) forming a common electrode on the substrate subjected to step 2), the common electrode being disposed above the pixel electrode with the passivation layer therebetween; wherein the test electrode is configured for testing characteristics of the thin film transistor when both the pixel electrode and the drain electrode are covered by the passivation layer, and wherein the common electrode is configured to be electrically connected to the test electrode so that a signal from the drain electrode is transmitted to the common electrode so as to test characteristics of the thin film transistor.