Patent ID: 9625938
Date: 2017-04-18
CPC Classifications: G06F,H03K

Claim:
1. An apparatus comprising: a first terminal configured to receive a clock signal; a second terminal configured to receive a complementary clock signal; a third terminal configured to receive a clock control signal; a latch circuit configured to generate a latched version of the clock control signal based on a version of the clock control signal, a version of the clock signal, and a version of the complementary clock signal; and a combinatorial circuit configured to generate a gated clock signal and a gated complementary clock signal based on the latched version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal, wherein in response to the clock control signal having a first level, the combinatorial circuit generates the gated clock signal having a low level and the gated complementary clock signal having a high level.