Patent ID: 9720767
Date: 2017-08-01
CPC Classifications: G06F

Claim:
1. A storage apparatus comprising: a switch; a plurality of channel adapters communicatively coupled to the switch, wherein each of the plurality of channel adapters includes a plurality of direct memory access controllers (DMACs) a plurality of data caches communicatively coupled to the switch; one or more disk adapters communicatively coupled to the switch, wherein each of the one or more disk adapters is communicatively coupled to one or more hard disk drives; and one or more processors communicatively coupled to the switch; wherein each of the one or more processors: receives, via a particular channel adapter from the plurality of channel adapters, a request to read a plurality of pieces of element data from a host computer communicatively coupled to the particular channel adapter, and transmits a start request to the plurality of DMACs of the particular channel adapter, wherein the start request identifies the plurality of pieces of element data; wherein the plurality of DMACs: receives the start request from a particular processor, reads the plurality of pieces of element data in parallel, wherein different DMACs read different pieces of element data, calculates a cyclic redundancy check (CRC) for each of the plurality of pieces of element data, concatenates the CRC calculated for each of the plurality of pieces of element data to the respective piece of element data to form a plurality of partial codes; and transmits the plurality of partial codes to the particular processor, and wherein the particular processor: calculates a sequence code that is a guarantee code of the plurality of partial codes and the CRC calculated for each of the plurality of pieces of element data, and concatenates the sequence code and the plurality of partial codes to form response data.