Patent ID: 9673798
Date: 2017-06-06
CPC Classifications: G11C,H03K

Claim:
1. An apparatus, comprising: a first circuit configured to determine a first delay setting corresponding with a first period of time during which an input signal is at a high voltage level; a second circuit configured to determine a second delay setting corresponding with a second period of time during which the input signal is at a low voltage level less than the high voltage level; a mid-point selection circuit configured to determine a mid-point delay setting at a mid-point between the first delay setting and the second delay setting and generate a delayed version of the input signal using the mid-point delay setting; and a duty cycle adjustment circuit configured to generate a corrected signal via application of a first logical operation to the delayed version of the input signal and the input signal if the first period of time is greater than the second period of time or application of a second logical operation to the delayed version of the input signal and the input signal if the first period of time is not greater than the second period of time.