Patent ID: 9601573
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor layer; a gate pad disposed on the semiconductor layer and formed at a center portion of the semiconductor layer as viewed in plan from a thickness direction of the semiconductor layer; and a plurality of unit cells formed in the semiconductor layer to each compose a transistor element that is either a metal oxide semiconductor (MOS) field effect transistor element or an insulated gate bipolar transistor element, and arranged in a radial direction about the gate pad as viewed in plan, wherein a gate electrode of a unit cell that is proximate to the gate pad, among the plurality of unit cells arranged in the radial direction, is electrically connected to the gate pad, and gate electrodes of unit cells that are adjacent to each other in the radial direction are connected to each other, the unit cells each have a regular hexagonal shape as viewed in plan, a source region of the unit cells other than the unit cells proximate to the gate pad is formed in a regular hexagonal ring shape as viewed in plan, and a source region of the unit cells proximate to the gate pad is formed in a partially missing regular hexagonal ring shape as viewed in plan.