Patent ID: 9654117
Date: 2017-05-16
CPC Classifications: H03L

Claim:
1. An integrated circuit device implementing a digital phase-locked loop, comprising: a measure period component structured to receive a reference signal and determine a period of the reference signal for each of a plurality of cycles of the reference signal; an averager component structured to receive the determined period for each of the plurality of cycles of the reference signal and determine an average period value based on the received determined periods; a generator component structured to receive the average period value and generate an output signal, wherein a period of the output signal is based on the average period value; and a compensator component structured to receive the reference signal and the output signal, wherein the compensator component is structured to determine an offset value based on a phase difference between the reference signal and the output signal, wherein the offset value is fed back to the generator component, and wherein the generator component is further structured to apply the offset value to the output signal to synchronize the output signal with the reference signal.