Patent ID: 9620632
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate; an upper electrode formed on a top surface of the semiconductor substrate; a lower electrode formed on a bottom surface of the semiconductor substrate; and a gate electrode, wherein an emitter region, a body region, a pillar region, a barrier region, a drift region, a collector region and a cathode region are formed in the semiconductor substrate, the emitter region has an n-type impurity and is connected to the upper electrode, the body region has a p-type impurity, is formed on a lateral side and on a lower side of the emitter region, and is connected to the upper electrode, the pillar region has an n-type impurity, is formed on a lateral side of the body region, extends along a depth from the top surface of the semiconductor substrate to a lower end of the body region, is connected to the upper electrode, and is separated from the emitter region by the body region, the barrier region has an n-type impurity, is formed on a lower side of the body region and the pillar region, and is separated from the emitter region by the body region, the drift region has an n-type impurity, is formed on a lower side of the barrier region, is separated from the emitter region by the barrier region, and has an n-type impurity concentration lower than an n-type impurity concentration in the pillar region and the barrier region, the collector region has a p-type impurity, is formed on a lower side of the drift region, is connected to the lower electrode, and is separated from the barrier region by the drift region, the cathode region has an n-type impurity, is formed on the lower side of the drift region, is connected to the lower electrode, is separated from the barrier region by the drift region, and has an n-type impurity concentration higher than the n-type impurity concentration in the drift region, a trench that penetrates through the emitter region, the body region and the barrier region and reaches the drift region is formed on the top surface of the semiconductor substrate, an inner surface of the trench is covered with a gate insulating film, the gate electrode is disposed in the trench, an n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region is arranged in a curved line which has a peak in the depth direction and has a maximum value in the pillar region, and the n-type impurity concentration distribution has a folding point on a side deeper than the maximum value in the pillar region and shallower than a border of the barrier region and the drift region in the depth direction.