Patent ID: 9691821
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A memory structure comprising: a first portion comprising logic circuitry to perform data operations on an array; a second portion comprising the array disposed above the first portion, the array comprising a first horizontal line, a second horizontal line, a first vertical line, a second vertical line, a third vertical line, a first two-terminal memory cell formed between a center conductor of the first vertical line and the first horizontal line, and a second two-terminal memory cell formed between the center conductor of the first vertical line and the second horizontal line; a bit line; a select device disposed above, and not within the first portion, the select device operable to selectively electrically couple the center conductor of the first vertical line and a center conductor of the third vertical line to the bit line, wherein the second vertical line is disposed between the first vertical line and the third vertical line and is not coupled to the select device; and at least one of a via or an interconnect to electrically connect the bit line to the logic circuitry in the first portion.