Patent ID: 9535665
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. A method comprising: encoding, by use of a processor, a logic design as a linear array comprising a plurality of logic states, each logic state comprising one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values; and generating source code from the plurality of logic states by generating a software structure selected from the group consisting of one of a case statement, a table, and a plurality of if/then statements, generating an encoded logic state for each logic state, generating a condition test for each encoded logic state, and appending a binary output variable statement and an assertion indicator value for binary output variable associated with the encoded logic state.