Patent ID: 9711648
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor structure comprising: a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate; a dielectric spacer structure located on each sidewall surface of the channel material portion and each sidewall surface of said mesa portion of said substrate, said dielectric spacer structure having a height that is greater than a height of said channel material portion; an isolation structure located on each dielectric spacer structure, wherein a sidewall edge of said isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of said dielectric spacer structure, and a first width between each dielectric spacer structure located on each sidewall surface of said channel material portion is less than a second width between said sidewall edges of each isolation structure; and a functional gate structure located in an area defined by said first and second widths and present on said channel material portion, wherein a topmost surface of said functional gate structure is coplanar with a topmost surface of said isolation structure.