Patent ID: 9646716
Date: 2017-05-09
CPC Classifications: G06F,G11C

Claim:
1. A circuit arrangement for detecting memory errors, comprising: a memory; and an error detection circuit, wherein the circuit arrangement is designed to store a code word of an error detection code or a code word that is inverted in a subset of bits in the memory at a memory location and to read out a data word from the memory from the memory location, wherein the error detection circuit is designed, for a case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code, and wherein the error detection circuit is designed, for a case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset of bits was written to the memory location, to determine on the basis of the data word read out from the memory whether a memory error is present if the code word that is inverted in the subset of bits is not a code word of the error detection code.