Patent ID: 9634001
Date: 2017-04-25
CPC Classifications: G03F,G06F,H01L

Claim:
1. A FinFET structure layout comprising: a semiconductor substrate comprising a plurality of FinFET active areas; a plurality of fins within each of the plurality of FinFET active areas; a gate having a gate length parallel to the semiconductor substrate and perpendicular to a length of the plurality of fins, wherein the gate extends across each FinFET active area of the plurality of FinFET active areas; a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts, wherein the plurality of metal features comprises a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction; a first plurality of mandrels in a first FinFET active area of the plurality of FinFET active areas; and a second plurality of mandrels in a second FinFET active area of the plurality of FinFET active areas, wherein a pitch of the first plurality of mandrels is equal to a pitch of the second plurality of mandrels.