Patent ID: 9640278
Date: 2017-05-02
CPC Classifications: G11C

Claim:
1. An apparatus comprising: an output driver circuit configured to (i) receive a data input signal, an input clock signal, and a first control signal and (ii) generate a data output signal and an output clock signal, wherein said data output signal is a delayed version of said data input signal and a length of delay between said data input signal and said data output signal is determined in response to said first control signal; and a trimming circuit configured to be enabled during production testing by a command received by said apparatus from automated test equipment and to generate said first control signal in response to a second control signal, wherein said data input signal is generated during said production testing in response to a test pattern and a test clock received by said apparatus from said automated test equipment and said trimming circuit is enabled to (i) vary a value of said first control signal to minimize a phase difference between said data output signal and said output clock signal, (ii) determine whether the apparatus passes or fails said production test based upon a trimming result, and (iii) notify the automated test equipment about the pass or fail status of the apparatus under test.