Patent ID: 9685949
Date: 2017-06-20
CPC Classifications: H01L,H02H,H03F,H03K,H05K

Claim:
1. An ESD protection circuit connected in parallel to a MIM capacitor between a first terminal and a second terminal, comprising first and second ESD protection circuits connected in anti-parallel to each other, the first ESD protection circuit includes a first transistor being depression-mode and field-effect type, a plurality of first Schottky diodes connected in series to each other, a second Schottky diode and a first resistor, a drain of the first transistor is connected to the first terminal, a source of the first transistor is connected to anodes of the plurality of first Schottky diodes, a gate of the first transistor is connected to an anode of the second Schottky diode, cathodes of the plurality of first Schottky diodes are connected to a cathode of the second Schottky diode and are connected to the second terminal, the first resistor is connected in series to the second Schottky diode, a product of built-in voltage and the number of the plurality of first Schottky diodes is higher than a threshold voltage of the first transistor, the second ESD protection circuit includes a second transistor being depression-mode and field-effect type, a plurality of third Schottky diodes connected in series to each other, a fourth Schottky diode and a second resistor, a drain of the second transistor is connected to the second terminal, a source of the second transistor is connected to anodes of the plurality of third Schottky diodes, a gate of the second transistor is connected to an anode of the fourth Schottky diode, cathodes of the plurality of third Schottky diodes are connected to a cathode of the fourth Schottky diode and are connected to the first terminal, the second resistor is connected in series to the fourth Schottky diode, and a product of built-in voltage and the number of the plurality of third Schottky diodes is higher than a threshold voltage of the second transistor.