Patent ID: 9607569
Date: 2017-03-28
CPC Classifications: G09G,H01L

Claim:
1. A semiconductor device comprising: first to seventh transistors and first to fifth wirings, wherein: a gate of the first transistor is electrically connected to the first wiring, one of a source and a drain of the first transistor is supplied with a first voltage, the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor, a gate of the second transistor is electrically connected to the second wiring, one of a source and a drain of the second transistor is supplied with a second voltage, the other of the source and the drain of the second transistor is electrically connected to the one of the source and the drain of the fifth transistor, a gate of the third transistor is electrically connected to the first wiring, one of a source and a drain of the third transistor is supplied with a third voltage, the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the sixth transistor, a gate of the fourth transistor is electrically connected to the second wiring, one of a source and a drain of the fourth transistor is supplied with a fourth voltage, the other of the source and the drain of the fourth transistor is electrically connected to the one of the source and the drain of the sixth transistor, a gate of the fifth transistor is electrically connected to the third wiring, the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the seventh transistor, a gate of the sixth transistor is electrically connected to the fourth wiring, the other of the source and the drain of the sixth transistor is electrically connected to the one of the source and the drain of the seventh transistor, a gate of the seventh transistor is electrically connected to the fifth wiring, the first wiring is supplied with a first signal, the second wiring is supplied with an inversion signal of the first signal, the third wiring is supplied with a second signal, the fourth wiring is supplied with an inversion signal of the second signal, the fifth wiring is supplied with a third signal, and a channel width of each of the first to fourth transistors is smaller than a channel width of each of the fifth to seventh transistors.