Patent ID: 9646991
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a plurality of transistors arranged in two rows and n columns on a substrate, where n≧2, to constitute a NOR circuit, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate, each of the plurality of transistors including: the plurality of transistors including: wherein the n n-channel MOS transistors and the n p-channel MOS transistors are arranged such that an n-channel MOS transistor in a k-th column and a p-channel MOS transistor in the k-th column form a pair, where k=1 to n, the gate of the n-channel MOS transistor in the k-th column and the gate of the p-channel MOS transistor in the k-th column being connected to one another, the drain regions of the n n-channel MOS transistors and the drain region of a p-channel MOS transistor in a first column are located on a side of the silicon pillars close to the substrate, the drain regions of the n n-channel MOS transistors and the drain region of the p-channel MOS transistor in the first column being connected to one another via a silicide region, and the source region of a p-channel MOS transistor in an s-th column and the drain region of a p-channel MOS transistor in an (s+1)-th column are connected to one another, where s=1 to n−1.