Patent ID: 9589655
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A storage device, comprising: a sensing amplifier and a processor; the sensing amplifier to apply a first read voltage to a word line of a page of memory cells, the page of memory cells being selected by the processor; the sensing amplifier to apply a pass voltage to word lines associated with one or more different pages of memory cells; upon applying the first read voltage, the sensing amplifier to sense whether a bit line of a memory cell in the selected page conducts; the sensing amplifier to measure a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and to bypass applying a second read voltage to the word line based on the measuring the side effect; and the processor to assign a log likelihood ratio (LLR) value to the memory cell as a soft low density parity check (LDPC) input based at least in part on the sensing amplifier applying the first read voltage and on the measured side effect.