Patent ID: 9553204
Date: 2017-01-24
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a first memory cell; a second memory cell; a first wiring; a second wiring; and a switch, wherein the first memory cell comprises a first transistor, a second transistor, and a capacitor, wherein the first wiring comprises a function of being supplied with a data voltage, wherein the second wiring comprises a function of being supplied with the data voltage of the first wiring via the first transistor, wherein the first memory cell comprises a function of being supplied with the data voltage of the second wiring via the second transistor, wherein the first memory cell comprises a function capable of holding a charge corresponding to the data voltage at a node where one electrode of the capacitor, a gate of the first transistor, and one of a source and a drain of the second transistor are electrically connected, wherein the first memory cell is electrically connected to the first wiring, wherein the second memory cell is electrically connected to the first wiring, wherein the first memory cell is electrically connected to the second wiring, wherein the second memory cell is electrically connected to the second wiring, wherein the switch is between the second wiring electrically connected to the first memory cell and the second wiring electrically connected to the second memory cell, and wherein the switch comprises a function capable of being turned off during a period in which the charge corresponding to the data voltage is supplied to the node of the first memory cell.