Patent ID: 9588904
Date: 2017-03-07
CPC Classifications: G06F

Claim:
1. An apparatus to transmit data access requests to a memory controller for flash memory, the apparatus comprising: circuitry to assign non-overlapping logical address ranges to respective virtual block devices defined with respect to the flash memory, wherein each one of the respective virtual block devices is characterized by associated performance characteristics comprising a minimum time required to program a page of memory cells in the flash memory, a minimum time required to erase a block of memory cells in the flash memory, and a minimum time required to read a page of memory cells in the flash memory; circuitry to receive from the memory controller, on an independent basis for each one of the respective virtual block devices, information identifying the need for a maintenance operation, the maintenance operation for each one of the respective virtual block devices comprising at least one of erase of an erase unit in the flash memory corresponding to the one of the respective virtual block devices or a data relocation operation for data stored in the flash memory corresponding to the one of the respective virtual block devices; and circuitry to schedule issuance of commands to the memory controller, the commands to control the performance of maintenance operations in respective virtual block devices, in a manner such that the scheduling of commands to perform a maintenance operation in a first one of the respective virtual block devices is unconstrained by the performance characteristics associated with a second one of the respective virtual block devices.