Patent ID: 9710241
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. A compiling apparatus comprising: an analysis unit configured to generate a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes, to determine data widths of input and output operands of the nodes and the connections in the data flow graph using type information regarding a type of the operands, and to add information about the determined data width of the input and output operands of the nodes and information about the connections between the nodes in the data flow graph; and a data processing unit configured to provide instructions to be executed by a processor comprising heterogeneous components that support different data widths, based on the determined data widths of the operands and the connections in the data flow graph, wherein the type information comprises a value indicating a number of bits, and the data processing unit is further configured to select, in response to respective determinations of the determined data widths of the operands and the connections in the data flow graph, instructions comprising a data width matching the determined data widths of the operands and the connections in the data flow graph, and wherein the analysis unit is further configured to initialize data widths of input and output nodes in the data flow graph based on the type information of the operands and to determine and set, using a fixed-point algorithm, data widths of unknown operands and connections as minimal data widths thereof from among available data widths.