Patent ID: 9665297
Date: 2017-05-30
CPC Classifications: G06F

Claim:
1. A method of data processing in a data processing system including a processor core supported by an upper level cache and a lower level cache, the method comprising: receiving, at the lower level cache from an interconnect fabric, a write injection request requesting injection of a partial cache line of data into a target cache line identified by a target real address; in response to receipt of the write injection request, determining that the upper level cache is a highest point of coherency for the target real address; in response to determining the upper level cache is the highest point of coherency for the target real address, the upper level cache and lower level cache collaborating to transfer the target cache line from the upper level cache to the lower level cache; and the lower level cache updating the target cache line received from the upper level cache by merging the partial cache of data into the target cache line and storing the updated target cache line in the lower level cache.