Patent ID: 9697317
Date: 2017-07-04
CPC Classifications: G03F,G06F,H01L

Claim:
1. An integrated circuit product prepared by a process comprising the steps of: receiving a design layout comprising a plurality of layout objects residing on a plurality of layers; receiving descriptions of a manufacturing process; constructing a system of initial constraints among said layout objects; computing one or more local process modifications to change said initial constraints using said descriptions of manufacturing process; constructing new local constraint distances by combining said local process modifications with constraint distances in said system of initial constraints; enforcing said new local constraint distances; updating the coordinate variables of said layout objects according to the solutions obtained from enforcing said new local constraint distances, thereby obtaining updated coordinate variables of said layout objects; and fabricating the integrated circuit product in accordance with the updated coordinate variables, wherein the integrated circuit product comprises a first plurality of routing wires running in a first direction, and a second plurality of routing wires running in a second direction, the second direction being orthogonal to the first direction, the routing wires of the first plurality of routing wires having first width values, the routing wires of the second plurality of routing wires having second width values, the first width values being substantially different from the second width values.