Patent ID: 9640637
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method for producing a semiconductor device, comprising: a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; a second step of, after the first step, forming a first pillar-shaped semiconductor layer, a first dummy gate formed from a first polysilicon, a second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon; a third step of, after the second step, forming a third dummy gate and a fourth dummy gate on side walls of the first dummy gate, the first pillar-shaped semiconductor layer, the second dummy gate, and the second pillar-shaped semiconductor layer; a fourth step of, after the third step, forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of, after the fourth step, depositing an interlayer insulating film; exposing upper portions of the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate; removing the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate; forming a first gate insulating film around the first pillar-shaped semiconductor layer and around the second pillar-shaped semiconductor layer; removing the first gate insulating film from around a bottom portion of the second pillar-shaped semiconductor layer; depositing a first metal; exposing an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the second pillar-shaped semiconductor layer; forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer; and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of, after the fifth step, depositing a second gate insulating film around the first pillar-shaped semiconductor layer, on the gate electrode, on the gate line, around the second pillar-shaped semiconductor layer, on the contact electrode, and on the contact line; removing a portion of the second gate insulating film on the gate line and at least portions of the second gate insulating film on the contact electrode and on the contact line; depositing a second metal; exposing an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the second pillar-shaped semiconductor layer; removing the second gate insulating film on the first pillar-shaped semiconductor layer; depositing a third metal; etching a portion of the third metal and a portion of the second metal to form a first contact in which the second metal surrounds an upper side wall of the first pillar-shaped semiconductor layer, to form a second contact that connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, to form a third contact formed of the second metal and the third metal formed on the gate line, to form a fourth contact in which the second metal surrounds an upper side wall of the second pillar-shaped semiconductor layer and is connected to the contact electrode, and to form a fifth contact that connects an upper portion of the fourth contact to an upper portion of the second pillar-shaped semiconductor layer.