Patent ID: 9589832
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A system to manufacture an integrated circuit, comprising: a plasma etch chamber comprising a stage to position a wafer, the wafer comprising an organic mask layer on a first insulating layer comprising a silicon nitride layer on a second insulating layer comprising a silicon oxide layer over a substrate, the plasma etch chamber having an inlet to input a first iodine containing gas; and at least one power source coupled to the plasma etch chamber; and a processor coupled to the plasma etch chamber, wherein the processor having a first configuration to control forming one or more openings in the organic mask layer; wherein the processor having a second configuration to control forming through the one or more openings in the organic mask layer one or more openings in the silicon nitride layer using the first iodine containing gas having a first iodine content, and wherein the processor having a third configuration to control forming through the one or more openings in the silicon nitride layer one or more openings in the silicon oxide layer using the second iodine containing gas having a second iodine content that is smaller than the first iodine content.