Patent ID: 9600416
Date: 2017-03-21
CPC Classifications: G06F,G11C,Y02D

Claim:
1. A computer system comprising: a processor having a plurality of cores to execute instructions and process data and one or more processor caches to cache instructions and data; a first architectural level of a main memory (“first level memory”) having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and a second architectural level of the main memory (“second level memory”) having a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively slower than either the first read access speed or first write access speed, respectively, non-volatility such that the second level memory maintains its content when power is removed, random access and memory subsystem addressability such that instructions or data stored therein may be randomly accessed at a granularity equivalent to that used by the main memory of the computer system; wherein at least a portion of the first level memory is configured as a memory side cache for instructions and data stored in the second level memory according to a selected one of multiple cache management mode options.