Patent ID: 9741870
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. An integrated junction field effect transistor formed as a complementary metal oxide semiconductor, comprising: a substrate layer of a first dopant type; an isolation well of a second dopant type disposed above the substrate; a first gate layer of the first dopant type disposed above the isolation well; a depletion channel of the second dopant type disposed above the first gate layer; a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor, the second gate layer separating the depletion channel from the surface, and the depletion channel separating the first gate layer from the second gate layer; and a drain contact and a source contact, each disposed proximate the surface and in electrical communication with the depletion channel, wherein each of the source and drain contacts are disposed proximate and abut a layer formed between the second gate layer and each of the source and drain contacts and configured to reduce flicker noise.