Patent ID: 9728403
Date: 2017-08-08
CPC Classifications: G02F,G09G,H01L

Claim:
1. A manufacturing method of an array substrate, comprising the following steps: (1) providing a base plate, sequentially forming a light shielding layer and a buffer layer on the base plate, forming a poly-silicon layer on the buffer layer, subjecting two opposite end portions of the poly-silicon layer to N-type ion implantation so as to obtain N-type heavily doped zones that are respectively located at the two end portions of the poly-silicon layer and a non-doped zone located between the two N-type heavily doped zone, and depositing a gate insulation layer on the poly-silicon layer; (2) coating photoresist on the gate insulation layer and using the half tone mask to subject the photoresist to exposure and development so as to obtain a photoresist layer, wherein the photoresist layer comprises through holes formed therein to correspond to the N-type heavily doped zones and the photoresist layer has a portion that corresponds to and located above the non-doped zone and has a thickness greater than a thickness of a remaining portion of the photoresist layer; (3) using the photoresist layer as a shielding layer to subject the gate insulation layer to dry etching so as to obtain first vias corresponding to and located above the N-type heavily doped zones and subjecting the photoresist layer to oxygen ashing treatment so that after the oxygen ashing treatment, a remaining portion of the photoresist layer is left and located above the non-doped zone of the poly-silicon layer and has a size less than that of the non-doped zone; (4) using the remaining portion of the photoresist layer as a shielding layer to conduct N-type ion implantation on two end portions of the non-doped zone so as to form N-type lightly-doped zones respectively on the two end portions of the non-doped zone and define a channel zone in a non-doped area between the two N-type lightly-doped zones; and removing the photoresist layer, depositing a metal layer on the gate insulation layer, and patterning the metal layer to form a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode, the source electrode, and the drain electrode are not connected with each other and the source electrode and the drain electrode are respectively connected through the first via to the N-type heavily doped zones; (5) forming a planarization layer on the gate electrode, the source electrode, and the drain electrode and applying a photolithographic operation to form, in the planarization layer, a second via that corresponds to and is located above the gate electrode and a third via that corresponds to and is located above the drain electrode; and (6) forming an indium tin oxide (ITO) film on the planarization layer and patterning the ITO film to obtain a common electrode and a transparent electrode, wherein the transparent electrode is connected through the second via to the gate electrode to allow a gate scan signal to be fed through the transparent electrode to the gate electrode.