Patent ID: 9653533
Date: 2017-05-16
CPC Classifications: H01G,H01L

Claim:
1. A multi-layer capacitor, comprising: a first level planar capacitor, comprising a first level first trace and a first level second trace; a dielectric layer, arranged over the first level planar capacitor; a second level planar capacitor, arranged over the dielectric layer, comprising a second level first trace and a second level second trace; and a bridged-post inter-layer interconnect, comprising at least two first posts and at least two second posts, extending through the dielectric layer, adjacent to and outside a perimeter of the first level planar capacitor and a perimeter of the second level planar capacitor, a first level first post coupler and a first level second post coupler, under the dielectric layer, wherein the first level first post coupler is configured to couple the at least two first posts together and to the first level first trace, and the first level second post coupler is configured to couple the first level second trace to at least one of the at least two second posts, and a second level first post coupler and a second level second post coupler, over the dielectric layer, wherein the second level second post coupler is configured to couple the at least two second posts together and to the second level first trace, and the second level first post coupler is configured to couple the second level first trace to at least one of the at least two first posts.