Patent ID: 9590695
Date: 2017-03-07
CPC Classifications: H04B

Claim:
1. A semiconductor device comprising: an Ethernet transceiver integrated circuit (IC) chip; a chip package including multiple pads for coupling to a wireline Ethernet link comprising multiple full-duplex twisted-pair channels, the IC chip mounted within the chip package; multiple RFI filters corresponding to the multiple full-duplex twisted-pair channels to filter interfering signals received via the multiple full-duplex twisted-pair channels, wherein each of the RFI filters is external to the Ethernet transceiver IC chip and disposed in the chip package; wherein the transceiver IC chip includes multiple transmitters having outputs coupled to respective input/output (I/O) pads, and multiple receivers having inputs coupled to the corresponding I/O pads; wherein the package includes off-chip transmit signal paths coupled to the I/O pads, and off-chip receive signal paths coupled to the I/O pads; and wherein each RFI filter is disposed entirely in a corresponding off-chip receive signal path to filter the RFI from signals received via the multiple twisted-pair channels.