Patent ID: 9627405
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a multi-layered source layer including a lower source layer, an interlayer source layer, and an upper source layer; conductive patterns and interlayer insulating layers alternately disposed on the multi-layered source layer; and a channel pillar penetrating the conductive patterns, the interlayer insulating layers, the upper source layer, and the interlayer source layer, the channel pillar extending into the lower source layer, the channel pillar being in contact with the interlayer source layer, wherein the channel pillar includes a first doped region, which includes a first dopant and overlap the interlayer source layer, and a second doped region, which includes a second dopant and overlap at least one layer from the lowermost layer among the conductive patterns.