Patent ID: 9748268
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a first electrode layer provided above a conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first insulating layer provided between the first electrode layer and the second electrode layer; a second insulating layer provided between the conductive layer and the second electrode layer; and a pillar layer extending through the first electrode layer, the second electrode layer, the first insulating layer, and the second insulating layer in a first direction directed from the conductive layer to the first electrode layer, the pillar layer having conductivity, the pillar layer including a first portion extending through the first insulating layer, a second portion extending through the second electrode layer, and a third portion extending through the second insulating layer, and the pillar layer having a first width in a second direction along a surface of the conductive layer at a periphery of the first portion, a second width in the second direction at a periphery of the second portion, and a third width in the second direction at a periphery of the third portion, wherein the second width is larger than the first width, and the third width is larger than the first width and narrower than the second width.