Patent ID: 9548119
Date: 2017-01-17
CPC Classifications: G11C,H01L

Claim:
1. A memory cell comprising: a silicon-on-insulator (SOI) substrate; an electrically floating body transistor fabricated on said silicon-on-insulator (SOI) substrate and comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type; a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with a floating body region of said floating body transistor; a drain region comprising said second conductivity type in physical contact with said floating body region and spaced apart from said source line region; and a charge injector region, wherein said charge injection region comprises said second conductivity type and is in physical contact with said floating body region and spaced apart from said source line region and said drain region; wherein said floating body transistor is configured to have more than one stable state through an application of a bias on said charge injector region; and wherein said drain region and said source line region are bounded at the bottom by an insulator layer.