Patent ID: 9728272
Date: 2017-08-08
CPC Classifications: G11C

Claim:
1. A semiconductor device comprising: a word line; a bit line pair; a memory cell arranged at a position where the word line and the bit line pair intersect with each other; and a drive circuit that drives the bit line pair with a predetermined voltage to write data into the memory cell, wherein a first potential and a second potential higher than the first potential are supplied to the memory cell as power sources, wherein the semiconductor device has a first operation mode and a second operation mode, wherein in the first operation mode, the drive circuit drives one bit line of the bit line pair toward the first potential and drives the other bit line toward the second potential, and wherein in the second operation mode, the drive circuit drives one bit line of the bit line pair to a third potential that is higher than the first potential and lower than the second potential, and drives the other bit line toward the second potential.