Patent ID: 9536947
Date: 2017-01-03
CPC Classifications: G06N,H01L

Claim:
1. An electronic device comprising a substrate and an elongate silicon nanowire less than 0.5 μm in cross sectional dimensions, the elongate silicon nanowire being integrally formed with a silicon anchor at each of two ends thereof and having a hexagonal cross-sectional shape, wherein the silicon anchors support the elongate silicon nanowire in a horizontal orientation relative to the substrate, and wherein: the substrate comprises a silicon device layer underlain by an oxide layer, the silicon device layer having a vertical span between upper and lower faces thereof; the silicon anchors are coextensive with respective portions of the silicon device layer; the elongate silicon nanowire is thinner than the silicon device layer, is seamlessly integral with the silicon anchors, and is situated within the vertical span of the silicon device layer; the electronic device further comprises at least one first doped source region and at least one first doped drain region defined in the silicon device layer and arranged relative to the elongate silicon nanowire such that a conduction channel between the at least one first doped source region and the at least one first doped drain region passes through the elongate silicon nanowire; the elongate silicon nanowire is at least partially enclosed within a wrap-around coating of a gate oxide; the wrap-around coating of the gate oxide is at least partially overlain by a polysilicon gate conductor; between the silicon anchors, the elongate silicon nanowire is suspended, without further vertical support, above a gap in the oxide layer that underlies the silicon device layer; the electronic device further comprises metal contact pads electrically connected to the at least one first doped source region and the at least one first doped drain region through respective interconnects that pass vertically through an interlayer dielectric region; and the electronic device further comprises a metal contact pad electrically connected to a top gate polysilicon layer through an interconnect that passes vertically through an interlayer dielectric region, wherein the top gate polysilicon layer is electrically connected to the polysilicon gate conductor.