Patent ID: 9569579
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A physical System on Chip (SoC) configured with a Network on Chip (NoC) and one or more output registers, the NoC and the one or more output registers generated by a process comprising: generating the NoC comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on an associated SoC floorplan and a NoC topology; and for each of the plurality of channels in the NoC, generating an output register of the one or more output registers for a corresponding one of the plurality of routers handling output for the each of the one or more channels in the NoC based on a setup time of the corresponding router and a timing path within the corresponding router; wherein the NoC is configured with the one or more pipeline stages by: