Patent ID: 9702932
Date: 2017-07-11
CPC Classifications: G01R,G06F

Claim:
1. A testing system for an arithmetic logic unit comprising: a control unit, a data providing unit coupled to the control unit, a first input unit coupled to the data providing unit, a second input unit, separate from the first input unit, coupled to the data providing unit, an arithmetic logic unit coupled to the first input unit and the second input unit, an expected result unit, a comparator coupled to the arithmetic logic unit and the expected result unit, and a test result storage unit coupled to the comparator, wherein: the control unit controls a testing process; the data providing unit provides inputs to the first input unit, the second input unit and the expected result unit; the first input unit and the second input unit provide test data to the arithmetic logic unit; the arithmetic logic unit performs an operation and provides an operation result to the comparator; the expected result unit generates an expected result and provides the expected result of a current round of testing to the comparator; and the comparator compares the operation result with the expected result and provides a comparison result to the test result storage unit, wherein the control unit comprises: a testing process control unit configured to control the testing process; a step recording unit configured to record a number of steps; a device selection unit configured to select the arithmetic logic unit and a working mode of the arithmetic logic unit; a first data selection unit configured to select the inputs provided by the data providing unit; a second data selection unit configured to select the inputs respectively received by the first input unit, the second input unit and the expected result unit; and a data conversion controller configured to determine whether data in the first input unit, the second input unit and the expected result unit needs to be shifted or inverted.