Patent ID: 9577620
Date: 2017-02-21
CPC Classifications: H03K,H05K,Y10T

Claim:
1. A printed circuit arrangement comprising: a processor circuit having a first input node, a second input node and an output node; a printed main circuit arrangement in electrical connection with the first input node of the processor circuit, the printed main circuit arrangement configured to receive at least one input signal and generate a main circuit signal based on the at least one input signal after a first delay from receiving the at least one input signal; and a printed reference circuit arrangement in electrical connection with the second input node of the processor circuit, the printed reference circuit arrangement configured to receive a further input signal, wherein the printed reference circuit arrangement has a second delay and is configured such that the second delay adapts to the first delay and is configured to generate a reference circuit signal based on the further input signal after the second delay from receiving the further input signal; wherein the processor circuit is configured to generate an output signal at the output node based on the main circuit signal in response to the reference circuit signal.