Patent ID: 9583218
Date: 2017-02-28
CPC Classifications: G06F,G11C,H01L,H03K,H04L

Claim:
1. An integrated circuit, comprising: a first memory element that produces a first configuration bit; a second memory element that produces a second configuration bit; a first multiplexer that receives the first configuration bit from the first memory element and first and second signals from first and second inputs, wherein the first multiplexer selects between the first and second signals based on the first configuration bit; a second multiplexer that receives the second configuration bit, a first clock signal, and a delayed first clock signal, wherein the second multiplexer selects between the first clock signal and the delayed first clock signal to generate a second clock signal based on the second configuration bit; a first register triggered based on the first clock signal, wherein the first register receives and stores the first signal from the first input; a second register triggered based on the second clock signal, wherein the second register receives and stores a selected one of the first and second signals from the first multiplexer; and a comparator that receives the stored first signal from the first register and the stored selected one of the first and second signals from the second register, the comparator generating a status signal based on a comparison of the stored first signal and the stored selected one of the first and second signals.