Patent ID: 9728742
Date: 2017-08-08
CPC Classifications: G02F,H01L

Claim:
1. A display panel assembly from which a plurality of unit display panels is formed, comprising: an upper mother substrate; a lower mother substrate disposed opposing the upper mother substrate and including a thin film transistor array provided in plural; a sealing member having a closed loop shape provided in plural between the upper mother substrate and the lower mother substrate and respectively surrounding the thin film transistor arrays; and a seal pattern which is at an edge region of the upper mother substrate and the lower mother substrate and bonds the upper mother substrate and the lower mother substrate to each other, wherein in a top plan view, the seal pattern commonly surrounds each of the sealing members having the closed loop shape and the thin film transistor arrays respectively surrounded thereby to define an inner area within the seal pattern at which the sealing members and thin film transistor arrays are disposed and an outer area outside the seal pattern, and the seal pattern comprises an open region thereof at which the inner and outer areas are connected to each other.