Patent ID: 9747244
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. An integrated circuit, comprising: a plurality of GPIO pins: a GPIO interface configured to receive a first set of signals from a processor and to provide a GPIO portion of the first set of signals to the plurality of GPIO pins for transmission to a remote processor as GPIO signals; a dedicated transmit pin; and a finite state machine (FSM) configured to receive a virtual GPIO portion of the first set of signals from the GPIO interface as a transmit set of virtual GPIO signals and to serially transmit the transmit set of virtual GPIO signals as a series of corresponding pulse-width-modulated signals to a remote processor over the dedicated transmit pin, wherein the FSM includes a oscillator and at least one counter configured to count oscillations from the oscillator, and wherein the FSM is further configured to determine a pulse width for each pulse-width-modulated signal responsive to a count from the at least one counter, and wherein the FSM is further configured to generate each pulse-width-modulated signal such that a first binary value for the corresponding virtual GPIO signal in the transmit set corresponds to the generation of a first pulse width for the pulse-width-modulated signal and such that an opposite second binary value for the corresponding virtual GPIO signal in the transmit set corresponds to the generation of a second pulse width for the pulse-width-modulated signal, and wherein the second pulse width is greater than the first pulse width.