Patent ID: 9647137
Date: 2017-05-09
CPC Classifications: G09G,H01L

Claim:
1. A semiconductor device comprising: a substrate; a gate electrode on the substrate; a first silicon nitride insulating layer on and in contact with the gate electrode; a first silicon oxide insulating layer on and in contact with the first silicon nitride insulating layer; an oxide semiconductor layer on and in contact with the first silicon oxide insulating layer; a source electrode and a drain electrode each in contact with the oxide semiconductor layer; and a second silicon oxide insulating layer on and in contact with the oxide semiconductor layer in a region overlapping with the gate electrode, wherein the second silicon oxide insulating layer is on and in contact with the source electrode and the drain electrode, and wherein every point where the oxide semiconductor layer is in contact with one of the source electrode and the drain electrode overlaps with the gate electrode.