Patent ID: 9542999
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A semiconductor device comprising: word lines; a pair of bit lines; static type memory cells coupled to the word lines and the pair of bit lines so that one static type memory cell is coupled to one word line and the pair of data lines, the static type memory cells each including a first Metal insulator Semiconductor Field Effect Transistor (MISFET); a sense amplifier circuit which amplifies data read out to the pair of bit lines from one memory cell selected by one word line, an amplification operation thereof being controlled by an enable signal; and a control circuit which includes second MISFETs gate lengths thereof being longer than a gate length of the first MISFET wherein the control circuit is configured to delay a control signal with the second MISFETs and generate the enable signal based on the delayed control signal.