Patent ID: 9711715
Date: 2017-07-18
CPC Classifications: G11C,H01L

Claim:
1. A method of manufacturing a dual mode memory array capable of storing an imprinted read-only (“RO”) data bit and a non-imprinted read/write (“R/W”) data bit per array storage cell, comprising: writing RO data to be imprinted to at least one storage cell of the memory array; and applying at least one over-stress condition to at least one state-determining element of the storage cell in order to imprint the storage cell with the RO data by permanently modifying a value of a state-determining property associated with the state-determining element and to thereby bias a magnitude of a read-out signal associated with at least one state of imprinted RO data; performing a plurality of RO mode read operations on at least one imprinted cell to determine, for each RO mode read operation, an apparent state of the RO data imprinted in the at least one imprinted cell; after each RO mode read operation, comparing the RO data written to the apparent state of the RO data imprinted in the at least one imprinted cell as read; calculating an RO data read reliability by performing an averaging operation on the compared RO data; and determining whether the RO data read reliability of the at least one imprinted cell is greater than or equal to a selected level.