Patent ID: 9703718
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. A computer program product for managing cache line evictions during a transaction executing in a transactional memory environment comprising: a computer operating system embodied on a computer readable storage medium having program instructions executable by a processor, the program instructions comprising: executing, by the processor, a non-conflict address range setting instruction, wherein: in response to the processor executing a memory data accessing instruction during a transaction, determining, by a cache manager, whether a pre-defined maximum number of read-set cache lines is reached; based on the pre-defined maximum number of read-set cache lines being reached, determining, by the cache manager, whether a memory address operand of the memory data accessing instruction is within the non-conflict address range; based on the pre-defined maximum number of read-set cache lines being reached, and based on a memory address operand of the memory data accessing instruction being within the non-conflict address range, evicting a read-set cache line having data from a memory address in the non-conflict address range; and completing, by the processor, the memory data accessing instruction.