Patent ID: 9640636
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method of forming a vertical transistor device, the method comprising: forming an initial vertically oriented channel semiconductor structure having a first height above a substrate; forming a sacrificial spacer structure adjacent said initial vertically oriented channel semiconductor structure; with said sacrificial spacer structure in position, performing at least one process operation to define a self-aligned bottom source/drain region for said device that is self-aligned with respect to said sacrificial spacer structure; with said sacrificial spacer structure in position, forming an isolation region in said substrate; with said sacrificial spacer structure in position, forming a bottom source/drain electrode above said isolation region, wherein said bottom source/drain electrode is conductively coupled to said self-aligned bottom source/drain region; removing said sacrificial spacer structure; and forming a bottom spacer material around said initial vertically oriented channel semiconductor structure above said bottom source/drain electrode.