Patent ID: 9645886
Date: 2017-05-09
CPC Classifications: G06F,H03M,H04L

Claim:
1. An error-correcting circuit, arranged to receive a clock signal, comprising: a multiplier arranged to generate a first output from a first input and a second input; an error detector arranged to generate an error flag indicative of whether or not it has detected an error in the first output, based on the first output, the first input and the second input; a correction generator suitable for generating a correcting output after a first time period beginning with a timing event in the clock signal, based on the first output, the first input and the second input; and an output generator arranged to generate an output of the error-correcting circuit after a second time period beginning with the timing event in the clock signal, in which if the error flag indicates that an error has been detected in the first output then the second time period is longer than the first time period, or if the error flag indicates that an error has not been detected in the first output then the second time period is not longer than the first time period, and in which if the error flag indicates that an error has been detected in the first output then the output of the error-correcting circuit comprises a combination of the first output and the correcting output whereby the error detected in the first output is corrected, or if the error flag indicates that an error has not been detected in the first output then the output of the error-correcting circuit corresponds directly to the first output.