Patent ID: 9607123
Date: 2017-03-28
CPC Classifications: G06F,H01L

Claim:
1. A method for performing a deep n-typed well correlated (DNW-correlated) antenna rule check of an integrated circuit, comprising: providing a design layout of the integrated circuit to a design rule check (DRC) tool, the design layout of the integrated circuit comprising a deep n-typed well, at least a first device formed in the deep n-typed well, a plurality of first interconnections electrically connected to the first device, at least a second device, a plurality of second interconnections electrically connected to the second device, and at least one or more diode electrically connected to the second device, and the second device being electrically connected to the deep n-typed well; checking the design layout of the integrated circuit with the DNW-correlated antenna rule by the DRC tool, the DNW-correlated antenna rule comprising an inequality as following: re-designing the layout design of the integrated circuit in the DRC tool when the DNW-correlated antenna rule is violated; and fabricating the integrated circuit from the design layout when the DNW-correlated antenna rule is complied.