Patent ID: 9659637
Date: 2017-05-23
CPC Classifications: G11C

Claim:
1. A method comprising: correlating, by at least one processor, a first physical page address associated with a multilevel memory cell and a second physical page address associated with the multilevel memory cell; causing, by the at least one processor, at least a first read operation to be applied the multilevel memory cell to determine a value of a first bit associated with the first physical page address; causing, by the at least one processor, at least a second read operation to be applied the multilevel memory cell to determine a value of a second bit associated with the second physical page address; determining, by the at least one processor, a soft decision value associated with the second bit based on the value of the first bit and the value of the second bit; and verifying, by the at least one processor, based at least in part on the soft decision value information associated with the second bit, the value of the second bit.