Patent ID: 9576933
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A fan-out wafer-level-package, comprising: a redistribution layer (RDL) comprising at least one dielectric layer and at least one first metal layer; a passive device in the first metal layer of the RDL; a first passivation layer covering a top surface of the RDL; a second passivation layer covering a bottom surface of the RDL; at least one chip mounted on the first passivation layer, wherein the chip comprises a terminal distributed directly on an active surface of the chip in direct contact with the first passivation layer; a molding compound disposed around the chip and on the first passivation layer; a via opening penetrating through the first passivation layer, the dielectric layer, and the second passivation layer, thereby exposing a portion of the terminal; a contact opening in the second passivation layer, thereby exposing a portion of one electrode of the passive device; and a second metal layer disposed on a lower surface of the second passivation layer wherein the via opening and the contact opening are filled with the second metal layer to electrically connect the electrode of the passive device with the terminal of the chip.