Patent ID: 9601467
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A microelectronic package, comprising: a substrate having an upper surface and a lower surface opposite the upper surface; a first wire bond wire of a first length coupled to the upper surface at a first end of the first wire bond wire; a first bond mass coupled to a second end of the first wire bond wire; a second wire bond wire of a second length coupled to the upper surface at a first end of the second wire bond wire; a second bond mass coupled to a second end of the second wire bond wire; the first wire bond wire and the second wire bond wire laterally jutting out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire; and the first wire bond wire and the second wire bond wire being horizontal for the distance with respect to being co-planar with the upper surface within +/−10 degrees.