Patent ID: 9667564
Date: 2017-05-30
CPC Classifications: H04L

Claim:
1. A method for implementing hierarchical high radix switching with a time-sliced crossbar comprising: providing a switching device comprising a plurality of inputs and a plurality of outputs; each input port belongs to one input group; and each output port belongs to one output group; providing a first respective link layer and data buffering logic block coupled to one said input group of said plurality of inputs; and providing a second respective link layer and data buffering logic block coupled to one said output group of said plurality of outputs; providing an arbitration element coupled to each said first respective link layer and data buffering logic block and coupled to each said second respective link layer and data buffering logic block; and providing a data crossbar coupled to each said first respective link layer and data buffering logic block and coupled to each said second respective link layer and data buffering logic block; one said input port receiving a packet in its data queues for one said output port; and said input port requesting an output for one said output port; each said input group, sending consolidated requests to each output by ORing the requests from the local input ports in said respective input group; each said output port, granting one of the requesting input groups using a rotating priority defined by a next-to-serve pointer; each said output group consolidating the output port grants and allowing one grant to pass back to one said input group; each said input port in said input group evaluating all incoming grants in an oldest packet first manner to form an accept; and each said input group consolidating the input port accepts and selecting one accept to send to the output port; providing said arbitration element with multiple input arbiters and multiple output arbiters; providing a separate arbitration path from a data path, each said input arbiter forming a request, queuing incoming packet destination information and managing active transfers; and each said output arbiter processing a grant, tracking subport availability and providing fairness using the next-to-serve pointer; each said first respective link layer and data buffering logic block and each said second respective link layer and data buffering logic block managing link protocol, and handling sequencing an arbitration winning packet out to the data crossbar, and receiving incoming crossbar data to sequence to an output link; and starting a data transfer, marking a time slice as busy, signaling data buffer logic and said data crossbar to start the packet data transfer, and transferring data in an assigned cycle once per supercycle and continuing data transfers until receiving an end of packet being signaled to guarantee all packet data is transferred; and marking the time slice as available.