Patent ID: 9634102
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A nonvolatile memory device comprising: a plurality of twin cells arrayed over a substrate, each of the twin cells including: a first source and a second source disposed in the substrate, a drain mesa protruding from a surface of the substrate between the first and second sources, a first floating gate overlapping with a first sidewall surface of the drain mesa and extending to the first source, and a second floating gate overlapping with a second sidewall surface of the drain mesa and extending to the second source, wherein the first and the second floating gates are arranged opposite to each other with respect to the drain mesa; and an isolation layer disposed in the substrate and separating the first source of a first twin cell among the plurality of twin cells from the second source of a second twin cell among the plurality of twin cells, wherein the first and second floating gates extend over portions of a top surface of the drain mesa.