Patent ID: 9536965
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; and a first heat dissipating layer disposed on the first gate portion and a second heat dissipating layer disposed on one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.