Patent ID: 9564889
Date: 2017-02-07
CPC Classifications: G09G,H03K

Claim:
1. A gate driving circuit, comprising plural-stage output circuits, an Nth stage output circuit of the plural-stage output circuits comprising: an Nth stage shift register configured to output an Nth pulse signal; and a mixer coupled to the Nth stage shift register and an (N+M)th stage shift register of an (N+M)th stage output circuit of the plural-stage output circuits connected to the Nth stage shift register in series, for respectively outputting a first clock signal and a predetermined pulse signal during different periods according to the Nth pulse signal and an (N+M)th pulse signal of the (N+M)th stage shift register; wherein pulse widths or phases of the first clock signal and the predetermined pulse signal are different, and N and M are positive integers.