Patent ID: 9680480
Date: 2017-06-13
CPC Classifications: H03L,H03M

Claim:
1. A reconfigurable, cascaded digital phase-locked loop integrated circuit coupleable to a reference frequency generator to generate an input signal having a reference frequency, the cascaded digital phase-locked loop integrated circuit comprising: a first digital phase-locked loop circuit configured to generate a first signal having a first frequency which is an integer multiple of the reference frequency, wherein the first digital phase-locked loop circuit includes a second digital phase-locked loop circuit coupled to the first digital phase-locked loop circuit, the second digital phase-locked loop circuit configured to generate a second, output signal having a second output frequency in response to a plurality of configuration parameters, the second frequency having a configurable fractional offset from the integer multiple of the reference frequency, and to match a phase of the second output signal with a first signal phase; and a memory storing the plurality of configuration parameters, at least one configuration parameter of the plurality of configuration parameters specifying the second output frequency.