Patent ID: 9634131
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A semiconductor device having a front side and a back side opposing the front side, which comprises: a) a metal collector layer on the backside, b) a layered semiconductor material disposed on the metal collector layer being selectively doped to provide; i) a first P-type collector layer disposed on the metal collector layer, ii) an N-type field stop layer disposed on the P-type collector layer; and iii) a lightly doped N-type drift layer disposed on the N-type stop layer, c) a gate trench having a conductive core that is surrounded by a gate oxide layer, that extends at least partially within the N-drift layer to subdivide the N-drift layer into an active cell region and a dummy cell region, which are disposed proximal to the front side of the device, d) an insulation layer at least partially covering the N-drift layer and the gate trench formed therein, e) a metal emitter layer disposed on the insulation layer and connected through a window in the insulation layer to the active cells region, which comprise: i) one or more N+ region alternating with a plurality of P+ regions, ii) a first P-well region disposed between the alternating N+ and P+ regions and the N− drift layer, the first P-well regions in active cells being continuous in a first direction along the gate trench and connected to the metal emitter electrode through the P+ regions, f) wherein the dummy cell region comprises one or more second P-well regions that are surrounded by the N− drift layer and isolated from the metal emitter layer by the insulation layer.