Patent ID: 9747979
Date: 2017-08-29
CPC Classifications: G11C,H01L

Claim:
1. A nonvolatile semiconductor storage device comprising: a plurality of memory cells arranged in a first matrix having rows and columns, each memory cell including a cell transistor and a variable resistance element connected to a first terminal of the cell transistor; a plurality of word lines provided, corresponding to the respective rows of the plurality of memory cells, each word line being connected to gates of the cell transistors included in the memory cells provided in the corresponding row; a plurality of first data lines provided, corresponding to the respective rows or columns of the plurality of memory cells, each first data line being connected to the variable resistance elements included in the plurality of memory cells provided in the corresponding row or column; a plurality of second data lines provided, corresponding to the respective rows or columns of the plurality of memory cells, each second data line being connected to second terminals of the cell transistors included in the plurality of memory cells provided in the corresponding row or column; a plurality of cell transistor performance measuring cells arranged in a second matrix having rows and columns, each cell transistor performance measuring cell including a transistor; at least one cell transistor performance measuring word line provided, corresponding to the respective rows of the at least one cell transistor performance measuring cell, each cell transistor performance measuring word line being connected to a gate of the at least one transistor provided in the corresponding row; a bit line driver configured to drive the first data line by applying a first voltage to the first data line; a source line driver configured to drive the second data line by applying a second voltage to the second data line; a column gate configured to select and connect one of the plurality of first data lines and one of the plurality of second data lines to the bit line driver and the source line driver, respectively; a bit line regulator configured to supply a third voltage to be driven by the bit line driver; a source line regulator configured to supply a fourth voltage to be driven by the source line driver; a bit line switch provided between the bit line driver and the bit line regulator; and a source line switch provided between the source line driver and the source line regulator, wherein: the transistor of the at least one cell transistor performance measuring cell is provided, corresponding to each row or column of the at least one cell transistor performance measuring cell, and a drain or source of the transistor of at least one cell transistor performance measuring cell provided in the row or column is connected to all or a portion of the plurality of first data lines, the transistor of the at least one cell transistor performance measuring cell is provided, corresponding to each row or column of the at least one cell transistor performance measuring cell, and one of the drain and source of the transistor of the at least one cell transistor performance measuring cell provided in the row or column, the one of the drain and source being not connected to the first data line, is connected to all or a portion of the plurality of second data lines, the bit line switch selects and supplies the third voltage supplied by the bit line regulator or a fifth voltage supplied by a current measuring device, to the bit line driver, and the source line switch selects and supplies the fourth voltage supplied by the source line regulator or a sixth voltage supplied by the current measuring device, to the source line driver.