Patent ID: 9660019
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A structure comprising: a semiconductor substrate comprising a first routing layer, a second routing layer, a third routing layer and a fourth routing layer; at least one concentric capacitor formed on the semiconductor substrate, wherein each of the at least one concentric capacitors comprises: a first plurality of capacitive perimeter plates formed in the first routing layer and a third plurality of capacitive perimeter plates formed in the third routing layer, the first plurality of capacitive perimeter plates and the third plurality of capacitive perimeter plates extending in a first direction; a second plurality of capacitive perimeter plates formed in the second routing layer and a fourth plurality of capacitive perimeter plates formed in the fourth routing layer, the second plurality of capacitive perimeter plates and the fourth plurality of capacitive perimeter plates extending in a second direction, wherein the second direction is different than the first direction, wherein a first set of the first plurality of capacitive perimeter plates is electrically coupled to a first set of the second plurality of capacitive perimeter plates to define an outer concentric capacitive plate, and wherein a second set of the first plurality of capacitive perimeter plates is electrically coupled to a second set of the second plurality of capacitive perimeter plates to define an inner concentric capacitive plate; a first plurality of capacitive cross-plates formed in the first routing layer, the first plurality of capacitive cross-plates extending longitudinally in the first direction, wherein each of the first plurality of capacitive cross-plates at least partially overlaps the second plurality of capacitive perimeter plates formed in the second routing layer, and wherein each of the first plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates by a first set of inter-layer vias, thereby increasing a capacitance of the at least one concentric capacitor; and a switching mechanism configured to selectively couple one of the outer concentric capacitive plate or the inner concentric capacitive plate to a signal source.