Patent ID: 9747972
Date: 2017-08-29
CPC Classifications: G06F,G11C

Claim:
1. A memory controller comprising: a first input buffer that determines a data signal that is to be received, based on a reference voltage; a second inputs buffer that inputs a data strobe signal that is to be received; a data latch circuit that fetches an internal data signal, which is outputted by the first input buffer, based on a phase of a rising edge and a falling edge of an internal data strobe signal, which is outputted by the second input buffer; a duty ratio detection circuit that detects a duty ratio of the internal data strobe signal, the duty ratio detection circuit including a reference voltage generating circuit that adjusts the reference voltage based on the duty ratio detected by the duty ratio detection circuit, the first phase difference detection unit includes: a first variable delay circuit that delays the internal data strobe signal by a delay amount based on a first variable delay setting value; and a first phase comparator that detects the first phase difference between a rising edge of a first delay data strobe signal delayed and output by the first variable delay circuit and the first reference edge of the clock and generates the first variable delay setting value according to the first phase difference, the second phase difference detection unit includes: a second variable delay circuit that delays the internal data strobe signal by a delay amount based on a second variable delay setting value; and a second phase comparator that detects the second phase difference between a falling edge of a second delay data strobe signal delayed and output by the second variable delay circuit and the second reference edge of the clock and generates the second variable delay setting value according to the second phase difference; and the duty ratio detection unit calculates the duty ratio based on a difference between the first variable delay setting value and the second variable delay setting value.