Patent ID: 9571094
Date: 2017-02-14
CPC Classifications: H03K

Claim:
1. A switch circuit provided at an input terminal of a semiconductor device, which is inputted with a positive or negative voltage, and controlling whether to transmit the positive or negative voltage to an internal circuit or shut off the positive or negative voltage, said switch circuit comprising: a first NMOS transistor having a drain connected to the input terminal of the semiconductor device, a source connected to a first node, and a gate connected to a second node; a second NMOS transistor having a drain connected to the first node, a source connected to a third node, and a gate connected to the second node; a third NMOS transistor having a source connected to a ground voltage, a drain connected to the first node, a gate connected to a switch control terminal via an inverter; and a boosting circuit having a boosting circuit control terminal connected to the switch control terminal, a voltage input terminal connected to a power supply, and a voltage output terminal connected to the second node, wherein the boosting circuit comprises: a rectifying element having an anode connected to the voltage input terminal and a cathode connected to a fourth node, a PMOS transistor having a drain connected to the voltage output terminal, a gate connected to the switch control terminal via the inverter, and source connected to the fourth node, a fourth NMOS transistor having a drain connected to the voltage output terminal, a gate connected to the switch control terminal via the inverter, and a source connected to the ground voltage, and a capacitor having one end connected to the fourth node and the other end connected to the boosting circuit control terminal; wherein the third node is connected to the internal circuit.