Patent ID: 9672923
Date: 2017-06-06
CPC Classifications: G11C,H01L

Claim:
1. A method for programming a PMOS multi-time programmable (MTP) flash memory cell, the memory cell comprising a select gate transistor connected in series with a floating gate transistor and a control gate capacitively coupled to the gate electrode of the floating gate transistor, the method comprising: applying a select gate bias voltage to a control terminal of the select gate transistor to generate a select gate drain current having a first current value; detecting a cell current flowing through the memory cell while applying to the control gate an increasing control gate bias voltage from a first voltage to a second, greater voltage; in response to detecting the cell current being less than a cell current limit, maintaining the control gate bias voltage at a constant voltage value while continuing to detect the cell current flowing through the memory cell; and in response to detecting the cell current being greater than the cell current limit, repeating the detecting the cell current while applying to the control gate the increasing control gate bias voltage, the control gate bias voltage being increased from a previous constant voltage value towards the second voltage until the control gate bias voltage reaches the second voltage.