Patent ID: 9548399
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a junction field effect transistor cell comprising a top gate region, a lateral channel region and a buried e region electrically separated from the top gate region, wherein the lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body, wherein the lateral channel region comprises at least two first zones of a first conductivity type and at least one second zone of a second conductivity type, the first and second zones alternating along the vertical direction, and wherein, in the lateral channel region, a first connection zone of the first conductivity type in the vertical projection of a source region structurally connects the first zones and the source region, and in the vertical projection of a vertical channel region a second connection zone structurally connects the first zones, and the at least one second zone extends from the first connection zone to the second connection zone, and wherein the at least one second zone floats.