Patent ID: 9712315
Date: 2017-07-18
CPC Classifications: G01R,G06F,H04B,H04L

Claim:
1. A method of analyzing a transient response of an electronic circuit, the method comprising: forming a model of a retimer, the model including: receiving and analyzing the output signal; wherein the signal input circuit includes a latch and that includes an latch input and a latch output, the latch input being coupled to ground through an input impedance and the latch output including a voltage controlled voltage source having positive and negative terminals, the negative terminal being coupled to ground through an output impedance and the positive terminal being connected to a latch output line, the method further comprising: forming a latch output signal based on a latch input signal received at the latch input with the voltage controlled voltage source, wherein the voltage controlled voltage source provides a high output when the latch input signal passes through a low to high transition value and continues to provide the high output until the latch input signal passes through a high to low transition value; wherein the voltage controlled voltage source generates a voltage that is based on the maximum of a first parameter and a second parameter; wherein the first parameter is P and k1 and k2 are constants, and V shl2h and V shh2l are switching voltages and v in (t) is the latch input signal.