Patent ID: 9666136
Date: 2017-05-30
CPC Classifications: G09G

Claim:
1. An array substrate comprising: a scanning driving unit configured to provide a row scanning signal to a plurality of gate lines, and a data driving unit configured to provide a data signal to a plurality of data lines, the plurality of gate lines and the plurality of data lines being horizontally and vertically crossed to form an array of pixel units arranged in a matrix form, wherein the array substrate further comprises: a control unit directly connected with the scanning driving unit and the data driving unit respectively, and configured to control the scanning driving unit to turn on each of the pixel units when a display device is powered off, such that charges stored in the pixel units are rapidly discharged through the data lines, wherein the control unit comprises: a control signal line for receiving an output signal of a timer, a first transistor and a second transistor; a gate of the first transistor is connected to the control signal line, a first electrode thereof is connected to the power line, and a second electrode thereof is connected to a ground; a gate of the second transistor is connected to the control signal line, a first electrode thereof is connected to the data signal line, and a second electrode thereof is connected to a ground.