Patent ID: 9602270
Date: 2017-03-21
CPC Classifications: H04J,H04L,H04W

Claim:
1. A method for clock drift compensation by a processor of a node in a network, comprising: receiving time synchronization information from a parent node in the network; determining a drift between a clock of the node and a clock of the parent node based upon the time synchronization information; determining a number of time slots of the network that have elapsed since making a last time adjustment based on previous time synchronization information received from the parent node; calculating a number of clock ticks in the drift; calculating a number of elapsed time slots that resulted in one clock tick of drift by dividing the number of time slots by the number of clock ticks to obtain a compensation interval; using the compensation interval to compensate a selected time slot by one clock tick, wherein the selected time slot corresponds to one time slot within the compensation interval; and repeating said compensating using a same value for the compensation interval until a subsequent drift, based on subsequent time synchronization information, meets or exceeds a predefined drift threshold, wherein the subsequent drift meeting or exceeding the predefined drift threshold triggers calculating a new value for the compensation interval.