Patent ID: 9558444
Date: 2017-01-31
CPC Classifications: G06N

Claim:
1. A computer-implemented method, the method being implemented by an integrated circuit on a chip, the integrated circuit including a first processor and a plurality of microengines that include a first microengine, the method comprising: storing, in a first memory, a first block that corresponds to a first neuron and a second block that corresponds to a second neuron, wherein the first block and the second block are stored sequentially in the first memory; obtaining, from the first memory, the first block that corresponds to the first neuron, wherein the first block includes connection information for the first neuron and an address representative of a location in a second memory, and wherein activation values matching the connection information for the first neuron are stored at the location in the second memory; obtaining, from the second memory, the activation values matching the connection information for the first neuron; sending, by the first processor, a packet that includes the connection information and the activation values, wherein the packet is sent to the first microengine to configure the first microengine as the first neuron; and generating, at the first microengine, a value representative of an output of the first neuron.