Patent ID: 9697319
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. A method of manufacturing a semiconductor device, the method comprising: placing a first plurality of cells into a first cell row with a first cell row height; placing a second plurality of cells into a second cell row with a second cell row height; placing a first cell into both the first cell row and the second cell row, wherein the first cell has a first cell height that is greater than the first cell row height and the second cell row height and less than a sum of the first cell row height and the second cell row height; adding a first filler region extending from the first cell to an edge of the first cell row, the first filler region connecting the first cell to a second cell adjacent to the first cell, the first filler region comprising a well with a stair step shape; and manufacturing a semiconductor device with the first filler region.