Patent ID: 9653141
Date: 2017-05-16
CPC Classifications: G11C

Claim:
1. A memory controller comprising: a control circuit configured to generate commands to be sent to a memory device, the commands including a write command; a table storing a plurality of weak cell row addresses of the memory device; and an address comparing unit configured to determine if a first address associated with a first write command to be sent to the memory device, the first address corresponding to one of the plurality of weak cell row addresses, wherein the control circuit is responsive to the address comparing unit to generate the first write command for a weak cell row corresponding to one of the plurality of weak cell row addresses stored in the table and a second write command for a normal cell row corresponding to one of a plurality of normal cell row addresses not identified by the table, wherein the control circuit is configured to generate a first precharge command that causes the memory device to perform a first precharge operation for the weak cell row, and to generate a second precharge command that causes the memory device to perform a second precharge operation for the normal cell row, and wherein the first precharge command is generated after a first time period from generating the first write command, and the second precharge command is generated after a second time period shorter than the first time period from generating the second write command.