Patent ID: 9613684
Date: 2017-04-04
CPC Classifications: G11C

Claim:
1. A multi-bank SRAM device comprising: a memory array comprising a plurality of SRAM banks, each SRAM bank including a block of single port SRAM memory cells organized as a matrix of rows and columns, a decoder, a sense amplifier, and a memory cell access circuitry, wherein each SRAM bank is capable of operating at a maximum frequency, f(m), and is configured for, and capable of, performing a read operation and a write operation together within a single f(m) clock cycle; a read/write control input circuit that receives a read operation and a write operation from an external source within a single external clock cycle of frequency, f(e), and provides those read and write operations to each SRAM bank; an address input circuit that receives a read address and a write address within the single external clock cycle of frequency, f(e), and provides those read and write addresses to each SRAM bank; a data input circuit that receives first and second beats of write data within the single external clock cycle of frequency, f(e), and provides the first and second beats of write data to each SRAM bank; and a bank access circuitry at the plurality of SRAM banks, coupled to the read/write control input circuit, the address input circuit, and the data input circuit, that controls combinations of the read and write operations to the SRAM banks at no greater than the maximum frequency, f(m); wherein the external clock cycle of frequency, f(e), is at least twice the maximum frequency, f(m), that each SRAM bank is capable of operating at, and the read/write control input circuit operates at the external clock cycle of frequency, f(e), and/or the address input circuit: operates at the external clock cycle of frequency, f(e), and/or the data input circuit: operates at the external clock cycle of frequency, f(e).