Patent ID: 9748265
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. An integrated structure, comprising: an upper deck comprising stacked first conductive levels, at least some of the first conductive levels being first wordline levels and comprising control gate regions of memory cells; one of the first conductive levels being a lowermost first conductive level; a lower deck is under the upper deck, with the lower deck comprising stacked second conductive levels, at least some of the second conductive levels being second wordline levels and comprising control gate regions of memory cells; one of the second conductive levels being an uppermost second conductive level; first vertically-extending channel material along the first conductive levels; a lower region of the first vertically-extending channel material being below the lowermost first conductive level; second vertically-extending channel material along the second conductive levels; an upper region of the second vertically-extending channel material being above the uppermost second conductive level; and at least one of the following structures: wherein the integrated structure includes the first charge-storage structure and does not include the second charge-storage structure.