Patent ID: 9570470
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a pixel portion over a substrate; a protective circuit over the substrate, wherein the protective circuit is placed on an outside of the pixel portion; a scan line electrically connected to the protective circuit; and a common wiring electrically connected to the protective circuit, wherein the protective circuit comprises a first transistor and a second transistor, wherein one of a source and a drain of the first transistor is electrically connected to the scan line, a gate of the first transistor, and one of a source and a drain of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the common wiring, a gate of the second transistor, and the other of the source and the drain of the second transistor, wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer comprising a channel region, and wherein the oxide semiconductor layer comprises indium, gallium, and zinc.