Patent ID: 9559079
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A semiconductor stack package comprising: a printed circuit board (PCB) having a first surface opposite to a second surface; a command/address (CA) bonding pad, a first data input/output (DQ) bonding pad, and a second DQ bonding pad disposed on the first surface; a first semiconductor chip disposed on the first surface between the CA bonding pad and the first DQ bonding pad, including a first CA chip pad and a first DQ chip pad; a second semiconductor chip disposed on the first surface between the first DQ bonding pad and the second DQ bonding pad, including a second CA chip pad and a second DQ chip pad; and a CA external connection terminal and a DQ external connection terminal disposed on the second surface, wherein the first CA chip pad is electrically coupled to the second CA chip pad through a first bonding wire, wherein the CA external connection terminal is electrically coupled to the first CA chip pad through the CA bonding pad, and wherein the DQ external connection terminal is electrically coupled to the first DQ chip pad through the first DQ bonding pad and is electrically coupled to the second DQ chip pad through the second DQ bonding pad.