Patent ID: 9735094
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A combined packaged power semiconductor device, comprising: a high-side (HS) MOSFET and a low-side (LS) MOSFET, each of said HS and LS MOSFETs comprising a bottom drain, a top gate and a top source; a lead frame comprising a die paddle and a plurality of pins separated and electrically insulated from said die paddle, wherein said LS MOSFET is flipped and stacked on said die paddle forming an electrical connection between said source of said LS MOSFET and a top surface of said die paddle, as such said source of said LS MOSFET is electrically connected to an exposed bottom surface of said die paddle; a first metal interconnection plate stacked on said drain of said flipped LS MOSFET, wherein said HS MOSFET directly stacked or flipped first and then stacked on said first metal interconnection plate, forming an electrical connection between said drain of said HS MOSFET or said source of said flipped HS MOSFET and said drain of said LS MOSFET through said first metal interconnection plate; a second metal interconnection plate stacked and electrically connected to said source of said HS MOSFET or said drain of said flipped HS MOSFET; an integrated circuit (IC) controller stacked on said die paddle, said IC controller comprising a plurality of electrodes, wherein electrical connections between said plurality of pins, said plurality of electrodes on said IC controller and electrodes of said HS and said flipped LS MOSFETs are formed; and an interposer wherein said gate of flipped LS MOSFET is electrically connected to a conductive top surface of said interposer and a bottom surface of said interposer is stacked on and electrically insulated from said die paddle.