Patent ID: 9668340
Date: 2017-05-30
CPC Classifications: H05K

Claim:
1. A method for electrolytically forming a finishing layer of metal at preselected locations on top of a contact metal layer disposed on at least a first side of a circuit board, the method comprising: forming a first dielectric film layer on top of a metal seed layer disposed on at least said first side of the circuit board; patterning the first dielectric film layer to expose the metal seed layer at preselected locations thereof and to mask the metal seed layer at preselected locations thereof; electrolytically forming a first contact metal layer on top of the exposed metal seed layer, wherein the first contact metal layer is not formed on the locations on the metal seed layer that are masked by the first dielectric film layer; removing the patterned first dielectric film layer to expose previously-masked locations of the metal seed layer; laminating a dielectric laminate over the first contact metal layer and over the exposed metal seed layer such that the dielectric laminate covers the first contact metal layer and the exposed metal seed layer; curing the dielectric laminate; removing preselected portions of the dielectric laminate to expose preselected locations of the first contact metal layer; electrolytically forming a second contact metal layer on top of the exposed preselected locations of the first contact metal layer; and electrolytically forming the finishing layer of metal on top of the second contact metal layer.