Patent ID: 9722552
Date: 2017-08-01
CPC Classifications: H03F,H04L

Claim:
1. A circuit comprising: a Darlington transistor pair comprising an input transistor and an output transistor wherein a gate of the input transistor is coupled to an input node, a drain of the output transistor is coupled to an output node, and a source of the input transistor is coupled to a gate of the output transistor to generate an output signal at the output node in response to an input signal received through the input node; a feedback coupling network having pair of split feedback resistors coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor; and a bias feedback network comprising a bias transistor and a resistive network that is coupled between a gate of the bias transistor, the gate of the output transistor, and the source of the input transistor, wherein a drain of the bias transistor is communicatively coupled to the input node through a tap point between the pair of split feedback resistors, and a source of the bias transistor is coupled to a fixed voltage node, and the resistive network consists of only resistive elements such that no inductors and no capacitors are provided between the gate of the bias transistor, the gate of the output transistor, and the source of the input transistor.