Patent ID: 9728461
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method comprising: forming a first gate stack over a first fin feature and a second gate stack over a second fin feature; removing the first gate stack to form a first gate trench that exposes a first channel region in the first fin structure; removing the second gate stack to form a second gate trench that exposes a second channel region in the second fin feature, the second channel region being formed of a semiconductor material; forming a hard mask (HM) layer within the second gate trench such that the HM layer physically contacts the semiconductor material of the second channel region without the HM layer being disposed within the first gate trench; performing a high-pressure-anneal (HPA) and changing a composition in the first channel region while the second channel region remains covered by the HM layer; removing the HM layer; and forming a first high-k/metal gate (HK/MG) within the first gate trench and a second HK/MG within the second gate trench.