Patent ID: 9674014
Date: 2017-06-06
CPC Classifications: H04L

Claim:
1. An apparatus comprising: a first simple two-input comparator configured to receive first and second input signals, and to responsively generate a first subchannel output; a second simple two-input comparator configured to receive third and fourth input signals, and to responsively generate a second subchannel output; and a third multi-input comparator configured to receive the first, second, third, and fourth input signals, and to responsively generate a third subchannel output; a first data detector connected to the second subchannel output; a second data detector connected to the third subchannel output; a configuration circuit configured to disable the third comparator and the second data detector in a first operating mode and to communicate the first subchannel output to a clock input of the first data detector, and to enable the third comparator and communicate a clock signal to clock inputs of the first and second data detectors in a second operating mode.