Patent ID: 9600618
Date: 2017-03-21
CPC Classifications: G01R,G06F

Claim:
1. A method for implementing system irritator accelerator field programmable gate array (FPGA) Units (AFUs) residing behind a Coherent Attached Processors Interface (CAPI) unit in a computer system comprising: providing a system processor; providing an accelerator function unit (AFU) implemented in a field programmable gate array (FPGA) residing behind a Coherent Attached Processors Interface (CAPI) unit; providing a plurality of AFU irritators including a read memory irritator, a write memory irritator, a cache injection irritator, an interrupt irritator, and scratch pad memory irritator implementing an AFU system irritator in said AFU; said system processor performing the steps of: configuring the AFU and enabling said AFU system irritator to execute irritation testing and verifying a design; replicating said AFU system irritator to create additional irritation testing and said AFU system irritator being re-programmable.