Patent ID: 9704799
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first diode and a second diode formed in a semiconductor substrate; a first input/output electrode coupled to an end of the first diode, a second input/output electrode coupled to an end of the second diode, and an intermediate electrode coupled to another end of the first diode and another end of the second diode, where the first and second input/output electrodes and the intermediate electrode are each formed on a surface of the semiconductor substrate; and a first wiring electrode coupled to the first input/output electrode via a first contact hole, and a second wiring electrode coupled to the second input/output electrode via a second contact hole, where the first and second wiring electrodes are each formed in a rewiring layer disposed on the surface of the semiconductor substrate, wherein the first wiring electrode is drawn in a region that has an overlap with the first input/output electrode and the intermediate electrode, but does not overlap a forming region of the second diode in planar view of the semiconductor device, and wherein the second wiring electrode is drawn in a region that has an overlap with the second input/output electrode and the intermediate electrode, but does not overlap a forming region of the first diode in planar view of the semiconductor device.