Patent ID: 9570118
Date: 2017-02-14
CPC Classifications: G11C

Claim:
1. A memory, comprising: peripheral circuitry powered by a first voltage provided by a variable first power supply; a memory array powered by a second voltage provided by a variable second power supply; a switch connected between the peripheral circuitry and the memory array; control circuitry configured to close the switch when the first and second voltages are the same and to open the switch when the first and second voltages are not the same; and voltage translation circuitry configured to shift a voltage level of an address signal output by the peripheral circuitry, from the first voltage to the second voltage for input of the signal by the memory array; wherein the memory is configured to enter a leakage reduction mode in which the voltage translation circuitry is disconnected from power and the second voltage is reduced to reduce current leakage from the memory array to the peripheral circuitry.