Patent ID: 9589632
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A resistive memory device comprising: a memory cell array comprising memory cells connected to a plurality of signal lines; and a column decoder comprising a first switch unit comprising at least two pairs of switches arranged in correspondence to each of the plurality of signal lines and a second switch unit comprising a pair of switches arranged in correspondence to the at least two pairs of switches of the first switch unit, wherein: the first switch unit comprises a first pair of switches connected to a first signal line, wherein the first pair of switches comprises a first switch and a second switch that are of the same type, and the second switch unit comprises a second pair of switches comprising a third switch and a fourth switch that are connected to the first pair of switches, and a selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch.