Patent ID: 9659614
Date: 2017-05-23
CPC Classifications: G11C

Claim:
1. An integrated circuit, comprising: a keeper circuit coupled to a bitline input path and configured to provide a first voltage source signal to the bitline input path based on a keeper enable signal, wherein the keeper circuit includes an n-type metal-oxide-semiconductor (NMOS) transistor, a first p-type MOS (PMOS) transistor, and a second PMOS transistor; and a logic device coupled to the bitline input path and configured to receive a bitline input signal, receive the first voltage source signal from the keeper circuit, and provide an inverted bitline input signal as an output signal, wherein the NMOS transistor is coupled between the first PMOS transistor and the second PMOS transistor, wherein the first PMOS transistor is configured to provide the first voltage source signal to the NMOS transistor based on a power gating signal, wherein the NMOS transistor is configured to receive the first voltage source signal from the first PMOS transistor and provide the first voltage source signal to the second PMOS transistor based on the keeper enable signal, and wherein the second PMOS transistor is configured to provide the first voltage source signal to the bitline input path based on the inverted bitline input signal received from the logic device.