Patent ID: 9672918
Date: 2017-06-06
CPC Classifications: G11C

Claim:
1. A semiconductor memory comprising: a first memory string including a first selection transistor above a semiconductor substrate, a second selection transistor above the first selection transistor, first memory cells above the second selection transistor, and a third selection transistor above the first memory cells; a second memory string including a fourth selection transistor, a fifth selection transistor above the fourth selection transistor, second memory cells above the fifth selection transistor, and a sixth selection transistor above the second memory cells; a first line connected to gate electrodes of the first selection transistor and the fourth selection transistor; a second line connected to a gate electrode of the second selection transistor; a third line, different from the second line, connected to a gate electrode of the fifth selection transistor; a first voltage generation circuit configured to generate a first voltage to the first line; a second voltage generation circuit configured to generate a second voltage to the second line; a control circuit configured to independently control the application of the first and second voltages; and a row decoder including a block decoder and a plurality of transfer transistors, the transfer transistors including a first transistor, a second transistor, a third transistor, and a fourth transistor, one ends of the first and second transistors being connected to the first line, one ends of the third and fourth transistors being connected to the second line, a gate of the first transistor being connected to a gate of the third transistor, and a gate of the second transistor being connected to a gate of the fourth transistor.