Patent ID: 9547489
Date: 2017-01-17
CPC Classifications: G06F

Claim:
1. A method for modifying a sequence of instructions in a read-only memory, the method comprising: providing set of addressable memory locations coupled to a processor; providing a set of one time programmable fuses further coupled to the processor; providing a sequence of instructions in a read-only memory coupled to the processor the sequence of instructions in the read only memory including at least one patch indicator at a desired location before a first instruction in the sequence of instructions, the at least one patch indicator identifying a patch instance: and enabling a patch process in the read-only memory that dynamically vectors to identified locations in the set of addressable memory locations and returns to the first instruction in the sequence of instructions in the read-only memory, wherein the patch instance includes mask information and is defined in no more than two words of N bits, where N is an integer, wherein when it is desired to modify the sequence of instructions, the patch instance comprising an instruction type, an address, and a return indicator is populated in one of the set of addressable memory locations, and information in the set of one time programmable fuses directs the processor to execute the patch instance stored in the addressable memory location, the patch instance executing based on the instruction type.