Patent ID: 9711361
Date: 2017-07-18
CPC Classifications: B23K,H01L

Claim:
1. A method of performing defect annealing at a defect anneal temperature T D of a semiconductor wafer having a surface that includes a pattern, comprising: forming from a CO passing at least 50% of the light beam in the first direction to form first transmitted light; focusing the first transmitted light at an intermediate focal plane to define a second intensity profile having a central peak and first side peaks immediately adjacent the central peak; truncating the second intensity profile within each of the first side peaks to define second transmitted light that forms on the wafer surface a first line image having between 2000 W and 3000 W of optical power and an intensity uniformity of within +/−5% over a first line length in the range from 5 mm to 100 mm; and scanning the first line image over the wafer surface to locally raise a temperature of the wafer surface to the defect anneal temperature T