Patent ID: 9633734
Date: 2017-04-25
CPC Classifications: G11C,H01L,H02M,H05K

Claim:
1. A driving circuit connected with a non-volatile cell array, the driving circuit comprising: a first transistor, wherein a source terminal and a body terminal of the first transistor are connected with a first supply voltage, a drain terminal of the first transistor is connected with a node a a second transistor, wherein a source terminal and a body terminal of the second transistor are connected with the first supply voltage, a drain terminal of the second transistor is connected with a node b a third transistor, wherein a source terminal of the third transistor is connected with a second supply voltage, a body terminal of the third transistor is connected with the first supply voltage, and a drain terminal and a gate terminal of the third transistor are connected with the node a a fourth transistor, wherein a source terminal of the fourth transistor is connected with the second supply voltage, a body terminal of the fourth transistor is connected with the first supply voltage, and a drain terminal and a gate terminal of the fourth transistor are connected with the node b a fifth transistor, wherein a source terminal and a body terminal of the fifth transistor are connected with the node a a sixth transistor, wherein a source terminal and a body terminal of the sixth transistor are connected with the node b a seventh transistor, wherein a source terminal and a body terminal of the seventh transistor are connected with the node a an eighth transistor, wherein a source terminal and a body terminal of the eighth transistor are connected with the node b a ninth transistor, wherein a drain terminal of the ninth transistor is connected with the node a a tenth transistor, wherein a drain terminal of the tenth transistor is connected with the node b an eleventh transistor, wherein a drain terminal of the eleventh transistor is connected with the node a a twelfth transistor, wherein a drain terminal of the twelfth transistor is connected with the node b a first biasing circuit connected with the node a a second biasing circuit connected with the node b