Patent ID: 9553718
Date: 2017-01-24
CPC Classifications: H03L,H04L

Claim:
1. A phase locked loop (PLL) circuit comprising: a phase comparator that compares a phase of a reference signal with a phase of a feedback signal and outputs a reference comparison result; a pulse width control unit that adjusts a pulse width of the reference comparison result, and outputs a first comparison result and a second comparison result having a pulse width smaller than that of the first comparison result; a first charge pump that outputs a first current according to the first comparison result; a second charge pump that outputs a second current according to the second comparison result; a first filter that removes a high-frequency component of a voltage generated based on the first current, and outputs a first control voltage; a second filter that outputs, as a second control voltage, a result obtained by integrating the second current; and an oscillator that generates an oscillating signal having a frequency according to the first and second control voltages, and feeds the oscillating signal back to the phase comparator as the feedback signal.