Patent ID: 9647107
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method for processing a vertical transistor comprising: forming a hemispherical or polygonal patterned semiconductor substrate; developing a first dielectric layer on some portions of the patterned semiconductor substrate, and forming a source region on a remaining portion of the patterned semiconductor substrate, the source region having a first doping type; forming a drift layer and a drain region film layer, the drift layer covering the first dielectric layer, the drain region film layer covering the drift layer, the drift layer and the drain region film layer comprising the first doping type; etching the drain region film layer and the drift layer to form a trench exposing the drift layer, the remaining drift layer forming a drift region, the remaining portion of the drain region film layer forming the drain region; forming a gate dielectric layer and a gate electrode, the gate dielectric layer covering the bottom and side walls of the trench, the gate electrode overlaying the gate dielectric layer and partially filling the trench; forming a second dielectric layer, the second dielectric layer covering the gate electrode, and filling said trench of the remaining portion of the trench.