Patent ID: 9536030
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. A method for optimizing an integrated circuit design, the method comprising: identifying, by one or more computer processors, one or more nets crossing a boundary between a parent block, having parent logic, and a child block, having child logic; inserting, by the one or more computer processors, based on a flat placement, one or more interior buffers on the one or more nets inside of the child block and one or more exterior buffers on the one or more nets outside of the child block and inside of the parent block, such that each of the one or more nets includes at least one interior buffer and at least one exterior buffer, wherein the at least one interior buffer and the at least one exterior buffer define a buffer pair for each of the one or more nets; determining, by the one or more computer processors, a first flat placement for the parent logic and a second flat placement for the child logic such that the at least one interior buffer and the at least one exterior buffer in the buffer pair for each net are placed substantially near to one another; and determining, by the one or more computer processors, one or more pin locations for the child block based, at least in part, on the second flat placement for the child logic.