Patent ID: 9536969
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of forming a split gate memory cell with a self-aligned spacer, comprising: providing a substrate including a pair of select gates and a corresponding hard mask layer disposed thereover; forming a charge trapping layer on upper surfaces of the hard mask layer, along hard mask sidewalls, along select gate sidewalls, and over an upper surface of the substrate; forming a memory gate material by depositing a conductive material over the charge trapping layer; after forming the memory gate material, performing a planarization process that lowers the conductive material, removes an upper portion of the charge trapping layer, and stops on the hard mask layer, the lowered conductive material being coplanar with the hard mask layer; performing an etch of the memory gate material to leave upper sidewalls of the charge trapping layer and an upper surface of the hard mask layer exposed; forming a pair of memory gate spacers along the upper sidewalls of the charge trapping layer over the memory gate material; and removing a portion of the memory gate material not covered by the pair of memory gate spacers, thereby forming a pair of memory gates about outermost sides of the pair of select gates.