Patent ID: 9553190
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: an active pattern protruding from a substrate; a gate structure crossing over the active pattern; source/drain regions disposed on the active pattern at opposite sides of the gate structure, wherein each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern, and wherein the first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern; an interlayer insulating layer on the gate structure; and contact plugs disposed in a contact hole that penetrates the interlayer insulating layer and the second epitaxial pattern and exposes a portion of the first epitaxial pattern, the contact plugs connected to the portion of the first epitaxial pattern, wherein the portion of the first epitaxial pattern has an upper surface contacting the contact plug, and the upper surface is parallel to a top surface of the substrate.