Patent ID: 9698155
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, comprising: alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate, each of the plurality of second insulating layers being a single layer which has a different material from each of the plurality of first insulating layers; forming spaces between the plurality of first insulating layers by partially etching the plurality of second insulating layers, wherein the spaces are defined by the plurality of first insulating layers and remaining portions of the plurality of second insulating layers; forming a plurality of horizontal electrodes in the spaces; and forming a contact structure penetrating the plurality of first insulating layers and the remaining portions of the plurality of second insulating layers, wherein after the forming of the spaces, the forming of the contact structure is performed, and wherein the remaining portions of the second insulating layers are interposed between the contact structure and the plurality of horizontal electrodes.