Patent ID: 9634862
Date: 2017-04-25
CPC Classifications: H04L

Claim:
1. An interconnect apparatus configured to communicate data packets through a network, the data packets arranged in a plurality of sub-packets including an address sub-packet that specifies a target node circuit for receiving the packet, the interconnect apparatus comprising: at least one node circuit of a plurality of node circuits interconnected in a network; and at least one bus coupling ones of the plurality node circuits in a selected arrangement, wherein the at least one bus includes parallel data lines configured to transmit, in parallel, multiple bits that make up ones of the sub-packets, and the at least one node circuit configured to receive the address sub-packet and determine routing based on: wherein the interconnect apparatus is configured to transfer the entire address sub-packet to each of multiple ones of the plurality of node circuits because the plurality of node circuits are each configured to route the plurality of sub-packets based on a respective bit of the address subpacket and are not configured to discard bits of the address sub-packet.