Patent ID: 9558126
Date: 2017-01-31
CPC Classifications: G06F

Claim:
1. A computer-implemented method, comprising: receiving a first input/output (I/O) trace including a list of storage addresses and sizes that were subject to a plurality of I/O requests from a first workload during a first period of time; running the first I/O trace through a cache simulation using a plurality of simulated cache sizes to determine a first miss ratio curve (MRC) for the first workload; receiving a second I/O trace including a list of storage addresses and sizes that were subject to a plurality of I/O requests from the first workload during a second period of time; running the second I/O trace through the cache simulation to determine a second MRC for the first workload; determining a first cache size corresponding to a target miss rate for the first workload using the first MRC; determining a second cache size corresponding to the target miss rate for the first workload using the second MRC; generating a first fingerprint of the first I/O trace and a second fingerprint of the second I/O trace; selecting the first cache size or the second cache size as a cache size for the first workload when the first and second fingerprints are within a threshold level of similarity with one another, wherein the first cache size is selected when the first cache size is larger than the second cache size, and wherein the second cache size is selected when the second cache size is larger than the first cache size; selecting a combination of the first and second cache sizes as the cache size for the first workload when the first and second fingerprints are not within a threshold level of similarity with one another; and generating a recommended cache size based upon the selected cache size for the first workload.