Patent ID: 9716041
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device, comprising; forming a pre-fin extending in a first direction, the pre-fin including a first region, a second region and a third region separating the first region from the second region; forming first and second gates on the pre-fin to extend in a second direction intersecting the first direction, the first and second gates being spaced apart from each other in the first direction and overlapping with the first and second regions, respectively; forming first and second dummy spacers on the first and second regions, respectively, to form a first trench in the third region that exposes the third region; forming a second trench by etching the exposed third region using the first and second dummy spacers as masks to separate the pre-fin into first and second active fins corresponding to the first and second regions, respectively; forming a dummy gate by filling the first and second trenches; and removing the first and second dummy spacers after the dummy gate has been formed.