Patent ID: 9563590
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. A device, comprising: data storage including one or more registers configured to store data; a plurality of external interfaces, each of the plurality of external interfaces configured to receive substantially simultaneously during a first communication interval a data access request for access to the one or more registers, the data access requests comprising one of a read request to the one or more registers and a write request to the one or more registers; an arbitrator communicatively coupled to each of the plurality of external interfaces; and an interface bus communicatively coupled between the arbitrator and the one or more registers, wherein the arbitrator is configured to arbitrate control of the interface bus between the plurality of external interfaces during a first single processing interval subsequent to the first communication interval to complete each write request and retrieve data for each read request during the first single processing interval, and wherein the plurality of external interfaces are configured to substantially simultaneously transmit the retrieved data for each read request during a second communication interval subsequent to the first single processing interval.