Patent ID: 9583179
Date: 2017-02-28
CPC Classifications: G11C,H01L

Claim:
1. A three-dimensional (3D) memory block, comprising: a random access memory (RAM) memory cell disposed in a first tier of a 3D integrated circuit (IC) (3DIC); at least one read access port disposed in a second tier of the 3DIC, the at least one read access port configured to provide read access to the RAM memory cell, wherein each read access port of the at least one read access port comprises a read transistor coupled to the RAM memory cell; at least one monolithic intertier via (MIV) coupling the at least one read access port to the RAM memory cell; a first voltage rail supplied with a first voltage disposed in the first tier of the 3DIC, the first voltage rail configured to supply the first voltage to the RAM memory cell; and a second voltage rail supplied with a second voltage lower than the first voltage supplied to the first voltage rail, the second voltage rail disposed in the second tier of the 3DIC and configured to supply the second voltage to the at least one read access port.