Patent ID: 9728528
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. An EDA (electronic design automation) tool, comprising: a non-transitory memory device having stored thereon: computer executable instructions causing a computer to make a first layout for a circuit design, the first layout including a floating p-well including a first n-type transistor and a floating n-well including a first p-type transistor, and the first layout including a first junction between differently doped regions, the first junction beneath the floating p-well, between the floating p-well and an underlying substrate region, wherein the n-well and the p-well are physically connected directly to each other along a range of shared well depths; and computer executable instructions causing the computer to make a second layout for the circuit design, the second layout including a first non-floating p-well and a first non-floating n-well having a same fixed well bias.