Patent ID: 9589850
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method comprising: providing a dielectric layer over first and second type transistor regions; providing first channel-cavities and second channel-cavities in the dielectric layer in each of the first and second type transistor regions, wherein the first channel-cavities have a greater width than the second channel-cavities; conformally forming a gate dielectric layer in the first and second channel-cavities, and on an upper surface of the dielectric layer; conformally forming a first-type work-function metal layer on the gate dielectric layer; forming a block mask over the first-type transistor region; removing the first-type work-function metal layer from the second-type transistor region; removing the block mask; conformally forming a second-type work-function metal layer on all exposed surfaces; forming a metal barrier layer on exposed surfaces and filling the second channel-cavities; filling the first channel-cavities with a conductive material; planarizing all material layers in the first channel-cavities and the second channel-cavities down to the upper surface of the dielectric layer, where the material layers comprise the second-type work-function metal layer, the metal barrier layer, and the conductive material; and applying dual tilted ion beams to recess the gate dielectric, first and second-type work function metal, and metal barrier layers, wherein a pair of crossing adjacent ion beams forms adjacent angles with respect to a line perpendicular to an upper surface of the first-type work function metal layer and the second-type work function metal layer, and wherein the ion beams have an energy level of 20 to 100 electron volts.