Patent ID: 9704995
Date: 2017-07-11
CPC Classifications: B82Y,H01L

Claim:
1. A semiconductor device fabrication process comprising: etching a first trench in a silicon substrate, wherein a length of the first trench is at least a channel length of the device and is bounded by a site for a source region and a site for a drain region; forming at least an oxide layer on top of the first trench; placing a stack of semiconducting layers on top of both the oxide layer and silicon substrate, wherein the stack comprises a plurality of semiconducting layers that alternate between at least two types of semiconducting layers and a bottom of the stack makes contact with the silicon substrate on either side of the first trench; creating a fin pattern from the stack; removing a portion of semiconducting layers of any type other than a first type from the stack, wherein the portion has a length approximately equal to that of the channel length, and wherein semiconducting layers of the first type form nanowires in a gate region of the device; and forming a silicon layer, a silicon dioxide layer and a high-k film on the nanowires in the gate region.