Patent ID: 9553205
Date: 2017-01-24
CPC Classifications: G02F,G09G,G11C,H01L

Claim:
1. A driver circuit comprising: a shift register unit comprising: n signal lines (n is a natural number of four or more); and p buffers (p is a natural number ranging one to (n−3)), the p buffers each comprising an output terminal, wherein one of a source and a drain of the first transistor is electrically connected to a high power supply potential line, wherein the other of the source and the drain of the first transistor is electrically connected to each of the p buffers and one of a source and a drain of the second transistor, wherein a gate of the first transistor is electrically connected to the set signal line, wherein the other of the source and the drain of the second transistor is electrically connected to a low power supply potential line, wherein a gate of the second transistor is electrically connected to each of the p buffers, one of a source and a drain of the fourth transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor, wherein one of a source and a drain of the third transistor is electrically connected to the high power supply potential line, wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein a gate of the third transistor is electrically connected to a first signal line of the n signal lines, wherein a gate of the fourth transistor is electrically connected to a second signal line of the n signal lines, wherein the other of the source and the drain of the fifth transistor is electrically connected to the low power supply potential line, wherein a gate of the fifth transistor is electrically connected to the set signal line, wherein the other of the source and the drain of the sixth transistor is electrically connected to the high power supply potential line, wherein a gate of the sixth transistor is electrically connected to a reset signal line, wherein a first buffer of the p buffers is electrically connected to a third signal line of the n signal lines, and wherein a second buffer of the p buffers is electrically connected to a fourth signal line of the n signal lines.