Patent ID: 9665194
Date: 2017-05-30
CPC Classifications: G02F,G06F

Claim:
1. A display device comprising: a translucent opposite substrate having a sensing unit provided with a first electrode pattern and a second electrode pattern, the first electrode pattern and the second electrode pattern each provided by a transparent conductive film, the first electrode pattern extending, along a first direction, the second electrode pattern extending along a second direction intersecting the first direction; an element substrate provided with a pixel unit in accordance with the sensing unit, a pixel unit including a plurality of light-emitting, elements arranged in a matrix; a sealing member having a closed-loop pattern surrounding the sensing unit, the sealing member fixing the translucent opposite substrate and the element substrate to each other with the translucent opposite substrate and the element substrate placed opposite each other; and a filling material provided above the pixel unit, the filling material is arranged inside and adjacent to the sealing member, wherein the translucent opposite substrate has an output wiring overlapping a portion of the sealing member in plan view, a protective insulating layer covering a side surface and an upper surface of the output wiring, and a peripheral member provided as overlapping the sealing member, the output wiring, the protective insulating layer and the peripheral member are provided over the same side with the first electrode pattern at the translucent opposite substrate; the protective insulating layer is provided with an opening through which an upper end face of the output wiring is exposed, and a side surface and a bottom surface of the protective insulating layer is covered with the sealing member; the first electrode pattern is extended from the sensing unit and electrically connected to the output wiring through the opening of the protective insulating layer, the first electrode pattern including an overlap region of part of the overlap with the pixel unit arranged in a matrix in a plan view, the output wiring and the protective insulating layer are arranged adjacent to the first electrode pattern in the overlap region, the first electrode pattern is in a region overlapping with the sealing member covers a part of a top surface of the protective insulating layer, the sealing member is provided to bury the peripheral member, wherein the peripheral member comprises: a dummy output wiring overlapping a portion of the sealing member in plan view, a part of the protective insulating layer covering a side surface and an upper surface of the dummy output wiring, the part of the protective insulating layer is provided with a dummy opening through which an upper end face of the dummy output wiring is exposed, a dummy first electrode pattern is electrically connected to the dummy output wiring through the dummy opening of the part of the protective insulating layer, the sealing member covers a side surface and upper surface of the dummy first electrode pattern, the dummy first electrode pattern is not electrically connected to the first electrode pattern, and the dummy first electrode pattern is nearer to a corner portion of the translucent opposite substrate than the first electrode pattern in plan view.