Patent ID: 9553596
Date: 2017-01-24
CPC Classifications: H03L,H04B

Claim:
1. A frequency synthesizer, comprising: a subband phase-locked loop (PLL) including an adjustable non-integer frequency divider, the subband PLL outputting a channel frequency of a maximum frequency band of all frequency bands by adjusting a divisor of the adjustable non-integer frequency divider; and a main PLL including an adjustable integer frequency divider and a mixer connected with an output end of the main PLL and an output end of the subband PLL, the main PLL outputting a center frequency required for each frequency band of the all frequency bands by adjusting a divisor of the adjustable integer frequency divider, the mixer mixing the center frequency and the channel frequency to produce a band frequency, wherein a quantization noise generated by the adjustable non-integer frequency divider is filtered out by the subband PLL to reduce an impact of the quantization noise on the main PLL.