Patent ID: 9559719
Date: 2017-01-31
CPC Classifications: H03M

Claim:
1. An apparatus comprising: a first stage including an integrator; a second stage coupled to the first stage, the second stage including an amplifier, a first capacitor, and a second capacitor coupled in series with the first capacitor between an input node and an output node of the amplifier; a quantizer coupled to the output node of the amplifier; and a feedback path coupled to an output node of the quantizer and to the first and second stages, the feedback path including a digital-to-analog converter (DAC), the DAC including an input node coupled to the output node of the quantizer and an output node coupled to the input node of the amplifier, wherein the second stage includes a resistor coupled in series with the first and second capacitors between the input and output nodes of the amplifier.