Patent ID: 9734269
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. A method of performing static timing analysis (STA) and power analysis of an integrated circuit, comprising: generating first timing data for the integrated circuit, wherein the first timing data is related to one or more variations of operating conditions for the integrated circuit, wherein the first timing data includes circuit path delay data for circuit components of the integrated circuit and circuit power data for circuit components of the integrated circuit, and wherein the circuit components include transistors of different types; characterizing the first timing data generated for the integrated circuit in association with the one or more variations of operating conditions; extracting parameter values from the first timing data based on the characterized first timing data and in association with the one or more variations of operating conditions; generating second timing data for the integrated circuit, wherein the second timing data is based on the characterized first timing data and the extracted parameter values; and storing the second timing data in memory, wherein the second timing data is used for performing static timing analysis (STA) and power analysis of the integrated circuit.