Patent ID: 9653547
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising: forming a plurality of channel material layers and a plurality of sacrificial material layers in a stacked configuration on a substrate, wherein one of the plurality of sacrificial material layers is a top layer of the stacked configuration; forming a plurality of dummy gates spaced apart from each other on the stacked configuration; removing portions of the stacked configuration to create openings in the stacked configuration corresponding to spaces between adjacent dummy gates of the plurality of dummy gates; epitaxially growing source/drain regions from the plurality of channel material layers in the openings corresponding to the spaces between the adjacent dummy gates of the plurality of dummy gates; depositing dielectric layers to fill in the spaces between the adjacent dummy gates of the plurality of dummy gates and portions of the openings around the source/drain regions; removing the plurality of dummy gates; forming etch stop layers on remaining portions of the top layer of the stacked configuration; removing remaining portions of the plurality of sacrificial material layers; depositing gate structures on respective upper surfaces the etch stop layers in areas where the plurality of dummy gates were removed, and under the etch stop layers in areas where the remaining portions of the plurality of sacrificial material layers were removed; removing the gate structures from the upper surfaces of the etch stop layers to expose the upper surfaces of the etch stop layers; depositing dielectric cap layers on the upper surfaces of the etch stop layers in place of the removed gate structures; and forming contacts through the dielectric layers between adjacent dielectric cap layers, wherein the contacts contact the source/drain regions.