Patent ID: 9613922
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a package substrate including: first portions where the solder resist is not present; a second portion where the solder resist is not present, the second portion being a different portion than the first portions; a semiconductor chip mounted on the package substrate; plating layers formed on the parts of the wirings, respectively; bumps disposed on the parts of the wirings via the plating layers, respectively; and a sealing resin sealing the semiconductor chip, wherein, in plan view, the parts of the wirings which are exposed from the solder resist at the first portions, are arranged along each side of the surface of the substrate, wherein no part of each of the wirings is present at the second portion, wherein, in plan view, the second portion surrounds the parts of the wirings, wherein, in the cross section view, the solder resist has a side surface located at the second portion, the side surface of the solder resist being located more inwardly from a side of the substrate in the first direction than the cutting surface of the substrate, and wherein an end surface of each of the wirings, which is directed toward the second portion, is exposed from the solder resist.