Patent ID: 9543306
Date: 2017-01-10
CPC Classifications: G11C,H01L

Claim:
1. A sub word line driver of a semiconductor memory device comprising: a semiconductor substrate including a PMOS region and a NMOS region, wherein an active region is formed to extend in a first direction in the PMOS section; a first metal contact formed over an edge of the active region; a second metal contact formed over a middle of the active region; a gate electrode extended in a second direction perpendicular to the first direction, and formed to include a hole through which a part of the active region is exposed; a metal pad formed over the first metal contact and coupled to the first metal contact; and a metal signal line coupled to the second metal contact, extended in the second direction, and bent in the first direction at a specific part adjacent to the metal pad, wherein the second metal contact is formed over the exposed active region inside the hole of the gate electrode with a gap between the second metal contact and the Rate electrode, wherein the sub word line driver is repeatedly arranged in the first direction, and wherein the bent part of the metal signal line of the sub word line driver is arranged to overlap with a first adjacent sub word line driver, and the bent part of the metal signal line of a second adjacent sub word line driver is arranged to overlap with the sub word line driver such that an upper portion of the gap in the first direction has substantially a same size as a lower portion of the gap in the first direction.