Patent ID: 9589970
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. An antifuse one-time programmable (OTP) memory cell, comprising: a semiconductor substrate; an isolation region in the semiconductor substrate, the isolation region having a top surface; at least a fin structure protruding from the top surface of the isolation region, wherein the fin structure has an end portion with a sidewall surface above the top surface; a select gate transistor on the fin structure, wherein the select gate transistor comprises a select gate traversing the fin structure, a select gate dielectric layer between the select gate and the fin structure, a drain region in the fin structure on one side of the select gate, and a source region in the fin structure on the other side of the select gate; and a vertical program gate transistor serially connected to the select gate transistor through the source region, wherein the vertical program gate transistor comprises a program gate directly disposed on the isolation region and covering the sidewall surface of the end portion, and a program gate dielectric layer between the program gate and the sidewall surface.