Patent ID: 9559686
Date: 2017-01-31
CPC Classifications: H03K

Claim:
1. A circuit, comprising: a first power node configured to carry a first voltage level; a second power node configured to carry a second voltage level; an output node; a plurality of first transistors serially coupled between the first power node and the output node, a gate terminal of a first transistor of the plurality of first transistors is configured to receive a first signal being set at: a gate terminal of a second transistor of the plurality of first transistors is configured to receive a second signal being set at the third voltage level; and a gate terminal of a third transistor of the plurality of first transistors is configured to receive a third signal being set in a manner that an absolute value of a source-gate voltage or an absolute value of a drain-gate voltage of the third transistor of the plurality of first transistors is equal to or less than the fourth voltage level; and a plurality of second transistors serially coupled between the second power node and the output node, a gate terminal of a first transistor of the plurality of second transistors is configured to receive a fourth signal being set at: a gate terminal of a second transistor of the plurality of second transistors is configured to receive a fifth signal being set at the fourth voltage level; and a gate terminal of a third transistor of the plurality of second transistors is configured to receive a sixth signal being set in a manner that an absolute value of a gate-source voltage or an absolute value of a gate-drain voltage of the third transistor of the plurality of second transistors is equal to or less than the fourth voltage level.