Patent ID: 9741744
Date: 2017-08-22
CPC Classifications: G02F,H01L

Claim:
1. An array substrate comprising a thin film transistor, a data line, a gate line and a passivation layer) disposed thereon, wherein the TFT comprises a gate electrode, a source electrode and a drain electrode, the data line is connected to the source electrode of the TFT, the gate line is connected to the gate electrode of the TFT, and the passivation layer covers the TFT, the data line and the gate line, and wherein the array substrate further comprises a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is disposed in a display area of the array substrate and on the passivation layer and above the TFT, the second conductive structures disposed on the passivation layer and above at least one of the data line and the gate line.