Patent ID: 9728935
Date: 2017-08-08
CPC Classifications: H01L,H01S

Claim:
1. A chip-scale package comprising: an edge-emitting semiconductor device chip, having a chip area, comprising a top surface and an opposite bottom surface; a top submount, having a top-submount area, disposed on the top surface of the edge-emitting semiconductor device chip; and a bottom submount, having a bottom-submount area, disposed on the bottom surface of the edge-emitting semiconductor device chip, wherein the top-submount area and the bottom-submount area are each greater than the chip area and less than or equal to about 1.2 times the chip area, a portion of the top submount overhangs a front facet of the edge-emitting semiconductor device chip and the bottom submount, and the front facet of the edge-emitting semiconductor device chip overhangs the bottom submount.