Patent ID: 9583200
Date: 2017-02-28
CPC Classifications: G11C

Claim:
1. A memory system comprising: a controller chip; and a memory chip configured to receive a plurality of commands from the controller chip; the memory chip comprising a first memory cell; a second memory cell; and a control circuit configured to apply a write voltage to a gate of the first memory cell when the memory chip receives an instruction of executing a write operation, suspend the write operation when the memory chip receives a suspend command, and resume the write operation when; the memory chip receives a resume command after the control circuit suspends the write operation, the memory chip being configured to output a first signal and a second signal to the controller chip when the memory chip receives a status command after the control circuit suspends the write operation and before the memory chip resumes the write operation, the first signal and the second signal indicating whether the write operation is completed or not and that the write operation is suspended.