Patent ID: 9564219
Date: 2017-02-07
CPC Classifications: G11C

Claim:
1. In a non-volatile flash memory circuit having an array of memory cells formed according to a NAND type of architecture, a method of determining NAND strings of a block of the array having slow to program memory cells, the memory cells of the NAND strings being formed along word lines and each of the NAND strings of the block connected along a corresponding bit line, the method comprising: performing a first write operation for a first set of memory cells of the block along a first word line corresponding to a first set of a plurality bit lines, but not for a second set of one or more memory cells of the block along the first word line corresponding to a second set of one or more bit lines, where the second set of bit lines is distinct from the first set of bit lines; determining an amount of current through the first set of memory cells during the first write operation; performing a second write operation for the second set of memory cells, but not for the first set of memory cells; determining an amount of current through the second set of memory cells during the second write operation; performing a comparison of the amount of current through the first set of memory cells during the first write operation with the amount of current through the second set of memory cells during the second write operation; and based upon the comparison, performing a determination of whether NAND strings corresponding to the second set of bit lines include memory cells that are slow to program.