Patent ID: 9558988
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method for manufacturing a shallow trench isolation (STI) region, said method comprising: providing a semiconductor substrate with a third dielectric layer and a hard mask layer stacked in that order over the semiconductor substrate; performing a first etch through regions of the third dielectric layer, the hard mask layer, and the semiconductor substrate to form a trench within the semiconductor substrate; forming a first dielectric layer lining the trench; forming a second dielectric layer filling the trench over the first dielectric layer; performing an ultraviolet curing process to the second dielectric layer; performing an annealing process to the second dielectric layer; performing a planarization into the second dielectric layer to about even with an upper surface of the hard mask layer; and performing a second etch through the hard mask layer to remove the hard mask layer.