Patent ID: 9698260
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method for forming a high voltage device comprising: providing a substrate prepared with isolation regions, wherein the isolation regions include a device isolation region and an internal isolation region, wherein the device isolation region defines a device region within the substrate and the internal isolation region is disposed within the device region, wherein a top substrate surface is coplanar with a top surface of the isolation regions; forming a first device well in the device region; forming a doped region within the first device well, wherein the doped region extends from the top substrate surface to a depth shallower than a bottom of the isolation regions; forming a recessed region after the doped region is formed in the first device well, wherein a depth of the recessed region is about equal to the depth of the doped region; forming a second device well in the device region and adjacent to the first device well; and forming a transistor, wherein forming the transistor comprises