Patent ID: 9653163
Date: 2017-05-16
CPC Classifications: G11C

Claim:
1. A memory cell comprising: first and second resistive elements, at least one of which is programmable to have one of at least two resistive states, a data value being represented by the relative resistances of the first and second resistive elements, the first resistive element being coupled between a first storage node and a first intermediate node, the second resistive element being coupled between a second storage node and a second intermediate node; a first transistor coupled between said first storage node and a first supply voltage; a second transistor coupled between said second storage node and said first supply voltage, wherein a control node of said first transistor is coupled to said second storage node and a control node of said second transistor is coupled to said first storage node; a third transistor coupled between the first and second intermediate nodes; a fourth transistor coupled by its main current nodes between said first storage node and a data input node; and control circuitry configured, during a write phase, to activate said third and fourth transistors and to couple said data input node to a second supply voltage via a first circuit block to generate a current in a first direction through said first and second resistive elements to program the resistive state of at least one of said elements.