Patent ID: 9576963
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A manufacturing method of a vertical channel transistor array, comprising: providing a semiconductor substrate; forming a plurality of first trenches in the semiconductor substrate, the first trenches being arranged in parallel and extended in a column direction; forming a plurality of embedded bit lines at bottoms of the first trenches, the embedded bit lines being electrically connected to the semiconductor substrate; forming a plurality of second trenches in the semiconductor substrate, the second trenches being arranged in parallel and extended in a row direction, the semiconductor substrate being divided by the first trenches and the second trenches into a plurality of semiconductor pillars; forming a gate dielectric layer on surfaces of the semiconductor pillars; forming a plurality of embedded word lines at bottoms of the second trenches, wherein each of the embedded word lines is located at a first side wall of one of the second trenches and connected to first sides of the semiconductor pillars in the same row, not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides, and only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row; and forming an isolation structure between a second side wall of each of the second trenches and each of the embedded word lines, the first side wall being opposite to the second side wall, wherein steps of forming the embedded word lines comprise: sequentially forming a first barrier layer and a first conductive layer in the second trenches; removing a portion of the first barrier layer and a portion of the first conductive layer, such that a surface of the first barrier layer and a surface of the first conductive layer are lower than a surface of the semiconductor substrate; and patterning the first barrier layer and the first conductive layer, forming the embedded word lines at the first side walls of the second trenches, and forming an opening between the second side wall of each of the second trenches and each of the embedded word lines, respectively.