Patent ID: 9595523
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A semiconductor integrated circuit device comprising: a standard cell region on a substrate; a first active region disposed in the standard cell region, wherein the first active region has a length in a first direction; a second active region disposed in the standard cell region, wherein the second active region has a length in the first direction, and wherein the length of the second active region is greater than the length of the first active region; a first gate electrode that extends across the first active region in the first direction, wherein the first gate electrode has a length in the first direction; a second gate electrode that extends across the second active region in the first direction wherein the second gate electrode has a length in the first direction that is greater than the length of the first gate electrode in the first direction; a first dummy gate pattern spaced apart from the first gate electrode; and a second dummy gate pattern spaced apart from the first gate electrode; wherein the first gate electrode is arranged between the first and second dummy gate patterns in the first direction, wherein an axis is defined in the first direction, and wherein the axis extends in the first direction through the length of the first gate electrode and through the first and second dummy gate patterns.