Patent ID: 9618562
Date: 2017-04-11
CPC Classifications: G01R,G11C

Claim:
1. A semiconductor device comprising: a first external terminal configured to be supplied with a power supply potential from outside the semiconductor device; a second external terminal configured to be supplied with a first internal potential from outside the semiconductor device; a third external terminal configured to be supplied with a test signal to be activated when the semiconductor device enters a test mode; a first internal-potential generation circuit configured to generate the first internal potential from the power supply potential and output the first internal potential to a first node; and an internal-potential force circuit that includes a first switch element coupled between the first node and the second external terminal, the internal-potential force circuit configured to cause the first switch element to enter into an off-state when the test signal supplied to the third external terminal is activated and a potential level of the first external terminal is at a first level, and cause the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is at a second level different from the first level.