Patent ID: 9614542
Date: 2017-04-04
CPC Classifications: H03M

Claim:
1. A digital-to-analog converter (DAC) comprising: a decoder configured to receive a digital input signal; first and second sub-DACs coupled in parallel to said decoder, each of said first and second sub-DACs comprising first and second least significant bit (LSB) banks, and a most significant bit (MSB) bank coupled between said first and second LSB banks; said decoder configured to selectively control the first and second LSB banks, and the MSB bank based upon the digital input signal; and an output network coupled to said first and second sub-DACs and configured to generate an analog output signal related to the digital input signal; said first and second LSBs banks being respectively coupled to first and second reference voltages, the second reference voltage being less than the first reference voltage; said decoder comprising