Patent ID: 9601191
Date: 2017-03-21
CPC Classifications: G11C

Claim:
1. A phase-change memory (PCM) chip comprising a circuit, wherein the circuit comprises: a buffer, the buffer configured to store one or more bits and to output a buffer signal; a finite states machine (FSM), the FSM configured to provide an output control, a first write-region control, and a second write-region control, wherein the first and second write-region controls specify which write-region is scheduled; a first AND gate, the first AND gate configured to receive the output control, the first write-region control, and an inverted buffer signal, wherein the inverted buffer signal is an inversion of the buffer signal output by the buffer; a second AND gate, wherein the second AND gate is configured to receive the buffer signal, the second write-region control, and an inversion of the output control; an OR gate, wherein the OR gate is configured to receive an output signal of the first AND gate and an output signal of the second AND gate; and a switch, the switch configured to provide the buffer signal to a write driver according to an output signal of the OR gate, wherein the write driver writes one or more bits stored in the buffer in the target cache line; wherein the circuit is configured to schedule writing requests in at least two stages, wherein a first stage comprises writing all bits of zero in a target cache line and a second stage comprises writing all bits of one in the target cache line.