Patent ID: 9620186
Date: 2017-04-11
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor storage device comprising: a memory cell array including a plurality of memory cells arranged in matrix, each one of the memory cells comprises a first transistor comprising a channel region formed with an oxide semiconductor; a decoder operationally connected with the plurality of memory cells; and a first circuit operationally connected with the decoder, the first circuit configured to select whether to output an address signal to the decoder, the first circuit comprising a first XOR gate, a second XOR gate, a first AND gate, a first element, a second element, a third element, a fourth element, a first line, a second line, a third line, and a fourth line, wherein: the first line is electrically connected to a first input of the first element and a first input of the first XOR gate; the second line is electrically connected to a first input of the second element and a second input of the first XOR gate; the third line is electrically connected to a first input of the third element and a first input of the second XOR gate; the fourth line is electrically connected to a first input of the fourth element and a second input of the second XOR gate; an output of the first XOR gate is electrically connected to a first input of the first AND gate; an output of the second XOR gate is electrically connected to a second input of the first AND gate; an out put of the first AND gate is electrically connected to a second input of the first element, a second input of the second element, a second input of the third element, and a second input of the fourth element; and in each of the plurality of memory cells, data is held by turning off the first transistor.