Patent ID: 9647119
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first transistor comprising a fin arranged on a substrate, the fin having a first relaxed silicon germanium layer arranged on the substrate and a compressively strained silicon germanium layer arranged on the first relaxed silicon germanium layer; a second transistor comprising a fin arranged on the substrate, the fin having a second relaxed silicon germanium layer arranged on the substrate and a tensile strained silicon germanium layer arranged on the second relaxed silicon germanium layer, the second relaxed silicon germanium layer comprising a germanium content that is different than the first relaxed silicon germanium layer; and a gate arranged on the fin of the first transistor and the fin of the second transistor; wherein the compressively strained silicon germanium layer and the tensile strained silicon germanium layer have a germanium content that is substantially the same.