Patent ID: 9591170
Date: 2017-03-07
CPC Classifications: H04N

Claim:
1. An image processing apparatus comprising: a first image processing unit configured to generate second image data having a pixel number smaller than a pixel number of first image data, wherein the first image processing unit generates a plurality of frames of the second image data corresponding to a plurality of frames of the first image data, and outputs the first and second image data in a first order such that, for each of the frames, the second image data is later than the first image data; a second image processing unit configured to subject the first and second image data to a predetermined process in a second order such that, for each of the frames, the first image data is later than the second image data; a memory having a plurality of storage regions; and a memory control unit configured to control a transferring the image data between the first and second image processing units and the memory, wherein the memory control unit writes, in the first order, in a first storage region of the memory, the first and second image data of a first frame from the first image processing unit, and writes, in the first order, in the first storage region of the memory, the first and second image data of a second frame next to the first frame from the first image processing unit, the memory control unit reads, in the second order, the first and second image data of the first frame from the first storage region, to output them to the second image processing unit, and reads, in the second order, the first and second image data of the second frame from the first storage region, to output them to the second image processing unit, and, after reading out the second image data of the first frame from the memory, the memory control unit writes the first image data of the second frame into an address at which the second image data of the first frame is stored.