Patent ID: 9640267
Date: 2017-05-02
CPC Classifications: G11C,H05K

Claim:
1. A semiconductor device comprising: a memory array including a plurality of twin cells each formed of electrically rewritable, first and second storage devices holding binary data depending on a difference between a threshold voltage of said first storage device and a threshold voltage of said second storage device; and a control circuit that controls erasing twin cell data held in said twin cells, when said control circuit has received a first erase command, said control circuit controlling performing a first pre-write process to allow said first storage device and said second storage device to have their respective threshold voltages both increased, said control circuit thereafter controlling performing an erase process to allow said first storage device and said second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level, whereas when said control circuit has received a second erase command, said control circuit controlling performing a second pre-write process to allow one of said first storage device and said second storage device to have its threshold voltage increased, said control circuit thereafter controlling performing said erase process.