Patent ID: 9735353
Date: 2017-08-15
CPC Classifications: G11C,H01L

Claim:
1. A memory cell comprising: a semiconductor substrate; a first insulating layer covering a surface of the semiconductor substrate; an active layer of semiconductor material covering the first insulating layer; a control gate of a selection transistor, the control gate being formed on the active layer and having a lateral flank; a trench formed through the active layer, the trench being defined on one side by a lateral flank of the active layer and defined on a bottom side by a top side of the first insulating layer; a second insulating layer covering the lateral flank of the control gate; and a variable-resistance element electrically coupled to a first conduction terminal of the selection transistor, wherein the variable-resistance element is at least partially in the trench and contacting the lateral flank of the active layer in the trench.