Patent ID: 9748238
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a device isolation layer on a substrate and defining an active pattern, the active pattern protruding upwardly from the substrate, extending in a first direction, and comprising an active fin, wherein the active fin is an upper portion of the active pattern, which is exposed by the device isolation layer; a first gate structure and a second gate structure crossing the active pattern, extending in a second direction intersecting the first direction and spaced apart from each other in the first direction; a dummy gate structure between the first gate structure and the second gate structure, the dummy gate structure extending in the second direction; a first source/drain region on the active pattern between the first gate structure and the dummy gate structure; a second source/drain region on the active pattern between the second gate structure and the dummy gate structure; a connection contact on the dummy gate structure, the connection contact extending in the first direction to connect the first source/drain region to the second source/drain region; and a common conductive line on the connection contact, the common conductive line configured to apply a voltage to the first and second source/drain regions through the connection contact.