Patent ID: 9728597
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor structure, comprising: forming a bottom electrode layer over a substrate by a physical vapor deposition process; forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process; forming a dielectric layer over the first passivation layer by a second atomic layer deposition process; forming a second passivation layer over the dielectric layer by a third atomic layer deposition process; forming a top electrode layer over the second passivation layer; patterning the top electrode layer and the second passivation layer to have a first width; and patterning the dielectric layer, the first passivation layer, and the bottom electrode layer to have a second width, wherein the second width is greater than the first width, wherein the bottom electrode layer and the first passivation layer are made of a same material, but the bottom electrode layer is a crystalline layer and the first passivation layer is an amorphous layer.