Patent ID: 9698256
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: a cell region comprising an array of device cells arranged on a device substrate, the cell region comprising a plurality of doped columns separated from one another by a gate electrode matrix and extended from an upper surface of the device substrate downwardly to a first depth within the device substrate; and a termination region disposed at an outer periphery of the cell region, the termination region comprising a plurality of termination rings concentrically surrounding the cell region; wherein the plurality of termination rings include a conformal layer of doped material which extends downwardly to different depths beneath the upper surface of the device substrate, and wherein a first distance separating a pair of neighboring termination rings near a center of the termination region nearest the cell region is greater than a second distance separating a second pair of neighboring termination rings near an outer periphery of the termination region; wherein the first depth of the plurality of doped columns is substantially equal to a depth of an innermost termination ring of the plurality of termination rings nearest the cell region; wherein a first dielectric layer extends over the upper surface of the device substrate and extends downwardly along inner sidewalls and lower surfaces of the plurality of doped columns and the conformal layer of doped material to fill a recess in upper surfaces of the doped columns and the conformal layer; wherein a second dielectric layer is disposed on the first dielectric layer, wherein the second dielectric layer has a bottom surface in direct contact with an upper surface of the plurality of doped columns in the cell region.