Patent ID: 9570547
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A lateral DMOS transistor, comprising: a substrate; first and second isolation regions formed above the substrate; a source region formed above the substrate between the first and second isolation regions; a first drain region formed above the substrate between the first isolation region and the source region; a first gate structure, formed over the substrate between the source region and the first drain region and adjacent to the source region; a first epitaxy layer formed over the substrate between the isolation regions; a first buried layer formed above the first epitaxy layer and extending laterally between, but not under, the source region and the first drain region; a second epitaxy layer formed over the first epitaxy layer and the first buried layer between the isolation regions; and a first surface layer formed over the second epitaxy layer between the first gate structure and the first drain region, wherein the substrate, first epitaxy layer, first buried layer, second epitaxy layer, and the first surface layer are alternately doped.