Patent ID: 9735233
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. An electronic device comprising: a substrate; an energy barrier forming layer on the substrate; an upper channel material layer on the substrate, the upper channel material layer including a two-dimensional (2D) material, the upper channel material layer at least partially covering an upper surface of the energy barrier forming layer; a lower channel material layer on the substrate, the lower channel material layer isolated, by the energy barrier forming layer, from contact with the upper channel material layer, the lower channel material layer at least partially overlapping the upper channel material layer, the lower channel material layer at least partially located between the energy barrier forming layer and the substrate; a gate insulating layer on the substrate, the gate insulating layer covering the upper channel material layer, the energy barrier forming layer, and the lower channel material layer; and a gate electrode that covers at least a portion of the gate insulating layer, the upper channel material layer, the energy barrier forming layer, and the lower channel material layer, the gate electrode isolated, by the gate insulating layer, from contact with each of the upper channel material layer, the energy barrier forming layer, and the lower channel material layer, the gate electrode extending continuously over an entirety of a top surface of the energy barrier forming layer and at least partially over at least one outer side surface of the energy barrier forming layer, such that the gate electrode include a side gate electrode portion that at least partially overlaps the at least one outer side surface of the energy barrier forming layer; a drain electrode on the substrate, the drain electrode contacting the lower channel material layer; and a source electrode on the upper channel material layer.