Patent ID: 9634121
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method of manufacturing a display panel having a plurality of lightly doped drain thin film transistors arranged as a matrix, the method comprising: providing a substrate; forming a semiconductor pattern with a predetermined shape on the substrate; forming a dielectric layer covering the semiconductor pattern on the substrate; forming a metal layer on the dielectric layer; forming a photoresist patterns smaller than the semiconductor pattern on the metal layer right above the semiconductor pattern; etching the metal layer to form a gate electrode smaller than the photoresist pattern; doping high concentration ions by using the photoresist pattern as a mask to form a pair of highly doped regions on the semiconductor pattern not covered by the photoresist pattern; removing the photoresist pattern; and doping low concentration ions by using the gate electrode as a mask to form a pair of lightly doped regions between the highly doped regions and a part of the semiconductor pattern covered by the gate electrode; wherein a center of the gate electrode is aligned with a center of the photoresist pattern, and two opposite edges of the gate electrode is concaved inwards a preset horizontal distance relative to two opposite edges of the photoresist pattern.