Patent ID: 9633704
Date: 2017-04-25
CPC Classifications: G11C

Claim:
1. A read method of a memory device, comprising: pre-charging upper bit lines and lower bit lines by turning on bit line sharing transistors; turning off the bit line sharing transistors after pre-charging the upper bit lines and the lower bit lines; applying a read voltage to first and second word lines selected according to an address; performing a first sensing operation to sense data of first memory cells connected with the first word lines through upper sense latches connected with the upper word lines; performing a second sensing operation to sense data of second memory cells connected with second word lines through lower sense latches connected with the lower word lines; transferring data stored at the upper sense latches and data stored at the lower sense latches to data latches; and outputting data stored at the data latches, wherein the bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal, and wherein the first and second sensing operations are both performed by a page data unit.