Patent ID: 9691756
Date: 2017-06-27
CPC Classifications: G11C,H01L

Claim:
1. A nonvolatile memory device comprising: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a gate stacked on the gate insulating layer; a source region formed in the semiconductor substrate the source region includes a first source region including a region intersecting the gate insulating layer and a second source region corresponding to the remaining source region other than the first source region, the first source region is lightly doped with a dopant, and the second source region is heavily doped with a dopant; a drain region formed in the semiconductor substrate, the drain region includes a first drain region including a region intersecting the gate insulating layer and a second drain region corresponding to the remaining drain region other than the first drain region, the first drain region is lightly doped with a dopant, and the second drain region is heavily doped with a dopant; and an insulating isolation layer is formed in a region including a channel region between the source and drain regions in the semiconductor substrate, wherein the gate has a lower portion including a metal layer, the gate insulating layer includes an insulating layer or a variable resistor, a portion of the gate insulating layer or the variable resistor between the gate and the first source region serves as a first storage layer, and a portion of the gate insulating layer or the variable resistor between the gate and the first drain region serves as a second storage layer, wherein, when the first storage layer is in an electrical conduction state, the gate and the first source region form a first diode, or when the second storage layer is in an electrical conduction state, the gate and the first drain region form a second diode.