Patent ID: 9584305
Date: 2017-02-28
CPC Classifications: H04L

Claim:
1. A source-synchronization interface circuit, comprising: a sender synchronous-to-asynchronous protocol converter that, during operation, receives sender data and a sender clock having a first period and a sender phase, wherein the sender synchronous-to-asynchronous protocol converter has regenerative gain to resolve metastability during phase synchronization of the sender clock and a receiver clock; an asynchronous first-in, first-out (FIFO) buffer electrically coupled to the sender synchronous-to-asynchronous protocol converter, wherein the asynchronous FIFO buffer includes multiple stages and, during operation, conveys data from the sender synchronous-to-asynchronous protocol converter to a receiver synchronous-to-asynchronous protocol converter; the receiver synchronous-to-asynchronous protocol converter, electrically coupled to the asynchronous FIFO buffer, which, during operation, receives a receiver clock having a second period, which is one of the first period and a rational multiple of the first period, and a receiver phase, wherein the receiver synchronous-to-asynchronous protocol converter has regenerative gain to resolve metastability during the phase synchronization, and wherein the asynchronous FIFO buffer conveys information corresponding to the sender phase to the receiver synchronous-to-asynchronous protocol converter and information corresponding to the receiver phase to the sender synchronous-to-asynchronous protocol converter; and wherein the data is transferred from the sender to the source-synchronization interface circuit, and from the source-synchronization interface circuit to the receiver with a data-transfer period that is the same as one of the first period and the rational multiple of the first period; and control logic, electrically coupled to the asynchronous FIFO buffer, which, during operation, initializes the source-synchronization interface circuit by: