Patent ID: 9608643
Date: 2017-03-28
CPC Classifications: H03K,H03L

Claim:
1. A delay lock loop, comprising: a delay unit comprising a delay factor and delaying a first clock signal to generate a second clock signal according to the delay factor; an elimination unit delaying a third clock signal to generate a fourth clock signal; a phase detection unit coupled to the delay unit and the elimination unit and generating an indication signal according to a phase difference between the second and fourth clock signals; and a control unit coupled to the phase detection unit and adjusting the delay factor according to the indication signal, wherein the control unit determines a duration of the indication signal being at a first level, when the duration of the indication signal being at the first level does not arrive at a pre-determined value and the indication signal is at a second level, the control unit increases the delay factor, and when the duration of the indication signal being at the first level arrives at the pre-determined value and the indication signal is at the second level, the control unit reduces the delay factor.