Patent ID: 9639652
Date: 2017-05-02
CPC Classifications: G01R,G06F

Claim:
1. A method for simulating an integrated circuit (IC) design in a circuit design simulator, the method comprising: receiving data representing a circuit design, said data configured for input to and processing by said circuit design simulator, said data specifying an uplift switch value for an integrated circuit quiescent current (IDDQ) prediction macro, said switch value corresponding to one of: said device, cell, circuit, or IC chip level of design being simulated; when simulating said circuit, using said IDDQ prediction macro to model a leakage current prediction for said circuit design, said leakage current prediction determinable at a device, cell, circuit, or IC chip level of said design, automatically calculating one or more uplift factors representing device variation effects for use in said leakage current prediction model according to the switch value, an uplift factor being a function of a statistical quantity σ wherein for a specified uplift factor switch value, σ wherein a processor device performs at least one of said receiving, using, modeling and uplift factor calculating.