Patent ID: 9684758
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A method of generating asserted sensitivities comprising: grouping, by one or more processors, a plurality of timing arcs of a plurality of tested circuits into a plurality of equivalence classes such that a given equivalence class is associated with one or more characteristics of one or both of the plurality of tested circuits and the plurality of timing arcs that are included in that given equivalence class, wherein each timing arc includes one or more delay tables; generating, by the one or more processors, for at least one equivalence class of the plurality of equivalence classes, an average sensitivity to an operational condition by performing a weighted average on respective sensitivities of timing arcs to the operational condition; matching, by the one or more processors, an electronic circuit to the at least one equivalence class based, at least in part, on a characteristic of the electronic circuit that matches a characteristic associated with the at least one equivalence class; and determining, by the one or more processors, a sensitivity of the electronic circuit to the operational condition based, at least in part, on i) a match between the characteristic of the electronic circuit and the characteristic that is associated with the at least one equivalence class and ii) the average sensitivity.