Patent ID: 9659847
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A semiconductor die comprising at least one active power device and at least one terminal structure; the at least one terminal structure comprising: a fundamental signal layer arranged to be electrically coupled between the at least one active power device and an external contact of an integrated circuit package; a conductive sub-structure extending in parallel with the fundamental signal layer, and located such that, when mounted within an integrated circuit device, the conductive sub-structure lies between the fundamental signal layer and a reference voltage plane, wherein the conductive sub-structure comprises a plurality of metallic strips extending in parallel with the fundamental signal layer, and located such that when mounted within an integrated circuit device the metallic strips lie in a plane between the fundamental signal layer and a reference voltage plane; and a plurality of interconnecting elements extending between the fundamental signal layer and the conductive sub-structure, and electrically coupling the fundamental signal layer to the conductive sub-structure, wherein the plurality of interconnecting elements comprise a first interconnecting element extending between a first lateral end region of the fundamental signal layer and the conductive sub-structure; and a second interconnecting element extending between a second lateral end region of the fundamental signal layer and the conductive sub-structure such that the first and second interconnecting elements are laterally spaced with respect to a direction of travel of a fundamental signal for the at least one active power device.