Patent ID: 9620614
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor power device in a semiconductor substrate comprising: implanting and forming multiple rows of horizontal slices of continuous layers of alternate P-type and N-type doped layers extending continuously and horizontally over an entire length of the semiconductor substrate by forming each of die continuous layers having a doping concentration and layer thickness to achieve a charge balance and a punch through in said alternated P-type and N-type doped layers during a conduction mode for conducting a current in a vertical direction perpendicular to and cross over the horizontal slices of the alternated P-doped and N-doped layers; forming a gate above and overlaying the alternated P-type and N-type doped layers; and forming a top electrode on a top surface of the semiconductor substrate and forming a bottom electrode on a bottom surface of the semiconductor substrate wherein the gate controls the current conducted in the vertical direction.