Patent ID: 9716103
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a stacked body including an insulating film and an electrode film alternately stacked; an insulating member provided in the stacked body, the insulating member extending in a stacking direction of the stacked body, and in a first direction crossing the stacking direction, the insulating member having a first maximum portion, the first maximum portion having a maximum width of the insulating member along a second direction crossing the stacking direction and the first direction, the first maximum portion being located between a top end portion of the insulating member and a bottom end portion of the insulating member in the stacking direction, the maximum width being greater than a width of the top end portion and a width of the bottom end portion; and a semiconductor pillar provided in the stacked body and extending in the stacking direction, the semiconductor pillar having a second maximum portion, the second maximum portion having a maximum diameter of the semiconductor pillar along a plane parallel with the first direction and the second direction, the first maximum portion and the second maximum portion being provided in different positions in the stacking direction.