Patent ID: 9543427
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; an electrode in contact with the impurity region; and a wiring positioned on the interlayer insulating layer and electrically connected to the electrode, wherein a part of the interlayer insulating layer is positioned between the gate electrode and the electrode, the gate electrode has a recess positioned at a corner in contact with the second surface of the gate electrode, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer, a cavity surrounded by the gate electrode and the interlayer insulating layer including the part of the interlayer insulating layer is positioned in a region including at least a part of the recess, a surface of the gate electrode defining the recess directly borders the cavity, and in the cross section of the gate electrode, a distance between an edge of the cavity in contact with the part of the interlayer insulating layer and a virtual center axis of the gate electrode is larger than or equal to a distance between an edge of the gate electrode at the first surface of the gate electrode and the virtual center axis of the gate electrode.