Patent ID: 9542519
Date: 2017-01-10
CPC Classifications: G06F

Claim:
1. A design method comprising: generating, by a processor, second design information by setting a first timing condition for a plurality of registers included in first design information of a semiconductor integrated circuit and performing first logic synthesis; generating, by the processor, third design information by setting a second timing condition for the plurality of registers and performing second logic synthesis, wherein the second timing condition has a smaller timing margin than the first timing condition; calculating, by the processor, an area change rate, due to a difference between the timing conditions, of each of a plurality of logic cones each including one of the plurality of registers at an end point, on the basis of the second design information and the third design information; categorizing, by the processor, the plurality of registers into a first group and a second group on the basis of magnitudes of the calculated area change rates, wherein the area change rates of the second group are smaller than the area change rates of the first group; and executing, by the processor, third logic synthesis with the second timing condition being set for first registers of the first group and the first timing condition being set for second registers of the second group.