Patent ID: 9569570
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A configurable delay cell, comprising: a complementary metal-oxide semiconductor (CMOS) inverter having an input terminal for receiving an input signal and an output terminal for generating an inverted input signal; a first transistor having a first diffusion terminal connected to the output terminal of the CMOS inverter for receiving the inverted input signal, a gate terminal for receiving a first signal, and a second diffusion terminal for outputting a first intermediate signal; a second transistor having a first diffusion terminal for outputting a second intermediate signal, a second diffusion terminal connected to the output terminal of the CMOS inverter for receiving the inverted input signal, and a gate terminal for receiving a second signal; a third transistor having a first diffusion terminal, a second diffusion terminal for receiving a first supply voltage, and a gate terminal connected to the second diffusion terminal of the first transistor for receiving the first intermediate signal; and a fourth transistor having a first diffusion terminal connected to the first diffusion terminal of the third transistor for generating an output signal, a second diffusion terminal for receiving a second supply voltage, and a gate terminal connected to the first diffusion terminal of the second transistor for receiving the second intermediate signal, and wherein a connection between the output terminal of the CMOS inverter and the second diffusion terminal of the first transistor, a connection between the output terminal of the CMOS inverter and the first diffusion terminal of the second transistor, connecting the second and first signals to an enable signal and an inverted enable signal, respectively, and a connection between the second diffusion terminal of the first transistor and the first diffusion terminal of the second transistor are configurable for achieving first, second, third, fourth, and fifth delay values.