Patent ID: 9548128
Date: 2017-01-17
CPC Classifications: G11C,H03M

Claim:
1. A device comprising: a circuit configured to: receive read data from a non-volatile solid state memory; determine a log likelihood ratio (LLR) based on the read data determine a data value based on the LLR, determine if decoding was successful, and output data when the decoding was successful; calculate means and variances of voltage distributions of the non-volatile solid state memory; provide the means and variances to an LLR generation circuit to update a LLR lookup table that maps read patterns in the read data to LLRs; implement a retry read operation when the decoding was not successful, the retry read operation includes adjusting a read voltage of a non-volatile solid state memory based on the means and variances of the voltage distributions of the non-volatile solid state memory; and perform a read, utilizing the read voltage, of a memory cell of the non-volatile solid state memory to generate retry read data.