Patent ID: 9748207
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. An electronic circuit structure comprising: a first die having a first active layer and a first interconnect layer on the first active layer; a second die having a second active layer and being mounted onto a surface of the first die; and an isolation capacitor disposed between the first and second dies and through which the first and second active layers communicate; wherein: the isolation capacitor includes a first electrically conductive plate in a topmost conductive layer of the first interconnect layer; the second die further has a second interconnect layer on the second active layer, including a second electrically conductive plate in a topmost conductive layer of the second interconnect layer; and the first and second dies are bonded by an electrically conductive material contacting the first electrically conductive plate and the second electrically conductive plate.