Patent ID: 9553819
Date: 2017-01-24
CPC Classifications: H04L

Claim:
1. A computer-implemented system including a processor executing instructions stored in a storage medium to support automatic timing adjustment of metadata paths in a network switch, comprising: a path identification engine running on a host and configured to identify a plurality of metadata paths in the network switch, wherein each of the metadata paths carries a piece of metadata of the incoming packet from one component in the network switch to another component in the network switch; a constraint generation engine running on a host and configured to generate a plurality of timing constraints for each of the metadata paths in the network switch, wherein the timing constraints need to be met in order for the network switch to function properly; a path timing optimization engine running on a host and configured to: calculate current path delays of each of the identified metadata paths, wherein the path delay is the time to carry the piece of metadata from one component to another via the metadata path; determine optimal timing values of each of the metadata paths to meet the timing constraints; compare the optimal timing values of the metadata paths to the current timing delays of the paths to identify one or more metadata paths which current delay values do not meet the timing constraints; adjust the delays of the identified one or more metadata paths in the network switch to meet the timing constraints at minimum cost.