Patent ID: 9721799
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: an encapsulation layer having a first surface, the encapsulation layer comprising a first material; a component within the encapsulation layer, the component having a front surface and comprising a plurality of pads on the front surface; a dielectric layer on the first surface of the encapsulation layer, the dielectric layer comprising a second material, and the dielectric layer defining a plurality of via holes; wherein the first material is different than the second material; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer, and each of the plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of pads; and a first patterned conductive layer embedded at the second surface of the dielectric layer and surrounding the via holes.