Patent ID: 9543236
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. An electronic package assembly comprising: a solder mask layer, the solder mask layer having at least one opening; a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side disposed opposite to the first side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, wherein the package interconnect structure is configured to route electrical signals between a die and an electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die; and a die pad configured to receive the die; wherein the plurality of pads includes a first row of pads, wherein the first row of pads is disposed adjacent to the die pad, wherein the plurality of pads includes a second row of pads disposed (i) adjacent to the first row of pads and (ii) parallel to the first row of pads, wherein the first row of pads is disposed closer to the die pad than the second row of pads, and wherein the extended portion of the at least one pad extends in a direction that is not perpendicular to the first row of pads.