Patent ID: 9691748
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method for forming a panel of stacked semiconductor packages, comprising: providing a bottom leadframe (LF) panel including an interconnected plurality of LFs downset each including at least a first die attach area, and a plurality of terminals; attaching a plurality of low side (LS) transistors to said first die attach area; placing a first clip panel including a plurality of first clips downset and interconnected on said bottom LF panel; attaching a dielectric interposer (interposer) on each of said plurality of first clips over said LS transistors; attaching a plurality of high side (HS) transistors on said interposers, and mating a second clip panel including a plurality of second clips to interconnect to said HS transistors including mating together said second clip panel, said first clip panel and said bottom LF panel.