Patent ID: 9652242
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. An apparatus comprising: first and second multiplexers configured to receive, respectively, first and second pluralities of data bits each corresponding to a modified condition code of an instruction, wherein the first and second plurality of data bits are mutually exclusive and the condition code indicates one or more conditions to be checked responsive to execution of the instruction, wherein at least one of the first and second pluralities of data bits is all logic zeros; an execution unit configured to, responsive to execution of the instruction, provide a first plurality of flag bits as selection bits to the first multiplexer and a second plurality of flag bits as selection bits to the second multiplexer, the first and second pluralities of flag bits being mutually exclusive; and a first logic circuit configured to output an indication of whether a condition associated with the condition code is true based on outputs received from the first and second multiplexers.