Patent ID: 9543214
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor layer, the method comprising: forming, in a semiconductor structure including a stressed semiconductor layer, one or more first isolation trenches in a first direction delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in said semiconductor structure, one or more second isolation trenches in a second direction delimiting a second dimension of said at least one transistor, said one or more first and second isolation trenches being at least partially filled with an insulating material having a viscosity; and before or after forming said one or more second isolation trenches, decreasing the viscosity of the insulating material in said one or more first isolation trenches by implanting atoms of a first material into said one or more first isolation trenches, wherein atoms of said first material are not implanted into said one or more second isolation trenches.