Patent ID: 9659912
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A circuit arrangement comprising: a plurality of semiconductor chips arranged one behind another in a series extending in a first lateral direction, wherein each of the semiconductor chips has a semiconductor body, and also a first load terminal and a second load terminal; the first load terminals of all the semiconductor chips are electrically conductively connected to one another; and the second load terminals of all the semiconductor chips are electrically conductively connected to one another; a first load current collecting conductor rack adjacent to the plurality of semiconductor chips and extending in the first lateral direction; at least one electrical connection conductor electrically connecting each of the semiconductor chips in the plurality to the first load current collecting conductor track, wherein the at least one electrical connection conductor that electrically connects each of the semiconductor chips is electrically conductively connected to the first load terminal of each of the semiconductor chips at a first connection location and is electrically conductively connected to the first load current collecting conductor track at a second connection location; and an external terminal of the circuit arrangement, said external terminal being electrically conductively connected to the first load current collecting conductor track; wherein for each section of the first load current collecting conductor track that is between two directly adjacent second connection locations that electrically connect first and second semiconductor chips of the plurality to the first load current collecting conductor track, a total inductance of the section of the first load current collecting conductor track is less than half of an inductance of the electrical connection conductors that electrically connect the second semiconductor chip to first load current collecting conductor track, wherein the second connection location of the first semiconductor chip is closer to the external terminal than the second connection location of the second semiconductor chip.