Patent ID: 9668341
Date: 2017-05-30
CPC Classifications: H01L,H05K

Claim:
1. A wiring substrate, comprising: a core layer having a penetrating hole; a first insulating layer disposed on a first surface of the core layer and having a first opening at a position of the penetrating hole, the first insulating layer containing no filler; a penetrating electrode disposed in the penetrating hole and in the first opening; and a first wiring layer laminated both on the first insulating layer at a first surface thereof facing away from the core layer and on an end face of the penetrating electrode; a second insulating layer disposed on a second surface of the core layer and having a second opening at a position of the penetrating hole; and a second wiring layer laminated on the second insulating layer at a second surface thereof facing away from the core layer, the second wiring layer being electrically connected to the penetrating electrode through the second opening, wherein the first surface of the first insulating layer and the end face of the penetrating electrode are planarized, and wherein the penetrating electrode is disposed in the penetrating hole, in the first opening, and in the second opening, and the first wiring layer has patterns that are more micro-miniaturized than patterns of the second wiring layer.