Patent ID: 9564506
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device comprising: providing a semiconductor substrate comprising a plurality of fins etched in the semiconductor substrate; creating device regions in the semiconductor substrate using shallow trench isolation (STI); filling the device regions with an insulator; planarizing the insulator; recessing the insulator, wherein the insulator has a thickness which is less than a height of the plurality of fins; forming a set of gate structures; depositing a first insulating material between the set of gate structures; selectively etching an active device area; depositing an oxide material over a top surface of the active device area; removing the first insulating material selective to the plurality of fins; forming a set of spacers adjacent to the set of gate structures; growing a doped source and drain region adjacent to the plurality of fins; depositing an etch stop layer over an upper surface of the deposited oxide material; depositing a second insulating material over an upper surface of the deposited etch stop layer; and depositing a metal within a contact opening to form a plurality of contacts.