Patent ID: 9606179
Date: 2017-03-28
CPC Classifications: G01R

Claim:
1. An automatic test pattern generation system, comprising: a controller, configured to receive m scan inputs from a tester, and provide a first control signal; an i-bit serializer-deserializer; a decompressor network, configured to receive the m scan inputs from the tester, the decompressor network comprising first and second parts, the first part of the decompressor network including a first spreading network of XOR logic gates configured to receive the m scan inputs from the tester and output 2 a second spreading network of XOR logic gates receiving an output of the i-bit serializer-deserializer; and a multiplexer stage including at least one multiplexer, the at least one multiplexer having a first multiplexer input configured to receive at least one of the outputs of the first spreading network, a second multiplexer input configured to receive an output from the second spreading network, and a third multiplexer input configured to receive the first control signal, wherein, based on the first control signal, the multiplexer selects one of the first and second multiplexer inputs to output to a plurality of scan channels.