Patent ID: 9741803
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A charge trap memory device comprising: a semiconductor material structure having a vertical channel extending from a first diffusion region formed in a semiconducting material to a second diffusion region formed over the first diffusion region, the vertical channel electrically connecting the first diffusion region to the second diffusion region; a tunnel dielectric layer disposed surrounding at least partially the vertical channel; and a multi-layer charge-trapping region including a first deuterated layer disposed abutting the tunnel dielectric layer, a first nitride layer disposed abutting the first deuterated layer, and a second nitride layer comprising a deuterium-free trap-dense, oxygen-lean nitride disposed abutting the first nitride layer, wherein the second nitride layer comprises a majority of charge traps distributed in the multi-layer charge-trapping region.