Patent ID: 9729849
Date: 2017-08-08
CPC Classifications: H04N

Claim:
1. A three dimensional (3D) video decoder apparatus comprising: circuitry to partition a block of a first picture into two or more sub blocks of the block including a first sub block and a second sub block; circuitry to access a depth map associated with the block; circuitry to access a disparity vector associated with the block, wherein the disparity vector provides disparity compensated prediction by referencing an already decoded second picture having a different view with respect to the first picture; circuitry to selectively determine a calibrated disparity vector for the first sub block based at least in part on the disparity vector associated with the block and the depth map, wherein to selectively determine the calibrated disparity vector, the circuitry determines, using the depth map, a characteristic depth value corresponding to the first sub block, and calibrates the disparity vector associated with the block based on the characteristic depth value to generate the calibrated disparity vector for the first sub block, wherein to calibrate the disparity vector to generate the calibrated disparity vector, the circuitry provides the calibrated disparity vector for the first sub block as a modification of the disparity vector associated with the block based at least in part on a scaling factor and an offset factor, wherein the scaling factor and the offset factor are determined based on the characteristic depth value; and circuitry to perform disparity compensated inter-prediction for the first sub block based on the calibrated disparity vector associated with the first sub block.