Patent ID: 9665528
Date: 2017-05-30
CPC Classifications: G06F

Claim:
1. A bus serializer device for use with a bus system including a first master device, a second master device, a set of controlled device(s) including at least a first controlled device, a set of bus communication line(s) including at least a first communication line with the set of bus communication lines being connected in data communication with each controlled device of the set of controlled device(s), the bus serializer device comprising: a control unit including machine logic; a first communication hardware set; a second communication hardware set; and a bus hang detection module structured and/or programmed to detect a first bus hang condition; wherein: the first communication hardware set is structured, connected, located and/or programmed to provide data communication between the first master device and the set of controlled device(s) through the set of bus communication line(s); the second communication hardware set is structured, connected, located and/or programmed to provide data communication between the second master device and the set of controlled device(s) through the set of bus communication line(s); the machine logic of the control unit further includes a bus recovery module structured and/or programmed to, responsive to detection of the first bus hang condition by the bus hang detection module, recover the device from the first bus hang condition; the machine logic of the control unit is structured and/or programmed to: the first bus hang condition is one of the following: (i) bus hang caused when a master device is set into a reset state while running an I2C write transaction, (ii) bus hang caused when a master device is set into a reset state while running an I2C read transaction, or (iii) bus hang caused when a master device is set into a reset state while setting up an I2C read operation.