Patent ID: 9594928
Date: 2017-03-14
CPC Classifications: G06F,G09C,H04L

Claim:
1. Encryption/authentication circuitry comprising: an encryption portion including: a first number of encryption lanes, each encryption lane including a plurality of encryption stages, and keyspace circuitry including a plurality of key lanes corresponding in number to a predetermined maximum number of channels, each key lane having key storage stages corresponding to said encryption stages, each key storage stage including key memories for said predetermined maximum number of channels, said key storage circuitry further including key channel selection circuitry for each stage to select an encryption key from among said key memories at said key storage stage; and an authentication portion including: a second number of authentication lanes, hash key storage for said predetermined maximum number of channels, partial hash state storage for said predetermined number of channels, hash channel selection circuitry for selecting, in each respective lane, respective hash key data from said hash key storage and respective partial hash state data from said partial hash state storage, said respective hash key data and said respective partial hash state data corresponding to a channel being processed in said respective authentication lane, and authentication circuitry for updating, in each respective authentication lane, said respective partial hash state data, based on said respective hash key data and data in said channel being processed in said respective authentication lane.