Patent ID: 9553599
Date: 2017-01-24
CPC Classifications: H03M

Claim:
1. A successive approximation register (SAR) analog-to-digital converter (ADC) comprising: a switched capacitor digital-to-analog converter (DAC) first array configured to sample an input signal and to convert a sample of the input signal to a digital value represented by a plurality of bits, the first array including a first group of capacitors representing at least some of the plurality of bits; a switched capacitor DAC second array, the second array including a second group of capacitors representing at least some of the plurality of bits, wherein at least one bit of the plurality of bits represented by the second group of capacitors is represented by at least two capacitors, and wherein each of the two capacitors is configured to be selectively connected to a selected one of at least two reference potentials such that the at least one bit of the plurality of bits represented by the second group of capacitors is switchable between at least three states, wherein the at least three states include a positive state, a negative state, and a null state.