Patent ID: 9741733
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A three-dimensional semiconductor memory device comprising: a semiconductor pattern disposed on a semiconductor substrate, wherein the semiconductor pattern comprises an opening, a first impurity region having a first conductivity type and a second impurity region having a second conductivity type that is different from the first conductivity type, and wherein the semiconductor pattern further comprises a body contact impurity region that has the first conductivity type and has an impurity concentration higher than an impurity concentration of the first impurity region; a peripheral transistor disposed between the semiconductor substrate and the semiconductor pattern; a first peripheral interconnection structure disposed between the semiconductor substrate and the semiconductor pattern and electrically connected to the peripheral transistor; memory cell gate conductive patterns disposed on the semiconductor pattern; memory cell vertical structures extending through respective ones of the memory cell gate conductive patterns and being connected to the semiconductor pattern; memory cell bit line contact plugs disposed on respective ones of the memory cell vertical structures; a bit line disposed on the memory cell bit line contact plugs; and a peripheral bit line contact structure being disposed between the bit line and the first peripheral interconnection structure and extending through the opening of the semiconductor pattern.