Patent ID: 9645933
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. An apparatus, comprising: a processor including a plurality of processing cores; a shared cache comprising a plurality of cache lines accessible by each of the plurality of processing cores and being partitioned into a plurality of sub-caches including (i) a plurality of private sub-caches each comprising a number of private cache lines accessible by a single processing core and (ii) a public sub-cache comprising a number of public cache lines accessible by each of the plurality of processing cores, each cache line of the plurality of cache lines includes a coordinate-based counter indicating a status of each corresponding cache line; a plurality of monitoring circuits, each monitoring circuit configured to detect shared cache hit information for each processing core of the plurality of processing cores; and a partitioning logic circuit configured to modify a coordinate value of the coordinate-based counter and adjust the number of public cache lines accessible by each of the plurality of processing cores when a cache line of the plurality of cache lines is hit by a corresponding single processing core by determining, based on a threshold range and the modified coordinate value of the coordinate-based counter, whether to allocate the cache line to the public sub-cache or to one of the private sub-caches accessible by the corresponding single processing core.