Patent ID: 9679982
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a device isolation pattern disposed in a substrate to define an active portion; a pair of gate electrodes disposed in a pair of gate grooves crossing the active portion, respectively, wherein a top surface of a center portion of the active portion between the pair of gate grooves is lower than top surfaces of opposing edge portions of the active portion and wherein top surfaces of the gate electrodes are lower than the top surface of the center portion of the active portion; a gate insulating layer disposed between each of the gate electrodes and an inner surface of each of the gate grooves; gate capping patterns filling the gate grooves on the gate electrodes, respectively; a contact pattern connected to the center portion of the active portion; a wire pattern including a conductive wire extending in a first direction on the contact pattern; and an insulating pattern disposed between the conductive wire and the device isolation pattern, wherein a top surface of the insulating pattern directly contacts the conductive wire, wherein the gate capping patterns comprise portions that extend outside the gate grooves to be connected to each other without an interface therebetween, and the portions of the gate capping patterns comprises a connected extending portion, and wherein a sidewall of the contact pattern is in contact with the gate capping patterns.