Patent ID: 9647671
Date: 2017-05-09
CPC Classifications: H03K,H03L

Claim:
1. A phase frequency detector comprising a reference signal input, a clock signal input, an up signal output, a down signal output, a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop, wherein: each of the first D flip-flop, the second D flip-flop, the third D flip-flop, and the fourth D flip-flop comprises a D input, a clock input, an active-low reset input, and a Q output; the Q output of the first D flip-flop is connected to the up signal output; the Q output of the second D flip-flop is connected to the down signal output; the reference signal input is connected to the clock input of the third D flip-flop; the clock signal input is connected to the clock input of the fourth D flip-flop; the Q output of the third D flip-flop is connected to the clock input of the first D flip-flop and the active-low reset input of the second D flip-flop; the Q output of the fourth D flip-flop is connected to the clock input of the second D flip-flop and the active-low reset input of the first D flip-flop; the third D flip-flop outputs a reference pulse on the Q output of the third D flip-flop in response to a reference signal provided by the reference signal input; and the fourth D flip-flop outputs a clock pulse on the Q output of the fourth D flip-flop in response to a clock signal provided by the clock signal input.