Patent ID: 9697324
Date: 2017-07-04
CPC Classifications: G01R,G06F

Claim:
1. An emulator used to functionally verify a digital electronic circuit design, the emulator comprising: a first domain, the first domain comprising integrated circuits that emulate at least a first digital electronic circuit design; a second domain, the second domain comprising integrated circuits that emulate a second digital electronic circuit design; a retiming FPGA coupled to the first domain and the second domain, the retiming FPGA controlling timing of signals communicated between the first domain and a first target system and controlling timing of signals communicated between the second domain and a second target system, the first target system being a system in which the first digital electronic circuit design being verified in the emulator will be installed once manufactured, the second target system being a system in which the second digital electronic circuit design being verified in the emulator will be installed once manufactured, the retiming FPGA generates test signals that test a first set of target connections, wherein the first set of target connections connect the emulator to the first target system; a multiplexer that selects the first set of target connections to receive the test signals; a target system FPGA, external to the emulator, that receives the test signals from the multiplexer over the first set of target connections, and sends the test signals over the first set of target connections to the first target system, wherein the target system FPGA determines failure of any of the first set of target connections and generates a failure indication; and a board manager device, external to the emulator, in communication with the target system FPGA and the emulation system, the board manager device receives the failure indication from the target system FPGA and reports said failure indication, wherein the emulator continues to emulate the second digital electronic circuit design of the second domain while testing the first set of target connections.