Patent ID: 9542154
Date: 2017-01-10
CPC Classifications: G06F

Claim:
1. A method comprising: multiplying a first mantissa term of a first floating point number with a second mantissa term of a second floating point number to obtain a product; performing, using an adder circuit, a first logical operation on a third mantissa term of a third floating point number and a first bit mask to obtain a first bit value, wherein the adder circuit supports an argument size of less than a pre-defined value proportional to a size of one of: the first mantissa term, the second mantissa term, or the third mantissa term; performing, using a logical AND circuit, a second logical operation on the third mantissa term and an inverse of the first bit mask to produce a second bit value; performing, using a logical OR circuit, a third logical operation on a sum of the product with the third mantissa term and one of: the first bit value incremented by one or the second bit value to generate a result; and responsive to detecting an underflow, denormalizing the result using a second bit mask.