Patent ID: 9721510
Date: 2017-08-01
CPC Classifications: G09G,G11C

Claim:
1. A gate driving unit including an input circuit, a pull-up circuit, a reset circuit, and an output circuit, the input circuit being directly connected to both the pull-up circuit and the reset circuit, the pull-up circuit and the reset circuit being directly connected to the output circuit, respectively, wherein the input circuit, which comprises an input terminal and is used for receiving a pull-up driving signal and inputting the pull-up driving signal to the pull-up circuit; the pull-up circuit is used for receiving the pull-up driving signal and outputting a high level signal to an input terminal of the output circuit; the reset circuit, which comprises an input terminal and is used for receiving a reset driving signal and resetting the high level signal at the input terminal of the output circuit to a low level signal; and the output circuit is used for receiving an output signal from the pull-up circuit and an output signal from the reset circuit, and outputting a gate driving signal under control of a clock signal; wherein, the pull-up driving signals received by the input terminal of the input circuit include the gate driving signals for pixel units of row n−2 and row n+4, the reset driving signals received by the input terminal of the reset circuit include the gate driving signals for pixel units of row n+2 and row n+8, and the gate driving signals output from the output circuit include the gate driving signals for pixel units of row n and row n+6, where n is a positive integer and n is equal to or greater than 3.