Patent ID: 9575665
Date: 2017-02-21
CPC Classifications: G06F,G06T,G09G,H04N

Claim:
1. A memory system comprising: a memory that is shared by a plurality of devices; a first memory controller; a second memory controller; a memory request arbiter coupled to the memory, wherein the memory request arbiter is configured to perform real time scheduling of memory requests from different devices having different priorities and provides access to the memory by the plurality of devices, the memory request arbiter comprising a first arbiter coupled to the first memory controller and a second arbiter coupled to the second memory controller; and a memory select circuit configured to: a circuit component associated with one or more of the plurality of devices and coupled between the associated devices and the memory request arbiter, wherein the circuit component is configured to enforce a minimum interval between subsequent accesses by the associated device to the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory.