Patent ID: 9748308
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of fabricating an image system, the method comprising: forming a first wafer that includes a first semiconductor substrate and a first interconnect layer, wherein a pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate, and wherein an insulating material in the first insulation-filled trench is planarized prior to forming the first interconnect layer, wherein the first insulation-filled trench is formed in the peripheral circuit region prior to a Back-End-of-Line (“BEOL”) process on the first wafer and subsequent to a Front-End-of-Line (“FEOL”) process on the first wafer; forming a second wafer that includes a second semiconductor substrate and a second interconnect layer, wherein a second insulation-filled trench is formed in the second semiconductor substrate; bonding the first wafer to the second wafer, wherein the first and second interconnect layers are positioned between the first and second semiconductor layers; bonding a third interconnect layer of a third wafer to the second wafer; forming at least one deep via cavity through the first and second interconnect layers and through the first and second insulation-filled trenches, wherein the at least one deep via cavity extends to a conductor within the third interconnect layer; and filling the at least one deep via cavity with a conductive material to form a deep via.