Patent ID: 9552993
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method comprising: depositing a first layer on a first semiconductor epi layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer, wherein the first layer comprises a first metal and a second metal, and wherein the trench structure comprises an isolating layer along a first wall, a bottom surface, and an opposite second wall, and a conductive layer formed in the trench between the first wall and the second wall, wherein the first layer overlies the conductive layer and the isolating layer; depositing a second layer comprising a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing; subjecting the first semiconductor epi layer to at least a first annealing act to provide a first structure wherein the first layer reacts with the first semiconductor epi layer and the conductive layer to form a silicide; and stripping at least a portion of the first structure to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act, wherein an opening is thereby formed to the isolating layer at the first and second wall of the trench structure and between the silicide formed overlying the first semiconductor epi layer and silicide formed overlying the conductive layer.