Patent ID: 9570375
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a package substrate; a silicon interposer mounted on the package substrate, the silicon interposer including a plurality of wiring lines extending in a predetermined direction on first and second wiring layers, the wiring lines having first ends located at a first region and second ends located at a second region; a first semiconductor chip mounted on the first region of the silicon interposer so that the first semiconductor chip is electrically connected to the first ends of the plurality of wiring lines; and a second semiconductor chip mounted on the second region of the silicon interposer so that the second semiconductor chip is electrically connected to the second ends of the plurality of wiring lines, wherein the plurality of wiring lines includes at least first, second and third wiring lines provided on the first wiring layer of the silicon interposer and a fourth wiring line provided on the second wiring layer of the silicon interposer, the third wiring line is arranged between the first and second wiring lines on the first wiring layer, the fourth wiring line is overlapped with the third wiring line, each of the first, second and fourth wiring lines conveys a power supply potential to the first and second semiconductor chips, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.