Patent ID: 9716164
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor device, comprising: epitaxially growing a III-V base layer over a surface of a first substrate in a first deposition chamber, the first substrate comprising metallic molybdenum or a metallic molybdenum alloy, the first substrate exhibiting a first average CTE, the III-V base layer comprising a III-V semiconductor material exhibiting a second average CTE within about 10% or less of the first average CTE; transferring the III-V base layer from the surface of the first substrate to a surface of a second substrate; after transferring the III-V base layer to the second substrate, epitaxially growing a first III-V device layer and on an exposed surface of the III-V base layer in a second deposition chamber separate from the first deposition chamber, and epitaxially growing a second III-V device layer on the first III-V device layer in the second deposition chamber while the III-V base layer is disposed on the second substrate, the first III-V device layer having first material composition, the second III-V device layer having a second material composition differing from the first material composition so as to define an electron channel of at least one transistor proximate a heterojunction between the first III-V device layer and the second III-V device layer; providing a first source contact and a second source contact of the at least one transistor in electrical contact with the second III-V device layer and in electrical communication with the electron channel; providing a gate structure of the at least one transistor proximate the electron channel between the first source contact and the second source contact; temporarily bonding a carrier substrate over the first source contact, the second source contact, and the gate structure; removing second substrate from the III-V base layer and exposing a surface of the III-V base layer; providing a layer of conductive material over at least a portion of the exposed surface of the III-V base layer, the layer of conductive material defining a drain contact of the at least one transistor; and providing a dielectric material over the drain contact on a side thereof opposite the III-V base layer; wherein the at least one transistor comprises a vertical high electron mobility transistor.