Patent ID: 9678158
Date: 2017-06-13
CPC Classifications: G01R

Claim:
1. An apparatus for testing a package-on-package semiconductor device, comprising: a top cover; a lower base arranged under the top cover, the top cover and the lower base forming an internal accommodation space for receiving an upper chip; a heat dissipation module including a heat sink, which is arranged in the internal accommodation space and attached to an upper surface of the upper chip; a plurality of probes arranged in the lower base for electrically connecting the upper chip with a lower chip; and a suction nozzle; wherein the heat dissipation module further includes a heat conduction block, the lower base includes a hollow portion, and the heat conduction block is arranged in the hollow portion between the upper chip and the lower chip; and wherein the heat conduction block includes a bottom recess and a negative pressure passage, the suction nozzle is provided in the bottom recess, and the negative pressure passage is communicated with the suction nozzle and coupled to a negative pressure source.