Patent ID: 9666509
Date: 2017-05-30
CPC Classifications: H01L,H03K

Claim:
1. A semiconductor device in which a first chip having a function of lowering an input voltage and a second chip having a function of performing signal processing on an output signal of the first chip are mounted on a die pad, wire connections are made between a part of chip electrodes of the first chip and the second chip and between an other part of the chip electrodes of the first chip and the second chip and external lead terminals, and a sealing resin is provided to seal, wherein the lead terminals constitute a first lead row and a second lead row which are opposite to each other with the die pad interposed in between, each of the first lead row and the second lead row having plural lead terminals, wherein the lead terminals of the first lead row are connected to a part of the chip electrodes of the first chip, an other part of the chip electrodes of the first chip are connected to a part of the chip electrodes of the second chip or a part of the lead terminals of the second lead row, and an other part of the chip electrodes of the second chip are connected to an other part of the lead terminals of the second lead row, wherein a distance between the lead terminals of the first lead row is set longer than a distance between the lead terminals of the second lead row to thereby allow the lead terminals of the first lead row withstand a higher applied voltage than the lead terminals of the second lead row, and wherein the sealing resin fills at least between the lead terminals of the first lead row.