Patent ID: 9685483
Date: 2017-06-20
CPC Classifications: G11C,H01L

Claim:
1. A method of fabricating a non-volatile memory device, comprising: forming a first transistor and a second transistor in a substrate; forming conductive interconnects as a backend-of-line (BEoL) process overlying the substrate, which further comprises: forming a first of the conductive interconnects having a first end thereof in electrical contact with a first gate of the first transistor; forming a second of the conductive interconnects having a first end thereof in electrical contact with a second gate of the second transistor; forming a volatile, resistive-switching selection device in electrical contact with a second end of the first of the conductive interconnects; forming a contact in electrical contact with a second end of the second of the conductive interconnects; and forming a metal layer overlying and in electrical contact with both the volatile selection device and the contact.