Patent ID: 9741764
Date: 2017-08-22
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a substrate; a plurality of first conductive lines on the substrate, the plurality of first conductive lines extending in a first direction parallel to a top surface of the substrate and being spaced apart from each other in a second direction crossing the first direction; a plurality of second conductive lines over the plurality of first conductive lines, the plurality of second conductive lines extending in the second direction and being spaced apart from each other in the first direction; a plurality of third conductive lines over the plurality of second conductive lines, the plurality of third conductive lines extending in the first direction and being spaced apart from each other in the second direction; a plurality of first memory cells at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines, each of the plurality of first memory cells including a first selection element layer and a first variable resistance layer; and a plurality of second memory cells at respective intersections of the plurality of second conductive lines and the plurality of third conductive lines, each of the plurality of second memory cells including a second selection element layer and a second variable resistance layer, wherein a first height of the first selection element layer in a third direction perpendicular to the first and second directions is different from a second height of the second selection element layer in the third direction, and wherein the first and second variable resistance layers are made of the same material, and the first and second selection element layers are made of the same material.