Patent ID: 9716097
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A flash memory device comprising: first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate; a common S/D region arranged laterally between the first and second individual S/D regions, and being separated from the first individual S/D region by a first channel region and being separated from the second individual S/D region by a second channel region; an erase gate arranged over the common S/D; a floating gate disposed over the first channel region and to a first side of the erase gate, and a control gate disposed over the floating gate; a wordline disposed over the first channel region and spaced apart from the erase gate by the floating gate and the control gate, wherein an upper surface of the wordline is a concave surface; and a spacer arranged along an outer sidewall of the wordline, the spacer being separated from the control gate by the wordline and having a spacer tip at a first height, wherein the first height is greater than a second height which corresponds to a bottom region of the concave surface.