Patent ID: 9564372
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method for fabricating a dual silicide device, comprising: growing source and drain regions adjacent to a gate structure for an N-type device; forming a protection layer over the gate structure and the source and drain regions of the N-type device; growing source and drain regions adjacent to a gate structure for a P-type device; conformally depositing a first dielectric layer on the gate structure for the N-type device and the gate structure for P-type device; removing the first dielectric layer to expose the source and drain regions adjacent to the gate structure for the P-type device; siliciding exposed source and drain regions adjacent to the gate structure for the P-type device to form a silicided liner for the P-type device; conformally depositing a second dielectric layer on the gate structure for the N-type device and the gate structure for P-type device; forming a dielectric fill over the second dielectric layer; opening contact holes in the dielectric fill and through the second dielectric layer to expose the silicided liner for the P-type device and expose the protection layer for the N-type device; exposing the source and drain regions adjacent to the gate structure for the N-type device by opening the protection layer; siliciding exposed source and drain regions adjacent to the gate structure for the N-type device to form a silicided liner for the N-type device; and forming contacts in the contact holes down to the silicided liners of the P-type device and the N-type device.