Patent ID: 9691495
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. A memory array, comprising: an upper supply bus developing a supply voltage level relative to a reference voltage level developed on a lower supply bus; a first switched supply bus and a second switched supply bus; a plurality of RAM cells, each having a RAM cell structure with a first power terminal and a second power terminal and configured to operate as a RAM cell when the memory array is in a RAM mode, wherein for each of said plurality of RAM cells, said first power terminal is coupled to one of said first and second switched supply buses and wherein said second power terminal is coupled to the other one of said first and second switched supply buses; a ROM cell comprising said RAM cell structure with first and second power terminals coupled to said upper supply bus, said ROM cell having at least one transistor that is modified so that said ROM cell settles to a predetermined logic state in either one of said RAM mode or a ROM mode, wherein said predetermined logic state is the same logic state in either one of said RAM mode and said ROM mode; a RAM enable circuit that couples said first and second switched supply buses to said upper supply bus in said RAM mode, and that does not couple said first and second switched supply buses to said upper supply bus in said ROM mode; and a ROM enable circuit that enables first and second bit lines of said ROM cell to couple only one of said first and second switched supply buses to said upper supply bus in said ROM mode so that each of said plurality of RAM cells operates as a ROM memory cell by settling to a predetermined logic state when the memory array is in said ROM mode, wherein said predetermined logic state of each of said plurality of RAM cells depends upon said predetermined logic state of said ROM cell.