Patent ID: 9748269
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A transistor pillar logic circuitry comprising a number of semiconductor core columns arrayed in a core column array, comprising a first array direction and a second array direction, wherein each core column includes: A. at least two transistor stacks, each transistor stack comprising: B. a core column fuse arranged vertically in between each of the transistor stacks, the transistor pillar logic circuitry further comprising: i. a source layer substantially conductively encompassing the first vertical through portion, ii. drain layer substantially conductively encompassing the second vertical through portion, iii. a gate layer substantially conductively encompassing the third vertical through portion, iv. a first conductive stripe layer in conductive connection with at least one core column immediately adjacent on one side of each core column fuse, wherein said first conductive stripe layer comprises at least one first conductive stripe that is in conductive connection with at least one of said number of core columns and that is aligned with said first array direction, and v. a second conductive stripe layer in conductive connection with at least one core column immediately adjacent on one other side of each core column fuse, wherein said second conductive stripe layer comprises at least one second conductive stripe that is in conductive connection with said at least one core column and that is aligned with said second array direction such that a core column fuse current is directed across said core column fuses via said first conductive stripe and said second conductive stripe.