Patent ID: 9583511
Date: 2017-02-28
CPC Classifications: G02F,G09G,H01L

Claim:
1. An array substrate comprising: a substrate including an active area and a gate circuit area; a gate connecting line on the substrate in the gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer, the active pattern spaced apart from the gate connecting line; a source connecting line and a pixel pattern sequentially disposed on the active pattern, the source connecting line and the pixel pattern wrapping a top surface and a side surface of the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer, the interlayer insulating layer and the organic pattern spaced apart from the source connecting line; a first passivation layer on the organic pattern, the first passivation layer and the gate insulating layer having a first contact hole exposing the gate connecting line, and the first passivation layer having a second contact hole exposing the pixel pattern; and a conductive pattern on the first passivation layer, the conductive pattern coupled to the gate connecting line through the first contact hole and coupled to the pixel pattern through the second contact hole.