Patent ID: 9748350
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor structure, comprising: forming a trench in a dielectric layer over a substrate; forming a first conductive gate layer on sidewalls and a bottom of the trench; forming a hard mask layer over the first conductive layer; performing a first etching process including etching the hard mask layer to form a blocking structure in a lower portion of the trench, wherein an uppermost surface of the blocking structure is below a top surface of the dielectric layer; etching a portion of the first conductive gate layer not covered by the blocking structure by performing a second etching process to form an etched portion of the first conductive gate layer, wherein a sloped top surface of the etched portion extends from a top surface of the blocking structure upwards to an underlying layer disposed under the first conductive gate layer in the trench; removing the blocking structure; and after removing the blocking structure, forming a conductive material in the trench over the etched portion of the first conductive gate layer.