Patent ID: 9704862
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate including a PMOSFET region and an NMOSFET region; a first gate electrode and a second gate electrode on the PMOSFET region; a third gate electrode and a fourth gate electrode on the NMOSFET region, the first to fourth gate electrodes defining a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes; and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively, a portion of each of the first and second contacts overlap with the gate cut region when viewed from a plan view such that a part of the first contact covers and extends along a sidewall of the first gate electrode in a thickness direction of the first gate electrode in the gate cut region and a part of the second contact covers and extends along a sidewall of the fourth gate electrode in the gate cut region.