Patent ID: 9569573
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A computer-implemented method comprising: identifying an electronic circuit, said electronic circuit comprising a plurality of circuit elements, said electronic circuit being based on a circuit design, said circuit design comprising structural information and logical information; generating a first verification model, said first verification model being for said circuit design, said verification model comprising a plurality of error report signal paths, each of said plurality of error report signal paths being for one of said plurality of circuit elements; identifying a first circuit element output, said first circuit element output being based on said plurality of error report signal paths; setting output for at least one of said first plurality of circuit elements to a fixed value; generating a second circuit element output, said second circuit element output being based on said plurality of error report signal paths, said second circuit element output being based on setting output for at least one of said first plurality of circuit elements to a fixed value; and determining a difference, said difference being between said first circuit element output and said second circuit element output.