Patent ID: 9543296
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A dual direction ESD protection circuit, comprising: a first NPN bipolar junction transistor (BJT) having first base, a first emitter and a first collector; a second NPN bipolar junction transistor (BJT) having second base, a second emitter and a second collector, wherein the first collector and the second collector are connected together; a first diode having a first anode and a first cathode; a second diode having a second anode and a second cathode; first and second resistors, wherein the first and second resistors are in addition to the first base and the second base; a voltage pad and a ground pad; wherein the voltage pad is coupled to the first emitter, the first anode and the first base through the first resistor; wherein the ground pad is coupled to the second emitter, the second anode and the second base through the second resistor; wherein the first cathode and the second cathode are coupled to the first collector and the second collector; wherein the dual direction ESD protection circuit is configured to have bipolar SCR (BSCR) characteristics; wherein the dual direction ESD protection circuit is embodied in a semiconductor structure; a p-type substrate; an n-buried layer (NBL) touching the top surface of the p-type substrate; an n-type epitaxial layer touching the top surface of the NBL layer, wherein the n-type epitaxial layer forms the first and second collectors of the first and second NPN bipolar junction transistors respectively and the first and second cathodes of the first and second diodes respectively; a plurality of selective SiGe epitaxial regions touching the top surface of the n-type epitaxial layer, configured to define the first and second bases of the first and second NPN bipolar junction transistors respectively; a plurality of n-type emitter regions touching the tops of each of the selective SiGe epitaxial regions, thereby forming the first and second emitters of the first and second NPN bipolar junction transistors respectively; a plurality of P+ regions formed in the top surface of the n-type epitaxial layer, configured to define the first and second anodes of the first and second diodes respectively; and wherein the plurality of selective SiGe epitaxial regions are spaced apart from each other and the plurality of P+ regions are spaced apart from each other and each of the plurality of selective SiGe epitaxial regions.