Patent ID: 9646895
Date: 2017-05-09
CPC Classifications: G01R,H01L

Claim:
1. A method of manufacturing a semiconductor package, the method comprising: providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad, a second test pad, a first switching device between the circuit pattern and the first test pad, and a second switching device between the circuit pattern and the second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern; evaluating reliability of the semiconductor chip when the first and second test pads are electrically disconnected from the circuit pattern; after the evaluating reliability of the semiconductor chip, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad; after the evaluating electrical characteristics of the semiconductor chip, electrically disconnecting the first test pad from the circuit pattern using the first switching device; and mounting the semiconductor chip on a substrate electrically connected to the connection pad and electrically disconnected from the first test pad and the second test pad.