Patent ID: 9589888
Date: 2017-03-07
CPC Classifications: G06F,H01L

Claim:
1. A storage device comprising: a flash memory, including a first channel and a second channel, each of the first channel and the second channel including a first way and a second way; and a controller programming a plurality of tasks into the flash memory, each of the plurality of tasks including first bit data and second bit data, wherein the controller does not back up the first bit data when programming the first bit data and the second bit data in a same transaction and backs up the first bit data when programming the first bit data and the second bit data in different transactions, wherein each of the transactions includes the plurality of tasks; wherein the first bit data is less significant bit data and the second bit data is most significant bit data; wherein each of the transactions is determined using a sync signal transmitted from a host; wherein a sequence number is allocated to one of the first bit data and the second bit data programmed into the flash memory in the order of the first way of the first channel, the first way of the second channel, the second way of the first channel, and the second way of the second channel; and wherein if a sequence number of the first bit data is greater than a reference sequence number, the controller is configured to determine that the first bit data and the second bit data are programmed in a same transaction.