Patent ID: 9606803
Date: 2017-03-28
CPC Classifications: G06F

Claim:
1. A digital signal processor comprising: a data register file including a plurality of data registers designed by register number storing data; an instruction memory storing instructions each specifying a data processing operation and at least one data operand by register number; an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand, said instructions including a stream start instruction and a stream operand instruction; at least one operational unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register; a stream engine connected to said instruction decoder operable in response to a stream start instruction to recall from an external memory a stream of an instruction specified plurality of data elements; a stream head register distinct from said plurality of data registers of said data register file, connected to said stream engine and readable by said at least one operational unit as an operand, said stream head register sequentially storing a next recalled data element of said stream of the instruction specified plurality of data elements for use as an operand; and wherein said at least one operational unit is responsive to a stream operand instruction to perform a specified data processing operation determined by the instruction decoder and to receive at least one operand from said stream head register.