Patent ID: 9673832
Date: 2017-06-06
CPC Classifications: H03M

Claim:
1. A successive approximation register analog-to-digital converter, comprising: a successive approximation register logic circuit, repeatedly generating digital control bits in a plurality of cycles of a search scheme of the successive approximation register analog-to-digital converter; a comparator, having a positive input terminal and a negative input terminal, and generating an output signal to be transmitted to the successive approximation register logic circuit for generation of the digital control bits; and a capacitor network, comprising a plurality of positive terminal capacitors coupled to the positive input terminal of the comparator and a plurality of negative terminal capacitors coupled to the negative input terminal of the comparator, wherein the positive terminal capacitors and the negative terminal capacitors sample an analog input of the successive approximation register analog-to-digital converter in a sampling phase prior to the search scheme and are operated based on the digital control bits in the search scheme to reduce a voltage difference between the positive input terminal and the negative input terminal of the comparator, wherein: a digital representation of the analog input is approximated in the search scheme and output by the successive approximation register logic circuit; and the successive approximation register logic circuit combines the output signal of the comparator collected during at least two successive cycles of the plurality of cycles of the search scheme to select between at least three capacitor network switching choices for controlling the voltage difference, wherein when the output signal of the comparator collected during the at least two successive cycles is kept at logic 1, the successive approximation register logic circuit pulls down a voltage level at the positive input terminal of the comparator; when the output signal of the comparator collected during the at least two successive cycles is kept at logic 0, the successive approximation register logic circuit pulls down a voltage level at the negative input terminal of the comparator; and when the output signal of the comparator switches between logic 1 and logic 0 during the at least two successive cycles, the successive approximation register logic circuit keeps the voltage levels at the positive input terminal and the negative input terminal of the comparator.