Patent ID: 9685395
Date: 2017-06-20
CPC Classifications: G03F,H01L

Claim:
1. A semiconductor integrated circuit structure comprising: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a first via having a first width and a first length smaller than the first width in the first dielectric layer; a second via having a second width and a second length greater than the second width in the first dielectric layer, wherein the first width is twice the second width, wherein the first length is equal to the second length, wherein the first via and the second via are spaced apart from each other by a first spacing; a first metal line connected to the first via, wherein the first length is perpendicular to a first center axis of the first metal line along a first longitudinal direction of the first metal line, and wherein the first metal line has a first edge and a second edge opposing the first edge, wherein the first edge and the second edge are parallel to the first center axis; and a second metal line connected to the second via, wherein the second metal line is perpendicular to the first metal line, wherein a first portion of the second metal line and the first edge of the first metal line are disposed on a first side of the first center axis, wherein a second portion of the second metal line and the second edge of the first metal line are disposed on a second side of the first center axis opposing the first side, wherein the first portion of the second metal line extends further away from the first center axis than the first edge of the first metal line, and the second portion of the second metal line extends further away from the first center axis than the second edge of the first metal line.