Patent ID: 9619320
Date: 2017-04-11
CPC Classifications: G06F,G11C,H03M

Claim:
1. A method, implemented by a processor, of error correcting data for writing to a memory, the method comprising: determining whether the memory includes a defective memory cell; receiving a message to be written to the memory; sub-dividing the message into a plurality of sub-messages; generating a first error correction code for the sub-messages, the first error correction code being a first type; generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, wherein a size of each of the plurality of sub-messages corresponds to a number of bits necessary for a second error correction code of the plurality of second error correction codes to mask the defective memory cell; generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes; and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.