Patent ID: 9684597
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. Network interface circuitry, forming a local node, configured to couple a host computer and a network, the network interface circuitry comprising: a processing pipeline configured to offload from the host computer at least a portion of communication protocol processing, including data transfer processing of the communication protocol processing, to accomplish at least one stateful communication connection for the transfer of data between the host computer and a peer via the network and, further, to operate a cache coherence protocol to scale coherent memory to multiple nodes; and a memory, wherein the memory is configured such that the processing pipeline may interact with the memory using an access procedure, to access a state by presenting, to the memory, an identifier corresponding to the state based on a message received by the network interface circuitry, wherein the state comprises one of a communication connection state and a cache coherence state; wherein