Patent ID: 9553020
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method comprising: bonding a first chip to a second chip; etching the first chip to form a first opening penetrating through a first semiconductor substrate of the first chip, wherein the first opening further extends into a first plurality of dielectric layers in the first chip, with a first metal pad in the first chip exposed to the first opening; forming a first dielectric layer extending on a bottom and sidewalls of the first opening; etching a bottom portion of the first dielectric layer and a dielectric region encircled by the first metal pad to form a second opening, with sidewall portions of the first dielectric layer remaining after the dielectric region is etched, wherein the second opening further extends down to a second metal pad in the second chip; and filling the first opening and the second opening with a conductive material to form a conductive plug.