Patent ID: 9589990
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A thin-film transistor array substrate comprising: a substrate; a plurality of scan lines on the substrate; a plurality of data lines on the substrate, wherein the plurality of scan lines are insulated and intersect with the plurality of data lines, and a plurality of pixel units are located near the intersections of the scan lines and the data lines; a gate electrode metal layer on the substrate; an insulating layer on the gate electrode metal layer, wherein the insulating layer comprises a via hole exposing a portion of the gate electrode metal layer; a semiconductor layer on the insulating layer wherein a portion of the semiconductor layer fills the via hole and contacts the gate electrode metal layer; and a source/drain electrode metal layer on the semiconductor layer, wherein the source/drain electrode metal layer fills the via hole partially by a patterning process using the semiconductor layer as an etch stop layer, wherein the gate electrode metal layer, the semiconductor layer and the source/drain electrode metal layer overlap at least partially.