Patent ID: 9704766
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. An interposer for a 3-dimensional integrated circuit (3D IC) package system, the interposer comprising: a substrate; a redistribution layer on the substrate; a first probe pad on the first surface; a second probe pad on the first surface; at least one first bump having a first dimension and being on the first surface, the at least one first bump being separated from the first probe pad in a first direction parallel to the first surface; a first electrical connection, on the first surface, electrically coupling the at least one first bump with the first probe pad; at least one second bump having the first dimension and being on the first surface, the at least one second bump being separated from the second probe pad in a second direction parallel to the first surface; a second electrical connection, on the first surface, electrically coupling the at least one second bump with the second probe pad; a third electrical connection which is substantially encapsulated by the redistribution layer, electrically coupling the at least one first bump with the at least one second bump; wherein the first probe pad is electrically coupled with the second probe pad through the first electrical connection, the at least one first bump, the third electrical connection, the second bump and the second electrical connection; third bumps having the first dimension adjacent to the first probe pad, the third bumps being electrically isolated from the first probe pad; first vias within the redistribution layer, the first vias being electrically coupled with corresponding ones of the third bumps; and first through-silicon-via (TSV) structures within the interposer, the first TSV structures being electrically coupled with corresponding ones of the first vias; and wherein the third bumps are electrically coupled with corresponding ones of the TSV structures through corresponding ones of the first vias; and wherein at least one of the first TSV structures and a corresponding at least one of the first vias are substantially coaxially aligned in a third direction which is orthogonal to the first surface.