Patent ID: 9634803
Date: 2017-04-25
CPC Classifications: G06F,H04B,H04J,H04L

Claim:
1. A system comprising: a joint forward error correction (FEC) code encoder to encode an associated input signal using at least one FEC code and provide an FEC code encoded output; a symbol mapper coupled to the joint FEC code encoder and configured to map the FEC code encoded output to a modulation format and provide a serial high symbol rate signal; a demultiplexer coupled to the symbol mapper and configured to separate the serial high symbol rate signal into a plurality of parallel low symbol rate signals, each of the plurality of low symbol rate signals having a symbol rate lower than the serial high symbol rate signal; a subcarrier modulator coupled to the demultiplexer and configured to modulate each of the plurality of parallel low symbol rate signals with a different subcarrier frequency to provide associated subcarrier signals; a multiplexer coupled to the subcarrier modulator and configured to multiplex the subcarrier signals to provide a subcarrier aggregate signal; and a modulator coupled to the multiplexer and configured to modulate an optical signal in response to the subcarrier aggregate signal to provide a subcarrier multiplexed optical signal.