Patent ID: 9577664
Date: 2017-02-21
CPC Classifications: G11B,H03F,H03K,H03M,H04B,H04L

Claim:
1. An apparatus comprising: a pair of circuit branches comprising a first circuit branch and a second circuit branch the pair of circuit branches arranged in a differential amplifier configuration, each circuit branch comprising one or more transistors connected in parallel, each transistor having an input connected to a wire of a multi-wire bus and configured to receive a symbol of a balanced codeword from the connected wire, wherein at least one of the circuit branches comprises at least two transistors receiving different symbols of the balanced codeword; each circuit branch further comprising a load impedance, connected in series with the one or more transistors of the corresponding circuit branch; a current source connected to the pair of circuit branches, the current source having a fixed current magnitude, the current source configured to draw currents through the one or more transistors and load impedance of each of the pair of circuit branches; and a differential amplifier output node having a differential voltage output signal formed by the load impedances, the differential voltage output signal having one of two values equal in magnitude and opposite in sign, wherein the sign of the value of the differential output signal is used to identify one or more output bits.