Patent ID: 9652248
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A computer implemented method for load queue entry reuse for operand store compare (OSC) history table update, the method comprising: issuing a load instruction into an instruction pipeline of a processor; allocating a load queue entry in a load queue to the load instruction, the load queue entry comprising a valid tag and a keep tag, wherein the valid tag is set and the keep tag is unset in the allocated load queue entry; determining whether the load instruction has been flushed; based on the load instruction not being flushed, determining whether the load instruction has been completed; based on determining the load instruction is completed: deallocating the load queue entry, unsetting the valid tag and unsetting the keep tag; flushing the load instruction by the instruction pipeline; based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag in the allocated load queue entry; reissuing the load instruction into the instruction pipeline; determining that the allocated load queue entry corresponds to the reissued load instruction; based on determining that the allocated load queue entry corresponds to the reissued load instruction: setting the valid tag and leaving the keep tag set in the allocated load queue entry; completing the reissued load instruction in the instruction pipeline; based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table with OSC information corresponding to the load instruction; based on determining that the allocated load queue entry does not correspond to the reissued load instruction: determining whether the load queue is full: allocating the identified load queue entry into the load instruction.