Patent ID: 9734802
Date: 2017-08-15
CPC Classifications: G02F,G09G

Claim:
1. A device comprising: a first circuit comprising a sampling circuit, a first latch circuit, and a second latch circuit, the first latch circuit and the second latch circuit being connected to an output of the sampling circuit; and a second circuit, wherein the first latch circuit comprises a memory circuit, wherein the memory circuit is configured to hold identical pieces of data of signals corresponding to a first period and a third non-adjacent period while writing in the second latch circuit different pieces of data of signals corresponding to a second period located between the first and the third periods, wherein the first circuit is configured to input into the second circuit the identical pieces of data for the first period from the first latch circuit, the different pieces of data for the second period from the second latch circuit, and the identical pieces of data for third period from the first latch circuit, sequentially and in this order, and wherein the sampling circuit is configured to sample signals and to input sampled signals into the first latch circuit and the second latch circuit.