Patent ID: 9691701
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method of manufacturing an integrated circuit, comprising: forming a plurality of wiring layers on a base, wherein at least one metal-insulator-metal (MIM) capacitor is formed within the plurality of wiring layers; coupling a semiconductor die to a first surface of the plurality of wiring layers, wherein the plurality of wiring layers further include conductors to connect the semiconductor die from the first surface of the plurality of wiring layers to a second surface of the plurality of wiring layers that is opposite to the first surface; encapsulating at least a portion of the semiconductor die in an insulating material; exposing the second surface of the plurality of wiring layers by removing at least a portion of the base; coupling a redistribution layer to the second surface of the plurality of wiring layers; coupling a circuit substantially below at least a portion of the MIM capacitor in the plurality of layers, wherein the circuit is electrically coupled to the capacitor through the plurality of wiring layers, wherein the circuit includes at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die; coupling a plurality of electrical connectors to the second surface at points separate from an area of the second surface that is occupied by the circuit; and connecting the integrated circuit to a circuit board using the plurality of electrical connectors.