Patent ID: 9536744
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of forming an alignment feature and a sidewall feature on an integrated circuit component, the method comprising: depositing a spacer material layer on the integrated circuit component comprising a gate electrode layer and a hard mask layer on the gate electrode layer; depositing a first mask layer on the spacer material layer and patterning an opening in the first mask layer; wherein the first mask layer is located on an alignment portion of the spacer material layer; removing the spacer material layer located in the opening of the first mask layer; depositing a mandrel material layer after removing the spacer material layer located in the opening of the first mask layer and polishing the mandrel material layer to form a polished mandrel material layer; depositing a second mask layer on the polished mandrel material layer and patterning a second opening in the second mask layer to expose an unprotected area of the polished mandrel material layer; removing the polished mandrel material layer located in the unprotected area to form a mandrel; depositing a sidewall spacer layer on the mandrel comprising a remaining mandrel material layer; etching the remaining mandrel material layer; removing portions of the hard mask layer selective to the spacer material layer and the gate electrode layer to form the alignment feature and the sidewall feature in the hard mask layer; and removing the alignment portion of the spacer material layer to expose the alignment feature and the sidewall feature.