Patent ID: 9602114
Date: 2017-03-21
CPC Classifications: G06F,H03L,H04L

Claim:
1. A method of designing a phase-locked loop, the phase-looked loop being of the type comprising: a controlled-frequency oscillator; a phase comparator, configured to determine a phase difference between an output signal of the said controlled-frequency oscillator and a reference signal; a first corrector, configured to receive as input a signal representative of the said phase difference and to generate at its output a first correction signal; at least one second corrector, configured to receive as input a signal representative of or affected by a phase noise of the said reference signal or of the said output signal of the said controlled-frequency oscillator and to generate at its output a second correction signal; and a circuit for generating a slaving signal for the said controlled-frequency oscillator from the said first and second correction signals; the said method comprising a step of determining transfer functions of the said correctors allowing rejection, in one and the same frequency band, the phase noise of the said reference signal and the phase noise of the said output signal of the said controlled-frequency oscillator, and wherein said step is implemented, by means of a computer, by applying the H-infinity (H∞) method utilizing: at input, a first weighting function for a phase noise of the said controlled-frequency oscillator and a second weighting function for a phase noise of a reference signal, and which are determined on the basis of nominal power spectral densities of the said noise; and at output, at least one third weighting function for a phase noise of an output signal of the phase-lock loop or of an error in tracking the said reference signal, determined on the basis of a phase noise power spectral density template of the said output signal having to be complied with.