Patent ID: 9715463
Date: 2017-07-25
CPC Classifications: G06F

Claim:
1. An integrated circuit comprising a memory and a processor, the memory comprising one or more memory regions and the processor comprising: a protection bit management element configured to receive protection setting information from a secured bus and generate protection information that specifies a unique protection bit corresponding to a memory region of the one or more memory regions; a plurality of processing stages for processing instructions retrieved from the memory; and a commit processing stage, of the plurality of processing stages configured to: receive address information from a previous processing stage of the plurality of processing stages, the address information identifying a protected memory region of the one or more memory regions; determine the protection state of the protected memory region in accordance with a corresponding protection bit derived from the protection information; control a state of one or more switches included in the commit processing stage based at least in part on the determined protection state for the protected memory region; and regulate access to the protected memory region using the one or more switches.