Patent ID: 9691900
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method of forming a complementary metal oxide semiconductor (CMOS) device structure, the method comprising: forming a spacer layer material over a substrate and over gate structures defined in both a first polarity type region and a second polarity type region of the substrate; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers, leaving the spacer layer material in the second polarity type region intact; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first epitaxially grown SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region, wherein the selectively formed protection layer prevents additional growth of epitaxial material on the first epitaxially grown SD regions, forming first and second electrically conductive SD contacts, an end of the first electrically conductive SD contacts contacting an upper surface of the first epitaxially grown SD regions, and an end of the second electrically conductive SD contacts contacting an upper surface of the second epitaxially grown SD regions, wherein a portion of the electrically conductive SD contacts are surrounded by the protection layer, while the protection layer is excluded from upper surfaces of the gate structures located in the first epitaxially grown SD regions.