Patent ID: 9673054
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method of forming an array of gated devices, the gated devices being arranged in rows and columns and comprising an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region, the method comprising: forming metal lines within bottoms of trenches between walls that longitudinally extend along one of rows or columns; forming pillars individually to comprise the mid region and the outer region of individual gated devices; forming a plurality of access lines elevationally outward of the metal lines and that individually are laterally proximate the mid regions along individual of the rows; forming a plurality of data/sense lines that individually are elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns; and the metal lines being formed to individually longitudinally extend along and between immediately adjacent the one of the rows or columns and being directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows or columns, the metal lines being electrically isolated from the data/sense lines, the metal lines being formed to the same total vertical thickness as that of the inner regions, the metal lines and the inner regions having respective longitudinally-elongated-uppermost surfaces that are elevationally coincident, the metal lines and the inner regions having respective longitudinally-elongated-lowermost surfaces that are elevationally coincident, the inner regions comprising doped semiconductor material that is directly against sidewalls of immediately-adjacent of the metal lines from their respective longitudinally-elongated-lowermost surfaces to their respective longitudinally-elongated-uppermost surfaces.