Patent ID: 9685908
Date: 2017-06-20
CPC Classifications: H03B

Claim:
1. A variable capacitor connected between first and second signal lines which are differential signal lines included in an integrated circuit of a differential structure and including first and second transistors coupled thereto, the variable capacitor comprising: a plurality of semiconductors separately arranged to receive a control voltage from an outside, and corresponding to a source region or a drain region; and a plurality of gate regions disposed between the semiconductors, wherein, among the gate regions, first gate regions corresponding to (2n−1)-th (n being a positive integer) serve as a gate of the first transistor and are connected with the first signal, and second gate regions corresponding to 2n-th serve as a gate of the second transistor and are connected with the second signal line, and the first and second transistors are formed such that positions of the source region and the drain region are opposite to each other based on the gate region thereof, and share source regions or drain regions through a semiconductor between the first and second gate regions.