Patent ID: 9728237
Date: 2017-08-08
CPC Classifications: G11C

Claim:
1. A determination circuit comprising: a first inverter circuit; a second inverter circuit which has a higher potential side node coupled to a higher potential side node of the first inverter circuit at a first node, has a lower potential side node coupled to a lower potential side node of the first inverter circuit at a second node, includes an input coupled to an output of the first inverter circuit, a first bit line, and a first signal line, and includes an output coupled to an input of the first inverter circuit, a second bit line, and a second signal line; a first transistor which turns on when receiving an asserted first signal; and a first capacity component including a first end which receives an inversion signal of the first signal, wherein the first node is coupled to a first potential node, the first transistor is coupled between the second node and a second potential node having a lower potential than a potential of the first potential node, and a second end of the first capacity component is coupled to the second node, or the second node is coupled to the second potential node, the first transistor is coupled between the first potential node and the first node, and the second end of the first capacity component is coupled to the first node, and the first signal is supplied to the first end of the first capacity component through odd logic inverters coupled in series.