Patent ID: 9641809
Date: 2017-05-02
CPC Classifications: H04N

Claim:
1. A circuit arrangement for processing a digital video stream and for detecting a fault in the processed digital video stream, the circuit arrangement comprising: an input interface for receiving an digital video stream, the digital video stream comprises information of a sequence of frames, the sequence of frames including first, second, and third frames; a processing circuit which is arranged to process the digital video stream and to provide the processed digital video stream to an output interface; and a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a memory to store a predefined amount of generated checksums including the first, second, and third checksums; and an analyzing unit arranged to compare a currently generated checksum of a current frame of the sequence of frames of the processed digital video stream with a plurality of corresponding checksums of preceding frames stored in the memory including the first, second, and third checksums, and to generate an error signal if at least one predefined amount of compared checksums are matching.