Patent ID: 9678399
Date: 2017-06-13
CPC Classifications: G02F

Claim:
1. An array substrate, comprising: a base substrate; gate lines and data lines that are arranged in a cross manner on the base substrate and a common electrode, wherein the common electrode comprises: sub-electrodes each in pixel areas defined by the gate lines and the data lines, common electrode lines that extend in a same direction as the gate lines and are employed to transmit a common electrode signal to the sub-electrodes, and connection lines that each electrically connects two sub-electrodes that are adjacent to each other in a direction along which the data lines extend; and data-line repair lines that are connected with the data lines and insulated from the common electrode within the pixel areas, wherein an orthogonal projection of the data-line repair lines on the base substrate has an overlapped area with an orthogonal projection of the sub-electrodes or the connection lines on the base substrate.