Patent ID: 9577115
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a plurality of isolation layer patterns spaced apart from each other in a second direction on a substrate, each of the isolation layer patterns extending in a first direction crossing the second direction and having a plurality of recesses extending therein from a top surface, each of said plurality of recesses being surrounded by a respective isolation layer pattern with a bottom of the recess being defined by a surface of the respective isolation layer pattern, said plurality of recesses being spaced apart from each other in the first direction thereon; a plurality of gate structures spaced apart from each other in the first direction on the substrate and the isolation layer patterns, each of the gate structures extending in the second direction; and an insulation layer pattern structure on the substrate, the isolation layer patterns and the gate structures, the insulation layer pattern structure having a plurality of air gaps spaced apart from each other in the first direction therein, each one of the plurality of air gaps extending in the second direction between the plurality of gate structures and having upper and lower portions, the lower portions of the air gaps being in the plurality of recesses that extend below said plurality of gate structures and below the top surfaces of said plurality of isolation layer patterns, wherein bottom surfaces of the air gaps are lower than a top surface of said substrate.