Patent ID: 9705484
Date: 2017-07-11
CPC Classifications: G06F,H03K

Claim:
1. A delay cell for generating a desired delay defined in a standard cell library comprising: a first delay element, receiving an input signal at an input node to generate a first internal signal with a first propagation delay relative to the input signal at a first internal node, wherein the first delay element comprises: a first P-type transistor, supplied by a supply voltage and controlled by the input signal, wherein the first P-type transistor has a first P-type turn-on resistance; a first resistor, coupled between the first P-type transistor and the first internal node, wherein the first resistor has a first resistance; a second resistor, coupled to the first internal node, wherein the second resistor has a second resistance, wherein the first propagation delay is dominated according to the first resistance, the second resistance, and a capacitance at the first internal node; and a first N-type transistor, coupled between the second resistor and a ground and controlled by the input signal, wherein the first N-type transistor has a first N-type turn-on resistance, wherein the first resistance exceeds 10 times the first P-type turn-on resistance, and the second resistance exceeds 10 times the first N-type turn-on resistance; and an output inverter, receiving the first internal signal to generate an output signal with the desired delay relative to the input signal, wherein the output inverter is configured to provide a driving capability defined in the standard cell library for a following stage, wherein the desired delay is dominated by the first propagation delay.