Patent ID: 9590027
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method for fabricating an electronic component, the method comprising: fabricating, on a substrate, at least one integrated MIM capacitor having a top capacitor electrode, and a bottom capacitor electrode at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer on the top capacitor electrode, wherein the first cover layer at least partly covers the top capacitor electrode and includes a lead-containing dielectric material; thinning the first cover layer, wherein the thinning step removes a more than proportional amount of lead from the lead-containing dielectric material such that the lead-containing dielectric material has a lower concentration of lead after the thinning step than before the thinning step; fabricating an electrically insulating second cover layer on the first cover layer, wherein the second cover layer at least partly covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer on the second cover layer, wherein the resistor layer has a defined ohmic resistance.