Patent ID: 9619750
Date: 2017-04-11
CPC Classifications: G06F,G06N

Claim:
1. A processor comprising: a store buffer for buffering store operations prior to completion, the store operations to store data to a memory hierarchy; and a store dependence predictor to predict whether load operations should be permitted to speculatively skip over each store operation based on a lookup of an array and responsively setting an indication within an entry associated with each store operation in the store buffer, the entry including bits of an instruction address of the store operation, wherein the store dependence predictor comprises the array containing a counter value associated with each store operation, wherein the store dependence predictor decrements a counter for a store operation each time a load operation hits an address of the store operation and increments the counter each time a load operation does not hit the address of the store operation; wherein a load operation checks the indication in the store buffer to determine whether to speculatively execute ahead of each store operation.