Patent ID: 9583597
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A semiconductor structure comprising: a support substrate; an electrical insulator layer overlying the support substrate and in direct physical contract with the support substrate; a first, second, and third fin structure disposed over and in direct physical contact with the electrical insulator layer, wherein the electrical insulator layer is continuous and uninterrupted underneath and between each of the first, second, and third fin structures, wherein the first fin structure is spaced apart from the second, adjacent fin structure by a first gap region having a first width across the semiconductor substrate, and wherein the second fin structure is space apart from the third, adjacent fin structure by a second gap region having a second width across the semiconductor substrate that is greater than the first width; a first metal gate structure comprising a first gate dielectric layer and a first metal gate material, the first metal gate structure being disposed within the first gap region so as to be in direct physical contact with a first sidewall of the first fin structure and a first sidewall of the second fin structure, wherein the first sidewalls of the first and second fin structures face each other across the first gap region, wherein the first metal gate structure is not disposed within the second gap region; and a second metal gate structure comprising a second gate dielectric layer and a second metal gate material, the second metal gate structure being disposed within the second gap region so as to be in direct physical contact with a second sidewall, opposite the first sidewall, of the second fin structure and a first sidewall of the third fun structure, wherein the second sidewall of the second fin structure and the first sidewall of the third fin structure face each other across the second gap region, wherein the second metal gate structure is not disposed within the first gap region.