Patent ID: 9570562
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method of planarizing a polysilicon gate, comprising: step 01: growing a polysilicon gate layer on a substrate having trenches filled with materials; wherein the surface of the polysilicon gate layer is uneven; step 02: depositing an oxide layer on the polysilicon gate layer; wherein the oxide layer has a flat surface; step 03: oxidizing the top portion of the polysilicon gate layer from the flat surface of the oxide layer, thereby the top portion of the polysilicon gate layer is oxidized to form a silicon oxide interlayer; the bottom of the silicon oxide interlayer is aligned with or lower than the low-lying areas of the surface of the polysilicon gate layer; step 04: removing the oxide layer and the silicon oxide interlayer formed by thermal oxidation, so as to form a flat surface of the polysilicon gate layer.