Patent ID: 9639326
Date: 2017-05-02
CPC Classifications: G06F

Claim:
1. A method for performing floating-point operations on an integrated circuit, comprising: receiving a first floating-point number having a first exponent and a first mantissa, a second floating-point number having a second exponent and a second mantissa, and a third floating-point number having a third exponent and a third mantissa, wherein each of the first, second, and third mantissas has a given precision; with bit extension circuitry on the integrated circuit, expanding the given precision of the first, second, and third mantissas to a greater number to produce corresponding first, second, and third extended mantissas, wherein the greater number is at least twice as big as the given precision; and with shifting circuitry on the integrated circuit, right shifting the first, second, and third extended mantissas to produce first, second, and third shifted mantissas.