Patent ID: 9558119
Date: 2017-01-31
CPC Classifications: G06F

Claim:
1. A method of main memory operation in a multi-node symmetric multiprocessing computer, the computer comprising a plurality of compute nodes, each compute node comprising at least one processor operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among and segmented across the compute nodes, and each cache controller coupled for data communications to cache controllers on other compute nodes, the method comprising: receiving, in the cache controller from an issuing resource, a memory instruction for a memory address, the memory instruction requiring writing data to main memory; wherein the cache controller receiving the memory instruction is on a compute node without main memory affinity for the memory address; locking by the cache controller the memory address against further memory operations for the memory address; establishing cache coherence for the memory address by communications among the compute nodes according to a cache coherence protocol, wherein establishing cached coherence for the memory address comprises identifying a compute node with main memory affinity for the memory address; wherein identifying the compute node with main memory affinity for the memory address comprises receiving a transmission from the compute node with main memory affinity for the memory address indicating the main memory affinity; advising the issuing resource of completion of the memory instruction only after establishing cache coherence for the memory address, after the identifying the compute node with main memory affinity for the memory address, and before the memory instruction completes in main memory; issuing by the cache controller the memory instruction to main memory including issuing the memory instruction through the cache coherence protocol to a cache controller on the compute node having main memory affinity for the memory address; and unlocking the memory address only after completion of the memory instruction in main memory.