Patent ID: 9658949
Date: 2017-05-23
CPC Classifications: G01R,G06F

Claim:
1. A test system for testing a plurality of system on chips, the test system comprising: a plurality of test units configured to test the plurality of system on chips according to a plurality of test cases, respectively; a power supplier configured to supply, to each of the plurality of test units, power of a level corresponding to a corresponding test case, among the plurality of test cases; a temperature controller configured to provide, to each of the plurality of test units, a temperature control signal according to the corresponding test case, and to monitor a measurement temperature, provided from each of the plurality of test units, of each of the plurality of system on chips; and an analyzer configured to analyze at least one of a driving voltage, a driving current, and a driving frequency of each of the plurality of system on chips, provided from each of the plurality of test units, wherein each of the plurality of test units determines whether software driven in any of the plurality of system on chips is defective based on respective test results with respect to the plurality of system on chips.