Patent ID: 9660056
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor device, the method comprising: forming a first trench in a first insulating layer; forming a two-dimensional (2D) material layer over the first insulating layer, the 2D material layer covering an upper surface of the first insulating layer, sidewalls of the first trench, and a bottom of the first trench; forming a gate dielectric over a portion of the 2D material layer; forming a first gate electrode over the gate dielectric along a first sidewall of the first trench; forming a source contact to the 2D material layer along the first sidewall of the first trench on a first side of the first gate electrode; and forming a drain contact to the 2D material layer along the first sidewall of the first trench on a second side of the first gate electrode.