Patent ID: 9588881
Date: 2017-03-07
CPC Classifications: G06F,Y02D

Claim:
1. A method for operating a stack processor comprising: a data POP wherein data is transferred from a bottom portion of a data stack to a top portion of the data stack in a first cycle of the stack processor, wherein the top portion of the data stack is in a volatile memory in a Forth core in the stack processor and the bottom portion of the data stack is in a ferroelectric random access memory in the stack processor, separate from the Forth core and coupled to the Forth core by a single code/data bus extending between the Forth core and ferroelectric random access memory only, and wherein data is transferred from the bottom portion of the data stack to the top portion of the data stack through the single code/data bus; transferring data from the top portion of the data stack to a top portion of a return stack in a second cycle of the stack processor, wherein the top portion of the return stack is a single register in the volatile memory, and wherein transferring data between the top portion of the data stack and the top portion of the return stack comprises copying data in the top portion of the data stack to the top portion of the return stack; and a return PUSH wherein data is transferred from the top portion of the return stack to a bottom portion of the return stack in a third cycle of the stack processor, wherein the bottom portion of the return stack is in the ferroelectric random access memory, and wherein data is transferred from the top portion of the return stack to the bottom portion of the return stack through the single code/data bus, wherein the first, second and third clock cycles are sequential, and wherein the data POP, return PUSH and the transferring data are performed in response to a stack-based computer programming language.