Patent ID: 9608160
Date: 2017-03-28
CPC Classifications: H01L,H01S

Claim:
1. A method for forming a semiconductor structure comprising: forming a dielectric material layer on an uppermost surface of a (100) silicon substrate; patterning the dielectric material layer forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching the exposed another portions of the uppermost surface of the (100) silicon substrate to form a plurality of openings within the (100) silicon substrate, each of the plurality of openings exposing a surface having a (111) crystal plane within the (100) silicon substrate; forming a buffer layer on exposed surfaces of the plurality of patterned dielectric material structures and the (100) silicon substrate; forming a dual phase Group III nitride structure filling a space between each neighboring pair of the plurality of patterned dielectric material structures and one of the plurality of openings located beneath the space, wherein the dual phase Group III nitride structure comprises a wurtzite phase region and a cubic phase region, wherein the cubic phase region defines an uppermost surface of the Group III nitride structure; and epitaxially growing at least one Group-III nitride layer on the cubic phase region of the dual phase Group-III nitride structure, wherein the epitaxially growing the at least one Group-III nitride layer comprises: