Patent ID: 9704566
Date: 2017-07-11
CPC Classifications: G11C

Claim:
1. A static random access memory circuit in a semiconductor device comprising: a power supply line; a plurality of word lines; a pair of bit lines; a plurality of memory cells coupled to the plurality of word lines and the pair of bit lines such that each memory cell is coupled to one word line and the pair of bit lines; a first circuit comprising: a second circuit comprising: wherein the first PMOS transistor and the second PMOS transistor have their gates coupled to receive a first control signal, wherein the third PMOS transistor and the fourth PMOS transistor have their gates coupled to receive a second control signal different from the first control signal, wherein the static random access memory circuit has a resume standby mode and a normal operation mode, wherein, when the static random access memory circuit is in the resume standby mode, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are turned off by the first control signal and the second control signal, respectively, and wherein, when the static random access memory circuit is changed from the resume standby mode to the normal operation mode: