Patent ID: 9684760
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A method, comprising: by a computer, analyzing the behavior of a circuit starting from a seed state for a first number of cycles of operation, wherein the analyzing comprises verifying a property of the circuit based at least in part on the value of a first proof radius variable using a first formal verification tool, the first proof radius variable being indicative of an amount of analysis performed for the property of the circuit without finding a counter-example for the property; by the computer, analyzing the behavior of the circuit starting from the seed state for a second number of cycles of operation, wherein the analyzing comprises verifying a property of the circuit based at least in part on the value of a second proof radius variable using a second formal verification tool, the second proof radius variable being indicative of an amount of analysis performed for the property of the circuit without finding a counter-example for the property; and by the computer, comparing the first proof radius and the second proof radius to determine a relative performance of the first and second formal verification tools.