Patent ID: 9733900
Date: 2017-08-15
CPC Classifications: G06F

Claim:
1. A multi-bit full adder based on resistive-switching devices, comprising: N word lines arranged in parallel, wherein N is larger than or equal to 3 and 1 N word line gating devices respectively connected to corresponding word lines; N bit lines arranged in parallel and placed across the word lines arranged in parallel, wherein 1 N bit line gating devices respectively connected to corresponding bit lines; N*N resistive-switching units each being located in a crossing point of a corresponding word line and a corresponding bit line and being connected to the corresponding word line and the corresponding bit line, wherein each resistive-switching unit has a first resistance state, a second resistance state, a third resistance state, and a fourth resistance state, and a resistance value in the first resistance state is less than a resistance value in the second resistance state, the resistance value in the second resistance state is less than a resistance value in the third resistance state, and the resistance value in the third resistance state is less than a resistance value in the fourth resistance state, where the first resistance state and the third resistance state represent “0” and the second resistance state and the fourth resistance state represent “1”; wherein, in data input through the word lines, input “1” represents a positive level pulse, and input “0” represents a zero level pulse, in data input through the bit lines, input “1” represents a negative level pulse, and input “0” represents a zero level pulse, a standard sum of an i