Patent ID: 9548748
Date: 2017-01-17
CPC Classifications: H03K,H03L

Claim:
1. A method, comprising: dividing a frequency of a reference clock signal to generate a second clock signal; generating a feedback clock signal based on a high-frequency clock signal from a digitally controlled oscillator (DCO) and a phase locked loop (PLL) feedback divide number; generating, based on the second clock signal and the feedback clock signal, a lead/lag detection result that indicates whether the feedback clock signal leads or lags the second clock signal; digitizing a skew between a falling edge of the second clock signal and a rising edge of the feedback clock signal to generate a skew signal that indicates the skew between the falling edge of the second clock signal and the rising edge of the feedback clock signal; and processing, during each cycle of the second clock signal, the lead/lag detection result and the skew signal to generate a digital control signal that controls cycle time of the DCO to change frequency of the high-frequency clock signal.