Patent ID: 9748961
Date: 2017-08-29
CPC Classifications: H03L,H03M

Claim:
1. A retiming circuit comprising: a clocked circuit for providing data in response to a reference clock, the reference clock having a rising edge and a falling edge; a positive-edge triggered capture register to capture data from the clocked circuit at the rising edge of the reference clock; a negative-edge triggered capture register to capture data from the clocked circuit at the falling edge of the reference clock; a selection circuit to sample the state of the reference clock and a second clock that is asynchronous to the reference clock, and select one of the positive-edge triggered capture register and the negative-edge triggered capture register based on the sampling; a first output register to receive data output from a selected one of the positive-edge triggered capture register and the negative-edge triggered capture register, wherein the first output register is clocked by the second clock; and a delay circuit operatively coupled to the first output register, wherein the delay circuit delays application of the second clock to the first output register; wherein data from the selected register is clocked to an output of the retiming circuit.