Patent ID: 9634094
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A transistor comprising: a semiconductor region having a plurality of transistor channel regions; gate fingers that overlap that semiconductor region, wherein each gate finger lies above a respective transistor channel region in the plurality of transistor channel regions, and wherein the gate fingers are coupled together to form a gate; isolation structures that surround the semiconductor region, wherein one of the isolation structures has an edge that is separated from an edge of an adjacent one of the gate fingers by a distance without any intervening gate structures therebetween, and wherein the gate fingers have adjacent edges that are separated from each other by a gate-to-gate spacing that is less than the distance; an entirety of dummy gate structures formed on the isolation structures; and an epitaxial region that is formed in the distance between the adjacent one of the gate fingers and the one of the isolation structures and that generates stress in a corresponding transistor channel region of the plurality of transistor channel regions.