Patent ID: 9634145
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A transistor comprising: a substrate; an electrically conductive gate over the substrate, the gate having a gate length; a source electrode and a drain electrode over the substrate, the source and drain electrodes separated by a gap defining a channel region, the channel region having a channel length that is less than the gate length; a semiconductor layer in contact with the source and drain electrodes, the semiconductor layer having a semiconductor pattern; a dielectric stack having a portion between the gate and the semiconductor layer, the portion of the dielectric stack having a surface that is in contact with the gate across the entire surface of the portion of the dielectric stack and having a plurality of dielectric layers that are in contact with each other with no intervening non-dielectric layers, wherein the portion of the dielectric stack includes first, second, and third regions, the first region in contact with the semiconductor layer in the channel region and having a first thickness, the second region adjacent to the first region and having the first thickness, and the third region adjacent to the second region and having a thickness that is greater than the first thickness; wherein one of the plurality of dielectric layers in the dielectric stack is a buffer layer that is in contact with the semiconductor layer, and wherein the buffer layer has the same pattern as the semiconductor layer such that terminating edges of the buffer layer are aligned to be coincident with terminating edges of the semiconductor layer; wherein another of the plurality of dielectric layers in the portion of the dielectric stack has a pattern such that it is present in the third region but is not present in the first and second regions such to provide the greater thickness.