Patent ID: 9595478
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A method comprising: forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; filling the first gate contact trench with a metal to form a first gate contact; removing a second sidewall spacer or a second cap on a second side of a second dummy gate structure and forming a second gate contact trench over the second dummy gate structure; filling the first and second gate contact trenches with tungsten, tungsten alloy, copper, aluminum-copper alloy, or silicon-copper alloy; and forming at least one real gate structure between the first and second dummy gate structures.