Patent ID: 9595561
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a plurality of cell gate electrodes extending in a first direction, each of the cell gate electrodes disposed in a cell region of a semiconductor substrate with a cell gate dielectric layer disposed between the cell gate electrode and the semiconductor substrate; a plurality of bit lines extending in a second direction perpendicular to the first direction; and a plurality of data storage elements arranged along the first and second directions, the data storage elements electrically connected between the bit lines and a doped region formed adjacent to the cell gate electrode; wherein each of the bit lines is in direct contact with the data storage elements arranged along the second direction, and wherein each of the bit lines includes first portions contacting with the data storage elements and a second portion between the data storage elements, and wherein the first portions have a first thickness and the second portion has a second thickness greater than the first thickness.