Patent ID: 9620565
Date: 2017-04-11
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device comprising: a plurality of memory cells arranged in rows and columns; a source line electrically connected to one terminal of each of the memory cells; a bit line electrically connected to the other terminal of each of the memory cells; a plurality of first word lines, each electrically connected to memory cells included in a corresponding one of the rows; and a plurality of second word lines, each electrically connected to memory cells included in a corresponding one of the columns; wherein each of the memory cells comprises: a first selection transistor including a current path having one end electrically connected to the source line; a second selection transistor including a current path having one end electrically connected to the other end of the current path of the first selection transistor; and a variable resistance element including a current path having one end electrically connected to the other end of the current path of the second selection transistor, and the other end electrically connected to the bit line.