Patent ID: 9748141
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate, wherein the first semiconductor layer is doped; patterning the second and first semiconductor layers to form an initial fin; depositing a dielectric layer on the substrate to cover the initial fin, wherein a portion of the dielectric layer on top of the initial fin has a thickness sufficiently less than that of a portion of the dielectric layer on the substrate, and wherein the deposited dielectric layer has a first surface whose lowest level is above a top surface of the initial fin; etching back the dielectric layer from the first surface in one step so that the etched dielectric layer has a second surface lower than the first surface to form an isolation layer, wherein the isolation layer partially exposes the first semiconductor layer, thereby defining a fin above the isolation layer, and wherein the second surface is substantially flat; and forming a gate stack intersecting the fin on the isolation layer.