Patent ID: 9626168
Date: 2017-04-18
CPC Classifications: G06F

Claim:
1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a computer program residing in the memory, the computer program including a plurality of instructions that includes at least one vector instruction; and a compiler residing in the memory and executed by the at least one processor, the compiler including a vector instruction optimization mechanism that eliminates at least one vector element reverse operation from the computer program to enhance run-time performance of the computer program, wherein the vector instruction optimization mechanism records characteristics of vector instructions and forms subgraphs of related instructions by analyzing def-use and use-def chains for the computer program in a first pass, determines whether any of the subgraphs cannot be optimized in a second pass, identifies a computation in the computer program where all operations performed on input vectors are single instruction multiple data (SIMD) instructions and marks at least one vector element reverse operation that corresponds to the computation for removal in a third pass, and deletes in a fourth pass the at least one vector element reverse operation marked for removal in the third pass.