Patent ID: 9721663
Date: 2017-08-01
CPC Classifications: G11C,H01L

Claim:
1. A memory device, comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; an array of memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, and the electrically conductive layers comprise word lines for the memory stack structures; a word line decoder circuitry including switches for activating a respective word line for the memory stack structures, and located underneath the array of memory stack structures and above the substrate; a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure electrically contacting a node of a respective device in the word line decoder circuitry; bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures; upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers; and at least one element selected from: a first element of word line contact via structures contacting a respective electrically conductive layer and extending above the alternating stack and contacting a respective upper-interconnect-level word line connector; a second element of a combination of at least one dielectric material layer overlying the word line decoder circuitry, and a semiconductor material layer overlying the at least one dielectric material layer and underlying the alternating stack; and a third element of a bit line decoder circuitry including switches for activating a respective bit line for the memory stack structures, located underneath the array of memory stack structures and above the substrate and adjacent to the word line decoder circuitry, and having an areal overlap with the area of the array of memory stack structures in the plan view.