Patent ID: 9685508
Date: 2017-06-20
CPC Classifications: B82Y,G05F,H01L

Claim:
1. A method of forming a high voltage transistor on a substrate, the method comprising: epitaxially growing a stack of semiconductor materials on the substrate, the stack comprising at least a first semiconductor material and a second semiconductor material having a larger bandgap than a bandgap of the first semiconductor material; etching the stack to define a nanowire; forming a drain contact coaxially wrapping completely around the first semiconductor material along a longitudinal drain length of the nanowire; forming a source contact coaxially wrapping completely around the first semiconductor material along a longitudinal source length of the nanowire; forming a gate conductor coaxially wrapping completely around the first semiconductor material along a longitudinal channel length of the nanowire, wherein the gate conductor is spaced apart from the drain contact by an extrinsic drain region comprising the second semiconductor material.