Patent ID: 9620406
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor device, the method comprising: forming a first fin-shaped pattern that includes an upper part and a lower part on a substrate; removing a portion of the upper part of the first fin-shaped pattern so as to reduce a width of the upper part of the first fin-shaped pattern at a first height above an upper surface of the substrate in order to form a second fin-shaped pattern; forming a dummy gate electrode that intersects the second fin-shaped pattern on the second fin-shaped pattern; and removing a portion of an upper part of the second fin-shaped pattern after forming the dummy gate electrode so as to reduce a width of the upper part of the second fin-shaped pattern at the first height above the upper surface of the substrate in order to form a third fin-shaped pattern.