Patent ID: 9672906
Date: 2017-06-06
CPC Classifications: G11C,H01L

Claim:
1. A memory device, comprising: a first electrode having an electrode surface; a conglomerate material on the electrode surface, the conglomerate material including nanocrystalline grains embedded in an amorphous matrix; a second electrode on the conglomerate material; and circuitry to apply a first bias arrangement to induce formation of amorphous material between the nanocrystalline grains within a region over the electrode surface, effective to increase electrical resistance of the conglomerate material between the first and second electrodes above a first threshold without eliminating nanocrystalline grains in the region, and to apply a second bias arrangement to induce expansion of the nanocrystalline grains in the region by an amount effective to decrease electrical resistance of the conglomerate material between the first and second electrodes below a second threshold.