Patent ID: 9727494
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A machine implemented method for sending an input/output status block (IOSB) and an interrupt message to a processor of a computing system interfacing with a device, comprising: placing an input/output command block (IOCB) by the processor of the computing system at a memory of the computing system with a command for the device to perform a task; retrieving the IOCB with the command by the device from the memory of the computing system using a direct memory access (DMA) operation; executing a task associated with the command by the device from one of reading and writing data to and from a networked storage device; configuring a DMA channel by a processor of the device for sending the IOSB indicating a status of the IOCB and for sending the interrupt message immediately after the IOSB using a same data path used for the interrupt message and the IOSB; generating the IOSB by the processor of the device; queuing by the device, the IOSB for transmission using the DMA channel; setting by the device, an indicator associated with the IOSB that triggers sending the interrupt message associated with the IOSB immediately after the IOSB is sent using the same data path; retrieving information by the device for generating the interrupt message after the IOSB is queued for transmission to the processor of the computing system; generating the interrupt message by the device while the IOSB is waiting to be transmitted; queuing the interrupt message behind the IOSB by the device; and transmitting the IOSB to the processor of the computing system by the device, followed immediately by the interrupt message, using the same data path for sending both the IOSB and the interrupt message to maintain an order between the IOSB and the interrupt message such that the interrupt message is sent after the IOSB.