Patent ID: 9614538
Date: 2017-04-04
CPC Classifications: G05F,G11C,H03L,H03M,H04L

Claim:
1. An integrated circuit (IC), comprising: sample-and-hold circuitry to sample an input signal based on a clock signal, and to output a sampled voltage for at least a holding period; a plurality of adjustable comparators, wherein each adjustable comparator has a respective reference voltage that is adjustable, and wherein each adjustable comparator outputs a result signal based on comparing the sampled voltage with the adjustable comparator's reference voltage; and control-logic circuitry to predict a voltage range of a future sample of the input signal, and to set reference voltages of the plurality of adjustable comparators based on the predicted voltage range of the future sample of the input signal, wherein the control-logic circuitry predicts the voltage range of the future sample of the input signal directly based on the result signals outputted by the plurality of adjustable comparators.