Patent ID: 9665346
Date: 2017-05-30
CPC Classifications: G06F

Claim:
1. A method, in a data processing system, for performing a floating point arithmetic operation, comprising: receiving, in hardware logic of the data processing system, a plurality of floating point operands of the floating point arithmetic operation; shifting, by the hardware logic, bits in a mantissa of at least one floating point operand of the plurality of floating point operands; storing, by the hardware logic, one or more bits of the mantissa that are shifted outside a range of bits of the mantissa of the at least one floating point operand; associating, by the hardware, a probability weight with each of the one or more shifted bits of the mantissa that are shifted outside the range of the bits of the mantissa of the at least one floating point operand; and generating, by the hardware logic, a resultant value for the floating point arithmetic operation based on the plurality of floating point operands and the probability weight associated with each of the one or more shifted bits.