Patent ID: 9684592
Date: 2017-06-20
CPC Classifications: G06F,G11C

Claim:
1. A processing system, comprising: a first memory storing a plurality of data items arranged in a first sequence, each data item having an associated memory address on the first memory; at least one processor coupled to the first memory and arranged to read and write data directly to the first memory; and a direct memory access controller coupled to the first memory, and including: wherein the computed sequence of read addresses and the computed sequence of write addresses are combined such that the direct memory access controller is configured to transfer the plurality of data items directly from the first memory to the second memory using the computed sequence of read addresses and the computed sequence of write addresses, such that the data items written to the second memory during the transfer are arranged in a second sequence that is different from the first sequence, and wherein a read mode is a pattern in which data items are read from memory in a single transaction and a write mode is a pattern in which data items are written to memory in a single transaction.