Patent ID: 9659652
Date: 2017-05-23
CPC Classifications: G06F,G11C

Claim:
1. A memory system comprising: a controller circuit capable of outputting a first chip enable signal, a second chip enable signal, a command latch enable signal, and an address latch enable signal; a first semiconductor chip including a first memory cell array and a first termination circuit, and configured to receive the first chip enable signal, the first termination circuit including a first termination resistor; a second semiconductor chip including a second memory cell array, and configured to receive the first chip enable signal; and a third semiconductor chip including a third memory cell array, and configured to receive the second chip enable signal; wherein the first semiconductor chip and a selected one of the second and third semiconductor chips are electrically connected to the controller circuit via a common data bus, the controller circuit sends a first command signal and a first address signal to the first semiconductor chip, the first address signal specifying the first semiconductor chip as a first target semiconductor chip, and the first command signal representing a command for activating an on-die termination of the first target semiconductor chip without information other than the command, the first semiconductor chip receives the first command signal while the command latch enable signal is active, the first semiconductor chip receives the first address signal while the address latch enable signal is active, the first semiconductor chip activates the first termination circuit based on the first command signal and the first address signal, and the controller circuit performs data transfer with the selected one of the second and third semiconductor chips via the common data bus while the first termination circuit is active.