Patent ID: 9735254
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method of manufacturing a trench-gate semiconductor device, comprising: forming a silicon substrate with an epitaxial layer doped with a first type of dopant, and which defines a device drift region; etching a gate trench into the substrate; forming a first portion of a gate oxide against at least side walls of the trench and forming a thicker gate oxide at a bottom of the trench; implanting a pillar region beneath the gate trench doped with a second type of dopant of opposite type to the first type of dopant; depositing, doping and annealing a gate electrode in the gate trench; implanting and annealing a semiconductor body region on each side of the gate trench; implanting and annealing source regions on each side of the gate trench over the semiconductor body region; forming a second portion of gate oxide on top of the first portion of gate oxide; etching the semiconductor body region using the second portion of gate oxide as a mask to form a moat region at the sides of the source regions to form contact openings for contact with the source regions; implanting and annealing RESURF regions at a base of the moat, wherein the RESURF regions are formed on each side of the gate trench, doped with the second type of dopant of opposite polarity type to the first type of dopant, and extend more deeply into the drift region than the gate trench; and depositing and patterning a metallisation layer to form source and gate contacts, wherein the pillar region is beneath and in substantial contact with the gate trench and configured and arranged to act as an additional RESURF region and reduce the effective width of the drift region in an area between the RESURF regions and increase gate shielding, and wherein the pillar region is formed to a depth which is at least substantially equal to the depth of the RESURF regions.