Patent ID: 9628264
Date: 2017-04-18
CPC Classifications: H04B,H04L

Claim:
1. A system comprising: a host communication circuit that is adapted to be connected to a client communication circuit by means of a single signal wire, the host communication circuit being configured to perform a voltage modulation on the signal wire by generating a voltage modulated signal based on a reference clock signal; in a first period of a clock cycle of the reference clock signal, to generate the voltage modulated signal with a significant voltage change based on a clock edge of the reference clock signal, wherein the significant voltage change is present during the first period; in a second period of the clock cycle, to generate the voltage modulated signal with a voltage variation that is basically constant during said second period, wherein the clock cycle consists of the first period and the second period, and wherein the first period is significantly shorter than the second period; and to demodulate a current modulated signal received via the signal wire from a connected client communication circuit; and a client communication circuit that is adapted to be connected to the host communication circuit by means of a single signal wire, the client communication circuit being configured to generate a sync signal with one or more sync pulses, the generation of each sync pulse based on a detection of the significant voltage change within the voltage modulated signal received via the signal wire from the connected host communication circuit; to generate a client clock signal based on the sync pulses of the sync signal, the sync pulses determining the clock cycle of the reference clock signal of the connected host communication circuit, wherein the client clock signal has a higher frequency than the sync signal; and to perform a current modulation on the signal wire by generating the current modulated signal based on the client clock signal and on data to be transmitted from the client communication circuit to the connected host communication circuit, wherein a current modulation based on the data to be transmitted is performed only after a predetermined settling time after one of the sync pulses until the respective following sync pulse, for each clock cycle of the reference clock signal respectively the sync signal.