Patent ID: 9659140
Date: 2017-05-23
CPC Classifications: G06F

Claim:
1. A method of identifying a region of a design block of an integrated circuit for redesign, the method comprising: dividing the design block into grids, each of the grids including a corresponding number of logic elements; filtering, using a processor, each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria; identifying, using the processor, the region as a set of two or more of the grids based on a result of the filtering; and computing, using the processor, a power efficiency score (PES) for each of the total number (A) of the logic elements in each grid, wherein the PES is computed for each of the logic elements in each grid as: CDS_assignment_score being based on a minimum and maximum cell drive strength (CDS) for each of the logic elements of each of the grids, VT_assignment_score being based on a threshold voltage (VT) used for the logic element, slack_achievement_score being based on slack as compared with a target slack, and slew_achievement_score being based on slew as compared with a target slew.