Patent ID: 9716605
Date: 2017-07-25
CPC Classifications: H04L

Claim:
1. A method, comprising: receiving Ethernet frame streams in a first clock cycle; obtaining X data segments, wherein the X data segments are data segments of a first Ethernet frame stream in the first clock cycle, wherein the number of bits of each data segment in the X data segments is M, wherein M is an integer greater than 1, and wherein X is a positive integer; obtaining Y data segments, wherein the Y data segments are data segments of a second Ethernet frame stream in the first clock cycle, wherein the number of bits of each data segment in the Y data segments is M, and wherein Y is a positive integer; separately distributing X pieces of input data to X scrambling circuits, wherein the X scrambling circuits are in a one-to-one correspondence with the X pieces of input data; separately distributing Y pieces of input data to Y scrambling circuits, wherein the Y scrambling circuits are in a one-to-one correspondence with the Y pieces of input data; calculating concurrently, by the X scrambling circuits, scrambling results of the X data segments according to a scrambling polynomial and by separately using the X pieces of input data, wherein the X data segments are in a one-to-one correspondence with the X scrambling circuits, and wherein each scrambling circuit of the X scrambling circuits is configured to calculate concurrently a scrambling result of a binary sequence in which the number of bits is M; and calculating concurrently, by the Y scrambling circuits, scrambling results of the Y data segments according to the scrambling polynomial and by separately using the Y pieces of input data, wherein the Y data segments are in a one-to-one correspondence with the Y scrambling circuits, and wherein each scrambling circuit of the Y scrambling circuits is configured to calculate concurrently a scrambling result of a binary sequence in which the number of bits is M; wherein the X data segments comprise the first data segment to the X wherein the separately distributing X pieces of input data to X scrambling circuits comprises distributing the a distributing first data and second data to a first calculation circuit and a second calculation circuit respectively, wherein the a