Patent ID: 9735242
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A transistor device, comprising: a gate structure; an active region of a semiconducting substrate surrounded by an isolation region; source/drain regions disposed on opposing sides of said gate structure, wherein a gate width direction is defined in a direction extending between said source/drain regions and a gate length direction is defined in a direction perpendicular to said gate width direction along an axial length of said gate structure; a stepped conductive source/drain contact structure formed above and contacting one of said source/drain regions and having a first upper surface with a first height and a second upper surface with a second height greater than said first height, wherein said stepped conductive source/drain contact structure has a stepped configuration when viewed in cross-sectional view taken along through said stepped conductive source/drain contact structure in a direction corresponding to said gate width direction; a non-conductive structure positioned above and contacting said first upper surface and having a third upper surface coplanar with said second upper surface; a layer of insulating material positioned above said gate structure, said stepped conductive source/drain contact structure and said non-conductive structure; a conductive gate contact disposed in said layer of insulating material and being conductively coupled to said gate structure, wherein, in a plan view of said transistor device, said non-conductive structure is disposed on left and right sides of said conductive gate contact; and a source/drain contact disposed in said layer of insulating material and contacting said second upper surface of said source/drain contact structure.