Patent ID: 9640552
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor structure, said method comprising: forming semiconductor fins on a substrate, said semiconductor fins including a first semiconductor fin formed in a first device region and a second semiconductor fin formed in a second device region; anisotropically depositing a dielectric material on said substrate and said first and second semiconductor fins; removing said dielectric material from said second device region, while said dielectric material is protected under a mask layer in said first device region; removing said mask layer; and forming at least one gate structure across said first and second semiconductor fins, wherein a dielectric material layer is formed on a top surface of said substrate and dielectric material portions are formed on top surfaces of said first and second semiconductor fins by said anisotropically deposited dielectric material, and further comprising: performing an isotropic etch on said dielectric material in said first device region after removing said mask layer, wherein all dielectric material portions in said first device region are removed by said isotropic etch, and a lower portion of said dielectric material layer remains after said isotropic etch.