Patent ID: 9632786
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A method of executing instructions in a processor of a type including an auxiliary execution unit, the method comprising: receiving first and second instructions from an instruction stream, wherein the first and second instructions are members of an instruction set architecture defined for the processor, and wherein each instruction in the instruction set architecture includes a primary opcode portion and an operand portion; in response to receiving the first and second instructions: after receiving the first and second instructions, receiving a plurality of auxiliary instructions from the instruction stream, wherein a number of auxiliary instructions in the plurality of auxiliary instructions is equal to the count stored in the count register by the second instruction, wherein each of the plurality of auxiliary instructions includes a primary opcode portion that includes at least one bit used to decode an operand of such auxiliary instruction; and for each auxiliary instruction among the plurality of auxiliary instructions: