Patent ID: 9558791
Date: 2017-01-31
CPC Classifications: G11C,H01L

Claim:
1. A static random access memory (SRAM) device fabricated in a multi-layer semiconductor device structure, comprising: a first device layer; a first array of SRAM cells formed in the first device layer; a second device layer formed on the first device layer; a second array of SRAM cells formed in the second device layer; an inter-layer connection structure extending across the first device layer and the second device layer and configured to transmit data read from and data to be written to a target SRAM cell located in one of the first device layer and the second device layer; a plurality of first word lines formed in the first device layer and respectively coupled to the SRAM cells in the first device layer; a first word-line driver formed in the first device layer and coupled to the first word lines; a first layer decoder formed in the first device layer, coupled to the first word-line driver, and configured to activate the first word-line driver of the first device layer in response to an access signal indicating that the target SRAM cell is located in the first device layer, wherein the first word-line driver is configured to, in response to the activation thereof by the first layer decoder, activate a first word line associated with the target SRAM cell; a plurality of second word lines formed in the second device layer and respectively coupled to the SRAM cells in the second device layer; a second word-line driver formed in the second device layer and coupled to the second word lines; and a second layer decoder formed in the second device layer, coupled to the second word-line driver, and configured to activate the second word-line driver of the second device layer in response to the access signal indicating that the target SRAM cell is located in the second device layer, wherein the second word-line driver is configured to, in response to the activation thereof by the second layer decoder, activate a second word line associated with the target SRAM cell.