Patent ID: 9646960
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A system-on-chip device, comprising: a substrate with an active pattern; a gate electrode crossing the active pattern and extending in a first direction parallel to a top surface of the substrate; and a first metal layer electrically connected to the active pattern and the gate electrode, wherein: the first metal layer comprises: the first metal line comprises a first sidewall parallel to the second direction, the second metal line comprises a second sidewall parallel to the second direction, the first sidewall and the second sidewall face each other, the first sidewall has a length that is two or three times a minimum line width by a design rule for a layout, the third metal line comprises a third sidewall parallel to the second direction, the fourth metal line comprises a fourth sidewall parallel to the second direction, the third sidewall and the fourth sidewall face each other, the fourth sidewall has a length shorter than that of the first sidewall, the first sidewall and the second sidewall are spaced apart from each other by a first distance, and the third sidewall and the fourth sidewall are spaced apart from each other by a second distance greater than the first distance.