Patent ID: 9563727
Date: 2017-02-07
CPC Classifications: G01R,G06F

Claim:
1. A method of verifying a function of a derived clock signal in an integrated circuit hardware design, the derived clock signal being derived in the hardware design from a reference clock signal to have a particular duty cycle and period, the method comprising: counting, by at least one first state machine, a number of full or half cycles of a first clock signal that occur between a rising edge and a falling edge of a second clock signal, the second clock signal operating at a lower frequency than the first clock signal, wherein the faster of the reference clock signal and the derived clock signal is designated as the first clock signal, and the slower of the reference clock signal and the derived clock signal is designated as the second clock signal; counting, by at least one second state machine, a number of full or half cycles of the first clock signal that occur between a falling edge and a rising edge of the second clock signal; receiving counts from said at least one first and second state machines; verifying the duty cycle and the period of the derived clock signal by evaluating one or more assertions written in an assertion-based language that compare the received counts from said at least one first and second state machines to one or more predetermined numbers; and manufacturing an integrated circuit in accordance with the integrated circuit hardware design having the verified function.