Patent ID: 9572265
Date: 2017-02-14
CPC Classifications: H05K,Y10T

Claim:
1. Method for producing a circuit including a support which support includes a conductive layer and a dielectric film laminated together, the method including a step of gluing onto an upper face of the dielectric film and a subsequent step of perforating the dielectric film before being laminated with the conductive layer for form windows in the dielectric film so that the support forms at least one cavity having a bottom wall formed by the conductive layer and borders formed by the dielectric film, the method including the step consisting of an electronic component being placed against the bottom wall of said at least one cavity and being connected to the bottom wall, and the method including the step consisting of etching grooves in the conductive layer, wherein the step of etching the conductive layer is performed after the lamination of the conductive layer with the dielectric film with the aid of an etching solution and the method includes a preliminary step to the step of etching, which preliminary step consists of depositing a layer of protective material on the conductive layer in the bottom of said at least one cavity and on at least one part of the dielectric film forming the borders of said at least one cavity, which protective material is a liquid material capable of hardening and once hardened resistant to the etching solution used in the step of etching the conductive layer.