Patent ID: 9536872
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A semiconductor chip comprising: a semiconductor substrate comprising a major surface; a source/drain region and a substrate contact region disposed at the semiconductor substrate; a shallow trench isolation (STI) area disposed at the major surface and disposed at least partially between the source/drain region and the substrate contact region, wherein the source/drain region and the substrate contact region are part of a transistor, and wherein the transistor is contacted through the source/drain region and the substrate contact region; and at least one capacitor at least partially buried in the STI area, wherein the at least one capacitor comprises a plurality of capacitors arranged such that the capacitors are completely buried within the STI area, wherein plates of the capacitors are oriented in a plane perpendicular to the major surface of the semiconductor substrate, and the capacitors are connected to each other in a line-to-line configuration, wherein all outer surfaces of the plates of the capacitors are disposed beneath the major surface of the semiconductor surface.