Patent ID: 9640568
Date: 2017-05-02
CPC Classifications: G02F,G03F,H01L

Claim:
1. A mask set configured to manufacture a pixel unit including a thin-film transistor (TFT) and a data line, comprising: a first mask including an active layer pattern portion configured to form an active layer of the TFT; a second mask including a gate electrode pattern portion configured to form a gate electrode of the TFT; and a third mask including a source electrode pattern portion, a drain electrode pattern portion and a data line pattern portion respectively configured to form a source electrode and a drain electrode of the TFT and the data line, wherein when the first mask, the second mask and the third mask are aligned and overlapped with each other, a maximum size value of an overlapped area between the active layer pattern portion of the first mask and the drain electrode pattern portion of the third mask in the direction parallel to the data line pattern portion is less than a size value of one side, overlapped with the data line pattern portion, in an overlapped area between the active layer pattern portion of the first mask and the source electrode pattern portion of the second mask; wherein the active layer pattern portion of the first mask is a first isosceles trapezoid; and when the first mask, the second mask and the third mask are aligned and overlapped with each other, bases of the first isosceles trapezoid are disposed in the direction parallel to the data line pattern portion; an upper base of the first isosceles trapezoid is disposed in an overlapped area between the drain electrode pattern portion and the first isosceles trapezoid; and a lower base of the first isosceles trapezoid is disposed in an overlapped area between the source electrode pattern portion and the first isosceles trapezoid.