Patent ID: 9548369
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a substrate comprising a first region and a second region; a first stack structure disposed on the substrate of the first region and comprising a plurality of first conductor layers and a plurality of first dielectric layers, wherein the first conductor layers and the first dielectric layers are stacked alternately; a plurality of second stack structures disposed on the substrate of the second region and each comprising a plurality of second conductor layers and a plurality of second dielectric layers, wherein the second conductor layers and the second dielectric layers are stacked alternately; and a bottom dielectric structure disposed between the substrate and the first stack structure and between the substrate and the second stack structures, wherein the bottom dielectric structure comprises a body part, a first protrusion part, and a plurality of second protrusion parts, wherein the first protrusion part extends from the body part and is located between the body part and the first stack structure, and the second protrusion parts extend from the body part and are respectively located between the body part and the second stack structures, wherein a sidewall of the first stack structure and a sidewall of the second stack structure have a concave-and-convex surface respectively.