Patent ID: 9633687
Date: 2017-04-25
CPC Classifications: G01R,G11B,H04L

Claim:
1. An apparatus, comprising: a loop filter receiving a plurality of input signals, wherein each of the input signals is based on a different timing error detector output signal; a plurality of read channels; a plurality of interpolation filters, each of the interpolation filters in communication with a corresponding one of the read channels; and an array of transducers, wherein each of the transducers is in communication with a corresponding one of the read channels; wherein the loop filter processes the plurality of input signals, and outputs a different total phase signal for each received input signal; wherein each of the interpolation filters samples the corresponding read channel based on one of the total phase signals output by the loop filter; wherein the loop filter processes the plurality of input signals by calculating a phase estimate of the samples, and a skew estimate of the samples, relative to written data.