Patent ID: 9553571
Date: 2017-01-24
CPC Classifications: H03K

Claim:
1. A device comprising: an interpolator including: a counter stage having an input terminal configured to receive the first clock signal, the counter stage being configured to count a number of clock cycles of the first clock signal, apply a modulo-M function to the number of clock cycles, and output a first number that is an outcome of applying the modulo-M function to the number of clock cycles, wherein M is an integer representing a desired ratio of the first clock frequency to the second clock frequency; a memory stage coupled to the counter stage and configured to receive the first number and store the first number under control of the second clock signal, the memory is further configured to receive a second number, which was output by the rounding counter stage prior to the first number, and store the second number under control of the second clock signal; a comparator stage coupled to an output of the memory stage and configured to receive the first and second numbers and determine if the first and second numbers are different from each other; and a reset stage coupled to an output of the comparator stage and configured to reset at least one of the derivator stage and the integrator stage if the first and second numbers are different from each other.