Patent ID: 9685938
Date: 2017-06-20
CPC Classifications: H01L,H03K

Claim:
1. A maximum-voltage selection circuit comprising: multiple inputs, each for receiving a different input voltage; an output for delivering the highest of the input voltages; and a voltage selection circuit that: wherein for each and every unique combination of two of the multiple inputs, the voltage selection circuit comprises: an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output, the enhancement mode FET also having a gate; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET, the gate of the depletion mode FET being connected to the output; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output, the additional enhancement mode FET having a gate; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs.