Patent ID: 9665112
Date: 2017-05-30
CPC Classifications: G05F

Claim:
1. A regulator circuit having a cascaded topology, comprising: a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and, using a loop gain much greater in magnitude than unity in a specified frequency range from about 10 kilohertz (kHz) to about 10 megahertz (MHz), configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node; and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a different second loop bandwidth and, using a loop gain much less in magnitude than unity in the specified frequency range from about 10 kilohertz (kHz) to about 10 megahertz (MHz), configured to provide a regulated second output voltage to an output node.