Patent ID: 9646663
Date: 2017-05-09
CPC Classifications: G11C

Claim:
1. A circuit, comprising: a plurality of memory banks arranged in a plurality of rows and a plurality of columns of memory building blocks, each of the plurality of memory banks comprising at least one memory cell, a column line tracking loop that has a first end and a second end and traverses at least a portion of the plurality of rows, and/or a row line tracking loop that has a first end and a second end and traverses at least a portion of the plurality of columns; and a tracking circuit configured to receive a first edge of a first internal clock signal, cause the first edge of the first internal clock signal to be propagated from the first end to the second end of the column line tracking loop and/or from the first end to the second end of the row line tracking loop and cause a second edge of the first internal clock signal when receiving the propagated first edge of the first internal clock signal; a time division multiplexing (TDM) circuit coupled to the tracking circuit and configured to receive an external clock signal and generate the first internal clock signal that has at least a first pulse and a second pulse during a clock cycle of the external clock signal,