Patent ID: 9627540
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate; patterning the stacked structure into a fin structure; forming an isolation insulating layer over the fin structure; forming a cover layer over the isolation insulating layer; patterning the cover layer so as to form an opening and remaining boundary portions; recessing the isolation insulating layer through the opening to partially expose the fin structure, end portions of the fin structure being buried in the isolation insulating layer; removing the second semiconductor layers in the partially exposed fin structure, so that the first semiconductor layers are exposed; forming a sacrificial gate structure over the exposed fin structure where the second semiconductor layers are removed, such that the sacrificial gate structure covers a part of the fin structure while remaining parts of the fin structure remain exposed, the remaining parts being source/drain regions and the part of the fin structure covered by the sacrificial gate structure being a channel region; forming epitaxial source/drain structures on the exposed first semiconductor layers in the source/drain regions so that the epitaxial source/drain structures wrap around each of the exposed first semiconductor layers in the source/drain regions; removing the sacrificial gate structure to expose the channel region of the fin structure; and forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in the channel region.