Patent ID: 9685382
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the semiconductor substrate including a PMOS region and an NMOS region, and a plurality of gate structures forming in the PMOS region and the NMOS region; depositing a spacer material layer overlying the plurality of gate structures and the surface of the semiconductor substrate; forming a first photoresist layer to cover the PMOS region and to expose the NMOS region; etching the exposed portion of the spacer material layer to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region; removing the first photoresist layer; depositing a sacrificial surface layer, the sacrificial layer overlying the spacer material layer covering the PMOS region, the first sidewall spacers, and the exposed surface of the semiconductor substrate; forming a second photoresist layer to cover the NMOS region and to expose the PMOS region; etching the sacrificial material layer and the spacer material layer in the exposed PMOS region to form second sidewall spacers on the sidewalls of the gate structure in the PMOS region; removing the second photoresist layer; then subsequently forming stress layers in source/drain regions in the PMOS region; forming a cover layer on the stress layers; and then subsequently removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.