Patent ID: 9640543
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a plurality of source-side half channels positioned in a first region and arranged in first to 2Nth rows, wherein N is an integer equal to or greater than 2; a plurality of first drain-side half channels positioned in a second region at one side of the first region and arranged in first to Nth rows; a plurality of second drain-side half channels positioned in a third region at the other side of the first region and arranged in first to Nth rows; a plurality of first pipe channels suitable for connecting the first to Nth rows of source-side half channels to the first to Nth rows of first drain-side half channels, respectively; and a plurality of second pipe channels suitable for connecting (N+1)th to 2Nth rows of source-side half channels to the first to Nth rows of second drain-side half channels, respectively, wherein each of the second drain-side half channels is offset from centers of the second drain-side half channels in adjacent rows.