Patent ID: 9741702
Date: 2017-08-22
CPC Classifications: H01L,H03K,H05K

Claim:
1. A method of forming an electronic component, comprising: providing a first transistor encased in a first package, the first package comprising a first conductive portion having a first area, the first transistor being mounted over the first conductive portion; providing a second transistor encased in a second package, the second package comprising a second conductive portion having a second area, the second transistor being mounted over the second conductive portion; providing a substrate comprising an insulating layer between a first metal layer and a second metal layer, the first metal layer being on a first side of the substrate and the second metal layer being on a second side of the substrate; mounting the first package on a first side of the substrate with the first conductive portion being electrically connected to the first metal layer; and mounting the second package on a second side of the substrate with the second conductive portion being electrically connected to the second metal layer; wherein the first package is opposite the second package, with at least 50% of the first area of the first conductive portion being opposite the second area of the second conductive portion.