Patent ID: 9698054
Date: 2017-07-04
CPC Classifications: H01L

Claim:
1. A method for fabricating a p-type field effect transistor, said method comprising: providing a dummy gate stack over a substrate; recessing the substrate to form source/drain (S/D) recess cavities in the substrate and adjacent to the dummy gate stack; selectively growing a strained material in the S/D recess cavities; performing a thermal process on the grown strained material to form source/drain (S/D) extensions conformably surrounding the S/D recess cavities; removing the dummy gate stack to form an opening exposing the substrate under the dummy gate stack; recessing the substrate exposed in the opening to form a channel recess cavity spaced apart from the S/D recess cavities; and forming a gate stack in the opening, said gate stack having a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity.