Patent ID: 9666284
Date: 2017-05-30
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device, comprising: a memory cell array including a first block and a second block, the first block including a first memory string, a second memory string, and a third memory string, the second block including a fourth memory string, a fifth memory string, and a sixth memory string, each of the first to third memory strings including a first selection transistor and a plurality of first memory cells connected in series, each of the fourth to sixth memory strings including a second selection transistor and a plurality of second memory cells connected in series; a plurality of first transistors connected to gates of the plurality of first memory cells of the first to third memory strings; a second transistor connected to a gate of the first selection transistor of the first memory string; a third transistor connected to a gate of the first selection transistor of the second memory string; a fourth transistor connected to a gate of the first selection transistor of the third memory string; a plurality of fifth transistors connected to gates of the plurality of second memory cells of the fourth to sixth memory strings; a sixth transistor connected to a gate of the second selection transistor of the fourth memory string; a seventh transistor connected to a gate of the second selection transistor of the fifth memory string; and an eighth transistor connected to a gate of the second selection transistor of the sixth memory string, wherein gates of the first transistors, the second transistor, the third transistor, the fourth transistor, the fifth transistors, the sixth transistor, the seventh transistor and the eighth transistor are electrically connected to a first line.