Patent ID: 9632794
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. An integrated circuit device comprising: a bus controller; a clock generation circuit configured to supply and stop supplying clock to a host processor; and a subprocessor connected to the host processor through the bus controller, the subprocessor including: the host processor setting a program counter value indicating a storage destination of the subprocessor program and a processing start command for a processing of the subprocessor to the register unit, the command fetch unit fetching a first command designated by the program counter value, the command decoding unit decoding the first command, the operation unit performing the command execution processing, the bus controller being connected to the subprocessor and the host processor, the bus controller performing bus control between a memory in which a host processor program and the subprocessor program are stored, the host processor, and the subprocessor, when a processing end command of the subprocessor program is decoded, the subprocessor issuing a processing complete signal, upon the host processor issuing the processing start command and the processing of the subprocessor being executed by the subprocessor, the host processor issuing a stop signal to the clock generation circuit to stop the clock generation circuit from supplying clock to the host processor, and the clock generation circuit, after stopping supplying clock, resuming the supply of clock to the host processor upon receiving the processing complete signal issued from the subprocessor.