Patent ID: 9728550
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A semiconductor memory device, comprising: a stacked body including a plurality of insulating portions and a plurality of conductive films, each of the plurality of insulating portions and each of the plurality of conductive films being alternately stacked, a trench being formed in the stacked body, the trench extending in a first direction, and each of the conductive films being divided by the trench; a plurality of semiconductor pillars provided in the trench and extending in a stacking direction of the insulating portions and the conductive films; a plurality of insulating layers provided around the semiconductor pillars; and an insulating member provided between the insulating layers in the trench, the plurality of semiconductor pillars and the insulating member being alternately arranged in the first direction in the trench, a pair of memory transistors being provided so as to correspond to regions of each of the semiconductor pillars, the regions facing a pair of side surfaces of the trench, the side surfaces extending along the first direction, the pair of memory transistors being disposed at an intersection between one of the semiconductor pillars and one of the conductive films, the pair of memory transistors being arranged in a second direction intersecting with a plane including the first direction and the stacking direction.