Patent ID: 9710622
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. A processor comprising: hardware circuitry further comprising: an enclave page cache to store a first secure control structure data in a first secure storage area allocated to a corresponding first secure enclave of a parent process, and to store a second secure control structure data in a second secure storage area allocated to a corresponding second secure enclave of a child process; a decode stage to decode a first instruction for execution by the processor, the first instruction specifying the second secure storage area as an operand; and one or more execution units, responsive to the decoded first instruction, to: copy the first secure control structure data from the first secure storage area to the second secure storage area; initialize the second secure control structure data with a unique enclave identifier associated with the child process; and record a second secure control structure link to the first secure control structure data in the second secure control structure data, wherein the second secure control structure data in the second secure storage area allocated to the corresponding second secure enclave of the child process cannot be used by an application unless the second secure control structure link to the first secure control structure data is removed from the second secure control structure data.