Patent ID: 9601379
Date: 2017-03-21
CPC Classifications: B82Y,H01L

Claim:
1. A method of forming a nanowire device comprising multiple nanowires, a channel region and a plurality of source/drain regions, the method comprising: forming a plurality of stacked substantially un-doped nanowire structures above a semiconductor substrate, said plurality of stacked substantially un-doped nanowire structures comprising a first plurality of nanowires made of a first semiconductor material and a second plurality of nanowires made of a second semiconductor material that is different than said first semiconductor material; forming a sacrificial structure around said plurality of stacked substantially un-doped nanowire structures at a location that corresponds to said channel region of said device; forming a layer of insulating material above and adjacent said plurality of stacked substantially un-doped nanowire structures and proximate said sacrificial structure; removing said sacrificial structure to define a cavity that exposes said plurality of stacked substantially un-doped nanowire structures within said cavity; performing a selective etching process through said cavity to remove said second plurality of nanowires from said channel region and said source/drain regions of said device while leaving said first plurality of nanowires in position; forming a metal conductive source/drain contact structure in each of said source drain regions, wherein each of said metal conductive source/drain contact structures is positioned all around said first plurality of nanowires positioned in said source/drain region; and forming a gate all around gate structure that is positioned all around each of said first plurality of nanowires positioned in said channel region of said device.