Patent ID: 9691477
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. A resistive memory system comprising: a memory device including a resistive memory cell array; and a controller generating write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states of a memory cell, wherein: the input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the number of memory cells in the erase state and the number of memory cells in other programming states, a resistance level of the first programming state is highest among resistance levels of the plurality of programming states, and a resistance level of the second programming state is second highest among the resistance levels of the plurality of programming states, and the controller performs the encoding in response to the controller determining that the input data is to be stored in the memory cell for a preset first reference period of time or longer.