Patent ID: 9741299
Date: 2017-08-22
CPC Classifications: G09G

Claim:
1. A display panel comprising: a plurality of gate lines and a plurality of data lines disposed to cross each other and define a plurality of sub-pixel regions; and a plurality of sub-pixels disposed in the plurality of sub-pixel regions and configured to share one of the data lines adjacent thereto, wherein the sub-pixels sharing the same data line are arranged in a shape of zigzagging along a vertical direction by four sub-pixels, wherein each sub-pixel region among the plurality of sub-pixel regions includes a thin-film-transistor-inclusive sub-pixel region connected to pixel electrodes in first, second and third sub-pixels adjacent to the thin-film-transistor-inclusive sub-pixel region, wherein the thin-film-transistor-inclusive sub-pixel region includes thin film transistors connected to the first, second and third sub-pixels, respectively, and wherein the thin film transistors include: wherein the first sub-pixel region is adjacent to the thin-film-transistor-inclusive sub-pixel region and disposed along a first direction directed away from the thin-film-transistor-inclusive sub-pixel region, the second sub-pixel region is adjacent to the thin-film-transistor-inclusive sub-pixel region and disposed along a second direction that is perpendicular to the first direction and directed away from the thin-film-transistor-inclusive sub-pixel region, and the third sub-pixel region is adjacent to the second sub-pixel region and disposed along a third direction that is opposite to the first direction and directed away from the second sub-pixel region.