Patent ID: 9542258
Date: 2017-01-10
CPC Classifications: G06F

Claim:
1. A method for determining voltage thresholds in a memory device of a non-volatile memory array, the memory device comprising one or more memory cells, the method comprising: performing a first read operation of the memory device using a first voltage threshold to obtain a first plurality of values; identifying, in the first plurality of values, a first number of bit errors of a first type and a first number of bit errors of a second type; performing a second read operation of the memory device using a second voltage threshold to obtain a second plurality of values, the second voltage threshold being different from the first voltage threshold; identifying, in the second plurality of values, a second number of bit errors of the first type and a second number of bit errors of the second type; performing a first linear interpolation process based on the first and second number of bit errors of the first type, the first voltage threshold, and the second voltage threshold; performing a second linear interpolation process based on the first and second number of bit errors of the second type, the first voltage threshold, and the second voltage threshold; and determining an error-minimizing voltage threshold that reduces bit errors during reads of the memory device based, at least in part, on the first linear interpolation process and the second linear interpolation process, wherein the method is performed under control of a controller.