Patent ID: 9702924
Date: 2017-07-11
CPC Classifications: G01R

Claim:
1. A method comprising: measuring a first set of values of a current Idd passing through each individual field effect transistor (FET) in a plurality of FETs, the plurality of FETs comprising an array of devices under test (DUT) located in a single testing circuit; simultaneously applying a stress voltage in parallel to one of drains and sources of all of the plurality of FETs and at least one signal to gates of all of the plurality of FETs, wherein the stress voltage and the at least one signal comprise a series of short periodic pulses applied during a low duty cycle; turning the at least one signal off in the gates of all of the plurality of FETs; turning on individual gates of individual FETs of the plurality of FETs one by one in succession such that the current Idd is conducted through each individual FET; measuring a second set of values of the current Idd through each individual FET in the plurality of FETs at a time when the gates of each individual FET are turned on; and comparing the first set of values of the current Idd to the second set of values of the current Idd to determine whether the second set of values is different from the first set of values, wherein a difference between the first set of values and the second set of values is an indication of device degradation in each individual FET of the plurality of FETs.