Patent ID: 9711189
Date: 2017-07-18
CPC Classifications: G11C

Claim:
1. A calibration buffer circuit coupled to a first input buffer and a first reference voltage select circuit of a data buffer circuit, the first reference voltage select circuit coupled to a first voltage divider circuit, the calibration buffer circuit monitoring a number of transitions of an output of a second buffer circuit contemporaneously with transmission of the output of the first input buffer of the data buffer circuit, the calibration buffer circuit comprising: the second input buffer coupled to a data input and a test reference voltage, with the test reference voltage derived separate from a reference voltage; an eye monitor circuit coupled to the second input buffer, the eye monitor circuit generating an output signal representative of a timing of the transitions of the output of the second input buffer with respect to a clock signal; a calibration control circuit coupled in series with the eye monitor circuit, the calibration control circuit receiving the output signal from the eye monitor circuit, and the calibration control circuit analyzing the output signal from the eye monitor circuit and providing a selection signal to the first reference voltage select circuit of the data buffer circuit, wherein the selection signal corresponds to the level of the reference voltage that produces a maximum horizontal width of an eye of the output of the first input buffer of the data buffer circuit based on a calibration of the test reference voltage; a second reference voltage select circuit coupled to the calibration control circuit, the second reference voltage select circuit transmitting the test reference voltage to the second input buffer; and a second voltage divider circuit coupled to the second reference select circuit, the second voltage divider circuit having a series of resistors equivalent to the first voltage divider circuit.