Patent ID: 9614060
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of fabricating a nanowire transistor, comprising: forming a fin structure having a first end and an opposing second end on a microelectronic substrate, wherein the fin structure comprises at least one sacrificial material layer alternating with at least one channel material layer; forming a first underlayer etch stop structure to abut the fin structure first end; forming a second underlayer etch stop structure to abut the fin structure second end; forming a source structure proximate the fin structure first end, wherein the first underlayer etch stop structure is disposed between the source structure and the fin structure first end and disposed between the entire source structure and the microelectronic substrate; and forming a drain structure proximate the fin structure second end, wherein the second underlayer etch stop structure is disposed between the drain structure and the at least one nanowire second end and disposed between the entire drain structure and the microelectronic substrate; and selectively removing the at least one sacrificial material layer from the fin structure, wherein the remain at least one channel material layer forms at least one channel nanowire.