Patent ID: 9690589
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A processor for deactivating an active operand, the active operand being an instruction accessible architecturally defined operand, wherein access to a deactivated operand need not return values previously stored to the operand, the processor comprising: an instruction fetcher, an instruction decoder and at least one execution unit, the processor configured to perform a method comprising; executing, by a processor, a first instruction and a second instruction, wherein the second instruction is a next sequential instruction to the first instruction in program order, the second instruction comprising an opcode field having an opcode value, the second instruction having an associated operand, wherein the first instruction indicates that the associated operand of the second instruction is a last-use operand to be deactivated, the execution comprising: determining, from the first instruction, a last-use of the associated operand of the second instruction; performing an opcode defined function using the associated operand of the second instruction; and placing the associated operand in a deactivated state.