Patent ID: 9685344
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device comprising: patterning a hardmask layer over a substrate comprising a major surface; etching the substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches has a first width and extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches has a second width less than first width and extends downward from the substrate major surface to a second height greater than the first height; forming a first isolation structure partially filling each first trench of the plurality of first trenches; and forming a second isolation structure partially filling each second trench of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height is substantially equal to a difference between a height of the second isolation structure and the second height.