Patent ID: 9741847
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of forming a vertically oriented transistor device, comprising: forming a semiconductor structure above a doped well region defined in a semiconductor substrate, said semiconductor structure having a long axis that is oriented approximately vertical to an upper surface of said substrate, said semiconductor structure comprising a lower source/drain region and an upper source/drain region, at least a portion of which is positioned vertically above said lower source/drain region, wherein said lower source/drain region physically contacts said upper surface of said substrate; forming a counter-doped isolation region in said substrate, wherein said counter-doped isolation region is doped opposite to said doped well region, and wherein said counter-doped isolation region separates and isolates an upper portion of said doped well region that is positioned above said counter-doped isolation region from a lower portion of said doped well region that is positioned below said counter-doped isolation region; forming a metal silicide region in said isolated upper portion of said doped well region above said counter-doped isolation region, wherein said metal silicide region is in physical contact with said lower source/drain region; and forming a lower source/drain contact structure that is conductively coupled to said metal silicide region.