Patent ID: 9720610
Date: 2017-08-01
CPC Classifications: G06F,G11C

Claim:
1. A memory device comprising: a plurality of memory modules arranged in a first direction, each of said memory modules including a plurality of memory units arranged in the first direction, each of said memory units of said memory modules including a plurality of memory cell groups which are arranged in a second direction different from the first direction, and each of which includes at least one memory cell for storing data therein, a plurality of first bit lines, each of which is coupled to said at least one memory cell of a respective one of said memory cell groups, a second bit line for transmitting to-be-read data, and a plurality of first controllable circuits, each of which has an input terminal coupled to a respective one of said first bit lines, an output terminal coupled to said second bit line, and a control terminal; and a plurality of first control line groups, each of said first control line groups including a plurality of first control lines, each of said first control line groups corresponding to a plurality of memory cell groups along the first direction, each of said first control lines of said first control line groups being coupled to said control terminal of a corresponding one of said first controllable circuits of at least one of said memory units of each of said memory modules; wherein each of said memory module outputs data transmitted from one of the second bit lines corresponding to a selected memory units; wherein, each of said first controllable circuits of said memory units of said memory modules is operable between an output enable state and an output disable state based on a voltage at said control terminal of a corresponding one of said first controllable circuits, and outputs, at said output terminal, a voltage associated with a voltage at said input terminal when operating in the output enable state; or wherein, each of said first controllable circuits of said memory units of said memory modules is operable between the output enable state and the output disable state based on the voltage at said input terminal and the voltage at said control terminal, and outputs a predetermined reference voltage at said output terminal when operating in the output enable state; wherein said plurality of first bit lines is not directly connected to said second bit line.