Patent ID: 9741845
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A device comprising: a substrate having a high voltage (HV) device region, wherein the HV device region is defined with first and second device isolation regions and an internal dielectric region, and wherein the device isolation regions and internal dielectric region are shallow trench isolation (STI) regions; a HV transistor disposed in the HV device region, wherein the HV transistor comprises a drift well disposed in the substrate, wherein the drift well encompasses the drain region and extends under a portion of the gate; a body well disposed in the substrate, wherein the body well encompasses the source region and extends laterally toward the drift well; and at least one buried RESURF region disposed within the drift well, wherein the at least one buried RESURF region comprises a first buried RESURF region which is disposed under the internal dielectric region, wherein the first buried RESURF region is an extended buried RESURF region which comprises