Patent ID: 9741424
Date: 2017-08-22
CPC Classifications: G06F,G11C

Claim:
1. A memory controller for controlling a dynamic random access memory (DRAM), the memory controller comprising: first and second buffers to output first and second clock signals to the DRAM, respectively, the first and second clock signals having different cycle times and requiring respective first and second propagation time intervals to propagate from the memory controller to the DRAM; a first transmit block to output two bits of address information onto each conductor of a first plurality of external conductors during a cycle time of the first clock signal; a second transmit block to output two bits of data in succession onto each conductor of a second plurality of external conductors during a cycle time of the second clock signal; and adjustment circuitry to offset a phase of one of the first and second clock signals from a phase of the other to compensate for a difference between the first and second propagation time intervals.