Patent ID: 9678716
Date: 2017-06-13
CPC Classifications: G06F

Claim:
1. An apparatus comprising: processing circuitry to perform an absolute difference operation to generate an absolute difference value in response to a first operand and a second operand, wherein the first operand, the second operand and the absolute difference value each comprise at least one data element having a current data element size selected from a plurality of data element sizes, and each data element of the absolute difference value represents an absolute difference between corresponding data elements of the first and second operands; the processing circuitry comprising: an adding stage to perform at least one addition using corresponding portions of the first operand and the second operand to generate at least one intermediate value, and to generate status information in dependence on said at least one addition, wherein each portion comprises a whole or part of a data element having said current data element size; an inverting stage to selectively invert selected bits of the at least one intermediate value to convert the at least one intermediate value into at least one corresponding portion of the absolute difference value; and control circuitry responsive to the current data element size and said status information to generate control information identifying said selected bits of the at least one intermediate value.