Patent ID: 9653175
Date: 2017-05-16
CPC Classifications: G11C,H01L

Claim:
1. A method comprising: performing a select gate to select gate stress operation on a first select gate line and a second select gate line of a non-volatile memory circuit comprising a memory array that includes a plurality of memory cells coupled in series between one or more drain select gates and one or more source select gates, the first select gate line coupled to a first one of the one or more drain select gates and the one or more source select gates, and the second select gate line coupled to a second one of the one or more drain select gates and the one or more source select gates, the select gate to select gate stress operation including applying a set of stress voltage levels to the first and second select gate lines to thereby introduce a voltage differential therebetween; and subsequently performing a defect determination operation on the first and second select gate lines to determine leakage therebetween.