Patent ID: 9686033
Date: 2017-06-20
CPC Classifications: H04J,H04L,H04W

Claim:
1. A method for separating clock recovery for synchronous communication, the method comprising: receiving, at a customer premises equipment (CPE) device, an incoming signal, through a metro Ethernet network, for pseudowire communication; separating the incoming signal into a first signal and a second signal; ordering packets within the first signal in a first register, wherein ordering the packets comprises reordering one or more packets that arrive out of order; extracting a clock signal from the second signal in a second register to generate a modified clock signal; accounting for a processing delay in generating the modified clock signal; communicating the first signal utilizing the modified clock signal; and disciplining a clock utilizing the modified clock signal after accounting for the processing delay in generating the modified clock signal, wherein the disciplining is performed for ticks of a reference clock encoded in the incoming signal, and wherein the disciplining is performed out of phase with the first signal in response to the processing delay.