Patent ID: 9704579
Date: 2017-07-11
CPC Classifications: G11C

Claim:
1. A non-volatile semiconductor memory device, comprising a control circuit, the control circuit performing a data erasure by applying predetermined erase voltages to predetermined regions of a memory cell array including memory cells disposed on each intersection of a plurality of word lines and a plurality of bit lines, and the non-volatile semiconductor memory device is characterized by: the control circuit applying the erase voltages to the memory cells to erase data by applying word line voltages different to each other to even-numbered word lines and odd-numbered word lines of the memory cell array except to an edge part thereof, and by applying a voltage different to the word line voltages to the word lines in the edge part of the memory cell array, wherein the word lines of the edge part of the memory cell array is at least one word line adjacent to a selection gate line or a dummy word line at both sides, wherein the control circuit performing a verification of the data erasure in different verify conditions to the memory cells of even-numbered bit lines and the memory cells of odd-numbered bit lines, and wherein the word line voltages different to each other are determined based on threshold value voltages measured while data erasure in a wafer test of the non-volatile semiconductor memory device.