Patent ID: 9652577
Date: 2017-05-16
CPC Classifications: G06F

Claim:
1. A method of utilizing a pre-marked circuit element object library to create an integrated circuit, the method comprising: inserting a first circuit element object into a schematic design, wherein the first circuit element object comprises a plurality of first terminals, and wherein each of the first terminals has one of a plurality of first pre-assigned voltage values; connecting each of the first terminals to one or more second terminals, wherein each of the one or more second terminals correspond to one or more second circuit element objects; generating a layout design from the schematic design in response to determining that the first pre-assigned voltage value of each of the first terminals matches a second pre-assigned voltage value of the one or more second terminals to which it is connected; determining whether the layout design passes or fails at least one of the one or more verification tests; replacing the first circuit element object with a third circuit element object in the layout design, in responses to a determination that the layout design fails the at least one of the one or more verification tests, wherein the third circuit element object comprises at least one of a plurality of third pre-assigned voltage values that is different than at least one of the plurality of first pre-assigned voltage values; generating mask layer data in response to a determination that the layout design passes the one or more verification tests, wherein the mask layer data is configured to generate a plurality of masks for construction of an integrated circuit corresponding to the schematic design.