Patent ID: 9689924
Date: 2017-06-27
CPC Classifications: G01R,G11C

Claim:
1. An integrated circuit (IC) comprising: at least one first group comprising a plurality of first portions to be tested, each of said plurality of first portions having respective first test circuits; and at least one second group comprising at least one second portion to be tested, the at least one second portion having at least one respective second test circuit; said at least one first and second groups being configured so that in use said first test circuits are configured to run in parallel with said at least one second test circuit, and said first test circuits are configured to run serially; wherein each of said first test circuits and at least one second test circuit comprises an output node configured to output a first output signal as a test completed output signal and otherwise a second output signal; and wherein said output node is coupled to an associated input node of a subsequent test circuit.