Patent ID: 9535696
Date: 2017-01-03
CPC Classifications: G06F

Claim:
1. A computer implemented method for handling outstanding cache miss prefetches, the method comprising: recognizing by a processor pipeline that a prefetch canceling instruction is being executed, wherein the prefetch canceling instruction has been inserted immediately after or before a transaction in which the transaction is known in advance to have a likelihood of utilizing a predefined amount of hardware transactional support structures; in response to recognizing that the prefetch canceling instruction is being executed, evaluating all outstanding prefetches according to a criterion as set forth by the prefetch canceling instruction in order to select qualified prefetches; in response to evaluating, communicating with a cache subsystem to cause canceling of the qualified prefetches that fit the criterion, wherein the prefetch canceling instruction cancels the qualified prefetches that are not linked with any pending instructions; and in response to successful canceling of the qualified prefetches, preventing a local cache from being updated from the qualified prefetches.