Patent ID: 9543031
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A semiconductor device, comprising: memory cells; an operation circuit suitable for performing a first read operation using a first read voltage on the memory cells included in a cell distribution, the first read operation dividing the cell distribution into a first cell distribution and a second cell distribution based on the first read voltage; and a check circuit suitable for comparing the number of memory cells included in the first cell distribution and the number of memory cells included in the second cell distribution, wherein the operation circuit selects a second read voltage based on a result of the comparison, and performs a second read operation using the second read voltage on the memory cells, and wherein, when the result of the comparison indicates the number of memory cells included in the first cell distribution being greater than the number of memory cells included in the second cell distribution, the second read operation divides the second cell distribution into two cell distributions based on the second read voltage.