Patent ID: 9589953
Date: 2017-03-07
CPC Classifications: H01L,H01R,H02M

Claim:
1. An integrated circuit comprising: an emitter/distributed diode electrode layer of a semiconductor material of a first conductivity type; a base region extending into the emitter/distributed diode electrode layer, wherein the base region is of a second conductivity type opposite the first conductivity type, wherein the base region has a first depth at its periphery; a plurality of collector regions extending into the base region, wherein the plurality of collector regions are of the first conductivity type; a plurality of distributed diode diffusion regions extending into the emitter/distributed diode electrode layer, wherein the plurality of distributed diode diffusion regions are of the second conductivity type, wherein the plurality of distributed diode diffusion regions are disposed in a two-dimensional array across the integrated circuit, wherein each of the distributed diode diffusion regions is separated from the base region by a respective part of the emitter/distributed diode electrode layer, and wherein each of the distributed diode diffusion regions has a second depth that is greater than the first depth of the base region; a first metal electrode that is coupled to the plurality of collector regions and is coupled to the plurality of distributed diode diffusion regions, wherein the first metal electrode is not coupled to the base region; a plurality of insulation features, wherein the first metal electrode is separated from the base region and from the emitter/distributed diode electrode layer by the plurality of insulation features; a second metal electrode that is coupled to the base regions; and a third metal electrode that is electrically coupled to the emitter/distributed diode electrode layer.