Patent ID: 9601499
Date: 2017-03-21
CPC Classifications: G11C,H01L

Claim:
1. A one time programmable (OTP) memory cell, comprising: a substrate structure; a shallow trench insulation area adjoining the substrate structure; a select gate transistor formed on the substrate structure, the select gate transistor having a first gate terminal, a first drain terminal, and a first source terminal; a following gate transistor formed on the substrate structure, the following gate transistor having a second gate terminal, a second drain terminal, and a second source terminal coupled to the first drain terminal; an antifuse varactor formed on the substrate structure, the antifuse varactor having a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal; and a dummy transistor partially formed on the substrate structure, the dummy transistor having a fourth gate terminal, and a fourth source terminal coupled to the third drain terminal; wherein a part of the fourth gate terminal is formed above the shallow trench insulation area.