Patent ID: 9679629
Date: 2017-06-13
CPC Classifications: G11C,H01L

Claim:
1. A memory device comprising: a memory cell comprising: a first wiring; a second wiring; a first switch; a second switch; and a second capacitor, wherein one of a source and a drain of the first transistor is electrically connected to the first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the first capacitor is electrically connected to the gate of the first transistor, wherein a first terminal of the first switch is electrically connected to the second wiring, wherein a second terminal of the first switch is electrically connected to a first electrode of the second capacitor, wherein a first terminal of the second switch is electrically connected to the second wiring, and wherein a second terminal of the second switch is electrically connected to a second electrode of the second capacitor.