Patent ID: 9684599
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A computer implemented method for tracking of processor transactional read and write sets comprising: maintaining a non-speculative read set indication of non-speculative reads of data stored in a cache by a processor cache unit for a transaction by a first requestor; maintaining a non-speculative write set indication of non-speculative writes of written data stored in the cache by the processor cache unit by the first requestor; maintaining a first queue of addresses corresponding to speculatively executed load memory read instructions corresponding to speculative members of a read set; maintaining a second queue of addresses corresponding to speculatively executed store memory write instructions corresponding to speculative members of a write set; performing a transaction interference resolution responsive to receiving a request for data by a remote processor, including determining a potential transaction interference exclusively conflicting with a speculative instruction; and holding a response to the received request until the speculative instruction is in a state selected from the group consisting of: committed and flushed.