Patent ID: 9553590
Date: 2017-01-24
CPC Classifications: G06F,H03K

Claim:
1. A programmable integrated circuit device comprising: a plurality of clusters of programmable logic resources; programmable device interconnect resources allowing user-defined interconnection between the clusters of programmable logic resources; a plurality of specialized processing blocks having dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources; a plurality of dedicated memory modules having inputs and outputs programmably connectable to the programmable device interconnect resources; a programmably connectable direct interconnect between at least one specialized processing block of the plurality of specialized processing blocks and at least one dedicated memory module of the plurality of dedicated memory modules; and at least one program instruction decoder programmably connectable to the at least one specialized processing block; wherein when the programmably connectable direct interconnect is turned on: wherein when the programmably connectable direct interconnect is turned off: