Patent ID: 9653161
Date: 2017-05-16
CPC Classifications: G11C

Claim:
1. A non-volatile memory device comprising: a memory cell array including memory cells arranged in an array, each of the memory cells having a resistance value and having a property that the resistance value reversibly transitions among resistance value ranges in a non-volatile manner in a variable state in accordance with application of different electrical signals; a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells; an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information; and a write circuit, wherein, in operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, thereby generating pieces of digital data, and the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.