Patent ID: 9536299
Date: 2017-01-03
CPC Classifications: G06T,H01L

Claim:
1. A computer-implemented method for detecting defects on a wafer, comprising: acquiring output for a wafer generated by an inspection system, wherein different dies are printed on the wafer with different process conditions, and wherein the different process conditions correspond to different failure modes for the wafer; comparing the output generated for a first of the different dies printed with the different process conditions corresponding to a first of the different failure modes with the output generated for a second of the different dies printed with the different process conditions corresponding to a second of the different failure modes opposite to the first of the different failure modes, wherein the different process conditions corresponding to the different failure modes comprise process conditions at corners of a process window for the wafer, wherein the different process conditions corresponding to the first of the different failure modes are at a first of the corners of the process window, and wherein the different process conditions corresponding to the second of the different failure modes are at a second of the corners of the process window opposite to the first of the corners; detecting defects on the wafer based on results of said comparing the output, wherein said acquiring, said comparing the output, and said detecting are performed by a computer system; and determining he process window by: