Patent ID: 9673100
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate; a plurality of gate structures on the substrate; an interlayer dielectric (ILD) layer around the gate structures; a first etch stop layer on the ILD layer and the gate structures; a first dielectric layer on the first etch stop layer; a second etch stop layer on the first dielectric layer; a second dielectric layer on the second etch stop layer; a plurality of first contact plugs in the ILD layer, the first etch stop layer, and the first dielectric layer for electrically connecting to a source/drain region in the substrate; a plurality of second contact plugs in the second etch stop layer and the second dielectric layer for electrically connecting to the first contact plugs, wherein the top surfaces of the second contact plugs and the second dielectric layer are coplanar and a bottom surface of the second contact plugs is greater than a top surface of the first contact plugs; and a plurality of third contact plugs in the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer for electrically connecting to the gate structures, wherein the third contact plugs contact the gate structures and the first contact plugs directly.