Patent ID: 9595600
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode layer over a substrate having an insulating surface; forming a gate insulating layer over the gate electrode layer; forming an In—Ga—Zn—O-based oxide semiconductor layer over the gate insulating layer; performing a first heat treatment after the oxide semiconductor layer is formed; forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer after performing the first heat treatment; forming an inorganic insulating layer over the gate insulating layer, the oxide semiconductor layer, and the source and the drain electrode layers; performing a second heat treatment after the inorganic insulating layer is formed; and forming a planarization layer comprising a resin material over the inorganic insulating layer, wherein an amount of change in threshold voltage according to a BT test applied to a transistor including the oxide semiconductor layer is less than or equal to 2 V, wherein the BT test is performed under conditions in which a temperature of the substrate is 150° C., an electrical field applied to the gate insulating layer is 2 MV/cm, and a time of application of the electrical field is one hour, wherein the second heat treatment is performed at a temperature higher than or equal to 100° C. and lower than a maximum temperature in the first heat treatment, wherein the oxide semiconductor layer is at least partially microcrystalline, wherein a protective layer is formed on and in contact with the oxide semiconductor layer, in a region comprised between the source electrode layer and the drain electrode layer and in regions overlapping with the source and the drain electrode layers, and wherein the source and the drain electrode layers are formed over the protective layer.