Patent ID: 9646123
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. A standard cell for use in an integrated circuit comprising: a first PMOS transistor whose gate terminal is configured to receive a first input and whose drain terminal is coupled to a first node; a second PMOS transistor whose gate terminal is configured to receive a second input and whose drain terminal is coupled to the first node; a first NMOS transistor whose gate terminal is configured to receive the first input and whose drain terminal is coupled to the first node; a second NMOS transistor whose gate terminal is configured to receive the second input and whose drain terminal is coupled to a source terminal of the first NMOS transistor to form a second node; a third NMOS transistor whose gate terminal is configured to receive the second input and whose drain terminal is coupled to the first node; and a fourth NMOS transistor whose gate terminal is configured to receive the first input and whose drain terminal is coupled to a source terminal of the third NMOS transistor to form a third node.