Patent ID: 9640566
Date: 2017-05-02
CPC Classifications: G02F,H01L

Claim:
1. A method of manufacturing a thin film transistor array panel, comprising: forming a plurality of gate lines on a substrate, wherein each gate line comprises a gate pad; forming a gate insulating layer on the plurality of gate lines; forming a semiconductor on the gate insulating layer; forming a plurality of data lines on the semiconductor, wherein each data line comprises a data pad connected to a source electrode and a drain electrode; forming a first passivation layer on the plurality of data lines and the drain electrode; forming a first electric field generating electrode on the first passivation layer; forming a second passivation layer on the first electric field generating electrode, the second passivation layer comprising a first layer on the first passivation layer and a second layer on the first layer; and forming a second electric field generating electrode on the second passivation layer, wherein an etching speed of the first passivation layer is slower than an etching speed of the second passivation layer and an etching speed of the second layer of the second passivation layer is faster than an etching speed of the first layer of the second passivation layer, and wherein the first passivation layer is formed at a temperature lower than that of the gate insulating layer, the first layer of the second passivation layer is formed at a temperature lower than that of the first passivation layer, and the second layer of the second passivation layer is formed at a temperature lower than that of the first layer of the second passivation layer.