Patent ID: 9563586
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. An apparatus comprising: a processor coupled to a first bus; one or more devices; and an interface unit coupled to the first bus and the one or more devices, the interface unit including a receive first-in first-out memory (FIFO), wherein the interface unit is configured to, responsive to a request from one of the one or more devices, read data from the one of the one or more devices and store the data in the receive FIFO, wherein the data is transferred into the receive FIFO over a second bus according to parameters controlled by the one of the one or more devices, the second bus being separate from the first bus and coupled directly between the interface unit and the one or more devices, wherein the interface unit is further configured to generate an interrupt to the processor subsequent to reading the data, wherein the interface unit includes a plurality of DMA (direct memory access) context registers each configured to store information for controlling data transfers between the processor and a selected one of the one or more devices, the stored information including an amount of data to be stored in the receive FIFO before triggering the interrupt, transaction identification information for transactions pending in the interface units, and data transfer parameters for the selected one of the one or more devices; wherein the processor is configured to access the data from the interface unit responsive to receiving the interrupt, wherein the data is transferred from the receive FIFO over the first bus according to parameters controlled by the processor, wherein the first bus is coupled directly between the processor and the interface unit.