Patent ID: 9740556
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A semiconductor memory apparatus comprising: an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data in response to a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals, wherein the data bus inversion circuit block comprises: a read data bus inversion operation unit configured to output the plurality of cell data by inverting or non-inverting the cell data according to the voltage logic levels of data included in the plurality of cell data, and generate a first inversion control signals and a second inversion control signals based on the number of data having a first voltage logic level that are included in the plurality of cell data; a data bus inversion control unit configured to output a data bus inversion control signal based on the first inversion control signals, the second inversion control signal and the error data discrimination signals; and a selection unit configured to output output signals of the read data bus inversion operation unit by inverting or non-inverting the output signals in response to the data bus inversion control signal.