Patent ID: 9620229
Date: 2017-04-11
CPC Classifications: G11C,H01L,Y10T

Claim:
1. An integrated circuit comprising: a substrate having a back surface extending in an X dimension and a Y dimension; a three-dimensional memory array comprising vertical memory cells extending in a Z direction from the back surface of the substrate; a first control circuit built on the substrate and positioned at least partially under a first quadrant of the three-dimensional memory array; a first set of control lines coupled to the first control circuit through vias that pass through at least one level of the three-dimensional memory array in the Z direction, coupled to the first quadrant of the three-dimensional memory array, and coupled to a second quadrant of the three-dimensional memory array; a second control circuit built on the substrate and positioned at least partially under the second quadrant of the three-dimensional memory array; and a second set of control lines coupled to the second control circuit, coupled to the second quadrant of the three-dimensional memory array, and coupled to a third quadrant of the three-dimensional memory array.