Patent ID: 9577638
Date: 2017-02-21
CPC Classifications: G01R,H03F,H03K,H03M,H04B,H04L,H04W

Claim:
1. A digital signal up-converting apparatus, comprising: a clock generating circuit, arranged to generate a reference clock signal; an adjusting circuit, coupled to the clock generating circuit, arranged to generate a first clock signal and a plurality of second clock signals according to the reference clock signal; a baseband circuit, coupled to the adjusting circuit, for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit, coupled to the adjusting circuit and the baseband circuit, for receiving the plurality of second clock signals and the digital output signal, wherein the plurality of second clock signals are non-overlapping; wherein the sampling circuit samples the digital output signal based on at least one of the plurality of second clock signals and then combines the sampled digital output signal in order to generate a combined digital signal; and the first clock signal is a phase-adjusted clock signal of the reference clock signal and the at least one of the plurality of second clock signals is a duty cycle-adjusted clock signal of the reference clock signal, wherein the duty cycle-adjusted clock signal is between 0% and 100%, non-inclusive.