Patent ID: 9734912
Date: 2017-08-15
CPC Classifications: G11C

Claim:
1. A method of operating a single bit per cell memory, comprising: erasing a group of memory cells establishing a first logical value in the memory cells of the group by setting threshold voltages in a first range of threshold voltages; first writing, after said erasing, including programming first selected memory cells in the group to establish a second logical value by setting threshold voltages in a second range of threshold voltages, the second range of threshold voltages different than the first range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage; second writing, after said first writing, including programming second selected memory cells in the group to establish the second logical value by setting threshold voltages in a third range of threshold voltages, the third range of threshold voltages different than the first and second ranges of threshold voltages, and saving the sensing state parameter to indicate a second read voltage; after a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, erasing the group of memory cells; and applying program pulses and respective program verify pulses following the program pulses in a pulse program sequence which incrementally increases program pulse voltages of the program pulses for programming the memory cells in the group, wherein at least one of a starting program pulse voltage magnitude in the pulse program sequence and a voltage step in the pulse program sequence is different for the first writing than for the second writing.