Patent ID: 9748262
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A memory structure, comprising: a bottom oxide layer; a first conductive layer located on the bottom oxide layer; a first insulation recess penetrating through the first conductive layer and located on the bottom oxide layer, wherein the bottom oxide layer contacts with the first insulation recess, and the first insulation recess has a first width; a plurality of insulating layers located on the first conductive layer; a plurality of second conductive layers, wherein the second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer; a second insulation recess penetrating through the insulating layers and the second conductive layers and located on the first insulation recess, the second insulation recess having a second width larger than the first width; a channel layer located on at least a sidewall of the second insulation recess; and a memory layer located between the channel layer and the second conductive layers; wherein the channel layer has a vertical extending portion and a horizontal extending portion, the horizontal extending portion is located above the second conductive layers, and the memory structure further comprises: a hard mask layer located on the channel layer, wherein the hard mask layer has an extending portion located on the horizontal extending portion of the channel layer, and the extending portion of the hard mask layer has an extending length longer than an extending length of the horizontal extending portion of the channel layer.