Patent ID: 9627052
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. An apparatus, comprising: a plurality of first decoder circuits; a plurality of second decoder circuits; an array of memory cells, each memory cell of the array of memory cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, each pair of first decoder circuits coupled via a respective first access line, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits, each pair of second decoder circuits coupled via a respective second access line; and a control circuit coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, the control circuit configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the memory cell.