Patent ID: 9543295
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first circuit; a second circuit; and a third circuit, wherein the first circuit comprises a first transistor, a first capacitor, and a first wiring, wherein the first transistor comprises a first conductor and a first oxide semiconductor, wherein the first conductor comprises a region in contact with the first oxide semiconductor, wherein one terminal of the first capacitor is electrically connected to the first conductor, wherein the other terminal of the first capacitor is electrically connected to the first wiring, wherein the second circuit comprises a second transistor, a second capacitor, and a second wiring, wherein the second transistor comprises a second conductor and a second oxide semiconductor, wherein the second conductor comprises a region in contact with the second oxide semiconductor, wherein one terminal of the second capacitor is electrically connected to the second conductor, wherein the other terminal of the second capacitor is electrically connected to the second wiring, wherein the third circuit comprises a third transistor, wherein the third transistor comprises a third conductor, a third oxide semiconductor, a first insulator, a second insulator, and a third insulator, wherein the third conductor and the third oxide semiconductor overlap with each other, wherein the first insulator is positioned between the third conductor and the third oxide semiconductor, wherein the second insulator is positioned between the third conductor and the first insulator, wherein the third insulator is positioned between the third conductor and the second insulator, wherein the second insulator comprises an electron trap region, wherein a gate voltage at which a drain current in a subthreshold region is 1×10 wherein a gate voltage at which a drain current in a subthreshold region is 1×10