Patent ID: 9659857
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method for forming an integrated circuit (IC) structure, comprising: providing a substrate including a first conductive feature; forming a cap layer on the first conductive feature such that a width of the cap layer is substantially similar to a width of the first conductive feature, wherein the cap layer includes at least one metal from the group consisting of: Co, Mn, Ni, Ru, and Ti; forming an Al-containing dielectric layer on the cap layer, wherein the Al-containing dielectric layer extends beyond the cap layer and the first conductive feature horizontally, and wherein the Al-containing dielectric layer includes: Al with a composition in a range from about 5 wt % to about 20 wt %, O with a composition in a range from about 60 wt % to about 80 wt %, and N with a composition in a range from about 10 wt % to about 30 wt %; forming a low-k dielectric layer on the Al-containing dielectric layer; etching the low-k dielectric layer to form a contact trench aligned with the first conductive feature, wherein a bottom of the contact trench is on a surface of the Al-containing dielectric layer; and forming a second conductive feature in the contact trench, wherein the first conductive feature is coupled to the second conductive feature by the Al-containing dielectric layer.