Patent ID: 9679633
Date: 2017-06-13
CPC Classifications: G06F,G11C

Claim:
1. A circuit comprising: a first differential input buffer configured to receive a differential strobe signal from a pseudo open drain output buffer, the differential strobe signal including a first component and a second component, the differential strobe signal including at least three time periods including: a second input buffer configured to receive the first component of the differential strobe signal; a control logic block configured to receive an output of the second input buffer, detect the transition of the first component from the first logic state to the second logic state during the preamble period, and assert an enable signal in response to the detection of the transition; and a gating logic block configured to receive the asserted enable signal and the differential strobe signal, and to un-gate an output of the first differential input buffer during the second holding period in response to receiving the asserted enable signal.