Patent ID: 9696965
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. An apparatus, comprising: input circuitry, configured to split an input value into multiple first bit-groups; multiple first memory arrays, which are each configured to be populated with first random numbers, to receive from the input circuitry a respective first bit-group, and to retrieve and output a first random number from a first address indicated by the received first bit-group; distribution circuitry, configured to split each first random number that is output by the first memory arrays into multiple second bit-groups, and to distribute the second bit-groups; multiple second memory arrays, which are each configured to be populated with second random numbers, to receive via the distribution circuitry a respective second bit-group from each first memory array, to concatenate the received second bit-groups so as to form an address indicator, and to retrieve and output a second random number from a second address indicated by the address indicator; and output circuitry, configured to at least combine respective second random numbers output by the second memory arrays into an output random number that depends on the input value.