Patent ID: 9733308
Date: 2017-08-15
CPC Classifications: G01R,G06F,H01L

Claim:
1. An integrated circuit comprising: (a) a TDI signal lead, a TDO signal lead, a TCK signal lead and a TMS signal lead; (b) a TAP state machine having an input coupled to the TCK signal lead, an input coupled to the TMS signal lead, instruction register control outputs, and data register control outputs; (c) an instruction register having an input coupled to the TDI signal lead, an output coupled to the TDO signal lead, control inputs coupled to the instruction control outputs of the TAP state machine and enable outputs; (d) a commandable data register control router including: an inverted clock input connected to the TCK signal lead; a data input connected to the TMS signal lead; a reset input connected to the data register control outputs; and a first control output; and an inverted clock input connected to the TCK signal lead; a data input connected to the first control output of the first flip flop; a reset input connected to the data register control outputs; and a second control output; and (e) a data register having an input coupled to the TDI signal lead, an output coupled to the TDO signal lead, and control inputs coupled to the data register control outputs of the routing circuit.