Patent ID: 9651959
Date: 2017-05-16
CPC Classifications: G05F,H02M

Claim:
1. A Single-Inductor Dual-Output (SIDO) power converter used in a Hysteresis Current Control Mode, comprising: an upper bridge transistor, connected between a first output end and an input voltage; a lower bridge transistor, connected between a second output end and a grounding voltage; and an inductor, connected between the first output end and the second output end; an error amplifying circuit, connected to the first output end and the second output end and configured to receive a first output voltage and a second output voltage and to respectively compare the received first output voltage and the received second output voltage with a first reference voltage and a second reference voltage, so as to generate a first loading signal and a second loading signal; a detecting circuit, connected to the upper bridge transistor and configured to receive a detecting value and compare the detecting value respectively with an upper limit threshold and a lower limit threshold, so as to generate a first control signal and a second control signal; and a control circuit, connected to the error amplifying circuit and the detecting circuit and configured to receive the first loading signal, the second loading signal, the first control signal and the second control signal, and to respectively control a tuning on or off of the upper bridge transistor and the lower bridge transistor according to the received first loading signal, the received second loading signal, the received first control signal and the received second control signal; wherein the control circuit comprises: a first flip flop, configured to receive the first control signal and the second control signal respectively via its set end and its reset end, and to output a first output signal and a second output signal respectively via its positive input end and its negative input end; an EXCLUSIVE-NOR gate, configured to receive the first loading signal and the second loading signal respectively via its two input ends, and to output a third output signal via its output end; a NOR gate, configured to receive the first loading signal and the second loading signal via its two input ends, and to output a fourth output signal via its output end; an AND gate, configured to receive the first output signal and the fourth output signal respectively via its two input ends, and to output a setting signal via its output end; a first OR gate, configured to receive the first loading signal and the third output signal respectively via its two input ends, and to output a fifth output signal via its output end; a second OR gate, configured to receive the second loading signal and the third output signal respectively via its two input ends, and to output a sixth output signal via its output end; a second flip flop, configured to receive the fifth output signal and the second output signal respectively via its set end and its reset end, and to output a first reset signal via its positive output end; a third flip flop, configured to receive the sixth output signal and the second output signal respectively via its set end and its reset end, and to output a second reset signal via its positive output end; a fourth flip flop, configured to receive the setting signal and the first reset signal respectively via its set end and its reset end, and to output a first switch control signal via its positive output end to turn on or off the upper bridge transistor; and a fifth flip flop, configured to receive the setting signal and the second reset signal respectively via its set end and its reset end, and to output a second switch control signal via its positive output end to turn on or off the lower bridge transistor.