Patent ID: 9627021
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. A transistor storage cell circuit, comprising: a read port that performs read operations and includes a first access transistor and a second access transistor; a first read bit line that is precharged to a low power supply voltage prior to a read operation and is coupled to the read port; a second read bit line that is precharged to the low power supply voltage prior to the read operation and is coupled to the read port, wherein the low power supply voltage comprises a ground voltage; a storage sub-circuit that is coupled to the first read bit line through the first access transistor and is coupled to the second read bit line through the second access transistor, wherein the storage sub-circuit includes a first pull-up transistor and a second pull-up transistor and is configured to store a single bit value; a read word line that is coupled to the read port via a gate of the first access transistor and via a gate of the second access transistor and configured to enable a differential representation of the single bit value to be transferred to the first read bit line and the single bit value to be transferred to the second read bit line during the read operation; and a write port that performs write operations and is separate and independent from the read port, the write port including a third access transistor and a fourth access transistor, wherein a drive strength of the third access transistor and the fourth access transistor is greater than a drive strength of the first pull-up transistor and the second pull-up transistor, and the drive strength of the first pull-up transistor and the second pull-up transistor is greater than a drive strength of the first access transistor and the second access transistor, wherein the drive strength of the third access transistor and the fourth access transistor and the drive strength of the first access transistor and the second access transistor are independently adjustable, and wherein increasing the drive strength of the third access transistor and the fourth access transistor does not increase the occurrence of read disturb faults associated with read operations performed via the read port.