Patent ID: 9571263
Date: 2017-02-14
CPC Classifications: H03L,H04L

Claim:
1. A data retiming circuit comprising: a voltage controlled oscillator; a clock generator configured to receive a recovered clock from the voltage controlled oscillator and generate therefrom, a latched clock; and a phase detector configured to receive the latched clock from the clock generator and to use two different voltage levels of the latched clock to generate from an input data signal provided to the phase detector, a first data output signal and a second data output signal, wherein each of the first data output signal, the second data output signal, and the latched clock is propagated in a differential signal format, and further wherein the clock generator comprises a first pair of transistors arranged in a first differential configuration, the first pair of transistors coupled to a second pair of transistors arranged in a second differential configuration, the second pair of transistors configured to operate as a latching circuit for latching output signals of the first pair of transistors.