Patent ID: 9590602
Date: 2017-03-07
CPC Classifications: G11C,H03K

Claim:
1. A method of generating a clock pulse, the method comprising: receiving an enable signal at an input of a tri-state buffer; receiving a leading edge of an input clock at a clock input at a time when an enable signal is active, the clock input coupled to a first input of a logic gate; generating a leading edge of an output clock at a clock output based on the received leading edge of the input clock; latching a logic value corresponding to the leading edge of the output clock at the clock output; after the logic value is latched, feeding a value representative of the output clock back to second input of the logic gate to prevent changes at the clock input from affecting the latched logic value and feeding the value representative of the output clock back to a control input of the tri-state buffer to isolate the latched logic value from changes of the enable signal at the input of the tri-state buffer; resetting the latched logic value after a first delay time thereby causing a trailing edge at the clock output; and maintaining the reset logic value until a second leading edge is received at the clock input.