Patent ID: 9666586
Date: 2017-05-30
CPC Classifications: G11C,H01L

Claim:
1. A memory cell comprising: a CMOS substrate having two adjacent wells of opposite conductivity types, having a trench isolation between the wells, wherein a first of the two adjacent wells is connected to a ground voltage level and a second of the two adjacent wells is connected to a constant voltage level; a shallow lightly doped n layer in the first of the two adjacent wells; a shallow lightly doped p layer in the second of the two adjacent wells; at least a first and second deep heavily doped p regions in the first adjacent well, said first deep heavily doped p region adjacent to the trench isolation, so that a shallow n region of the shallow lightly doped n layer is left between said first and second deep heavily doped p regions; at least a first and second deep heavily doped n regions in the second of the two adjacent wells, said first deep heavily doped n region adjacent to the trench isolation, so that a shallow p region of the shallow lightly doped p layer is left between said first and second deep heavily doped n regions, wherein the production of the shallow lightly doped n and p layers and the deep heavily doped p and n regions is performed in a same manner used for forming of such elements during a CMOS process; and a conductor connecting the first and second deep heavily doped p regions, the shallow n region, the first and second deep heavily doped n regions and the shallow p region to the same input voltage level relative to the ground voltage level, the input voltage level is switchable between the ground voltage level and the constant voltage level.