Patent ID: 9646995
Date: 2017-05-09
CPC Classifications: G02F,H01L

Claim:
1. An FFS array substrate comprising: a substrate; a first metal layer mounted on the substrate to form a scanning line and a gate electrode of a thin-film transistor; a first insulated layer mounted on the first metal layer to insulate the first metal layer and a second metal layer from each other, wherein the second metal layer is mounted on the first insulated layer to form a data line, a source electrode of the thin-film transistor and a drain electrode of the thin-film transistor; a second insulated layer mounted on the second metal layer to insulate the second metal layer and a transparent electrode layer from each other, wherein the transparent electrode layer is mounted on the second insulated layer to form a transparent pixel electrode; and the transparent pixel electrode is connected to the drain electrode of the thin-film transistor via a first through hole of the second insulated layer; and a third insulated layer mounted on the transparent electrode layer to insulate the transparent electrode layer and a common electrode layer from each other, wherein the common-electrode layer includes a common-electrode line formed on the third insulated layer and a transparent common electrode formed on the common-electrode line and the third insulated layer; wherein a resistivity of the common-electrode line is smaller than that of the transparent common electrode, wherein the second metal layer is further provided with a common line for providing a common signal, and the common-electrode line is connected to the common line on the second metal layer by passing through the third insulated layer, the transparent electrode layer and a second through hole of the second insulated layer.