Patent ID: 9632832
Date: 2017-04-25
CPC Classifications: G06F

Claim:
1. A method to process an instruction to assign a thread to a particular core in a multi-core processor, wherein the multi-core processor includes a first core, a second core, a first memory controller, and a second memory controller, the method comprising: determining first miss data that relates to a first number of times the first memory controller fetches from a memory in response to cache misses experienced by the first core during a period of time; determining second miss data that relates to a second number of times the first memory controller fetches from the memory in response to cache misses experienced by the second core during the period of time; determining third miss data that relates to a third number of times the second memory controller fetches from the memory in response to cache misses experienced by the first core during the period of time; determining fourth miss data that relates to a fourth number of times the second memory controller fetches from the memory in response to cache misses experienced by the second core during the period of time; processing a first instruction to assign the thread to the first core, wherein the first instruction to assign the thread is based on the first, second, third, and fourth miss data; selecting the first memory controller based on a proximity between the first memory controller and the first core; identifying memory addresses assigned to the selected first memory controller; and processing a second instruction to migrate pages of data for the thread in the memory addresses to page frames that have a same color as the first memory controller.