Patent ID: 9569190
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. An apparatus for compiling source code to reduce run-time execution of vector element reverse operations, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: identifying, by a compiler, a first loop and a second loop in a computer program, wherein the first loop is embedded within the second loop; identifying, by the compiler, at least one vector element reverse operation within the first loop; analyzing, by the compiler, a dataflow graph containing that at least one vector element reverse operation within the first loop, including determining whether all vector operations in a portion of the dataflow graph including the first loop are lane-insensitive and determining whether all vector operations in the portion of the dataflow graph containing the first loop are lane-adjustable; and responsive to the analysis, replacing, by the compiler, the vector element reverse operations from the first loop by placing the vector element reverse operations inside the second loop; moving, by the compiler and within the second loop, a plurality of vector element reverse operations to the perimeter of the first loop; and for each pair of vector element reverse operations moved to the perimeter of the first loop in which a result of one of the vector element reverse operations in the pair is the source of the other vector element reverse operation in the pair: removing at least one of the vector element reverse operations in the pair.