Patent ID: 9652099
Date: 2017-05-16
CPC Classifications: G06F,G09G,H01L

Claim:
1. An array substrate including a display area and a peripheral area, wherein: the display area includes a plurality of thin film transistors provided on a base substrate, first transparent electrodes electrically connected with drain electrodes of the thin film transistors, second transparent electrodes, and a transparent insulation layer that contacts the second transparent electrodes, wherein the thin film transistors and the first and second transparent electrodes function as display pixels; the transparent insulation layer is applied a voltage such that, in the case where the voltage applied on the transparent insulation layer is larger than a predetermined voltage, the transparent insulation layer becomes a conductor, and in the case where the voltage applied on the transparent insulation layer is less than the predetermined voltage, the transparent insulation layer becomes an insulator; the second transparent electrodes include first sub-electrodes arranged into a plurality of rows in a first direction, and second sub-electrodes arranged into a plurality of rows in a second direction; the first sub-electrodes in different rows are insulated from each other, the second sub-electrodes in different rows are insulated from each other, and the first sub-electrodes and the second sub-electrodes are insulated from each other; the first direction is intersected with the second direction; the transparent insulation layer is extended into the peripheral area; the peripheral area includes a grounded first metal line; and the transparent insulation layer is electrically connected to the grounded first metal line in the peripheral area, and charges accumulated on the second transparent electrodes flow from the second transparent electrodes to the grounded first metal line through the transparent insulation layer when the transparent insulation layer becomes the conductor.