Patent ID: 9679945
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A semiconductor memory device comprising: a first conductive layer; a second conductive layer separated from the first conductive layer in a first direction; a first resistance change layer provided between the first conductive layer and the second conductive layer; a third conductive layer arranged with the first conductive layer in a second direction crossing the first direction, the third conductive layer containing a material contained in the first conductive layer; a fourth conductive layer arranged with the second conductive layer in a direction crossing the first direction, the fourth conductive layer being arranged with the third conductive layer in the first direction, electrically connected with the third conductive layer, and containing a material contained in the second conductive layer; and a first intermediate layer provided between a portion of the third conductive layer and a portion of the fourth conductive layer and containing a material contained in the first resistance change layer.