Patent ID: 9633747
Date: 2017-04-25
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: an input/output I/O drive controller configured to generate drive control signals and an input control signal for controlling first and second global I/O lines according to a first test mode or a second test mode; a data I/O unit configured to drive the first global I/O line in response to an input data when a write operation is executed in the first test mode, and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode; and a data transmitter configured to transfer data loaded on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode, and configured to transfer data loaded on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode.