Patent ID: 9619387
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. An apparatus for data processing, comprising: data processing circuitry configured to perform data processing operations with reference to data values stored in a memory, wherein each data processing operation has an identifier associated therewith; and address translation circuitry configured to store address translations between first addresses used in a first addressing system corresponding to the data processing operations performed by the data processing circuitry and second addresses used in a second addressing system used by the memory, wherein each stored address translation is stored with a corresponding identifier, wherein the address translation circuitry is configured to respond to an invalidation command to perform an invalidation process on a selected stored address translation to invalidate the selected stored address translation, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier, and the address translation circuitry is further configured to perform the invalidation process dependent on identifier grouping information, the specified identifier and the specified first address, wherein the identifier grouping information associates more than one identifier together as a group of identifiers comprising less than all identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.