Patent ID: 9607714
Date: 2017-03-28
CPC Classifications: G11C

Claim:
1. A method of training a command signal for a memory module, said method comprising: programming a memory controller into a mode wherein a first bit of an address signal is active for a single clock cycle; programming a first programmable delay line of said address signal with a delay value, such that said address signal is delayed by said delay value; initializing said memory module; during said initialization, sending said first bit of said address signal delayed by said delay value as a write leveling mode register set command, wherein said first bit is set at a first level; placing said memory module in a write leveling mode when said first bit is sampled at said first level at said memory module; at said memory controller, performing a write leveling procedure and determining a response thereto from said memory module; determining said memory module is in a pass state when said response comprises said first level and indicates said memory module is in said write leveling mode; determining said memory module is in an error state when said response comprises a second level opposite said first level and indicates said memory module is not in said write leveling mode; and programming a second programmable delay line of said command signal with said delay value when said memory module is in a pass state.