Patent ID: 9633920
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A group III-V semiconductor device comprising: a substrate; a bulk buffer layer disposed over the substrate; a device layer of III-V material disposed over the bulk buffer layer; a source region, a drain region and a gate region located laterally between the source and drain regions, and wherein the gate region comprises a gate electrode overlying a gate separation layer and wherein the gate separation layer comprises a doped III-V material layer or an insulator; a bulk passivation layer arranged over the device layer; and an interfacial layer of III-V material contacting the bulk passivation layer and the device layer, wherein the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to contact the device layer; and a capping layer disposed over the bulk passivation layer, the source region and the drain region, wherein the gate region extends over an upper surface of the capping layer.