Patent ID: 9698785
Date: 2017-07-04
CPC Classifications: G01R,H03F,H03K,H03M,H04B,H04L,H04W

Claim:
1. A digital signal up-converting apparatus, comprising: a clock generating circuit, arranged to generate a first reference clock signal, a second reference clock signal, a third reference clock signal, and a fourth reference clock signal; a phase adjusting circuit, arranged to adjust the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal to generate a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal; a baseband circuit, arranged to generate a first digital output signal, a second digital output signal, a third digital output signal, and a fourth digital output signal according to a first baseband data, a second baseband data, the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal; and a sampling circuit, arranged to sample the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal to generate a first sampled digital signal, a second sampled digital signal, a third sampled digital signal, and a fourth sampled digital signal according to a first sampling clock signal, a second sampling clock signal, a third sampling clock signal, and a fourth sampling clock signal, respectively.