Patent ID: 9673183
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device package, comprising: providing a fan out wafer comprising semiconductor-device-package locations at a base level, each semiconductor-device-package location comprising: stacking semiconductor dice on a side of at least some semiconductor-device-package locations of the fan out wafer opposite the electrically conductive traces to mutually superimpose vias of the semiconductor dice of at least one stack and to vertically superimpose the vias of the semiconductor dice with vias extending from the electrically conductive traces of the base level, vias of the base level and vias of the at least one stack of semiconductor dice being distinct, and formed separately, from one another; electrically connecting the stacks of semiconductor dice to vertically adjacent electrically conductive vias and associated electrically conductive traces of the at least some semiconductor-device-package locations; and singulating the semiconductor-device-package locations having stacks of semiconductor dice thereon from the fan out wafer.