Patent ID: 9601494
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: an interlayer insulating layer on a semiconductor substrate; contact pads on the semiconductor substrate and penetrating the interlayer insulating layer; a stopping insulating layer on the interlayer insulating layer; storage electrodes on the contact pads; upper supporters between upper parts of the storage electrodes; side supporters between the storage electrodes and the upper supporters; lower supporters between the upper supporters and the stopping insulating layer; a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters; a storage barrier layer on side surfaces of the storage electrodes; and a plate electrode on the capacitor dielectric layer, wherein the capacitor dielectric layer comprises: a lower capacitor dielectric layer on lower surfaces of the lower supporters, an upper surface of the stopping insulating layer, and the side surfaces of the storage electrodes; an intermediate capacitor dielectric layer on upper surfaces of the lower supporters, lower surfaces of the upper supporters, and the side surfaces of the storage electrodes; and an upper capacitor dielectric layer on upper surfaces of the storage electrodes, upper surfaces of the side supporters, and upper surfaces of the upper supporters, and wherein an upper surface of the storage barrier layer is coplanar with an upper surface of the intermediate capacitor dielectric layer.