Patent ID: 9543736
Date: 2017-01-10
CPC Classifications: G02B,H01L,H01S

Claim:
1. A method of assembling a multi-chip system, comprising: providing a first chip stack element having two major surfaces, the first chip stack element comprising a first solder pad on a plane of one of the major surfaces, a first vertical stop, a first lateral stop, and a first waveguiding element; providing a second chip stack element having two major surfaces, the second chip stack element comprising a second solder pad, a flow resistor connected to the second solder pad, a second vertical stop, a second lateral stop, a reservoir pad connected to the flow resistor, and a second waveguiding element; optionally plating the reservoir pad with a reservoir solder material; plating a solder material on the second solder pad to form a plated solder pad, wherein the height of the plated solder material on the second solder pad is at a height that is higher than the height of plated reservoir solder material; pre-aligning the first chip stack element and the second chip stack element to bring the first solder pad in proximity to the plated solder pad; raising the temperature to a temperature above the melting temperature of the solder material; flowing solder through the flow resistor; aligning the first and second waveguiding elements; cooling the connected assembly to re-solidify the solder material.