Patent ID: 9721912
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A wafer-level chip-scale package device comprising: an integrated circuit chip; and an array of bump assemblies disposed directly on the integrated circuit chip, the array of bump assemblies comprising a plurality of first bump assemblies including solder bumps, where the solder bumps are without a core and are for electrical interconnection with a redistribution layer of the integrated circuit chip, composed at least substantially of a solder composition and a plurality of second bump assemblies including a solder bump having a plastic core configured to furnish shock absorber functionality to the integrated circuit chip, where the plurality of second bump assemblies is disposed about the perimeter of the integrated circuit chip and is not electrically interconnected with the integrated circuit chip, and where the plurality of first bump assemblies includes a first solder composition and the plurality of second bump assemblies includes a second solder composition different from the first solder composition.