Patent ID: 9571341
Date: 2017-02-14
CPC Classifications: G06F,G06N,H04L,Y02D

Claim:
1. A hardware element in a Network on Chip (NoC) and/or System on Chip (SoC) comprising: a clock gating circuit that configures one or more neighboring hardware elements to activate before receiving new incoming data; and to configure the one or more neighboring hardware elements to sleep after a defined number of cycles, said defined number of cycles are counted from a cycle having non-receipt of incoming data and having a clearance of all data within an input queue of a source hardware element, the defined number of cycles being set based on at least one of a predetermined number of cycles and a calculation based on a self-learning process associated with one or more conditions of the at least one of the SoC and the NoC; wherein the hardware element is configured to be clock gated or clock disabled through one of a system level signal and a programmed register, upon which hardware element sends interrupt to its neighboring hardware elements to prevent them from sending messages to the hardware element.