Patent ID: 9620590
Date: 2017-04-11
CPC Classifications: H01L,H05K

Claim:
1. A method of fabricating a nanosheet semiconductor device, the method comprising: forming nanosheet fins including nanosheet stacks comprising alternating silicon (Si) layers and silicon germanium (SiGe) layers on a substrate; etching each nanosheet fin to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin; undercutting the SiGe layers in the nanosheet stacks at the first end and the second end to form divots at the first end and the second end; depositing a dielectric at the first end and the second end, wherein the depositing includes depositing the dielectric in the divots at the first end and the second end; removing the SiGe layers between the Si layers such that there are gaps between the Si layers of each nanosheet stack and the dielectric anchors the Si layers at the first end and the second end, wherein the removing the SiGe layers precedes forming source and drain regions of the nanosheet semiconductor device; filling the gaps with an oxide to form second nanosheet stacks comprising alternating layers of the Si and the oxide prior to forming a dummy gate above the nanosheet stacks; and removing the oxide after removal of the dummy gate and prior to replacement with a replacement gate.