Patent ID: 9660026
Date: 2017-05-23
CPC Classifications: G06N,H01L

Claim:
1. A method for fabricating an electronic device comprising a silicon nanowire, comprising the steps of: lithographically patterning a silicon layer to define an elongate silicon structure underlain by an oxide layer; doping selected portions of the patterned silicon layer by ion implantation so as to define respective source and drain regions connected by a channel region that passes through the elongate silicon structure; depositing and patterning a first interlayer dielectric layer (first ILD) so that it overlies selected portions of the patterned silicon layer; etching away at least a portion of the underlying oxide layer such that at least a portion of the elongate silicon structure is suspended, thereby forming a nanowire; in at least one iteration, oxidizing an outer portion of the nanowire and then etching away the oxidized portion, so as to thin the nanowire; and annealing the nanowire under conditions effective to cause a partial reshaping of the nanowire such that the nanowire assumes a hexagonal cross-sectional profile; wherein the nanowire is included in an integrated circuit, and wherein the method further comprises completing the integrated circuit by a sequence of complementary metal-oxide-semiconductor (CMOS) processing steps that comprises: growing an all-around gate oxide layer that envelopes the nanowire; depositing and patterning an all-around gate polysilicon layer so that the gate polysilicon layer envelopes the nanowire; depositing a second interlayer dielectric layer (second ILD) of silicon oxide so as to fill space around the nanowire and so as to overlie the first ILD; forming support structures for a top gate electrode, wherein the support structures are made of silicon nitride and pass through the second ILD; depositing a top gate polysilicon layer over the second ILD and over the support structures, and patterning and etching the top gate polysilicon layer so as to form the top gate electrode; depositing a third interlayer dielectric layer (third ILD) of silicon oxide over the second ILD and over the top gate electrode; etching contact holes through the first, second, and third ILDs for contact with the source region, the drain region, and the top gate electrode; forming contacts within and over the contact holes; and then, by etching, removing silicon oxide of the second and third ILDs from under, over, and around the nanowire.