Patent ID: 9645604
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. An integrated circuit, comprising: a plurality of processing units operable to synchronize respective processing to a respective plurality of mesochronous clock signals, the mesochronous clock signals including a first clock signal and a second clock signal, the first and second clock signals having a same frequency and different phases, respectively, the processing units including a first processing unit operable to synchronize processing to the first clock signal and a second processing unit operable to synchronize processing to the second clock signal, wherein the second processing unit includes a latch circuit coupled to receive data from the first processing unit, and wherein the latch circuit is configured to operate based on states of the first and second clock signals, and wherein the second processing unit further includes a clock buffer operable to receive the first clock signal from the first processing unit and to generate the second clock signal by shifting a phase of the first clock signal by an amount less than one clock period of the first clock signal.