Patent ID: 9671557
Date: 2017-06-06
CPC Classifications: G02B

Claim:
1. A method for forming vertically integrated hybrid waveguides with interlayer thickness control, the method comprising multiple steps in a sequential order of: (1) providing a silicon-on-insulator (SOI) substrate; (2) forming a multi-layer hard mask overlying the SOI substrate, the multi-layer hard mask comprising a top silicon oxide layer overlying a silicon nitride layer overlying a first silicon oxide layer; (3) forming one or more silicon waveguide patterns in the SOI substrate, each silicon waveguide pattern carrying the multi-layer hard mask on top of at least one silicon waveguide; (4) forming a dielectric layer to overlay the one or more silicon waveguide patterns and cover any gaps separating the one or more silicon waveguide patterns; (5) removing at least partially the dielectric layer to expose the multi-layer hard mask overlying the at least one silicon waveguide; (6) removing at least partially the multi-layer hard mask to leave substantially the first silicon oxide layer overlying the at least one silicon waveguide; (7) forming a second silicon oxide layer overlying the first silicon oxide layer such that total thickness of the first silicon oxide layer and the second silicon oxide layer is controlled to be no greater than 90 nm across entire area of the SOI substrate; (8) forming one or more silicon nitride waveguides, at least one of the one or more silicon nitride waveguides overlying the second silicon oxide layer at least vertically overlapping with the at least one silicon waveguide.