Patent ID: 9590096
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A vertical field-effect transistor (FET) comprising: a substrate having a drift region of a first conductivity type situated over a drain of the first conductivity type, a body region of a second conductivity type opposite the first conductivity type situated over said drift region and having source diffusions of the first conductivity type formed therein, a gate trench extending through said body region and into said drift region, and channel regions adjacent said gate trench; said channel regions being spaced apart along id gate trench by respective spatially confined deep body implants of the second conductivity type; each of said spatially confined deep body implants being situated below said body region approximately under at least one of said source diffusions and extending deeper into said drift region than said gate trench; each of said spatially confined deep body implants providing both lateral and vertical depletion of said drift region.