Patent ID: 9658920
Date: 2017-05-23
CPC Classifications: G06F

Claim:
1. A method of correcting a configuration memory frame in an integrated circuit with a plurality of configuration memory frames, comprising: with error detection circuitry on the integrated circuit, identifying an erroneous memory frame in the plurality of configuration memory frames; reading a portion of data stored in an off-chip memory module with controller circuitry, wherein the read data portion corresponds to the erroneous memory frame; generating an error message with the error detection circuitry, wherein the error message comprises a frame address of the erroneous memory frame, and wherein the read data portion is read from the off-chip memory module based on the frame address; with the controller circuitry, determining an address of a leading memory bit in the erroneous memory frame based on at least the frame address, a size of a single configuration memory frame in the plurality of configuration memory frames, and an address of a first memory bit in a first configuration memory frame in the plurality of configuration memory frames, wherein the address of the first memory bit and the size the single configuration memory frame are constants that are stored in the controller circuitry; determining an address of a last memory bit in the erroneous memory frame based at least on the address of the leading memory bit in the erroneous memory frame; and correcting the erroneous memory frame by loading the read data portion into the erroneous memory frame during normal operation of the integrated circuit, wherein loading the read data portion into the erroneous memory frame comprises updating the leading and last memory bits in the erroneous memory frame and each memory bit between the leading and last memory bits in the erroneous memory frame without affecting other configuration memory frames of the plurality of configuration memory frames.