Patent ID: 9543336
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A thin-film transistor array panel, comprising: a substrate; a first gate electrode disposed on the substrate; a first self-assembled monolayer disposed on the first gate electrode; a gate insulating layer disposed on the first self-assembled monolayer; a semiconductor disposed on the gate insulating layer; a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor; a first interlayer insulating layer disposed on the source electrode and the drain electrode; a second self-assembled monolayer disposed on the first interlayer insulating layer; a second gate electrode disposed on the second self-assembled monolayer; a second interlayer insulating layer disposed on the second gate electrode; and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.