Patent ID: 9691820
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A three dimensional memory structure, comprising: a first plurality of conductive lines; a first socket region; a memory array area, wherein the conductive lines included in the first plurality of conductive lines extend from the memory array area to the first socket region; a second plurality of conductive lines; a second socket region, wherein the conductive lines included in the second plurality of conductive lines extend from the memory array area to the second socket region; wherein the first socket region extends along a first side of the memory array area, wherein the second socket region extends along a second side of the memory array area, wherein at the first socket region a number of conductive lines in the first plurality of conductive lines is equal to m, wherein at the second socket region a number of conductive lines in the second plurality of conductive lines is equal to n, wherein m has a value that is at least twice a value of n, wherein the memory array area includes a plurality of memory cells, and wherein a length of the memory cells in a direction y parallel to the first side of the memory array area is greater than a length of the memory cells in a direction x parallel to the second side of the memory array area.