Patent ID: 9633956
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method comprising: performing a first implantation to implant a semiconductor substrate and to form a deep well region, wherein the semiconductor substrate is of a first conductivity type, and wherein in the first implantation, an impurity of a second conductivity type opposite to the first conductivity type is implanted; performing a second implantation to implant the semiconductor substrate, wherein a well region of the first conductivity type is formed over the deep well region, and wherein after the first and the second implantations, the semiconductor substrate comprises: forming a gate dielectric over the top portion of the semiconductor substrate; forming a gate electrode over the gate dielectric; performing a third implantation to implant the top portion of the semiconductor substrate and to form a source region and a drain region, wherein the source region and the drain region are spaced apart from the well region by a remaining part of the top portion of the semiconductor substrate, and wherein the source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch configured to operate in a RF frequency range; forming a gate spacer on a sidewall of the gate electrode, wherein the gate spacer has an outer edge in physical contact with a top surface of one of the source region and the drain region; and forming a dielectric layer comprising a portion over and contacting the one of the source region and the drain region, wherein the dielectric layer has a substantially flat top surface extending to the outer edge of the one of the source region and the drain region.