Patent ID: 9654114
Date: 2017-05-16
CPC Classifications: G11C,H03L,H03M

Claim:
1. A transmission circuit, comprising: a shift register configured to include a plurality of flip-flop circuits which are cascade-connected, and to shift, in synchronization with a first clock signal, input parallel data set within the plurality of flip-flop circuits; a control circuit configured to detect a phase of the first clock signal, and to output a second clock signal of a phase in accordance with the detected phase of the first clock signal; a selector configured to select any one of the input parallel data set and a plurality of output parallel data sets, each of the plurality of output parallel data sets being held by a corresponding one of the plurality of flip-flop circuits; and a conversion circuit configured to convert, in synchronization with the second clock signal, the parallel data set selected by the selector into pieces of serial data, wherein: the control circuit outputs a selection signal in accordance with a deviation amount of the detected phase of the first clock signal; and the selector selects, in accordance with the selection signal, any one of the input parallel data set and the plurality of output parallel data sets.