Patent ID: 9563534
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a computer program residing in the memory, the computer program including a plurality of instructions that includes at least one vector instruction; a debug table that specifies a vector register, a corresponding address range for the specified vector register, and a corresponding endian reformatting type for the specified vector register; and a debugger residing in the memory and executed by the at least one processor, the debugger receiving a request to display contents of a vector register at a current instruction in the computer program, and in response, the debugger determines whether the current instruction has an address within an address range in the debug table, and when the current instruction is not within an address range in the debug table, the debugger displays the contents of the vector register, and when the current instruction has an address within an address range of the debug table, the debugger determines from the debug table an endian reformatting type corresponding to the address range, and displays the contents of the vector register and additionally displays the contents of the vector register after reformatting the contents according to the endian reformatting type.