Patent ID: 9733301
Date: 2017-08-15
CPC Classifications: G01R

Claim:
1. A system for communicatively connecting devices for testing to respective test pins of an automatic test equipment (ATE), comprising: a tester interface device physically and communicatively connected to all of the test pins of the ATE, the test interface device includes a first connector and a second connector, the first connector is physically connected to all of the test pins of the ATE and is communicatively connected by the tester interface device to a selective first group of the test pins of the ATE, and the second connector is physically connected to all of the test pins of the ATE and is communicatively connected by the test interface device to a selective second group of the test pins of the ATE, wherein the tester interface device includes a support plate and a tester interface board physically engaged with the support plate, the support plate having portal holes that permit test pins of the ATE to protrude through the portal holes and mate with connections on the tester interface board, all of the connections on the tester interface board being connected to a first cable and to a second cable; a first interface system that includes a first device board having a first test socket for testing a first device under test, a first stiffening plate, and a first block board having first block pins that are physically connected to all of the test pins of the ATE and communicatively connected to the selective first group of the test pins of the ATE via the first connector and the first cable; and a second interface system that includes a second device board, having a second test socket for testing a second device under test, a second stiffening plate, and a second block board having second block pins that are physically connected to all of the test pins of the ATE and communicatively connected to the selective second group of the test pins of the ATE via the second connector and the second cable, wherein the system has a configuration that uses a plurality of vector patterns for conducting a plurality of test schemes, including parallel testing in which same tests are conducted in alternating succession, concurrent testing in which different or same tests are concurrently performed, and parallel concurrent testing in which different tests are conducted in alternating succession.