Patent ID: 9659928
Date: 2017-05-23
CPC Classifications: H01L,Y10S

Claim:
1. A semiconductor device, comprising: a first active region formed in a semiconductor layer; a first gate electrode structure formed above said first active region; a second active region formed in said semiconductor layer; a second gate electrode structure formed above said second active region; a trench isolation structure positioned between said first and second gate electrode structures so as to electrically isolate said first and second gate electrode structures, said trench isolation structure comprising an insulating material having a top surface; and a conductive line formed above a portion of said first gate electrode structure, a portion of said second gate electrode structure and a portion of said trench isolation structure, said conductive line being conductively coupled to a top surface of each of the first and second gate electrode structures and in contact with said top surface of said trench isolation structure.