Patent ID: 9666492
Date: 2017-05-30
CPC Classifications: B82Y,H01L

Claim:
1. A method of forming a pair of semiconductor devices on a substrate, the method comprising: disposing on a first region of the substrate a first stack of semiconductor layers including a crystalline group IV semiconductor layer overlying a first sacrificial layer; disposing on a second region of the substrate a second stack of semiconductor layers including a crystalline group III-V semiconductor layer overlying a second sacrificial layer; etching the first stack to define a first nanowire comprising the group IV semiconductor layer; etching the second stack to define a second nanowire comprising the group III-V semiconductor layer; forming a first gate stack coaxially wrapping completely around the group IV crystalline layer along a longitudinal channel length of the first nanowire; and forming a second gate stack coaxially wrapping completely around the group III-V crystalline layer along a longitudinal channel length of the second nanowire; wherein the first sacrificial layer is the crystalline group III-V semiconductor layer and wherein the second sacrificial layer is the crystalline group IV semiconductor layer and wherein disposing the first and second stacks of semiconductor layers on the substrate comprises epitaxially growing the both the crystalline group III-V semiconductor layer and the crystalline group IV semiconductor layer over both the first and second regions of the substrate.