Patent ID: 9583484
Date: 2017-02-28
CPC Classifications: G11C,H01L,H03K,H03L

Claim:
1. An integrated circuit, comprising: a first deeply depleted channel transistor formed in the substrate and having a first source-drain current path coupled between a first and a second node, the first deeply depleted channel transistor having a first source drain vertical doping profile with a first extension region that extends in a lateral direction under a gate electrode of the first deeply depleted channel transistor, the first deeply depleted channel transistor being configured to selectively couple a first output node to the first or second node in response to one or more input signals, the first deeply depleted channel transistor having a first drawn gate length of less than one micron; and a second deeply depleted channel transistor formed in the substrate and having a second source-drain current path coupled between the first node and the second node, the second deeply depleted channel transistor having a second source drain vertical doping profile with a second extension region of which dopant concentration is less than dopant concentration of the first extension region, the second deeply depleted channel transistor being configured to selectively couple a second output node to the first or second node in response to the one or more input signals, the second deeply depleted channel transistor having a second drawn gate length of less than one micron and same channel doping profile as a channel doping profile of the first deeply depleted channel transistor.