Patent ID: 9690653
Date: 2017-06-27
CPC Classifications: G06F,G11C

Claim:
1. An apparatus comprising: n data terminals, each of the n data terminals being configured to input or output burst data of m bits, where n and m are integers more than 1; a memory cell array into which write data is written and from which read data is read, each of the write data and the read data comprising a data portion of m×n bits and a parity portion of k bits, where k is an integer more than 1; and an error correction code (ECC) control circuit configured to: receive the read data from the memory cell array to correct, if any, an error bit contained in the data portion of the read data responsive, at least in part, to the parity portion of the read data, detect the error bit of the data portion of the read data based, at least in part, on the first error determination signals and the second error determination signals.