Patent ID: 9588900
Date: 2017-03-07
CPC Classifications: G06F

Claim:
1. A method to control caching of data in a chip multiprocessor having multiple processor cores, the method comprising: tracking, with a processor included in the chip multiprocessor, an eviction rate of a first private cache that is operated and preferentially used by a first processor core of the chip multiprocessor; tracking, with the processor, an eviction rate of a second private cache that is operated and preferentially used by a second processor core of the chip multiprocessor; determining, with the processor, an aggregate eviction rate based on the eviction rate of the first private cache and the eviction rate of the second private cache by computing an average eviction rate that includes the tracked eviction rate of the first private cache and the tracked eviction rate of the second private cache; detecting, with the processor, that the aggregate eviction rate has exceeded a particular threshold; and in response to the detecting, preventing, with the processor, one or more data blocks used by the first processor core from being stored in the second private cache.