Patent ID: 9680492
Date: 2017-06-13
CPC Classifications: H03M

Claim:
1. An analog to digital converter (ADC), comprising: a comparator; a plurality of capacitor pairs coupled between a first input and a second input of the comparator, wherein each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage; a voltage detection circuit coupled between the first and second inputs; and a state machine configured to: upon determining during a first cycle of the plurality of cycles that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs corresponding to the first cycle in a reset state such that the sampled analog voltage is unchanged; and upon determining during the first cycle that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs does not satisfy the threshold, switching the first pair of the plurality of capacitor pairs to change the sampled analog voltage.