Patent ID: 9672316
Date: 2017-06-06
CPC Classifications: G03F,G06F,H01L

Claim:
1. A method of manufacturing integrated circuits having one or more layers with a respective layout design at least partially formed using a direct write lithography step, said method comprising the steps of: measuring one or more performance characteristics of an at least partially formed integrated circuit; changing said layout design of at least one of said one or more layers to be formed using said direct write lithography step in dependence upon said one or more performance characteristics to generate a changed layout design; and forming said at least one of said one or more layers using said step of direct write lithography in accordance with said changed layout design, wherein said one or more performance characteristics include a speed of operation of at least a portion of said integrated circuit and said changed layout design provides a changed nominal speed of operation of said at least a portion of said integrated circuit.