Patent ID: 9646822
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method of fabricating a non-planar semiconductor device, the method comprising: forming a semiconductor fin protruding from and continuous with a bulk crystalline semiconductor substrate; forming an isolation layer laterally adjacent to a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin extends above the isolation layer, the upper portion of the semiconductor fin having a top surface and laterally adjacent sidewall surfaces; oxidizing outermost portions of the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin, the oxidizing forming an oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin; depositing a gate material on the oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin; patterning the gate material and the oxide layer to form a gate electrode on a gate dielectric layer on a portion of the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin; removing a portion of the upper portion of the semiconductor fin; and forming a replacement semiconductor fin upper portion comprising a semiconductor material different than the bulk crystalline semiconductor substrate, wherein the gate dielectric layer is on a channel region of a top surface and laterally adjacent sidewall surfaces of the replacement semiconductor fin upper portion.