Patent ID: 9715912
Date: 2017-07-25
CPC Classifications: G06F,G11C,Y02D

Claim:
1. An integrated circuit device comprising: a physical interface element having a first data interface configured to synchronously communicate data signals according to a first clock signal at a first clock speed, said first data interface being a physical interface with one or more external devices, external to said integrated circuit device, and a second data interface configured to synchronously communicate said data signals, communicated by said one or more external devices according to said first clock signal at said first clock speed, at a second clock speed lower than said first clock speed; and a data processing element, different than the one or more external devices, configured to operate in response to a second clock signal at said second clock speed and to synchronously communicate said data signals with said physical interface element via said second data interface according to said second clock speed; said physical interface element being configured to derive, from a source clock signal, said first clock signal and said second clock signal; and said physical interface element and said data processing element each comprising a clock signal interface by which said second clock signal is provided by said physical interface element to said data processing element.