Patent ID: 9613967
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A method of fabricating a memory device, comprising: providing a substrate having a first region and a second region; forming a plurality of word line sets in the substrate in the first region, wherein each of word line sets has two buried word lines; forming a first dielectric layer on the substrate in the first region; forming a conductive layer on the substrate in the second region, wherein a top surface of the conductive layer is lower than a top surface of the first dielectric layer; forming a second dielectric layer on the substrate conformally; performing a first etching process to remove a portion of the second dielectric layer and a portion of the conductive layer, so as to form a first opening in the conductive layer and the second dielectric layer in the second region, wherein the first opening exposes a surface of the substrate in the second region; performing a second etching process to remove a portion of the substrate in the second region, so as to form a trench in the substrate in the second region, wherein the first opening is located on the trench; forming a third dielectric layer in the trench and the first opening; removing a portion of the first dielectric layer and the third dielectric layer to form a second opening on a remainder of the first dielectric layer and to form a third opening on a remainder of the third dielectric layer; and forming a fourth dielectric layer in the second opening and the third opening.