Patent ID: 9691615
Date: 2017-06-27
CPC Classifications: G03F,H01L

Claim:
1. A method of forming a semiconductor structure comprising: forming a vertical stack of a patterned hard mask layer and a patterned neutral layer overlying the patterned hard mask layer over a transfer layer located over a substrate, wherein the patterned hard mask layer and the patterned neutral layer include a first pattern of trenches exposing portions of the transfer layer; applying a self-assembling material over the transfer layer and the patterned neutral layer; forming a self-assembled self-aligned structure of the self-assembling material across top surfaces of the transfer layer and the patterned neutral layer, the self-assembled self-aligned structure comprising alternating first domains and second domains composed of first and second components of the self-assembling material, respectively; forming a second pattern of the first domains by removing the second domains selective to the first domains; patterning the patterned neutral layer and the patterned hard mask layer by employing portions of the first domains not intersecting the trenches as an etch mask; patterning the transfer layer employing remaining portions of the patterned hard mask layer as an etch mask to provide a patterned transfer layer; and forming tone-inversion layer portions by filling the spaces between the patterned transfer layer with a tone-inversion material.