Patent ID: 9619207
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. Galois-field reduction circuitry for reducing a Galois-field expansion value using an irreducible polynomial, wherein reducing said Galois-field expansion value yields a Galois-field reduction value having a reduced-field width, the Galois-field reduction circuitry comprising: a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective expansion bit position, wherein each memory in said plurality of memories has a memory width; gates that select ones of said plurality of memories corresponding to ones of said respective expansion bit positions that contain ‘1’; an exclusive-OR gate for combining outputs of said gates that select; and cascade circuitry for connection of said Galois-field reduction circuitry to at least one other instance of said Galois-field reduction circuitry; whereby: when said reduced-field width exceeds said memory width, said cascade circuitry is used to connect said Galois-field reduction circuitry to said at least on other instance of said Galois-field reduction circuitry.