Patent ID: 9676075
Date: 2017-06-13
CPC Classifications: B24B

Claim:
1. A method for controlling chemical mechanical polishing, comprising: polishing a semiconductor wafer in a chemical mechanical polishing (CMP) tool; measuring a resistance of a resistive pathway through the semiconductor wafer while the semiconductor wafer is undergoing polishing in the CMP tool, wherein the resistive pathway includes at least one through substrate via (TSV) formed in a substrate of the semiconductor wafer, at least one via formed in a metallization level of the semiconductor wafer, a conductive polishing pad of the CMP tool, and a conductive membrane of the CMP tool, wherein the semiconductor wafer is sandwiched between the conductive polishing pad and the conductive membrane of the CMP tool; and terminating the polishing of the semiconductor wafer when the measured resistance reaches a target resistance.