Patent ID: 9729143
Date: 2017-08-08
CPC Classifications: G06F,G09G,G11C,H01L,H03K

Claim:
1. A gate drive on array (GOA) circuit based on low temperature polycrystalline silicon (LTPS) semiconductor thin film transistor (TFT), comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part, a pull-up part, a first pull-down part and a pull-down holding part; the pull-up control part comprises a first transistor, and both a gate and a source are electrically coupled to an output end of an N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to a first node; the pull-up part comprises a second transistor, and a gate thereof is electrically coupled to the first node, and a source is electrically coupled to a first clock driving signal, and a drain is electrically coupled to an output end; the pull-down holding part is electrically coupled to the first node, the output end, a DC constant high voltage level, and a first, a second and a third DC constant low voltage levels; the pull-down holding part utilizes a high/low voltage reverse design and comprises: a third transistor, and both a gate and a source of the third transistor are electrically coupled to the DC constant high voltage level, and a drain is electrically coupled to a source of a fifth transistor; a fourth transistor, and a gate of the fourth transistor is electrically coupled to the drain of the third transistor, and a source is electrically coupled to the DC constant high voltage level, and a drain is electrically coupled to a second node; the fifth transistor, and a gate of the fifth transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the third transistor, and a drain is electrically coupled to the first DC constant low voltage level; a sixth transistor, and a gate of the sixth transistor is electrically coupled to the first node, and a source is electrically coupled to the second node, and a drain is electrically coupled to a source of an eighth transistor; the eighth transistor, and the gate of the eighth transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the sixth transistor, and a drain is electrically coupled to the third DC constant low voltage level; the tenth transistor, and the gate of the tenth transistor is electrically coupled to the second node and a source is electrically coupled to the DC constant high voltage level, and a drain is electrically coupled to the drain of the sixth transistor; a twelfth transistor, and a gate of the twelfth transistor is electrically coupled to the second node, and a drain is electrically coupled to the first node, and a source is electrically coupled to the second DC constant low voltage level; a thirteenth transistor, and a gate of the thirteenth transistor is electrically coupled to the second node, and a drain is electrically coupled to the output end, and a source is electrically coupled to the first DC constant low voltage level; the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, provide positive high voltage levels, employed to control activations of the twelfth transistor and the thirteenth transistor; the eighth transistor constructs a reverse bootstrap of negative voltage level in a functioning period, employed to provide a lower voltage level to the second node in the functioning period; the DC constant high voltage level is utilized to provide a proper high voltage level to the second node in a non-functioning period to maintain the first node and the output end at low voltage level; the first pull-down part is electrically coupled to the first node, a second clock driving signal and the second DC constant low voltage level, and the pull-down part pulls down a voltage level of the first node to the second DC constant low voltage level according to the second clock driving signal; the first pull-down part comprises a fourteenth transistor, and a gate of the fourteenth transistor is electrically coupled to the second clock driving signal, and a source is electrically coupled to the first node, and a drain is electrically coupled to the second DC constant low voltage level; the third DC constant low voltage level being smaller than the second DC constant low voltage level, which is in turn smaller than the first DC constant low voltage level, wherein the pull-down holding part further comprises a ninth transistor, and a gate of the ninth transistor is coupled to the first node, and a source is electrically coupled to the gate of the tenth transistor, and a drain is electrically coupled to the third DC constant low voltage level; an eleventh transistor, and both a gate and a source of the eleventh transistor are electrically coupled to the DC constant high voltage level, and a drain is electrically coupled to the gate of the tenth transistor; the gate of the tenth transistor is disconnected with the second node.