Patent ID: 9564246
Date: 2017-02-07
CPC Classifications: G11C

Claim:
1. A semiconductor device, comprising: memory blocks including main data storage units and cycling information storage units; a circuit group that performs a wear leveling operation on the memory blocks; and a control circuit that sets a threshold value based on the cycling information, and controls the circuit group so that the wear leveling operation is performed based on the set threshold value, wherein the circuit group includes: a page buffer that receives the cycling information stored in the memory blocks based on a page buffer control signal output from the control circuit; a column decoder that receives the cycling information from the page buffer based on a column address output from the control circuit: and an input/output unit that transmits a command signal and an address received from the outside to the control circuit, transmits data received from the outside to the column decoder, and transmits the cycling information received from the column decoder to the control circuit.