Patent ID: 9665934
Date: 2017-05-30
CPC Classifications: G06T,H04N

Claim:
1. A fault detection circuit for detecting faults in a video sequence, the fault detection circuit comprising: a multiple input signature register (MISR) that includes a linear feedback shift register (LFSR) with a tap polynomial and a seed register, the MISR being configured to sequentially receive multiple bits of pixel data for each pixel in a predetermined or programmable frame region for each video frame of the video sequence, the MISR being configured to receive a data valid signal at a clock input to the MISR in conjunction with each pixel in the predetermined or programmable frame region to read the corresponding pixel data and shift the MISR, and the MISR being configured to hold a frame signature value for the predetermined or programmable frame region of each video frame in conjunction with receiving a frame end signal for the corresponding video frame; a multiple signature storage buffer (MSSB) configured to store at least two frame signature values, the MSSB being configured to store a current frame signature value held by the MISR in response to receiving the frame end signal for the corresponding video frame, and the MSSB being configured to store a reference frame signature value related the current frame signature value; and a signature comparator configured to compare the current and reference frame signature values stored by the MSSB to determine if a fault condition exists for one or more frames in the video sequence.