Patent ID: 9710274
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. A method of executing an instruction in a processing unit, the method comprising: concurrently forwarding the instruction to fixed point and auxiliary decode logic respectively associated with fixed point and auxiliary execution units in the processing unit, wherein the processing unit is of a type including a designed, verified and tested core, wherein the fixed point execution unit is disposed in the core and the auxiliary execution unit is external to the core, and wherein the auxiliary execution unit is implemented using an application specific hardware design and has a higher priority than the fixed point execution unit; concurrently decoding the instruction with the fixed point decode logic and the auxiliary decode logic; in response to the fixed point decode logic decoding the instruction as a valid instruction for the fixed point execution unit and the auxiliary decode logic decoding the instruction as an invalid instruction for the auxiliary execution unit, forwarding the instruction to the fixed point execution unit for execution thereby; in response to the fixed point decode logic decoding the instruction as an invalid instruction for the fixed point execution unit and the auxiliary decode logic decoding the instruction as a valid instruction for the auxiliary execution unit, forwarding the instruction to the auxiliary execution unit for execution thereby; in response to the fixed point decode logic decoding the instruction as a valid instruction for the fixed point execution unit and the auxiliary decode logic decoding the instruction as a valid instruction for the auxiliary execution unit, asserting an invalidate signal to the fixed point decode logic to disable forwarding of the instruction to the fixed point execution unit and forwarding the instruction to the auxiliary execution unit for execution thereby; in response to the fixed point decode logic decoding the instruction as an invalid instruction for the fixed point execution unit and the auxiliary decode logic decoding the instruction as an invalid instruction for the auxiliary execution unit, signaling an illegal instruction program interrupt; and with a first and a second rename logic respectively associated with the fixed point and auxiliary decode logic, applying different renaming operations to the instruction based upon respective register architectures of respective register files of the fixed point and auxiliary execution units.