Patent ID: 9601351
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising the steps of: forming, in a semiconductor substrate having at least two surfaces opposite to each other, a vertical transistor comprising a gate electrode and a source layer at one surface side of the two surface sides of the semiconductor substrate, and comprising a drain layer at the other surface side of the semiconductor substrate; forming a first interlayer dielectric film over the one surface of the semiconductor substrate; forming, in the first interlayer dielectric film, a contact coupled with the source layer of the vertical transistor; forming, over the first interlayer dielectric film, a first source wiring overlapped with the vertical transistor as viewed in plan and coupled with the contact, and further making openings in the first source wiring; and conducting a treatment with a reducing gas, thereby subjecting the vertical transistor to a first reducing treatment wherein the semiconductor substrate comprises a power control region where the vertical transistor is to be formed, and a logic region where a logic circuit is to be formed, the method further comprising, before the step of forming the first interlayer dielectric film, a step of: forming a planar MOS transistor configured as the logic circuit in the one surface of the logic region of the semiconductor substrate, the method further comprising, after the step of conducting the first reducing treatment, the steps of: forming a second interlayer dielectric film over the first interlayer dielectric film and the source wiring; burying a first via to be coupled with the first source wiring in the second interlayer dielectric film; forming, over the second interlayer dielectric film, a second source wiring to be positioned in the power control region and to be coupled with the first via, and a logic wiring to be positioned in the logic region; and conducting a treatment with a reducing gas, thereby subjecting the vertical transistor to a second reducing treatment, the logic wiring being lower in density than the second source wiring.