Patent ID: 9746515
Date: 2017-08-29
CPC Classifications: G01R,G06F

Claim:
1. An integrated circuit comprising: (a) an address and command port having a data input and output lead, a clock in lead, a trace out lead, a trace clock out lead, a trace data in lead, a test data in lead, a test mode select out lead, a test clock out lead, and a test data out lead; (b) plural trace circuits, each trace circuit having a trace input connected to the trace out lead, a trace clock input connected to the trace clock out lead, a trace data output connected to the trace data in lead, a test data in input, a control input, and a test data out output; and (c) plural TAP domain circuits, each TAP domain circuit having a test data input connected to the test data in lead, a test mode select input connected to the test mode select out lead, a test clock input connected to the test clock out lead, a test data output connected to the test data out lead, a test data in output coupled to the test data in input of the trace circuitry, a control output coupled to the control input of the trace circuitry, and a test data out input coupled to the test data out output of the trace circuitry, there being one TAP domain circuit for each trace circuit.