Patent ID: 9589609
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A static random access memory (RAM) comprising: a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines; a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line; a column switch having transistor pairs which connect one of the plurality of bit line pairs, which is selected, to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of writing of the memory cell, wherein a well of the transistor pairs of the column switch is an independent well which is separated from wells of other transistors, and connected to the drive line so as to prevent an erroneous write to the memory cells of non-selected columns.