Patent ID: 9658278
Date: 2017-05-23
CPC Classifications: G01R,H01L

Claim:
1. A semiconductor device comprising: a first layer; a second layer configured to overlap with the first layer at a plurality of positions wherein a first position of the plurality of positions is separated from a second position of the plurality of positions by a non-overlapping portion of the first layer or a non-overlapping portion of the second layer; a plurality of first layer contacts configured to be selectively activated to test the first layer for a first layer leakage current; and a plurality of second layer contacts configured to be selectively activated to test the second layer for a second layer leakage current, wherein the first layer contacts are arranged on the first layer on a first side and a second side of the plurality of positions at which the second layer overlaps with the first layer, the second layer contacts are arranged on the second layer on a third side and a fourth side of the plurality of positions at which the second layer overlaps with the first layer, and a determined first layer leakage current or second layer leakage current is indicative of the presence of a crystal defect in the semiconductor device.