Patent ID: 9640539
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: a substrate; a plurality of gate structures, each the gate structure comprising a gate disposed over the substrate and sidewalls abutting lateral surfaces of the gate; source/drain regions disposed in the substrate adjacent to the gate structures; metal silicide regions on the source/drain regions at a surface of the substrate; a plurality of self-aligned contacts, each the self-aligned contact being disposed on an instance of the source/drain regions and abutting at least one instance of the gate structures along a height of the instance of the gate structure from the metal silicide regions to a top surface of the instance of the gate structure, wherein a top surface of the self-aligned contact is not higher than a top surface of the gate of the instance of the gate structure; a pre-metal dielectric (PMD) layer disposed over the gate structures and over the self-aligned contacts; vias disposed in the PMD layer, such that the vias make electrical connections to at least a portion of the self-aligned contacts; and a plurality of metal interconnects disposed over the vias, the metal interconnects making electrical connections to the vias.