Patent ID: 9543043
Date: 2017-01-10
CPC Classifications: G11C

Claim:
1. A method for testing a non-transitory array fuse block of a semiconductor apparatus, wherein the non-transitory array fuse block of the semiconductor apparatus storing a test program, and when executed by a processor, causes the processor to perform method steps comprising: starting the test program; generating a test source file containing information for accessing all unit fuses of the non-transitory array fuse block; generating a test vector using the test source file, wherein the test vector comprises a pattern of sequentially performing boot-up, rupture, reboot-up, and normal active operations for each of unit fuses of the non-transitory array fuse block; extracting a repair confirmation information by performing a simulation using the test vector; extracting a repair confirmation information expected value from the test source file; and determining a pass or fail by comparing the repair confirmation information to the repair confirmation information expected value.