Patent ID: 9704918
Date: 2017-07-11
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor storage device comprising: a first area including a plurality of memory cells; a second area that is adjacent to the first area in a first direction and does not include a plurality of memory cells; a plurality of first bit lines electrically connected to first ends of the memory cells and extending in the first direction in the first and second areas; a plurality of first source lines electrically connected to second ends of the memory cells and extending in the first direction in the first and second areas; a plurality of second bit lines extending in the first direction in the second area, wherein the second bit lines are extensions of the first bit lines; a plurality of second source lines extending in the first direction in the second area, wherein the second source lines are extension of the first source lines; a plurality of first switch transistors which connect the first bit lines and the second bit lines; and a plurality of second switch transistors which connect the first source lines and the second source lines, wherein with respect to each of the memory cells: wherein the first and second switch transistors comprise a plurality of second cell transistors each including: wherein the first area includes a plurality of first active areas in which a plurality of first cell transistors, each of which is the first cell transistor of one of the memory cells, are formed and which extend in a direction crossing the first direction at a first angle, and wherein the second area includes a plurality of second active areas in which the second cell transistors are formed and which extend in a direction crossing the first direction at a second angle.