Patent ID: 9645792
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. A method for emulating a fused multiply-add operation for a first operand, a second operand, and a third operand, the method comprising: determining, by at least one processor, an intermediate value based at least in part on multiplying the first operand with the second operand; determining, by the at least one processor, at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value; determining, by the at least one processor, an upper value and a lower value, including adding the third operand to one of the upper intermediate value or the lower intermediate value based at least in part on a difference between exponents of the third operand and the intermediate value; and determining, by the at least one processor, an emulated fused multiply-add result for the first operand, the second operand, and the third operand by adding the upper value and the lower value.