Patent ID: 9672162
Date: 2017-06-06
CPC Classifications: G06F

Claim:
1. A data processing system, the data processing system comprising: a host processor that executes an operating system; an accelerator operable to process data under the control of the operating system executing on the host processor; and memory for storing data to be used or processed by or generated by the accelerator, the memory being configurable to have both protected memory regions that are not readable by the operating system when it is operating in a non-secure mode and non-protected memory regions that are readable by the operating system when it is operating in a non-secure mode; wherein: the accelerator can be switched between a normal mode of operation in which the accelerator has read and write access to data that is stored in non-protected memory regions but write-only access to any protected memory regions, and a protected mode of operation in which the accelerator has read and write access to data that is stored in protected memory regions but only has read-only access to any non-protected memory regions; and the data processing system further comprises a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation; wherein the accelerator's access to the memory is controlled by using bus transaction filtering or by using memory address virtualisation mapping in a memory management unit (MMU), wherein MMU stage two page tables are used for both normal mode and protected mode operation and wherein the same MMU stage two page tables are used for both normal mode and protected mode operation, but the interpretation of the page table access permissions depends upon the mode an accelerator processing operation is being performed in.