Patent ID: 9576972
Date: 2017-02-21
CPC Classifications: H01L

Claim:
1. A manufacturing method of a semiconductor device, comprising: forming two stacked structures above a substrate, wherein each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer, the gate layers and the gate insulating layers are alternately disposed, and the top insulating layer is disposed on the gate layers and the gate insulating layers; forming a charge trapping structure and a channel layer on a lateral surface of each of the stacked structures, wherein the charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers; etching part of each of first dielectric layers and etching part of each of second dielectric layers to expose part of the channel layer; and forming a landing pad layer on the first dielectric layers and the second dielectric layers to connect the channel layer.