Patent ID: 9748385
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor structure, said method comprising: providing a structure on a surface of a substrate, said structure comprising a semiconductor channel material structure extending vertically upwards from a surface of a silicon germanium alloy layer, wherein a dielectric cap is located on a topmost surface of said semiconductor channel material structure, a bottom spacer is located on each side of said semiconductor channel material structure and in direct contact with said silicon germanium alloy layer, and a top spacer is located on each side of said semiconductor channel material structure and is spaced apart from said bottom spacer; forming a gate structure on each side of said semiconductor channel material structure, wherein each gate structure comprises a gate dielectric material portion directly contacting an exposed sidewall surface of said semiconductor channel material structure; forming a middle-of-the-line (MOL) dielectric material adjacent said gate structures and said semiconductor channel material structure; removing said dielectric cap to expose said topmost surface of said semiconductor channel material structure; recessing said semiconductor channel material structure to provide a semiconductor channel region; forming a contact opening in said MOL dielectric material that exposes another surface of said silicon germanium alloy layer; removing said silicon germanium alloy layer to provide a cavity; and forming a conductive material in said contact opening, said cavity and atop said semiconductor channel region, wherein said conductive material in said contact opening and said cavity provides a bottom Schottky contact source/drain region containing a vertically extending portion and a base portion, and wherein said conductive material formed atop said semiconductor channel region forms a top Schottky contact source/drain region.