Patent ID: 9583480
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. An integrated circuit comprising: a substrate; at least one buffer layer formed over the substrate; a GaN channel layer formed over the at least one buffer layer; a barrier layer formed over the GaN channel layer; and an isolation region that isolates a first portion of the barrier layer for an enhancement mode transistor device from a second portion of the barrier layer for a depletion mode transistor device, the first and second portions of the barrier layer each having respective gate contact recesses, the enhancement mode transistor device and the depletion mode transistor device each having a threshold voltage; a first gate contact disposed at least partially in the gate contact recess of the first portion of the barrier layer for the enhancement mode transistor device; and a second gate contact disposed at least partially in the gate contact recess of the second portion of the barrier layer for the depletion mode transistor device; wherein the gate contact recess of the first portion of the barrier layer and the gate contact recess of the second portion of the barrier layer are formed with respective thicknesses such that the threshold voltage of the enhancement mode transistor device and the threshold voltage of the depletion mode transistor device are approximately equal in absolute value.