Patent ID: 9564354
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A via-hole etching method, comprising: forming a structure for via-hole etching, comprising a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away a remaining thickness of the gate insulating layer uncovering the low-temperature poly-silicon layer and ending the second etching process so as to retain the low-temperature poly-silicon layer that is uncovered; and removing the mask layer to form a via-hole structure; wherein the second etching process is dry etching with an organic etching gas, which is a mixed gas including CF