Patent ID: 9729145
Date: 2017-08-08
CPC Classifications: G06F,H03K

Claim:
1. A circuit, comprising: a first power supply terminal connected to a first p-type metal oxide semiconductor transistor; a second power supply terminal connected to a second p-type metal oxide semiconductor transistor; an output node connected between the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor; a decision circuit connected to the first power supply terminal and the second power supply terminal, wherein the output node powers the decision circuit and where the power to the decision circuit is substantially the same as the power from the output node, and wherein gate terminals of the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor are complementarily and actively controlled by the decision circuit; and a biasing circuit connected to the decision circuit, wherein the biasing circuit is configured to modulate the decision speed of the decision circuit to a fast mode wherein the first power supply terminal supplies power to the circuit, and to modulate the decision speed of the decision circuit to a slow mode wherein the second power supply terminal supplies power to the circuit; and wherein the output node powers the biasing circuit.