Patent ID: 9645937
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. A processing unit, comprising: a processor core including: a cache memory including a cache array and a store queue for buffering store operations to be serviced with respect to the cache array; and marking logic within at least one of set including the processor core and the cache memory, wherein the marking logic selectively marks the store operation as a high priority store operation, wherein the marking logic marks the store operation as a high priority store operation in response to detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority, and wherein the marking logic refrains from marking the store operation as a high priority store operation in response to not detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority; wherein the cache memory expedites handling of the store operation in the store queue in response to the store operation being marked as a high priority store operation and otherwise refrains from expediting handling of the store operation in the store queue.