Patent ID: 9704787
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A power semiconductor package comprising: a power transistor having a first power electrode and a gate electrode on a top surface of said power transistor, and a second power electrode on a bottom surface of said power transistor; said second power electrode being configured for attachment to a partially etched leadframe segment, said partially etched leadframe segment having a thickness across an entire length thereof and being configured for attachment to a substrate that is separate from said power semiconductor package; a first conductive clip having a substantially horizontal portion situated over said first power electrode and a substantially vertical portion connected to said substantially horizontal portion, said first conductive clip being coupled to said first power electrode and being configured for attachment to said substrate that is separate from said power semiconductor package by said substantially vertical portion without using a leadframe; and a second conductive clip configured for coupling said gate electrode to said substrate; wherein said substantially horizontal portion of said first conductive clip has a thickness that is greater than said thickness of said partially etched leadframe segment.