Patent ID: 9595972
Date: 2017-03-14
CPC Classifications: H03L

Claim:
1. A digital phase locked loop arrangement with master clock redundancy, comprising: a plurality of master clock sources in the form of stable oscillators generating local clock signals; a digital phase locked loop (DPLL) including a digital controlled oscillator (DCO) driven by one of said plurality of master clock sources; a first multiplexer for selecting one of a plurality of reference clock signals as an input to said DPLL; clock monitors for monitoring a performance of said plurality of master clock sources; a second multiplexer for selecting one of said master clock sources to drive said DCO; and a controller programmed to control said second multiplexer to switch said DCO from being driven by a previously selected one of said master clock sources to a newly selected one of said master clock sources upon loss of a clock signal from said previously selected master clock source or when the performance of said previously selected one of said master clock sources falls below a predetermined acceptable level.