Patent ID: 9584542
Date: 2017-02-28
CPC Classifications: H04K,H04L,H04W

Claim:
1. An apparatus for reducing the probability of a relay attack, comprising: a microcontroller; a receiver wherein the receiver receives a challenge message from a verifier, the challenge message having a challenge message frequency at a first challenge message frequency during a first time slot; and a transmitter wherein the transmitter transmits a response message to the verifier, the response message having a response message frequency at a first response message frequency during the first time slot, the first response message frequency being different than the first challenge message frequency; wherein the probability of the relay attack is reduced as a result of the first response message frequency being different than the first challenge message frequency; wherein the challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slot, the second challenge message frequency being different than the second response message frequency; wherein the probability of the relay attack is reduced as a result of the second response message frequency being different than the second challenge message frequency; wherein the frequencies at which the response messages are sent are negotiated between the verifier and the transmitter prior to the first time slot; and wherein the time slots when the response messages are sent are negotiated between the verifier and the transmitter prior to the first time slot.