Patent ID: 9704971
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. A method comprising: providing a gate structure on a silicon-on-insulator (SOI) layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure, wherein the first pair of spacers have upper surfaces parallel to the SOI layer and side surfaces of the first pair of spacers inclined from the upper surfaces of the first pair of spacers, such that each of the inclined side surfaces of the first pair of spacers forms an acute angle with the SOI layer and each of the inclined side surfaces of the first pair of spacers forms an obtuse angle with the upper surfaces of the first pair of spacers; forming a second pair of spacers on the upper surface of the first pair of spacers, but not on the inclined side surfaces of the first pair of spacers, adjacent to and on the opposite sides of the gate structure, wherein upper surfaces and lower surfaces of the second pair of spacers are parallel to the upper surfaces of the first pair of spacers and the lower surfaces of the second pair of spacers contact the upper surfaces of the first pair of spacers; and forming a pair of faceted raised source/drain structures on the SOI layer, wherein each of the faceted raised source/drain structures has a corner formed by two facets contacting an interface of the upper surface of a corresponding one of the first pair of spacers and the lower surface of a corresponding one of the second pair of spacers, and wherein portions of the pair of faceted raised source/drain structures contact the inclined side surfaces of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.