Patent ID: 9594867
Date: 2017-03-14
CPC Classifications: G06F,H01L

Claim:
1. A method for detecting actual hotspot regions in an initial layout pattern and generating detected actual hotspot data operably configured for use in the subsequent production of a lithographic mask that is utilized in a semiconductor fabrication process to fabricate an integrated circuit, said method using a hotspot pattern including at least one opaque portion and at least one transparent portion disposed within a window boundary, and at least one of an edge tolerance range and an unspecified region, the method comprising, using a processor to perform the following: generating a plurality of pattern topologies based on corresponding alternative block arrangements defined by said hotspot pattern, each said pattern topology comprising a plurality of block tiles and a plurality of space tiles disposed in a unique pattern arrangement; extracting a plurality of critical design rules from the plurality of pattern topologies such that each of the plurality of pattern topologies is represented by at least one said critical design rule; grouping the critical design rules into at least two rule groups, where a first said rule group includes first critical design rules from each of said plurality of pattern topologies, and a second group includes second critical design rules from at least some of said plurality of pattern topologies; performing first DRC processing on said initial layout pattern using said first critical design rules; generating a reduced layout pattern by modifying said initial layout pattern to include only regions identified as satisfying at least one first critical design rule during said first DRC processing; performing second DRC processing on said reduced layout pattern using said second critical design rules; and generating said detected actual hotspot data using results from said second DRC processing.