Patent ID: 9548138
Date: 2017-01-17
CPC Classifications: G11C

Claim:
1. A test method for testing a memory device including a memory array, the memory array including a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines, the test method including: in testing a first word line of the word lines, charging a first bit line of the bit lines to test a single bit of a first half of a first symmetric memory cell adjacent to the first bit line; and charging a second bit line of the bit lines to test a single bit of a second half of a second symmetric memory cell adjacent to the second bit line; and in testing a second word line of the word lines, charging the first bit line of the bit lines to test a single bit of the second half of a third symmetric memory cell adjacent to the first bit line; and charging the second bit line of the bit lines to test a single bit of the first half of a fourth symmetric memory cell adjacent to the second bit line; wherein in testing each of the word lines, each of the bit lines is charged once.