Patent ID: 9711471
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor device package comprising: a circuit chip having a semiconductor substrate with an upper substrate surface, and further having a plurality of interconnect layers stacked on the upper substrate surface of the semiconductor substrate along a given stacking direction, said semiconductor substrate incorporating electrically doped regions having electrical resistivity values of less than 10 Ohm·cm, and said stack of interconnect layers incorporating metal tracks and vias configured to electrically connect doped regions of the semiconductor substrate; bond pads located at an upper stack surface of the stack of interconnect layers opposite the semiconductor substrate, and electrically connected to at least some of the tracks and vias, the upper substrate surface and the upper stack surface both extending generally perpendicular to the stacking direction; and a wafer level chip scale package located on the upper stack surface, said wafer level chip scale package incorporating a plurality of under-bump metallization areas each provided with a respective solder ball dedicated for connecting the semiconductor device package to an external support, and said wafer level chip scale package further incorporating electrically conducting segments extending parallel to the upper stack surface and each connecting at least one of the bond pads to at least one of the under-bump metallization areas; wherein the interconnect layers and the substrate are devoid of any material portion having an electrical resistivity less than 10 Ohm·cm within at least one exclusion cylinder extending parallel to the stacking direction from a first one of the under-bump metallization areas, and the substrate is devoid of electrical doping or has mutually compensating electrical doping loads within the exclusion cylinder.