Patent ID: 9583500
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A monolithic three-dimensional memory device comprising: a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate; at least one dielectric material layer overlying the lower stack structure; an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the at least one dielectric material layer; a memory opening extending through the second stack, the at least one dielectric material layer, and the first stack; a memory film and at least one semiconductor channel located within the memory opening; and at least one via contact structure vertically extending through the upper stack structure, the at least one dielectric material layer, and a portion of the lower stack structure, and electrically shorted to at least one conductive structure located in, or underneath, the first stack; wherein the at least one via contact structure comprises: wherein the at least one dielectric material layer comprises: wherein each of the at least one via contact structure has a greater lateral extent within the inter-stack dielectric material layer than within the second-stack-base dielectric layer.