Patent ID: 9536878
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first fin on a substrate; a field insulating layer disposed on portion of sidewalls of the first fin and on the substrate; an interlayer dielectric layer on the field insulating layer and including a trench exposing at least a portion of the field insulating layer; a spacer on a sidewall of the trench; a deposition insulating layer on the spacer in the trench and on the portion of the field insulating layer; a gate insulating layer in the trench and on the deposition insulating layer therein; and a metal gate on the gate insulating layer in the trench, wherein a first height from a top surface of the first fin to a top surface of the metal gate is smaller than a second height from the field insulating layer to the top surface of the first fin.