Patent ID: 9716491
Date: 2017-07-25
CPC Classifications: G06F,H03K

Claim:
1. A programmable logic device (PLD), comprising: a plurality of programmable logic blocks (PLBs), wherein at least one of the PLBs comprises first and second logic cells, each logic cell comprising a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT, and the associated mode logic is configured to use a single physical output port to provide a logic cell output signal from its respective logic cell corresponding to an operational mode selected from a logic function operational mode, a ripple arithmetic operational mode, and an extended logic function operational mode wherein, for at least one of the first and the second logic cells the selected operational mode is configured to be the ripple arithmetic operational mode, the associated mode logic comprises carry logic that is configured to receive one or more of a carry input signal, a generate signal, and the LUT output signal, and to provide a carry output signal and the LUT is configured to receive a value of a generate register and provide the generate signal to the associated mode logic.