Patent ID: 9680436
Date: 2017-06-13
CPC Classifications: H03G,H03H,H04B,H04L

Claim:
1. A receiver for a serial link, the receiver having an analog input and comprising: an analog front end connected to the analog input and having an output and an adjustable DC gain; a data slicer having an input coupled to the output of the analog front end, and an output; an error slicer having an input coupled to the output of the analog front end, and an output; and a processor circuit coupled to the outputs of the data slicer and the error slicer and configured to iteratively adjust the DC gain based on a respective estimate of a zeroth channel tap value until the zeroth channel tap value falls into a set range of values, wherein the estimating of the zeroth channel tap value comprises iteratively updating the estimated zeroth channel tap value according to the equation: wherein: