Patent ID: 9563400
Date: 2017-02-07
CPC Classifications: G06F

Claim:
1. An integrated circuit chip for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections, the integrated circuit chip comprising: one or more electronic circuits configured to generate a first implicit bit correction term for a base-2 multiplier with an implicit bit that is one and a second implicit bit correction term for the base-2 multiplier with an implicit bit that is zero; one or more electronic circuits configured to generate a third implicit bit correction term for a base-2 multiplicand with an implicit bit that is one and a fourth implicit bit correction term for the base-2 multiplicand with an implicit bit that is zero; one or more electronic circuits configured to determine a value of a first implicit bit of the base-2 multiplier and a value of a second implicit bit of the base-2 multiplicand; one or more electronic circuits configured to receive a plurality of partial products of a product of the base-2 multiplier and the base-2 multiplicand; one or more electronic circuits configured to add, the plurality of partial products of the base-2 multiplier and the base-2 multiplicand in an adder array; one or more electronic circuits configured to append the first actual implicit bit correction term to the immediate left of a first addend to a first adder in the adder array such that a number of bits in the first actual implicit bit correction term does not exceed a number of bit positions between a left-most bit of the first addend and a left-most bit of a second addend to the first adder; and one or more electronic circuits configured to append the second actual implicit bit correction term to the immediate left of a third addend to a second adder in the adder array such that a number of bits in the second actual implicit bit correction term does not exceed a number of bit positions between a left-most bit of the first addend and a left-most bit of a fourth addend to the second adder.