Patent ID: 9568530
Date: 2017-02-14
CPC Classifications: G01M,G01R,H04B

Claim:
1. A cable testing arrangement, comprising: a testing module comprising a pattern generator to be coupled with an active cable having a plurality of lanes to generate a test pattern to be transmitted over the active cable, wherein the test pattern is to be transmitted at least over two or more lanes of the active cable that are concatenated in loopback connections, and a processing unit to be coupled with the active cable to process a result of the transmission of the test pattern over the active cable, wherein to process includes to determine a bit error rate (BER) associated with the transmission of the test pattern over the active cable; and a plurality of testing cables to concatenate the two or more of the plurality of lanes of the active cable in the loopback connections, to enable the transmission of the test pattern over the two or more lanes of the active cable concatenated in the loopback connections.