Patent ID: 9564199
Date: 2017-02-07
CPC Classifications: G11C,H01L

Claim:
1. A method of operating a volatile memory array having anode lines, cathode lines, a first set of data storing thyristors having anodes coupled to anode lines and having cathodes coupled to a first cathode line, a first set of dummy vertical thyristors having anodes coupled to anode lines and having cathodes coupled to a second cathode line, the first cathode line being coupled to a first input terminal of a sense amplifier, the second cathode line being coupled to a second input terminal of the sense amplifier, the method to read a selected thyristor coupled to the first cathode line, comprising performing steps of: pre-charging each of the first and second cathode lines to zero volts; applying a current source to the second terminal of the sense amplifier; determining whether (a) potential of the first cathode line rose above the second cathode line or (b) potential of the second cathode line rose above the first cathode line.