Patent ID: 9620243
Date: 2017-04-11
CPC Classifications: G11C

Claim:
1. A test system comprising: a plurality of memory chips and a tester external to the plurality of memory chips and configured to generate a test mode register set (TMRS) signal, wherein the plurality of memory chips comprises a first memory chip and a second memory chip, the first memory chip includes a first memory cell array including memory cells susceptible to a first failure attribute, a first storage unit that stores first failure attribute information, and first built-in self-test (BIST)/built-in self-stress (BISS) circuitry, and the second memory chip includes a second memory cell array including memory cells susceptible to a second failure attribute different from the first failure attribute, a second storage unit that stores second failure attribute information, and second BIST/BISS circuitry, in response to the TMRS signal, the first storage unit provides the first failure attribute information to the tester and the second storage unit provides the second failure attribute information to the tester, and thereafter, the first BIST/BISS circuitry, the second BIST/BISS circuitry and tester are collectively configured in response to the first failure attribute information and second failure attribute information to simultaneously apply a first stress test associated with the first failure attribute to the first memory chip, and a second stress test associated with the second failure attribute and different from the first stress test to the second memory cell chip.