Patent ID: 9697895
Date: 2017-07-04
CPC Classifications: G11C

Claim:
1. An integrated circuit comprising: a plurality of first wiring lines; a plurality of second wiring lines intersecting with the plurality of first wiring lines; a plurality of resistive change memory elements provided in cross regions of the plurality of first wiring lines and the plurality of second wiring lines, each of which includes a first electrode connected to a corresponding one of the first wiring lines, a second electrode connected to a corresponding one of the second wiring lines, and a resistive change layer provided between the first electrode and the second electrode, and in each of which a resistive state between the first electrode and the second electrode can be programmed from one of a first resistive state and a second resistive state, which has a larger resistance value than the first resistive state, to the other; a driver configured to drive the plurality of first wiring lines and the plurality of second wiring lines; and a verification circuit connected to the plurality of first wiring lines or the plurality of second wiring lines, and comparing resistance of the resistive change memory elements with a first determination value, wherein the driver limits current, which flows in the resistive change memory elements, by using one of a first limit current value and a second limit current value that is larger than the first limit current value, and changes a resistive state of the resistive change memory elements from the first resistive state to the second resistive state.