Patent ID: 9570477
Date: 2017-02-14
CPC Classifications: G02F,H01L

Claim:
1. A thin film transistor array panel comprising: a substrate including a display area and a periphery area adjacent to the display area; a thin film transistor disposed in the display area and including a drain electrode; a passivation layer covering the thin film transistor; a first partition disposed on the passivation layer and having a contact portion disposed on the drain electrode; a second partition disposed on the passivation layer of the periphery area; a color filter formed on the passivation layer and disposed in a region defined by the first partition; an organic capping layer formed on the first partition, the second partition, and the color filter; and a pixel electrode formed on the organic capping layer, and connected to the drain electrode through the contact portion formed in the passivation layer and the first partition; a first light blocking member disposed in the display area; and a second light blocking member disposed in the periphery area including a protrusion, wherein the protrusion of the second light blocking member overlaps the second partition and the first light blocking member overlaps the first partition.