Patent ID: 9608641
Date: 2017-03-28
CPC Classifications: H03L

Claim:
1. An all-digital phase-locked loop comprising: a reference phase generator configured to receive a digital signal and split the received digital signal into an integer part and a fractional part; an estimator block configured to determine an estimated control signal; a digital-to-time converter configured to (i) receive the estimated control signal, (ii) receive a reference clock signal, and (iii) derive a delayed reference clock signal based on the reference clock signal and the estimated control signal; and a time-to-digital converter configured to (i) receive the delayed reference clock signal, (ii) receive a desired clock signal phase, and (iii) derive a fractional phase error based on the delayed reference clock signal and the desired clock signal phase, wherein the estimator block is further configured to receive the fractional phase error, and wherein determining the estimated control signal comprises: