Patent ID: 9721920
Date: 2017-08-01
CPC Classifications: H01L,H01Q

Claim:
1. A method for manufacturing an embedded chip package, the method comprising forming a first layer of electrically conductive lines over a substrate to form a pre-formed via arrangement; wherein the first layer of electrically conductive lines are substantially the same length; placing the pre-formed via arrangement perpendicularly next to a first side of a chip arrangement comprising a chip, the chip comprising a chip bottom side disposed directly over at least one solder structure and a chip top side comprising one or more contact pads, wherein one or more of the electrically conductive lines of the first layer are arranged proximate to a first side wall of the chip and wherein the pre-formed via arrangement is turned so that the electrically conductive lines are facing the first side wall of the chip; forming a second layer of electrically conductive lines at a second side of the chip arrangement; wherein the first layer of electrically conductive lines comprises a first width, and wherein the second layer of electrically conductive lines comprises a second width, and wherein the first width and the second width are different; and subsequent to the placing the pre-formed via arrangement next to the chip arrangement, forming one or more electrical interconnects over the chip arrangement substantially perpendicular to the electrically conductive lines and substantially parallel to a top side of the chip so as to electrically connect at least one electrically conductive line to at least one of the contact pads.