Patent ID: 9717051
Date: 2017-07-25
CPC Classifications: H04W,Y02D

Claim:
1. A method for controlling operation of hardware processing components on a computing device, the method comprising: receiving a data packet at the computing device; processing the data packet with a plurality of processors to display the data packet; monitoring movement of the data packet among the processors; generating, based upon the monitoring, time indications, each of the time indications indicating when a corresponding one of the processors will receive the data packet; monitoring a frame processing rate of each of the plurality of processors; and adjusting, in response to a particular time indication indicating a particular processor is going to receive the data packet, a frequency of the particular processor based upon the frame processing rate of a processor that previously processed the data packet; initiating an interrupt when an application processor receives the data packet; obtaining type and size information about the data packet; adjusting the frequency of each of the processors based upon the type and size information so that each of the processors completes its processing of the data packet within a particular time window; and receiving Vsync signals that define boundaries of the particular time window.