Patent ID: 9602136
Date: 2017-03-21
CPC Classifications: H03M

Claim:
1. A bit group-unit interleaver, comprising: a first memory configured to store a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; and a second memory configured to store the interleaved codeword corresponding to a modulator for 256-symbol mapping, wherein the interleaving is performed using the following equation using permutation order: where X wherein the permutation order corresponds to an interleaving sequence represented by the following interleaving sequence: {13 121 137 29 27 1 70 116 35 132 109 51 55 58 11 67 136 25 145 7 75 107 45 21 127 52 90 22 100 123 69 112 155 92 151 59 5 179 44 87 56 139 65 170 46 0 124 78 166 8 61 97 120 103 4 19 64 79 28 134 93 86 60 135 126 53 63 14 122 17 150 76 42 39 23 153 95 66 50 141 176 34 161 26 106 10 43 85 131 2 147 148 144 54 115 146 101 172 114 119 3 96 133 99 167 164 9 142 68 149 94 83 16 175 73 38 143 159 130 84 169 18 138 102 72 47 32 160 82 81 168 30 12 173 156 158 125 98 62 178 48 163 117 110 91 37 80 105 31 174 111 49 113 108 74 157 128 24 118 40 88 177 154 6 162 129 77 36 165 20 89 140 15 33 104 152 71 171 57 41} and wherein a modulated signal output from the modulator corresponds to a transmission signal, the transmission signal being transmitted to a reception device.