Patent ID: 9548375
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method for fabricating a vertical diode, comprising: providing a substrate; forming a bottom N-type implanted region in the substrate; forming a high-voltage N-type well region in the substrate and on the bottom N-type implanted region, wherein the high-voltage N-type well region extends from a top surface of the substrate downward to a depth, and wherein the high-voltage N-type well region has a first N-type dopant concentration; forming an N-type well region in the high-voltage N-type well region, wherein the N-type well region has a second N-type dopant concentration that is higher than the first N-type dopant concentration; forming a plurality of isolation structures on the top surface of the substrate to define an anode region and a cathode region, wherein the bottom N-type implanted region under the high voltage N-type well region correspond to the anode region, and wherein the bottom N-type implanted region directly contacts the high-voltage N-type well region; forming two P-doped regions in the high-voltage N-type well region, wherein the P-doped regions are spaced apart from each other; forming an N-type heavily doped region in the N-type well region, wherein the N-type heavily doped region has a third N-type dopant concentration that is higher than the second N-type dopant concentration; forming an anode electrode electrically connected to the P-doped regions and the high voltage N-type well region between the P-doped regions; forming a cathode electrode electrically connected to the N-type heavily doped region; and wherein a height of the bottom N-type implanted region is 5-15% of the depth of the high-voltage N-type well region.