Patent ID: 9564884
Date: 2017-02-07
CPC Classifications: G01R,H03K

Claim:
1. A wear-sensing integrated circuit comprising: an aging pattern generator that generates a plurality of patterns to accelerate wear of transistors; a plurality of toggling functional critical paths that receive patterns generated by the aging pattern generator; a plurality of toggling functional critical path timing sensors, each receiving an output of a toggling functional critical path in the plurality of toggling functional critical paths; a plurality of fail signals generated by the plurality of toggling functional critical path timing sensors, wherein a fail signal is generated when a delay through a toggling functional critical path exceeds a timing requirement; and a margin delay adjustment controller that receives the fail signals generated by the plurality of toggling functional critical path timing sensors, the margin delay adjustment controller adjusting a margin value in response to receiving the fail signals; wherein the margin value increases over time as the wear-sensing integrated circuit ages during a lifetime of the wear-sensing integrated circuit.