Patent ID: 9685539
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. A method for manufacturing a semiconductor device, comprising: forming a doped semiconductor layer on a bulk substrate; forming an undoped cap layer on the doped semiconductor layer; forming a stacked configuration of silicon germanium (SiGe) and silicon layers on the undoped cap layer, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on an SiGe layer; forming a plurality of dummy gates spaced apart from each other on the stacked configuration, the doped semiconductor layer and the undoped cap layer; forming a spacer layer on each of the plurality of dummy gates, and on the doped semiconductor layer and the undoped cap layer; selectively removing the doped semiconductor layer adjacent the bulk substrate; and filling the area from where the doped semiconductor layer was selectively removed with a dielectric layer.