Patent ID: 9715934
Date: 2017-07-25
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; coupling circuits including pass transistors coupled between global lines and local lines coupled to the plurality of memory cells; and an address decoder coupled to block word lines coupled to gates of the pass transistors and the global lines, wherein the address decoder applies a voltage pulse to the local lines coupled to an unselected memory block and floats the local lines during an erase operation of memory cells included in a selected memory block, among the plurality of memory cells, wherein the address decoder applies a block voltage pulse to turn on the pass transistors coupling memory cells included in the unselected memory block, applies the voltage pulse to the global lines coupled to the unselected memory block when the pass transistors are turned on, and turns off the pass transistors, and wherein the address decoder applies a low voltage pulse having a level greater than a ground voltage and lower than the voltage pulse to the global lines coupled to the selected memory block.