Patent ID: 9721621
Date: 2017-08-01
CPC Classifications: G06F,G11C

Claim:
1. A semiconductor memory device comprising: a multi-layered wiring substrate; a volatile semiconductor element provided on a first main surface of the multi-layered wiring substrate; a first nonvolatile semiconductor element provided on the first main surface of the multi-layered wiring substrate; a second nonvolatile semiconductor element provided on the first main surface of the multi-layered wiring substrate; a third nonvolatile semiconductor element provided on a second main surface facing an opposite direction to the first main surface of the multi-layered wiring substrate; a fourth nonvolatile semiconductor element provided on the second main surface of the multi-layered wiring substrate; a controller provided on the first main surface of the multi-layered wiring substrate and controls the four nonvolatile semiconductor elements and the volatile semiconductor element; a connector provided on the multi-layered wiring substrate; a first signal line connecting the connector and the controller; a second signal line connecting the controller and the volatile semiconductor element; a third signal line connecting the controller and the first and third nonvolatile semiconductor elements; and a fourth signal line connecting the controller and the second and fourth nonvolatile semiconductor elements, wherein the first nonvolatile semiconductor element and the third nonvolatile semiconductor element are disposed to be symmetric to the multi-layered wiring substrate, the second nonvolatile semiconductor element and the fourth nonvolatile semiconductor element are disposed to be symmetric to the multi-layered wiring substrate, the third signal line includes a first common signal line, a signal line divided from the first common signal line and connected to the first nonvolatile semiconductor element, and a signal line connected to the third nonvolatile semiconductor element, the fourth signal line includes a second common signal line, a signal line divided from the second common signal line and connected to the second nonvolatile semiconductor element, and a signal line connected to the fourth nonvolatile semiconductor element, and the multi-layered wiring substrate is configured such that, in a plan view, a first region provided with the first signal line and a region provided with the third or fourth signal line do not overlap each other.