Patent ID: 9553053
Date: 2017-01-24
CPC Classifications: B23K,C23C,H01L

Claim:
1. A bump structure for electrically coupling semiconductor components, comprising: a first bump on a first semiconductor component, the first semiconductor component having an outermost passivation layer, the first bump extending over the outermost passivation layer, the first bump having a first non-flat outermost surface and first sidewalls, the first sidewalls being over the outermost passivation layer and extending away from the first semiconductor component; a second bump on a second semiconductor component, the second bump having a second non-flat outermost surface, the first non-flat outermost surface being complementary to the second non-flat outermost surface such that a number of projections in one of the first non-flat outermost surface and the second non-flat outermost surface equal a number of recesses in an other of the first non-flat outermost surface and the second non-flat outermost surface, the number of projections being greater than one, the projections having a circular shape, the recesses having a circular shape, each of the recesses having a first central axis in a plan view laterally displaced from each other, each of the projections having a second central axis in the plan view laterally displaced from each other, wherein lateral boundaries of each of the projections in the plan view are within lateral boundaries of a respective one of the recesses; and a solder joint formed between the first and second non-flat outermost surfaces to electrically couple the first and second semiconductor components, wherein the first sidewalls of the first bump and second sidewalls of the second bump are free of the solder joint, the first sidewalls directly connect to the first non-flat outermost surface and the second sidewalls directly connect to the second non-flat outermost surface.