Patent ID: 9619358
Date: 2017-04-11
CPC Classifications: G06F

Claim:
1. A system-on-a-chip comprising: a processor; a performance monitoring unit configured to (i) monitor events performed by the processor or a component operatively coupled to the processor, and (ii) based on monitoring the events performed by the processor or the component operatively coupled to the processor, selectively generate an interrupt; an interrupt service routine (ISR) module configured to, based on the interrupt generated by the performance monitoring unit, identify (i) a first instruction address of a first instruction executed immediately prior to a second instruction that generated the interrupt, and (ii) context information associated with the interrupt; an instruction analyzer configured to (i) receive the first instruction address, (ii) based on the first instruction address, identify a second instruction address of the second instruction that generated the interrupt, and (iii) identify a data address of first data that is associated with the second instruction address of the second instruction; and a sample collector configured to transmit, to a host external to the system-on-a-chip, (i) the second instruction address of the second instruction that generated the interrupt, (ii) the data address of the first data that is associated with the second instruction address of the second instruction, and (iii) the context information associated with the interrupt, to cause the host to identify potential performance bottlenecks in the system-on-a-chip.