Patent ID: 9620642
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method for forming a device comprising: providing a substrate prepared with a device region; forming a fin in the device region, the fin includes top and bottom fin portions, wherein the top fin portion serves as a body of a fin type transistor; forming an isolation layer on the substrate, wherein the isolation layer has a top isolation surface disposed below the top fin portion; forming at least one isolation buffer in the bottom fin portion, leaving the top fin portion crystalline, wherein the at least one isolation buffer does not extend throughout the entire length of the bottom fin portion and partially isolates the top fin portion from the substrate, wherein forming the at least one isolation buffer comprises forming source/drain (S/D) regions in the top portions of the fin; and forming a gate wrapping around the fin, wherein the gate comprises a top gate portion on top of the fin and side gate portions extending from a top surface of the fin towards the top isolation surface, wherein the side gate portions extend below the S/D regions and are in direct contact with sidewalls of the bottom fin portion.