Patent ID: 9553015
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method for fabricating a III-V-on-insulator (IIIVOI) platform for a semiconductor device, comprising: growing a plurality of compositionally-graded III-V buffer layers on a first substrate; implanting ions into one or more of the plurality of compositionally-graded III-V buffer layers to create a cleave plane; bonding a second substrate to one or more of the plurality of compositionally-graded III-V buffer layers; separating, along the cleave plane, the second substrate and the one or more compositionally-graded III-V buffer layers bonded to the second substrate from the first substrate and one or more compositionally-graded III-V buffer layers bonded to the first substrate; growing a semi-insulating buffer layer on one of the one or more compositionally-graded III-V buffer layers bonded to the second substrate; and growing a channel layer on the semi-insulating buffer layer.