Patent ID: 9558991
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A method comprising: forming a first resist mask directly on top of a first hard mask layer and above a first region of a semiconductor substrate; removing a portion of the first hard mask layer selective to the first resist mask and selective to a second hard mask layer beneath the first hard mask layer; forming a first type well in a second region of the semiconductor substrate not covered by the first resist mask; forming a second resist mask directly on top of the second hard mask layer and above the second region of the semiconductor substrate; forming an opening in the second hard mask layer selective to the second resist mask and a remaining portion of the first hard mask layer; forming a second type well in the first region of the semiconductor substrate, the second type well at least partially overlapping the first type well in a third region of the semiconductor substrate; expanding the opening in the second hard mask layer horizontally using an isotropic etching process selective to the remaining portion of the first hard mask layer and selective to the second resist mask; etching a deep trench in the third region of the semiconductor substrate, the deep trench separates the first type well from the second type of well; and filling the deep trench with insulating materials.