Patent ID: 9653361
Date: 2017-05-16
CPC Classifications: H01L

Claim:
1. A method of manufacturing a semiconductor device, comprising: forming a fin structure on a substrate; forming a sacrificial layer pattern on the fin structure, wherein the sacrificial layer pattern comprises a first region and a second region; forming an active layer pattern on the sacrificial layer pattern, wherein the active layer pattern comprises a first region formed on the first region of the sacrificial layer pattern and a second region formed on the second region of the sacrificial layer pattern; forming a dummy gate pattern crossing the first region of the active layer pattern; forming an interlayer dielectric layer on the dummy gate pattern and on the second region of the active layer pattern; planarizing the interlayer dielectric layer to expose the dummy gate pattern; removing the dummy gate pattern to expose the first region of the active layer pattern and the first region of the sacrificial layer pattern; removing the first region of the sacrificial layer pattern; forming a gate dielectric layer on the first region of the active layer pattern, wherein the gate dielectric layer surrounds the first region of the active layer pattern; and forming a gate electrode layer on the gate dielectric layer, wherein the gate electrode layer surrounds the first region of the active layer pattern.