Patent ID: 9660024
Date: 2017-05-23
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device, comprising: a first memory cell including a first transistor and a first capacitor, the first transistor comprising a first gate electrode, a first source, and a first drain; a second memory cell including a second transistor and the first capacitor, the second transistor comprising a second gate electrode, a second source, and a second drain; a first word line coupled to the first gate electrode; a second word line coupled to the second gate electrode; a third word line disposed between the first word line and the second word line; a first bit line coupled to the first drain to cross the first and second word lines; a second bit line coupled to the second drain and disposed parallel to the first bit line; a third transistor including a third gate electrode, a third drain, and a third source; a fourth transistor including a fourth gate electrode, a fourth drain, and a fourth source; a fourth word line and a fifth word line disposed parallel to the second word line; and a third bit line disposed parallel to the second bit line, wherein the first capacitor is electrically connected between the first and second transistors, wherein the first capacitor vertically overlaps the third word line, wherein the first capacitor is shared by the first and second memory cells and is coupled in common to the first and second sources, wherein the third gate electrode is coupled to the fourth word line, the third drain is coupled to the third bit line, the fourth gate electrode is coupled to the fifth word line, and the fourth drain is coupled to the second bit line, and wherein the third and the fourth sources are coupled in common to a second capacitor.