Patent ID: 9554013
Date: 2017-01-24
CPC Classifications: H04N

Claim:
1. An arithmetic memory module comprising: an input block to which a digital pixel reset signal and a digital pixel image signal are input; and a plurality of unit cells configured to generate a digital difference signal representing a difference between the digital pixel reset signal and the digital pixel image signal, wherein: the input block comprises first and second multiplexers to which the digital pixel reset signal and the digital pixel image signal are input and an inverter that is connected to the first multiplexer; the plurality of unit cells comprise a first unit cell that is connected to the input block and a second unit cell through an N-th unit cell that are successively connected to the first unit cell; N is a natural number that is two or greater; and the first unit cell comprises third and fourth multiplexers that are connected to the first multiplexer and the inverter, a first flip/flop that is connected to the third multiplexer, and a first AND gate that is connected to the fourth multiplexer and the second multiplexer; wherein the first multiplexer receives a shift signal and a feedback signal from the N-th unit cell; the shift signal is configured to cause the digital pixel reset signal first input to the first multiplexer to be input to the plurality of unit cells from a most significant bit (MSB) without an addition or subtraction operation; the second multiplexer receives a carry/borrow control signal, wherein a carry/borrow is not performed when the carry/borrow control signal is in a high state and is performed when the carry/borrow control signal is in a low state.