Patent ID: 9728410
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method for forming a split gate memory device, comprising: forming a select gate of the split gate memory device over a semiconductor substrate having a top portion and a bottom portion, wherein the bottom portion is between the top portion and the semiconductor substrate, and the top portion has a smaller width than the bottom portion; forming a first insulating layer over the bottom portion of the select gate and adjacent a first sidewall of the top portion of the select gate; removing portions of the bottom portion of the select gate exposed by the first insulating layer such that a first sidewall of the bottom portion is vertically aligned with a sidewall of the first insulating layer; forming a charge storage layer of the split gate memory device over the semiconductor substrate and the select gate, and along the sidewall of the first insulating layer and the first sidewall of the bottom portion; and after forming the charge storage layer, forming a control gate of the split gate memory device over the charge storage layer and adjacent the select gate, wherein: