Patent ID: 9666671
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. A device comprising: a semiconductor substrate having a surface; a gate structure supported by the semiconductor substrate at the surface; a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed proximate the gate structure; source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region; an isolation region disposed in the semiconductor substrate between the body region and the drain region; and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel; wherein the composite drift region comprises a first, channel-side section adjacent the channel, a second, drain-side section adjacent the drain region, and a third section disposed between the first and second sections; wherein the first and second sections have a dopant concentration level that decreases by an order of magnitude or more between upper and lower boundaries of the first and second sections; wherein the first and second sections have a lower dopant concentration level than the third section at a first depth, relative to the surface of the semiconductor substrate, deeper than a lower boundary of the isolation region; and wherein the first and second sections have a higher dopant concentration level than the third section at a second depth, relative to the surface of the semiconductor substrate, shallower than the lower boundary of the isolation region.