Patent ID: 9557346
Date: 2017-01-31
CPC Classifications: G01P

Claim:
1. An accelerometer fabrication technique comprising the following steps: (i) forming, by use of photolithography, deep etching and etching, a plurality of holes penetrating from a top silicon layer and a bottom silicon layer to a middle silicon layer of a double-sided silicon on insulator (SOI) silicon wafer; (ii) depositing polycrystalline silicon in the holes to fill up the holes, then growing a silicon dioxide layer on surfaces of the top silicon layer and the bottom silicon layer of the double-sided SOI silicon wafer; (iii) forming, by use of photolithography, deep etching and etching, a plurality of resilient E-shaped beams, range-of-motion stops and connection beams in the top silicon layer and the bottom silicon layer of the double side SOI silicon wafer, then growing, by use of thermal oxidation, silicon dioxide on exposed surfaces of the resilient E-shaped beams, the range-of-motion stops and the connection beams, or depositing, by use of chemical vapor deposition (CVD), a layer of silicon dioxide on exposed surfaces of the resilient E-shaped beams, the range-of-motion stops and the connection beams; (iv) removing, by use of photolithography and etching, the exposed silicon dioxide in the middle silicon layer, and deep etching the middle silicon layer to a certain depth; (v) corroding the middle silicon layer located between a support frame and a mass in order to form free-moving resilient beams; (vi) removing by etching the exposed silicon dioxide layer; and (vii) bonding together in one-step the top cap silicon wafer, the processed double-sided SOI silicon wafer, and the bottom cap silicon wafer.