Patent ID: 9646947
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method of manufacturing an integrated circuit (‘IC’), the method comprising: providing a first semiconductor die, the first semiconductor die comprising a first electrical endpoint; providing a second semiconductor die, the second semiconductor die comprising a second electrical endpoint; affixing to the first semiconductor die a first pad, the first pad characterized by a first capacitance, the first pad coupled to the first electrical endpoint; affixing to the second semiconductor die a second pad, the second pad characterized by a second capacitance, the second pad coupled to the second electrical endpoint, wherein the second semiconductor die is stacked on the first semiconductor die, in an IC package; determining a first inductance of a first bond wire for the IC in dependence upon electrical characteristics of the IC, the first inductance of the first bond wire configured to decrease signal degradation caused by the capacitance of the first pad on electrical signals transmitted between an IC package pin and the first electrical endpoint of the first semiconductor die; determining a second inductance of a second bond wire for the IC in dependence upon electrical characteristics of the IC, the second inductance of the second bond wire configured to decrease signal degradation caused by the capacitance of the second pad on electrical signals transmitted between the IC package pin and the second electrical endpoint of the second semiconductor die, wherein the first inductance of the first bond wire is different from the second inductance of the second bond wire; creating the first bond wire into a first inductor characterized by the determined first inductance; creating the second bond wire into a second inductor characterized by the determined second inductance; coupling the first pad to the IC package pin with the first bond wire; and coupling the second pad to the IC package pin with the second bond wire, wherein the first inductance of the first bond wire and the second inductance of the second bond wire are determined from the entire group consisting of the capacitance of the pads, an average frequency of electrical signals to be transmitted between the IC package pin and the electrical endpoints of the semiconductor dies, electrical characteristics of the IC package, and electrical characteristics of the IC package pin.