Patent ID: 9563597
Date: 2017-02-07
CPC Classifications: G06F,G11C,H01L

Claim:
1. A memory controller adapted for use in a memory system in which the memory controller is to issue commands, each command to an addressed one of a first rank of memory or a second rank of memory, over a command/address bus having (i) at least one shared link that couples the memory controller with both of the first rank of memory and the second rank of memory in a point-to-multi-point configuration, (ii) one or more first dedicated links that couples the memory controller with the first rank of memory but not the second rank of memory, and (iii) one or more second dedicated links that couple the memory controller with the second rank of memory but not the first rank of memory, where each rank of memory has an open loop clock distribution architecture that defines a respective sampling instant used to sample each shared link of the command/address bus, and the respective first or second dedicated links, the memory controller comprising: logic operable to generate a first command/address signal and to transmit the first command/address signal to an addressed one of the first rank of memory or the second rank of memory over the respective one of the one or more first or second dedicated links, according to a unique clock phase corresponding to offset experienced by the addressed one of the first or second ranks of memory relative to the other of the first or second ranks of memory; and logic operable to generate a second command/address signal and to transmit the second command/address signal over the at least one shared link to either one of the first or second ranks of memory.