Patent ID: 9608652
Date: 2017-03-28
CPC Classifications: H03M

Claim:
1. An analog-to-digital converter (ADC) apparatus, comprising: a coarse ADC to convert an input analog signal to a coarse digital output at a first sampling rate in response to a first clock signal having a first frequency, the coarse digital output constituting a timing reference for the ADC apparatus; a plurality of time-interleaved (TI) ADCs comprising at least a first TI ADC to convert the input analog signal to a first TI digital output at a second sampling rate in response to a second clock signal having a second frequency, wherein: a timing-skew controller, coupled to at least the first TI ADC, to make a first comparison of the coarse digital output constituting the timing reference and the first TI digital output and significantly reduce a first timing-skew error between the coarse digital output and the first TI digital output based at least in part on the first comparison.