Patent ID: 9646911
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method of fabricating a heterostructure, the method comprising: obtaining a composite substrate including a plurality of substrate layers, wherein the plurality of substrate layers includes a first substrate layer formed of a first material having a first thermal expansion coefficient and a second substrate layer formed of a second material having a second thermal expansion coefficient different from the first thermal expansion coefficient, wherein the obtaining includes selecting a relative thickness of each of the plurality of substrate layers according to the following:  wherein E epitaxially growing a semiconductor layer having a third thermal expansion coefficient on the composite substrate, wherein the third thermal expansion coefficient is greater than or equal to the first thermal expansion coefficient and smaller than or equal to the second thermal expansion coefficient and wherein the composite thermal expansion coefficient for the composite substrate is selected to reduce an amount of tensile stress within the semiconductor layer at at least one of: room temperature or an operating temperature for a device fabricated using the heterostructure, wherein the composite thermal expansion coefficient for the composite substrate is selected according to the following: σ is the tensile stress, E is the biaxial modulus of the composite substrate, T low is a temperature measured at a room or an operating temperature, T high is a temperature at a highest epitaxial growth temperature, α f (T) is a thermal expansion coefficient of the semiconductor layer at a temperature T, α c (T) is a thermal expansion coefficient of the composite substrate at a temperature T and dT is the difference between T low and T high , and wherein α c (T) is chosen to minimize σ.