Patent ID: 9659939
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method comprising: forming a trench in a Silicon substrate; depositing metal on sidewalls and a bottom of the trench; annealing the deposited metal to react the metal with underlying Si and form a layer of metal silicide adjacent to sidewalls and the bottom of the trench; removing unreacted deposited metal; depositing a dielectric layer on the layer of metal silicide, where the layer of metal silicide functions as a bottom plate, a metal layer over the dielectric layer to form a top plate and electrically conductive polysilicon to fill the remainder of the trench thereby forming a top plate electrode of a metal-insulator-metal (MIM) capacitor in the trench; and after forming the top plate electrode of the MIM capacitor in the trench, forming a transistor adjacent to a top of the trench, where the transistor is formed so as to be connected to the top plate electrode of the MIM capacitor via a self-aligned strap interface that comprises a portion of the metal silicide layer that is disposed at the top of the trench.