Patent ID: 9678374
Date: 2017-06-13
CPC Classifications: G02F,G09G

Claim:
1. An array substrate, wherein the array substrate comprises a display area and a peripheral area; the display area has a plurality of data lines; wherein the array substrate further comprises: low temperature compensation circuits arranged in the peripheral area and one-to-one corresponding to the data lines; each low temperature compensation circuit comprises a first branch and a second branch connected in parallel; wherein the first branch comprises a divider resistance; the second branch comprises a diode and a capacitance connected in series; wherein an anode terminal of the diode is connected with an input terminal of a data line, a cathode terminal of the diode is connected with a terminal of the capacitance, another terminal of the capacitance is connected with a data signal receiving terminal; or, a cathode terminal of the diode is connected with a data signal receiving terminal, an anode terminal of the diode is connected with a terminal of the capacitance, another terminal of the capacitance is connected with an input terminal of a data line.