Patent ID: 9691502
Date: 2017-06-27
CPC Classifications: G11C

Claim:
1. A multi-port memory comprising: a memory cell; first and second word lines; first and second bit lines; first and second address terminals; and an address control circuit, wherein the multi-port memory includes first and second operation modes, wherein the first word line is activated and thereby the memory cell is electrically coupled to the first bit line, wherein the second word line is activated and thereby the memory cell is electrically coupled to the second bit line, wherein in the first operation mode, the address control circuit performs control as to whether the first word line is activated on the basis of a first address signal that is input into the first address terminal, and performs control as to whether the second word line is activated on the basis of a second address signal that is input into the second address terminal, and wherein in the second operation mode, the address control circuit performs control as to whether the first word line and the second word line are activated on the basis of the first address signal that is input into the first address terminal.