Patent ID: 9691767
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A manufacturing method of a semiconductor device, comprising: implanting a first impurity into a first region of a semiconductor substrate including the first region and a second region; forming a semiconductor layer on the upper surface of the semiconductor substrate; forming a trench in the semiconductor layer and the semiconductor substrate; forming an isolation insulating film in the trench; implanting a second impurity into the semiconductor layer in the second region; forming a first gate insulating film on the semiconductor layer in the first region; forming a second gate insulating film on the semiconductor layer in the second region; forming a first gate electrode on the first gate insulating film; forming a second gate electrode on the second gate insulating film; forming a first source region and a first drain region in the semiconductor layer at both sides of the first gate electrode, the first source region and the first drain region having a conductivity type opposite to a conductivity type of the first impurity; and forming a second source region and a second drain region in the semiconductor layer at both sides of the second gate electrode, the second source region and the second drain region having a conductivity type opposite to a conductivity type of the second impurity, wherein the semiconductor substrate further includes a third region, and the manufacturing method of the semiconductor device further comprises: implanting a third impurity into the third region of the semiconductor substrate; forming a third gate insulating film on the semiconductor layer in the third region; forming a third gate electrode on the third gate insulating film; and forming a third source region and a third drain region in the semiconductor layer at both sides of the third gate electrode, the third source region and the third drain region having a conductivity type opposite to a conductivity type of the third impurity, wherein between the formation of the semiconductor layer and the formation of the third gate electrode, implanting an impurity into the semiconductor layer in the third region is not performed.