Patent ID: 9626188
Date: 2017-04-18
CPC Classifications: G06F

Claim:
1. A computer implemented method for relative offset branching in a reduced instruction set computing (RISC) architecture, the method comprising: fetching an instruction group from a memory comprising a branch instruction of an instruction stream having a fixed instruction width; determining whether the instruction group includes the branch target address value; acquiring a relative offset value from the instruction stream, the relative offset value formatted as an offset relative to a program counter value and sized as a multiple of the fixed instruction width; adding the relative offset value with the program counter value to form a branch target address value; loading the branch target address value into a program counter based on the branch instruction; redirecting execution of the instruction stream to a next instruction based on the branch target address value in the program counter and determining that the instruction group includes the branch target address value; and based on determining that the instruction group does not include the branch target address value, generating and executing an internal operation sequence in a branch execution unit and a load-store unit to load the branch target address value from the memory and update the program counter.