Patent ID: 9692429
Date: 2017-06-27
CPC Classifications: H03L

Claim:
1. Phase lock loop (PLL) circuitry comprising: voltage controlled oscillator (VCO) circuitry that generates a feedback clock signal; phase frequency detector (PFD) circuitry that receives the feedback clock signal and a reference clock signal, compares phase of the feedback clock signal to phase of the reference clock signal, and outputs a phase comparison signal; first charge pump circuitry that receives the phase comparison signal and outputs, to the VCO circuitry, a control signal proportional to the phase comparison signal; frequency detector (FD) circuitry that receives the feedback clock signal and the reference clock signal, compares frequency of the feedback clock signal to frequency of the reference clock signal, and outputs a frequency difference signal that is proportional to frequency difference between frequencies of the feedback clock signal and the reference clock signal determined by the comparison; second charge pump circuitry that receives the frequency difference signal and outputs, to the VCO circuit, a control signal proportional to the frequency difference signal; wherein the FD circuitry comprises first shift register chain circuitry that receives the reference clock signal; second shift register chain circuitry that receives the feedback clock signal; and gate circuitry that generates a set signal based on an output of the first shift register chain circuit and/or an output of the second shift register chain circuit; and wherein one or more of: the first shift register chain circuitry is initialized to a logic 1 state and configured to shift in a logic 0 state when it receives the reference clock signal; the second shift register chain circuitry is initialized to a logic 1 state and configured to shift in a logic 0 state when it receives the feedback clock signal; the gate circuitry is configured to generate the set signal when a last stage output of the first shift register chain circuit is logic 0 and/or a last stage output of the second shift register chain circuit is logic 0; the first shift register chain circuitry is reset to a logic 1 state after the set signal is generated; and/or the second shift register chain circuitry is reset to a logic 1 state after the set signal is generated.