Patent ID: 9659817
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method for forming an integrated circuit comprising: providing a patterned substrate comprising a contact hole in a dielectric layer, wherein the contact hole includes sidewalls formed of the dielectric layer and a bottom surface defined by a source/drain region or a metal gate; generating nitrogen ions from a nitrogen containing gas selected from the group consisting of nitrogen (N exposing the substrate including the dielectric layer to form a nitrogen enriched dielectric layer at about a surface of the dielectric layer; conformally depositing a single metal liner layer onto the patterned substrate and forming a metal nitride at an interface between the single metal liner layer and the nitrogen enriched dielectric layer and into at least a portion of the metal liner layer; depositing a tungsten metal into the contact hole, wherein the tungsten metal is in direct contact with the nitrogen enriched metal liner layer; and removing regions of the tungsten metal and regions of the metal nitride on a top surface of the dielectric layer such that the tungsten metal is coplanar to the top surface of the dielectric layer.