Patent ID: 9748248
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate including a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned in the trench and at a level lower than a top surface of the substrate, wherein the gate electrode includes a first buried portion and a second buried portion, wherein the second buried portion is formed over the first buried portion; and a first doping region and a second doping region formed in the substrate and over first and second sides of the gate electrode, wherein each of the first doping region and the second doping region overlaps the second buried portion, wherein the first buried portion includes a first barrier with a first work function, wherein the second buried portion includes second barrier with a second work function, wherein the second work function is lower than the first work function, wherein the first barrier includes metal silicon nitride with 20 atomic percent or less of silicon and the second barrier includes metal silicon nitride with 30 atomic percent or more of silicon.