Patent ID: 9691763
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width; a first semiconductor fin formed on an upper surface of the substrate, an entire base of the first semiconductor fin directly contacting the substrate and extending continuously between a first pair of fin ends along the second direction at a first distance without disengaging the substrate to define a first fin width, a first source/drain junction of the first semiconductor fin formed on the upper surface of the substrate; and a second semiconductor fin formed on the upper surface of the substrate, an entire base of second semiconductor fin directly contacting the substrate and extending continuously between a second pair of fin ends along the second direction at a second distance without disengaging the substrate to define a second fin width, a second source/drain junction of the first semiconductor fin formed on the first semiconductor fin, wherein the at least one fin end included in the first pair of fin ends is not aligned with at least one fin end included in the second pair of fin ends, and wherein the first and second fins are orientated in parallel arrangement with respect to one another on the substrate, and wherein the first and second source/drain junctions define a first gate channel therebetween, the first gate channel being non-planar with respect to at least one of the first and second source/drain junctions.