Patent ID: 9553143
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a semiconductor substrate; a semiconductor layer disposed over the semiconductor substrate; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer, being adjacent to the first well region; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the first and second well regions, between the first and second isolation elements, and having a zig-zag like shape or a U-like shape, wherein the gate structure comprises a gate insulating layer and a conductive layer overlaying the gate insulating layer, a bottom surface of the conductive layer is above a bottom surface of the first well region and a bottom surface of the second well region, and the bottom surface of the conductive layer is below a top surface of the first well region and a top surface of the second well region; a first doped region disposed in the first well region; and a second doped region disposed in the second well region, wherein the semiconductor substrate, the semiconductor layer, and the second well region have a first conductivity type, and the first well region, the first doped region, and the second doped region have a conductivity type that is opposite to the first conductivity type, and a bottom surface of the gate structure is above, lower than or level with a bottom surface of the first isolating element.