Patent ID: 9680475
Date: 2017-06-13
CPC Classifications: G06F,H03K

Claim:
1. A method comprising: receiving a user design for a programmable logic device (PLD), wherein the PLD comprises a plurality of configurable resources, global set/reset (GSR) resources, and a plurality of sequential components; identifying a plurality of set/reset signals of the user design; determining, for each set/reset signal, a measurement of configurable resource savings associated with an assignment of the set/reset signal to the GSR resources; and assigning a selected one of the set/reset signals to the GSR resources based on the associated measurement, wherein the user design identifies connections between the set/reset signals and the sequential components; and the determining a measurement comprises filtering the sequential components, and determining configurable resource savings associated with assigning the set/reset signal to the GSR resources connected to the filtered sequential components.