Patent ID: 9620460
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A semiconductor chip comprising: a semiconductor substrate including a first region and a second region; a plurality of interlayer insulation layers formed on the semiconductor substrate; a first crack stopper formed in the plurality of interlayer insulation layers of the first region; an interconnector formed in the plurality of interlayer insulation layers of the second region; a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, and a bonding pad formed on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire; and a protection layer covering on the pad wire and exposing the bonding pad, wherein the first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad in a plan view while not overlapping with the bonding pad and not being directly connected to the pad wire, and wherein the first crack stopper further comprises: