Patent ID: 9589853
Date: 2017-03-07
CPC Classifications: H01L

Claim:
1. A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber wherein the semiconductor substrate is supported on a support surface of a substrate support assembly located in the plasma etch chamber, the substrate support assembly including an array of independently controlled thermal control elements therein wherein the thermal control elements of the array of independently controlled thermal control elements are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones to correspond to a desired temperature profile across the upper surface of the semiconductor substrate such that the etch rate across the upper surface of the semiconductor substrate can be controlled during plasma etching so that the upper surface of the semiconductor substrate may be planarized, the method comprising: analyzing the upper surface of the semiconductor substrate thereby measuring nonuniformity of surface topography of the upper surface wherein the upper surface is formed by a Si-containing material; calculating an amount of the Si-containing material to remove from the upper surface of the semiconductor substrate based upon the analysis of the upper surface to achieve a planar upper surface of the semiconductor substrate after plasma etching the semiconductor substrate for a predetermined time; generating a temperature profile of the spatial and temporal temperatures across the support surface of the substrate support assembly which corresponds to desired temperatures across the upper surface of the semiconductor substrate required to remove the calculated amount of the Si-containing material from the upper surface, wherein the etch rate of the Si-containing material forming the upper surface depends on the localized temperature thereof;