Patent ID: 9627096
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a memory bank having a plurality of word lines arranged at a predetermined address interval; an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines; and a refresh control unit suitable for performing a refresh operation on first and second word lines having a first address interval and a second address interval, respectively, from the target word line based on the target address in response to a smart refresh command, wherein, when the target word line is an Nth word line, and the first word lines having the first address interval from the target word line include (N−1)th and (N+1)th word lines, and the second word lines having the second address interval from the target word line include (N−2)th and (N+2)th word lines, where N is a natural number.