Patent ID: 9625525
Date: 2017-04-18
CPC Classifications: G01R

Claim:
1. An integrated circuit decompress and maskable compress test access mechanism comprising: (a) a serial data input lead and a serial data output lead; (b) parallel data output leads; (c) a scan frame input register having a scan frame input lead connected with the serial data input lead, the scan frame input register including a compressed stimulus section coupled with the parallel data output leads, a compressed mask section, a command section, and a frame marker section connected in series with the serial data input lead; and (d) a scan frame copy register having an output coupled with the serial data output lead, the scan frame copy register having a compressed stimulus section coupled to the compressed stimulus section of the scan frame input register, a compressed mask section coupled with the compressed mask section of the scan frame input register, a command section coupled with the command section of the scan frame input register, and a frame marker section coupled to the scan frame marker section of the scan frame input register, the scan frame copy register being coupled to the serial data input lead through the scan frame input register.