Patent ID: 9620190
Date: 2017-04-11
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a first memory segment including a plurality of first variable resistance memory cells arranged along first and second directions crossing each other; a first source structure electrically connected in common to the plurality of first variable resistance memory cells, the first source structure including a plurality of first local source lines extending in the first direction and a plurality of first source connection lines extending in the second direction and being connected to the plurality of first local source lines; a second memory segment, controlled separately from the first memory segment, the second memory segment including a plurality of second variable resistance memory cells arranged along the first and second directions; a second source structure electrically connected in common to the plurality of second variable resistance memory cells, the second source structure including a plurality of second local source lines extending in the first direction and a plurality of second source connection lines extending in the second direction and being connected to the plurality of second local source lines, wherein the first and second source structures are physically separated from each other.