Patent ID: 9746728
Date: 2017-08-29
CPC Classifications: G02F,H01L

Claim:
1. A display panel, comprising a peripheral wiring region, wherein the peripheral wiring region comprises a metal connecting line area, and the metal connecting line area comprises: a gate insulating layer disposed on a gate metal layer; and a protective layer, a passivation layer and an indium tin oxide (ITO) coating layer disposed on the gate insulating layer in sequence; and a through hole is provided in the gate insulating layer, the protective layer, and the passivation layer and exposes part of the gate metal layer, and the ITO coating layer is electrically connected with the exposed part of the gate metal layer via the through hole; the protective layer comprises a first protective layer and a second protective layer; the first protective layer is provided in a same layer and made from a same material as an active layer of a thin film transistor of the display panel; and the second protective layer is provided in a same layer and made from a same material as source/drain electrodes of the thin film transistor of the display panel.