Patent ID: 9612272
Date: 2017-04-04
CPC Classifications: G01R,G11C

Claim:
1. A system for testing a device under test (DUT), the system comprising: a first buffer memory bank operable for capturing fresh failure related data from the device under test at a first time; a second buffer memory bank operable for transmitting existing failure related data from a previous DUT test, which precedes the first time; a fail engine operable for accessing the existing failure related data and for generating a failure list based thereon, wherein one or more of the receiving the existing failure related data, the accessing the existing failure related data, and the generating the failure list, is performed contemporaneously in relation to the capturing the fresh failure related data; a queue operable for queuing a generated failure list; and a failure processor operable for controlling the capturing and for computing a redundancy analysis based on a queued failure list.