Patent ID: 9633741
Date: 2017-04-25
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor memory device, comprising: a plurality of stacked bodies, one of the stacked bodies including a plurality of control gate electrodes stacked in a first direction, the stacked bodies extending in a second direction intersecting the first direction; an insulating isolation layer disposed between a pair of the stacked bodies adjacent in a third direction intersecting the first direction and the second direction, the insulating isolation layer extending in the second direction; a plurality of semiconductor layers, one of the semiconductor layers extending in the first direction and having its side surface covered by the plurality of control gate electrodes, the semiconductor layers being disposed in a plurality of columns in one of the plurality of stacked bodies; a memory cell disposed between one of the control gate electrode and one of the semiconductor layer, the memory cell including a charge accumulation layer; a plurality of bit lines connected to one end of the semiconductor layers, the bit lines extending in the third direction; and a control circuit being configured to control the control gate electrodes and the bit lines, the control circuit, during a read operation, being configured to apply a first voltage to a first bit line connected to the semiconductor layer positioned in a first column of the plurality of columns, thereby reading a first one of the memory cells connected to the first bit line, and apply a second voltage different from the first voltage to a second bit line connected to the semiconductor layer positioned in a second column which is at a position more distant from the insulating isolation layer than the first column is, thereby reading a second one of the memory cells connected to the second bit line.