Patent ID: 9748329
Date: 2017-08-29
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a first trench extending in a semiconductor region, the first trench having a shield electrode and a gate electrode vertically stacked therein, the shield electrode being insulated from the gate electrode; a source pad configured to receive a first external connection and electrically coupled to the shield electrode of the first trench; a gate pad disposed above the semiconductor region and configured to receive a second external connection; an electrical trace electrically coupled to the gate pad or to the source pad; a second trench extending in the semiconductor region and disposed directly under at least one of the gate pad and the electrical trace, the second trench having a first electrode disposed therein, the second trench being insulated from the electrical trace by a dielectric when directly under the electrical trace; a first mesa of semiconductor material adjacent the first trench; and a second mesa of the semiconductor material adjacent the second trench.