Patent ID: 9711395
Date: 2017-07-18
CPC Classifications: G03F,H01L

Claim:
1. A method of fabricating a semiconductor device using an overlay mark, the method comprising: preparing a substrate having a circuit area, a vernier rule area, and a main rule area; forming gate patterns in the circuit area of the substrate; forming a lower interlayer insulating layer on the substrate to surround the gate patterns; forming a contact pattern between the gate patterns in the circuit area and a mirror pattern in the lower interlayer insulating layer in the main rule area; forming a lower stopping insulating layer on the gate patterns, the contact pattern, the mirror pattern, and the lower interlayer insulating layer; forming an upper interlayer insulating layer on the lower stopping insulating layer; forming a trench mask on the upper interlayer insulating layer, wherein the trench mask includes a trench opening vertically aligned with the contact pattern in the circuit area and a main pattern in the main rule area; forming a sacrificial layer on the trench mask; and forming a via mask on the sacrificial layer, wherein the via mask includes a via opening vertically aligned with the trench opening in the circuit area and a vernier pattern in the vernier rule area.