Patent ID: 9619855
Date: 2017-04-11
CPC Classifications: G06T

Claim:
1. An apparatus, comprising: a plurality of processor cores to perform three-dimensional (3D) graphics processing, each processor core including local storage to buffer geometry setup results; shared storage communicatively coupled to the plurality of processor cores, the shared storage to buffer vertex processing results provided by each processor core; and a bus communicatively coupled to the local storage of each processor core, the bus to distribute at least some of the geometry setup results among the plurality of processor cores, wherein the local storage comprises a First In First Out (FIFO) buffer, wherein the FIFO buffer includes two sets of read pointers, wherein one set of read pointers is to reference objects spanning only target pixels of the processor core that includes the FIFO buffer, and wherein the other set of read pointers is to reference objects spanning target pixels of the processor core that includes the FIFO buffer and target pixels of at least one other processor core.