Patent ID: 9735229
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate comprising a first conductivity type, a top surface, an active region, and an edge termination region, wherein said edge termination region is spaced from and encloses said active region; a semiconductor element formed in said active region; and a plurality of impurity layers of a second conductivity type that are formed at least partly overlapping one another in a region spanning from an edge portion of said active region to said edge termination region in said top surface of said semiconductor substrate, wherein, for an arbitrary pair of adjacent ith and an i+1th impurity layers among said plurality of impurity layers, P(i)>P(i+1), D(i)<D(i+1), and B(i)<B(i+1) are satisfied, where P(i) and P(i+1) are respectively surface concentrations that are concentrations of impurities of said second conductivity type in said ith impurity layer and said i+1th impurity layer at said top surface of said semiconductor substrate, D(i) and D(i+1) are respectively bottom-end distances that are distances from said top surface of said semiconductor substrate to bottom ends of said ith impurity layer and said i+1th impurity layer, B(i) and B(i+1) are respectively distances from an edge of said edge termination region on a side of said active region to edges of said ith impurity layer and said i+1th impurity layer on an edge side of said semiconductor substrate, and i is a positive integer greater than one, and said surface concentration in an impurity layer whose bottom-end distance is the largest among said bottom-end distances of said plurality of impurity layers is 10 to 1000 times a concentration of impurities of said first conductivity type in said semiconductor substrate, and said bottom-end distance of said impurity layer is in a range of 15 to 30 μm.