Patent ID: 9666577
Date: 2017-05-30
CPC Classifications: H01L

Claim:
1. An integrated circuit comprising a device for protecting against electrostatic discharges, the protection device comprising a buried insulant layer having a thickness of less than or equal to 50 nm, first and second bipolar transistors arranged on the buried insulant layer, one of the first and second bipolar transistors being an npn transistor, the other of the first and second bipolar transistors being a pnp transistor, the base of the first bipolar transistor being merged with the collector of the second bipolar transistor and the base of the second bipolar transistor being merged with the collector of the first bipolar transistor, the first and second bipolar transistors being configured for selectively conducting a discharge current between two electrodes of the protection device, a first semiconductor ground plane arranged under the buried insulant layer, wherein said ground plane is capable of being electrically biased, wherein said ground plane extends plumb with the base of the first bipolar transistor, wherein said round plane has a first type of doping that is identical to that of the base of the first bipolar transistor, and wherein the ground plane has a doping density that is at least ten times greater than that of the base of the first bipolar transistor, an FDSOI transistor formed on said buried insulant layer, and a semiconductor ground plane arranged under said buried insulant layer, plumb with said FDSOI transistor.