Patent ID: 9653209
Date: 2017-05-16
CPC Classifications: H01F,H05K,Y10T

Claim:
1. A method for producing an electronic component formed by laminating a plurality of insulator layers, the electronic component including a laminate with a mounting surface constituted by a series of first sides of the insulator layers, a circuit element provided in the laminate, and external conductors electrically connected to the circuit element and led out to the first sides, the method comprising steps of: obtaining a mother laminate that, when viewed in a plan view in a direction of lamination, has a plurality of the laminates arranged in a matrix-like state in a first direction and a second direction perpendicular to the first direction; and cutting the mother laminate into the laminates, wherein, in the step of obtaining, the mother laminate is obtained such that the external conductors of two laminates adjacent in the first direction are joined, and circuit elements provided in the two laminates have a point-symmetrical relationship with each other, in the step of cutting, the mother laminate is cut along first cutoff lines extending in the second direction after the mother laminate is cut along second cutoff lines extending in the first direction, the external conductors being located on the first cutoff lines, and a number of the external conductors per laminate on each of the second cutoff lines is less than a number of the external conductors per laminate on each of the first cutoff lines.