Patent ID: 9557655
Date: 2017-01-31
CPC Classifications: G03F,H01L

Claim:
1. A method of manufacturing an integrated circuit device, comprising: forming a feature pattern and a focus metrology mark, the focus metrology mark comprising a plurality of metrology patterns spaced apart from each other to measure a focal variation of the feature pattern, on a same level on a substrate via an exposure process; radiating a radiation beam to be incident on the focus metrology mark; detecting powers of ±n-order diffracted light beams diffracted at identical angles so as to be symmetrical with each other about a zero-order diffracted light beam from among output beams diffracted by the focus metrology mark, wherein n is an integer equal to or greater than 1; and inferring defocus that has been experienced by the substrate during an exposure process, based on comparison of the powers of the ±n-order diffracted light beams.