Patent ID: 9652575
Date: 2017-05-16
CPC Classifications: G06F,H01L,H04N

Claim:
1. A floorplan-optimized stacked image sensor, comprising: a sensor layer having a plurality of pixel sub-arrays (PSAs) that form a contiguous two-dimensional pixel array; a circuit layer having a local-based space, with a plurality of analog-to-digital converters (ADCs) thereon each communicatively coupled to a different one of the plurality of PSAs, interleaved with at least one contiguous global-based space of the circuit layer that is uninterrupted by any of the ADCs; in a direction parallel to rows of the pixel array, a first spatial dimension of the at least one global-based space exceeds a first spatial dimension of a PSA, and in a direction parallel to columns of the pixel array, a second spatial dimension of the global-based space exceeds a second spatial dimension of the PSA.