Patent ID: 9703739
Date: 2017-07-11
CPC Classifications: G06F

Claim:
1. An integrated circuit comprising: a first circuit; a second circuit; a bus; and means for: 1) receiving a first command from the first circuit via the bus, wherein the first command includes a PPI (Packet Portion Identifier), wherein the means in response to the first command translates the PPI into an address and then uses the address to cause a packet portion to be written into a memory so that the packet portion is then stored in the memory in association with the PPI, 2) receiving a second command from the second circuit via the bus, wherein the second command includes the PPI but does not include any credit number, wherein the means in response to receiving the second command uses the PPI to determine a corresponding credit number, wherein the means is also for adding the credit number to a CTBR (Credits To Be Returned) value stored in the means thereby generating an updated CTBR value, and 3) receiving a third command from the first circuit via the bus, wherein the means in response to the third command sends the updated CTBR value back to the first circuit via the bus.