Patent ID: 9620580
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A semiconductor structure, comprising: a substrate; a first passivation layer disposed on the substrate; a conductive pad disposed on the first passivation layer; a second passivation layer disposed on the first passivation layer; a passive device disposed on the conductive pad, the passive device having a first portion located above the second passivation layer and a second portion passing through the second passivation layer, the first portion having a top surface and side walls extending upwardly toward the top surface; an organic solderability preservative (OSP) film covering the side walls and top surface of the first portion of the passive device; and an under bump metallurgy (UBM) layer covering the second portion of the passive device, wherein the UBM layer and the OSP film entirely wrap the passive device; and wherein the under bump metallurgy layer extends over a top surface of the second passivation layer such that the OSP film does not contact the second passivation layer.