Patent ID: 9734897
Date: 2017-08-15
CPC Classifications: G11C,H01L

Claim:
1. Static random access memory (SRAM) bitcell structures, the structures comprising: a semiconductor substrate including a silicon substrate, a deep n-well (DNW) layer formed over the silicon substrate, p-well (PW) regions formed over portions of the DNW layer, and doped back-plate (BP) regions formed over portions of the PW regions; a buried oxide (BOX) layer formed over the PW regions and the BP regions of the semiconductor substrate; first, second, third and fourth active regions formed on the BOX layer and over portions of the BP regions; a first polysilicon gate conductor (PC) construct overlapping a portion of the first active region transistor and a portion of the third active region forming channels of a first pull-down (PD at least one shallow trench isolation (STI) region extending at least one of from the third active region and below the first PC construct or from the fourth active region and below the fourth PC construct; and at least one contact to back gate (CBP), wherein a BP region extends directly beneath the at least one CBP, the at least one STI region and the BOX layer below the channel of at least one of the PG