Patent ID: 9569114
Date: 2017-02-14
CPC Classifications: G06F

Claim:
1. A system, including a processor, and coupled to the memory device, containing instructions executed by the processor, comprising: an address mapping master configured to: receive a write instruction, including: (1) a logical address and (2) write data to be stored at the logical address; determine if the logical address is stored in an address table that includes one or more mappings between one or more logical addresses and a physical address; and select a deduplication state based at least in part on: (1) whether the logical address is stored in the address table and (2) whether a fingerprint is stored in a fingerprint table, wherein the fingerprint table includes one or more mappings between a fingerprint and a physical address; and a fingerprinting slave configured to: generate the fingerprint using the write data; and determine if the fingerprint is stored in the fingerprint table, wherein: (1) the address mapping master and the fingerprinting slave are configured to run in parallel and (2) the address mapping master is the master to the fingerprinting slave.