Patent ID: 9728581
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method of forming an integrated circuit, comprising the steps: providing a substrate comprising a p-type semiconductor material; implanting n-type dopants into the substrate to concurrently form a first n-type isolation layer and a second n-type isolation layer, the first n-type isolation layer providing a Hall plate of a Hall sensor of the integrated circuit, the second n-type isolation layer providing an isolation layer for an NMOS transistor of the integrated circuit; implanting p-type dopants into the substrate to concurrently form a first shallow p-type well and a second shallow p-type well, the first shallow p-type well being in the first n-type isolation layer and located over, and extending to, the Hall plate, the second shallow p-type well being in the second n-type isolation layer and located under an area for the NMOS transistor; forming the NMOS transistor over the second shallow p-type well; forming a PMOS transistor of the integrated circuit; and forming at least one of a current source electrically coupled to the Hall sensor and a voltage sensor electrically coupled to the Hall sensor, wherein the implanting n-type dopants into the substrate concurrently to form first shallow n-type wells and second shallow n-type well, the first shallow n-type wells providing electrical connections to the Hall plate and the second shallow n-type well located in an area for the PMOS transistor.