Patent ID: 9697878
Date: 2017-07-04
CPC Classifications: G11C

Claim:
1. A storage device comprising: a word line; a first sub word line; a second sub word line; a first transistor; a second transistor; a first selection transistor; a second selection transistor; a first capacitor; and a second capacitor, wherein a gate of the first selection transistor is electrically connected to the first sub word line, wherein a gate of the second selection transistor is electrically connected to the second sub word line, wherein the first capacitor is electrically connected to one of a source and a drain of the first selection transistor, wherein the second capacitor is electrically connected to one of a source and a drain of the second selection transistor, wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the word line, wherein the other of the source and the drain of the first transistor is electrically connected to the first sub word line, wherein the other of the source and the drain of the second transistor is electrically connected to the second sub word line, wherein off-state leakage current per micrometer of channel width of each of the first transistor and the second transistor is 1×10 wherein the first transistor, the first selection transistor and the first capacitor overlap each other, and wherein the second transistor, the second selection transistor and the second capacitor overlap each other.