Patent ID: 9570573
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A method for forming a gate tie-down, comprising: exposing an active area by etching dielectric material on adjacent sides of a gate structure to pen up trench contact openings and forming trench contacts therein; forming a etch stop layer on the trench contacts and on spacers of gate structures adjacent to the trench contact; depositing an interlevel dielectric (ILD) to fill over the etch stop layer in the trench contact openings and over the gate structures adjacent to the trench contacts; opening up the ILD and the etch top layer on one side of the gate structure to provide an exposed etch stop layer portion; recessing the gate structure to remove a cap layer, recess one space and expose a gate conductor and removing the exposed etch stop layer portion; and deposition a conductive material to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.