Patent ID: 9728457
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A method comprising: etching a recess in a first side of a first substrate, the recess extending partially into the first substrate, the recess adjacent an active region in the first side of the first substrate; lining the recess with a dielectric material; filling the lined recess with a first material; forming contacts over the first side of the first substrate with at least one contact coupled to the active region and at least another contact over and aligned with the first material in the recess; forming an interconnect layer over the contacts and coupled to the at least one contact and the at least another contact; forming a bond pad over the interconnect layer; thinning a second side of the first substrate to expose the dielectric material; removing the first material from the recess; and filling the recess with a conductive material, the conductive material in the recess being coupled to the at least another contact.