Patent ID: 9659864
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first layer of an interconnect structure formed over a substrate, wherein the first layer contains a first dielectric material and a first conductive element disposed in the first dielectric material; a first etching stop layer that is disposed on the first dielectric material of the first layer but not on the first conductive element of the first layer; and a second conductive element disposed over the first layer, wherein the second conductive element is at least partially aligned with, and electrically coupled to, the first conductive element; a second etching stop layer disposed over the first etching stop layer and over the first layer, wherein the second conductive element extends through the second etching stop layer; and a second layer of the interconnect structure disposed over the second etching stop layer, wherein the second layer of the interconnect structure includes a second dielectric material and a third conductive element disposed in the second dielectric material, wherein the third conductive element is disposed over, and electrically coupled to, the second conductive element.