Patent ID: 9543246
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising one parallel transistor in which a plurality of vertical transistors disposed in an active region on a semiconductor substrate are connected in parallel, wherein the parallel transistor comprises: a plurality of semiconductor pillars protruding out in a direction perpendicular to a main surface of the semiconductor substrate; a lower diffusion layer disposed below the plurality of semiconductor pillars; a plurality of upper diffusion layers, disposed respectively at the top of the plurality of semiconductor pillars; and a gate electrode disposed over the side surfaces, in their entirety, of the plurality of semiconductor pillars, with the interposition of a gate insulating film; and wherein the plurality of upper diffusion layers are connected to one upper contact plug disposed on the plurality of upper diffusion layers, and wherein the one upper contact plug is connected to a wiring line disposed on the one upper contact plug.