Patent ID: 9570123
Date: 2017-02-14
CPC Classifications: G06F,G11C

Claim:
1. A memory system comprising: a memory bank including a serial data path for coupling the serial bitstream read data and the serial bitstream write data between the memory bank and an input/output interface wherein the memory bank includes: a first bank half coupled to first n parallel datalines for receiving the read data from the first page buffer, where n is an integer value greater than 0, a second bank half coupled to second n parallel datalines, and the parallel/serial data converter is configured to selectively convert one of the first and the second n parallel datalines into the serial bitstream read data, and for selectively converting the serial bitstream write data into parallel data for one of the first and the second n parallel datalines and wherein the parallel/serial data converter includes: a first parallel/serial data converter for sequentially coupling each of the first n parallel datalines to a first terminal, a second parallel/serial data converter for sequentially coupling each of the second n parallel datalines to a second terminal, and a data path selector for selectively coupling one of the first terminal and the second terminal to a bidirectional serial data line.