Patent ID: 9559690
Date: 2017-01-31
CPC Classifications: G06F,H01L,H03K

Claim:
1. An array substrate, comprising: a base substrate; a gate electrode and a gate line located on the base substrate; an active layer located on a film layer where the gate electrode and the gate line are located; a drain electrode, a source electrode and a data line located on the active layer; a pixel electrode located on a film layer where the drain electrode, the source electrode and the data line are located and electrically connected to the drain electrode through a first via hole; and a common electrode layer located on a film layer where the pixel electrode is located and electrically insulated from the pixel electrode; wherein, the common electrode layer includes a plurality of self-capacitive electrodes disposed on a same layer and mutually insulated; the array substrate further comprises: a plurality of conducting lines, located on the film layer where the drain electrode, the source electrode and the data line are located, and electrically insulated from the drain electrode, the source drain, the data line and the pixel electrode; and, disposed on a layer different from the common electrode layer, and each of the conducting lines being electrically connected to a corresponding self-capacitive electrode through a second via hole.