Patent ID: 9703364
Date: 2017-07-11
CPC Classifications: G06F,Y02D

Claim:
1. A processor comprising: computational logic having a plurality of slices, wherein each of the plurality of slices is to comprise a plurality of sub-slices to perform one or more computations related to one or more graphics operations; and logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices based on an indication to reduce power consumption of the computational logic, wherein the indication to reduce power consumption of the computational logic is to be generated based at least in part on a ratio of leakage power and dynamic power, wherein the one or more graphics operations are to be performed on a plurality of frames, wherein logic to cause rotation of the power-gating is to cause the rotation of the power-gating partway through a frame or at a frame boundary, wherein residency in each rotation of power-gating is capable to differ for each of the sub-slices, wherein logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices is to cause each powered down single sub-slice within each slice of the plurality of slices to be powered up in response to expiration of a timer.