Patent ID: 9536877
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method of forming source/drain conductive contacts to first and second source/drain regions, said first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, said second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than said first gate pitch dimension, wherein said first and second pairs of transistor devices have a gate structure, a gate cap layer positioned above said gate structure, and sidewall spacers positioned adjacent the gate structure, the method comprising: forming a first layer of insulating material above said first and second source/drain regions; forming a second layer of insulating material above said first layer of insulating material; forming first and second contact openings above said first and second source/drain regions, wherein forming said first contact opening removes substantially all of said first layer of insulating material positioned above said first source/drain region and between facing sidewall spacers on said first pair of transistor devices having said first gate pitch, and wherein forming said second contact opening removes some, but not all, of said first layer of insulating material positioned above said second source/drain region and between facing sidewall spacers on said second pair of transistor devices having said second gate pitch, so as to provide a remaining portion of said first layer of insulating material over said sidewall spacers on said second pair of transistor devices, said second contact opening extending through a portion of said first layer of insulating material; performing an etching process through said first contact opening to remove the facing sidewall spacers on said first pair of transistor devices and thereby exposing facing edges of the gate structures and the gate cap layers on said first pair of transistor devices; performing a common deposition and etch process sequence to form first and second low-k sidewall spacers within said first and second contact openings, respectively, wherein said first low-k sidewall spacer contacts the exposed facing edges of the gate structure of said first pair of transistor devices and said second low-k sidewall spacer is formed on said remaining portion of said first layer of insulating material within said second contact opening; forming a first source/drain conductive contact in said first contact opening contacting said first source/drain region and said first low-k sidewall spacer; and forming a second source/drain conductive contact in said second contact opening contacting said second source/drain region and said second low-k sidewall spacer.