Patent ID: 9711529
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A method for fabricating a 3D NAND device, comprising: providing a semiconductor substrate; forming a control gate structure having a plurality of staircase stacked layers and memory structures on the semiconductor substrate, each layer in the control gate structure having a first end and a second end opposing to the first end; forming a dielectric layer covering the semiconductor substrate, the memory structures, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the plurality of layers of the control gate structure; forming a photoresist layer on the hard mask layer and in the plurality of openings; repeating a photoresist trimming process and a first etching process to sequentially expose the plurality of openings, and to form a plurality of holes with predetermined depths in the dielectric layer above the corresponding second ends; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form a plurality of through holes; and forming a metal via in the through holes.