Patent ID: 9691878
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A method for manufacturing a MOSFET, comprising: forming a shallow trench isolation in a semiconductor substrate to define an active region for the MOSFET; performing etching with the shallow trench isolation as a hard mask so that a surface of the semiconductor substrate is exposed and a portion of the shallow trench isolation protrudes with respect to the surface of the semiconductor substrate to form a protruding portion; forming a first spacer on sidewalls of the protruding portion of the shallow trench isolation; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the shallow trench isolation, the gate stack, the first spacer and the second spacer as a hard mask, wherein each of the openings has a bottom surface and also sidewalls directly below the first spacer defined by the semiconductor substrate; epitaxially growing a semiconductor layer by using the bottom surface and the sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form a source region and a drain region.