Patent ID: 9679882
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A method comprising: attaching a plurality of first semiconductor dies to a top side of a first wafer, the first wafer comprising a plurality of second semiconductor dies; depositing a first photo-sensitive material layer over the top side of the first wafer, wherein the plurality of first semiconductor dies are surrounded by the first photo-sensitive material layer, wherein the first photo-sensitive material layer covers top surfaces of the plurality of first semiconductor dies; forming a plurality of first openings in the first photo-sensitive material layer by exposing the first photo-sensitive material layer to light and developing the first photo-sensitive material layer; plating a first conductive material in the plurality of first openings to form a first group of through assembly vias in the first photo-sensitive material layer and a plurality of first redistribution layers on top of the first photo-sensitive material layer; dicing the first wafer to form a plurality of first packages, each of the plurality of first packages comprising at least one of the plurality of first semiconductor dies and at least one of the plurality of second semiconductor dies; attaching at least one of the plurality of first packages to a top side of a second wafer, the second wafer comprising a plurality of third semiconductor dies; depositing a second photo-sensitive material layer over the top side of the second wafer, wherein the second photo-sensitive material layer surrounds the at least one of the plurality of first packages, and covers sidewalls and top surfaces of the first photo-sensitive material layer of the at least one of the plurality of first packages; forming a plurality of second openings in the second photo-sensitive material layer by exposing the second photo-sensitive material layer to light and developing the second photo-sensitive material layer; and plating a second conductive material in the plurality of second openings to form a second group of through assembly vias in the second photo-sensitive material layer and a plurality of second redistribution layers on top of the second photo-sensitive material layer.