Patent ID: 9684332
Date: 2017-06-20
CPC Classifications: G06F,H03K

Claim:
1. A timing control circuit, comprising: a first variable delay circuit configured to receive first data having a first communication speed, and to delay the first data by a variable delay; a first multiplexer configured to receive an output of the first variable delay circuit, and to convert, based on a reception clock, the first data into second data having a second communication speed different from the first communication speed; a second replicating variable delay circuit configured to receive third data having the first communication speed, and to delay the third data by another replicating variable delay which substantially replicates the variable delay of the first variable delay circuit according to a transmission clock for a second multiplexer transmitting the first data having the second communication speed to the first variable delay circuit; a decision circuit configured to compare a phase of the delayed third data output of the replicating second variable delay circuit and a phase of the reception clock; and a control circuit configured to control the variable delay of the first variable delay circuit and the another replicating variable delay of the second replicating variable delay circuit based on the comparison of the decision circuit.