Patent ID: 9734907
Date: 2017-08-15
CPC Classifications: G11C,H01L

Claim:
1. An apparatus comprising: a first memory array including first memory cells and a first group of conductive lines configured to access the first memory cells; a second memory array including second memory cells and a second group of conductive lines configured to access the second memory cells; a first group of transistors coupled to the first group of conductive lines, the first group of transistors configured to respond to a first signal; a first switching circuit configured to apply a signal to a selective conductive line of the first group of conductive lines, wherein the first switching circuit includes a phase change material; a second group of transistors coupled to the second group of conductive lines, the second group of transistors configured to respond to a second signal; and a second switching circuit configured to apply the signal to a selective conductive line of the second group of conductive lines, wherein the second switching circuit includes a phase change material.