Patent ID: 9727188
Date: 2017-08-08
CPC Classifications: G06F,G09G

Claim:
1. A touch display panel, comprising: a touch display unit and drive circuit units disposed at the periphery of the touch display unit, wherein the touch display unit comprises touch drive electrodes, the drive circuit unit comprises a first drive circuit unit and a second drive circuit unit which are electrically connected with two ends of each of the touch drive electrodes, respectively, and the first drive circuit unit is electrically connected with the second drive circuit unit through a first connecting line; wherein the first drive circuit unit comprises a first shift register unit, a first multi-channel strobe unit and a first output unit which are sequentially electrically connected, an output end of the first output unit is electrically connected with a first end of the touch drive electrode, and the second drive circuit unit comprises a second output unit, an output end of the second output unit is electrically connected with a second end of the touch drive electrode; wherein the first shift register unit comprises a first inverter, a second inverter, a third inverter, a first three-state inverter, a second three-state inverter and a first NAND gate, wherein a first electrode of the first inverter is electrically connected with a fourth electrode of the first three-state inverter and a third electrode of the second three-state inverter and is configured to receive a first clock signal, and a second electrode of the first inverter is electrically connected with a third electrode of the first three-state inverter and a fourth electrode of the second three-state inverter; a first electrode of the second inverter is electrically connected with a second electrode of the first three-state inverter and a second electrode of the second three-state inverter; a second electrode of the second inverter, a first electrode of the second three-state inverter and a second electrode of the first NAND gate are electrically connected together and are electrically connected to an input end of a next drive circuit unit; and the input end of the next drive circuit unit is an input end of a next adjacent shift register unit which is disposed on the same side as the present first shift register unit; a first electrode of the first three-state inverter is an input end of the first shift register unit; a first electrode of the first NAND gate is configured to receive a second clock signal, a third electrode of the first NAND gate is electrically connected with a first electrode of the third inverter, and a second electrode of the third inverter is an output end of the first shift register unit; the first multi-channel strobe unit comprises a fourth inverter, a first transmission gate and a first N-type transistor, wherein: