Patent ID: 9704861
Date: 2017-07-11
CPC Classifications: H01L

Claim:
1. An integrated circuit (IC) device comprising: a substrate including a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; source and drain features in the MOS region and separated by the gate region, wherein the gate region includes a fin structure and a nanowire over the fin structure, the nanowire extending from the source feature to the drain feature, the fin structure is an integral portion of the substrate formed of a first semiconductor material layer; a second semiconductor material layer disposed directly on the fin structure, the second semiconductor material layer being different than the first semiconductor material layer and having a top surface facing away from the substrate; a gate dielectric layer disposed directly on the top surface of the second semiconductor material layer; and a gate electrode layer disposed over the gate dielectric layer.