Patent ID: 9595590
Date: 2017-03-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate; a well region of a first conductivity type disposed in the substrate; an extended drain junction region disposed in the well region of a first conductivity type; a source region disposed in the well region; a drain region disposed in the extended drain junction region; a shallow trench isolation region disposed adjacent to the drain region; and a stepped gate oxide layer disposed on the extended drain junction region comprising a thin gate insulating layer and a thick gate insulating layer, the thick gate insulating layer being disposed closer to the drain region than the thin gate insulating layer; a gate electrode disposed above the stepped gate oxide layer; wherein the gate electrode is positioned to overlap an entire length of the thick gate insulating layer that overlaps the extended drain junction region, wherein the extended drain junction region overlaps with a portion of the thick gate insulating layer and a portion of the thin gate insulating layer, wherein the extended drain junction region extends laterally to a portion of the well region from the drain region, and wherein the well region of the first conductivity type is disposed to have a depth deeper than a depth of the shallow trench isolation region.