Patent ID: 9661339
Date: 2017-05-23
CPC Classifications: H04N

Claim:
1. A decoder apparatus comprising: a first processor of a multi-core processor configured to perform one or more first decoding operations in a decoding of a plurality of macroblocks of video in a bitstream; a second processor of said multi-core processor operating as a slave to said first processor and configured to perform one or more second decoding operations in said decoding of said macroblocks; and a third processor of said multi-core processor operating as a slave to said second processor and configured to perform one or more third decoding operations in said decoding of said macroblocks, wherein the first, second, and third processors are configured to operate in parallel during a first time slot on a first macroblock, a second macroblock, and a third macroblock of said macroblocks, respectively, wherein the second macroblock was previously operated on by the first processor in a second time slot prior to the first time slot, and the third macroblock was previously operated on by the first processor in a third time slot prior to the second time slot and by the second processor in the second time slot.