Patent ID: 9690730
Date: 2017-06-27
CPC Classifications: G06F

Claim:
1. A register slicing circuit, comprising: first and second register circuits configured to sequentially store requests received from a plurality of master devices to output the stored requests toward a slave device; a forward channel configured to send a first request from the first register circuit to the second register circuit; and a backward channel configured to send back a second request from the second register circuit to the first register circuit, wherein the requests each include a corresponding urgent flag, each urgent flag indicating whether or not an urgent service of the corresponding request is required such that a request having the urgent flag of a first value corresponds to an urgent request and a request having the urgent flag of a second value corresponds to a normal request, and wherein the first register circuit and the second register circuit are configured to perform an inter-node swapping operation based on the urgent flags for exchanging the first request and the second request.