Patent ID: 9612614
Date: 2017-04-04
CPC Classifications: G06F,H03K,Y02D

Claim:
1. A clock driver circuit for a resonant clock distribution network, the clock driver circuit comprising: at least one clock driver output stage having an output for driving a drive point of a sector of the resonant clock distribution network, having a clock input coupled to a global clock signal, and having a first enable input for enabling and disabling a pull-up driver of the at least one clock driver output stage and a second enable input for enabling and disabling a pull-down driver of the at least one clock driver output stage; a delay line having a selectable delay selected in conformity with a mode select input and further having an input for receiving the global clock signal, wherein the delay line further includes a mode select control logic responsive to the mode select input; and a clock pulse width control logic having a first output coupled to the first enable input of the clock driver output stage, a second output coupled to the second enable input of the clock driver output stage and an input coupled to an output of the delay line, wherein the clock pulse width control logic enables the at least one clock driver output stage in response to changes in state of global clock signal and disables the at least one clock driver output stage when the changes in state of the global clock signal have propagated through the delay line, and wherein the mode select control logic prevents the clock pulse width control logic from enabling the at least one clock driver output stage for a duration shorter than a delay time of the delay line when the mode select input changes state.