Patent ID: 9711482
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor package comprising: first semiconductor chips disposed in a rotationally symmetrical structure, the first semiconductor chips including a plurality of first bonding pads arranged over the bottom surfaces of the first semiconductor chips, wherein the first bonding pads are arranged such that two groups of the first bonding pads each haying two rows are arranged in a direction in which an edge of the first semiconductor chip extends and the two row groups are spaced apart at a certain distance from one another; a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips; a plurality of via patterns formed in the first encapsulation member; second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips, the second semiconductor chips including a plurality of second bonding pads electrically connected to the via patterns and arranged over bottom surfaces of the second semiconductor chips, wherein the second bonding pads are arranged such that two groups of the second bonding pads each having two rows are arranged in the direction in which the edge extends and the two row groups are spaced apart at a certain distance from one another; and a second encapsulation member formed over the top surfaces of the first semiconductor chips and the first encapsulation member to surround at least side surfaces of the second semiconductor chips.