Patent ID: 9627301
Date: 2017-04-18
CPC Classifications: H01L,H03F

Claim:
1. An integrated circuit arrangement comprising: a flange, the flange comprising conducting material; a transistor die disposed on a surface of the flange; an elongate capacitor bar disposed on the surface of the flange; a first conducting element defining a lead, the first conducting element being electrically connected to the transistor die via connecting elements to allow current flow from the transistor die; wherein the flange defines return current paths allowing the current flow via the connecting elements and the lead to return to the transistor die, wherein the flange comprises one or more reduced thickness portions, the one or more reduced thickness portions being configured to limit the return current paths and therewith to control current flow passing through the flange to the transistor die, wherein the one or more reduced thickness portions correspond to one or more pits in the flange surface, wherein the one or more pits comprise an elongate trench, wherein a longitudinal axis of the elongate trench is parallel to a longitudinal axis of the transistor die, wherein the elongate trench is located between at least one of: i) the elongate capacitor bar and the first conducting element or ii) the elongate capacitor bar and the transistor die.