Patent ID: 9548727
Date: 2017-01-17
CPC Classifications: H03K,H03L

Claim:
1. An oscillator circuit comprising: a plurality of delay elements, a first delay element of the plurality of delay elements configured to receive a first oscillator signal outputted from a second delay element of the plurality of delay elements, the second delay element being one stage before the first delay element, and to receive a second oscillator signal outputted from a third delay element of the plurality of delay elements, the third delay element being two or more stages before the first delay element, the plurality of delay elements being connected in a ring, and the first oscillator signal and the second oscillator signal having phases different from one another; a bias voltage generator configured to change a ratio of a first input bias current for the first oscillator signal to a second input bias current for the second oscillator signal, in accordance with a first bias voltage and a second bias voltage supplied to the plurality of delay elements; and a replica bias circuit configured to cause an output common level of the first delay element to be maintained when the first input bias current and the second input bias current are changed.