Patent ID: 9536751
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. A method for forming patterns for semiconductor device comprising: providing a substrate, the substrate comprising a hard mask layer and a sacrificial layer formed thereon; forming a plurality of spacer patterns parallel with each other on the substrate, the spacer patterns being directly formed on the sacrificial layer; removing portions of the sacrificial layer to form a plurality of recesses in the sacrificial layer; forming a plurality of first blocking layers respectively in the recesses; forming a plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion of the first blocking layers on the substrate after forming the first blocking layers; and etching the sacrificial layer and the hard mask layer with the spacer patterns, the first blocking layers and the second blocking layers serving as etching masks to form a patterned hard mask layer on the substrate.