Patent ID: 9741577
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first gate and a second gate arranged on a substrate; a trench arranged between the first gate and the second gate, the trench extends from a surface of the first gate and a surface of the second gate to the substrate; a liner disposed along sidewalls of the trench and a bottom portion of the trench in contact with the substrate; a high purity cobalt disposed in the trench directly on the liner, the high purity cobalt completely filling the bottom portion of the trench and forming a thin film on upper sidewalls of the trench such that a thickness of the high purity cobalt on the upper sidewalls is substantially thinner than a thickness that completely fills the bottom portion of the trench, the high purity cobalt comprising less than 200 ppm impurities; and a metal disposed directly on the high purity cobalt and filling remaining portions of the trench, the high purity cobalt and the metal forming a contact, the high purity cobalt being substantially free of voids, and the trench consisting essentially of the liner, the high purity cobalt, and the metal.