Patent ID: 9664753
Date: 2017-05-30
CPC Classifications: G01R

Claim:
1. A circuit, comprising: a Hall effect cell having first, second, third and fourth nodes; a first circuit having a first input coupled to the third node, a second input coupled to receive a non-zero force voltage and an output coupled to the first node, said first circuit configured to bias the first node at a first voltage and further provide a bias current flowing through the Hall effect cell from the first node to the second node; and a second circuit having a first input coupled to the fourth node, a second input coupled to receive a non-zero offset voltage different from said non-zero force voltage and an output coupled by a feedback resistor to the fourth node to maintain the fourth node at the non-zero offset voltage and generate an output voltage across terminals of said feedback resistor having a magnitude corresponding to an intensity of a magnetic field acting on the Hall effect cell and a sign corresponding to a direction of said magnetic field.