Patent ID: 9748960
Date: 2017-08-29
CPC Classifications: G11C,H03K,H03L,H04L

Claim:
1. A method for operating an integrated circuit device, comprising: phase-aligning a first data signal and a first timing signal to produce a second data signal: generating a second timing signal from the first timing signal using a frequency multiplying circuit the second timing signal being mesochronous with respect to the first timing signal; retiming the second data signal to produce a third data signal that is phase-aligned to a clock domain based on the second timing signal; determining whether a first phase-relationship between the second data signal and the clock domain based on the second timing signal is within an unsafe region for retiming the second data signal based on the second timing signal; when the first phase-relationship between the second data signal and the clock domain based on the second timing signal is within the unsafe region for retiming the second data signal based on the second timing signal, retiming the second data signal based on the first timing signal to produce a fourth data signal that has a second phase-relationship that is within a safe region for retiming the fourth data signal based on the second timing signal, and retiming the fourth data signal based on the second timing signal to produce the third data signal; and, when the first phase-relationship between the second data signal and the clock domain based on the second timing signal is within the safe region for retiming the data signal based on the second timing signal, retiming the second data signal based on the second timing signal to produce the third data signal.