Patent ID: 9721925
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method of making a semiconductor device, comprising: providing a first semiconductor die; providing a second semiconductor die; forming a first interconnect structure on a first surface of the first semiconductor die; forming a second interconnect structure on the first surface of the first semiconductor die including a height of the second interconnect structure over the first surface of the first semiconductor die greater than or equal to a height of the first interconnect structure over the first surface of the first semiconductor die added to a thickness of the second semiconductor die; forming a third interconnect structure on a first surface of the second semiconductor die with the third interconnect structure including a height of the third interconnect structure over the first surface of the second semiconductor die substantially equal to the height of the second interconnect structure over the first surface of the first semiconductor die; disposing the second semiconductor die over the first semiconductor die with the first interconnect structure extending from the first surface of the first semiconductor die to the first surface of the second semiconductor die; and depositing an encapsulant in contact with the first surface of the first semiconductor die and the first surface of the second semiconductor die after disposing the second semiconductor die over the first semiconductor die, wherein the second interconnect structure and third interconnect structure are exposed from the encapsulant.