Patent ID: 9747108
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. A processor comprising: a plurality of processor elements; and a first processor element to perform a user-level fork instruction of a software thread, the first processor element including: a decoder to decode the user-level fork instruction, wherein the user-level fork instruction is to indicate at least one instruction address; and a user-level thread fork module, in response to the user-level fork instruction being decoded, to configure each of the plurality of processor elements to perform instructions in parallel, wherein each of the plurality of processor elements is to perform a corresponding user-level synchronize and end instruction, and wherein each of the plurality of processor elements comprises: a decoder to decode the corresponding user-level synchronize and end instruction; and a user-level synchronized thread end module, in response to the corresponding user-level synchronize and end instruction being decoded, to cause the corresponding processor element in which it is included to: stop performing additional instructions; wait until each of the plurality of processor elements has performed the corresponding user-level synchronize and end instruction; and transfer control to a second instruction of the software thread that is to be performed on the first processor element, after each of the plurality of processor elements has performed the corresponding user-level synchronize and end instruction.