Patent ID: 9654093
Date: 2017-05-16
CPC Classifications: H03K,H03L

Claim:
1. An electronic device, comprising: a first duty cycle correction circuit configured to receive a clock signal and detect a duty cycle error of the clock signal by performing a time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the detected duty cycle error of the clock signal; a delay line configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code; a second duty cycle correction circuit configured to receive a first output clock signal through a feedback loop, to detect a duty cycle error of the first output clock signal by performing an integration operation on the first output clock signal, and to generate a second output clock signal by adjusting a duty cycle of the delayed corrected clock signal based on the detected duty cycle error of the first output clock signal; and a delay control circuit configured to receive the clock signal and to generate the delay control code based on the clock signal and the first output clock signal.