Patent ID: 9727474
Date: 2017-08-08
CPC Classifications: G06F

Claim:
1. A non-blocking texture cache memory configured by a processor, the non-blocking texture cache memory comprising: an in-order retry buffer configured to store result data for a previous texture request, according to a hit pipeline and a miss pipeline of the texture cache memory, in respective addresses of corresponding fragment ID information and texture request ID information of the retry buffer; a lookup retry buffer configured to look up the retry buffer in response to a new texture request and before a performing of a cache hit/miss determination of a local cache, storing texture data, based on a texture address corresponding to the new texture request; a verifier configured to verify whether result data corresponding to the new texture request is stored in the retry buffer; an output controller configured to output the stored result data when the verifier verifies that the result data corresponding to the new texture request is stored in the retry buffer; and a cache hit/miss determiner including the local cache storing texture data, the cache hit/miss determiner configured to, when the verifier verifies that the result data corresponding to the new texture request is not stored in the retry buffer, generate the texture address corresponding to the new texture request and then to perform a determining of the cache hit/miss determination of whether texture data is a cache hit or a cache miss in the local cache based on the generated texture address.