Patent ID: 9741639
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor chip, comprising: a chip metallization applied on the semiconductor body and having an underside facing away from the semiconductor body; and a layer stack directly contacting the underside of the chip metallization and having a number N wherein the first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers, wherein each of the first partial layers comprises an alloying metal, wherein each of the second partial layers comprises a solder which can form an intermetallic phase with the alloying metal of the first partial layer adjoining that second partial layer, the intermettalic phase formed by an interdiffusion of metal atoms of the first partial layers and of metal atoms of the second partial layers, the intermetallic phase having a melting point significantly higher than a melting point of the second partial layers.