Patent ID: 9742408
Date: 2017-08-22
CPC Classifications: G11C,H03K

Claim:
1. A dynamic decode circuit for decoding a plurality of input signals, the dynamic decode circuit comprising: a decoder comprising a plurality of decode transistors, the decode transistors configured to cause a first node to be in a first state based on the input signals being in a first input signal state and an evaluation clock signal being active; the decode transistors configured to cause the first node to be in a second state based on the input signals being in a second input signal state other than the first input signal state and the evaluation clock signal being active; an evaluate clock circuit conductively connected between a first power source and a second node, the evaluate clock circuit consisting of a first transistor and a second transistor, the first transistor serially connected by a first interconnecting node to the second transistor, the first transistor comprising a first gate configured to receive the evaluation clock signal, the first transistor configured to conduct based on the evaluation clock signal being active, the second transistor comprising a second gate conductively connected to the first node, the first transistor configured to not conduct based on the evaluation clock signal being inactive; and one or more precharge circuits conductively connected to a second power source, the one or more precharge circuits configured to precharge the first node and the second node and the first interconnecting node based on the evaluation clock signal being inactive, the one or more precharge circuits configured to not conduct based on the evaluation clock signal being active.