Patent ID: 9614102
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. An active matrix backpanel including an array of metal oxide TFTs with reduced inter-electrode capacitance, each TFT of the array of TFTs comprising: a transparent substrate having a front surface and a rear surface; an opaque gate metal positioned on the front surface of the substrate and defining a gate area for the TFT and gate selection bus-lines of the active matrix; a layer of transparent gate dielectric material positioned on the front surface of the substrate overlying the gate metal and a surrounding area; a layer of transparent metal oxide semiconductor material positioned on the surface of the layer of transparent gate dielectric; a layer of etch stop material positioned on the layer of metal oxide semiconductor material overlying and aligned with the gate metal, the layer of the etch stop material defining a channel area in the layer of metal oxide semiconductor material; and conductive material patterned to form data lines of the active matrix crossing over the gate/selection lines and source/drain electrodes on opposed sides of the channel area of each TFT, wherein the source/drain contacts are aligned on a portion of the etch stop layer overlying and aligned with the gate metal and on the layer of metal oxide semiconductor material.