Patent ID: 9741609
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A method of fabricating features of a semiconductor device, the method comprising: forming a contact over a substrate, the contact comprising a cobalt core and a liner layer arranged on sidewalls, wherein the contact includes a portion that is laterally surrounded by an interlevel dielectric (ILD); depositing an another layer of ILD on the contact; etching a first opening in the another layer of ILD to expose a surface of the contact; removing the liner layer of the contact to expose a portion of the cobalt core; etching the ILD that laterally surrounds the contact to form a second opening beneath the first opening, the second opening having a width that is less than the first opening; depositing a liner on sidewalls of the first opening, the second opening, and directly on the cobalt core; and depositing a metal on the liner layer to form an interconnect structure.