Patent ID: 9673227
Date: 2017-06-06
CPC Classifications: G09G,H01L

Claim:
1. A method for manufacturing a thin-film transistor (TFT) substrate, comprising the following steps: (1) providing a substrate, depositing a first metal layer on the substrate, and applying a photolithographic process to patternize the first metal layer so as to form a first gate terminal and a second gate terminal that are spaced from each other; (2) depositing a gate insulation layer on the first gate terminal, the second gate terminal, and the substrate; (3) depositing a semiconductor layer on the gate insulation layer and applying a photolithographic process to patternize the semiconductor layer into a patterned semiconductor layer having a first semiconductor, a connection semiconductor, and a second semiconductor that are arranged in sequence and are contiguously connected, wherein the first semiconductor is located above and corresponding to the first gate terminal; the second semiconductor is located above and corresponding to the second gate terminal; and the connection semiconductor is located between the first semiconductor and the second semiconductor; (4) depositing an etch stop layer on the semiconductor layer and applying a photolithographic process to form a first through hole, a second through hole, and a third through hole that are spaced from each other in the etch stop layer, wherein the first through hole, the second through hole, and the third through hole respectively expose an end of the first semiconductor that is distant from the connection semiconductor, the connection semiconductor, and an end of the second semiconductor that is distant from the connection semiconductor; (5) with the etch stop layer as a shielding layer, applying N-type heavy doping, through the first through hole, the second through hole, and the third through hole, to the end of the first semiconductor that is distant from the connection semiconductor, the connection semiconductor, and the end of the second semiconductor that is distant from the connection semiconductor, so as to form a first source contact zone and a first channel zone in the first semiconductor and to form a second channel zone and a second drain contact zone in the second semiconductor in such a way that opposite ends of the connection semiconductor are respectively connected to the first channel zone and the second channel zone, wherein the first source contact zone, the connection semiconductor, and the second drain contact zone are all N-type heavily doped zones; and (6) depositing a second metal layer on the etch stop layer and applying a photolithographic process to patternize the second metal layer to form a first source terminal and the second drain terminal that are spaced from each other, wherein the first source terminal is set in contact with the first source contact zone via the first through hole; and the second drain terminal is set in contact with the second drain contact zone via the third through hole; and wherein the first gate terminal, the first semiconductor, the first source terminal, and the N-type heavily doped connection semiconductor constitute a first TFT; the second gate terminal, the second semiconductor, the N-type heavily doped connection semiconductor, and the second drain terminal constitute a second TFT; and the first TFT and the second TFT are connected in series through the N-type heavily doped connection semiconductor.