Patent ID: 9697119
Date: 2017-07-04
CPC Classifications: G06F,H03M

Claim:
1. A method of optimizing use of a configuration memory of a reconfigurable processor, the method comprising: analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and details of the configuration memory; scheduling groups of function units (FUs), which will be activated in each cycle of the loop, according to the analyzed parallelism to generate configuration data of each cycle; and sequentially mapping the generated configuration data in at least one row of the configuration memory that is divided into fields having different sizes, with respect to the scheduled groups, determining whether regular encoding is possible with respect to the configuration data, based on the architecture and the details of the configuration memory, and in response to a determination that the regular encoding is not possible, some or all of bits of the configuration data are mapped in the fields having the different sizes.