Patent ID: 9660060
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A thin film transistor, comprising: a semiconductor stacked layer including a first metal oxide semiconductor layer and a second metal oxide semiconductor layer disposed on an upper surface of the first metal oxide semiconductor layer, and the upper surface of the first metal oxide semiconductor layer is an interface between the first metal oxide semiconductor layer and the second metal oxide semiconductor layer, wherein a resistance value of the first metal oxide semiconductor layer is less than a resistance value of the second metal oxide semiconductor layer; an insulating layer disposed on the semiconductor stacked layer; a gate disposed on the insulating layer; a dielectric layer covering the gate, wherein the dielectric layer has a plurality of contact openings that expose a portion of the upper surface of the first metal oxide semiconductor layer; and a source and a drain, disposed on the dielectric layer and filled into the contact openings to electrically connect with the semiconductor stacked layer, wherein the source and the drain contact the exposed portion of the upper surface of the first metal oxide semiconductor layer through the contact openings.