Patent ID: 9710226
Date: 2017-07-18
CPC Classifications: G06F

Claim:
1. A memory module, comprising: a first memory device to perform a first verify operation after a first attempted write, the first memory device to store a first entry in a first internal write retry buffer in response to the first verify operation determining the first attempted write failed, the first memory device to output a first indicator to indicate to a memory controller when the first internal write retry buffer meets a threshold criteria associated with unused entries in the first internal write retry buffer; a second memory device to perform a second verify operation after a second attempted write, the second memory device to store a second entry in a second internal write retry buffer in response to the second verify operation determining the second attempted write failed, the second memory device to output a second indicator to indicate to the memory controller when the second internal write retry buffer meets the threshold criteria associated with unused entries in the second internal write retry buffer; wherein, in response to a command from a memory controller, the first memory device is to retry the first attempted write using the first entry and the second memory device retry the second attempted write using the second entry; and, wherein the second memory device is to perform a third verify operation after a third attempted write, the third attempted write to occur concurrently with the first attempted write, and, in response to the third verify operation determining the third attempted write succeeded, the second memory device not to store an entry in the second internal write retry buffer.