Patent ID: 9601432
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A method for forming an integrated circuit comprising: patterning a substrate including a first contact hole in a first dielectric layer, wherein the contact hole includes sidewalls formed of the first dielectric layer and a bottom surface is in contact with a device layer of the integrated circuit; depositing tungsten into the first contact hole forming a first tungsten via, the first tungsten via having a bottom surface in contact with the device layer and a top surface; patterning a second dielectric layer over a first portion of the first dielectric layer and a first portion of the top surface of the tungsten via, the patterning including an etch step which damages a second portion of the top surface of the first tungsten via, wherein a pattern formed by the patterning is for a metal line layer in electrical contact with the first tungsten via, wherein the etch step includes an overetch which reduces a height of a top surface of a second, unprotected portion of the first dielectric layer lower than a height of a top surface of the first portion of the first dielectric layer, wherein the first portion of the first dielectric layer is protected by a pattern of the second dielectric layer; and selectively depositing a metal layer over the second portion of the top surface of the first tungsten via to form a metal repair layer to repair damage caused by the etch step.