Patent ID: 9614439
Date: 2017-04-04
CPC Classifications: G05F,G11C,H02M,H03K

Claim:
1. A semiconductor device comprising: a booster circuit configured to boost an input voltage and generate a first boosted voltage; a voltage hold circuit configured to hold a second boosted voltage having a smaller absolute value than the first boosted voltage; a first output terminal configured to output the first boosted voltage as first output; a second output terminal configured to output the second boosted voltage as second output; a first switch that is placed between the first output terminal and the second output terminal; and a control circuit configured to generate a switch signal for switching the first switch from close to open in response to an output voltage of the booster circuit reaching a hold voltage level set to the voltage hold circuit, wherein during a first period when the switch signal indicates close of the first switch, the voltage hold circuit is further configured to increase or decrease a voltage value of the second boosted voltage to be output in accordance with the output voltage of the booster circuit, and during a second period when the switch signal indicates open of the first switch, the voltage hold circuit is further configured to maintain a constant voltage value of the second boosted voltage at a point when a value of the switch signal is switched from close to open.