Patent ID: 9716598
Date: 2017-07-25
CPC Classifications: H04L

Claim:
1. An information processing device including a plurality of data transfer processors, comprising: a first data transfer processor configured to use a first data transmission path only; a second data transfer processor configured to use a second data transmission path only; a control processor configured to monitor whether or not a data transfer by the first data transfer processor is available in the plurality of data transfer processors; the control processor configured to inhibit, based on monitoring of the control processor, the data transfer of the second data transfer processor while the data transfer by the first data transfer path is available; a memory configured to store an additional program to be newly added; and the control processor configured to inhibit the additional program from being added to the memory while the data transfer by the first data transfer processor is available, wherein the first data transfer processor and the second data transfer processor are within the information processing device, wherein data is prevented from being leaked out from the first data transfer processor by inhibiting the data transfer while the data transfer by the second data transfer processor is available, wherein the control processor repeats monitoring until the data transfer by the first data transfer processor is available, wherein the control processor inhibits the data transfer of each data transfer processor by rewriting a value in a control register, a function pointer, control or table information of a device corresponding to each data transfer processor, or rewriting a part or the whole of the data related to the data transfer of each data transfer processor, wherein the control processor cancels the inhibition of the data transfer by returning the value in the control register to a previous value, by returning the function pointer to a previous status, or by rewriting the control information or the table information to the previous status, wherein the previous value is a value before being rewritten, and the previous status is a status before being rewritten, wherein an inhibition target information further defines the additional program inhibited from being added to the memory, and wherein the control processor inhibits the additional program from being added to the memory by referring to the inhibition target information.