Patent ID: 9612281
Date: 2017-04-04
CPC Classifications: G01R,H03K

Claim:
1. A flip-flop, comprising: a scan-in clock path configured to delay a flip-flop clock signal by a first delay to produce a scan-in clock signal responsive to an assertion of a scan mode enable signal; a scan-in signal path configured to propagate a scan-in signal to a master latch state node responsive to an assertion of the scan-in clock signal; a data clock path configured to delay the flip-flop clock signal by a second delay greater than the first delay to produce a data clock signal responsive to a de-assertion of the scan mode enable signal; a data path configured to propagate a data input signal to the master latch state node responsive to an assertion of the data clock signal; and a master latch including a keeper cross-coupled with a master latch inverter, the master latch state node being an input node to the master latch inverter.