Patent ID: 9645824
Date: 2017-05-09
CPC Classifications: G06F

Claim:
1. Apparatus for processing data comprising: prefetch circuitry configured to prefetch from a sequence of addresses within a memory program instructions to be executed; a branch target address cache coupled to said prefetch circuitry and configured to store: tag value generating circuitry configured to generate said tag value by performing a hashing function upon a portion of said fetch address, said tag value having bit length less than a bit length of said portion of said fetch address; wherein the branch target address cache is configured to detect a hit for the branch target data associated with one of said previously encountered branch instructions when a tag value generated by the tag value generating circuitry by performing the hashing function upon a portion of said fetch address is detected to match the tag value stored in the branch target address cache for said one of said previously encountered branch instructions, even if said one of said previously encountered branch instructions was fetched from a different address to said fetch address, wherein said hashing function operates upon a plurality of contiguous fields of contiguous bits of said fetch address, and wherein a first field of said plurality of contiguous fields has a lowest bit order within said fetch address of said plurality of contiguous fields and comprises a number of bits equal to a number of bits of said tag value and each bit in descending bit order within said tag value is dependent upon a bit within said first field following a descending bit order within said fetch address.