Patent ID: 9548392
Date: 2017-01-17
CPC Classifications: H01L

Claim:
1. A method of manufacturing a thin film transistor, the method comprising: providing a substrate; successively forming a gate electrode and an electrically insulating layer on the substrate; forming an electric conducting layer on the electrically insulating layer; forming a first photoresist layer on the electric conducting layer; photolithographing the first photoresist layer from a top face and a bottom face by using a photo mask as a top face photo mask and the gate electrode as a bottom face photo mask to form a first photoresist pattern layer; etching a portion, which is not covered by the first photoresist pattern layer, of the electric conducting layer to form an electric conduction layer; forming a semiconductor layer on the electric conduction layer; forming a second photoresist layer on the semiconductor layer; photolithographing the second photoresist layer from a top face and a bottom face using the photo mask as a top face photo mask and the gate electrode as a bottom face photo mask to form a second photoresist pattern layer; etching a portion, which is not covered by the second photoresist pattern layer, of the semiconductor layer to form a channel layer covering the electric conduction layer; and forming a source electrode and a drain electrode at two lateral portions of the channel layer respectively.