Patent ID: 9741838
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type on the first semiconductor region; a third semiconductor region of the first conductivity type on the second semiconductor region such that the second semiconductor region is between first and third region in a first direction; a plurality of gate electrodes on the second semiconductor region and extending through the third semiconductor region in the first direction, the plurality of gate electrodes extending in a second direction and spaced from each other in a third direction, the second and third directions crossing each other and being parallel to a plane of the first semiconductor region, the first direction extending away from the plane; a fourth semiconductor region of the second conductivity type on the third semiconductor region, a concentration of second conductivity type impurities in the fourth semiconductor region being greater than a concentration of second conductivity type impurities in the second semiconductor region; a fifth semiconductor region of the first conductivity type on the third semiconductor region and adjacent to the fourth semiconductor region in the second direction, a concentration of first conductivity type impurities in the fifth semiconductor region being greater than a concentration of first conductivity type impurities in the third semiconductor region, wherein each gate electrode includes: a first insulating film on the plurality of gate electrodes and the second, third, fourth, and fifth semiconductor region; a first interconnect portion disposed on the first or second portion of at least one gate electrode in the plurality of gate electrodes, extending in the first direction through the first insulating film to electrically connecting the gate electrode to a gate pad; and a second interconnect portion disposed on the fourth and fifth semiconductor regions, extending in the first direction through the first insulating film, and electrically connecting the fourth and fifth semiconductor regions to an emitter pad.