Patent ID: 9583584
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A method of producing an integrated circuit comprising: forming a work function layer overlying a substrate and a plurality of dielectric columns, wherein the plurality of dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width; forming a first organic layer overlying the work function layer; recessing the first organic layer in the long region to about the long region work function height; recessing the first organic layer in the short region to about the short region work function height; recessing the work function layer in the long region to a long region work function height, wherein the long region work function height is between a dielectric column top surface and a substrate top surface; and recessing the work function layer in the short region to a short region work function height, wherein the short region work function height is between the dielectric column top surface and the substrate top surface, and wherein recessing the work function layer in the long region and recessing the work function layer in the short region is conducted in the absence of lithography techniques.