Patent ID: 9608604
Date: 2017-03-28
CPC Classifications: H03K

Claim:
1. A voltage level shifter with reduced layout area, comprising: an inverter including a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate coupled to an input terminal, a source coupled to a first positive voltage (VDDL) and a first bulk formed within a Nwell coupled to a second positive voltage (VDD) which is higher than VDDL; a second PMOS transistor with its gate coupled to the inverter via an NMOS transistor, the second PMOS transistor has a source and a second bulk formed within said Nwell coupled to the VDD, and a drain coupled to an output node; and a third PMOS transistor having a gate coupled to the output node, a source and a third bulk formed within said Nwell coupled to the VDD, and a drain coupled to the gate of the second PMOS transistor, respectively, such that the VDDL voltage level at the input terminal is shifted to the VDD voltage level at the output node.