Patent ID: 9620193
Date: 2017-04-11
CPC Classifications: G11C

Claim:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cell rows; and a refresh control circuit configured to perform a normal refresh operation on the plurality of memory cell rows and configured to perform a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows, each of the weak pages including at least one weak cell whose data retention time is smaller than normal cells, wherein the refresh control circuit is configured to transmit a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages, and wherein the refresh control circuit is configured to simultaneously perform the weak refresh operation on the weak pages with the normal refresh operation on the memory cell rows when the refresh control circuit performs the normal refresh operation on the memory cell rows in response to a first command from the memory controller.