Patent ID: 9646886
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method, comprising: forming one or more first gate stacks and one or more second gate stacks on a semiconductor material substrate, in a planar or a non-planar configuration, wherein the one or more first gate stacks have a threshold voltage (Vt) different from the one or more second gate stacks; forming the one or more first gate stacks comprising a first silicon material layer disposed directly on a first region of the semiconductor material substrate, in a planar or a non-planar configuration, a first dielectric material layer disposed on the first silicon material layer, and a masking layer disposed on the first dielectric material layer; forming the one or more second gate stacks comprising a second silicon material layer disposed directly on a second region of the semiconductor material substrate, in a planar or a non-planar configuration, a second dielectric material layer disposed on the second silicon material layer; and causing the hydrogen content of the first silicon material layer to be different from the hydrogen content of the second silicon material layer by: forming a catalytic material layer on top of the second dielectric material layer and forming no catalytic material layer on top of the first dielectric material layer, wherein the catalytic material layer is selected from the group consisting of rhodium, ruthenium, and nickel.