Patent ID: 9643558
Date: 2017-05-09
CPC Classifications: B60R

Claim:
1. A system for detecting a mismatch between first and second input signals, comprising: a first analog-to-digital converter (ADC) for receiving the first input signal and generating a first digital output signal; a second ADC for receiving the second input signal and generating a second digital output signal; a time-division multiplexing (TDM) circuit, connected to the first and second ADCs, for receiving and time-division multiplexing the first and second digital output signals, and outputting a TDM signal; a first processor connected to the TDM circuit for receiving the TDM signal and generating a first processed output signal; a time-division de-multiplexing (TDDM) circuit, connected to the first processor, for receiving and time-division de-multiplexing the first processed output signal, and outputting first and second TDDM signals, respectively; a second processor connected to the first ADC for receiving the first digital output signal and generating a second processed output signal; a first gating circuit, connected to the TDDM circuit and the second processor, for receiving the first TDDM signal and the second processed output signal, respectively, comparing the first TDDM signal with the second processed output signal, and generating a first gating signal indicating a mismatch between the first TDDM signal and the second processed output signal; a third processor connected to the second ADC for receiving the second digital output signal and generating a third processed output signal, wherein the first processor comprises: wherein the second processor comprises: wherein the third processor comprises: wherein the gating circuit comprises a first comparison circuit, connected to the TDDM circuit and the second HPF, for receiving and comparing the first TDDM signal and the second processed output signal; and a second gating circuit connected to the TDDM circuit and the third HPF for receiving and comparing the second TDDM signal and the third processed output signal, and generating a second gating signal, and wherein bandwidths of the second and third IIR filters are greater than a bandwidth of the first IIR filter, and bandwidths of the second and third HPFs are greater than a bandwidth of the first HPF.