Patent ID: 9570355
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first gate and a second gate disposed on a substrate, a dielectric material layer disposed on the substrate around and between the first gate and the second gate; a patterned hard mask arranged on the dielectric material layer, the patterned hard mask having an opening that exposes surfaces of the first gate and the second gate; and a patterned soft mask arranged on the dielectric material layer between the first gate and the second gate such that a portion of a hard mask arranged on the first gate is exposed, and a portion of a hard mask arranged on the second gate is exposed; wherein the dielectric material layer between the first gate and the second gate extends from a sidewall of the first gate to a sidewall of the second gate, has a sidewall that is substantially perpendicular to the first gate and the second gate, and a top surface of the dielectric material layer is substantially flush with a top surface of the hard mask of the first gate and a top surface of the hard mask of the second gate.