Patent ID: 9620384
Date: 2017-04-11
CPC Classifications: H01L

Claim:
1. A method of forming a semiconductor structure, the method comprising: depositing a first dielectric layer over a substrate and over a dummy gate structure; depositing a second dielectric layer over the deposited first dielectric layer; forming a spacer pair on the dummy gate structure based on a portion of the second dielectric being deposited on a portion of the first dielectric layer located on opposing sidewalls of the dummy gate structure; removing the dummy gate structure and forming a recess region; forming, within the recess region, a gate dielectric layer, wherein the formed gate dielectric layer is located on the portion of the first dielectric layer and top surface of the substrate exposed by the recess region; depositing, within the recess region, a gate electrode on the gate dielectric layer; and subsequent to the depositing, within the recess region, a gate electrode on the gate dielectric layer, exposing the semiconductor structure to an oxygen environment, wherein the portion of the first dielectric layer transports oxygen to the gate dielectric layer when exposing the semiconductor structure to an oxygen environment, wherein exposing the semiconductor structure to an oxygen environment comprises an oxygen anneal.