Patent ID: 9607992
Date: 2017-03-28
CPC Classifications: G06F,H01L

Claim:
1. A semiconductor device, comprising, a first inter-layer dielectric (ILD) layer disposed above a silicon substrate; a first etch stop layer disposed on the first ILD layer; a second ILD layer disposed on the first etch stop layer; a second etch stop layer disposed on the second ILD layer; a third ILD layer disposed on the second etch stop layer; a third etch stop layer disposed on the third ILD layer; a metal-insulator-metal (MIM) capacitor formed along sidewalls and a bottom of a trench extending through the third etch stop layer, the third ILD layer, the second etch stop layer, the second ILD layer, and the first etch stop layer; a first plurality of metal lines in the second ILD layer and laterally adjacent the MIM capacitor; and a second plurality of metal lines in the third ILD layer and laterally adjacent the MIM capacitor.