Patent ID: 9583220
Date: 2017-02-28
CPC Classifications: G11C

Claim:
1. A memory circuit comprising: a first array of non-volatile memory cells formed along a plurality of word lines and a plurality of columns, wherein the columns are subdivided into a plurality of N divisions, each division formed of a plurality of contiguous columns, where the word lines span all of the columns of the array; a first plurality of N sets of access circuitry, each connectable to the columns of a corresponding division of the first array, wherein N is an integer greater than one; a serializer circuit connected to the first plurality of sets of access circuitry to receive in parallel each of N words of data from a corresponding one of the first plurality of sets of access circuitry and connected to a data bus to transfer thereto the received data in a word-wide serial data format according to a first clock signal; and column redundancy circuitry connected to the serializer circuit to provide defective column information thereto, whereby, in converting data from a parallel to a serial format the serializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location thereof corresponds to a defective column.