Patent ID: 9565041
Date: 2017-02-07
CPC Classifications: H04L

Claim:
1. A double-data-rate (DDR) receiver comprising: an equalizer to issue an equalized data signal responsive to an input data signal; a first data sampler to sample the equalized data signal on edges of a first data-clock signal, thereby generating a first series of data samples; a second data sampler to sample the equalized data signal on edges of a second data-clock signal, thereby generating a second series of data samples; an edge sampler to sample at least one of the input data signal and the equalized data signal on edges of an edge-clock signal, thereby generating a series of edge samples; and equalizer control circuitry to receive the first series of data samples, the second series of data samples, and the series of edge samples, the equalizer control circuitry including a phase detector to generate a relative-timing signal responsive to the first series of data samples and the series of edge samples, the equalizer control circuitry to adjust the equalizer responsive to the relative-timing signal and a specific pattern of the first and second series of data samples, the specific pattern including successive first bit values followed by a transition to a second bit value.