Patent ID: 9658960
Date: 2017-05-23
CPC Classifications: G06F

Claim:
1. A method implemented by a cache controller in a processor for controlling tag lookup request messages from a compute unit to one of a plurality of subcaches, each respectively having a multiplexer on its input, comprising: controlling a multiplexer to select a first tag lookup request at a first input of the multiplexer, the first input being directly connected to the compute unit with no intervening controller; forwarding the selected tag lookup request to a first subcache of the plurality of subcaches that is physically closest to the compute unit relative to each of the plurality of subcaches; responsive to obtaining a second tag lookup request, from a second compute unit, that is directed to the first subcache, providing the second tag lookup request to the multiplexer via a second input of the multiplexer, the second input being coupled to the cache controller; controlling the multiplexer to select the second tag lookup request at the second input of the multiplexer; and forwarding the second tag lookup request to the first subcache.