Patent ID: 9680002
Date: 2017-06-13
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first doped layer implanted in a semiconductor substrate forming one of a source or a drain; a first dielectric layer disposed over the first doped layer; a gate metal layer disposed over the first dielectric layer; a second dielectric layer disposed over the gate metal layer; a second doped layer disposed over the second dielectric layer forming the other of the source or the drain, wherein the first doped layer, the first dielectric layer, the gate metal layer, the second dielectric layer, and the second doped layer form a vertical stack of layers of the semiconductor device; and a conduction channel formed in a trench that extends vertically through the first dielectric layer, the gate metal layer, and the second dielectric layer, wherein a width of the conduction channel at the gate metal layer is smaller than a width of the conduction channel at the first dielectric layer underneath the gate metal layer.