Patent ID: 9601199
Date: 2017-03-21
CPC Classifications: G06F,G11C

Claim:
1. A memory system comprising: a memory to store data in a pointer-linked data structure, the pointer-linked data structure including a plurality of nodes; and a processor in communication with the memory, the processor including at least one iterator register, wherein the iterator register is to store a first pointer chain that specifies a location of a first data element within the pointer-linked data structure from a root node, of the plurality of nodes, to a leaf node, of the plurality of nodes, wherein the first pointer chain includes a first, a second, and a third pointer, wherein the first pointer points to the second pointer and the second pointer points to the third pointer; and wherein when a subsequent access of data in the pointer-linked data structure causes a writing of a second pointer chain, associated with access of a second data element within the pointer-linked data structure, to the iterator register and the second pointer chain includes one or more same pointers as included in the first pointer chain, a first portion of the iterator register is to store only a portion of the second pointer chain not in common with the first pointer chain and a second portion of the iterator register is to retain the one or more same pointers as included in the first pointer chain.