Patent ID: 9608002
Date: 2017-03-28
CPC Classifications: A45F,B24B,B26B,G11C,H01L

Claim:
1. A semiconductor device comprising: first memory cells provided in a first stacked body including first electrode layers alternately stacked with a plurality of first insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor portion as channels extending inside the first stacked body; and second memory cells provided in a second stacked body including second electrode layers alternately stacked with a plurality of second insulating layers therebetween, the second memory cells having the second electrode layers as control gates and a second semiconductor portion as channels extending inside the second stacked body and being electrically connected to the first semiconductor portion; wherein a central axis of the first semiconductor portion and a central axis of the second semiconductor portion are shifted in a direction perpendicular to a stacking direction of the first and second stacked bodies, and an intermediate layer is provided above the first stacked body and below the second stacked body, the intermediate layer being made of a material different from the first and second electrode layers and the first and second insulating layers.