Patent ID: 9628050
Date: 2017-04-18
CPC Classifications: G09G,H03K

Claim:
1. A scan driving circuit configured for driving cascaded scan lines, the scan driving circuit comprising: an input control module inputted with a first clock signal of a current stage, cascade signals of a preceding stage, and cascades signal of a succeeding stage, and for generating a control signal based upon the first clock signal of the current stage, the cascade signals of the preceding stage, and the cascade signals of the succeeding stage; a latch module for performing a latch operation for the control signal; a driving-signal generation module for generating a driving signal based upon the control signal and a second clock signal of the current stage; an output control module for outputting a scanning signal of the current stage based upon the driving signal; a constant high voltage source for providing a high voltage; and a constant low voltage source for providing a low voltage, wherein an inverted signal of the control signal is used as cascade signals on the current stage and outputted into the scan driving circuit on the succeeding stage, wherein the input control module includes a 19th switching transistor, a 20th switching transistor, a 21st switching transistor, a 22nd switching transistor, a 23rd switching transistor, and a 24th switching transistor, wherein a control end of the 19th switching transistor is connected with an output end of the driving-signal generation module, an input end of the 19th switching transistor is connected with the constant high voltage source, and an output end of the 19th switching transistor is connected with a control end of the 21st switching transistor and a control end of the 22nd switching transistor, wherein a control end of the 20th switching transistor is connected with the output end of the driving-signal generation module, an input end of the 20th switching transistor is connected with the constant low voltage source, and an output end of the 20th switching transistor is connected with the control end of the 21st switching transistor and the control end of the 22nd switching transistor, wherein an input end of the 21st switching transistor is connected with the constant high voltage source, and an output end of the 21st switching transistor is connected with a control end of the 23rd switching transistor and a control end of the 24th switching transistor, wherein an input end of the 22nd switching transistor is connected with the constant low voltage source, and an output end of the 22nd switching transistor is connected with the control end of the 23rd switching transistor and the control end of the 24th switching transistor, wherein an input end of the 23rd switching transistor is connected with the constant high voltage source, and an output end of the 23rd switching transistor is connected with an output end of the output control module, wherein an input end of the 24th switching transistor is connected with the constant low voltage source, and an output end of the 24th switching transistor is connected with the output end of the input control module, wherein the 19th switching transistor, the 21st switching transistor and the 23rd switching transistor are PMOS transistors, and the 20th switching transistor, the 22nd switching transistor and the 24th switching transistor are NMOS transistors, the input control module includes a 1st switching transistor, a 2nd switching transistor, a 3rd switching transistor, a 4th switching transistor, a 5th switching transistor, and a 6th switching transistor, wherein a control end of the 1st switching transistor is inputted with the first clock signal of the current stage, an input end of the 1st switching transistor is connected with the constant high voltage source, and an output end of the 1st switching transistor is connected with an output end of the input control module, wherein a control end of the 2nd switching transistor is inputted with the cascade signals of the preceding stage, an input end of the 2nd switching transistor is connected with the constant high voltage source, and an output end of the 2nd switching transistor is connected with an input end of the 3rd switching transistor, wherein a control end of the 3rd switching transistor is inputted with the cascade signals on the succeeding stage, and an output end of the 3rd switching transistor is connected with the output end of the input control module, wherein a control end of the 4th switching transistor is inputted with the first clock signal of the current stage, an input end of the 4th switching transistor is connected with an output end of the 5th switching transistor, and an output end of the 4th switching transistor is connected with the output end of the input control module, wherein a control end of the 5th switching transistor is inputted with the cascade signals of the preceding stage, and an input end of the 5th switching transistor is connected with the constant low voltage source, wherein a control end of the 6th switching transistor is inputted with the cascade signals of the succeeding stage, an input end of the 6th switching transistor is connected with the constant low voltage source, and an output end of the 6th switching transistor is connected with the output end of the 5th switching transistor.