Patent ID: 9613704
Date: 2017-04-04
CPC Classifications: G11C

Claim:
1. A HiNAND2 memory chip with two-level bit line (BL) hierarchy array structure for random concurrent and pipeline NAND operations, the HiNAND2 memory chip comprising: a plane of NAND cells formed on a common Triple-Pwell (TPW) region over a deep-Nwell region on a P-substrate, the plane comprising a first plurality of Groups arranged in column direction, each Group being associated with a first number of global bit lines (GBLs) arranged in the column direction as top-level metal lines and being separated from adjacent Groups by a row of Group-divided devices, each Group comprising a second plurality of Segments arranged in the column direction, each Segment being associated with a second number of local bit lines (LBLs) disposed as lower-level metal lines in parallel to the GBLs and being separated from adjacent Segments by a row of Segment-divided devices, each GBL being coupled to one or more LBLs respectively by one or more Segment-select transistors gated respectively with one or more segment-control SEG signals, the second number of LBLs being coupled to a common power line respectively through a row of Precharge/Discharge (P/D) transistors commonly gated by corresponding one of precharge-control PRE signals, each Segment comprising a third plurality of Blocks wherein each Block comprises the second number of Strings one-to-one parallelly coupled to the second number of LBLs and each String comprising M cells connected in series and capped by a top String-select transistor and a bottom String-select transistor, the top String-select transistor connecting its drain to one corresponding LBL, the bottom String-select transistor connecting its source to a common source line disposed in parallel to but not connected to the common power line, the second number of Strings in a Block forming M pages of cells respectively gated by M word lines (WLs) and all corresponding top String-select transistors are gated by a SSL line and all corresponding bottom String-select transistors are gated by a GSL line; a data buffer configured to store the first number of bits of partial page SLC or MLC data received from external I/Os which are transferred and stored in selected second number of LBLs precharged locally with an inhibit voltage Vinh from the corresponding common power line in one more sequential cycles through the first number of GBLs; a Segment-decoder configured with a latch to control one or more SEG signals for controlling connection between each GBL and one or more corresponding LBLs; a Block-decoder configured with a latch to connect or disconnect a set of M+2 bus lines shared to m sets of M WLs, 1 SSL line, and 1 GSL line on one-set-per-Block basis, m being an integer equal to 1 or greater; wherein m pages of cells being selected on one-page-per-Block basis from m Blocks selected on one-Block-per Segment basis from the second plurality of Segments of one or more of the first plurality of Groups in the plane are configured to perform m-page all-BL concurrent operations of Erase, Program, Verify, or Read of mixed SLC and MLC data by executing LBL-precharge/discharge, WL-precharge/discharge in concurrent and pipeline manner with self-timed controls of transferring and latching an inhibit voltage Vinh precharged through the common power line per Segment to the LBLs and m sets of M WL voltages, 1 SSL voltage, and 1 GSL voltage through the set of M+2.