Patent ID: 9716138
Date: 2017-07-25
CPC Classifications: H01L

Claim:
1. A method comprising: obtaining a wafer comprising a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; forming at least one opening having sidewalls and a bottom surface within the filled at least one recess; depositing a high k dielectric layer over the wafer; depositing a work function material (WFM) layer over the wafer; depositing an organic planarization layer (OPL) to partially fill the at least one opening; removing at least a portion of the WFM layer; and depositing an oxide layer over the wafer and filling the at least one opening.