Patent ID: 9601531
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A wafer level packaging structure for image sensors, comprising: a wafer to be packaged comprising a plurality of chip regions and scribe line regions between the chip regions, image sensing regions located on a first surface of the wafer and located in the chip regions, pads located on the first surface of the wafer and crossing over the scribe line regions; first dike structures covering surfaces of the pads and the scribe line regions, a packaging cover arranged facing the first surface of the wafer, and second dike structures located on a surface of the packaging cover; wherein the pads are spaced at peripheries of the chip regions, each first dike structure covers surface of one or more of the pads, and the first dike structures covering the surfaces of the pads are spaced from each other; wherein the second dike structures are arranged corresponding to the scribe line regions, and the packaging cover and the wafer are joined fixedly via the second dike structures and the first dike structures, wherein both the second dike structure and the packaging cover are made of silicon and the second dike structures are integrated with the packaging cover; wherein a width of the second dike structures is smaller than a width of the scribe line regions, and wherein the width of the second dike structures is equal to or smaller than a width of incisions generated in singulating the wafer.