Patent ID: 9728275
Date: 2017-08-08
CPC Classifications: G06F,G11C

Claim:
1. A memory system, comprising: a plurality of pins for connection to the outside of the memory system, the pins including a first pin configured to receive a chip select signal, a second pin configured to receive a clock signal, and a third pin configured to receive a command signal in synchronization with the clock signal; a memory cell array including a plurality of first memory blocks and a second memory block in which status data indicating whether or not each of the first memory blocks is defective is stored; and a control circuit configured to determine whether or not a first memory block targeted by the command signal is indicated as being defective in the status data, and allow an operation to be performed on the targeted first memory block in accordance with the command signal when the targeted first memory block is not indicated as being defective in the status data and block the operation to be performed on the targeted first memory block when the targeted first memory block is indicated as being defective in the status data.