Patent ID: 9589625
Date: 2017-03-07
CPC Classifications: G11C

Claim:
1. A method of operating a memory device including word lines and bit lines connected to a plurality of memory cells, the method comprising: enabling a first word line of the word lines, the first word line corresponding to a first address corresponding to a selected memory cell of the plurality of memory cells, after receiving an active command; providing a first power supply voltage having a first voltage level to a sense amplifier connected to a first bit line of the bit lines, the first bit line corresponding to the selected memory cell based on a first control signal during a first time interval, the first time interval being between a first time at which a voltage is provided to the first bit line based on the first power supply voltage, and a second time at which a pre-charge command is received; providing a second power supply voltage having a second voltage level greater than the first voltage level to the sense amplifier based on a second control signal during a second time interval, during which the word line is enabled after the pre-charge command is received, the second power supply voltage being irrespective of and greater than the first power supply voltage; and restoring the selected memory cell corresponding to the first address based on the first power supply voltage and the second power supply voltage, wherein the first power supply voltage is provided by regulating a first external voltage having a third voltage level, using a first regulator, wherein the second power supply voltage is provided by regulating a second external voltage having a fourth voltage level, using a second regulator, and wherein the third voltage level is less than the fourth voltage level, and the fourth voltage level is less than the second voltage level.