Patent ID: 9612282
Date: 2017-04-04
CPC Classifications: G01R

Claim:
1. Addressable test access port circuitry comprising: (a) test access port circuitry having a TDI input lead, a TMS input lead, a TCK input lead, and a TDO output lead; (b) test access port control circuitry including state machine circuitry, the control circuitry having a TCK input coupled with the TCK input lead, a TMS input coupled with the TMS input lead, and state outputs indicating Run Test/Idle, Pause-DR and Pause-IR TAP states; (c) addressing circuitry having a TDI input coupled to the TDI input lead, a TMS input coupled to the TMS input lead, a TCK input coupled to the TCK input lead, and state inputs coupled to the state outputs, the addressing circuitry including: (d) gating circuitry having one input connected to the TMS input lead, another input connected to the enable output, and an output connected to the TMS input of the test access port control circuitry.