Patent ID: 9602085
Date: 2017-03-21
CPC Classifications: G06F,H03K,H04L

Claim:
1. A data storage element, comprising: a master stage with a first latch configured to provide a first logical signal based on an input signal in relation to a first threshold level, the first logical signal generated based on a clock signal, and with a second latch configured to provide a second logical signal based on the input signal in relation to a second threshold level, the second logical signal generated based on the clock signal, the second threshold level distinct from the first threshold level; an error stage configured to provide an error signal with a first logical state if the first and the second logical signal have the same logical state, and with a second logical state if the first and the second logical signal have different logical states; and a slave stage comprising: a first input line to receive the first logical signal, a second input line to receive the second logical signal, a third input line to receive the error signal, and an output line to output an output signal, the output signal comprising an output value of the data storage element, the output value configured to be a common logical state of the first and the second logical signal when the error signal has the first logical state, and to keep the output value unchanged otherwise.