Patent ID: 9659778
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method of manufacturing a CMOS device, the method comprising: forming a gate material stack over a substrate comprising a first region, a second region, and a third region, the gate material stack including a semiconductive gate material; patterning the gate material stack in the first region and the second region; modifying the semiconductive gate material of the gate material stack in the first region or the second region of the substrate by introducing a substance comprising N, C, In, Fl, or Cl, to the semiconductive gate material using a first process; modifying the semiconductive gate material of the gate material stack in the third region of the substrate by introducing a substance comprising N, C, In, Fl, or Cl, to the semiconductive gate material using a second process different from the first process; and forming a first transistor in the first region of the substrate, a second transistor in the second region of the substrate, and a third transistor in the third region of the substrate, wherein the first, the second, and the third transistors are all NMOS transistors or all PMOS transistors, wherein the first transistor has a first threshold voltage, the second transistor has a second threshold voltage, the third transistor has a third threshold voltage, wherein the first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other.