Patent ID: 9601424
Date: 2017-03-21
CPC Classifications: G01R,H01L

Claim:
1. A method of forming and testing an interposer, comprising: forming vias in a semiconductor material of a wafer having a front side and a back side; disposing an electrically conductive layer on the front side of the wafer such that the electrically conductive layer is electrically connected to the vias; forming electrically conductive pads on the front side of the wafer wherein each electrically conductive pad is electrically connected to the electrically conductive layer and wherein the electrically conductive layer is sandwiched between at least one of the conductive pads and at least one of the vias; forming electrically conductive bumps on the back side of the wafer wherein each electrically conductive bump is electrically connected to at least one via; and testing electrical connectivity from a first bump of the electrically conductive bumps to a second bump of the electrically conductive bumps after said disposing of the electrically conductive layer.