Patent ID: 9740625
Date: 2017-08-22
CPC Classifications: G06F

Claim:
1. A method of facilitating translation of memory addresses, said method comprising: establishing, by a monitor executing on a processor, a partition having a first portion and a second portion, the partition managed by the monitor; selecting, by the monitor, a first address translation structure format for the first portion of the partition, the first address translation structure format being for handling first address translation requests of at least one first processing resource of one or more processing resources of the partition; and selecting, by the monitor, a second address translation structure format for the second portion of that partition, the second address translation structure format being for handling second address translation requests of at least one second processing resource of the one or more processing resources of the partition, the first address translation structure format being a different structural format from the second address translation structure format, wherein the first translation structure format and the second translation structure format are for handling the first address translation requests and second address translation requests, respectively, by concurrently operating first and second translation processes operating on behalf of the first portion of the partition and second portion of the partition respectively.