Patent ID: 9607124
Date: 2017-03-28
CPC Classifications: G06F

Claim:
1. A method for performing a hierarchical timing analysis and closure of a component of an integrated circuit (IC) chip using load-sensitive feedback constraints, the method comprising: obtaining at least one original feedback constraint, a base load representation, and a sensitivity of the at least one original feedback constraint to the base load representation for one or more boundary pins of the component; performing timing analysis and closure of the component, wherein the timing closure involves at least one of gate re-sizing, wire re-routing, and wire buffering, and updating an electrical parasitic of the one or more boundary pins; obtaining an updated value of the load representation of the one or more boundary pins that accounts for the electrical parasitic updates; computing an updated feedback constraint of the one or more boundary pins based on the at least one original feedback constraint, the base load representation, the sensitivity of the at least one original feedback constraint to the base load representation for the one or more boundary pins of the component, and the updated value of the load representation; and employing the computed updated feedback assertion to perform a new timing analysis of the component as part of timing closure of a design of the chip prior to manufacturing the integrated circuit chip.