Patent ID: 9557998
Date: 2017-01-31
CPC Classifications: G06F,H04N

Claim:
1. A method comprising: decoding a single instruction into a decoded single instruction with a decoder of a processor core; and executing, in an execution unit of the processor core, the decoded single instruction that includes a source operand and a destination operand each having a same plurality of packed data elements to calculate for each packed data element position of the source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.