Patent ID: 9627535
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A device, comprising: a gate structure positioned above an active region of a semiconductor substrate, wherein said gate structure has an axial length in a gate width direction of said device and comprises a first gate structure portion positioned above said active region and second gate structure portions positioned above an isolation region formed in said semiconductor substrate; an etch stop layer positioned on said gate structure, wherein said etch stop layer covers sidewall surfaces of said second gate structure portions but does not cover any sidewall surfaces of said first gate structure portion; first and second contact trenches that extend continuously along said first gate structure portion for less than said axial length of said gate structure, wherein said first and second contact trenches are positioned above at least a portion of said active region on respective opposing first and second sides of said gate structure; and an epi semiconductor material positioned on said active region within each of said first and second contact trenches.