Patent ID: 9741726
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. A memory device, comprising: a first capacitor having a first electrode and a second electrode, the first electrode of the first capacitor serving as a first control gate of the memory device, wherein the first capacitor is formed over a first well region in a first portion of a semiconductor material; a tunneling-enhanced capacitor having a first electrode and a second electrode, the first electrode of the tunneling-enhanced capacitor serving as an erase gate of the memory device, and the second electrode of the tunneling-enhanced capacitor coupled to the second electrode of the first capacitor to form a first floating gate, wherein the tunneling-enhanced capacitor is formed over a second well region in a second portion of the semiconductor material; and a transistor having a control electrode, a first current carrying electrode, and a second current carrying electrode, the control electrode of the transistor directly coupled to the first floating gate, wherein the transistor is formed over a third portion of the semiconductor from which a well region is absent.