Patent ID: 9627224
Date: 2017-04-18
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a multi-layer interconnect board comprising in stacked relation a lower conductive layer, at least one dielectric layer, and an upper conductive layer; said at least one dielectric layer having a recess formed therein with a bottom and sloping sidewall extending upwardly from the bottom, the sloping sidewall having an oblique angle with respect to the bottom of the recess; said at least one dielectric layer comprising upper and lower dielectric layers bonded together, said upper dielectric layer being ring-shaped with an opening therein also defining the recess; said upper conductive layer comprising a plurality of upper conductive traces extending across the sloping sidewall; said lower conductive layer comprising a plurality of lower conductive traces; a plurality of vias extending between said lower and upper conductive layers; at least one integrated circuit (IC) carried by said multi-layer interconnect board in the recess; a plurality of bond wires coupling upper conductive traces to said at least one IC; and encapsulation material adjacent said at least one IC and adjacent portions of said multi-layer interconnect board.