Patent ID: 9628084
Date: 2017-04-18
CPC Classifications: H03K

Claim:
1. A reconfigurable logic device, comprising: a plurality of logic units, wherein the reconfigurable logic device is configured to allow a plurality of logic circuits to be formed in accordance with configuration data, wherein each of the plurality of logic units includes: a configuration memory configured to store first configuration data and second configuration data, a data input line, a data output line, a first address input line through which a clock is inputted as a first address for the configuration memory, a second address input line through which an input of the data input line is inputted as a second address for the configuration memory, a register unit configured to, in accordance with the clock, read the second configuration data specified by the first address from the configuration memory and retain the second configuration data, and output the first configuration data retained in a previous state, and a reconfigurable logic multiplexer configured to, in accordance with the first configuration data or the second configuration data outputted from the register unit, selectively combine a data input from the data input line and a data output to the data output line, and/or output, to the data output line, data produced by a logical operation related to a data input from the data input line, and wherein adjacent logic units are connected by the data input line and the data output line.