Patent ID: 9647665
Date: 2017-05-09
CPC Classifications: H03K

Claim:
1. A semiconductor device comprising: a first buffer circuit; a level shifter circuit electrically connected to the first buffer circuit; a second buffer circuit electrically connected to the level shifter circuit; and a first wiring, a second wiring, and a third wiring, wherein each of the level shifter circuit and the second buffer circuit is electrically connected to the second wiring and the third wiring, wherein potential that is supplied to the first wiring is switched from a third potential to a first potential, wherein potential that is supplied to the second wiring is switched from the third potential to a second potential, wherein switching the third potential that is supplied to the second wiring from the third potential to the second potential at a first timing follows switching the third potential that is supplied to the first wiring from the third potential to the first potential at a second timing, wherein the second potential is higher than the first potential, and wherein the third potential is lower than the first potential and the second potential.