Patent ID: 9564319
Date: 2017-02-07
CPC Classifications: H01L

Claim:
1. A method of fabricating a transient semiconductor based on a single-wall nanotube, the method comprising: (a) stacking a thermal oxide layer on a silicon substrate and depositing a nickel thin layer on the thermal oxide layer; (b) depositing an oxide layer on the nickel thin layer through a plasma enhanced chemical vapor deposition scheme; (c) depositing a metallic layer on the oxide layer through an electron-beam deposition scheme, and patterning the metallic layer through a photolithography scheme to form a gate electrode; (d) depositing a gate insulating layer on the gate electrode through the plasma enhanced chemical vapor deposition scheme; (e) changing a surface of the gate insulating layer into a hydrophilic surface through plasma treatment or ultraviolet ozone treatment, and washing and drying the gate insulting layer; (f) coating a single-wall nanotube on the hydrophilic surface of the gate insulating layer; (g) forming source and drain electrodes by forming a contact opening through a reactive ion etching scheme for the gate insulating layer; (h) attaching a thermal release tape after removing a surrounding single-wall nanotube through the reactive ion etching scheme; (i) performing a transfer onto a polyvinyl alcohol thin layer after etching the nickel thin layer using an iron chloride solution; and (j) releasing the thermal release tape on a thermal plate.