Patent ID: 9564454
Date: 2017-02-07
CPC Classifications: G09G,H01L

Claim:
1. A TFT array substrate having compensated gate signal delays, the TFT array substrate comprising: a plurality of gate lines, each of which having a first end and a second end and coupled to N thin film transistor (TFT) switches, wherein the plurality of gate lines comprise a plurality of first gate lines and a plurality of second gate lines; N+1 data lines intersecting with the plurality of gate lines; a plurality of first driving units located at peripheries of the first ends of the plurality of gate lines; a plurality of second driving units located at peripheries of the second ends of the plurality of gate lines; a plurality of first compensation units located at peripheries of the first ends of the plurality of gate lines and coupled to the first of the N+1 data lines; a plurality of second compensation units located at peripheries of the second ends of the plurality of gate lines and coupled to the (N+1)th of the N+1 data lines; wherein the first end of each of the plurality of first gate lines is connected to an associated one of the plurality of first driving units, the second end of each of the plurality of first gate lines is connected to an associated one of the plurality of second compensation units, the first end of each of the plurality of second gate lines is connected to an associated one of the plurality of first compensation units, the second end of each of the plurality of second gate lines is connected to an associated one of the plurality of second driving units, and N TFT switches coupled to each of the plurality of first gate lines are connected to the N+1 data lines excluding the (N+1)th, and N TFT switches coupled to each of the plurality of second gate lines are connected to the N+1 data lines excluding the first.