Patent ID: 9715845
Date: 2017-07-25
CPC Classifications: G09G,G11C,H01L

Claim:
1. A semiconductor display device comprising: a pixel portion including a first area comprising a plurality of first pixels including a plurality of first transistors and a plurality of first display elements and a second area comprising a plurality of second pixels including a plurality of second transistors and a plurality of second display elements, the first area and the second area display in the same direction; and a scan line driver circuit comprising a decoder outputting a selection signal, wherein switching of each of the plurality of first transistors and the plurality of second transistors is controlled by the selection signal, wherein an operation of the plurality of first display elements is controlled in accordance with a video signal having an image data so that display of an image is performed in the first area and display of an image is not performed in the second area at the same time, wherein each of the plurality of first transistors and the plurality of second transistors includes an oxide semiconductor for a channel formation region, wherein the decoder comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first wiring, a second wiring and a third wiring, wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein the one of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor, wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the ninth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor, wherein the one of the source and the drain of the ninth transistor is electrically connected to one of a source and a drain of the eleventh transistor, wherein the one of the source and the drain of the ninth transistor is electrically connected to the first wiring, wherein a gate of the sixth transistor is electrically connected to the other of the source and the drain of the sixth transistor, wherein a gate of the seventh transistor is electrically connected to a gate of the tenth transistor, wherein a gate of the eighth transistor is electrically connected to a gate of the eleventh transistor, wherein a first potential is supplied to the other of the source and the drain of the sixth transistor and the other of the source and the drain of the ninth transistor through the second wiring, and wherein a second potential is supplied to the other of the source and the drain of the seventh transistor, the other of the source and the drain of the eighth transistor, the other of the source and the drain of the tenth transistor and the other of the source and the drain of the eleventh transistor through the third wiring.