Patent ID: 9640443
Date: 2017-05-02
CPC Classifications: H01L

Claim:
1. A method of fabricating a semiconductor device, the method comprising: forming a gate insulating layer on first through fourth areas of a substrate; providing a first concentration of nitrogen to portions of the gate insulating layer that are formed on the first and second areas of the substrate, and a second concentration of nitrogen to portions of the gate insulating layer that are formed on the third and fourth areas of the substrate, wherein the second concentration of nitrogen comprises a different concentration from the first concentration of nitrogen; forming a work function control material layer on the first through fourth areas of the substrate; forming a capping layer on the work function control material layer, wherein the capping layer is formed to a first thickness on the first and third areas of the substrate, and to a second thickness that is different from the first thickness, on the second and fourth areas of the substrate; and annealing the substrate.