Patent ID: 9666725
Date: 2017-05-30
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising: a first memory cell comprising a first transistor, a second transistor, and a capacitor; a second memory cell comprising a third transistor; a first wiring configured to be supplied with a data voltage; a second wiring; and a first switch, wherein the first wiring is electrically connected to one of a source and a drain of the first transistor, wherein the second wiring is electrically connected to the other of the source and the drain of the first transistor, one of a source and a drain of the second transistor, and one of a source and a drain of the third transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor and one electrode of the capacitor, and wherein the first switch is provided between the other of the source and the drain of the first transistor and the one of the source and the drain of the third transistor.