Patent ID: 9613979
Date: 2017-04-04
CPC Classifications: H01L

Claim:
1. A semiconductor memory device, comprising: a plurality of control gate electrodes and a plurality of inter-layer insulating layers stacked alternately above a substrate; a semiconductor layer having as its longitudinal direction a first direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes; a charge accumulation layer positioned between the semiconductor layer and the control gate electrode; and a plurality of first insulating layers separated in the first direction and positioned between the semiconductor layer and the plurality of inter-layer insulating layers, one of the plurality of first insulating layers being a second insulating layer, and another of the plurality of first insulating layers being a third insulating layer positioned above the second insulating layer, an external diameter of the second insulating layer being smaller than an external diameter of the third insulating layer, and a film thickness of the second insulating layer being thinner than a film thickness of the third insulating layer.