Patent ID: 9646884
Date: 2017-05-09
CPC Classifications: H01L

Claim:
1. A method, comprising: forming a plurality of fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess, wherein a residual amount of the NCOL covers side and bottom surfaces of each recess; depositing an optical planarization layer (OPL) and anti-reflective coating (ARC) over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove the residual amount of the NCOL present at the side and bottom surfaces of each recess of the portion of the recesses.