Patent ID: 9659961
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A method, comprising: forming a high-k dielectric material on a semiconductor material; forming a metal gate material on the high-k material; forming a semiconductor layer on the metal gate material; forming a stacked structure in an active region by patterning the semiconductor material, high-k dielectric material, metal gate material and semiconductor layer; forming a liner on a top and side surfaces of the stacked structure in the active region, and exposed surfaces of a buried oxide layer or bulk silicon; forming an insulator layer over the liner; planarizing the insulator layer to form insulator regions, separated by the stacked structure formed in the active region; recessing the insulator regions to form STI structures; forming a second semiconductor material over the STI structures and the semiconductor layer of the stacked structure in the active region; and performing well implantation processes through the second semiconductor material.