Patent ID: 9536822
Date: 2017-01-03
CPC Classifications: H01L

Claim:
1. An integrated circuit, comprising: a substrate; a component located on said substrate; a dielectric layer located on said substrate and above said component; a plurality of electrically active ferroelectric structures located over said dielectric layer; a hydrogen barrier located above said electrically active ferroelectric structures; an inter-level dielectric layer located on said hydrogen barrier; a plurality of electrically active vias located in said inter-level dielectric layer and said hydrogen barrier; and a plurality of hydrogen permeable dummy vias configured in one of a linear array or a rectangular array, said plurality of hydrogen permeable dummy vias symmetrically positioned over said component and located in said inter-level dielectric layer and said hydrogen barrier such that at least a portion of bottom surfaces of said plurality of hydrogen permeable dummy vias contact said dielectric layer.