Patent ID: 9627054
Date: 2017-04-18
CPC Classifications: G11C

Claim:
1. A memory operating method, comprising: applying a first read voltage to a memory cell having a plurality of resistance levels, wherein the memory cell is a multi-level-cell of a phase change memory; and applying a second read voltage to the memory cell when failing to read data of the memory cell under the first read voltage; wherein the second read voltage is set to larger than the first read voltage when a resistance of the memory cell under the first read voltage is larger than an upper resistance limit of a resistance sensing window; and the second read voltage is set to smaller than the first read voltage when the resistance value of the memory cell under the first read voltage is smaller than a lower resistance limit of the resistance sensing window; wherein the resistance sensing window has the upper resistance limit and the lower resistance limit between which data corresponding to a resistance level exhibited by the memory cell is configured to be read.