Patent ID: 9711593
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a first doped region and a second doped region both formed in a substrate, the first and second doped regions having opposite conductivity types and having a native region interposing the first and second doped regions; a first gate formed over the substrate, the first gate overlying a portion of the first doped region, a first portion of the second doped region, and the native region; a second and a third gate formed over the substrate and on a first surface of the substrate, the first surface defined by the second doped region, the second and third gates overlying a second portion of the second doped region different from the first portion of the second doped region and separate from the first portion of the second doped region, wherein the second and third gates are dummy gate structures, wherein the first surface extending from a first interface with the first gate structure to a second interface with the second gate structure consists of the second doped region; a third doped region in the second doped region, the third doped region includes a first edge portion, a second edge portion, and a middle portion interposing the first and second edge portions, wherein: the middle portion has a first dopant concentration and the first and second edge portions having a second dopant concentration, the first dopant concentration greater than the second dopant concentration; a first edge of the middle portion of the third doped region is aligned with an edge of a first spacer element abutting the second gate and a second edge of the middle portion of the third doped region is aligned with an edge of a second spacer element abutting the third gate, wherein the first edge portion underlies the first spacer element and the second edge portion underlies the second spacer element and the first edge portion has an edge aligned with an edge of the second gate stack and the second edge portion has an edge aligned with an edge of the third gate stack, wherein the first and second edge portions and the middle portion of the third doped region each having opposite conductivity types of the second doped region, wherein the third doped surface has a silicided surface extending from the first edge to the second edge of the middle portion; and wherein the third doped region directly interfaces the second doped region a source region in the first doped region; and a drain region in the second doped region, the drain region disposed on a first side of the two or more second gates opposite a second side of the two or more second gates proximate the first gate, wherein the drain region has a first edge self-aligned with a first sidewall spacer of one of the two more second gates and a second opposing edge interfacing an isolation feature disposed in the substrate.