Patent ID: 9618581
Date: 2017-04-11
CPC Classifications: G01R

Claim:
1. A test architecture within an integrated circuit comprising: A. core wrappers, each core wrapper having a serial data input, a serial data output, and control inputs, the control inputs including a clock input, a shift input, a capture input, an update input, a reset input, an enable input, and a core select input; B. input circuitry having a serial test data input, serial data outputs selectively coupled to the serial test data input, and control inputs, each serial data output being connected to the serial data input of a core wrapper; C. output circuitry having serial data inputs, a serial test data output, and a control input, each serial data input being connected to the serial data output of a core wrapper and each serial data input being selectively coupled to the serial test data output; and D. a link instruction register including: