Patent ID: 9735251
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate having a surface; forming a metal gate structure on the surface of the substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the surface of the substrate; forming a cap layer on a top surface of the metal gate structure; etching a top portion of the first dielectric layer with a predetermined thickness using the cap layer as an etching mask; forming a protective sidewall spacer having a sidewall with a first portion covering a side surface in the thickness direction of the cap layer and a second portion covering a side surface of a portion of the first dielectric layer that is under the cap layer, the protective sidewall spacer having a bottom on a top surface portion of the first dielectric layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least one first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.