Patent ID: 9747204
Date: 2017-08-29
CPC Classifications: G06F

Claim:
1. A system, comprising: memory including a load-monitored region register (LMRR) and a sampled data address register (SDAR); and a hardware processor configured to exchange data with the memory, the hardware processor configured to perform a garbage collection process that reclaims unused objects of the memory and a performance monitoring process performed independent of the garbage collection process, the performance monitoring process providing information indicating a utilization of an instruction execution performed by the hardware processor, wherein the SDAR is configured to store first data generated according to the garbage process and second data generated according to the performance monitoring process, and wherein the first data in the SDAR is accessed during the garbage collection process when a SDAR control bit is set to a first bit, the second data in the SDAR is accessed during the performance monitoring process when the SDAR control bit is set to a second bit different from the first bit.