Patent ID: 9659618
Date: 2017-05-23
CPC Classifications: G06F,G11C,H03K

Claim:
1. A memory interface for connecting a memory controller to a volatile memory, comprising: a sampling circuit configured to couple to the memory controller; and a clock generation circuit coupled to the sampling circuit, the memory controller and the volatile memory, wherein the clock generation circuit is configured to receive a first data strobe signal and a second data strobe signal from the volatile memory, wherein the first data strobe signal and the second data strobe signal are differential signals corresponding to each other, wherein the clock generation circuit is further configured to generate a clock signal in response to the first data strobe signal and the second data strobe signal if a relative relation between a first voltage value of the first data strobe signal and a reference voltage value of a reference voltage signal conforms to a default condition, wherein the sampling circuit is configured to sample a data signal from the volatile memory based on a raising edge and a falling edge of the clock signal.