Patent ID: 9547027
Date: 2017-01-17
CPC Classifications: G01R,G06F,Y02D

Claim:
1. A processor comprising: a plurality of cores to independently execute instructions; a first sensor to measure a first power consumption level of the processor based at least in part on a plurality of events that occur on the plurality of cores; and a first logic to combine the first power consumption level and a second power consumption level of the processor determined based on a value of a dynamic current provided to the processor, wherein the first logic is to execute a low power load on the processor and calculate the first and second power consumption levels using sensor information from the first sensor and the dynamic current, respectively, determine and store an offset based on the first and second power consumption levels, execute a high power load on the processor and calculate the second power consumption level using the dynamic current, determine and store a slope based on the offset and the calculated second power consumption level, and determine the combined power consumption level using another second power consumption level, the slope and the offset.