Patent ID: 9583167
Date: 2017-02-28
CPC Classifications: G11C,H01L

Claim:
1. A memory cell comprising: a first magnetic tunnel junction (MTJ) element coupled to a first bit line; a second MTJ element coupled to a second bit line, wherein the first and second MTJ elements have a common node; a first selector having a first selector first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, wherein the common node of the first and second MTJ elements is coupled to the first S/D region of the first selector first select transistor; and a second selector having a second selector first select transistor with a second gate coupled to a second wordline and first and second S/D regions, and a second selector second select transistor with a third gate coupled to the second wordline and first and second S/D regions, wherein the first S/D regions of the second selector first select transistor and second selector second select transistor are a common first S/D region coupled to the second bitline.