Patent ID: 9711602
Date: 2017-07-18
CPC Classifications: H01L

Claim:
1. An array substrate, comprising: a thin film transistor; a source/drain line trench; and a source/drain line; wherein the thin film transistor comprises: an active layer on a base substrate; an insulating layer over the active layer, the insulating layer comprising a source via and a drain via, each of which extends through the insulating layer; a source electrode within the source via in contact with the active layer; and a drain electrode within the drain via in contact with the active layer; wherein the source electrode and the drain electrode are completely within the insulating layer; the source/drain line trench extends from a first source electrode in one thin film transistor to a second source electrode in a neighboring thin film transistor, the source/drain line trench is completely within the insulating layer in an area corresponding to the source via; and the source/drain line is in the source/drain line trench.