Patent ID: 9543405
Date: 2017-01-10
CPC Classifications: H01L

Claim:
1. A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure, the method comprising: forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate; forming a body region between adjacent ones of the transistor gate structures; and forming an insulator layer along the semiconductor substrate; forming an opening in the insulator layer such that the insulator layer covers adjacent ones of the transistor gate structures and exposes a region of the substrate that is between the adjacent ones of the transistor gate structures; forming an end-of-range irradiation region between the adjacent ones of the transistor gate structures by irradiating the semiconductor substrate, the end-of-range irradiation region having a plurality of vacancies, wherein the insulator layer is used as a mask for irradiating the semiconductor substrate such that irradiated particles pass through the opening formed in the insulating layer but are prevented by the insulator layer from damaging gate insulators disposed on inner walls of the trenches, and wherein the opening in the insulator layer is formed such that sidewalls of the opening form an oblique angle with an upper surface of the substrate, and wherein forming the end-of-range irradiation region comprises passing the irradiated particles through the sidewalls of the region such that the end-of-range irradiation region forms a well-shaped region within the semiconductor substrate, wherein the well-shaped region comprises sidewalls that are parallel to the sidewalls of the opening and directly adjoin outer walls of the gate trenches.