Patent ID: 9583539
Date: 2017-02-28
CPC Classifications: H01L

Claim:
1. A three-dimensional monolithic memory device, comprising: at least one device region and a plurality of contact regions each comprising a stack of an alternating plurality of electrically conductive word line contact layers and electrically insulating layers located over a substrate, wherein the stacks in the plurality of contact regions are separated from one another by an insulating material; and a bridge connector comprising an electrically conductive material extending between a first electrically conductive word line contact layer of a first stack in a first contact region and a second electrically conductive word line contact layer of a second stack in a second contact region, wherein the first electrically conductive word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second electrically conductive word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level.