Patent ID: 9716510
Date: 2017-07-25
CPC Classifications: H03K,H03M

Claim:
1. A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter, said comparator circuit comprising: a comparator having first and second input terminals; an input voltage sampling switch connected between an input voltage and a first node; a sampling capacitor connected between said first node and a second node and arranged to store a voltage which varies with said input voltage when said sampling switch is closed; an isolation buffer having an input and an output, said buffer input coupled to said second node and said buffer output coupled to said comparator's first input terminal; circuitry arranged to apply a reset voltage to said second input terminal of said comparator such that the comparator operating point is independent of the input voltage, said circuitry comprising: a voltage ramp switch arranged to apply a global voltage ramp to said first node and thereby to said sampling capacitor when closed; said comparator circuit arranged such that the output of said comparator toggles when said global voltage ramp exceeds said input voltage, and such that said isolation buffer maintains a substantially constant capacitive load on the said global voltage ramp said comparator circuit arranged to: