Patent ID: 9559113
Date: 2017-01-31
CPC Classifications: H01L

Claim:
1. A memory device including an array of strings of memory cells, comprising: a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips; a plurality of vertical active strips between the plurality of stacks; charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and the vertical active strips in the plurality of vertical active strips; and gate dielectric, having a different composition than the charge storage structures, in interface regions at cross-points between and contacting the vertical active strips in the plurality of vertical active strips and side surfaces of the conductive strips in the top plane of conductive strips, wherein the insulating material separating conductive strips in the stacks of conductive strips contacts vertical active strips in the plurality of vertical active strips, and wherein conductive strips in at least one of the bottom plane and the top plane have different material than conductive strips in the plurality of intermediate planes.