Patent ID: 9660090
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. An array substrate having at least two thin film transistors, comprising: gate and data lines formed on the array substrate and defining a pixel region, wherein the thin film transistors are located in a device area of the pixel region; a light-shielding pattern arranged on the array substrate in the device area, wherein the thin film transistors overlap the light-shielding pattern, and wherein the light-shielding pattern absorbs or reflects light; an auxiliary line connected to the light-shielding pattern and supplying a constant voltage to the light-shielding pattern, wherein the auxiliary line is parallel to and spaced apart from one of the gate and data lines; a buffer layer of an inorganic material located on the light-shielding pattern and a surface of the array substrate; a semiconductor layer located on the buffer layer and the light-shielding pattern; an inter-insulating layer on the semiconductor layer, wherein the semiconductor layer includes an active portion located entirely on the light-shielding pattern and having a channel formed thereon, and conductive portions located on sides of the active portion, wherein the thin film transistors include a switching thin film transistor and a driving thin film transistor in the device area, and wherein the thin film transistors are separated from each other, wherein a drain electrode of the switching thin film transistor is connected to a gate electrode of the driving thin film transistor.