Patent ID: 9673202
Date: 2017-06-06
CPC Classifications: G06F,H01L

Claim:
1. An integrated circuit (IC) layout, comprising: at least four first patterns located at a first layer of the IC layout, wherein the first patterns are spaced from each other in a first direction; and each of the first patterns is an elongated shape extending lengthwise in a second direction that is orthogonal to the first direction; at least four second patterns located at a second layer of the IC layout, wherein each of the second patterns is an elongated shape extending lengthwise in the second direction, the second patterns are spaced from each other in the first direction, each of the second patterns covers a side of one of the first patterns when the first and second layers are superimposed, the side extending in the second direction; and third patterns located at a third layer of the IC layout, wherein the third patterns are spaced from each other, each of the third patterns covers a portion of another side of one of the first patterns that is not covered by the second patterns when the first, second, and third layers are superimposed, the another side extending in the second direction, wherein: the first, second, and third patterns are used for collectively defining active regions for forming transistors; and the active regions are defined along sides of the first patterns that extend in the second direction and are not covered by the second and third patterns when the first, second, and third layers are superimposed.