Patent ID: 9570563
Date: 2017-02-14
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a substrate layer; a first set of source/drain component(s) defining an nFET (n-type field-effect transistor) region in the substrate layer; a second set of source/drain component(s) defining a pFET (p-type field-effect transistor) region in the substrate layer; a first suspended nanowire, at least partially suspended over the substrate layer in the nFET region, made from III-V material, and electrically connected to act as a gate for the first set of source/drain component(s); and a second suspended nanowire, at least partially suspended over the substrate layer in the pFET region, made from Silicon-Germanium (SiGe), and electrically connected to act as a gate for the second set of source/drain component(s).