Patent ID: 9654025
Date: 2017-05-16
CPC Classifications: G06F,H02M,Y02B

Claim:
1. A method of designing a cascaded multi-level inverter for minimized large-scale voltage distortion, comprising: determining N as a number of inverter modules and DC voltage sources in a cascaded multi-level inverter based on a maximum inverter level of the cascaded multi-level inverter H, a step series S, and an inverter level j; applying N inverter modules and DC voltage sources in the cascaded multi-level inverter; connecting a positive electrode of a DC bus of each of the inverter modules with a positive electrode of a corresponding DC voltage source; connecting a negative electrode of the DC bus of each of the inverter modules with a negative electrode of the corresponding DC voltage source; connecting an input control terminal for a conduction angle of the inverter module with a corresponding output control terminal of a controller; connecting an AC output terminal of the inverter module with an AC voltage input terminal corresponding to the controller; and connecting the AC voltage input terminal of the controller with the AC output terminal of the corresponding inverter module, wherein N is determined by