Patent ID: 9685466
Date: 2017-06-20
CPC Classifications: H01L

Claim:
1. An array substrate, comprising a substrate, a TFT, a pixel electrode, a gate line and a data line, wherein: the TFT and the gate line are arranged on the substrate; a source electrode and a drain electrode of the TFT are arranged on different layers; a semiconductor layer of the TFT is in electrical connection to the source electrode and the drain electrode, respectively; the pixel electrode is in electrical connection to the drain electrode of the TFT; the source electrode of the TFT is in electrical connection to the data line; and wherein: the source electrode of the TFT is arranged above the semiconductor layer of the TFT and the data line is located at an identical layer to the source electrode of the TFT, the drain electrode of the TFT is arranged below the semiconductor layer of the TFT and the pixel electrode is arranged below the semiconductor layer of the TFT, a lower surface of the source electrode of the TFT covers a part of an upper surface of the semiconductor layer of the TFT, and a lower surface of the semiconductor layer of the TFT covers a part of an upper surface of the drain electrode of the TFT.