Patent ID: 9542124
Date: 2017-01-10
CPC Classifications: G05F,G06F,G11C,H02M

Claim:
1. An electronic device comprising a power supply circuit which comprises: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive a delayed output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the delayed output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level which is higher than the first level, wherein the delayed output voltage is generated by delaying the output voltage, and wherein the electronic device further comprises a semiconductor memory unit which comprises: a cell array comprising a plurality of storage cells configured to store data; and a control circuit configured to write data to the plurality of storage cells or read data from the plurality of memory cells, and the power supply circuit supplies power used in one or more of the cell array and the control circuit.