Patent ID: 9703704
Date: 2017-07-11
CPC Classifications: G06F,Y02D

Claim:
1. A semiconductor device comprising: a CPU comprising cache memory sets and an arithmetic circuit that monitors a frequency of access to the cache memory sets; and a power supply control circuit, wherein the cache memory sets comprise a line comprising a dirty bit, wherein the power supply control circuit stops a supply of a power supply voltage to the CPU in the case where the frequency of access to the cache memory sets is uniform and to resume the supply of the power supply voltage to the CPU, wherein the dirty bit of the line shows a match or a mismatch of data stored in the line and data stored in an address of a memory device, wherein the address corresponds to the line, and wherein the cache memory stores the data stored in the line into the address of the memory device when the dirty bit of the line shows the mismatch before the supply of the power supply voltage to the CPU is stopped.