Patent ID: 9716472
Date: 2017-07-25
CPC Classifications: H03F

Claim:
1. A voltage follower circuit to mitigate gain loss, said voltage follower circuit comprising: a voltage replica generation circuit that is selected from a group comprising (i) a NMOS based voltage follower circuit, (ii) a NPN BJT based voltage follower circuit, (iii) a n-channel JFET based voltage follower circuit, (iv) a PMOS based voltage follower circuit, (v) a P-Channel JFET based voltage follower circuit, or (vi) a PNP BJT based voltage follower circuit; wherein said NMOS based voltage follower circuit comprises (a) a NMOS transistor, which comprises a gate terminal, a drain terminal, and a source terminal, wherein said gate terminal is connected to an input voltage Vin, said source terminal is connected to a bias current source; and (b) a NMOS voltage replica generator, wherein said NMOS voltage replica generator comprises one or more NMOS transistors wherein said NMOS voltage replica generator is connected to said drain terminal of said NMOS transistor and a fixed voltage, wherein said NMOS voltage replica generator creates a close replica of said input voltage Vin at said drain terminal of said NMOS transistor; wherein said NPN BJT based voltage follower circuit, comprises (a) a NPN BJT transistor that comprises a base terminal, a collector terminal, and an emitter terminal, wherein said base terminal is connected to said input voltage Vin, said emitter terminal is connected to said bias current source; and (b) a NPN BJT voltage replica generator, that comprises one or more NPN BJT transistors, wherein said NPN BJT voltage replica generator is connected to said collector terminal and said fixed voltage; wherein said n-channel JFET based voltage follower circuit comprises; (a) a n-channel JFET transistor that comprises a gate terminal, a drain terminal, and a source terminal, wherein said gate terminal is connected to said input voltage Vin; and (b) a n-channel JFET voltage replica generator, which comprises one or more n-channel JFET transistors, wherein said n-channel JFET voltage replica generator is connected to said n-channel JFET drain terminal and said fixed voltage; wherein said PMOS based voltage follower circuit comprises (a) a PMOS transistor that comprises a gate terminal, a source terminal, and a drain terminal, wherein said gate terminal is connected to said input voltage Vin; and (b) a PMOS voltage replica generator, which comprises one or more PMOS transistors, wherein said PMOS voltage replica generator is connected to said PMOS drain terminal and a fixed voltage; wherein said P-Channel JFET based voltage follower circuit comprises (a) a P-Channel JFET transistor that comprises a gate terminal, a source terminal, and a drain terminal, wherein said gate terminal is connected to said input voltage Vin; and (b) a P-Channel JFET voltage replica generator that comprises one or more P-Channel JFET transistors, wherein said P-Channel JFET voltage replica generator is connected to said drain terminal of said P-Channel transistor and said fixed voltage; wherein said PNP BJT based voltage follower circuit comprises (a) a PNP BJT transistor that comprises a base terminal, a emitter terminal, and a collector terminal, wherein said base terminal is connected to said input voltage Vin; and (b) a PNP BJT voltage replica generator that comprises one or more PNP BJT transistors, wherein said PNP BJT voltage replica generator is connected to said collector terminal of said PNP BJT transistor and said fixed voltage.