Patent ID: 9721050
Date: 2017-08-01
CPC Classifications: G06F,G11C,H01L

Claim:
1. A design structure tangibly embodied in a non-transitory machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: One or more Static Random-Access Memory (SRAM) cell groups, wherein each of the one or more SRAM cell groups includes two or more SRAM cells that are connected to an input of a local read amplifier by at least one common local bit-line, and wherein outputs of the local read amplifiers are connected to a shared global bit-line, the shared global bit-line being connected to a pre-charge circuit that is adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data, the pre-charge circuit including a limiter circuit comprising: wherein the pre-charge regulator circuit comprises: a 1st p-FET connected with its source to a power supply voltage and its drain to a first terminal of a pre-charge switch which is connected with its second terminal to the shared global bit-line; and a 1st n-FET which is connected with its source to the first terminal of the pre-charge switch, wherein a drain of the 1st n-FET is connected to a gate of the 1st p-FET as well as to a first terminal of a first programmable resistor which is connected with its second terminal to the power supply voltage, wherein a gate of the 1st n-FET is connected to a reference voltage (Vref) signal.