Patent ID: 9684751
Date: 2017-06-20
CPC Classifications: G06F

Claim:
1. A method of implementing an integrated circuit design, the method comprising: obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries; identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack; selecting redistribution cycle boundaries among the candidate cycle boundaries; generating, using a processor, a modified timing database based on redistributing the positive timing slack associated with the redistribution cycle boundaries; and performing, using the processor, power recovery using the modified timing database to reduce power at one of more of the redistribution cycle boundaries; and generating a physical implementation of the integrated circuit design resulting from the power recovery using the modified timing database.