Patent ID: 9673229
Date: 2017-06-06
CPC Classifications: G02F,H01L

Claim:
1. An array substrate, comprising: a substrate; a common electrode and a pixel electrode sequentially formed on the substrate and insulated from each other; a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode, wherein the drain electrode is electrically connected with the pixel electrode; and a common electrode line disposed in a same layer as the gate electrode; wherein the array substrate further comprises an insulating layer between the gate electrode and the common electrode to isolate the gate electrode from the common electrode, and the common electrode is connected with the common electrode line through a first through hole, and wherein the common electrode line and the gate electrode are provided on the substrate, the insulating layer is provided on the substrate and covers the common electrode line and the gate electrode, the common electrode is provided on the insulating layer, a portion of the insulating layer covering the common electrode line has the first through hole.