Patent ID: 9559705
Date: 2017-01-31
CPC Classifications: H03L,H04L

Claim:
1. A clock and data recovery circuit, comprising: a phase detection circuit, configured to receive an input signal and a clock signal, and to detect a phase difference between the input signal and the clock signal to output a first voltage signal; a first comparing circuit, coupled to the phase detection circuit, and configured to determine whether the first voltage signal is within a voltage range to output a first up signal and a first down signal; a counting circuit, configured to receive the input signal and the clock signal, take one of the input signal and the clock signal as a reset signal, take another one of the input signal and the clock signal as a trigger signal, and update a counting value according to the reset signal and the trigger signal; a second comparing circuit, coupled to the counting circuit, and configured to determine whether the counting value is within a value range to output a second up signal and a second down signal; a selection circuit, coupled to the first comparing circuit and the second comparing circuit, and configured to output a second voltage signal according to the first up signal, the first down signal, the second up signal and the second down signal; and a voltage controlled oscillator, coupled to the phase detection circuit and the selection circuit, and configured to output the clock signal according to the first voltage signal and the second voltage signal.