Patent ID: 9713266
Date: 2017-07-18
CPC Classifications: C23C,C25D,H05K

Claim:
1. A method for manufacture of fine line circuitry comprising, in the following order, the steps of (i) providing a dielectric build-up layer having a front side surface area and a back side surface area and wherein at least a portion of the back side surface area comprises at least one copper area and wherein a dielectric layer is attached to said back side surface area and wherein an adhesion promoting layer consisting of organosilane compounds is attached to the front side surface area of the build-up layer, wherein the adhesion promoting layer is formed by (a) treating said front side surface area with a solution comprising at least one organosilane compound to form the adhesion promoting layer consisting of the organosilane compounds, and (b) treating said adhesion promoting layer consisting of the organosilane compounds with a solution comprising an oxidizing agent, (ii) depositing a first conductive layer onto the adhesion promoting layer, (iii) forming at least one opening which extends through the first conductive layer, the adhesion promoting layer and the build-up layer to the at least one copper area, (iv) cleaning the dielectric side walls and the copper area of the at least one opening to obtain cleaned side walls and a cleaned copper area, (v) forming a second conductive layer only on the cleaned side walls wherein the second conductive layer is selected from the group consisting of electrically conductive polymers, colloidal particles comprising a noble metal, and electrically conductive carbon particles, (vi) applying a resist layer onto the first conductive layer; and patterning said resist layer, (vii) depositing a copper layer by electroplating into the at least one opening of the patterned resist layer, (viii) removing the patterned resist layer and (ix) removing those portions of the first conductive layer which are not covered by the electroplated copper layer.