Patent ID: 9685471
Date: 2017-06-20
CPC Classifications: G02F,G09F,H01L

Claim:
1. A manufacture method of a thin film transistor substrate, comprising steps of: step 1, providing a substrate; step 2, deposing a first metal layer on the substrate and patterning the first metal layer to form a gate of a switching transistor and a gate of a driving transistor; step 3, deposing a gate isolation layer on the gates of the switching transistor and the driving transistor and the substrate; step 4, deposing an oxide semiconducting layer on the gate isolation layer and patterning the oxide semiconducting layer to form an oxide semiconducting block associated with the switching transistor and an oxide semiconducting block associated with the driving transistor and spaced from the oxide semiconducting block associated with the switching transistor; step 5, deposing an etching stopper layer on the gate isolation layer and the oxide semiconducting layer; step 6, implementing one photolithographic process that involves application of a photoresist layer that is treated for subsequently conducting a via deposing process to the gate isolation layer and patterning the etching stopper layer, wherein a via is formed in the via disposing process to extend through the etching stopper layer and the gate insolation layer and reach and expose the gate of the driving transistor and portions of the oxide semiconducting block of the switching transistor and portions of the oxide semiconducting block of the driving transistor are exposed such that one of the exposed portions of the oxide semiconducting block of the switching transistor and the exposed gate of the driving transistor are in communication with each other with a void space formed therebetween; step 7, forming a source/a drain associated with the switching transistor and a source/a drain associated with the driving transistor on the etching stopper layer, wherein the source/the drain of the switching transistor is in connection with the gate of the driving transistor through the via and the void space so as to form electrical connection between the source/the drain of the switching transistor and the gate of the driving transistor; step 8, sequentially forming a protective layer and a flat layer on the etching stopper layer and the source/the drain; step 9, forming a transparent conducting layer on the flat layer and exposed portions of the sources/the drains and patterning the transparent conducting layer; and step 10, sequentially forming a pixel defining layer and a photospacer on the flat layer and the transparent conducting layer; wherein in step 6, the one photolithographic process is conducted solely to expose both the exposed gate of the driving transistor and the one of the exposed portions of the oxide semiconductor block of the switching transistor such that the source/the drain of the switching transistor that is formed in step 7, which is subsequent step 6, is allowed to simultaneously contact both the exposed gate of the driving transistor and the one of the exposed portions of the oxide semiconductor block of the switching transistor.