Patent ID: 9691841
Date: 2017-06-27
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a lower wire formed on a substrate in a first direction; impurity injection regions formed inside the substrate adjacent to edges of the lower wire; a first insulating layer formed on the substrate to cover the lower wire; first electrodes passing through the first insulating layer to be connected to the lower wire, wherein each of the first electrodes consists of one segment; a second insulating layer formed on the first insulating layer to cover the first electrodes; second electrodes passing through the second insulating layer and a part of the first insulating layer to have lower surfaces positioned higher than lower surfaces of the first electrodes, wherein each of the second electrodes consists of one segment; first contact plugs passing through the first insulating layer to be connected to the impurity injection regions, and arranged in the first direction; second contact plugs passing through the second insulating layer to be connected to the first contact plugs; third contact plugs passing through the second insulating layer to be connected to the first electrodes; first signal wires extended in a second direction to be connected onto the third contact plugs; and second signal wires extended in the first direction to be connected to the second contact plugs, or extended in the second direction to be connected to the second electrodes, wherein the first and second electrodes form capacitors.