Patent ID: 9697123
Date: 2017-07-04
CPC Classifications: G06F

Claim:
1. An information processing device comprising a plurality of nodes, each nodes comprising: a main memory which stores data; and an arithmetic operation device configured to read a target data of which the arithmetic operation device executes an arithmetic operation from a storage device except the main memory and write the target data into the main memory of own node, and execute the arithmetic operation of the target data in the main memory, wherein the read the target data is based on a first address information indicating a storage position in the storage device, wherein the arithmetic operation device in one node in the plurality of nodes creates an I/O (Input/Output) processing thread that transfers the target data that the arithmetic operation device of each of the plurality of nodes shares the arithmetic operation in a parallel arithmetic processing, from the storage device to the main memory of the each of the plurality of nodes, to the arithmetic operation device in each of the plurality of nodes in response to an instruction of the parallel arithmetic processing, and wherein the arithmetic operation device in each of the plurality of nodes performs the I/O processing thread to transfer the target data for the parallel arithmetic processing, from the storage device to the main memory of own node.