Patent ID: 9741895
Date: 2017-08-22
CPC Classifications: H01L

Claim:
1. An etching method comprising: providing a support containing a semiconductor buffer layer; forming a dielectric masking layer on the semiconductor buffer layer; forming openings in the dielectric masking layer to expose the semiconductor buffer layer; growing a plurality of semiconductor nanostructures extending away from the support through the openings in the dielectric masking layer and in contact with the semiconductor buffer layer exposed in the openings, such that the plurality of semiconductor nanostructures extend above a top surface of the dielectric masking layer; forming a flowable material layer between the semiconductor nanostructures and over a top surface of the dielectric masking layer to cover an entire top surface of the dielectric masking layer; forming a patterned mask over a first portion of the flowable material and the first portion of the plurality of semiconductor nanostructures, wherein the patterned mask is vertically spaced from the dielectric masking layer at least by a bottom portion of the flowable material that overlies the dielectric masking layer, such that a second portion of the flowable material and a second portion of the plurality of semiconductor nanostructures are not located under the patterned mask; and etching the second portion of the flowable material and the second portion of the plurality of semiconductor nanostructures to remove the second portion of the flowable material and the second portion of the plurality of semiconductor nanostructures to leave the first portion of the flowable material and the first portion of the plurality of semiconductor nanostructures unetched.