Patent ID: 9660070
Date: 2017-05-23
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: a semiconductor substrate of a first conductive type having a tetragonal shape including a first side, a second side, a third side, and a fourth side, wherein the first side and the second side are arranged along a first direction, and the third side and the fourth side are arranged along a second direction which is perpendicular to the first direction; a drift region of the first conductive type formed on the semiconductor substrate; a cell region arranged in the drift region; a plurality of power MOSFETs formed in the cell region; a first peripheral region arranged in the drift region and arranged between the cell region and the first side; a second peripheral region arranged in the drift region and arranged between the cell region and the second side; a third peripheral region arranged in the drift region and arranged between the cell region and the third side; and a fourth peripheral region arranged in the drift region and arranged between the cell region and the fourth side, wherein the first peripheral region has a plurality of first columns of a second conductive type opposite to the first conductive type which are formed in the drift region and which extend along the second direction, wherein the second peripheral region has a plurality of second columns of the second conductive type which are formed in the drift region and which extend along the second direction, wherein the third peripheral region has a plurality of third columns of the second conductive type which are formed in the drift region and which extend along the first direction, wherein the fourth peripheral region has a plurality of fourth columns of the second conductive type which are formed in the drift region and which extend along the first direction, wherein the cell region has a plurality of fifth columns of the second conductive type which are formed in the drift region and which extend along the first direction, wherein a resurf region of the second conductive type is formed in the drift region and is arranged at upper portions of the first, second, third and fourth columns, wherein a plurality of gate electrodes of the power MOSFETs are formed over the drift region of the cell region, wherein a plurality of well regions of the second conductive type are formed in the drift region of the cell region, are arranged at upper portions of the fifth columns and have higher impurity concentration than the resurf region, and wherein a plurality of source regions of the power MOSFETs of the first conductive type are formed in the well regions.