Patent ID: 9728549
Date: 2017-08-08
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a cell array area and a step area; a cell gate conductive pattern in the cell array area and extending to the step area; a cell vertical structure in the cell array area and extending through the cell gate conductive pattern; a cell gate contact structure on the cell gate conductive pattern in the step area; a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure; a first peripheral contact structure spaced apart from the cell gate conductive pattern; a second peripheral contact structure spaced apart from the first peripheral contact structure; a first peripheral contact region under the first peripheral contact structure; and a second peripheral contact region under the second peripheral contact structure, wherein the cell gate contact region comprises implanted impurities of a first element and a remainder of the cell gate conductive pattern does not substantially comprise implanted impurities of the first element.