Patent ID: 9552244
Date: 2017-01-24
CPC Classifications: G06F,G11C,H03M

Claim:
1. A method of correcting a bit failure in a memory array, the method comprising: determining a failure in a first failed bit in a first row stored in a first bank of the memory array; storing a first address of the first failed bit in a first single bit repair (SBR) array; storing a valid field in the first SBR array for indicating that a value of the first failed bit at the first address is inverted due to the failure, wherein the first address is a full address of the first failed bit, wherein the first SBR array is stored in a second bank of the memory array, and wherein the first bank and the first SBR array are accessible in parallel; accessing the first row stored in the first bank and the first SBR array stored in the second bank in parallel; and correcting the failure in the first failed bit during a read operation for the first row or a refresh operation by inverting a bit value read out from the first row at the first address, wherein the first row stored in the first bank comprises an upper half or more significant bits of a data word and a second row stored in the second bank comprises a lower half or less significant bits of the data word.