Patent ID: 9607694
Date: 2017-03-28
CPC Classifications: G11C

Claim:
1. A semiconductor memory device, comprising: a first wiring; a second wiring intersecting with the first wiring; a memory cell disposed on an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element; and a control circuit that controls a voltage applied to the memory cell, wherein the control circuit applies a read voltage with respect to the memory cell for a plurality of times to determine a resistive state of the memory cell for a plurality of times, so as to obtain a first determination result or a second determination result, and the control circuit compares a number of the first determination result with a number of the second determination result, terminates a reading operation when the comparison result suggests that an accurate reading is performed, and starts the reading operation again when the comparison result suggests that a read error is caused.