Patent ID: 9634112
Date: 2017-04-25
CPC Classifications: H01L

Claim:
1. A method of fabricating a field effect transistor, comprising: forming a capping layer on a substrate; forming a source ohmic electrode and a drain ohmic electrode on the capping layer to be spaced apart from each other; sequentially forming a first insulating layer and a second insulating layer on the capping layer to cover the source and drain electrodes; forming a photoresist layer with a first opening exposing a portion of the second insulating layer between the source and drain ohmic electrodes; partially etching the second and first insulating layers using the photoresist layer as an etch mask to define a second opening; removing the photoresist layer; partially etching the capping layer using the first and second insulating layers defining the second opening as an etch mask to form a third opening partially exposing the substrate; forming a Γ-shaped gate electrode with a leg portion connected to the substrate through the third opening and a head portion covering a top surface of the second insulating layer; forming a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode; and forming a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode through the first planarization layer, the second insulating layer, and the first insulating layer; wherein the defining of the second opening comprises: partially and anisotropically etching the second and first insulating layers using the photoresist layer as an etch mask to form a preliminary second opening having substantially the same width as the first opening; and selectively and isotropically etching the second insulating layer to define a Y-shaped second opening.