Patent ID: 9673154
Date: 2017-06-06
CPC Classifications: H01L

Claim:
1. A semiconductor device, comprising: a substrate including a chip region; a plurality of dielectric films formed on the substrate; seal rings formed in a peripheral part of a chip region, the seal rings including a first seal ring and a second seal ring, the first seal ring surrounding the second seal ring, the first seal ring and the second seal ring both provided through at least one of the plurality of dielectric films in the peripheral part of the chip region; a protection film formed on a first dielectric film, the first dielectric film being an uppermost film among the plurality of dielectric films; a cap layer having a convex shape, the cap layer having an upper portion and a lower portion which is narrower than the upper portion; and an interconnect formed in the first dielectric film in the chip region, wherein the first seal ring has a plurality of seal components, an uppermost seal component among the plurality of seal components disposed in the first dielectric film, the uppermost seal component having a first side surface and a second side surface which is located outside the first side surface when viewed from above, the cap layer disposed on the uppermost seal component, the upper portion of the cap layer has a first bottom surface and a second bottom surface which is located outside the first bottom surface when viewed from above, the lower portion of the cap layer has a first side surface and a second side surface which is located outside the first side surface when viewed from above, and a connecting point which connects the second bottom surface of the upper portion and the second side surface of the lower portion is located outside the second side surface of the uppermost seal component when viewed from above.