Patent ID: 9601580
Date: 2017-03-21
CPC Classifications: H01L

Claim:
1. A semiconductor device comprising: an n conductivity type first transistor including an n conductivity type SiC layer, a p conductivity type SiC well region provided on the SiC layer, an n conductivity type SiC first source region provided on the well region, an n conductivity type SiC first drain region provided on the well region, a first source electrode electrically connected to the first source region, a first drain electrode electrically connected to the first drain region, and a first gate electrode provided on the well region between the first source region and the first drain region, a first gate insulating film provided between the well region and the first gate electrode; a p conductivity type second transistor including a p conductivity type SiC second source region provided on the SiC layer, a p conductivity type SiC second drain region provided on the SiC layer, a second source electrode electrically connected to the second source region, a second drain electrode electrically connected to the second drain region, and a second gate electrode provided on the SiC layer between the second source region and the second drain region, a second gate insulating film provided between the SiC layer and the second gate electrode, an n conductivity type SiC first dummy region provided between the second source region and a second contact region, an n conductivity type SiC second dummy region provided between the second drain region and a third contact region, wherein an angle between a direction of a channel forming portion of the second transistor and a direction of a channel forming portion of the first transistor is larger than 0 degree and smaller than 90 degrees; and an element isolation region provided between the well region and the second drain region, a bottom of the element isolation region positioned in the SiC layer.