Patent ID: 9735051
Date: 2017-08-15
CPC Classifications: H01L

Claim:
1. A method to fabricate a semiconductor device, comprising: forming a dual damascene opening in an ILD (inter-level dielectric) layer, wherein the dual damascene opening comprises a via opening and a trench opening which is disposed over the via opening; depositing a layer of diffusion barrier material to cover the ILD layer and to line the via opening and the trench opening with the diffusion barrier material; depositing a layer of first metallic material on the layer of diffusion barrier material to cover the ILD layer with overburden first metallic material and to line the via opening and the trench opening with a layer of the first metallic material; performing a reflow process by thermal annealing at a temperature which causes the layer of first metallic material to melt and allow at least a melted portion of the overburden first metallic material on the ILD layer and at least a melted portion of the layer of first metallic material which lines the trench opening to reflow into the via opening and at least partially fill the via opening with the melted first metallic material; and depositing a layer of second metallic material on the reflowed first metallic material to at least partially fill a remaining portion of the dual damascene opening in the ILD layer, wherein the first metallic material comprises cobalt.