Patent ID: 9553129
Date: 2017-01-24
CPC Classifications: H01L

Claim:
1. A method of forming a device comprising: providing a substrate defined with a memory cell region; providing a first upper dielectric layer over the substrate, wherein the first upper dielectric layer comprises a first upper interconnect level with one or more metal lines in the memory cell region; providing a second upper dielectric layer over the first upper dielectric layer, wherein the second upper dielectric layer comprises a via plug coupled to the metal line of the first upper interconnect level; providing a protective layer over the second upper dielectric layer and covers the via plug; forming an alignment trench which extends from a top surface of the protective layer to a portion of the second upper dielectric layer; forming various layers of a magnetic tunnel junction (MTJ) stack over the second upper dielectric layer, wherein profile of the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which serves as an alignment mark; and patterning the various layers of the MTJ stack to define at least one MTJ element using the topography feature which serves as the alignment mark visible in top surface of the various layers of the MTJ stack to align the patterned MTJ element to the underlying via plug and to ensure that the patterned MTJ element is coupled to and in direct contact with the underlying via plug.