Patent ID: 9748247
Date: 2017-08-29
CPC Classifications: G11C,H01L

Claim:
1. A semiconductor device comprising a memory cell having an SRAM structure formed on a semiconductor substrate, the memory cell including: a first p-type well, an n-type well, and a second p-type well formed in an upper surface of the semiconductor substrate in that order in a first direction along a principal surface of the semiconductor substrate; a first n-type field effect transistor and a second n-type field effect transistor formed in a first active region on an upper surface of the first p-type well; a first p-type field effect transistor formed in a second active region on an upper surface of the n-type well; a second p-type field effect transistor formed in a third active region on an upper surface of the n-type well; and a third n-type field effect transistor and a fourth n-type field effect transistor formed in a fourth active region on an upper surface of the second p-type well, wherein the second active region is formed on a first p-type well side of the third active region, wherein the second active region includes an extending portion extending in a second direction along a boundary between the first p-type well and the n-type well in a plan view and an end in the second direction of the second active region, and wherein a distance in the first direction between the boundary and the end is larger than a distance in the first direction between the boundary and the extending portion.