Patent ID: 9721848
Date: 2017-08-01
CPC Classifications: H01L

Claim:
1. A method for forming a semiconductor device, the method comprising: forming a first fin and a second fin on a substrate; forming a sacrificial gate having a gate cap on the first fin and the second fin; forming spacers adjacent to sidewalls of the sacrificial gate; forming a source/drain region on exposed portions of the first fin and the second fin; forming an insulator layer on the source/drain region; depositing a sacrificial liner layer on the sacrificial gate and the insulator layer; removing portions of the sacrificial liner layer and removing portions of a gate cap to expose portions of the sacrificial gate; removing portions of the sacrificial gate and exposed portions of the second fin to form a first cavity and a second cavity, where an exposed portion of the second fin is removed from the second cavity; depositing a liner layer in the first cavity and the second cavity; removing portions of the liner layer in the second cavity to expose the substrate, and removing portions of the substrate in the second cavity; depositing a dielectric fill material in the first and second cavity; removing the sacrificial gate; and forming a gate stack over a channel region of the first fin.