Patent ID: 9529686
Filing Date: 2016-12-27
CPC Classification: G06F

Claim Text:
1. A method of detecting faults on a bus interconnect that connects a bus master circuit to bus slave circuits, comprising: concurrently executing an application program and a fault detection program by the bus master circuit, wherein the application program initiates first bus transactions to the bus slave circuits, and the fault detection program initiates second bus transactions to the bus slave circuits for detection of faults in data channels of the bus interconnect; wherein the concurrently executing the fault detection program includes for each of the bus slave circuits: generating by an error code generator circuit, error codes from addresses of the first and second bus transactions transmitted by the bus master circuit; transmitting the error codes with the first and second bus transactions on address channels of the bus interconnect to addressed ones of the bus slave circuits; determining by respective error code checker circuits coupled between the bus interconnect and the bus slave circuits, whether or not the addresses of the bus transactions are correct based on the error codes.