Patent ID: 9431117
Filing Date: 2016-08-30
CPC Classification: G06F,G11C

Claim Text:
1. A memory system comprising: a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers; and a memory controller configured to control the nonvolatile memory device, wherein the memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation, wherein the read reclaim operation is processed as complete when all the valid data of the target memory block is transferred to the one or more memory blocks of the first memory area, wherein the read reclaim operation is timewise divided into a plural separately executed parts in which respective portions of the valid data of the target memory block are transferred to the one or more memory blocks of the first memory area, wherein the memory controller is configured to execute at least a part of the read reclaim operation after a write operation requested by a host is completed, and wherein, in the read reclaim operation, a portion of the valid data is transferred from the target memory block after the write operation is completed and before expiration of a predetermined time period, and wherein a data amount of the portion of the valid data is determined based on a time remaining after the write operation is complete until the predetermined time period.