Patent ID: 9473344
Filing Date: 2016-10-18
CPC Classification: G06F,H04L

Claim Text:
1. An integrated circuit, comprising: plural configuration pins that, when configured, establish a priority value assigned to the integrated circuit; a storage unit; a detecting circuit that receives the priority value from the configuration pins and stores the priority value in the storage unit; an interface circuit that receives plural PHY addresses in succession, wherein the plural PHY addresses include a first PHY address and a second PHY address; a determining circuit comprising: a register; a comparing circuit; and a priority control circuit, wherein based on the priority value, the determining circuit stores the first PHY address in the register, and based on receiving the second PHY address, the comparing circuit compares the first PHY address stored in the register with the second PHY address and outputs a comparison result, wherein the priority control circuit receives the comparison result and based on the priority value, determines: if the first PHY address is equal to the second PHY address, the priority control circuit does not store the second PHY address; and if the first PHY address is not equal to the second PHY address, the priority control circuit stores the second PHY address in the storage unit.