Patent ID: 9425174
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. An integrated circuit package, comprising: a package substrate having a surface, the package substrate having a plurality of conductive pads at the surface of the package substrate; a solder mask layer that is formed on the surface of the package substrate over the plurality of conductive pads; an integrated circuit die having front and back surfaces, wherein the integrated circuit die is mounted on the package substrate, and wherein the front surface of the integrated circuit die faces the package substrate; a plurality of conductive pillars formed on the front surface of the integrated circuit die, each of which makes direct physical contact with a corresponding conductive pad in the plurality of conductive pads without any intervening solder; a plurality of interconnect pathways in the package substrate, each of which is coupled to a corresponding conductive pad in the plurality of conductive pads; an additional integrated circuit die that is mounted on the package substrate and that is coupled to the integrated circuit die through the plurality of interconnect pathways; and an additional plurality of conductive pads formed at a top surface of the solder mask layer, wherein the additional integrated circuit die is mounted directly on the additional plurality of conductive pads.