Patent ID: 9411592
Filing Date: 2016-08-09
CPC Classification: G06F,H03M

Claim Text:
1. A processor comprising: a first register comprising a first plurality of data fields, wherein each of the first plurality of data fields is to store a plurality of bits; a first destination register comprising a second plurality of data fields corresponding to the first plurality of data fields, wherein each of the second plurality of data fields is to store a count of a number of bits set to one for a corresponding data field of the first plurality of data fields; a second register comprising a third plurality of data fields corresponding to the second plurality of data fields, wherein each of the third plurality of data fields is to store a copy of a specific value; a second destination register comprising a plurality of mask fields, a portion of the plurality of mask fields corresponding to the second plurality of data fields; a decode stage to decode one or more instructions; one or more execution units, responsive to the decoded one or more instructions, to: