Patent ID: 9406677
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first region and a second region; forming at least one first dummy gate on the semiconductor substrate in the first region and at least one second dummy gate on the semiconductor substrate in the second region; forming a dielectric layer with a top surface leveling with top surfaces of the first dummy gate and the second dummy gate on the semiconductor substrate; oxidizing a top portion of the second dummy gate to form a protective layer to prevent over-polishing on the second region on the second dummy gate; removing the first dummy gate to form a first gate trench; forming a first metal layer to fill the first gate trench and cover the protective layer and the dielectric layer in the second region; and removing a portion of the first metal layer higher than the dielectric layer to form a first metal gate in the first gate trench.