Patent ID: 9252192
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device including a cross point cell array, the method comprising: forming a first stack structure including a first conductive layer over a substrate; forming a first mask pattern over the first stack structure, wherein the first mask pattern includes a pair of first line-shaped patterns extending in a first direction and a pair of first end connectors connecting both end portions of one of the pair of first line-shaped patterns to corresponding end portions of the other of the pair of first line-shaped patterns, respectively; etching the first stack structure using the first mask pattern as an etch mask to form a first intermediate pattern structure including a pair of parallel line patterns; forming a first gap-fill insulation layer to fill a space between the parallel line patterns of the first intermediate pattern structure; forming a second stack structure including a second conductive layer over the first gap-fill insulation layer and the first intermediate pattern structure; forming a second mask pattern over the second stack structure, wherein the second mask pattern includes a pair of second line-shaped patterns extending in a second direction crossing the first direction and a pair of second end connectors connecting both end portions of one of the pair of second line-shaped patterns to corresponding end portions of the other of the pair of second line-shaped patterns, respectively; etching the second stack structure and the first intermediate pattern structure using the second mask pattern as an etch mask to form a second intermediate pattern structure, wherein the second intermediate pattern structure includes a pair of first conductive lines extending in the first direction, a pair of first conductive connectors connecting both end portions of one of the pair of first conductive lines to corresponding end portions of the other of the pair of first conductive lines, a pair of second conductive lines crossing the pair of first conductive lines, a pair of second conductive connectors connecting both end portions of one of the pair of second conductive lines to corresponding end portions of the other of the pair of second conductive lines; forming a second gap-fill insulation layer over the substrate to fill a space between the pair of second conductive lines of the second intermediate pattern structure; forming a cut mask pattern over the second gap-fill insulation layer to expose portions of the second gap fill insulation layer disposed over the first and second conductive connectors; etching the second-gap-fill insulation layer and the second intermediate pattern structure using the cut mask pattern as an etch mask to remove the first and second conductive connectors; and wherein the cut mask pattern includes a trench to expose the portions of the second gap-fill insulation layer disposed over the first and second conductive connectors, and wherein the trench has a width that is greater than widths of the first and second conductive connectors and does not overlap with intersection regions of the first and second conductive lines.