Patent ID: 9372229
Filing Date: 2016-06-21
CPC Classification: G01R

Claim Text:
1. An integrated circuit comprising: a parallel scan distributor having a serial test data input and parallel test data outputs; a parallel scan collector having parallel test data inputs and a serial test data output; a first serial scan path having an input coupled with one of the parallel test data outputs, an output coupled with one of the parallel test data inputs, parallel functional outputs, a first strobe signal input and a second strobe signal input; a second serial scan path having an input coupled with one of the parallel test data outputs, an output coupled with one of the parallel test data inputs, and parallel functional inputs; combinational logic having functional inputs coupled with the functional outputs of the first serial scan path and functional outputs coupled with the functional inputs of the second serial scan path; a controller including: synchronizer circuitry having a shift parallel scan path input connected to the shift parallel scan path output (SHPSP), a signal input, and a strobe output; first buffer circuitry having an input coupled to the strobe output and having a first buffer output connected to the first strobe signal input; and second buffer circuitry having an input coupled to the first buffer output and having a second buffer output connected to the second strobe signal input.