Patent ID: 9490263
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate on which a plurality of logic cells are provided; a plurality of active portions provided on the substrate and extending in a first direction; contacts and gate structures extending in a second direction intersecting the first direction, the contacts and the gate structures alternately arranged; a common conductive line extending along a boundary region of the plurality of logic cells in the first direction, wherein at least one of the contacts is electrically connected to the common conductive line through a via therebetween, wherein each of the contacts intersects a plurality of the active portions, wherein end portions of the contacts are aligned with each other along the first direction, wherein each of the logic cells includes a P-type metal-oxide-semiconductor field effect transistor (PMOSFET) region and an N-type metal-oxide-semiconductor field effect transistor (NMOSFET) region, wherein the contacts include PMOS contacts on the PMOSFET region and NMOS contacts on the NMOSFET region, and wherein the PMOS contacts and the NMOS contacts are seperated from each other at a boundary region of the PMOSFET region and the NMOSFET region; and a first device isolation layer provided in the substrate between the PMOSFET region and the NMOSFET region, and wherein end portions of the PMOS contacts or the NMOS contacts are aligned with each other in the first direction on the first device isolation layer.