Patent ID: 9253145
Filing Date: 2016-02-02
CPC Classification: H04L

Claim Text:
1. An electronic component with assignment of an address to the component, comprising: a first terminal for application of a clock signal and a data signal; a second terminal, different from the first terminal, for application of the clock signal and the data signal, wherein the component is configured to be operated in a first operating mode, in which the clock signal is present at the first terminal and the data signal is present at the second terminal, and wherein the component is configured to be operated in a second operating mode, in which the data signal is present at the first terminal and the clock signal is present at the second terminal; a mode recognition unit for determining the first and second operating mode of the component by evaluating which one of the clock signal and the data signal is present at the first terminal and the second terminal; and an address selection unit for assigning at least one first or second address to the component, wherein the address selection unit is configured so that the address selection unit assigns the first or the second address to the component, depending on the operating mode of the component, and wherein the component is configured to be addressed for performing both read and write access via each of the first and second address.