Patent ID: 9257444
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming a preliminary stack structure including an upper preliminary stack structure on a lower preliminary stack structure by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate, removing a portion of the upper preliminary stack structure on the second pad area; forming a first mask on an entire portion of the cell area, a portion of the first pad area, an entire portion of the dummy area, and a portion of the second pad area; forming first patterns in the upper preliminary stack structure and an other first pattern in the lower preliminary stack structure by removing portions of the plurality of sacrificial layers and the plurality of interlayer insulating layers thereunder, which are not covered with the first mask; shrinking sides of the first mask to expose two opposite end portions of the first patterns on the first pad area and the dummy area, and one end portion of the other first pattern on the second pad area; forming second patterns in the upper preliminary stack structure and an other second pattern in the lower preliminary stack structure by removing parts of the plurality of sacrificial layers and the plurality of interlayer insulating layers exposed by the shrunken first mask under the first patterns and the other first pattern while removing the portions of the first patterns and the other first pattern exposed by the shrunken first mask; forming a staircase structure and a dummy staircase structure in the upper preliminary stack structure while forming an other staircase structure in the lower preliminary stack structure after repeating the performing the staircase forming process a plurality of times,