Patent ID: 9246475
Filing Date: 2016-01-26
CPC Classification: H03K

Claim Text:
1. A dual-complementary integrating duty cycle detector with dead band noise rejection comprising: a first integrator for receiving a first clock signal having first and second outputs; a second integrator for receiving a second clock signal having first and second outputs; a first comparator having a first input coupled to the first output of the second integrator, a second input coupled to the second output of the first integrator, and an output for providing a first correction signal; and a second comparator having a first input coupled to the first output of the first integrator, a second input coupled to the second output of the second integrator, and an output for providing a second correction signal, wherein the first and second comparators are configured to provide a dead band in the first and second correction signals wherein at least one of the first and second integrators comprises first, second, and third resistors in series.