Patent ID: 9477591
Filing Date: 2016-10-25
CPC Classification: G06F

Claim Text:
1. A device, comprising: a hybrid controller configured to manage data transfers between a host processor and a secondary memory, the secondary memory configured to serve as a cache for a primary memory, the primary memory including a memory space corresponding to host logical block addresses (LBAs), the hybrid controller configured to receive incoming memory access requests from the host processor, the memory access requests including a range of host LBAs, the memory access requests comprising: route the incoming memory access requests to a set of incoming queues, the set of incoming queues comprising an incoming free queue containing a number of incoming nodes; map the range of host LBAs into clusters of secondary memory LBAs; transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of secondary memory LBAs; route the outgoing memory access requests from the incoming queues into a set of outgoing queues, the set of outgoing queues comprising a set of outgoing execute queues and an outgoing free queue that includes a number of outgoing nodes; use an outgoing node to store data about the outgoing memory access request; make the outgoing node that stores the data about the outgoing memory access request unavailable to store data about other outgoing memory access requests; return the outgoing node to the outgoing free queue after at least a portion of the outgoing memory access request has been executed; and access the secondary memory using the outgoing memory access requests.