Patent ID: 9270257
Filing Date: 2016-02-23
CPC Classification: H03K

Claim Text:
1. A dual-port positive level sensitive reset data retention latch comprising: a clocked inverter configured to receive a first data bit, a first clock signal, a second clock signal, a reset control signal and a retention mode control signal (RET) wherein the first clock signal, the second clock signal, the reset control signal and the retention mode control signal determine whether a first data output from the clocked inverter is the binary compliment of the first data bit or an indeterminate value; a dual-port latch configured to receive the first data output of the clocked inverter, a second data bit, the first clock signal, the second clock signal, the reset control signal, the retention mode control signal, a first latch control signal and a second latch control signal wherein the first clock signal, the second clock signal, the reset control signal, the retention mode control signal, the first latch control signal and the second latch control signal determine whether the first data output of the clocked inverter or the second data bit is latched in the dual-port latch.