Patent ID: 9319031
Filing Date: 2016-04-19
CPC Classification: H03B,H03K,H03L

Claim Text:
1. A current mode logic (CML) ring oscillator comprising: a CML negative impedance compensation circuit comprising two cross coupled transistors and a first resistor connected to the two transistors for resistive biasing; and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation, the CML interpolating delay cell comprising a first differential pair of transistors and a second differential pair of transistors, wherein a first gate of the first differential pair of transistors is coupled to a second resistor, a second gate of the first differential pair of transistors is coupled to a third resistor, a first gate of the second differential pair of transistors is coupled to the second resistor, and a second gate of the second differential pair of transistors is coupled to the third resistor; wherein an impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.