Patent ID: 9490371
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A nonvolatile memory device, comprising: a vertically-stacked gate structure including a plurality of inter-gate insulating patterns stacked on a substrate and a plurality of gate electrodes interposed between the inter-gate insulating patterns in an alternating gate electrode and insulating pattern sequence; a vertical active pillar extending at least partially through the vertically-stacked gate structure; a vertical charge-storing layer extending between the vertical active pillar and the plurality of gate electrodes; a vertical tunnel insulating layer extending between the vertical charge-storing layer and the vertical active pillar; and a vertical blocking insulating layer extending between the vertical charge-storing layer and the plurality of gate electrodes; wherein the vertical charge-storing layer comprises a first charge-storing layer containing silicon nitride adjacent to the vertical blocking insulating layer and a second charge-storing layer adjacent to the vertical tunnel insulating layer, said second charge-storing layer comprising silicon oxynitride; wherein the vertical tunnel insulating layer comprises a first tunnel insulating layer adjacent to the second charge-storing layer and a second tunnel insulating layer adjacent to the vertical active pillar; and wherein the first tunnel insulating layer comprises a silicon oxide layer having a nitrogen concentration therein that is lower than a nitrogen concentration within the second charge-storing layer.