Patent ID: 9519578
Filing Date: 2016-12-13
CPC Classification: G06F

Claim Text:
1. A flash memory controller integrated circuit to receive memory access requests from a host, the flash memory controller integrated circuit comprising: at least one host interface to receive the memory access requests from the host and to exchange data with the host; at least one memory interface to program the data into the flash memory dies, and to read the data therefrom; circuitry to map, for each memory access request, a logical base address conveyed by the memory access request to a variable number of physical locations in respective ones of the flash memory dies, depending on logical base address, such that circuitry to control data programming and read operations in the flash memory dies via the memory interface in response to the memory access requests, according to the mapped, variable number of physical locations; wherein the physical locations are respective ones of a unit of flash memory cells, such that a variable data size is to be exchanged between the flash memory controller integrated circuit and the host in association with each memory access request, corresponding to the logical base address conveyed with the memory access request.