Patent ID: 9400762
Filing Date: 2016-07-26
CPC Classification: G06F

Claim Text:
1. An integrated device, comprising: memory systems, respectively including a plurality of unit memories able to be independently accessed; at least one processing module configured to access the plurality of unit memories through an input/output port; a memory interface, facing the processing module and centrally positioned between the memory systems and connected to the processing module and each unit memory by connection interconnects for interfacing data transfer between the unit memories and the processing module; a connection interconnect layer including a bypass route and a basic route that connect in a stacking direction to the plurality of unit memories, wherein the basic route is shared by the plurality of unit memories for selectively accessing an arbitrary unit memory of the plurality of unit memories by the at least one processing module by using public interconnects, the bypass route is configured to access a predetermined unit memory of the plurality of unit memories by the at least one processing module by using a combination of private interconnects and the public interconnects, the basic route and the bypass route provide simultaneous access routes to the predetermined unit memory, the plurality of unit memories are positioned to be the shortest distance from the processing modules by being sandwiched between the memory interface and the processing module, and the private interconnects are configured to individually connect one of the processing module to at least one of the memory systems.