Patent ID: 9268495
Filing Date: 2016-02-23
CPC Classification: G06F

Claim Text:
1. A memory system comprising: an electrically erasable semiconductor memory, to store data; a storage processor, coupled to the memory; a command interface to receive multiple access requests for the memory, wherein the multiple access requests each include an external priority; an expectation table, to store a latency expectation associated with each external priority; and a mode selector, to select an operating mode for the storage processor, the operating modes including a normal mode and a preemption mode, the preemption mode to cause the storage processor to process the multiple access requests in an order based on the expectation table, the storage processor further to process a second access request having a second external priority before a first access request having a first external priority, wherein the first external priority is relatively higher than the second external priority and the second access request has a pendency period that exceeds the latency expectation associated with the second external priority.