Patent ID: 9367496
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A DMA transfer apparatus that is disposed between a source memory and a destination memory and performs DMA transfer from the source memory and the destination memory, comprising: a pattern generation section that generates predetermined pattern data which will be transferred to the destination memory; a queuing section that receives transfer data which is continuously output from the source memory, and queues the transfer data so as to synchronize the transfer data with the predetermined pattern data generated in the pattern generation section; and a measuring section that measures the size of the transfer data which has been transferred; and a multiplexer which is configured to insert the predetermined pattern data into the transfer data in such a way that the predetermined pattern data is started to be inserted when the measuring section indicates that the size of the transfer data which has been transferred reaches a predetermined size and in such a way that a rest part of the transfer data which has relinquished a right of transfer to the inserted predetermined pattern data is delayed by the queuing section and follows the predetermined pattern data, wherein a plurality of types of the predetermined pattern data are prepared, and the pattern generation section generates the predetermined pattern data based on both of a parameter indicating which pattern data is to be output and a parameter indicating the size of the predetermined pattern data per each of the plurality of types of the predetermined pattern data.