Patent ID: 9343388
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A power semiconductor device comprising: a semiconductor-element substrate including an insulation substrate, a front-surface electrode pattern formed on a surface of the insulating substrate, and a back-surface electrode pattern formed on another surface of the insulating substrate; a semiconductor element for electric power which is affixed, by using a bonding material, to the surface of the front-surface electrode pattern opposite the insulating substrate; a partition wall which is provided on the front-surface electrode pattern by bonding, and encloses the semiconductor element for electric power; a first sealing resin member which is filled inside the partition wall, and covers the semiconductor element for electric power and the front-surface electrode pattern in the partition wall; and a second sealing resin member which covers the partition wall, the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall, wherein a modulus of elasticity of the second sealing resin member is smaller than a modulus of elasticity of the first sealing resin member, and wherein an electrode for a relay terminal which is separate from the front-surface electrode pattern is disposed on a surface of the partition wall, the power semiconductor device further comprising a first wiring from inside of the partition wall to the electrode for a relay terminal, and second wiring, which is thicker than the first wiring, from the electrode for the relay terminal to outside of the partition wall, wherein the first wiring is entirely covered with the first sealing resin member and the second wiring is covered with the second sealing resin member.