Patent ID: 9390925
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A method of refining a semiconductor device under construction, the method comprising: providing an uncovered intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer, with the base layer including a top surface and the first fin structure including a first lateral surface and a second lateral surface; refining the uncovered intermediate sub-assembly into a covered intermediate sub-assembly by covering at least a portion of the top surface of the base layer of the uncovered intermediate sub-assembly and at least a portion of the first and second lateral surfaces of the first fin structure of the uncovered intermediate sub-assembly with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and refining the covered intermediate sub-assembly into a thermally-oxidized intermediate sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure, thereby changing the pre-thermal oxidation layer into a post-thermal oxidation layer.