Patent ID: 9507739
Filing Date: 2016-11-29
CPC Classification: G06F,G11C

Claim Text:
1. A sub-system, comprising: an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the interface circuit configured to: interface the plurality of physical memory circuits and the system for emulating a virtual memory circuit having a refresh cycle time constraint that is different from a refresh cycle time constraint of the plurality of physical memory circuits; receive a refresh command from the system directed to the virtual memory circuit; in response to receiving the refresh command from the system directed to the virtual memory circuit, determine a staggered sequence of timings for issuing refresh commands to the plurality of physical memory circuits, wherein the staggered sequence of timings satisfy the refresh cycle time constraint of the virtual memory circuit and the refresh cycle time constraint of the plurality of physical memory circuits; and based on the staggered sequence of timings, issue refresh commands to respective physical memory circuits, wherein the refresh cycle time constraint of the virtual memory circuit specifies a minimum refresh cycle time (tRFC) associated with the virtual memory circuit, and wherein the first refresh command and the second refresh command are issued within a span of time specified by the tRFC associated with the virtual memory circuit.