Patent ID: 9292290
Filing Date: 2016-03-22
CPC Classification: G06F

Claim Text:
1. A circuit arrangement, comprising: a processing unit; a memory address translation data structure for use in performing memory address translation for instructions in an instruction stream being executed by the processing unit, wherein the memory address translation data structure includes a decode-related attribute associated with an instruction from the instruction stream, wherein the instruction is associated with an address at which the instruction is stored in an address space, and wherein the decode-related attribute is accessed using at least a portion of the address; decode logic configured to access the decode-related attribute in the memory address translation data structure and decode at least a portion of an opcode for the instruction using the decode-related attribute; and an opcode data structure configured to store a plurality of opcodes, wherein the decode logic is configured to access the opcode data structure using the decode-related attribute to determine the at least a portion of the opcode, wherein the opcode data structure comprises a table storing the plurality of opcodes, and wherein the decode-related attribute includes at least a portion of an index used to select an opcode from among the plurality of opcodes.