Patent ID: 9312174
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method for manufacturing contact plugs for semiconductor devices, comprising: providing a substrate comprising a plurality of transistors and a first dielectric layer filling spaces between the transistors formed thereon, wherein the transistors respectively comprises a gate and a source/drain; forming a plurality of silicide layers respectively on the gates; forming a sacrificial layer, a mask layer, and a patterned photoresist layer sequentially on the first dielectric layer after forming the silicide layers; etching the mask layer and the sacrificial layer through the patterned photoresist layer to form a patterned sacrificial layer on the first dielectric layer, the patterned sacrificial layer comprising a plurality of first openings corresponding to the gates of the transistors; forming a second dielectric layer filling up the first openings; removing the patterned sacrificial layer to form a plurality of second openings in the second dielectric layer, the second openings being formed correspondingly to the sources/drains of the transistors; performing an etching process to etch the first dielectric layer through the second openings to form a plurality of first contact holes exposing the sources/drains of the transistors; and forming a plurality of first contact plugs respectively in the first contact holes.