Patent ID: 9324583
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A high-density system-level chip packaging method, comprising: forming an adhesive layer on a carrier board directly, where a shape and position of the adhesive layer correspond to shapes of functional surfaces of units to be packaged and positions on the carrier board where the units to be packaged are to be attached, respectively, so that the units to be packaged are attached according to the position of the adhesive layer in subsequent processes; affixing at least one chip and at least one periphery circuit on the adhesive layer with functional surfaces of the at least one chip and the at least one periphery circuit-attached to the adhesive layer, where one unit to be packaged comprises one chip and one periphery circuit; forming a sealing material layer on a surface of the carrier board to which the at least one chip and the at least one periphery circuit are attached and performing packaging and curing, wherein a plurality of grooves are formed on the sealing material layer in positions corresponding to intervals between the units to be packaged, and the plurality of grooves form a plurality of closed loops each of which is around at least one of the units to be packaged; and removing the carrier board and the adhesive layer entirely.