Patent ID: 9313505
Filing Date: 2016-04-12
CPC Classification: H04N

Claim Text:
1. A decoder, comprising: one or more processors; and a storage medium coupled to the one or more processors having instructions stored thereon which, when executed by the one or more processors, cause the one or more processors to perform operations comprising: obtaining a coded video picture including a first slice and a second slice that are divided by at least one slice boundary and a first tile and a second tile that are divided by a tile boundary, wherein the first tile and the second tile do not have tile headers; obtaining, from the coded video picture, a parameter set including a first flag for controlling a deblocking filter operation across the tile boundary; determining that the first flag indicates an application of the deblocking filter operation across the tile boundary; and in response to determining that the first flag indicates the application of the deblocking filter operation across the tile boundary, applying the deblocking filter operation across the tile boundary; obtaining, from the coded video picture, a slice header including a second flag for controlling a deblocking filter operation across the at least one slice boundary; determining that the second flag indicates an application of the deblocking filter operation across the at least one slice boundary; in response to determining that the second flag indicates the application of the deblocking filter operation across the at least one slice boundary, applying the deblocking filter operation across the at least one slice boundary; and wherein applying a deblocking filter operation across a boundary comprises: