Patent ID: 9301387
Filing Date: 2016-03-29
CPC Classification: H05K,Y10T

Claim Text:
1. A PCB with burr prevention structure, the PCB comprising: a plurality of unit PCBs arrayed on the PCB; a plurality of dummy PCBs arranged at a periphery of the unit PCBs; a first sawing line formed among the plurality of unit PCBs; and a second sawing line formed among the plurality of dummy PCBs and connected to the first sawing line, wherein the second sawing line is formed with an ID (identification) mark for a sawing process of the PCB, wherein the ID mark includes a conductive pad comprising a first laver formed with a Photo Solder Resistor (PSR) and a second laver on which the PSR is removed at a predetermined area to open the conductive pad, and wherein the first sawing line is formed at each corner of the plurality of unit PCBs with a hole to inhibit the corner of the unit PCBs from being sharpened; wherein the first sawing line includes grooves formed at an upper surface and a bottom surface of the PCB.