Patent ID: 9263344
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method of making a semiconductor device comprising: providing a substrate having an NMOS region and a PMOS region; forming a gate structure on each of the NMOS region and the PMOS region; applying an interlevel dielectric between the gate structure over the NMOS region and the gate structure over the PMOS region; removing the gate structure over the NMOS region and the gate structure over the PMOS region to leave an opening in the interlevel dielectric over each of the NMOS region and the PMOS region; depositing at least one of: lanthanum oxide in the opening over the NMOS region, depositing a high-k dielectric in the opening over the NMOS region and further directly depositing the high-k dielectric over the lanthanum oxide when the lanthanum oxide is in the opening over the NMOS region and depositing a high-k dielectric in the opening over the PMOS region and further directly depositing the high-k dielectric directly over the aluminum oxide when the aluminum oxide is in the opening over the PMOS region; depositing a first work function setting metal in the opening over the NMOS region and depositing a second work function setting metal in the opening over the PMOS region to partially fill the openings; and depositing a gate electrode fill metal to fill the openings.