Patent ID: 9361160
Filing Date: 2016-06-07
CPC Classification: G06F,Y02D

Claim Text:
1. A multi-core processor, comprising: a set of main processing elements, each configured to request a set of sub-processing elements from a logical group of sub-processing elements, the set of main processing elements comprising: wherein the logical group of sub-processing elements comprises: a first sub-processing element located in the first physical partition, a second sub-processing element located in the second physical partition, and a third sub-processing element located in the third physical partition; and a first virtualized control thread generated by the first main processing element, the first virtualized control thread associating the second main processing element of the second physical partition with the logical group of sub-processing elements; wherein each of the first main processing element, the second main processing element, and the third main processing element, is configured to log events taking place at each of the first sub-processing element, the second sub-processing element, and the third sub-processing element.