Patent ID: 9301388
Filing Date: 2016-03-29
CPC Classification: H05K,Y10T

Claim Text:
1. A printed circuit board ( 10 ), having printed circuit tracks ( 11 , 11 a ) which are arranged on at least one surface of the printed circuit board ( 10 ) and are used to make electrical contact with components, and having at least one test zone ( 12 ) which is formed by a section of a printed circuit track ( 11 ) and is used to make electrical contact with a testing element ( 20 ), wherein the surface of the printed circuit board ( 10 ) is provided with a protective layer ( 14 ), which is interrupted in the test zone ( 12 ) in the region of a contact zone ( 15 ), and wherein the contact zone ( 15 ) is provided with a layer ( 18 ) which is exposed to make an electrical contact between the testing element ( 20 ) and the layer ( 18 ), characterized in that the contact zone ( 15 ) is arranged at least partially with lateral spacing from edges of the printed circuit track ( 11 ) in the region of the test zone ( 12 ), wherein the layer ( 18 ) forms an elevation which projects above the protective layer ( 14 ) of the printed circuit board ( 10 ) in an upward direction and the test zone ( 12 ) has a lateral spacing (A) from at least one other printed circuit track ( 11 a ) which is less than the radius of the testing element ( 20 ) so that, when the testing element ( 20 ) is placed on the contact zone ( 15 ), the other printed circuit track ( 11 a ) is covered by the testing element ( 20 ), wherein the testing element ( 20 ) does not make electrical contact with the other printed circuit track ( 11 a ).