Patent ID: 9466388
Filing Date: 2016-10-11
CPC Classification: G11C

Claim Text:
1. A readout circuit with a self-detection circuit, comprising: a precharge circuit and a control circuit, the precharge circuit and the control circuit being connected at a first node and being configured to charge a memory unit; characterized in that, the readout circuit further comprises a detection circuit, the detection circuit and the precharge circuit are connected at the first node; the detection circuit comprises a third NOT gate, a fourth NOT gate, a first NAND gate, a sixth NOT gate, a first trigger and an eighth NOT gate; wherein an input of the third NOT gate EX is connected to the first node, an output of the third NOT gate and an input of the fourth NOT gate are connected at a third node, an output of the fourth NOT gate and an input for a clock signal of the first trigger are connected at a fourth node, an inverse reset terminal of the first trigger is connected to an output of the eighth NOT gate, an input of the eighth NOT gate is connected to a first signal terminal, an output of the first trigger is connected to an input of the first NAND gate, another input of the first NAND gate is connected to a first read terminal, an output of the first NAND gate is connected to an input of the sixth NOT gate, the first NAND gate is further connected to the third node.