Patent ID: 9404971
Filing Date: 2016-08-02
CPC Classification: G01R

Claim Text:
1. A monolithic stacked integrated circuit (IC) comprising: a first layer and a second layer, wherein the first layer and the second layer are formed in different wafers and are bonded together, and wherein the first layer includes a known-good-layer (KGL) test circuit, the KGL test circuit comprising: first and second control elements; a first input, to receive a first scan data; a scan segment, to receive the first scan data from the first input and to shift the first scan data to an output of the scan segment; a first multiplexer, to select between the first input and the output of the scan segment in response to a value of the first control element; a first output, coupled to an output of the first multiplexer and to send the first scan data to the second layer; a second input, to receive a second scan data from the second layer; a second multiplexer, to select between the second input and the output of the first multiplexer in response to a value of the second control element; and a second output, coupled to an output of the second multiplexer.