Patent ID: 9524910
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate; patterned first and second semiconductor layers sequentially formed on the substrate; an isolation layer formed on the substrate, wherein the isolation layer has a top surface located between top and bottom surfaces of the first semiconductor layer, and thus defines a fin comprising the patterned first and second semiconductor layers above the isolation layer and extending in a first direction; a gate stack formed on the isolation layer and extending in a second direction crossing the first direction to intersect the fin, wherein the first semiconductor layer comprises a compound semiconductor, with at least one component whose concentration has a graded distribution in a height direction of the fin and wherein the first semiconductor layer is recessed with respect to the second semiconductor layer in the second direction so as to define a lateral recess therein, and the semiconductor device further comprises a dielectric body spacer formed in the lateral recess.