Patent ID: 9318329
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming alternating interlayer insulating layers and sacrificial layers on a substrate; forming a first capping layer on the interlayer insulating layers and the sacrificial layers; forming a channel hole passing through the first capping layer, the interlayer insulating layers and the sacrificial layers to expose a first portion of the substrate; forming a dielectric pattern conforming to a wall of the channel hole; forming an amorphous channel active pattern conforming to the dielectric pattern and the exposed first portion of the substrate; forming a channel core pattern in a space defined by the amorphous channel active pattern; forming an amorphous silicon layer on the first capping layer and the amorphous channel active pattern; forming a mask pattern on the amorphous silicon layer and the amorphous channel active pattern; forming an insulating barrier layer on the mask pattern; forming a metal catalytic layer on the insulating barrier layer; and annealing to change the amorphous silicon layer and the amorphous channel active pattern into a single-crystalline silicon layer and a single-crystalline channel active pattern, respectively.