Patent ID: 9274962
Filing Date: 2016-03-01
CPC Classification: G06F

Claim Text:
1. An apparatus comprising: a cache memory including data storage including a first data entry and a second data entry; state storage associated with the data storage, the state storage including a first state entry to hold a first processing element speculative value to indicate a first processing element has speculatively accessed the first data entry and a second state entry to hold the first processing element speculative value to indicate the first processing element speculatively accessed the second data entry, wherein the state storage further comprises a coherency storage structure to hold a coherency state for the first state entry and for the second state entry, and a speculative storage structure to hold speculative values of the first state entry and for the second state entry; and a first speculative port operatively coupled to the first state entry and a second speculative port operatively coupled to the second state entry, the first and second speculative ports including speculative algorithm logic to: