Patent ID: 9299826
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A memory device, comprising: a gate structure including a first conductive layer pattern and a second conductive layer pattern sequentially stacked on a substrate, the second conductive layer pattern having a resistance lower than a resistance of the first conductive layer pattern; a contact plug passing through an upper surface of the second conductive layer pattern and penetrating into the second conductive layer pattern, a sidewall of the contact plug directly contacting at least a portion of the second conductive layer pattern; and a spacer surrounding a portion of the sidewall of the contact plug and contacting the gate structure, wherein the contact plug includes a metal layer pattern and a barrier layer pattern surrounding the metal layer pattern, and wherein a width of at least a portion of the barrier layer pattern contacting the second conductive layer pattern is greater than widths of other portions of the barrier layer pattern not contacting the second conductive layer pattern.