Patent ID: 9529377
Filing Date: 2016-12-27
CPC Classification: G01R,G05F,G06F,H02M,Y02D

Claim Text:
1. An adaptive voltage scaling circuit comprising: a performance classification monitor disposed inside a chip and configured to detect working performance of the chip at a current working voltage; and an adaptive controller for receiving a detection result signal from the performance classification monitor; wherein the performance classification monitor comprises a source signal generating circuit, a comparison reference circuit, at least first and second delay circuits, at least first and second comparison branch circuits and at least first and second comparison detection circuits; and the adaptive controller comprises a configuration circuit; wherein an input end of the source signal generating circuit and first input ends of the comparison reference circuit, the first comparison branch circuit and the second comparison branch circuit each receives a clock signal as a drive; a first output end of the configuration circuit provides a first configuration signal connected to a first input end of the first delay circuit; a second output end of the configuration circuit provides a second configuration signal connected to a first input end of the second delay circuit; an output end of the source signal generating circuit configured to provide a source signal and connected to second input ends of the comparison reference circuit and the first and second delay circuits; an output end of the first delay circuit connected to a second input end of the first comparison branch circuit; an output end of the second delay circuit connected to a second input end of the second comparison branch circuit; an output end of the comparison reference circuit configured to provide a reference signal and connected to each of first input ends of the first comparison detection circuit and the second comparison detection circuit; an output end of the first comparison branch circuit connected to a second input end of the first comparison detection circuit, and an output end of the second comparison branch circuit connected to a second input end of the second comparison detection circuit; and each of an output ends of the first comparison detection circuit and the second comparison detection circuit connected to an input end of the control circuit and configured to provide the detection result signal.