Patent ID: 9312868
Filing Date: 2016-04-12
CPC Classification: H03K,H03L,H04L

Claim Text:
1. A semiconductor device comprising: a data buffer suitable for receiving an input signal from an external; a clock buffer suitable for receiving a clock; a first path suitable for transmitting the input signal from the data buffer; a second path suitable for transmitting the clock from the clock buffer; a delay locked loop (DLL) suitable for delaying the clock from the second path to generate a delay locked clock; a code generation unit suitable for generating a digital code corresponding to 1/N of the clock cycle where N is an integer equal to or more than two; a delay unit suitable for delaying the delay locked clock from the DLL by a value corresponding to the digital code to output a delayed clock; a third path suitable for transmitting the delayed clock from the delay unit; and a strobing unit suitable for strobing the input signal from the first path using the delayed clock from the third path, wherein the DLL delays the clock by [(M*tCK)−(B+C−A)], where M is an integer equal to or more than one, tCK is one cycle of the clock, B is a delay value of the second path, C is a delay value of the third path, and A is a delay value of the first path.