Patent ID: 9396982
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: an insulating layer having a first surface and a second surface opposite the first surface, wherein a package trace layout comprising a plurality of traces is embedded in the insulating layer between the first surface and the second surface of the insulating layer, the plurality of traces are entirely exposed and recessed on the first surface of the insulating layer to form a recessed pattern such that an exposed surface of the embedded traces is not on the same plane as the first surface of the insulating layer; a semiconductor chip disposed on the first surface of the insulating layer and comprises a plurality of conductors connecting the semiconductor chip to the package trace layout, wherein an inner part of the package trace layout lies inside an area of the semiconductor chip, the conductors are disposed between the semiconductor chip and the inner part of the package trace layout, and extend from a surface of the semiconductor chip to the embedded traces of the inner part of the package trace layout; and an encapsulating layer disposed on the first surface of the insulating layer and encapsulates the semiconductor chip, wherein an outer part of the package trace layout lies outside the area of the semiconductor chip, the encapsulating layer further fills the trace pattern and encapsulates the embedded traces of the outer part of the package trace layout.