Patent ID: 9252277
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate; a plurality of wire layers stacked to be apart from each other on the semiconductor substrate; a plurality of gate insulators disposed on upper surfaces, lower surfaces and side surfaces of respective wire layers; a gate electrode disposed on the upper surfaces, the lower surfaces and the side surfaces of the wire layers via the gate insulators; a plurality of epitaxial layers disposed on the side surfaces of the respective wire layers; and an interlayer dielectric disposed on the semiconductor substrate to cover the wire layers, and applying a stress to the wire layers and the epitaxial layers, wherein a spacing of a gap between the epitaxial layers adjacent in a height direction, and a spacing of a gap between the lower most epitaxial layer and a bottom surface of the interlayer dielectric change in accordance with heights at which the gaps are located.