Patent ID: 9349791
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. An integrated circuit comprising a transistor, the transistor comprising: a first conductive layer over a substrate; a first insulating layer over the first conductive layer; an oxide semiconductor layer including a channel formation region over the first insulating layer, wherein the channel formation region and the first conductive layer overlap each other with the first insulating layer therebetween, a second conductive layer in contact with the oxide semiconductor layer; a third conductive layer in contact with the oxide semiconductor layer; a second insulating layer over the oxide semiconductor layer, the second conductive layer, and the third conductive layer; and a fourth conductive layer over the second insulating layer, wherein the channel formation region and the fourth conductive layer overlap each other with the second insulating layer therebetween, wherein the fourth conductive layer overlaps the second conductive layer and the third conductive layer, wherein the oxide semiconductor layer comprises a first region and a second region below the first region, wherein the first region comprises a crystal, and a c-axis of the crystal is substantially perpendicular to a surface of the oxide semiconductor layer, wherein the second region has a lower crystallinity than the first region, wherein all the metal elements included in the first region are included in the second region, and all the metal elements included in the second region are included in the first region, and wherein a portion of the second insulating layer is in contact with the first region.