Patent ID: 9397784
Filing Date: 2016-07-19
CPC Classification: H01Q,H03M,H04B,H04L

Claim Text:
1. A split signal processing system comprising: multiple antennas for receiving transmitted signals carrying an information-bearing symbol, the information bearing symbol being part of a transmission of coded bits; multiple signal processing modules associated with the respective antennas and generating respective bit log-likelihood ratio (LLR) sequences based in part on a channel estimate from a channel estimator, each bit LLR sequence corresponding to the information-bearing symbol; at least one of the signal processing modules comprising a LLR combiner for combining the bit LLR sequences; and at least one of the signal processing modules comprising a forward error correction (FEC) decoder for decoding the combined bit LLR sequences and releasing an information sequence and an estimate of the coded bits; wherein the channel estimator of at least one of the signal processing modules forms a channel estimate based on the estimate of the coded bits from another of the signal processing modules.