Patent ID: 9250915
Filing Date: 2016-02-02
CPC Classification: G06F

Claim Text:
1. A computer-implemented method for operand fetching control in a computer processor pipeline of a processor having a data cache to store operands fetched by load/store instructions, the method comprising: calculating a summation weight value for each instruction or group of instructions in the computer processor pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction or group of instructions reside in the computer processor pipeline relative to other instructions in the computer processor pipeline; mapping, by a control unit logic of the computer processor pipeline, the summation weight value of a selected load/store instruction in the computer processor pipeline that is attempting to access system memory to one of a number of distinct pre-defined ranges of summation weight values, each of the pre-defined ranges of summation weight values corresponding to a respective memory access control, each of the memory access controls specifying a different manner of handling an operand fetching operation from the data cache, wherein each manner of handling defines a respective depth in a cache hierarchy of the data cache that an operand fetch is permitted to access; receiving the mapped memory access control for the selected load/store instruction from the control unit logic by a load-store unit of the computer processor pipeline via an interface between the control unit logic and the load-store unit; and performing a memory access operation in the data cache for the selected load/store instruction based on the manner of handling the operand fetching operation that is specified by the received mapped memory access control by the load-store unit.