Patent ID: 9431372
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A multi-chip package, comprising: a master chip including transmission/reception circuits suitable for transmitting/receiving a predetermined data; a first slave region that includes data transmission/reception blocks suitable for transmitting/receiving data to/from the master chip through first chip vias and is vertically stacked over the master chip; and a second slave region that includes data transmission/reception blocks suitable for transmitting/receiving the predetermined data to/from the master through second chip vias and is vertically stacked over the first slave region, wherein the data transmission/reception blocks of the first slave region and the first chip vias are arranged over a first portion of the master chip, and the data transmission/reception blocks of the second slave region and the second chip vias are arranged over a second portion of the master chip, which is opposite to the first portion.