Patent ID: 9252744
Filing Date: 2016-02-02
CPC Classification: H03H

Claim Text:
1. An electronic circuit simulating the behavior of an inductance between a respective input node and a reference potential, said electronic circuit comprising: a compensation network having a respective input terminal electrically connected to the input node of the electronic circuit and a respective output terminal, said compensation network being electrically connected between said reference potential and a further reference potential; an inverting amplification stage having a respective input terminal electrically connected to the output terminal of the compensation network, and a respective output terminal electrically connected to the input node of the electronic circuit, said inverting amplification stage being electrically connected between the further reference potential and the reference potential, said inverting amplification stage comprising a transistor having a control terminal operatively connected to the input terminal of the inverting amplification stage, a first bias terminal operatively connected to the output terminal of the inverting amplification stage, a second bias terminal operatively connected to the reference potential; wherein said inverting amplification stage comprises a feedback capacitance interposed between the first bias terminal and the control terminal, respectively, of the transistor, and a feedback inductance interposed between the second bias terminal of the transistor and the reference potential.