Patent ID: 9508433
Filing Date: 2016-11-29
CPC Classification: G11C

Claim Text:
1. A memory cell comprising: first and second resistive elements, at least one of which is programmable to have one of at least two resistive states, a data value being represented by the relative resistances of the first and second resistive elements, the first resistive element being coupled between a first storage node and a first intermediate node, the second resistive element being coupled between a second storage node and a second intermediate node; a first transistor coupled between said first storage node and a first supply voltage; a second transistor coupled between said second storage node and said first supply voltage, wherein a control node of said first transistor is coupled to said second storage node and a control node of said second transistor is coupled to said first storage node; a third transistor coupled between the first and second intermediate nodes; a fourth transistor connected between the first storage node and a second supply voltage; a fifth transistor connected between the second storage node ( control circuitry configured to active said third transistor while applying, by activating the fourth or fifth transistors, the second supply voltage to said first or second storage node to generate a programming current in a selected direction through said first and second resistive elements to program the resistive state of at least one of said elements.