Patent ID: 9274957
Filing Date: 2016-03-01
CPC Classification: G06F

Claim Text:
1. A computer implemented method for monitoring a value without repeated storage access, the method comprising: processing, by a processing circuit comprising a register, an instruction of a program that specifies a memory address of a memory location in a cache to be monitored; configuring, by the processing circuit, a monitor station for monitoring the specified memory address of the memory location in the cache; wherein the register comprises the monitor station, the monitor station being in the processing circuit; receiving, by the processing circuit, a cross-invalidate request from a memory controller, the cross-invalidate request indicating to the monitor station that another processing circuit is requesting exclusive ownership of the specified memory address of the memory location in the cache; wherein the memory controller controls the cache having the specified memory address of the memory location, the processing circuit receiving the cross-invalidate request from the memory controller controlling the cache having the specified memory address of the memory location; wherein the monitor station is configured to make a determination to initiate an interruption of the program; wherein the monitor station is configured to initiate execution of firmware to interrupt the program; wherein the monitor station, in the processing circuit, is configured to delay initiating the execution of the firmware to interrupt the program for a predefined delay time period in order to avoid the processing circuit from receiving frequent interrupts from other monitor stations within the processing circuit, such that the monitor station initiates the execution of the firmware after the predefined delay time period based on a match between a saved memory address in the monitor station and an invalidation target address.