Patent ID: 9530802
Filing Date: 2016-12-27
CPC Classification: H01L

Claim Text:
1. An array substrate, comprising: a gate line and a data line in a display region and crossing each other to define a pixel region; first and second auxiliary patterns having upper surfaces in a non-display region; a gate insulating layer between the gate and data lines and the first and second auxiliary patterns; a passivation layer having an upper surface on the data line and the second auxiliary pattern and including first and second contact holes respectively exposing the first and second auxiliary patterns; a planarization layer on the passivation layer and including first and second pack holes, which respectively correspond to the first and second contact holes; a bridge pattern between the first and second pack holes, the bridge pattern overlapping the second auxiliary pattern; a pixel electrode on the planarization layer and in the pixel region; and a connection pattern on the bridge pattern and contacting the first and second auxiliary patterns, wherein the first and second pack holes expose the upper surface of the passivation layer and the upper surfaces of the first and second auxiliary patterns.