Patent ID: 9419139
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method comprising: forming an oxide layer on a substrate; forming a nitride protection layer on the oxide layer; forming a dummy gate layer on the nitride protection layer; patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate; forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively; forming first and second low-k dielectric spacers at opposite sides of the first and second dummy gate stacks, respectively; growing first and second embedded silicon germanium (eSiGe) source/drain regions in the first and second source/drain cavities, respectively; removing the first dummy gate and the second dummy gate stack; removing the nitride protection layer from the first dummy gate stack, leaving the oxide layer in the first dummy gate stack; removing the nitride protection layer and the oxide layer from the second dummy gate stack; and replacing the first dummy gate with a first high-k dielectric layer and a first metal gate, wherein the first high-k dielectric layer is formed between the first low-k dielectric spacers and along side edges of the oxide layer, resulting in filling of gaps between the oxide layer and the first low-k dielectric spacers.