Patent ID: 9361998
Filing Date: 2016-06-07
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a block of memory cells, the memory cells of the block being erasable as a unit, the block including a first memory string and a second memory string, the first memory string including a first selection transistor and a plurality of first memory cells which are stacked above a semiconductor substrate, the second memory string including a second selection transistor and a plurality of second memory cells which are stacked above the semiconductor substrate; a plurality of word lines, each of which is commonly connected to control gates of one of the first memory cells and one of the second memory cells; and a control unit configured to perform programming and verification of data in the memory cells, wherein the control unit is configured to consecutively perform programming of data in a first page that includes one of the first memory cells and a second page that is connected to the same word line as the first page and includes one of the second memory cells, by turning on the first selection transistor and turning off the second selection transistor when programming data in the first page and then turning on the second selection transistor and turning off the first selection transistor when programming data in the second page, and then to consecutively perform verification of data in said first and second pages of the memory cells.