Patent ID: 9418949
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate comprising a non-device region and a device region, wherein no semiconductor electronic device is disposed in the non-device region; a dielectric layer on the non-device region and the device region; a dummy bonding pad on the dielectric layer of the non-device region; a first metal interconnect in the dielectric layer of the non-device region and directly connected to the dummy bonding pad, the first metal interconnect comprises a plurality of first top metal layers; a bonding pad on the dielectric layer of the device region; a second metal interconnect in the dielectric layer below the bonding pad of the device region, the second metal interconnect is not directly connected to the bonding pad, the second metal interconnect comprises a plurality of second top metal layers, a plurality of first voids are between a plurality of gaps between the first top metal layers and a plurality of second voids are in a plurality of gaps between the second top metal layers, and a number of the second voids is greater than a number of the first voids; a buffer layer between the bonding pad and the dielectric layer, wherein the buffer layer comprises a metal, metal nitride, or a combination thereof; and a redistribution layer on the dielectric layer, wherein the redistribution layer connects the dummy bonding pad and the bonding pad.