Patent ID: 9385076
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a passivation layer overlying a semiconductor substrate; an interconnect structure overlying the passivation layer; a protective layer overlying the interconnect structure and comprising a first opening and a second opening exposing portions of the interconnect structure, wherein the first opening is surrounded by the second opening, and the first opening is separated from the second opening by at least a portion of the protective layer, and the second opening is located closer to an edge of a landing pad region than the first opening; a barrier layer within the first opening and the second opening; and a continuous bump structure overlying the protective layer and electrically connected to the interconnect structure through the first opening and the second opening, wherein the continuous bump structure extends into at least one of the first opening or the second opening.