Patent ID: 9343498
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A semiconductor device manufacturing method comprising: a wafer stack manufacturing process of manufacturing a wafer stack in which a plurality of wafers comprising circuits and electrodes electrically connected to the circuits are stacked; and a dicing process of dicing the wafer stack, wherein the wafer stack manufacturing process comprises: a first wafer manufacturing process of manufacturing a resin film covering the plurality of circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the first holes to form a first wafer; a second wafer manufacturing process of manufacturing a resin film covering the plurality of circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and a wafer bonding process of causing respective electrode sides of the first wafer and the second wafer to be opposite to each other, bonding the respective resin films together by heating the resin film of the second wafer to a temperature higher than the glass transition point, and bonding the respective electrodes together to form a stack of the first wafer and the second wafer constituting at least a part of the wafer stack.