Patent ID: 9423455
Filing Date: 2016-08-23
CPC Classification: G01R

Claim Text:
1. A digital electronic circuit (DCCT) configured for testing in accordance with a segmented, random access scan (SRAS) Design-for-Test (DFT) technique comprises: the DCCT wherein a plurality of data storage cells in the DCCT comprise data storage cells having a random access back-door mechanism (SRAS scan cells); and a tree structure hierarchy of blocks, which hierarchy of blocks includes, at the top of the hierarchy, a top block (top scan group (TSG)) that interfaces highest circuit level scan pins to the SRAS scan cells, and, at the lowest level hierarchical block (a leaf scan group (LSG)), includes SRAS scan cells; wherein: blocks at the second level of the hierarchy (intermediate scan groups (ISGs)) interface to the LSGs and to a block at a higher level in the hierarchy (higher level ISG) or to the TSG; and higher level ISGs interface to ISGs and to an ISG at a still higher level in the hierarchy or to the TSG; a number of blocks at each level of the hierarchy below the TSG is a predetermined integer number; each LSG includes the predetermined integer number of SRAS scan cells; ISGs at the second level of the hierarchy interface to the predetermined integer number of LSGs and to an ISG at a higher level in the hierarchy or to the TSG; and ISGs above the second level of the hierarchy interface to the predetermined integer number of ISGs at a lower level in the hierarchy and to an ISG at a higher level in the hierarchy or to the TSG; and the DCCT implements multiple compression-decompression modes of operation wherein: an LSG, an ISG and a TSG have a functional mode of operation, a One Address (ON) mode of operation and one or more of the following modes of operation: an Address Increment (AI) mode of operation; a Test Bypass (TB) mode of operation; a Less Than or Equal Address (LE) mode of operation; a Greater Than Address (GT) mode of operation; and an All Except Address (AE) mode of operation.