Patent ID: 9461152
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first main electrode; a second main electrode; a first semiconductor region of a first conductivity type being in electrically contact with the first main electrode; a second semiconductor region of the first conductivity type being in electrically contact with the second main electrode; a third semiconductor region of a second conductivity type arranged between the first semiconductor region and the second semiconductor region, and separating the first semiconductor region and the second semiconductor region; and a depletion layer suppression region arranged inside of the third semiconductor region, and being configured to suppress a spread of a depletion layer extending in the third semiconductor region when a reverse bias voltage is applied between the second semiconductor region and the third semiconductor region, wherein the third semiconductor region comprises a shortest region where a distance between a first boundary surface and a second boundary surface is shortest, the first boundary surface being a boundary surface between the third semiconductor region and the first semiconductor region, and the second boundary surface being a boundary surface between the third semiconductor region and the second semiconductor region, and the shortest region includes a region where the depletion layer suppression region does not exist between the first boundary surface and the second boundary surface when the first boundary surface and the second boundary surface are viewed along a direction which connects the first boundary surface and the second boundary surface at a shortest distance from each other.