Patent ID: 9368194
Filing Date: 2016-06-14
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor integrated circuit, comprising; a first line provided with a power supply potential; a first P-channel transistor having a source electrode which is coupled to the first line and a gate electrode which is coupled to a first signal line; a second P-channel transistor having a source electrode which is coupled to the first line and a gate electrode which is coupled to a second signal line; a third P-channel transistor having a source electrode which is coupled to a drain electrode of the second P-channel transistor; a memory cell array which is coupled to a drain electrode of the first P-channel transistor and a drain electrode of the third P-channel transistor; and wherein first and second signals set the memory cell array to a first state when the first and second P-channel transistors are set to an on state.