Patent ID: 9265143
Filing Date: 2016-02-16
CPC Classification: H01L,H05K

Claim Text:
1. A logic gate array, comprising: a substrate; an array of first conductive lines with a plurality of first pads disposed on each of the first conductive lines, wherein the array of first conductive lines is disposed on the substrate in a first direction; an array of isolation lines extending in a second direction over the first conductive lines, wherein the isolation lines are not disposed on the first pads, and wherein orientation of the second direction is different than the orientation of the first direction; an array of second conductive lines with a plurality of second pads disposed on each of the second conductive lines, wherein the array of second conductive lines is disposed on the substrate in the second direction, and wherein each isolation line of the array of isolation lines bands only the geometry of a corresponding second conductive line of the array of second conductive lines; and conductive ink dots that sufficiently cover the intersection of selected first pads and selected second pads to electrically connect the corresponding first conductive lines and the second conductive lines to enable logic circuitry of the logic gate array.