Patent ID: 9378788
Filing Date: 2016-06-28
CPC Classification: G11C

Claim Text:
1. An apparatus, comprising: one or more bitlines; a write driver, coupled to the one or more bitlines, to drive at least one of the one or more bitlines in response to logical combinations of a write enable signal and a data signal; a bias capacitor coupled to the one or more bitlines and having an input terminal and an output terminal; and a multiplexer coupled with the output terminal and the one or more bitlines, wherein the multiplexer is to selectively couple the output terminal with one of the one or more bitlines in response to one or more of the data signal and an inverted version of the data signal, the bias capacitor to transfer charge between the input terminal and the output terminal to selectively drive the coupled one of the one or more bitlines to a negative voltage level in response to a drive signal, wherein the drive signal is coupled with the input terminal and is a delayed version of the write enable signal.