Patent ID: 9397868
Filing Date: 2016-07-19
CPC Classification: H03L,H04L

Claim Text:
1. An integrated circuit, comprising: an electrical contact adapted to receive an incoming data signal from a path external to the integrated circuit; circuitry operatively coupled to the electrical contact so as to receive the incoming data signal and equalize the incoming data signal using a first linear equalizer to generate a first output; circuitry operatively coupled to the electrical contact so as to receive the incoming data signal and equalize the incoming data signal using a second linear equalizer to generate a second output in parallel with the first output; and circuitry operatively coupled to the first output and to the second output to generate a clock therefrom; wherein the second output is equalized differently than the first output according to equalization characteristics respective to the first linear equalizer and the second linear equalizer; and wherein the circuitry to generate the clock comprises