Patent ID: 9299837
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a transistor channel region and having a first surface that is a substantially vertical sidewall surface, a second surface that extends from a bottom edge of the first surface at an angle upwardly towards to a first point beneath the transistor channel region, and a third surface that extends from the first point at an angle upwardly to a second point at a top surface of the crystalline semiconductor substrate beneath a spacer layer; depositing a layer of crystalline dielectric material onto a surface of the crystalline semiconductor substrate that is exposed within the recess, where the layer of crystalline dielectric material is comprised of at least one of a rare earth oxide or a combination of rare earth oxides, a Perovskite or an aluminum oxide or an aluminum oxide compound; and depositing channel region stressor material into the recess such that the layer of crystalline dielectric material is disposed between the channel region stressor material and the surface of the crystalline semiconductor substrate, where the channel region stressor material is deposited so as to at least surround the transistor channel region and is comprised of at least one of silicon, germanium, silicon germanium, carbon doped silicon, a silicon-germanium alloy and a compound semiconductor material.