Patent ID: 9235258
Filing Date: 2016-01-12
CPC Classification: G06F,G11C,Y02B,Y02D,Y02P

Claim Text:
1. A processor comprising: a first processor core to save at least a portion of a state of the first processor core to a cache memory and to enter a first sleep state in which the first processor core is powered off; a second processor core to save at least a portion of a state of the second processor core to the cache memory and to enter the first sleep state in which the second processor core is powered off, wherein a processor package including the first and second processor cores is to enter a package sleep state after the first and second processor cores enter the first sleep state; and the cache memory, wherein the cache memory is to be powered when the first and second processor cores are to be powered off, and the saved state of the first processor core and the saved state of the second processor core are to be restored when the first processor core and the second processor core transition to a mode in which the first processor core and the second processor core are to be powered on, respectively.