Patent ID: 9324574
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method of forming a pattern in a semiconductor device, the method comprising: sequentially forming a first hard mask layer and a second hard mask layer on an etching target layer comprising first and second regions; sequentially forming a third hard mask layer and a first spacer layer on the second hard mask layer; forming a third hard mask pattern layer by etching the third hard mask layer using the first spacer layer; forming a second hard mask pattern layer by etching the second hard mask layer using at least a portion of the third hard mask pattern layer; forming a second spacer layer on a sidewall of the second hard mask pattern layer; forming a first hard mask pattern layer by etching the first hard mask layer using the second spacer layer; and etching the etching target layer using the first hard mask pattern layer, wherein the third hard mask pattern layer remaining on the second hard mask pattern layer has a first thickness in the first region and has a second thickness in the second region, and the first thickness is different from the second thickness.