Patent ID: 9245599
Filing Date: 2016-01-26
CPC Classification: G11C

Claim Text:
1. An apparatus, comprising: a plurality of memory cells including a first memory cell connected to a first bit line and a second memory cell connected to a second bit line; one or more managing circuits configured to determine a first sensing time associated with the first memory cell and determine a second sensing time associated with the second memory cell; and a read circuit in communication with the first bit line and the second bit line, the read circuit configured to integrate a first current associated with the first bit line during the first sensing time and integrate a second current associated with the second bit line during the second sensing time, the read circuit configured to detect a first state of the first memory cell based on the integration of the first current and a reference voltage using a detection block during a first time period, the read circuit configured to detect a second state of the second memory cell based on the integration of the second current and the reference voltage using the detection block during a second time period subsequent to the first time period.