Patent ID: 9431485
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method for forming a finFET comprising: forming a dummy gate over a fin in a gate region of the finFET, wherein the dummy gate comprises a dummy dielectric layer in direct contact with the fin and a dummy material above the dummy dielectric layer; forming a gate spacer pair over the fin sandwiching the dummy gate, wherein the gate spacer pair is located above the fin in an intermediate region of the finFET, and wherein the intermediate region of the finFET is adjacent to the gate region of the finFET; forming a dummy spacer pair adjacent to the gate spacer pair, wherein the dummy spacer pair sandwiches the dummy gate and the gate spacer pair, and wherein the dummy spacer pair is located above the fin in the intermediate region of the finFET; forming an epi-layer above the fin in a source/drain region of the finFET, wherein the epi-layer is in direct contact with the dummy spacer pair and the source/drain region is adjacent to the intermediate region of the finFET; removing at least the dummy material to form a gate void; forming a replacement gate in the gate void, wherein forming the replacement gate comprises depositing a dielectric layer in the gate void and then depositing an electrode in the gate void; removing the dummy spacer pair after forming the replacement gate to form an implantation void; implanting at least one dopant through the implantation void and into the fin located in the intermediate region of the finFET; filling the implantation void with an insulating material to form an insulating layer; and activating the at least one dopant in the fin located in the intermediate region of the finFET.