Patent ID: 9368515
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A thin film transistor array panel, comprising: a channel layer comprising an oxide semiconductor and formed in a semiconductor layer; a source electrode formed in the semiconductor layer and connected to the channel layer at a first side of the channel layer; a drain electrode formed in the semiconductor layer and connected to the channel layer at a second side of the channel layer, opposing the first side; a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode; an insulating layer disposed on the channel layer; a gate line comprising a gate electrode disposed on the insulating layer; a passivation layer disposed on the source electrode, the drain electrode, the pixel electrode, and the gate line; and a data line disposed on the passivation layer, wherein a width of the channel layer is substantially equal to a width of the pixel electrode in a direction parallel to the gate line, wherein the source electrode, the channel layer, the drain electrode and the pixel electrode are disposed in a same plane extending in a straight line below the gate electrode, wherein the insulating layer covers the channel layer and does not extend beyond end portions of the channel layer, wherein the insulating layer is not overlapped with the source electrode, the drain electrode, and the pixel electrode, and wherein the source electrode and the drain electrode are not overlapped with the channel layer and the gate electrode.