Patent ID: 9417960
Filing Date: 2016-08-16
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A data storage system comprising: a host system; and a solid state drive (SSD) interfaced with the host system, the SSD including an SSD controller and at least one nonvolatile memory (NVM), the SSD controller including at least one SSD processor, a tier 1 error-correcting code (ECC) encoder/decoder, and a tier 2 ECC encoder/decoder, wherein the NVM includes at least a first flash memory having a plurality of flash memory cells, reference voltage range determination logic and tier 2 ECC decoding logic, the SSD controller receiving write data from the host system to be programmed into flash cells of the NVM, the write data comprising at least a first most significant bit (MSB) page of data and at least a first least significant bit (LSB) page of data, the tier 1 ECC encoder/decoder performing tier 1 ECC encoding of the first LSB page of data to produce a tier 1-encoded first LSB page of data, the tier 2 ECC encoder/decoder performing tier 2 ECC encoding of the tier 1-encoded first LSB page of data to produce a tier 1/tier 2-encoded first LSB page data, the SSD controller sending the tier 1/tier 2-encoded first LSB page of data to the first flash memory, the tier 1 ECC encoding/decoding logic performing tier 1 ECC encoding of the first MSB page of data to produce a tier 1-encoded first MSB page of data, the SSD controller sending the tier 1-encoded first MSB page of data to the first flash memory, the tier 1 ECC encoding and the tier 2 encoding being different types of encoding, the tier 2 decoding logic of the first flash memory being adapted to perform tier 2 decoding of LSB page data in the first flash memory.