Patent ID: 9496261
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. An integrated circuit having transistor devices of a plurality of device types formed on a substrate, comprising: a first screening layer for a first device type, the first screening layer being positioned below a first gate insulator of the first device type, the first screening layer having a first dopant concentration; a second screening layer for a second device type, the second screening layer being positioned below a second gate insulator of the second device type, the second screening layer having a second dopant concentration; a first substantially undoped layer for the first device type being positioned above and adjacent to the first screening layer; a second substantially undoped layer for the second device type being positioned above and adjacent to the second screening layer; a shallow trench isolation between the first device type and the second device type; a first source and drain region for the first device type penetrating the first substantially undoped layer and the first screening layer; a second source and drain region for the second device type penetrating the second substantially undoped layer and the second screening layer; and wherein a thickness of the first gate insulator is different from a thickness of the second gate insulator.