Patent ID: 9466022
Filing Date: 2016-10-11
CPC Classification: G06N

Claim Text:
1. A system comprising a computer processor, a computer-readable hardware storage device, and program code embodied with the computer-readable hardware storage device for execution by the computer processor to implement a method for simulating slowest and fastest neural dynamics of a neural model, the method comprising: maintaining neuronal states for multiple neurons in a memory device, wherein each neuron represents an instance of said neural model, and each neuronal state is expressed by one or more variables of said neural model; maintaining neuronal state transition information representing said slowest and fastest neural dynamics of said neural model in a delta-based lookup table, wherein said delta-based lookup table comprises a sequence of neuronal states, said delta-based lookup table further comprises, for each neuronal state of said sequence, corresponding state transition information identifying a subsequent neuronal state that said neuronal state transitions to, and said corresponding state transition information comprises a combination of bits including a first bit indicating whether an outgoing spike event is generated in said subsequent neuronal state and one or more additional bits representing one or more delta values for the one or more variables of said neural model; and updating a current neuronal state for a neuron based on one or more incoming spike events targeting said neuron and said delta-based lookup table, wherein said current neuronal state is a neuronal state of said sequence, said current neuronal state is updated to another neuronal state of said sequence in response to adding at least one delta value of said delta-based lookup table to said current neuronal state, and said at least one delta value is included in state transition information corresponding to said current neuronal state.