Patent ID: 9307121
Filing Date: 2016-04-05
CPC Classification: H04N

Claim Text:
1. A conversion circuit, comprising: a conversion section configured to convert each of analog pixel signals into digital pixel data; a timing acquisition section configured to acquire specified timing, the specified timing defining a display period in a cycle of a synchronization signal; a timing setting section configured to set timing in which the display period is extended to define an extended display period in the cycle of the synchronization signal without changing the cycle of the synchronization signal, wherein display of each of the analog pixel signals is performed during the extended display period and wherein the extended display period is longer than the display period, the timing being other than the specified timing; an enable signal generation section configured to generate an enable signal, the enable signal indicating the extended display period as a period during which the digital pixel data is valid; and an output section configured to output the digital pixel data that is valid, in accordance with the enable signal.