Patent ID: 9385894
Filing Date: 2016-07-05
CPC Classification: H04B,H04L

Claim Text:
1. A receiving circuit comprising: a first decision circuit configured to output, as boundary data, data obtained by performing a binary decision on an input data signal in synchronization with a first clock signal; a first decision feedback equalizer configured to output, as center data, data obtained by performing equalization and a binary decision on the input data signal using a first equalization coefficient in synchronization with a second clock signal; a phase detection circuit configured to detect phase information of the input data signal based on the boundary data and the center data; an equalization control circuit configured to receive a request signal and output an amplitude value of a data transition pattern of the input data signal in response to the request signal; a phase control circuit configured to output the request signal to the equalization control circuit, receive the amplitude value from the equalization control circuit and the phase information from the phase detection circuit and output phase difference information of the center data based on the amplitude value and the phase information; a first phase adjustment circuit configured to adjust a phase of the first clock signal in accordance with the phase information; and a second phase adjustment circuit configured to adjust a phase of the second clock signal in accordance with the phase information and the phase difference information.