Patent ID: 9355206
Filing Date: 2016-05-31
CPC Classification: G06F

Claim Text:
1. A system to support automatic functional coverage generation and management for an integrated circuit (IC) design protocol, comprising: a specification generation engine running on a host, which in operation, is configured to automatically generate one or more specifications for functional coverage of the IC design protocol based on inputs from an architect of the IC design protocol; a coverage validation engine running on a host, which in operation, is configured to validate the one or more specifications for the functional coverage and generate coverage data on reachable states at formal verification (FV) level; a coverage data collection engine running on a host, which in operation, is configured to conduct simulation of the IC design protocol and collect coverage data of reached coverage points at register-transfer level (RTL); and a coverage data analysis engine running on a host, which in operation, is configured to analyze and verify completeness of the functional coverage of the IC design protocol based on the coverage data collected at the formal verification level and at the RTL, respectively; wherein the IC design protocol is a directory-based cache coherence protocol, which connects a plurality of System-on-Chips (SOCs) as a single multicore processor via connections among the SOCs.