Patent ID: 9412707
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method of manufacturing stacked semiconductor packages, the method comprising: preparing a wafer substrate comprising a first surface in which an active area is formed and a second surface that is opposite to the first surface; forming a first through electrode extending by a predetermined length from the second surface toward the first surface; trimming an edge of the second surface in predetermined intervals and by a predetermined thickness, thereby forming a trimmed wafer substrate surface; forming a protection layer that covers the second surface and a first portion of the trimmed wafer substrate surface such that a second portion of the trimmed wafer substrate surface is exposed; forming an adhesive layer on a wafer carrier; attaching the wafer substrate and the protection layer on the adhesive layer such that the adhesive layer covers an upper surface and a side surface of the protection layer; exposing an upper portion of the first through electrode by grinding the first surface; stacking a plurality of semiconductor chips on the first surface, at least one of which is electrically connected to the first through electrode; forming a molding element to cover the first surface of the wafer substrate and the plurality of semiconductor chips, wherein a diameter of the molding element is greater than a diameter of the wafer substrate and less than respective diameters of the protection layer and the adhesive layer; and sequentially removing the wafer carrier and the adhesive layer.