Patent ID: 9235465
Filing Date: 2016-01-12
CPC Classification: G06F

Claim Text:
1. A system, comprising: a physical memory store comprising a plurality of cells, wherein one or more of the plurality of cells have permanent stuck-at faults; a write/read component that receives a plurality of bits to be written to the plurality of cells; a recursively determined invertible set (RDIS) component that identifies at least one stuck-at wrong (SA-W) cell from the plurality of cells that have permanent stuck-at faults based at least in part on values associated with the plurality of bits and at least one value associated with the at least one SA-W cell, wherein the RDIS component determines an invertible set that comprises the at least one SA-W cell; and an auxiliary information store that maintains a plurality of auxiliary counters that specify the invertible set, wherein the write/read component writes a bitwise complement to each cell in the invertible set and writes normally to each cell not in the invertible set, and wherein, upon a read operation, the write/read component reads a bitwise complement from each cell in the invertible set and reads normally from each cell not in the invertible set.