Patent ID: 9406398
Filing Date: 2016-08-02
CPC Classification: G09G,G11C,H01L,H03K

Claim Text:
1. A semiconductor device comprising a shift register circuit, the shift register circuit comprising: a first transistor; a second transistor; and a third transistor, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a gate electrode, a gate insulating film, and an oxide semiconductor layer, wherein the first transistor, the second transistor, and the third transistor are depletion-mode transistors, wherein one of a source and a drain of the first transistor is connected to one of a source and a drain of the second transistor, wherein a gate of the first transistor is connected to the other of the source and the drain of the first transistor, wherein one of a source and a drain of the third transistor is connected to a gate of the second transistor, wherein a first signal is input to a gate of the third transistor, and wherein an amplitude voltage of the first signal is greater than a potential difference between the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor.