Patent ID: 9281027
Filing Date: 2016-03-08
CPC Classification: G11C

Claim Text:
1. A memory device comprising: latching circuitry to receive a latching value and to provide said latching value as an output; a path to receive said latching value and to pass said latching value to said latching circuitry; first storage circuitry to provide a first stored value when said memory device is in a read mode of operation; a bit line connected to said first storage circuitry; first control circuitry to selectively connect said bit line to said path; sensing circuitry to, when an enable signal is active, detect a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and to output said latching value on said path, wherein said latching value is dependent on said voltage change; second storage circuitry to provide a second stored value when said memory device is in a test mode of operation; and second control circuitry to receive said second stored value and to selectively output said second stored value as said latching value on said path, wherein said latching circuitry is to output said latching value as said output in dependence on said enable signal, such that said enable signal controls both said latching circuitry and said sense circuitry.