Patent ID: 9286222
Filing Date: 2016-03-15
CPC Classification: G06F,Y02D

Claim Text:
1. A data processing apparatus comprising: first processing circuitry and second processing circuitry, where both circuitries are configured to perform a processing workload such that the processing workload is performed by one of the first processing circuitry and the second processing circuitry at a time; power control circuitry for independently controlling power supply to the first processing circuitry and the second processing circuitry; a workload transfer controller configured to be responsive to a transfer stimulus to initiate a transfer of performance of the processing workload from a source processing circuitry to a destination processing circuitry prior to the source processing circuitry being placed in a power saving condition by the power control circuitry, the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry; wherein: at least the source processing circuitry has a cache; the power control circuitry is configured, following said transfer, to maintain at least the cache of the source processing circuitry in a powered condition during a snooping period following the start of performance of the transferred processing workload by the destination processing circuitry; cache snooping circuitry is configured, during the snooping period, to snoop data values in the cache of the source processing circuitry and to retrieve the snooped data values for the destination processing circuitry; and the power control circuitry is configured to place said at least the cache of the source processing circuitry in the power saving condition following the end of the snooping period, the power saving condition is a condition in which the cache of the source processing circuitry is not accessed by the cache snooping circuitry, wherein the snooping period ends on the occurrence of any one of a plurality of predefined snoop stop events, and wherein the any one of the plurality of predefined snoop stop events is based on at least one of: (i) a number of snoops performed by the cache snooping circuitry, (ii) a predetermined number of processing transactions of a predetermined type following said transfer, (iii) a predetermined number of processing cycles after the destination processing circuitry starts performing the transferred processing workload, (iv) a particular memory region of a shared memory is accessed for the first time by the destination processing circuitry after starting performance of the transferred processing workload, (v) a particular memory region of the shared memory, which was accessed by the destination processing circuitry for an initial period after starting performance of the transferred processing workload, is not accessed by the destination processing circuitry for a predetermined period, and (vi) the destination processing circuitry writing to a predetermined memory location of the shared memory for the first time after starting performance of the transferred processing workload.