Patent ID: 9460649
Filing Date: 2016-10-04
CPC Classification: G06T,G09G

Claim Text:
1. A timing controller, applied in a panel display system, the timing controller being coupled between a display controller and a display panel, the timing controller comprising: an image signal receiver, configured to receive an image signal outputted from the display controller; an overdrive circuit, configured to receive the image signal, and to generate a converted image signal according to successive first frame data and second frame data in the image signal; an image signal transmitter, configured to receive the converted image signal outputted from the overdrive circuit and to transmit the converted image signal to the display panel; a memory; and a memory interface unit; wherein, in a normal read/write period, the memory interface unit receives the first frame data outputted from the overdrive circuit and stores the first frame data in the memory, and when the overdrive circuit receives the second frame data in the image signal, the memory interface unit fetches the first frame data from the memory according to a preferred delay phase and transmits the first frame data to the overdrive circuit; and in a memory calibration period, the memory interface unit adjusts a delay phase of a reference clock a number of times, accordingly samples a read signal outputted from the memory to obtain a plurality of sampling results, and determines the preferred delay phase according to the sampling results.