Patent ID: 9423457
Filing Date: 2016-08-23
CPC Classification: G01R,G11C

Claim Text:
1. A built-in self-test system for use in circuitry having two or more delay locked loops (DLLs), comprising: a first DLL having a first delay input, a first clock input disposed to receive a clock input signal and a first clock output providing a first clock output signal delayed in comparison with the clock input signal; a second DLL having a second delay input, a second clock input disposed to receive the clock input signal and a second clock output providing a second clock output signal delayed in comparison with the clock input signal; a test controller provides a first delay amount over the first delay input of the first DLL to create a start offset between the first clock output signal and the second clock output signal and further provides at least one common delay amount to both the first delay input of the first DLL and the second delay input of the second DLL, wherein the at least one common delay amount modifies delays of the first clock output signal and second clock output signal; a sample component that creates a test dataset by sampling the second clock output signal from the second DLL during at least one edge of the first clock output signal from the first DLL, wherein the test dataset stores samples of the second clock output signal; and a compare component that performs a comparison of the test dataset with a comparison dataset and produces a comparison result from the comparison of the test dataset and comparison dataset, wherein the comparison result indicates if the first DLL is functioning properly or is not functioning properly, and wherein the comparison dataset comprises data that is expected when comparing the first clock output signal from the first DLL with the second clock output signal from the second DLL.