Patent ID: 9419134
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. An integrated circuit device comprising: a semiconductor substrate comprising a first portion in a first device region and a second portion in a second device region; a first semiconductor strip in the first device region; a second semiconductor strip in the second device region; a first dielectric liner comprising an edge contacting a sidewall of the first semiconductor strip, wherein the first dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip; and a first Shallow Trench Isolation (STI) region over the first dielectric liner, wherein a sidewall and a bottom surface of the first STI region is in contact with a sidewall and a top surface of the first dielectric liner, respectively, with the top surface being directly underlying the first STI region, and the first STI region comprises: