Patent ID: 9424100
Filing Date: 2016-08-23
CPC Classification: G06F,H04W

Claim Text:
1. A method for monitoring the coordinated execution of sequenced tasks by an electronic device comprising a main electronic card comprising at least one main processor synchronized to a main clock of main time period and at least one auxiliary electronic card comprising at least one auxiliary processor synchronized to an auxiliary clock of auxiliary time period, the auxiliary clock being faster than the main clock, the sequenced tasks having to be carried out simultaneously by the processors, the method comprising: executing, by the at least one main processor and over a determined main time period, a first sequenced task while the at least one auxiliary processor executes instructions of the first sequenced task over a plurality of auxiliary time periods; executing, by the at least one main processor and over the consecutive main time period, a second sequenced task; emitting, by the at least one main processor, a coordination marker to the at least one auxiliary processor at the start of each main time period; emitting, by the at least one auxiliary processor, a response word formed on the basis of the last coordination marker received to the main processor at the end of each auxiliary time period; validating, by the at least one main processor, the response word received with respect to the first coordination marker emitted, wherein the validating is carried out at the start of the consecutive time period before the emission of a new coordination marker; and signaling, by the at least one main processor, if the response word received is not valid so as to signal a defect of coordination of the at least one auxiliary processor,