Patent ID: 9385096
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor chip comprising a main face which includes a pair of long sides parallel to each other and a pair of short sides orthogonal to said pair of long sides; a plurality of first bumps arrayed in a first bump placement region of said semiconductor chip, said first bump placement region being positioned along one of said pair of long sides; a plurality of second bumps arrayed in a second bump placement region of said semiconductor chip, said second bump placement region being positioned along an other of said pair of long sides; a plurality of first power lines disposed in a region between said first bump placement region and said second bump placement region, said plurality of first power lines extending, in a direction parallel to said pair of long sides, between opposing edges of the first bumps and the second bumps; and a plurality of third bumps, located between the first bumps and the second bumps, integrated on said semiconductor chip, and arrayed in a third bump placement region of said semiconductor chip, the third bump placement region being different from said first bump placement region and said second bump placement region, wherein each of said plurality of third bumps provides short-circuiting of said plurality of first power lines.