Patent ID: 9324441
Filing Date: 2016-04-26
CPC Classification: G11C

Claim Text:
1. A non-volatile memory circuit, comprising: an array of non-volatile memory cells connected along bit lines; a data bus; read/write/erase circuitry connected to the array, including data latches connectable to the bit lines and data bus for transfer of data between the data bus and the array; registers for storing operating parameters; and control circuitry connected to the read/write/erase circuitry, wherein, in response to receiving a specified command sequence including a set of operating parameters, the memory circuit loads the received set of operating parameters into the data latches and subsequently transfers the received set of operating parameters from the data latches to the registers prior to executing by the read/write/erase circuitry of a subsequent portion of the specified command sequence using the received set of operating parameters.