Patent ID: 9269669
Filing Date: 2016-02-23
CPC Classification: C23C,H01L

Claim Text:
1. A method for forming a device, the process comprising: depositing a resist layer over an insulator on a substrate; forming openings for metal interconnects in the resist layer; forming a first metal interconnect in a first region, a second metal interconnect and a third metal interconnect in a second region, and a fourth metal interconnect in a third region, by depositing a metal comprising copper within the openings using a pattern plating process; removing the resist layer after depositing the metal; forming a further metal layer comprising a further metal as a blanket layer over the substrate using a plasma vapor deposition process over and contacting the metal comprising copper, the further metal comprising a material selected from Ti, Hf, Nb, Zr, Ru, Rh, and Ir; forming a silicon oxide or silicon nitride layer covering the further metal layer in the second region; converting all of the further metal layer in the first region and the third region to form an oxide of the further metal layer without converting the underlying metal comprising copper; forming a silicon nitride layer over the first, the second, the third, and the fourth metal interconnects, the silicon nitride layer covering the oxide of the further metal layer in the first region, the silicon oxide or silicon nitride layer in the second region; forming a first metal via within the silicon nitride layer, the first metal via contacting the oxide of the further metal layer in the first region; forming a second metal via within the silicon nitride layer, the second metal via contacting the fourth metal interconnect in the third region; and forming a fifth metal interconnect and a sixth metal interconnect over and contacting the silicon nitride layer, wherein the fifth metal interconnect contacts the first metal via and the sixth metal interconnect contacts the second metal via, wherein the first metal interconnect, the oxide of the further metal layer in the first region, and the first metal via form a MIM capacitor, wherein the further metal layer covered by the silicon oxide or silicon nitride layer in the second region forms a resistor, and wherein the second metal via forms an electrical contact to the fourth metal interconnect.