Patent ID: 9252765
Filing Date: 2016-02-02
CPC Classification: G11C,H03K

Claim Text:
1. A circuit, comprising: a thin-oxide PMOS transistor having a source and a switched n-well; a native thick-oxide NMOS transistor having a gate controlled responsive to a control signal, a drain coupled to a low-voltage supply configured to provide a low voltage, and a source coupled to the thin-oxide PMOS transistor's source and switched n-well; and a thick-oxide PMOS transistor having a gate controlled responsive to the control signal, a source coupled to a high-voltage supply configured to provide a high voltage that is greater than the low voltage, and a drain coupled to the thin-oxide PMOS transistor's source and switched n-well, wherein the native thick-oxide NMOS transistor and the thick-oxide PMOS transistor each have a first gate-oxide thickness that is greater than a second gate-oxide thickness for the thin-oxide PMOS transistor.