Patent ID: 9230046
Filing Date: 2016-01-05
CPC Classification: G06F

Claim Text:
1. A method of generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate defined operations of a device-under-test (DUT), the DUT including multiple device clocks generating multiple device clock signals for operating the DUT at multiple device frequencies, said multiple device frequencies having a defined frequency ratio, the method comprising: mapping the defined operations of the DUT to the FPGA based hardware accelerator, the FPGA based hardware accelerator including multiple accelerator clocks generating multiple accelerator clock signals to operate said FPGA based hardware accelerator to simulate the defined operations of the DUT; and generating the accelerator clock signals of the FPGA based hardware accelerator at multiple accelerator frequencies, said multiple accelerator frequencies having said defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA based hardware accelerator.