Patent ID: 9281807
Filing Date: 2016-03-08
CPC Classification: H03K

Claim Text:
1. A master-slave flip-flop implemented in an integrated circuit, the master-slave flip-flop comprising: a master latch coupled to receive data at an input; a first inverter coupled to an output of the master latch; a slave latch comprising a first slave latch inverter, a second slave latch inverter, a third slave latch inverter and a fourth slave latch inverter, wherein an output of the first inverter is coupled to a first slave latch inverter output of the first slave latch inverter and a third slave latch inverter output of the third slave latch inverter, and the input of the master latch is coupled to a second slave latch inverter output of the second slave latch inverter and a fourth slave latch inverter output of the fourth slave latch inverter; and a second inverter coupled to an output of the slave latch at the second slave latch inverter output and the fourth slave latch inverter output.