Patent ID: 9312003
Filing Date: 2016-04-12
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: a plurality of first lines; a plurality of second lines extending to intersect the first lines; a plurality of memory cells respectively disposed at intersections of the first lines and the second lines and including a variable resistance element; and a control circuit configured to control a voltage applied to the memory cells, the control circuit being configured able to, during a setting operation that changes the memory cell to a set state, execute the setting operation such that a setting voltage is applied to a selected memory cell connected to a selected first line and a selected second line, and the control circuit being configured able to change a voltage application time of the setting voltage according to a state of change of the selected memory cell during the setting operation to execute an additional setting operation that applies the setting voltage to the selected memory cell, wherein the control circuit comprises a current detection circuit configured to compare a cell current flowing in the selected memory cell during the setting operation and a threshold value current, and a timer configured to determine a time until the cell current reaches the threshold value current, and the control circuit is configured to execute the setting operation and the additional setting operation continuously and change the voltage application time of the additional setting operation based on the time until the cell current reaches the threshold value current.