Patent ID: 9257191
Filing Date: 2016-02-09
CPC Classification: G11C,H01L

Claim Text:
1. A method for operating a memory device, comprising: performing a plurality of erase-verify iterations for a set of memory cells connected to a set of word lines until a verify test is passed by the set of memory cells, each memory cell of the set of memory cells comprises a charge-trapping material, the verify test determines whether memory cells of the set of memory cells have a threshold voltage which is below a verify voltage, and the set of memory cells has a threshold voltage distribution when the verify test is passed by the set of memory cells; and after the verify test is passed by the set of memory cells, biasing the set of memory cells to cause a lower tail of the threshold voltage distribution to move lower, the biasing the set of memory cells comprises providing a positive control gate-to-drain voltage for each memory cell in the set of memory cells.