Patent ID: 9252081
Filing Date: 2016-02-02
CPC Classification: G06F,G11C,H01L

Claim Text:
1. A semiconductor device comprising: a plurality of memory chips arranged in a stacked arrangement, wherein each of the memory chips includes a plurality of memory banks and a plurality of data buses each transferring data to/from an associated one of the memory banks, and a plurality of penetration electrodes penetrating through the memory chip and each transferring the data to/from an associated one of the data buses; wherein the plurality of memory chips are configured to receive an address signal in common, the address signal indicating an address value, and wherein the plurality of memory chips includes a first memory chip and a second memory chip, the first and second memory chips being configured to be simultaneously selected based on the address value, and wherein each of the first and second memory chips are configured to transfer the data by corresponding penetration electrodes in parallel when simultaneously selected.