Patent ID: 9377833
Filing Date: 2016-06-28
CPC Classification: G06F,Y02D

Claim Text:
1. A power management method for use in an electronic system, wherein the electronic system comprises a processor, and a power management unit, the power management method comprising: when the processor has entered a low power state and an awakening event of the processor occurs, calculating by the power management unit a staying time from the time point the processor entered the low power state till the time point the awakening event occurs, wherein an operation voltage of the processor is at a first voltage level in the low power state; when the processor starts to exit the low power state according to the awakening event, determining by the power management unit a wait time, during which the operation voltage of the processor is recovered to a second voltage level of a working state from the first voltage level, according to the calculated staying time, wherein the first voltage level is lower than the second voltage level, and wherein the determining operation further comprises: dividing the calculated staying time into a plurality of levels; and mapping the calculated staying time to the wait time according to one of the levels corresponding to the calculated staying time.