Patent ID: 9367516
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A circuit arrangement for a data processing system comprising: a plurality of modules configured to process data independently and in parallel with other modules of the plurality of modules, the data having a time base and a base given by a first physical variable, the plurality of modules at least including: a phase locked loop configured to (i) determine a time interval until a next expected sensor value from a sequence of sequential sensor values, the sensor values being received from a sensor that measures the first physical variable, and (ii) distribute a defined number of pulses over the time interval; a time-base unit having a time-based counter and a position-based counter, the time-base unit being configured to (i) provide the time base, (ii) count the pulses from the phase locked loop, (iii) estimate values for the first physical variable at the pulses, and (iv) provide the estimated values for the first physical variable as the base given by the first physical variable; and a central routing unit connected to the plurality of modules, the central routing unit being configured to route the data cyclically between each module of the plurality of modules.