Patent ID: 9342643
Filing Date: 2016-05-17
CPC Classification: G06F

Claim Text:
1. A non-transitory computer readable medium storing a timing analysis program causing a computer to execute, comprising: storage processing of storing circuit information of a circuit to be analyzed and to be fabricated as a semiconductor integrated circuit, timing constraint information defining timing constraints on the circuit to be analyzed, delay information defining a plurality of delay values associated with a plurality of cells constituting the circuit to be analyzed, and delay upper limit information including at least one delay upper limit for setting an upper limit to the plurality of delay values associated with the plurality of cells into a storage unit, the storage processing being executed on the computer including a processor; delay value change processing of changing, at least one of the plurality of delay values associated with the plurality of cells to the delay upper limit, to provide a changed delay upper limit, the delay value change processing being executed on the computer; analysis processing of analyzing timing of the circuit to be analyzed by estimating a slack value using the changed delay upper limit in addition to the circuit information, the timing constraint information, and the delay information, the analysis processing being executed on the computer; and a delay upper limit setting processing of retrieving the circuit information of the circuit to be analyzed, and setting a value calculated by applying a calculated average to a cell with highest driving capability for each function of the plurality of cells as the delay upper limit set for each function of the plurality of cells.