Patent ID: 9236436
Filing Date: 2016-01-12
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate having a main surface having an element formation region at a center of the semiconductor substrate; a plurality of guard ring electrodes formed on said main surface of said semiconductor substrate to surround a circumference of said element formation region when said plurality of guard ring electrodes and said element formation region is viewed from a plan view; a plurality of guard rings formed in said main surface of said semiconductor substrate and electrically connected, respectively, to said plurality of guard ring electrodes; a channel stopper electrode formed on said main surface of said semiconductor substrate to be located outside of said plurality of guard ring electrodes when said channel stopper electrode and said plurality of guard ring electrodes are viewed in the plan view; a channel stopper region formed in said main surface of said semiconductor substrate and electrically connected to said channel stopper electrode; and a field plate disposed over and insulated from said semiconductor substrate, said field plate including a first portion disposed to surround a circumference of an outermost guard ring electrode of the plurality of guard ring electrodes when said first portion and the plurality of guard ring electrodes are viewed from the plan view, said field plate including a second portion located between said main surface of said semiconductor substrate and the outermost guard ring electrode, and a third portion located between said main surface of said semiconductor substrate and said channel stopper electrode, said second portion having a portion overlapping with the outermost guard ring electrode when viewed in a cross-section view, said third portion having a portion overlapping with said channel stopper electrode when viewed in the cross-section view.