Patent ID: 9247644
Filing Date: 2016-01-26
CPC Classification: H05K

Claim Text:
1. A wiring substrate, comprising: an insulating layer having a first surface formed with a first recess portion; a pad that is embedded in the first recess portion, the pad including a solder resist layer that is provided on the first surface of the insulating layer and that is formed with an opening portion through which the second recess portion is exposed, wherein an adjacent portion of the solder resist layer to a peripheral portion of the opening portion (i) surfaces of the pad including the second surface of the pad and being in contact with the insulating layer and (ii) the peripheral portion of the third surface of the pad are roughened surfaces, the first surface of the insulating layer is a roughened surface, and an adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.