Patent ID: 9454049
Filing Date: 2016-09-27
CPC Classification: G02F,G09G,G11C,H01L

Claim Text:
1. A method of manufacturing a substrate for a display device, comprising: forming a gate pattern on a base substrate having a display region and a driving circuit region, the gate pattern comprising a gate line, gate electrodes of switching transistors in the display region, gate electrodes of driving transistors in the driving circuit region and a main wiring in the driving circuit region; forming a gate insulation layer on the base substrate on which the gate pattern is formed; forming an active layer pattern and a data pattern on the gate insulation layer, the data pattern comprising a data line, drain and source electrodes of the switching transistors in the display region, drain and source electrodes of the driving transistors in the driving circuit region, and a branch wiring extended from one of the drain and source electrodes of the driving transistors; forming a passivation layer on the base substrate; forming a plurality of contact holes, the contact holes comprising a first contact hole through the passivation layer and the gate insulation layer, the first contact hole exposing a portion of the main wiring, and a second contact hole through the passivation layer, the second contact hole exposing a portion of the branch wiring; and forming an electrode pattern on the passivation layer, the electrode pattern comprising a pixel electrode electrically connected to one of the drain electrodes of the switching transistors, and a first connecting electrode connecting the main wiring and the branch wiring through the first and second contact holes.