Patent ID: 9361988
Filing Date: 2016-06-07
CPC Classification: G11C,H01L

Claim Text:
1. A nonvolatile semiconductor memory device comprising: a first memory cell; a second memory cell above the first memory cell; a third memory cell above the second memory cell; a first word line electrically connected to a gate of the first memory cell; a second word line electrically connected to a gate of the second memory cell; a third word line electrically connected to a gate of the third memory cell; and a control unit configured to perform an erasing operation on the first memory cell, the second memory cell, and the third memory cell, wherein during the erasing operation, the control unit applies a first voltage to the first word line, a second voltage different from the first voltage to the second word line, and a third voltage different from both the first voltage and the second voltage to the third word line.