Patent ID: 9525576
Filing Date: 2016-12-20
CPC Classification: H03L,H04L

Claim Text:
1. An apparatus, comprising: a phase-locked loop (PLL) filter of a read channel comprising a filter portion having an input coupled to delay circuitry having an output, the input of the filter portion configured to receive a phase error signal; a look-up table coupled to the filter portion, the look-up table comprising phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes, the look-up table configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal; and the PLL filter configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient; wherein a phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry, the filter portion comprises a low pass filter configured to receive the phase error signal, and an output of the low pass filter is coupled to an input of the look-up table.