Patent ID: 9263592
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A transistor, comprising: source/drain electrodes provided on a substrate; a semiconductor oxide layer provided between the source/drain electrodes; a gate electrode facing the semiconductor oxide layer; and a gate insulating layer interposed between the semiconductor oxide layer and the gate electrode, wherein the semiconductor oxide layer has a nano-layered structure including at least one first nano layer comprised of a first material and at least one second nano layer comprised of a second material that are alternatingly stacked one on another to provide at least one interface, wherein the first material and the second material are different materials that are effective to form an electron transfer channel layer at the interface, and wherein the at least one first nano layer and the at least one second nano layer have an interface there between which interface has at least one of a dangling bond and an incomplete atom coordination.