Patent ID: 9344408
Filing Date: 2016-05-17
CPC Classification: G06F,H04L

Claim Text:
1. A method for formal verification of a digital circuit comprising: extracting a proof problem from data representing a register-transfer level functionality of the digital circuit with a local processor by removing timing aspects from data representing the register-transfer level functionality of the digital circuit; reducing said proof problem to proof relevant data by removing all signals that are not inputs or states of the digital circuit; anonymizing with a translation table and encrypting said reduced proof problem; transmitting said anonymized and encrypted reduced proof problem to a remote server; decrypting said anonymized and encrypted reduced proof problem at said remote server; storing said anonymized reduced proof problem in a memory at said remote server; running a proof for verification of the design of the digital circuit on said anonymized reduced proof problem at said remote server to generate an anonymized proof result; encrypting said anonymized proof result at said remote server; transmitting said anonymized and encrypted proof result to said local processor; de-anonymizing and decrypting said anonymized and encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using the inputs and the states from said de-anonymized and decrypted proof result.