Patent ID: 9509438
Filing Date: 2016-11-29
CPC Classification: H04L,H04N,Y02D

Claim Text:
1. A network controller, comprising: physical interface (PHY) circuitry comprising transmitter circuitry configured to transmit data frames to a link partner in communication with the transmit circuitry over a channel link; link speed cycling circuitry configured to, upon initialization of the PHY circuitry, cause the transmitter circuitry to transmit the data frames to the link partner using at least one high rate link speed, the data frames including at least one first high rate (HR) bit sequence modulated with a first low rate bit stream; and equalization presets cycling circuitry configured to apply at least one equalization preset setting to the transmitter circuitry based in part on the at least one modulated first HR bit sequence while the transmitter circuitry is transmitting the data frames to the link partner; wherein the link speed cycling circuitry is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed; wherein the transmitter dwell time period is sufficient to allow the link partner to lock on to the transmitted data frames.