Patent ID: 9229719
Filing Date: 2016-01-05
CPC Classification: G06F

Claim Text:
1. A system comprising: a memory controller; a graphics controller; a network controller; and a processor coupled to the memory controller, the processor comprising: multiple levels of cache, including a level 1 (L1) cache; a plurality of registers, including a first register to store a plurality of control bytes and one or more second registers to store a plurality of byte values of a table; an instruction decoder to decode instructions including a Single Instruction Multiple Data (SIMD) instruction to perform a table lookup, the SIMD instruction to identify the first register, the one or more second registers, and a destination register; and an execution unit coupled to the instruction decoder and the plurality of registers, the execution unit to store a resultant in the destination register in response to the SIMD instruction, wherein for each control byte including a set to zero value in a most significant field, a zero is to be stored in a corresponding byte of the resultant, and for each control byte not including a set to zero value in a most significant field, a byte value from a position in the one or more second registers indicated by the control byte is to be stored in a corresponding byte of the resultant.