Patent ID: 9348539
Filing Date: 2016-05-24
CPC Classification: G11C

Claim Text:
1. A method for processing data in a hybrid memory system, the method comprising: providing a hybrid memory system comprising: determining, by the processor, an address of a target data page from the plurality of second memory modules; determining, by the processor, an index of a target buffer destination in an SRAM buffer provided in the NMP module; initiating, by the processor, transfer of the target data page to the target buffer destination via writing to control and status registers provided in the MSC module; and updating, by the processor, a data status related to the target data page and the target buffer destination in the control and status registers using the HMB module; retrieving, by the HMB module, sixteen 4-byte data or eight 8-byte data from one or more data pages from the plurality of first or second memory modules; combining, by the HMB module, the sixteen 4-byte data or eight 8-byte data into a single 64-byte data; and determining, by the HMB module, an ECC (Error Correcting Code) parity for the single 64-byte data.