Patent ID: 9244870
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. A semiconductor memory system comprising: semiconductor memories; and a memory controller configured to control the semiconductor memories, wherein each of the semiconductor memories is configured to execute an internal sequence including operations and have a wait period after an end of each of the operations, to issue, during the wait period, a status signal that is issued during every wait period to indicate that a corresponding semiconductor memory is in the wait period and which notifies in advance a start of a next operation, to the memory controller, and to start the next operation upon receiving a restart instruction of the internal sequence from the memory controller, the next operation being one of a program operation, a verify operation, a read operation and an erase operation, and the memory controller is configured to issue, upon receiving the status signal from a first semiconductor memory of the semiconductor memories, the restart instruction to the first semiconductor memory, on condition that a peak period of current of the next operation of the first semiconductor memory does not overlap with a peak period of current of a second memory of the semiconductor memories excluding the first semiconductor memory.