Patent ID: 9520485
Filing Date: 2016-12-13
CPC Classification: G11C,H01L

Claim Text:
1. A memory device, comprising: first and second multilayer stacks of conductive strips; a plurality of active pillars between the first and second stacks, each active pillar comprising a vertical channel structure, a charge storage layer and an insulating layer, the insulating layer in a frustum of an active pillar contacting a first edge of a first conductive strip in a layer of the first stack and a second edge of a second conductive strip in a same layer of the second stack; isolation pillars separating adjacent active pillars between the first and second stacks, wherein the isolation pillars contact the adjacent active pillars along arcuate edges; a bounded conductive layer configured as a common source of reference potential, below and in electrical communication with the plurality of active pillars; and a source line conductor over the first and second stacks, and an interlayer connector adjacent the first and second stacks, and connecting the source line conductor to the bounded conductive layer below the first and second stacks.