Patent ID: 9354474
Filing Date: 2016-05-31
CPC Classification: G02F

Claim Text:
1. An array substrate comprising a plurality of pixel units, each of the pixel units including a thin film transistor and an insulating layer, wherein at least two first pixel electrodes and at least two first common electrodes are disposed on an upper surface of the insulating layer, at least two second pixel electrodes and at least two second common electrodes are disposed on a lower surface of the insulating layer, the at least two second common electrodes are aligned to the at least two first pixel electrodes respectively, the at least two second pixel electrodes are aligned to the at least two first common electrodes respectively, wherein the at least two first pixel electrodes and the at least two second pixel electrodes are electrically connected through a pixel electrode connecting line and at least two first through hole vias disposed above the pixel electrode connecting line, the at least two first common electrodes and the at least two second common electrodes are electrically connected through a common electrode connecting line and at least two second through hole vias disposed above the common electrode connecting line, wherein, vertical projections of the pixel electrode connecting line and the common electrode connecting line on the upper surface of the insulating layer do not overlap, and vertical projections of all the first and second pixel electrodes and all the first and second common electrodes on the upper surface of the insulating layer are located between the vertical projections of the pixel electrode connecting line and the common electrode connecting line on the upper surface of the insulating layer.