Patent ID: 9262165
Filing Date: 2016-02-16
CPC Classification: G06F

Claim Text:
1. A vector processor, comprising: an instruction fetching unit configured to acquire an instruction from memory to perform an operation on an element data column; a decoding/issuing unit configured to decode the acquired instruction and issuing the decoded instruction in a cycle unit; an operation group configured to include a plurality of operation units each processing the issued instruction; and a register configured to store the element data column in consecutive addresses, wherein the plurality of operation units include a first operation unit which processes a first type instruction and a second operation unit which processes a second type instruction in addition to the first type instruction; and when a plurality of divided instructions, for which the element data of an instruction to be issued has been divided, are processed by the second operation unit, in a case where the second type instruction is not present in an instruction subsequent to the instruction to be issued, the decoding/issuing unit issues the divided instructions, and in a case where the second type instruction is present, the decoding/issuing unit issues the instruction to be issued without performing division.