Patent ID: 9442801
Filing Date: 2016-09-13
CPC Classification: G06F

Claim Text:
1. A device comprising: a first error corrector to perform platform error correction based on striding through a memory array of a memory according to a stride length, wherein the device is to interface with the memory that includes a second error corrector that is to perform on-memory error correction; a controller interfaced with the first error corrector to provide a disable indication to the second error corrector to turn off error checking, in response to an error indication by the second error corrector of encountering an error that is uncorrectable by the second error corrector, wherein the first error corrector is to correct the error using platform error correction, and wherein the controller is to provide an enable indication to the second error corrector to turn on error checking; wherein the stride length of the first error corrector is greater than a first codeword size of a cacheline of the platform error correction, and wherein the stride length is to correspond to a multiple of a second codeword size of the on-memory error correction of the second error corrector; and wherein, in response to the error indication, the first error corrector is to reduce the stride length, and perform a detailed scrub to isolate a location of the error within the cacheline.