Patent ID: 9361118
Filing Date: 2016-06-07
CPC Classification: G06F

Claim Text:
1. A method comprising: receiving a portion of program code, the portion having a first thread and a second thread; identifying a store memory event associated with the first thread and a load memory event associated with the second thread, wherein the store memory event and the load memory share a same variable; and determining, in accordance with a memory consistency model, when a program is heterogeneous-race-free due to a release synchronization event associated with the first thread and an acquire synchronization event associated with the second thread, the memory consistency model having a property of scope order, scope inclusion, scope transitivity or combination thereof, wherein the determining in accordance with the memory consistency model includes determining a correctness with regard to an ordering in program code of the release synchronization event and the acquire synchronization event and wherein the properties of the scope order, scope inclusion, and scope transitivity are defined based upon a capability of a system on which program code is being executed.