Patent ID: 9252044
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A method of fabricating a fin field effect transistor (FinFET) device including both shallow and deep shallow trench isolation (STI) regions, the method comprising: forming a deep STI region adjacent to a first side of an end fin among a plurality of fins; lining the deep STI region, including the first side of the end fin, with a passivation layer; depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin; etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap extending from a sidewall of the STI oxide to the first side of the end fin, the gap being located directly between the sidewall of the STI oxide and the first side of the end fin; and depositing gate material, the gate material covering the gap.