Patent ID: 9245796
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A method of fabricating an interconnection structure, the method comprising: sequentially stacking a first dielectric layer and a second dielectric layer on a semiconductor substrate; patterning the second dielectric layer to form a first recession region including a first nest-shaped recession region having a first width, a third nest-shaped recession region having a fifth width, and a first line-shaped recession region having a second width, which is less than the first and fifth widths, wherein the first line-shaped recession region is connected to the first nest-shaped recession region and spaced apart from the third nest-shaped recession region; forming a guide spacer layer on sidewalls of the first recession region to provide a second recession region in the first recession region, wherein the second recession region includes a second nest-shaped recession region disposed in the first nest-shaped recession region to have a third width that is less than the first width, and a fourth nest-shaped recession region disposed in the third nest-shaped recession region to have a sixth width that is less than the fifth width; forming a self-assembling block copolymer material that fills the second and fourth nest-shaped recession regions; annealing the self-assembling block copolymer material to form a circular pillar-shaped polymer block domain and a cylinder-shaped polymer block matrix, surrounding the circular pillar-shaped polymer block domain, in each of the second and fourth nest-shaped recession regions; removing the circular pillar-shaped polymer block domains; etching the guide spacer layer exposed by the cylinder-shaped polymer block matrixes to form a first via cavity in the second nest-shaped recession region and a third via cavity in the fourth nest-shaped recession region; and etching the first dielectric layer exposed by the first and third via cavities to form a second via cavity, which is deeper than the first via cavity, and a fourth via cavity, which is deeper than the third via cavity.