Patent ID: 9472507
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. An array substrate comprising: a substrate; a barrier layer disposed on the substrate; a buffer layer disposed on the barrier layer; a first insulating layer disposed on the buffer layer; a second insulating layer disposed on the first insulating layer; a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer or on the second insulating layer, and wherein the wiring patterns are separated from each other, and extend toward a side of the substrate, a recess pattern disposed adjacent to the plurality of wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of the top surface of the substrate; and an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.