Patent ID: 9406521
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate, having a fin field effect transistor (finFET) region, a first region, a second region and a third region, the first region and the second region having a first surface and a second surface respectively and the third region having a third surface, wherein the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface; a plurality of fin shaped structures, disposed on a surface of the finFET region, wherein the second region is extended in a direction perpendicular to an extending direction of the fin shaped structures, and has a length at least two times greater than a pitch of the fin shaped structures; and an insulating layer, covering the first surface, the second surface, the third surface, and a bottom portion of the fin shaped structures, to form a first shallow trench isolation (STI) in the first region, a second STI in the second region, a third STI in the third region and a fourth STI in the finFET region, wherein the first STI, the second STI and the third STI have different depths.