Patent ID: 9337203
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: forming a first inter-layer dielectric layer over a substrate; forming a first contact hole by etching the first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure including a bit line over the preliminary first conductive plug; forming a first conductive plug and a gap by etching the preliminary first conductive plug so that the gap is formed inside of the first contact hole and between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer and extending from over an upper portion of the insulating plug to over a sidewall of the bit line structure; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.