Patent ID: 9236320
Filing Date: 2016-01-12
CPC Classification: H01L

Claim Text:
1. A chip package, comprising: a semiconductor chip having at least one conducting pad, an interconnect structure, and a device, a surface of the semiconductor chip extending from a first level to a second level, and the second level being lower than and substantially parallel to the first level, wherein the conducting pad is disposed on the first level of the surface of the semiconductor chip, the interconnect structure and the device are disposed in the semiconductor chip, and the device is electrically connected to the conducting pad through the interconnect structure; an isolation layer disposed on the surface of the semiconductor chip, and having at least one first opening to expose a part of the conducting pad; a redistributing metal layer disposed on the isolation layer, and having a redistributing metal line corresponding to the conducting pad, wherein the redistributing metal line is connected to the conducting pad through the first opening; and at least one bonding pad disposed on the isolation layer and positioned on the second level of the surface of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad disposed on the first level of the surface of the semiconductor chip and the bonding pad positioned on the second level of the surface of the semiconductor chip.