Patent ID: 9300892
Filing Date: 2016-03-29
CPC Classification: H03M,H04N

Claim Text:
1. A solid-state image pickup device comprising: an image pickup, in which a plurality of pixels each including a photoelectric conversion element for converting an optical signal into an electrical signal are arranged in a matrix, for sequentially scanning pixels in each row and outputting pixel signals of a selected row through a plurality of vertical readout lines arranged in respective columns; and a plurality of converters each for converting a pixel signal outputted through a corresponding vertical readout line from an analog signal to a digital value, wherein: each of the converters includes: a comparison circuit having a comparator input node, a reference voltage node and an output node, the comparison circuit comparing voltages of the comparator input node and the reference voltage node, and outputting a comparison result to the output node; a sample and hold circuit for sampling and holding a voltage of the pixel signal outputted through the vertical readout line, and outputting the voltage of the pixel signal to the comparator input node; a first determination circuit, including a plurality of circuit units, for changing the voltage of the comparator input node by voltages respectively corresponding to upper bits of the digital value, and determining each bit of the upper bits in accordance with the comparison result; and a second determination circuit for determining lower bits of the digital value in accordance with the reference voltage and the upper bits determined by the first determination circuit, wherein each of the circuit units comprises: a holding circuit having a pair of data holding lines, the pair of data holding lines being configured to hold a data; and a switching circuit for receiving the comparison result and switching a state of the data, and wherein the second determination circuit comprises: a capacitive element coupled to the comparator input node; a control circuit coupled to the capacitive element and configured to change a voltage of the comparator input node in a step manner; and a counter circuit configured to count a comparison time accordance with the comparison result and determine the lower bits of the digital value in accordance with the comparison time.