Patent ID: 9484108
Filing Date: 2016-11-01
CPC Classification: G11C

Claim Text:
1. An integrated circuit, comprising: a memory array including a plurality of memory cells to store data; a page buffer unit including a first register, and configured to read the data from the memory array in response to a read request, temporarily store the data read from the memory array in the first register and output the data stored in the first register in response to a data out request; an input/output circuit receiving the data stored in the first register and connected with the first register via a data line; and a voltage supplying circuit supplying a first operating voltage to the page buffer unit, and supplying a second operating voltage that is higher than the first operating voltage to the first register included in the page buffer unit wherein the voltage supplying circuit supplies the first operating voltage to the page buffer while the page buffer reads the data from the memory array and increases the first operating voltage supplied to the first register to the second operating voltage in response to the data out request, and the second operating voltage is transmitted to the data line while the page buffer outputs the data stored in the first register to the input/output circuit in response to the data out request.