Patent ID: 9425200
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming a inter-layer dielectric layer over a substrate; forming a first contact hole by etching the inter-layer dielectric layer; forming a pre-first contact plug that fills the first contact hole; forming a bit line over the pre-first contact plug; forming a first contact plug and a sidewall contact hole by etching the pre-first contact plug, wherein the sidewall contact hole is formed at both sidewalls of the first contact plug and inside of the first contact hole; forming a multi-layer spacer including first spacers, sacrificial spacers, and second spacers on sidewalls of the bit line and sidewalls of the first contact plug, wherein a portion of the sacrificial spacers and the first spacers fills the sidewall contact hole; forming, over the multi-layer spacer, a plug isolation layer including a second contact hole, wherein the second contact hole exposes sidewalls of the multi-layer spacer and the substrate; forming a second contact plug in the second contact hole, wherein the forming of the second contact plug includes: partially removing the multi-layer spacer to expose the sacrificial spacers; and forming air gaps extending from between the first contact plug and the first plug to between the bit line and the second plug by removing the sacrificial spacers.