Patent ID: 9230686
Filing Date: 2016-01-05
CPC Classification: G11C

Claim Text:
1. An apparatus comprising: a plurality of memory banks each including a plurality of memory cells; a plurality of redundant circuits each allocated to an associated one of the plurality of memory banks to replace a defective memory cell among the plurality of memory cells included in the associated memory bank; a plurality of roll call circuits allocated to an associated one of the plurality of memory banks to generate a roll call data when an address corresponding to the defective memory cell is supplied, each of the plurality of roll call circuits having first and second operation modes and each of the plurality of roll call circuits configured to generate when in the first operation mode the roll call data when an address corresponding to a defective word line included the memory bank is supplied and configured to generate when in the second operation mode the roll call data when an address corresponding to a defective bit line included the memory bank is supplied; and a plurality of data buses commonly allocated to the plurality of memory banks, wherein the plurality of roll call circuits output the roll call data to the plurality of data buses in parallel.