Patent ID: 9287282
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate; forming a dielectric protection layer overlapping the first pad oxide layer; removing the second pad oxide layer; forming a floating gate dielectric over the second active region; forming a floating gate layer, wherein the floating gate layer comprises a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric; performing a planarization on the first portion and the second portion of the floating gate layer; forming a blocking layer, a control gate layer, and a hard mask layer over the second portion of the floating gate layer; and patterning the hard mask layer, the control gate layer, and the blocking layer, wherein a remaining portion of the control gate layer forms a control gate.