Patent ID: 9244867
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. An integrated circuit configured to access memory, comprising: circuitry that generates memory access requests; a programmable memory interface that receives the memory access requests from the circuitry through a memory interface port having a port width and is configurable to vary the port width used in receiving the memory access requests from the circuitry; and a memory controller having a plurality of data ports each of which has an associated port width, wherein the memory controller fulfills the memory access requests by accessing the memory, wherein the programmable memory interface uses a selected number of the data ports in providing the memory access requests to the memory controller, wherein a sum of the port widths of the selected number of data ports is at least equal to the port width of the memory interface port, wherein the programmable memory interface is interposed between the memory controller and the circuitry that generates memory access requests.