Patent ID: 9330731
Filing Date: 2016-05-03
CPC Classification: G11C

Claim Text:
1. A circuit, comprising: a first transistor in a strap cell region between a first memory array and a second memory array of a memory device, the first transistor including a first node connected to a first data line, and a second node connected to a second data line, the first node and the second node of the first transistor being complementary to each other in voltage level; a second transistor, in the strap cell region, including a first node connected to the second data line, and a second node connected to the first data line, the first node and the second node of the second transistor being complementary to each other in voltage level; an access transistor biased at a controlled voltage, the access transistor including a first terminal connected to the second data line; and a third transistor including a gate connected to the first data line, and a terminal connected to a second terminal of the access transistor.