Patent ID: 9379711
Filing Date: 2016-06-28
CPC Classification: H01L,H03K

Claim Text:
1. A multiplexer comprising: a first switch comprising a first transistor and a second transistor; and a second switch comprising a third transistor and a fourth transistor; wherein one of a source and a drain of the first transistor is configured to receive a first signal from a configuration memory, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein one of the source and the drain of the second transistor is electrically connected to a first wiring, wherein the other of a source and a drain of the second transistor is electrically connected to a second wiring, wherein one of a source and a drain of the third transistor is configured to receive a second signal from the configuration memory, wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to a third wiring, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring, wherein a third signal is input to the one of the source and the drain of the second transistor via the first wiring, wherein a fourth signal is input to the one of the source and the drain of the fourth transistor via the third wiring, and wherein one of the third signal and the fourth signal is output via the second wiring.