Patent ID: 9275745
Filing Date: 2016-03-01
CPC Classification: G11C

Claim Text:
1. A semiconductor device, comprising: a memory cell array including a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages; a second storage unit into which a page address, of the plurality of page addresses, stored in the first storage unit is loaded; and a control circuit configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, perform the program operation and update the second storage unit with the externally inputted page address if the externally inputted page address is greater than the page address, transfer the externally inputted page address to the first storage unit if the program operation is canceled, read the second storage unit after the program operation is terminated to determine whether or not a delay time has occurred, and determine that the delay time has occurred if a page address corresponding to a last programmed page is stored in the second storage unit and that the delay time has not occurred if the page address corresponding to the last programmed page is not stored in the second storage unit.