Patent ID: 9368518
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A thin film transistor array panel comprising: a gate conductor disposed on a substrate and including a gate line and a gate electrode; a semiconductor layer overlapping the gate electrode and including an oxide semiconductor, the semiconductor layer having reduced oxygen vacancies within a channel region thereof resulting from a plasma treatment performed thereon; a data conductor including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode; a first sidewall disposed directly on the semiconductor layer and covering side surface parts of the drain electrode and the source electrode adjacent to the channel region of the semiconductor layer, the first sidewall configured to prevent the plasma treatment, which reduced oxygen vacancies within the channel region, from reacting with the source and drain electrodes; a second sidewall covering both a side surface part of the drain electrode and a side surface part of the semiconductor layer, and covering both a side surface part of the source electrode and a side surface part of the semiconductor layer; and a passivation layer covering the source electrode, the drain electrode, the first side wall and the second sidewall.