Patent ID: 9281745
Filing Date: 2016-03-08
CPC Classification: H02M

Claim Text:
1. A digital controller for a switch-mode DC-DC converter, the DC-DC converter having at least two switching elements and an LC circuit for producing an output voltage on an output of the DC-DC converter that is maintained at a desired level regardless of load changes that can occur on the output, the digital controller comprising: an input stage configured to produce a difference signal between a reference voltage (V a proportional-integral-derivative (PID) compensator configured to process the difference signal to stabilize the feedback loop by compensating for an undesired phase shift introduced in the DC-DC converter output voltage by the LC circuit for large variations on a load on the output of the DC-DC converter, the load variations ranging from no load to just more than zero ohms, the PID compensator having an output for outputting a processed difference signal; and a digital sigma-delta modulator coupled to the PID compensator output configured to (i) generate at least one switching element control signal in response to the processed difference signal and (ii) output the at least one switching element control signal to a control input of at least one of the at least two switching elements for controlling a respective switching element of the DC-DC converter, wherein the first input is configured to receive the analog reference voltage signal, and the second input is configured to receive the analog feedback voltage signal, the comparator further having an output for outputting a comparator output signal that is produced by the comparator in response to the first and second inputs, wherein the flip-flop has an input for receiving the comparator output signal, the flip-flop further having an output for outputting a sampled signal that is generated by the flip-flop in response to the received comparator output signal, and wherein the multiplexer is configured to multiplex, in response to the sampled signal, quantization values on an output of the multiplexer, wherein multiplexing the quantization values converts the sampled signal which corresponds to an unsigned signal of 0's and 1's into a two's complement signal, wherein the two's complement signal comprises the difference signal for processing by the PID compensator.