Patent ID: 9437712
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a dummy gate stack over a semiconductor substrate, wherein the dummy gate stack is adjacent to a gate spacer; forming a protective liner over the semiconductor substrate, the dummy gate stack and the gate spacer, wherein the protective liner is a metal dielectric liner and covers a sidewall of the gate spacer, and further wherein a first portion of the protective liner is over a top surface of the dummy gate stack and above an uppermost surface of the gate spacer and a second portion of the protective liner over an active region at a top surface of the semiconductor substrate; forming a first inter-layer dielectric (ILD) over the protective liner; replacing the dummy gate stack with a conductive gate stack, the replacing comprising: patterning a contact opening in the first ILD, exposing the second portion of the protective liner; removing the second portion of the protective liner, exposing the active region; and forming a contact in the contact opening, wherein the contact is electrically connected to the active region.