Patent ID: 9280498
Filing Date: 2016-03-08
CPC Classification: G06F

Claim Text:
1. A data control system comprising: a central processing unit (CPU) which controls data transfer from a first device to a second device in a kernel mode; and a main memory which is configured to store data to be transferred from the first device to the second device, wherein the CPU comprises: wherein the data transfer control unit allocates memory space in the main memory, and creates a direct memory access list in the main memory, wherein the first device control unit is configured to cause the first device to write data into the memory space using direct memory access with the direct memory access list, wherein the second device control unit is configured to cause the second device to read the data written by the first device from the memory space using direct memory access with the direct memory access list, and wherein the data transfer control unit is configured to multiplex and formulate the read instruction and the write instruction in parallel.