Patent ID: 9423454
Filing Date: 2016-08-23
CPC Classification: G01R,G11C

Claim Text:
1. A test circuit of a semiconductor apparatus comprising: a plurality of pads; a pattern generator that generates at least one internal test pattern in response to at least one pattern select signal; and a plurality of test units that transmit the at least one internal test pattern through the plurality of pads in response to a self test mode signal, compare the at least one test pattern received via the plurality of pads with the at least one generated internal test pattern and generate at least one test determination value based on the comparison, wherein the plurality of test units comprise: determining sections that compare the at least one test pattern received via the plurality of pads and the at least one internal test pattern generated in accordance with the self test mode signal, and generate the at least one test determination value based on the comparison; at least one first multiplexer that selects one of an output signal of one of an upper test unit and an output signal of at least one of the determining sections in response to a first test mode control signal; at least one flip-flop that stores an output of at least one of the first multiplexers and transmits the output to a lower test unit; at least one second multiplexer that selects one of an output signal of at least one of the flip-flops and normal mode transmission data in response to a second test mode control signal; and at least one third multiplexer that selects one of an output signal of at least one of the second multiplexers and the internal test patterns and transmits the selected one of the output signal of at least one of the second multiplexers and the internal test patterns to the plurality of pads.