Patent ID: 9395698
Filing Date: 2016-07-19
CPC Classification: G04F,H03K,H03L,H03M

Claim Text:
1. A time to digital converter comprising: a mutual exclusion element configured to receive a first clock and a second clock and to generate a first pulse and a second pulse, wherein the mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock; and a sampling component configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse, wherein the decision signal includes a first early indicator and a second early indicator, wherein the first early indicator is set to the first logic state upon the first clock being earlier than the second clock and the second early indicator is set to the first logic state upon the second clock being earlier than the first clock.