Patent ID: 9384814
Filing Date: 2016-07-05
CPC Classification: B82Y,G11C

Claim Text:
1. A method of writing data to a thyristor memory cell, comprising: applying a data pulse to a data line coupled to the thyristor memory cell such that a voltage on the data line moves to a data pulse height and then the voltage on the data line moves from the data pulse height to a data line standby level; and applying an access pulse to an access line coupled to a gate of the thyristor memory cell such that a voltage on the access line moves to an access pulse height and then the voltage on the access line moves from the access pulse height to an access standby level such that the voltage on the access line comes to the access standby level as the voltage on the data line comes to the data line standby level; wherein while the voltage on the access line is moving from the access pulse height to the access standby level, the voltage of the access line moves to an intermediate level, between the access pulse height and the access standby level, before the voltage on the data line begins to move from the data pulse height to the data line standby level and the voltage of the access line is maintained at the intermediate level for a selected amount of time prior to moving to the access standby level.