Patent ID: 9356122
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A method of forming a field effect transistor, said method comprising: forming on a first side of a semiconductor substrate of a first conductivity type, a plurality of layers of material defining gate, source and drain regions, with said gate region having a lateral gate channel; generating, upon said semiconductor substrate, a layer of semiconductor material having a first conductivity type associated therewith; generating on said first semiconductor layer a second semiconductor layer, with said second semiconductor layer having multiple regions of differing conductivity types, defining a super-junction structure in electrical communication with said gate, source and drain regions; forming one or more trenches from a second side opposed to said first side of said semiconductor substrate extending from one or more orifices toward said first side of said semiconductor substrate with a controlled depth; and filling said plurality of one or more trenches with a conductive material forming a first contact in electrical communication with one of said source region and said drain region.