Patent ID: 9413374
Filing Date: 2016-08-09
CPC Classification: H03M

Claim Text:
1. A circuit comprising: a multiplexed sampling network sampling either an input voltage or a common-mode voltage into a sampled voltage in accordance with a sampling signal and a status of a foreground calibration indicator; a first digital-to-analog converter outputting a conversion voltage in response to a conversion code; a second digital-to-analog converter outputting an offset-correction voltage in response to an offset-correction code; a summing circuit receiving the sampled voltage, the conversion voltage, and the offset-correction voltage and outputting an error voltage; a comparator receiving the error voltage and outputting a binary decision; and a successive-approximation-register finite state machine receiving the binary decision and outputting an output data, the sampling signal, the foreground calibration indicator, the conversion code, and the offset-correction code, wherein the finite stage machine includes a foreground calibration state and a normal operation state; wherein when the finite state machine operates in the foreground calibration state, the common-mode voltage is sampled, the conversion code is set to a common-mode code, and a calibrated value of the offset-correction code is established by successive approximation and wherein when the finite state machine is in the normal operation state, the input voltage is sampled, the offset-correction code is set to the calibrated value, and the conversion code is established by successive approximation.