Patent ID: 9252358
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising a memory cell array comprising: a plurality of first lines and a plurality of second lines intersecting each other; and a plurality of memory cells each disposed at each of intersections of the plurality of first lines and the plurality of second lines and each including a variable resistance element, the method comprising: stacking a plurality of first conductive layers and a plurality of interlayer insulating layers alternately on a substrate, the first conductive layers functioning as the first lines; forming a trench that penetrates the plurality of first conductive layers and the plurality of interlayer insulating layers; forming a side wall layer on a side surface of the plurality of first conductive layers facing the trench and on a side surface of the plurality of interlayer insulating layers facing the trench; forming a column-shaped conductive layer to fill the trench via the side wall layer, the column-shaped conductive layer functioning as one of the second lines; and after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, making a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, thereby causing the side wall layer adjacent to the first conductive layers to function as the variable resistance element.