Patent ID: 9397642
Filing Date: 2016-07-19
CPC Classification: H03K

Claim Text:
1. A latch circuit comprising: a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node; a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node; a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node; a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node; a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on; and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on, wherein the first separation element and the second separation element include a PMOS transistor, respectively.