Patent ID: 9513660
Filing Date: 2016-12-06
CPC Classification: G06F

Claim Text:
1. A processor-implemented method for implementing a shared counter architecture, the method comprising: receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value; acquiring, by the worker thread, the shared timer value; recording, by the common timer thread, a shared calibration factor, wherein the shared calibration factor comprises the difference between a current clock time and an interval time the common timer thread was last dispatched; acquiring, by the worker thread, a configuration value corresponding to the application request; generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value; registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing, by the common timer thread, resources based on the timeout occurrence.