Patent ID: 9417647
Filing Date: 2016-08-16
CPC Classification: G05F,H03K

Claim Text:
1. A semiconductor integrated circuit device comprising: a PMOS bulk bias generation block configured to output a first external voltage as a bulk voltage of a PMOS transistor in a power-up period, and output a second external voltage as the bulk voltage of the PMOS transistor in a power-down mode, in response to a bulk bias enable signal configured to be enabled in the power-down mode and a leakage signal; and a NMOS bulk bias generation block configured to output a ground voltage as a bulk voltage of an NMOS transistor in the power-up period, and output a negative voltage as the bulk voltage of the NMOS transistor in the power-down mode, in response to the bulk bias enable signal, wherein the second external voltage has a higher level than the first external voltage, and wherein the negative voltage has a larger absolute value than the ground voltage.