Patent ID: 9285917
Filing Date: 2016-03-15
CPC Classification: G02F,G06F

Claim Text:
1. A liquid crystal display, comprising: a first gate line for transmitting a first gate signal; a second gate line for transmitting a second gate signal; a data line for transmitting a data signal; a pixel unit, electrically connected to the first gate line and the data line, for outputting an image signal according to the first gate signal and the data signal; a photo-sensing input unit, electrically connected to the first gate line, for generating a sensing voltage according to a driving voltage and an incident light signal, and for outputting a readout signal according to the sensing voltage and the first gate signal; a driving adjustment unit, electrically connected to the second gate line and the photo-sensing input unit, for providing the driving voltage according to the second gate signal and the incident light signal; and a readout line, electrically connected to the photo-sensing input unit, for transmitting the readout signal; wherein the photo-sensing input unit comprises: a first transistor having a first end for receiving a first common voltage, a gate end for receiving the driving voltage, and a second end; a first capacitor, electrically connected between the first and second ends of the first transistor; and a second transistor having a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first gate line, and a second end electrically connected to the readout line; wherein the driving adjustment unit comprises: a third transistor having a first end for receiving a second common voltage, a gate end electrically connected to the second gate line, and a second end electrically connected to the gate end of the first transistor; a fourth transistor having a first end for receiving a third common voltage, a gate end electrically connected to the second gate line, and a second end electrically connected to the second end of the first transistor; and a second capacitor electrically connected between the second end of the third transistor and the second end of the fourth transistor.