Patent ID: 9502305
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method of forming a CMOS transistor, comprising: providing a semiconductor substrate having at least an NMOS transistor and at least a PMOS transistor thereon, and a source/drain of the PMOS transistor comprising germanium (Ge), wherein the semiconductor substrate has an N well disposed therein, and the PMOS transistor is formed in the N well, and wherein the source/drain of the PMOS transistor is formed comprising a step of an implantation process to implant P-type dopants into the semiconductor substrate; forming a carbon-doped layer in a top portion of the source/drain of the PMOS transistor, wherein the carbon-doped layer is not in contact with the N well and the carbon-doped layer is formed by a carbon implantation process, and wherein the carbon implantation process is performed after the implantation process; performing a self-aligned silicide process; forming at least a tensile thin film covering the semiconductor substrate, the NMOS transistor, and the PMOS transistor; and performing a surface treatment on the tensile thin film.