Patent ID: 9436600
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. A method for monitoring memory access operations in a computer system having a memory controller, the method comprising: coupling the memory controller of the computer system to an interface via a set of data lines and a set of address and control signal lines; coupling the interface to a first memory channel via a first set of data lines and a first set of address and control signal lines, wherein a first volatile memory subsystem is coupled to the interface via the first memory channel, the first volatile memory subsystem communicates data with the memory controller of the computer system via the interface using the first set of data lines; coupling the interface to a second memory channel via a second set of data lines and a second set of address and control signal lines, wherein a second volatile memory subsystem is coupled to the interface via the second memory channel, the second volatile memory subsystem communicates data with the memory controller of the computer system via the interface using the second set of data lines; coupling the interface to a nonvolatile memory subsystem, the nonvolatile memory subsystem including an NV (non-volatile) controller and at least one nonvolatile memory element; monitoring each of the first and second memory channels to detect one or more memory access operations from the memory controller of the computer system to at least one predetermined address range of the first or second volatile memory subsystems; and capturing a copy of data associated with the one or more memory access operations.