Patent ID: 9336086
Filing Date: 2016-05-10
CPC Classification: G06F,G11C,H03M

Claim Text:
1. An apparatus comprising: first memory cells located on a first level of a memory device; second memory cells located on a second level of the memory device; and a controller to cause data to be stored in a first memory cell group of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in a second memory cell group of the first memory cells, to cause additional data to be stored in a first memory cell group of the second memory cells and to cause a second portion of the error correction code to be stored in a second memory cell group of the second memory cells, wherein the controller is further configured to cause at least a portion of an error correction code associated with the additional data to be stored in a third memory cell group of the second memory cells concurrently with storing of the second portion of the error correction code in the second memory cell group of the second memory cells.