Patent ID: 9405873
Filing Date: 2016-08-02
CPC Classification: G06F

Claim Text:
1. A circuit simulation method comprising: dividing a well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate into two or more meshes each including two or more resistor segments; and analyzing a substrate noise of the substrate, wherein parallel components of resistors coupling said Pwell with said substrate are deleted in accordance with a state of said Deep Nwell diffusing into said Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value, wherein said process for expressing the rise in the resistance value is a resistor segment deleting process in which, after said mesh division, resistor segments in a depth direction of said semiconductor substrate are deleted in a mesh corresponding to said Pwell region eroded by the diffusion of said Deep Nwell.