Patent ID: 9490014
Filing Date: 2016-11-08
CPC Classification: G06F,G11C

Claim Text:
1. A method comprising: receiving a chip select signal for activating a plurality of non-volatile memory banks, each non-volatile memory bank being independently operable and comprising control circuitry, row decoding circuitry, column decoding circuitry, and sense amplifier circuitry; receiving a first data stream at a common interface configured to receive command data, address data and write data, all at different times; parsing the first data stream to extract a first memory bank identifier of a first of the plurality of non-volatile memory banks; updating a first memory bank status register corresponding to the first non-volatile memory bank to indicate that the first non-volatile memory bank is busy; and routing write data of the first data stream between the common interface and a non-volatile memory cell array of the first non-volatile memory bank.