Patent ID: 9412764
Filing Date: 2016-08-09
CPC Classification: G09G,H01L

Claim Text:
1. A semiconductor device comprising: a first input terminal to which a start pulse signal is input; a second input terminal to which a clock signal is input; a third input terminal to which a reset signal is input; an output terminal from which a pulse signal is output; a first transistor; a second transistor; a third transistor; and a switching element, wherein a first terminal of the first transistor is electrically connected to the first input terminal, wherein a second terminal of the first transistor is electrically connected to a gate electrode of the second transistor, wherein a gate electrode of the first transistor is electrically connected to the first terminal of the first transistor, wherein a first terminal of the second transistor is electrically connected to the second input terminal, wherein a second terminal of the second transistor is electrically connected to a first terminal of the third transistor and the output terminal, wherein a second terminal of the third transistor is electrically connected to a wiring to which a first low power supply potential is applied, wherein a gate electrode of the third transistor is electrically connected to the third input terminal, wherein a first terminal of the switching element is electrically connected to the second terminal of the first transistor and the gate electrode of the second transistor, wherein a second terminal of the switching element is electrically connected to a wiring to which a second low power supply potential lower than the first low power supply potential is applied, wherein the start pulse signal comprises the first low power supply potential and a high power supply potential, and wherein the second low power supply potential is applied to the gate electrode of the second transistor through the switching element, when the start pulse signal is the first low power supply potential.