Patent ID: 9379120
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A non-volatile memory array, comprising: a plurality of control gates including at least one metal layer extending in a row direction over a surface of a substrate, each control gate including first and second sidewalls elongated in the row direction and extending vertically with respect to the substrate surface; a plurality of sidewall spacers including sidewall spacers formed along the first and the second sidewalls of each control gate; a plurality of rows of charge storage regions, each row of charge storage regions underlying a corresponding control gate and being separated therefrom by an intermediate dielectric material; a plurality of word line air gaps including an air gap between each pair of control gates adjacent in a column direction, each word line air gap extending vertically with respect to the substrate surface; a first column of non-volatile storage elements formed over a first active area of the substrate and a second column of non-volatile storage elements formed over a second active area of the substrate; an isolation region in the substrate between the first active area and the second active area; and a bit line air gap in the isolation region.