Patent ID: 9250288
Filing Date: 2016-02-02
CPC Classification: G01R

Claim Text:
1. A wafer-level testing method for testing a plurality of singulated 3D-stacked chip cubes comprising the steps of: providing a carrier wafer with the same dimension as a semiconductor wafer for loading in a wafer tester; attaching a plurality of first 3D-stacked chip cubes onto the carrier wafer according to a first wafer map, wherein the first wafer map defines a plurality of first probe card activated regions, each being corresponding to a probe card in the wafer tester and including a plurality of first component-attaching regions to constitute a M-by-N matrix, wherein each first component-attaching region is one-to-one corresponding to one of the first 3D-stacked chip cubes on the carrier wafer and is one-to-one corresponding to one of a plurality of component probing units of the probe card; proceeding a first wafer-level testing in the wafer tester, including probing the first 3D-stacked chip cubes disposed in each corresponding first probe card activated region by the probe card whereas the electrical functions of the component probing units of the probe card are fully activated; building a second wafer map according to the testing results of the first wafer-level testing to confirm one or more prone-to-overkill component-attaching regions in each first probe card activated region, wherein the second wafer map defines a plurality of second probe card activated regions, each being corresponding to the probe card and including a plurality of second component-attaching regions arranged in a same pattern to constitute an incomplete matrix by excluding the above mentioned prone-to-overkill component-attaching regions; attaching a plurality of second 3D-stacked chip cubes with the same dimension as the first 3D-stacked chip cubes on the carrier wafer according to the second wafer map whereas the second 3D-stacked chip cubes are not disposed in the corresponding prone-to-overkill component-attaching regions; and proceeding a second wafer-level testing in the wafer tester, including probing the second 3D-stacked chip cubes in each corresponding second probe card activated region by the probe card.