Patent ID: 9373561
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method of forming a continuous cooling channel in a back end of the line (BEOL) of an integrated circuit (IC) chip, the method comprising: providing a first interconnect level having a first conductive filler layer; forming a second interconnect level on the first interconnect level; forming a pair of openings in the second interconnect level to expose the first conductive filler layer; lining each of the openings with a barrier layer; removing a horizontal portion of a barrier layer from each of the openings using gas cluster ion beam etching to expose an upper surface of the first conductive filler layer wherein a vertical portion of the barrier layer located on a sidewall of each of the openings remains intact; filling the openings with a second conductive filler layer, wherein the second conductive filler layer in each of the openings is in contact with the first conductive filler layer; and removing the second conductive filler layer from each of the opening and removing the first conductive filler layer to form a continuous cooling channel.