Patent ID: 9246088
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A semiconductor memory device comprising a memory cell array, the memory cell array comprising memory cells, the memory cell array comprising: first conductive layers stacked at a predetermined pitch in a first direction perpendicular to a substrate, the first conductive layers extending in a second direction parallel to the substrate; a memory layer provided in common on side surfaces of the first conductive layers; and a second conductive layer comprising a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction, an entire width in the second direction of the first side surface at a first position being smaller than an entire width in the second direction of the first side surface at a second position lower than the first position, and an entire thickness in the first direction of a conductive layer of the first conductive layers at the first position being larger than an entire thickness in the first direction of another conductive layer of the first conductive layers at the second position.