Patent ID: 9356208
Filing Date: 2016-05-31
CPC Classification: G02F,H01L

Claim Text:
1. A manufacturing method of a pixel structure, comprising: forming a first conductive layer on a substrate, the first conductive layer comprising a first electrode; forming a first insulation layer on the first conductive layer; forming a second conductive layer on the first insulation layer, the second conductive layer comprising a gate and a second electrode, the second electrode being located above the first electrode; forming a second insulation layer on the second conductive layer; forming a semiconductor layer on the second insulation layer above the gate, wherein the second electrode and the semiconductor layer do not overlap each other; forming a third conductive layer on the second insulation layer, the third conductive layer comprising a source, a drain and a third electrode, the source and the drain being located on the semiconductor layer, the third electrode being located above the second electrode and electrically connected to the first electrode, wherein the gate, the semiconductor layer, the source, and the drain together constitute a thin film transistor, and the first electrode, the second electrode, and the third electrode together constitute a capacitor; forming a third insulation layer on the third conductive layer; and forming a pixel electrode on the third insulation layer, the pixel electrode being electrically connected to the drain.