Patent ID: 9530866
Filing Date: 2016-12-27
CPC Classification: B82Y,H01L

Claim Text:
1. A method of forming a vertical transistor device, the method comprising: forming a vertically oriented channel semiconductor structure with a cap layer positioned above said vertically oriented channel semiconductor structure; forming a first sidewall spacer adjacent said vertically oriented channel semiconductor structure and adjacent said cap layer; forming a layer of insulating material adjacent said first sidewall spacer; performing at least one planarization process so as to planarize an upper surface of said layer of insulating material and expose an upper surface of said cap layer and an upper surface of said first sidewall spacer; performing at least one etching process to remove a portion of said first sidewall spacer and to remove an entirety of said cap layer so as to thereby expose an upper surface of said vertically oriented channel semiconductor structure and define a spacer/contact cavity above said vertically oriented channel semiconductor structure and said first sidewall spacer; forming a second spacer in said spacer/contact cavity, wherein after formation of said second spacer, at least a portion of said upper surface of said vertically oriented channel semiconductor structure remains exposed; after forming said second spacer, forming a top source/drain region in said vertically oriented channel semiconductor structure; and forming a top source/drain contact within said spacer/contact cavity that is conductively coupled to said top source/drain region, wherein said conductive contact physically contacts said second spacer in said spacer/contact cavity.