Patent ID: 9529760
Filing Date: 2016-12-27
CPC Classification: G06F

Claim Text:
1. A method of handling cache-inhibited operations in a data processing system, comprising: receiving, at a replicated bus unit, a cache-inhibited (CI) operation; determining, by the replicated bus unit, whether an address of the CI operation matches an address for the replicated bus unit and whether a source indicated by the CI operation is a source that is serviced by the replicated bus unit; in response to the address of the CI operation matching the address for the replicated bus unit and the source indicated by the CI operation being a source that is serviced by the replicated bus unit, processing, by the replicated bus unit, the CI operation; and in response to the address of the CI operation not matching the address for the replicated bus unit or the source indicated by the CI operation not being a source that is serviced by the replicated bus unit, ignoring, by the replicated bus unit, the CI operation.