Patent ID: 9495498
Filing Date: 2016-11-15
CPC Classification: G06F,H01L

Claim Text:
1. A circuit arrangement, comprising: a plurality of semiconductor dies physically and electrically coupled to one another in a stack, the plurality of semiconductor dies including at least three dies, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer that includes at least one functional unit, wherein at least one face of each semiconductor die includes a standardized inter-layer interface region disposed thereon, and wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack; a first inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the first inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack; and a second inter-layer bus topographically separated from the first inter-layer bus, wherein the stack of semiconductor dies defines first and second vertically-oriented supernodes, wherein the circuit layers on multiple semiconductor dies in the stack include functional units allocated to each of the first and second supernodes, with the functional units allocated to the first supernode coupled to the first inter-layer bus and the functional units allocated to the second supernode coupled to the second inter-layer bus, and wherein each semiconductor die includes a regular array of contact pads disposed on at least one face of such semiconductor die, wherein the plurality of electrical conductors disposed within the inter-layer interface region of such semiconductor die and extending between the opposing faces of each semiconductor die are topographically aligned and electrically coupled to at least a first subset of the regular array of contact pads that are topographically disposed within the inter-layer interface region of such semiconductor die.