Patent ID: 9230910
Filing Date: 2016-01-05
CPC Classification: G03F,H01L

Claim Text:
1. A method for creating a layout of a semiconductor device, comprising: processing a layout of a semiconductor device to identify a first linear-shaped gate electrode level layout structure that forms a gate electrode of a first transistor and a second linear-shaped gate electrode level layout structure that forms a gate electrode of a second transistor, each of the first and second linear-shaped gate electrode level layout structures oriented to extend lengthwise in a first direction, the first and second linear-shaped gate electrode level layout structures positioned next to each other such that their respective lengthwise-oriented centerlines are separated from each other by a gate electrode pitch as measured in a second direction perpendicular to the first direction; processing the layout of the semiconductor device to identify a first linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure; processing the layout of the semiconductor device to identify a second linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure; processing the layout of the semiconductor device to identify a third linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure; determining a size of the first linear-shaped gate electrode level layout structure as measured in the second direction; creating a first rectangular-shaped interlevel connection layout structure to have a horizontal cross-section with a first size as measured in the first direction and a second size as measured in the second direction, the second size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure at least twice the first size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure, and the second size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure larger than twice the size of the first linear-shaped gate electrode level layout structure as measured in the second direction; modifying the layout of the semiconductor device by positioning the first rectangular-shaped interlevel connection layout structure in a substantially centered manner on the first linear-shaped gate electrode level layout structure relative to the second direction and in a substantially centered manner on the first linear-shaped interconnect level layout structure relative to the first direction; creating a second rectangular-shaped interlevel connection layout structure to have a horizontal cross-section with a first size as measured in the first direction and a second size as measured in the second direction, the first size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure at least twice the second size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure, and the first size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure larger than a size of the second linear-shaped interconnect level layout structure as measured in the first direction; modifying the layout of the semiconductor device by positioning the second rectangular-shaped interlevel connection layout structure in a substantially centered manner on the second linear-shaped interconnect level layout structure relative to the first direction and in a substantially centered manner on a position located one-half of the gate electrode pitch as measured in the second direction away from the lengthwise-oriented centerline of the first linear-shaped gate electrode level layout structure; creating a third rectangular-shaped interlevel connection layout structure to have a horizontal cross-section with a first size as measured in the first direction and a second size as measured in the second direction, the first size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure at least twice the second size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure, and the first size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure larger than a size of the third linear-shaped interconnect level layout structure as measured in the first direction; modifying the layout of the semiconductor device by positioning the third rectangular-shaped interlevel connection layout structure in a substantially centered manner on the third linear-shaped interconnect level layout structure relative to the first direction and in a substantially centered manner on a position located one-half of the gate electrode pitch as measured in the second direction away from the lengthwise-oriented centerline of the first linear-shaped gate electrode level layout structure, such that the second and third rectangular-shaped interlevel connection layout structures are located on different sides of the first linear-shaped gate electrode level layout structure relative to the second direction; and recording the layout of the semiconductor device as modified to include each of the first, second, and third rectangular-shaped interlevel connection layout structures on a non-transitory computer readable medium in a format for fabrication of the semiconductor device.