Patent ID: 9257195
Filing Date: 2016-02-09
CPC Classification: G11C

Claim Text:
1. A method of operating a memory controller in a memory system including a nonvolatile memory device, the method comprising: erasing memory cells of a target memory block of the non-volatile memory device on a block basis; after erasing the memory cells of the target memory block, searching for a bad memory cell by a performing an erase verifying operation on the target memory block, the bad memory cell located in a sub-block among a plurality of sub-blocks of the target memory block; comparing a threshold voltage of the bad memory cell to a plurality of reference voltages to generate comparison results; and selectively designating as a bad area either one of the entire target memory block or only a portion of target memory block in response to the comparison results, wherein the portion of the target memory block is less than the entire target memory block and includes the sub-block of the target memory block in which the bad memory cell is located.