Patent ID: 9245967
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: device including a field effect transistor (FET), the device comprising: a substrate including a first portion having a first top surface, and a second portion having a second top surface, the second top surface being recessed below the first top surface; a gate stack disposed on a channel region in the first portion; a lightly doped drain junction region disposed underneath the gate stack and adjacent to a side thereof in the first portion; a crystallized silicon layer disposed in the second portion of the silicon substrate; a metal silicide layer disposed on the crystallized silicon layer, the metal silicide layer extending along the second top surface, contacting with the second top surface, and having an end portion contacting with the lightly doped drain junction region,; an insulating layer disposed on the metal silicide layer; and a plurality of contact plugs disposed substantially vertically through the insulating layer, the contact plugs having a metal barrier layer lining in the insulating layer and physically connecting with the metal silicide layer, wherein the contact plugs pass through an entire thickness of the metal silicide layer to contact ion implantation regions formed within a source region and a drain region of the substrate, and wherein the metal barrier layer lining of the contact plugs is filled with a conductive material.