Patent ID: 9442838
Filing Date: 2016-09-13
CPC Classification: G06F,G11C

Claim Text:
1. A method of operating a memory device, the memory device comprising: groups of memory cells, the groups including a first group of memory cells, each one of the groups having a respective physical address and initially being associated with a respective logical address; an additional group of memory cells having a physical address but not initially being associated with a logical address; and a future endurance comparator to compare future endurances of the first group of memory cells and the additional group of memory cells, wherein the future endurance comparator comprises a circuit current comparator, the method comprising: identifying a difference in a future endurance between the first group of memory cells and the additional group of memory cells; and in accordance with a determination, made using the current comparator of the future endurance comparator, that the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference: