Patent ID: 9385078
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method for forming a via in an integrated circuit, the method comprising: patterning and removing exposed portions of a first organic self-planarizing polymer (OPL) layer to form a first cavity that exposes a first hardmask; removing an exposed portion of the first hardmask in the first cavity to expose a second hardmask; removing an exposed portion of the second hardmask in the first cavity to expose a portion of a second OPL layer; removing the first OPL layer to expose the first hardmask and removing an exposed portion of the second OPL layer in the first cavity to expose a portion of a third hardmask; removing an exposed portion of the third hardmask in the first cavity to expose a portion of a first dielectric layer; removing an exposed portion of the first dielectric layer in the first cavity to expose a first portion of a first cap layer; depositing a third OPL layer in the first cavity and over the first hardmask; removing a portion of the third OPL layer to form a second cavity that exposes a second portion of the first hardmask; removing the second portion of the first hardmask in the second cavity to expose a second portion of the second hardmask; removing the second portion of the second hardmask in the second cavity to expose a second portion of the second OPL layer; removing portions of the third OPL layer and the first hardmask to expose the second hardmask and removing portions of the third OPL layer in the first cavity; removing the second portion of the second OPL layer in the second cavity to expose a second portion of the third hardmask and removing exposed portions of the third OPL layer in the first cavity to expose the portion of the first cap layer; removing an exposed portion of the third hardmask in the second cavity to expose a second portion of the first dielectric layer and removing the portion of the first cap layer in the first cavity to expose a first portion of a second dielectric layer; removing the second portion of the first dielectric layer in the second cavity to expose a second portion of the first cap layer and removing the first portion of the second dielectric layer to expose a first portion of a second cap layer; and removing the first portion of the second cap layer in the first cavity to expose a first conductive contact and removing the second portion of the first cap layer to in the second cavity to expose a second conductive contact.