Patent ID: 9530689
Filing Date: 2016-12-27
CPC Classification: H01L

Claim Text:
1. A method for fabricating an integrated circuit, the method comprising: patterning a first hard mask layer overlying a dielectric layer of dielectric material that overlies a semiconductor substrate using a first photomask to transfer a first line feature pattern from the first photomask to the first hard mask layer to form a first patterned hard mask layer having a first line feature opening formed therethrough that corresponds to the first line feature pattern and that exposes a first portion of the dielectric layer; depositing a photoresist layer overlying the first patterned hard mask layer including overlying the first portion of the dielectric layer; patterning the photoresist layer using a second photomask to transfer a second line feature pattern from the second photomask to the photoresist layer to form a patterned photoresist layer having a second line feature opening formed therethrough that corresponds to the second line feature pattern, wherein patterning the photoresist layer comprises forming the patterned photoresist layer such that the first and second line feature openings partially overlap to expose a first part of the first portion of the dielectric layer; and transferring the first and second line feature patterns from the first patterned hard mask layer and the patterned photoresist layer to the dielectric layer to form an interconnect-hole that extends through the first part of the first portion of the dielectric layer and a metal line trench that extends laterally in an upper portion of the dielectric layer open to the interconnect-hole, wherein the interconnect-hole extends through a lower portion of the dielectric layer directly below the first part of the metal line trench.