Patent ID: 9425616
Filing Date: 2016-08-23
CPC Classification: H02H

Claim Text:
1. A device comprising: a native n-type metal oxide semiconductor (NMOS) transistor having a first drain/source region directly connected to a first voltage potential and a second drain/source region directly connected to a first terminal of a capacitor, wherein a gate of the native NMOS transistor is connected to the first terminal of the capacitor, and wherein parameter values of the native NMOS transistor are selected such that the native NMOS transistor functions as a pull-up resistor; a resistance element connected between the first voltage potential and the first terminal of the capacitor, wherein the resistance element comprises at least a p-type metal oxide semiconductor (PMOS) transistor, and wherein the resistance element has at least two resistance values, and wherein a first resistance value of the resistance element is greater than a resistance value of the pull-up resistor, and a second resistance value of the resistance element is less than the resistance value of the pull-up resistor; and the capacitor having a second terminal coupled to a second voltage potential, wherein the first voltage potential is higher than the second voltage potential, and wherein the native NMOS transistor, the resistance element and the capacitor form an electrostatic discharge (ESD) trigger circuit.