Patent ID: 9412719
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. An apparatus comprising: a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the first dielectric layers over the first substrate; a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate; a conductive plug extending from a second surface of the first semiconductor chip to one of the plurality of second metal lines in the second semiconductor chip; and a plurality of dielectric liners interposed between the conductive plug and the first substrate, at least one of the plurality of dielectric liners not extending between the conductive plug and the plurality of first dielectric layers, the plurality of dielectric liners comprising a first dielectric liner and a second dielectric liner, the first dielectric liner contacting the first substrate, and the second dielectric liner contacting the first dielectric liner, an uppermost surface of the second dielectric liner not extending above an uppermost surface of the first dielectric liner, an uppermost surface of the conductive plug being level with the uppermost surface of the first dielectric liner.