Patent ID: 9360885
Filing Date: 2016-06-07
CPC Classification: G06F,H04J,H04L

Claim Text:
1. A system comprising logic integrated with a processor, the logic being configured to: synchronize clocks of two intermediate devices across a plurality of link aggregation (LAG) ports 1 to N therebetween, wherein N is at least 2, and wherein the clock synchronization is performed independently across each of the LAG ports; determine a latency for each LAG port based on information derived from synchronizing the clocks of the two intermediate devices; store the latency for each LAG port to a LAG structure along with an identifier of a corresponding LAG port and mark a LAG port having a lowest latency; discover a configuration of a network fabric after determining the latency for each LAG port; synchronize clocks of two devices across a plurality of paths 1 to P connecting the two devices through the network fabric, wherein P is at least 2, wherein each path has an equal path cost factor, and wherein the clock synchronization is performed independently across the plurality of paths connecting the two devices in the network fabric; determine a transit delay for each path of the plurality of paths connecting the two devices in the network fabric based on information derived from synchronizing the clocks of the two devices and the latency for LAG ports included in the plurality of paths; store the transit delay for each path of the plurality of paths connecting the two devices in the network fabric to an equal cost multi-path (ECMP) structure along with an identifier for each path of the plurality of paths connecting the two devices in the network fabric; and sort the plurality of paths connecting the two devices in the network fabric in the ECMP structure according to each path's transit delay and mark a path having a lowest latency.