Patent ID: 9430676
Filing Date: 2016-08-30
CPC Classification: G06F,H04L

Claim Text:
1. An apparatus comprising: a frequency selection module that selects a plurality of frequencies for a first noise output, the plurality of frequencies within a range of frequencies of a second noise output, the second noise output produced by one or more first voltage regulating modules providing power to a processor; an amplitude selection module that selects an amplitude for each frequency of the plurality of frequencies of the first noise output; a noise scrambling module that produces the first noise output based on one or both of the frequency selection module and the amplitude selection module, wherein the first noise output combines with the second noise output to produce a third noise output such that a coherence between the third noise output and operations of the processor is below a threshold; and a noise detection module comprising a transducer, wherein the transducer detects the third noise output; wherein said modules comprise one or more of a hardware circuit, a programmable logic device, and code stored on one or more computer readable storage devices, wherein when the code is stored on one or more computer readable storage devices, further comprising a processor for execution of the code.