Patent ID: 9484365
Filing Date: 2016-11-01
CPC Classification: G02F,G09G,H01L

Claim Text:
1. A semiconductor device comprising: first to n-th transistors (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period; (n+1)-th to m-th transistors (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period; first to n-th signal lines; and (n+1)-th to m-th signal lines, wherein the first to m-th signal lines are parallel, wherein a distance between the n-th signal line and the (n+1)-th signal line is longer than a distance between the (n−1)-th signal line and the n-th signal line and is longer than a distance between the (n+1)-th signal line and the (n+2)-th signal line, and wherein one of a source terminal and a drain terminal of the n-th transistor is closer to the (n+1)-th transistor than the other of the source terminal and the drain terminal of the n-th transistor.