Patent ID: 9368499
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method of forming a plurality of gate electrode structures on a shared substrate comprising: forming a first gate dielectric device in a first region of a semiconductor substrate for one or more first voltage level transistors, wherein the first gate dielectric device comprises a grown gate dielectric layer formed on the shared substrate, a deposited gate dielectric layer formed on the grown gate dielectric layer, a first high-k gate dielectric layer deposited on the deposited gate dielectric layer, and a second high-k gate dielectric layer deposited on the first high-k gate dielectric layer; forming a second gate dielectric device in a second region of a semiconductor substrate for one or more second voltage level transistors, wherein the second gate dielectric device comprises the first high-k gate dielectric layer deposited on the shared substrate, and the second high-k gate dielectric layer deposited on the first high-k gate dielectric layer; forming a third gate dielectric device in a third region of a semiconductor substrate for one or more third voltage level transistors, wherein the third gate dielectric device comprises a base gate dielectric layer grown on the third region of the shared substrate and a second high-k gate dielectric layer deposited on the base gate dielectric layer; forming one or more gate conductor layers on the first, second, and third gate dielectric devices; and selectively etching the gate conductor layers and the first, second, and third gate dielectric devices to form a plurality of gate electrode structures on the first, second, and third regions of the shared substrate; where the first gate dielectric device has a combined thickness that is thicker than the second gate dielectric device, where the second gate dielectric device has a combined thickness that is thicker than the first gate dielectric device, and where the first voltage level is higher than the second voltage level which is higher than the third voltage level.