Patent ID: 9355714
Filing Date: 2016-05-31
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array comprising memory cells, each memory cell being able to store multi-bit data; word-lines connected to the memory cells, the word-lines being arranged in a first direction; bit-lines arranged in a second direction crossing the first direction, the bit-lines reading data from the memory cell array; and a control circuit controlling the operation of the memory cell array, the control circuit performs a first write operation of applying a first write voltage between a selected word-line and a channel of a selected memory cell, then, performs a verify operation of determining whether the first write operation is completed, and performs a second write operation of applying, if the write operation to the first threshold voltage is completed in the verify operation, a second write voltage lower than the first write voltage between the selected word-line and the channel.