Patent ID: 9418900
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method for forming fins for complementary metal oxide semiconductor (CMOS) devices, comprising: growing a SiGe layer followed by a silicon layer over a surface of a bulk Si substrate; patterning fin structures from the silicon layer and the SiGe layer; filling between the fin structures with a dielectric fill; forming trenches through the dielectric fill, the fin structures and into the substrate, the trenches including a cut perpendicular to the fin structures to expose end portions of the fin structures; blocking off a first region of the fin structures with a dielectric layer; removing the SiGe layer of the fin structures of a second region by selectively etching the fin structures from the end portions of the fin structures to form voids; filling the voids with dielectric material; exposing the silicon layer of the fin structures in the first and second regions; and thermally oxidizing the SiGe layer in the first region to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.