Patent ID: 9496216
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a plurality of first semiconductor chips comprising an uppermost first semiconductor chip on a board, the plurality of first semiconductor chips including respective ones of a plurality of data pads and respective ones of a plurality of power pads, and the plurality of data pads comprising a first data pad in the uppermost first semiconductor chip; a wiring layer on the uppermost first semiconductor chip, the wiring layer including a redistribution pattern and a redistribution pad; a second semiconductor chip on the uppermost first semiconductor chip, the second semiconductor chip being electrically connected to the redistribution pattern; a plurality of first conductive connections between two of the plurality of data pads; a second conductive connection between the uppermost first semiconductor chip and the second semiconductor chip; a third conductive connection between the second semiconductor chip and the board, wherein the redistribution pattern is between the second semiconductor chip and the board, wherein the redistribution pad comprise: wherein the second semiconductor chip is closer to the first redistribution pad than the third redistribution pad, and wherein one of the plurality of data pads is electrically connected to the board via the first redistribution pad, the second conductive connection, the second semiconductor chip, the second redistribution pad, the redistribution pattern, the third redistribution pad and the third conductive connection, sequentially.