Patent ID: 9478510
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. An integrated circuit, comprising: an interconnect region; a top interconnect level formed in the interconnect region, the top interconnect level including a connection pad; a dielectric layer formed over the top interconnect level, such that a portion of a top surface of the connection pad is exposed, while the dielectric layer overlaps a periphery of the connection pad, and such that a connection opening sidewall is formed at a boundary of the dielectric layer over the connection pad; a self-aligned under bump metal pad formed on the exposed portion of the top surface of the connection pad, such that the self-aligned under bump metal pad contacts the connection opening sidewall, and such that the self-aligned under bump metal pad does not contact a top surface of the dielectric layer; and a solder ball formed on a top surface of the self-aligned under bump metal pad, wherein the self-aligned under bump metal pad includes: at least one of a metal adhesion sub-layer and a metal blocking sub-layer, wherein the adhesion sub-layer if present is formed on the exposed portion of the connection pad, is continuous along the connection opening sidewall, and is less than one-third as thick as the dielectric layer, and the blocking sub-layer if present is continuous along the connection opening sidewall, and is less than one-half as thick as the dielectric layer; and a solder connection sub-layer formed over the adhesion sub-layer if present and the blocking sub-layer if present, wherein the solder connection sub-layer is at least one-half as thick as the dielectric layer.