Patent ID: 9263147
Filing Date: 2016-02-16
CPC Classification: G11C

Claim Text:
1. An apparatus for concurrent test of a set of flash memory banks, comprising: a memory data path module coupled to a test controller, the test controller being configured to generate a test stimulus and to check a response from the set of flash memory banks, the memory data path module comprising: a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; a set of comparators, corresponding to each of the set of flash memory banks, each comparator configured to generate a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks that indicates a state of the set of flash memory banks; a reduction logic configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed to match the width of a data bus of the test controller; a control logic configured to generate a control output in response to the test stimulus and the comparator output for selective programming across different flash bits of the set of flash memory banks; and a fail flag configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read from the set of flash memory banks in any access.