Patent ID: 9524970
Filing Date: 2016-12-20
CPC Classification: G11C,H01L

Claim Text:
1. An asymmetric semiconductor memory cell comprising: a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type; said floating body region comprising means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell; a first region having said first conductivity type, wherein said first conductivity type of said first region is and being in direct contact with said first conductivity type of said floating body region; a gate positioned above said floating body region; and a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having a second conductivity type selected from said n-type and said p-type conductivity type, said second conductivity type being different from said first conductivity type.