Patent ID: 9470755
Filing Date: 2016-10-18
CPC Classification: G01R,G06F

Claim Text:
1. A method, implemented by a computer, for performing physical scans of an integrated circuit by dividing an area of an integrated circuit into a 2-dimensional grid, the method comprising: a) determining a grid size of the 2-dimensional grid which includes the area of the integrated circuit and a number of flops within the 2-dimensional grid, the grid size having a first side length and a second side length; b) for each region of the grid, having a number of flops for the grid region, having one of a respective first side length and a respective second side length that is greater than one: c) repeating b)i)-b)iv) until said respective first side length is one and said respective second side length is one; and d) for each region of the grid wherein the respective first side length is one and the respective second length is one, providing logic circuitry for performing the physical scan.