Patent ID: 9299655
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. An integrated circuit, including: integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions; the integrated circuit portions being formed by a plurality of layers on the single die, the layers including a plurality of metal layers, a plurality of dielectric layers, and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions; and a discontinuous die seal around the rated circuit portions, the discontinuous die seal being the form of mutually spaced die seal portions separated by gaps disposed at locations corresponding to the at least one coupling region; wherein the discontinuous die seal is configured to restrict or block lines of sight from outside the die seal to any of the integrated circuit portions or any of the at least one coupling region to inhibit crack propagation thereto from outside the die seal.