Patent ID: 9484923
Filing Date: 2016-11-01
CPC Classification: G11C,H03K

Claim Text:
1. A signal transmission circuit suitable for DDR, adapted to drive a connecting pad, said signal transmission circuit comprising: a level shifting circuit, comprising: a buffer circuit, comprising: an output circuit, comprising: wherein, the up level shifter and the down level shifter adopt input and output (IO) devices to respectively output the first shift signal and the second shift signal; the up buffer unit, the down buffer unit, the pull-up circuit and the pull-down circuit adopt core devices; the second reference voltage is equal to the second operating voltage, and the first reference voltage is a difference between the DDR operating voltage and the second reference voltage, wherein the up level shifter comprises: a 1 a 2 a 3 a 4 a 5 wherein, the 1 an 11 a 12 a 13 a 14 a 15 a 16 a 17 an 18 a 19 a 20 wherein, the 11