Patent ID: 9269762
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a first inter-metal dielectric (IMD) layer over a substrate; a bottom plate in the first IMD layer; a second IMD layer over the bottom plate; a bottom electrode disposed on a bottom and sidewalls of a first opening in the second IMD layer; a dielectric layer in the first opening, the dielectric layer being adjacent to the bottom electrode, a portion of the dielectric layer contacting the second IMD layer; a top electrode in the first opening, the top electrode being adjacent to the dielectric layer in the first opening, wherein the portion of the dielectric layer is interposed between the top electrode and the second IMD layer; a top plate over the second IMD layer, the top plate being connected to the top electrode; a first metal contact in the first opening of the second IMD layer, wherein the first metal contact contacts the top electrode; a third IMD layer over the first metal contact, wherein the top plate is disposed in the third IMD layer; and a via disposed in the third IMD layer, the via connecting the top plate to the first metal contact.