Patent ID: 9412816
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate extending in a longitudinal direction; at least two nanowire patterns over the substrate; a gate electrode surrounding at least a part of the at least two nanowire patterns; and a gate dielectric film between the at least two nanowire patterns and the gate electrode in a direction substantially perpendicular to the longitudinal direction, wherein longitudinal widths of the at least two nanowire patterns become narrower in a direction away from the substrate and have different channel impurity concentrations; wherein the at least two nanowire patterns include: a first nanowire pattern having a first channel region at a first distance from the substrate and having a first channel impurity concentration and a first channel width, and a second nanowire pattern having a second channel region at a second distance from the substrate greater than the first distance, having a second channel impurity concentration higher than the first channel impurity concentration, and having a second channel width smaller than the first channel width; and wherein the at least two nanowire patterns further include a third nanowire pattern having a third channel region at a third distance from the substrate greater than the second distance, having a third channel impurity concentration higher than the second channel impurity concentration, and a third channel width smaller than the second channel width, wherein the first channel threshold voltage of the first channel region is substantially the same as the third channel threshold voltage of the third channel region.