Patent ID: 9507728
Filing Date: 2016-11-29
CPC Classification: G06F

Claim Text:
1. Apparatus for processing data comprising: bridge circuitry having a first port configured to transmit memory transactions of a first type, a second port configured to receive memory transactions of a second type and translation circuitry configured to translate between memory transactions of said first type and memory transactions of said second type; wherein said memory transactions of said first type specify X significant bits of address and A bits of attribute data, where X and A are both positive integer values; said memory transactions of said second type specify Y significant bits of address, where Y is a positive integer value and Y is greater than X; and said translation circuitry is configured to map at least some of said A bits of attribute data of a memory transaction of said first type to unused bits within said Y significant bit of address of a second type unused to represent said X significant bits of address of said memory transaction of said first type.