Patent ID: 9239502
Filing Date: 2016-01-19
CPC Classification: G02F,H01L

Claim Text:
1. A pixel structure, comprising: a substrate, a scan line, disposed on the substrate; a data line, disposed on the substrate, the scan line crossed to the data line, and the data line comprising a linear transmitting part and a cross-line transmitting part connected to each other, wherein the cross-line transmitting part crosses over the scan line; a first insulating layer, covering the scan line and the linear transmitting part and located between the scan line and the cross-line transmitting part; an active device, connected to the scan line and the data line, wherein the active device comprises: a second insulating layer, comprising an etching blocking pattern located on the oxide channel and the gate electrode, and an isolation pattern located on the linear transmitting part, wherein the etching blocking pattern is located within a boundary of the gate electrode and not in direct contact with the first insulating layer, the isolation pattern is contacting the first insulating layer, and the etching blocking pattern and the isolation pattern of the second insulating layer are not continuous and do not directly contact each other; a common electrode, disposed on the isolation pattern and located on the linear transmitting part, wherein the first insulating layer and the second insulating layer are disposed between the common electrode and the linear transmitting part, and the common electrode is electrically isolated from the data line; and a first pixel electrode, connected to the drain electrode.