Patent ID: 9412759
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming at least one gate structure on a substrate comprising a first device region and a second device region separated from one another by an insulating region, wherein the at least one gate structure overlies at least one channel portion of each of the first device region and the second device region and comprises a gate spacer, a U-shaped gate dielectric laterally surrounded by the gate spacer, and a gate conductive portion in contact with the U-shaped gate dielectric; forming a gate contact trench through a contact level dielectric layer and at least a portion of an interlevel dielectric (ILD) layer underlying the contact level dielectric layer, wherein the gate contact trench exposes a topmost surface and at least portions of outermost sidewalls of the gate conductive portion in a portion of the at least one gate structure located in the insulating region of the substrate; and forming a gate contact within the gate contact trench, wherein the gate contact is in contact with the topmost surface and the at least portions of the outermost sidewalls of the gate conductive portion located within the gate contact trench.