Patent ID: 9425064
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A process comprising: positioning a plurality of semiconductor wafers over a receptacle, the plurality of semiconductor wafers disposed within a holder configured to hold the plurality of semiconductor wafers in a vertically oriented configuration, the receptacle containing liquid solder, wherein a flux is disposed over the receptacle, each semiconductor wafer of the plurality of semiconductor wafers further comprising silicon; prior to transitioning the plurality of semiconductor wafers through the flux and a solder bath, pre-heating respective semiconductor wafers of the plurality of semiconductor wafers to a temperature that is twenty to thirty degrees Celsius below a melting point of the liquid solder to minimize breakage of the respective semiconductor wafers of the plurality of semiconductor wafers; transitioning the plurality of semiconductor wafers through the flux to apply the flux to an underbump metallurgy of respective semiconductor wafers of the plurality of semiconductor wafers; transitioning the plurality of semiconductor wafers into the solder bath; placing the plurality of semiconductor wafers into the receptacle to coat the underbump metallurgy with the liquid solder; and removing the plurality of semiconductor wafers from the receptacle to allow the liquid solder coated on the underbump metallurgy to solidify and form a solder bump on the underbump metallurgy of the plurality of semiconductor wafers.