Patent ID: 9514683
Filing Date: 2016-12-06
CPC Classification: G09G

Claim Text:
1. A gate driving circuit, connected to a row pixel circuit which comprises a row pixel driving circuit and a light emitting element connected to each other, the row pixel driving circuit comprising a driving transistor, a driving circuit and a compensation circuit, the compensation circuit being connected with a gate scanning signal, and the driving circuit being connected with a driving level; wherein the gate driving circuit comprises a row pixel control circuit, which is configured to provide the gate scanning signal to the compensation circuit and provide the driving level to the driving circuit, so as to control the compensation circuit to compensate for a threshold voltage of the driving transistor and control the driving circuit to drive the light emitting element, wherein the row pixel control circuit comprises a first control clock input end, a second control clock input end, a first control clock switch, and a second control clock switch; wherein the first control clock switch is configured to set up a connection between the first control clock input end and a first pulling-down node, in response to the first control clock signal being of a high level; wherein the second control clock switch is configured to set up a connection between the second control clock input end and a second pulling-down node, in response to a second control clock signal being of a high level; and wherein the first control clock signal and the second control clock signal are inverted, while an output level at the first pulling-down node and an output level at the second pulling-down node are inverted.