Patent ID: 9514836
Filing Date: 2016-12-06
CPC Classification: G11C

Claim Text:
1. A memory comprising: memory cells coupled in series, one of the memory cells being capable of storing one of four values; word lines coupled to gates of the memory cells; a sense amplifier including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first node, a first latch, and a second latch, a first terminal of the first transistor being electrically connected to memory cells, a second terminal of the first transistor being electrically connected to a first terminal of the second transistor and a first terminal of the fourth transistor, a second terminal of the second transistor being electrically connected to a first terminal of the third transistor, a second terminal of the third transistor being electrically connected to the first node and a second terminal of the fourth transistor, gate of the fifth transistor being electrically connected to the first node, a first terminal of the fifth transistor being electrically connected to a first terminal of the sixth transistor and a first terminal of the seventh transistor, a second terminal of the sixth transistor being electrically connected to the first latch, a second terminal of the seventh transistor being electrically connected to the second latch; and a controller configured to perform a verify operation including a first sensing operation and a second sensing operation, the verify operation being performed for one of the four values.