Patent ID: 9236099
Filing Date: 2016-01-12
CPC Classification: G11C

Claim Text:
1. An apparatus comprising: an interface configured to process a plurality of read/write operations to/from a memory; and a control circuit configured to (i) adjust an initial one of a plurality of read voltages in a read channel of the memory by shifting the initial read voltage an amount toward a center of a window, (ii) read a codeword from the memory a number of times and (iii) generate read data by an iterative decode of the codeword based on the reads, wherein (a) the window bounds a range of the read voltages, (b) each of the reads uses a different one of the read voltages according to a pattern, (c) the pattern is symmetrically spaced about the initial read voltage as shifted such that the read voltages of consecutive reads are on opposite sides of the initial read voltage and (d) the pattern fits in the window.