Patent ID: 9350339
Filing Date: 2016-05-24
CPC Classification: G06F,G11C,H01L,H03K

Claim Text:
1. A multi-die package comprising: a first die having a transmit clock tree feeding a first plurality of flip-flops; and a second die having a receive clock tree feeding a second plurality of flip-flops, wherein the transmit clock tree is configured to forward a clock signal to the receive clock tree; wherein individual flip-flops on the first die have a bit correspondence to respective individual flip-flops on the second die, each clock tree being unbalanced and configured to provide matched insertion delays for corresponding flip-flops on the first and second die, wherein the individual flip-flops of the first plurality of flip-flops have different insertion delays relative to each other, and wherein the individual flip-flops of the second plurality of flip-flops have different insertion delays relative to each other.