Patent ID: 9436211
Filing Date: 2016-09-06
CPC Classification: G06F,H04J,H04L

Claim Text:
1. A clock conversion apparatus comprising: an elastic store memory in which data are written in synchronization with a first clock and from which data are read out in synchronization with a second clock; a first phase shifter configured to generate a first plurality of different clocks by imparting a first variable phase shift to a divided clock of the first clock; a second phase shifter configured to generate a second plurality of different clocks by imparting a second variable phase shift to a divided clock of the second clock; a first selector configured to output a third clock from among the first plurality of different clocks generated by the first phase shifter by selecting the first variable phase shift in accordance with a number of times of stuff reception; a second selector configured to output a fourth clock from among the second plurality of different clocks generated by the second phase shifter by selecting the second variable phase shift in accordance with the number of times of stuff reception; a phase comparator configured to detect a phase difference between the third clock and the fourth clock; and an oscillator configured to generate the second clock having a frequency in accordance with the phase difference.