Patent ID: 9443618
Filing Date: 2016-09-13
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array configured to include a first main cell array, a first spare cell array, a second main cell array, and a second spare cell array each of which has internal cells that are selected in response to internal addresses, and an address mapping unit configured to map an external address as a first main internal address when the external address designates the first main cell array, map the external address as a first spare internal address when the external address designates the first spare cell array, map a calculation result as a second main internal address when the external address designates the second main cell array, and map the calculation result as a second spare internal address when the external address designates the second spare cell array; and wherein the calculation result is obtained by adding a given value to the external address, and wherein the given value is a value corresponding to one of a number obtained by subtracting a total number of the cells of the first spare cell array from a total number of cells of the first main cell array, a number obtained by subtracting a total number of the cells of the second spare cell array from a total number of cells of the second main cell array, or a number obtained by subtracting a sum of a total number of cells of the first spare cell array and a total number of cells of the second spare cell array from a sum of a total number of cells of the first main cell array and a total number of cells of the second main cell array and dividing the number obtained by 2; and wherein the first main internal address and the second main internal address have the same bits except for an uppermost one bit, the first spare internal address and the second spare internal address have the same bits except for an uppermost one bit, and the first main internal address and the first spare internal address have the same bits except for one bit; and wherein the internal addresses comprises the first main internal address, the first spare internal address, the second main internal address, and the second spare internal address; and wherein the external address is inputted in burst mode, and wherein the external address inputted in the memory cell array is consecutive across the first main cell array, the first spare cell array, the second main cell array and a second spare cell array, and wherein the first main internal address and the first spare internal address is consecutive across the first main cell array and the first spare cell array, the second main internal address and second spare internal address is consecutive across the second main cell array and the second spare cell array, and the first spare internal address and the second main internal address is non-consecutive across the first spare cell array and the second main cell array.