Patent ID: 9411584
Filing Date: 2016-08-09
CPC Classification: G06F

Claim Text:
1. A processor comprising: a first register comprising a first plurality of data fields, wherein each of the first plurality of data fields in the first register corresponds to an offset for a data element in a memory; a destination register comprising a second plurality of data fields corresponding to the first plurality of data fields, wherein a portion of each of the second plurality of data fields in the destination register is to store a bit-mask having a mask bit for each of the first plurality of data fields; a decode stage to decode a first instruction specifying a vector conflict operation and a data field size; and one or more execution units, responsive to the decoded first instruction, to: read the values of each of the data fields in the first register; for each data field of the first plurality of data fields in the first register, compare its corresponding offset with every less significant data field of the plurality of data fields to determine if they hold a matching offset, and for each data field of the second plurality of data fields in the destination register corresponding to a data field in the first register, set to a first value, any mask bits corresponding to a less significant data field in the first register holding an offset matching said corresponding data field in the first register, and set any other bits in the destination register to a second value.