Patent ID: 9319073
Filing Date: 2016-04-19
CPC Classification: G06F,H03M

Claim Text:
1. An apparatus comprising: a control circuit configured to read data from and write data to a memory configured to store two or more bits per cell; and an adaptive strength error correction code (ECC) decoder enabled to perform a plurality of different strength error correction code (ECC) decoding processes, wherein (i) after writing data to a least significant bit (LSB) page in the memory, the control circuit checks the data stored in the LSB page using a first strength error correction code (ECC) decoding process of the adaptive strength error correction code (ECC) decoder, and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page in the memory, the control circuit checks the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process of the adaptive strength error correction code (ECC) decoder.