Patent ID: 9235467
Filing Date: 2016-01-12
CPC Classification: G06F,H03M

Claim Text:
1. A method of providing log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder in a nonvolatile memory storage module, the method comprising: identifying an estimated bit-error-rate (BER) for the nonvolatile memory storage module; identifying a plurality of sets of soft-decision reference voltages, each of the plurality of sets of soft-decision reference voltages comprising a plurality of individual soft-decision reference voltages and each of the individual soft-decision reference voltages in each set of soft-decision reference voltages separated from each other by a distance equal to a selected soft-decision reference voltage partitioning value, wherein the selected soft-decision reference voltage partitioning value is different for each of the plurality of sets of soft-decision reference voltages; calculating a LLR (log likelihood ratio) introduced error value for each set of soft-decision reference voltages based upon the identified BER of the nonvolatile memory storage module, wherein the calculated LLR introduced error value represents an error introduced by the computation of the LLR for each set of soft-decision reference voltages; comparing the calculated LLR introduced error value for each set of soft-decision reference voltages to identify the set of soft-decision reference voltages having a smallest calculated LLR introduced error value; reading an LDPC encoded codeword stored in the nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword; accessing an LLR look-up table for the nonvolatile memory storage module to extract the LLRs from the LLR look-up table for each of the soft-decision bits; and providing the extracted LLRs to an LDPC decoder for decoding of the codeword.