Patent ID: 9239902
Filing Date: 2016-01-19
CPC Classification: G06F

Claim Text:
1. A method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design, the method comprising: generating a pattern for the layout based on the circuit design; determining, by a processor, if at least one layout rule is violated by an inclusion of the generated pattern in the layout, the at least one layout rule comprising a constraint on a relationship between a power line pattern and a device pattern in the layout, and the at least one layout rule being specified by comparing a predetermined threshold value with at least one of an estimated voltage drop along a signal path in a second layout different than the layout or an estimated current density on the signal path in the second layout, wherein the constraint comprises a minimum number of contacts per device or a minimum number of power vias per device; and modifying the layout if the at least one layout rule is violated.