Patent ID: 9443529
Filing Date: 2016-09-13
CPC Classification: G10L

Claim Text:
1. An integrated sensor-array processor, comprising: a plurality of sensor array time-domain input ports configured to receive sensor signals from a plurality of time-domain sensors; a sensor transform engine (STE) configured to create sensor transform data from the sensor signals and to apply sensor calibration adjustments; a plurality of transducer time-domain input ports configured to receive a plurality of time-domain transducer signals; a transducer output transform engine (TTE) configured to generate transducer output transform data from the transducer signals; the STE and TTE each being configured to respectively create the sensor transform data and transducer output transform data by use of a multichannel transform engine that converts multiple channels of digital time domain inputs into vectors of data with each vector including a set of transform domain bins representing non-uniform frequency spacing and a non-uniform time sampling output frame rate R, and in which each bin is a complex data value representing a phase and magnitude component of a bin center frequency F in a block of N time-domain inputs; a spatial filter engine (SFE) configured to apply one or more sets of suppression coefficients to the sensor transform data, to suppress target signals received from noise locations and/or amplification locations; a blocking filter engine (BFE) is configured to apply one or more sets of subtraction coefficients to the sensor transform data, to subtract the target signals from the sensor transform data; a noise reduction filter engine (NRE) configured to subtract noise signals from the BFE output; an inverse transform engine (ITE) configured to generate time-domain data from the NRE output; and one or more output ports configured to output the time-domain data.