Patent ID: 9349745
Filing Date: 2016-05-24
CPC Classification: G11C,H01L

Claim Text:
1. A memory device, comprising: a plurality of stacks of conductive strips having a depth direction along which adjacent conductive strips in a same stack are separated by dielectric material; a plurality of word lines over and orthogonal to the plurality of stacks of conductive strips, the plurality of word lines electrically coupled to a plurality of vertical gate columns acting as gates controlling current flow in the plurality of stacks of conductive strips, the plurality of word lines including a first word line and a second word line adjacent to each other; and the plurality of vertical gate columns between the plurality of stacks of conductive strips, the plurality of vertical gate columns including a first set of vertical gate columns electrically coupled to the first word line and a second set of vertical gate columns electrically coupled to the second word line, the first set of vertical gate columns staggered relative to the second set of vertical gate columns, control circuitry controlling the plurality of word lines as gates to control current flow in the plurality of stacks of conductive strips, and controlling nonvolatile memory operations.