Patent ID: 9293564
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device including: an active region through which a current flows when in an on-state; a termination structure portion surrounding the active region, which secures a predetermined breakdown voltage; a first parallel pn layer provided from the active region over to the termination structure portion, in which first-conductivity-type semiconductor regions and second-conductivity-type semiconductor regions are alternately disposed; and a second parallel pn layer disposed on the top of the first parallel pn layer, the method comprising: (a) forming the first parallel pn layer in a first formation step; (b) depositing a first-conductivity-type first semiconductor layer on a surface of the first parallel pn layer in a second formation step that further includes forming the second parallel pn layer by selectively introducing second-conductivity-type impurities into the first semiconductor layer; and forming first second-conductivity-type impurity regions in positions opposed in a depth direction to regions of the first parallel pn layer in which the second-conductivity-type semiconductor regions are formed; (c) forming a local insulating film on a surface of the first semiconductor layer in the termination structure portion so that an end portion of the local insulating film is positioned on the first second-conductivity-type impurity region, by heating in a first heat treatment at a low temperature effective to suppress diffusion of the first second-conductivity-type impurity regions; and (d) diffusing the first second conductivity type impurity regions by heating in a second heat treatment.