Patent ID: 9496863
Filing Date: 2016-11-15
CPC Classification: G05F,H03K

Claim Text:
1. A power gating circuit in an integrated circuit including a circuit block coupled to a virtual power supply line, the power gating circuit comprising: a first transistor coupled between a first power supply line and the virtual power supply line, the first transistor having a body coupled to the first power supply line; and a buffer configured to buffer a control signal to apply the buffered control signal to the first transistor, the buffer including a second transistor having a source coupled to a second power supply line and a body coupled to the first power supply line, wherein either a first high power supply voltage is applied to the first power supply line and a second high power supply voltage which is greater than the first high power supply voltage is applied to the second power supply line, or a first low power supply voltage is applied to the first power supply line, and a second low power supply voltage which is less than the first low power supply voltage is applied to the second power supply line.