Patent ID: 9240372
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A semiconductor die, comprising: a first bond pad, arranged in an outer periphery of the semiconductor die, connected to a first lead wire, wherein the first bond pad is configured to receive a reference voltage potential through the first lead wire; a second bond pad arranged in the outer periphery of the semiconductor die, between the first bond pad and an interior portion of the semiconductor die, such that the second bond pad is arranged inside of the first bond pad relative to the interior portion of the semiconductor die; a first via arranged in a substrate of the semiconductor die, wherein the first via is connected between the first bond pad and an interconnecting layer in the substrate of the semiconductor die; a second via arranged in the substrate of the semiconductor die, wherein the second via is connected between the interconnecting layer and the second bond pad such that the reference voltage potential, received by the first bond pad, is provided to the second bond pad through the first bond pad, the first via, and the second via; a third bond pad arranged in the interior portion of the semiconductor die, wherein the third bond pad is connected to the second bond pad using a second lead wire, and wherein the third bond pad is configured to receive the reference voltage potential through the second lead wire; and a circuit arranged in the interior portion of the semiconductor die, the circuit arranged between the second bond pad and the third bond pad below the second lead wire.