Patent ID: 9295159
Filing Date: 2016-03-22
CPC Classification: H01L,H05K,Y10T

Claim Text:
1. A method for fabricating a packaging substrate with an embedded semiconductor chip, comprising the steps of: providing a carrier board and forming an assisting layer with a plurality of apertures on the carrier board, the apertures being filled with a filling material; providing the semiconductor chip having an active surface with a plurality of electrode pads thereon and an opposite inactive surface; forming a plurality of bumps on the electrode pads, respectively, wherein the bumps correspond in position to the apertures, respectively, and are attached to the filling material in the apertures, thereby allowing the semiconductor chip to be coupled to the assisting layer; filling an adhesive member between the assisting layer and the semiconductor chip so as to encapsulate the bumps and the electrode pads; forming a first dielectric layer on the assisting layer so as to encapsulate the semiconductor chip, the first dielectric layer having a first surface for coupling to the assisting layer and an opposite second surface; removing the carrier board for exposing the assisting layer; removing the filling material and the bumps so as to form vias; and forming in each of the vias a first conductive via for electrical connection with a corresponding one of the electrode pads.