Patent ID: 9443791
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A method of forming a leadless packaged semiconductor device having a leadframe structure comprising an array leadframe sub-structures each having a semiconductor die arranged thereon, the method comprising: providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure, wherein the leadframe structure includes at least two die attach regions.