Patent ID: 9513658
Filing Date: 2016-12-06
CPC Classification: G06F,H03K

Claim Text:
1. A method, comprising: assessing, by one or more processors, one or more timing slack properties of input pins and output pins on each bit in a plurality of multi-bit clocked storage devices utilized in a design for an integrated circuit, wherein the plurality of multi-bit clocked storage devices comprise a common logical clock input; assigning, by the one or more processors, based on the assessed timing slack properties of the bits, each of the bits to one bit group selected from a plurality of bit groups; remapping, by the one or more processors, the bits within the plurality of multi-bit clocked storage devices such that at least one of the multi-bit clocked storage devices comprises two or more bits selected from one bit group; and applying one or more timing corrections to one or more of the multi-bit clocked storage devices, wherein at least one timing correction is applied to the at least one multi-bit clocked storage device that comprises the two or more bits selected from the one bit group.