Patent ID: 9484434
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method for forming a structure, the method comprising: forming a first crystalline semiconductor layer over a substrate, the first crystalline semiconductor layer being strained and having a first lattice constant; forming a second crystalline semiconductor layer on a top surface of the first crystalline semiconductor layer, the second crystalline semiconductor layer being relaxed and having a lattice constant different from the first lattice constant; forming a transistor including a gate electrode disposed above the second crystalline semiconductor layer, a sidewall spacer adjacent the gate electrode, and a channel region disposed below the gate electrode and at least partially in the second crystalline semiconductor layer; and creating a free surface above the channel region in at least one of the gate electrode or the sidewall spacer, wherein the free surface induces strain in at least a portion of the channel region disposed in the second crystalline semiconductor layer.