Patent ID: 9497864
Filing Date: 2016-11-15
CPC Classification: H01L,H05K,Y10T

Claim Text:
1. A circuit substrate, comprising: a stacked circuit structure having a first surface and a second surface opposite to the first surface; a first patterned inner conductive layer disposed on the first surface and having a plurality of first pads; a first patterned outer conductive layer disposed on the first patterned inner conductive layer and having a plurality of first conductive pillars, wherein each of the first conductive pillars is located on the corresponding first pad; a first dielectric layer covering the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer and having a plurality of first concaves, wherein each of the first concaves exposes a top and a side of the corresponding first conductive pillar, and the top and the side of the first conductive pillar are exposed for directly soldering a chip; a second patterned inner conductive layer disposed on the second surface and having a plurality of second pads; a second patterned outer conductive layer disposed on the second patterned inner conductive layer and having a plurality of second conductive pillars, wherein each of the second conductive pillars is located on the corresponding second pad; and a second dielectric layer covering the second surface, the second patterned inner conductive layer and the second patterned outer conductive layer and having a plurality of second concaves, wherein each of the second concaves exposes a top and a side of the corresponding second conductive pillar; wherein an outer diameter of each of the second conductive pillars is greater than an outer diameter of the corresponding second pad, and the corresponding second concave exposes a portion of the corresponding second pad.