Patent ID: 9324426
Filing Date: 2016-04-26
CPC Classification: G11C

Claim Text:
1. A resistive memory device, comprising: a two-dimensional array of resistive memory cells, each memory cell including a resistive memory element connected in series with a cell selector transistor, each memory cell being accessed by a word line, a bit line and a source line, wherein the resistive memory cells sharing a common word line form a row of the array and the resistive memory cells sharing a common bit line and a common source line form a column of the array; a write driver configured to apply write bias voltages to the bit line and the source line to write data to one or more resistive memory cells in the array selected for access, the write bias voltages being applied to program a resistance of the resistive memory element of each of the one or more selected resistive memory cells in response to the write data; and a sense amplifier configured to sense a signal difference between a reference signal and a sense node signal and to generate an output signal indicative of the signal difference, the sense node signal being related to a programmed resistance of the resistive memory elements of the one or more resistive memory cells in the array selected for access, wherein two or more memory cells in a column of the two-dimensional array sharing the same bit line and the same source line are configured to operate by its own word line in parallel as a merged memory cell, the write driver being configured to program the resistance of the resistive memory element of each of the two or more resistive memory cells in the merged memory cell simultaneously, and the sense amplifier being configured to read the programmed resistance of the resistive memory element of each of the two or more resistive memory cells in the merged memory cell simultaneously.