Patent ID: 9455273
Filing Date: 2016-09-27
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate having a main surface; a semiconductor layer which is formed over the main surface of the semiconductor substrate through a buried insulating film; a first n-well region and a second n-well region which are formed in the main surface of the semiconductor substrate and which extend in a first direction of the main surface; a dummy p-well region which is provided between the first n-well region and the second n-well region and which extends in the first direction; a first p-well region which is adjacent to the first n-well region on an opposite side of the dummy p-well region and which extends in the first direction; a second p-well region which is adjacent to the second n-well region on an opposite side of the dummy p-well region and which extends in the first direction; a first bit line and a second bit line each of which extends in the first direction; a plurality of memory cells each of which is connected to the first bit line and the second bit line; and a plurality of word lines which are connected to the plurality of memory cells, respectively, and each of which extends along a second direction crossing the first direction, wherein each of the plurality of memory cells includes: a first p-channel transistor which is provided in the semiconductor layer over the first n-well region, whose drain is connected to a first storage node, and whose gate is connected to a second storage node; a first n-channel transistor which is provided in the semiconductor layer over the first p-well region, whose drain is connected to the first storage node, and whose gate is connected to the second storage node; a second p-channel transistor which is provided in the semiconductor layer over the second n-well region, whose drain is connected to the second storage node, and whose gate is connected to the first storage node; a second n-channel transistor which is provided in the semiconductor layer over the second p-well region, whose drain is connected to the second storage node, and whose gate is connected to the first storage node; a third n-channel transistor which is provided in the semiconductor layer, and which electrically connects the first bit line to the first storage node; and a fourth n-channel transistor which is provided in the semiconductor layer, and which electrically connects the second bit line to the second storage node.