Patent ID: 9405546
Filing Date: 2016-08-02
CPC Classification: G06F

Claim Text:
1. An apparatus for non-blocking execution of a static scheduled processor, the apparatus comprising: a processor to process at least one operation using transferred input data, the processor comprising at least one functional unit (FU) to execute the at least one operation; and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the at least one FU selectively processes the transferred input data using at least one of a regular latency operation and an irregular latency operation, wherein, when an irregular operation is used to process the transferred input data and when a value resulting from a previous operation is absent in the input buffer, the at least one FU executes an operation and determines whether an extra latency occurs during execution of the operation, wherein, when an extra latency occurs during execution of the operation, the at least one FU outputs a dummy value and records a state bit corresponding to the output dummy value in the input buffer, and when the extra latency did not occur during execution of the operation, the at least one FU outputs a value resulting from the execution of the operation and records the output resulting value in the input buffer.