Patent ID: 9529949
Filing Date: 2016-12-27
CPC Classification: G06F

Claim Text:
1. A method for generating a circuit path comprising: generating a first nodal list that identifies a grid of macro nodes at a first resolution that is referenced to an area, wherein each macro node is associated with a particular portion of the area; modifying, by a computing device comprising a processor, the first nodal list to identify a reference macro node circuit path through the grid of macro nodes; generating a second nodal list that identifies a grid of micro nodes that is referenced to the area at a second resolution that is a greater resolution than the first resolution, wherein each macro node is associated with a different subset of the micro nodes; and modifying the second nodal list to identify at least one derived micro node circuit path that extends through a plurality of the micro nodes based on a coordinate offset with respect to the reference macro node circuit path to position the at least one derived micro node circuit path a coordinate distance from the reference macro node circuit path.