Patent ID: 9455016
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A semiconductor device, comprising: a memory cell array including a normal memory cell array and a redundancy memory cell array; a normal refresh counter configured to generate a normal address for performing a refresh operation to the normal memory cell array with a first period during a refresh mode; a redundancy refresh counter configured to generate a redundancy address for performing a refresh operation to the redundancy memory cell with a second period shorter than the first period; and a redundancy period control unit configured to generate a redundancy period signal for controlling activation of the normal refresh counter and the redundancy refresh counter so that when the redundancy period signal is activated, the normal refresh counter stops a first counting operation and the redundancy refresh counter starts a second counting operation, and when the redundancy period signal is deactivated, the normal refresh counter resumes the first counting operation and the redundancy refresh counter stops the second counting operation.