Patent ID: 9379214
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A metal-oxide semiconductor (MOS) transistor having reduced random threshold variations σVT through reduced channel length variability, the MOS transistor comprising: a gate having an oxide on its sides; a channel region; the gate being insulated from the channel region by a gate dielectric; an implanted source region, adjacent but spaced away from a first end, that is a source end, of the channel region; an implanted drain region, adjacent but spaced away from a second end, that is the drain end, of the channel region, the second end being opposite to the first end; an epitaxial source extension layer in a first recess partially formed within a part of the implanted source region and adjacent the source end of the channel region, the epitaxial source extension layer contacting the implanted source region and the source end of the channel region and extending below, but not extending under, any of the gate dielectric; an epitaxial drain extension layer in a second recess partially formed within a part of the implanted drain region and adjacent the drain end of the channel region, the epitaxial drain extension layer contacting the implanted drain region and the drain end of the channel region and extending below, but not extending under, any of the gate dielectric.