Patent ID: 9262268
Filing Date: 2016-02-16
CPC Classification: G06F

Claim Text:
1. An apparatus comprising: a memory comprising a plurality of memory devices, each memory device having a plurality of pages, wherein the plurality of pages in each memory device are classified into a plurality of different types of pages based on error rate variations among the pages in each memory device; and a controller configured to write user data and error-correction data to a super-page of the memory, wherein the super-page comprises a plurality of sub-pages including user data pages and one or more parity data pages, the plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using two or more types of pages, and calculation of the one or more parity data pages by the controller is divided into a number of portions corresponding to a number of types of pages used to store the sub-pages of the super-page.