Patent ID: 9406660
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A semiconductor die assembly, comprising: a package substrate including a plurality of bond pads arranged in a first array and a plurality of bond pads arranged in a second array that is adjacent and perpendicular to the first array of bond pads; a first semiconductor die attached to the package substrate; a support member attached to the package substrate, wherein the support member is separated from the first semiconductor die on the package substrate; a second semiconductor die having one region coupled to the support member and another region coupled to the first semiconductor die, wherein a portion of the first semiconductor die extends beyond a perimeter of the second semiconductor die; a first wirebond connector connecting a first bond pad of the first array of bond pads to the portion of the first semiconductor die; a second wirebond connector connecting a second bond pad of the second array of bond pads to the portion of the first semiconductor die; and a third wirebond connector connecting a third bond pad of the first array of bond pads to the second semiconductor die, wherein the third wirebond connector extends over the second wirebond connector, and wherein the third wirebond connector is transverse to the second wirebond connector.