Patent ID: 9438248
Filing Date: 2016-09-06
CPC Classification: H03K

Claim Text:
1. An n-bit counter circuit, comprising: a plurality of cascaded counter sub-modules including at least first and second cascaded counter sub-modules, the first counter sub-module being at least a lower-order counter sub-module relative to the second counter sub-module, the second counter sub-module being a higher-order counter sub-module relative to the first counter sub-module, as well as being a lower-order counter sub-module relative to subsequent cascaded counter sub-modules; and control logic coupled to the first counter sub-module, wherein: wherein: the CGIC is coupled between the first counter sub-module and the second counter sub-module and controls a clock input of the second counter sub-module; the CGIC comprises a latch having an output operatively coupled to a first input of a two-input AND gate, wherein: