Patent ID: 9253877
Filing Date: 2016-02-02
CPC Classification: H01L,H05K

Claim Text:
1. A wiring substrate comprising: a plurality of wiring layers and a plurality of insulation layers, the wiring layers and the insulation layers being alternately stacked; a plurality of via holes that is formed in the insulation layers; a plurality of first via wirings that is formed in the via holes to electrically connect the wiring layers to one another; a plurality of through holes that extends through a lowermost one of the insulation layers in a thickness direction, the lowermost insulation layer covering a lowermost one of the wiring layers; and a plurality of second via wirings that is formed in the through holes to define an identification mark, the identification mark being identifiable as a specific shape including a character, a symbol, or a combination thereof, wherein a lower surface of each of the second via wirings is exposed from a lower surface of the lowermost insulation layer and flush with a lower surface of the lowermost wiring layer.