Patent ID: 9508809
Filing Date: 2016-11-29
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate; a semiconductor layer having a buffer layer, a spacer layer, and a barrier layer sequentially stacked on the substrate; and first and second ohmic electrodes installed on an upper surface of the barrier layer to be separated from each other; and a third electrode installed between the first and second ohmic electrodes on the upper surface of the barrier layer, wherein each of the first and second ohmic electrodes includes: a portion formed on the upper surface of the barrier layer; and electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves, wherein the portion and the electrode portions are integrally formed, wherein a shape of an opening of each of the plurality of the grooves is rectangular, wherein the plurality of the grooves are arranged in a direction perpendicular to a longitudinal direction of the opening of each of the grooves, wherein the longitudinal direction of the opening of each of the grooves is perpendicular to an extending direction of the third electrode, and wherein both long sides of the opening of each of the plurality of the grooves are formed in a saw teeth shape.