Patent ID: 9444490
Filing Date: 2016-09-13
CPC Classification: G06F,H03M

Claim Text:
1. A method of operating a data compression circuit, the method comprising: receiving and storing a plurality of data blocks output from a input data register until a cache is full; writing the data blocks, which have been stored in the cache, to a buffer memory when the cache is full; performing forced encoding on each delay-adjusted data block output from the input data register regardless of repetitiveness of each delay-adjusted data block without determining a repetitiveness of the delay-adjusted data blocks, wherein the writing the data blocks to the buffer memory comprises writing each of the data blocks to one of a plurality of memories respectively having addresses allocated using an interleaving method, wherein the buffer memory includes the plurality of the memories, wherein the input data register receives an input data stream including the data blocks, adjusts a delay of each of the data blocks using delay circuits, and generates a plurality of delay-adjusted data blocks, and wherein the delay circuits are connected between an input of the cache and an input of the compressed-data generation circuit.