Patent ID: 9263574
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate, having a first conductivity type; a semiconductor layer formed over the semiconductor substrate, having the first conductivity type; a well region disposed in a portion of the semiconductor layer, having a second conductivity type opposite to the first conductivity type; a plurality of first doped regions of the first conductivity type vertically and separately disposed in various portions of the well region, wherein a pitch is between the adjacent first doped regions; a second doped region of the second conductivity type disposed in a portion of the well region, wherein the second doped region is adjacent to the first doped regions; an isolation element disposed in a portion of the top-most one of the first doped regions; a third doped region of the first conductivity type disposed in a portion of the top-most one of the first doped regions, being adjacent to the isolation element; a fourth doped region of the first conductivity type disposed in a portion of the second doped region; an insulating layer overlying a portion of the third doped region, the isolation element, a portion of the second doped region, and a portion of the fourth doped region; and a conductive layer overlying a portion of the insulating layer.