Patent ID: 9331080
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: an N-type fin and a P-type fin on a substrate; a first gate electrode configured to cross the N-type fin and cover a side surface of the N-type fin; a second gate electrode configured to cross the P-type fin and cover a side surface of the P-type fin; a first source/drain on the N-type fin adjacent to the first gate electrode; a second source/drain on the P-type fin adjacent to the second gate electrode; a buffer layer on a surface of the second source/drain, the buffer layer including a material different from the second source/drain; an interlayer insulating layer on the buffer layer and the first source/drain; a first plug connected to the first source/drain, the first plug passing through the interlayer insulating layer; and a second plug connected to the second source/drain, the second plug passing through the interlayer insulating layer and the buffer layer.