Patent ID: 9292426
Filing Date: 2016-03-22
CPC Classification: G06F,G11C

Claim Text:
1. A system comprising: a dynamic random access memory (DRAM) device capable of an external refresh or self-refresh mode, wherein a self-refresh command within the DRAM is configured to trigger refresh of a specific number of multiple rows of the DRAM; a memory controller operatively coupled to the DRAM device; wherein when the memory controller sends a signal to the DRAM device configured to indicate the self-refresh mode is to be aborted, if the DRAM device is configured for a fast exit from the self-refresh, responsive to receipt of the signal from the memory controller, the DRAM device configured to abort a self-refresh command and exit from the self-refresh to the external refresh prior to a completion within the DRAM of refresh of the specific number of multiple rows, and if the DRAM device is not configured for a fast exit from the self-refresh, responsive to receipt of the signal from the memory controller, the DRAM device configured to not abort a self-refresh command and not exit from the self-refresh prior to completion within the DRAM of refresh of the specific number of multiple rows; and wherein the memory controller is configured to issue at least an extra DRAM external refresh command upon causing the DRAM device to abort the self-refresh mode prior to completion of the self-refresh command.