Patent ID: 9466794
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method of making a resistive random access memory (RRAM) structure cell array, the method comprising: forming a plurality of transistors on a semiconductor substrate; depositing a first RRAM stop layer; etching a bottom electrode via in the first RRAM stop layer; depositing a bottom electrode layer in the bottom electrode via and over the first RRAM stop layer; depositing a hardmask and a photoresist pattern; etching the bottom electrode layer to form a bottom electrode having a non-planar portion with an apex, the etching the bottom electrode layer to form the bottom electrode comprising an anisotropic etch process and an isotropic etch process; depositing a resistive material layer, a capping layer, and a top electrode layer over the bottom electrode; forming a top electrode by patterning and etching the top electrode layer, the capping layer and the resistive material layer; and depositing a second RRAM stop layer and a dielectric layer.