Patent ID: 9356018
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate; a first gate structure and a second gate structure on the substrate; a source/drain region adjacent to the first gate structure; an interlayered insulating layer on the source/drain region and the first and second gate structures, wherein the interlayered insulating layer comprises a first interlayered insulating layer and a second interlayered insulating layer on the first interlayered insulating layer; a source/drain contact hole extending through the interlayered insulating layer and exposing the source/drain region; a trench in the interlayered insulating layer, the trench exposing a top surface of the second gate structure; a source/drain contact plug in the source/drain contact hole and in contact with the source/drain region; and a resistor pattern in the trench and in contact with a top surface of the second gate structure.