Patent ID: 9515169
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A method of fabricating a FinFET, comprising: a. providing a substrate ( b. forming a fin ( c. forming a channel protective layer ( d. forming a shallow trench isolation ( e. forming a sacrificial gate stack ( f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack ( h. removing the sacrificial gate stack ( i. covering a portion of the semiconductor structure which is formed in the foregoing steps with a photoresist layer ( j. thinning or removing a portion of the spacer ( k. removing the photoresist layer ( l. planarizing the semiconductor structure formed by the foregoing steps to expose the channel protective layer (