Patent ID: 9507724
Filing Date: 2016-11-29
CPC Classification: G06F

Claim Text:
1. A memory access processing method executed by one or more processors included in an information processing device, the memory access processing method comprising: storing, in a cache memory, a plurality of pages stored in a main memory; storing the plurality of pages in a buffer memory, each of the plurality of pages being associated with an identifier indicating whether the each of the plurality of pages being a zero page to be zero-cleared; allocating a page to be set to the zero page from among the plurality of pages, when a page fault occurs during execution of an access to the cache memory and execution of a process is stopped; updating an identifier corresponding to the allocated page to an identifier indicating the allocated page being the zero page; resuming the execution of the process; controlling an access to the cache memory, based on the identifier for each of the plurality of pages stored in the buffer memory; and executing initialization of a page corresponding to the allocated page and is included in the main memory.