Patent ID: 9455736
Filing Date: 2016-09-27
CPC Classification: H03M

Claim Text:
1. A ΔΣ modulator for converting an m-value (m: an integer of 3 or more) digital signal into an n-value (n: an integer of 2 or more smaller than m) digital signal and outputting the n-value output signal, the ΔΣ modulator comprising: a loop filter including a plurality of cascaded integrators each having a subtractor at its input, for inputting the m-value digital signal into the subtractor at a first integrator in the plurality of cascaded integrators; an n-value quantizer for inputting a first output signal output from the loop filter and outputting a second output signal that is the n-value digital signal, the first output signal based on an output of a last integrator in the plurality of cascaded integrators; and a selecting device for inputting the first output signal and the second output signal therein and selecting between feeding back the first output signal and the second output signal based on the first output signal and not based on outputs of the first integrator to next-to-last integrator in the plurality of cascaded integrators, and feeding back the first output signal to all of the subtractors of the loop filter when an absolute value of the first output signal is a predetermined value or more, and feeding back the second output signal to all of the subtractors of the loop filter when the absolute value of the first output signal is less than a predetermined value, wherein the predetermined value in the selecting device is set to be larger than a maximum value of an absolute value of a quantization value to be obtained by the n-value digital signal.