Patent ID: 9477423
Filing Date: 2016-10-25
CPC Classification: G06F,G11C

Claim Text:
1. A data storage system comprising: a host system, the host system including at least one host processor that controls operations of the host system and a host memory device that stores data and computer instructions that are used by the host processor; and a solid state drive (SSD) device interfaced with the host system, the SSD device including an SSD controller and at least one nonvolatile memory (NVM), the NVM including at least a first flash memory having a plurality of flash cells for storing data, the first flash memory including reference voltage determination logic, the SSD controller including at least one SSD processor and at least one buffer, the SSD controller receiving write data from the host system to be programmed into flash cells of the NVM, the SSD controller buffering the write data in the buffer prior to programming the write data into the flash cells, the buffered write data comprising at least a first most significant bit (MSB) page of data and at least a first least significant bit (LSB) page of data, the SSD controller sending the first LSB page of data to the first flash memory and maintaining a copy of the first LSB page of data in a temporary memory, and wherein subsequent to sending the first LSB page of data to the first flash memory the SSD controller sends the copy of the first LSB page of data and sends the first MSB page of data to the first flash memory, and wherein the reference voltage determination logic uses the copy of the first LSB page of data and the first MSB page of data to determine reference voltage ranges to be programmed into a first MSB page of the flash cells of the first flash memory.