Patent ID: 9349809
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a silicon-germanium (SiGe) layer on a semiconductor-on-insulator (SOI) layer, the SOI layer is on an insulator layer; oxidizing the SiGe layer using a Ge-condensation process, such that germanium atoms are displaced from the SiGe layer into the SOI layer and the SiGe layer becomes an oxidized semiconductor layer, the SOI layer having the displaced germanium atoms is a strained SiGe layer; removing the oxidized semiconductor layer from above the strained SiGe layer; forming first trenches through a hardmask and into the strained SiGe layer, the hardmask is directly on the strained SiGe layer, edges of the strained SiGe layer are exposed by the first trenches, the edges of the strained SiGe layer are relaxed; forming barrier layers in the first trenches; forming a second trench by removing the hardmask; and growing a III/V semiconductor layer in the second trench, the III/V semiconductor layer is grown on the strained SiGe layer having relaxed edges.