Patent ID: 9503089
Filing Date: 2016-11-22
CPC Classification: G11C,H03K,H04N

Claim Text:
1. An integrated circuit comprising a plurality of N adjacent identical blocks indexed by an index j, a current block being connected to a preceding block and to a following block, each block comprising an identification circuit comprising: N ordered inputs indexed i, which inputs are connected to the N outputs of the preceding block of same index; and N ordered outputs indexed i, which outputs are connected to the N inputs of the following block of same index; each input i for i≠N of the current block is connected by a routing line indexed i to the output i+1 of the current block; a last input N of the current block is not connected to any output of said current block; and a first output each block further comprising: the connection pad being coupled to the buses via the identification circuit and the logic gates so that: