Patent ID: 9524870
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming a plurality of line patterns over a first region of an etch target layer and a pre-pad pattern over a second region and a third region of the etch target layer; forming a plurality of pillars over the line patterns and a sacrificial pad pattern over the pre-pad pattern of the second region; forming an open mask which caps a sidewall and a top surface of the sacrificial pad pattern; forming a plurality of first spacers over sidewalls of the pillars such that the first spacers contact one another and form a plurality of first pre-openings therebetween; forming a second spacer over a sidewall of the open mask; removing the pillars to form a plurality of second pre-openings; cutting the line patterns through the first pre-openings and the second pre-openings, and forming a plurality of cut patterns over the first region; etching the pre-pad pattern using the sacrificial pad pattern as an etch mask, and forming a pad pattern over the second region; and etching the etch target layer using the cut patterns and the pad pattern as an etch mask, to define first patterns and a second pattern over the first region and the second region, respectively.