Patent ID: 9294354
Filing Date: 2016-03-22
CPC Classification: G06F,H04L

Claim Text:
1. A method, comprising: generating a network on chip (NoC) from a specification, the specification comprising a plurality of traffic profiles and requirement information for each of the plurality of traffic profiles, wherein the NoC is configured to satisfy one or more requirements indicated in the requirement information of the each of the plurality of traffic profiles in the specification; wherein the requirement information for each of the plurality of traffic profiles comprises at least one of: a bandwidth requirement, a latency requirement, and a Quality of Service (QoS) requirement, protocol and dependency requirements between various messages, clock frequency requirements of System on Chip (SoC) agents, and power domain and power sequence requirements of the SoC agents; wherein the specification comprises subset information indicative of one or more subsets of the plurality of traffic profiles that can co-exist during a same time window; wherein the generating the NoC from the specification is performed automatically based on a dependency graph from a deadlock avoidance process and a consolidation of the plurality of traffic profiles from a topology design process.