Patent ID: 9324437
Filing Date: 2016-04-26
CPC Classification: G11C

Claim Text:
1. A system for controlling a memory array comprising a first string of memory cells and a second string of memory cells, the system comprising: a group of control transistors for controlling the first and second strings of memory cells, the group of control transistors comprising: a first string select transistor, a first upper ground select transistor, and a first ground select transistor, each operably connected to the first string of memory cells; and a second string select transistor, a second upper ground select transistor, and a second ground select transistor, each operably connected to the second string of memory cells, wherein the first string select transistor is operable to connect the first string of memory cells to a bit line; and wherein the second string select transistor is operable to connect the second string of memory cells to the bit line; and a controller operable to trim the first and second string select transistors, the first and second upper ground select transistors, and the first and second ground select transistors, thereby changing the threshold voltages of the control transistors that are trimmed, wherein the controller is further operable to inhibit programming of the second upper ground select transistor during a time when the first upper ground select transistor is trimmed.