Patent ID: 9291665
Filing Date: 2016-03-22
CPC Classification: G01R

Claim Text:
1. A test structure of a semiconductor wafer, the test structure comprising: a series of electrical units connected electrically in series output-to-input in an open loop configuration, the series of electrical units configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit, and such that each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates, wherein the series of electrical units is a series of latches, and wherein each latch of the series of latches comprises two pairs of cross-coupled FETs, wherein a gate of a first pair of the FETs is connected to a drain-to-drain connection of the second pair of the FETs, and a gate of the second pair of the FETs is connected to a drain-to-drain connection of the first pair of the FETs.