Patent ID: 9257337
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; wherein the first wafer comprises: a first semiconductor substrate comprising a plurality of first components therein; and a first interconnection layer on the first semiconductor substrate, wherein the first interconnection layer is electrically connected to the first components, providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; wherein the second wafer comprises: a second semiconductor substrate comprising a plurality of second components therein; and a second interconnection layer on the second semiconductor substrate, wherein the second interconnection layer is electrically connected to the second components, bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit, wherein forming the at least a conductive through via in the second wafer comprises: