Patent ID: 9231600
Filing Date: 2016-01-05
CPC Classification: H03L,H04L

Claim Text:
1. A clock generator unit to generate a target clock signal having a target frequency, the clock generator unit comprising: a Fractional-N phase-locked loop (FNPLL) circuit having: an Integer-N PLL (INPLL) circuit having second phase detector circuitry and second VCO circuitry operationally connected to the second phase detector circuitry, the second phase detector circuitry having an INPLL reference input terminal and an INPLL feedback input terminal, the INPLL reference input terminal to receive the intermediate clock signal, the second VCO circuitry to output the target clock signal, the INPLL circuit being configured to have an INPLL bandwidth that filters out Phase Noise generated by the second VCO circuitry, the INPLL feedback input terminal configured to receive an INPLL feedback signal that is a function of the target clock signal, the FNPLL feedback input terminal configured to receive a FNPLL feedback signal that is also function of the target clock signal.