Patent ID: 9529959
Filing Date: 2016-12-27
CPC Classification: G06F,H01J

Claim Text:
1. A method for pattern correction for electron-beam (e-beam) lithography, comprising: receiving, by a processor, a computer file including an integrated circuit (IC) layout, the IC layout including a plurality of patterns; classifying, by the processor, each pattern of the plurality of patterns according to a plurality of pattern types; performing, by the processor, model fittings to determine a plurality of models for the plurality of pattern types respectively, the plurality of models including a first model for a first pattern type and a second model for a second pattern type; performing, by the processor, a pattern correction to the integrated circuit (IC) layout using at least the first model and the second model of the plurality of models to generate a corrected IC layout using the first model to correct a first classified pattern and using the second model to correct a second classified pattern, wherein the first and second models are different; determining that an error of one of the model fittings is outside a predetermined range; modifying a corresponding model and performing another pattern correction using the modified corresponding model; providing the corrected IC layout to an e-beam lithography tool, the corrected IC layout including a corrected first classified pattern and a corrected second classified pattern, wherein at least one of the corrected first classified pattern and the corrected second classified pattern is generated using the modified corresponding model; and writing the corrected IC layout to an e-beam sensitive resist layer using an e-beam lithography tool.