Patent ID: 9478548
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: forming a preliminary isolation pattern to define a plurality of active patterns of a substrate that are spaced apart from each other, each of the active patterns having a first contact region at a central portion thereof and second and third contact regions at edge portions thereof on opposite sides of the central portion, respectively; forming buried gate structures in upper portions of the preliminary isolation pattern and the active patterns, each of the buried gate structures extending in a first direction; forming a first insulation layer on the preliminary isolation pattern and the active patterns; etching away a portion of the first insulation layer on the first contact region of one of the active patterns and an upper portion of the first contact region thereunder to form a preliminary first opening having a bottom at which the first contact region is exposed and sides at which an upper portion of preliminary the isolation pattern defining the first contact region is exposed; etching away said upper portion of the preliminary isolation pattern exposed at the sides of the preliminary first opening such that two of the active patterns adjacent to opposites sides of said one of the active patterns, respectively, in the first direction and two of the buried gate structures adjacent one another in a second direction are exposed, and to thereby form a second opening, the second opening exposing a side surface of each of said two of the active patterns in the first direction and exposing said two of the buried gate structures in the second direction; forming an insulation pattern along sides of the second opening; and forming a wiring structure contacting the first contact region in the second opening.