Patent ID: 9401197
Filing Date: 2016-07-26
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor device, comprising: a clock generator configured to generate a clock signal; a clock output terminal, connected to the clock generator and configured to output the clock signal; a command generator circuit, configured to generate commands; an address generator circuit, configured to generate addresses; a plurality of command/address terminals; a command/address buffer having an output connected to the plurality of command/address terminals, the command/address buffer being connected to the command generator circuit and the address generator circuit to transmit command and address signals externally from the semiconductor device via the plurality of command/address terminals; a phase controller configured to control the command/address buffer to transmit a sequence of n training patterns via the plurality of command/address terminals, n being an integer greater than 2, the phase controller configured to adjust a phase of at least some of the n training patterns with respect to the clock signal; a read enable circuit configured to generate a read enable signal; a first terminal connected to the read enable circuit to transmit the read enable signal during a time when the sequence of n training patterns is transmitted; data terminals; and a data buffer connected to the data terminals, wherein the phase controller is configured to adjust a phase of command and address signals with respect to the clock signal in response to first information received by the data buffer via the data terminals.