Patent ID: 9268898
Filing Date: 2016-02-23
CPC Classification: G06F

Claim Text:
1. A method, comprising: associating, using a processor, each partition of a plurality of partitions of a circuit design with a probability distribution; wherein each partition is a portion of the circuit design; wherein for each partition, the associated probability distribution specifies a non-constant switching rate of an output of the partition indicating a variance in power consumption of the partition; and calculating, using the processor, an output probability distribution specifying a variance in power consumption of the circuit design according to the probability distribution of each partition of the circuit design; wherein the circuit design is used to implement an electronic circuit and is in the form of a netlist or a hardware description language; wherein each partition is a clock region or a circuit module; and wherein calculating the output probability distribution specifies the variance in power consumption of the circuit design using Monte Carlo simulation, the Monte Carlo simulation implements random point calculations for the partitions, and each partition point calculation is independent of other partition point calculations.