Patent ID: 9514041
Filing Date: 2016-12-06
CPC Classification: G06F

Claim Text:
1. A memory controller, comprising: a front-end unit that issues an invalidation request in response to receiving a command from a host, the command including a logical address information; an address translation unit that stores a correspondence relationship between a logical address and a physical address; an invalidation command processing unit that registers, in a reservation table, a first logical address associated with the invalidation request and issues an invalidation start request in response to receiving the invalidation request as the logical address for which an invalidation process is not completed, and issues a completion notification to the front-end unit upon completion of registration of the first logical address; and an internal processing unit that starts the invalidation process in response to receiving the invalidation start request, the invalidation process including dissolving a correspondence relationship between the first logical address and first physical address in the address translation unit in a predetermined order by referencing the first logical address registered in the reservation table, wherein, in a case where a logical address corresponding to first stored data is included in the first logical address, the internal processing unit dissolves a correspondence relationship of the logical address corresponding to the first stored data in the address translation unit preferentially over the predetermined order, and wherein the front-end unit transmits, to the host, a completion response, which indicates the completion of the command in response to receiving the completion notification, before the internal processing unit completes dissolving all of the correspondence relationship between the first logical address and the first physical address.