Patent ID: 9306567
Filing Date: 2016-04-05
CPC Classification: G06F,G11C,H03K

Claim Text:
1. A non-volatile memory device comprising: programmable register circuitry to store an identifier value that distinguishes the non-volatile memory device from one or more other non-volatile memory devices within a memory system; a signaling interface to receive a selector address in association with a memory access command, the signaling interface including at least one input/output (I/O) node to be coupled to a bidirectional signaling line; on-die termination circuitry coupled to the I/O node and configurable in any one of a plurality of states, including a first state and a second state, wherein in the first state, a first termination resistance is switchably coupled between the I/O node and a supply voltage line; and control circuitry to compare the selector address with the identifier value and, based at least in part on whether the selector address matches the identifier value, to (i) transition the on-die termination circuitry from one of the first and second states to the other or (ii) maintain the on-die termination circuitry in one or the other of the first and second states.