Patent ID: 9503073
Filing Date: 2016-11-22
CPC Classification: H01L,H03K

Claim Text:
1. A power semiconductor device, comprising: an output transistor connected between a power supply terminal and an output terminal; a first discharge transistor having a drain connected with a first node connected to a gate of the output transistor and a source connected to the output terminal; a second discharge transistor having a drain connected with the first node, wherein a source and a back gate of the second discharge transistor are connected with a second node; a countercurrent prevention device connected between the second node and a third node to prevent a current flow from the third node to the second node, a control circuit configured to control charging and discharging of the first node, an ON/OFF condition of the first discharge transistor, an ON/OFF condition of the second discharge transistor, and a connection between the third node and a ground terminal, in response to an input signal inputted to an input terminal, wherein, when the input signal is activated, the control circuit turns on a transistor connected between the third node and the ground terminal, and the control circuit further controls, in response to an occurrence of a load abnormality, the charging of the first node, the ON/OFF condition of the first discharge transistor, and the ON/OFF condition of the second discharge transistor, and wherein, when the input signal is deactivated, the control circuit stops the charging of the first node, turns on the first discharge transistor, sets a gate level of the second discharge transistor to a high level, and turns off the transistor connected between the third node and the ground terminal.