Patent ID: 9280199
Filing Date: 2016-03-08
CPC Classification: G06F,Y02D

Claim Text:
1. An image processing apparatus including a Peripheral Component Interconnect Express bus, comprising: a first controller configured to switchably operate as either a root complex or an endpoint of Peripheral Component Interconnect Express and perform control of the image processing apparatus and first processing for data; a second controller, connected to said first controller via the Peripheral Component Interconnect Express bus, configured to, upon receiving power supply, be operated as a single root complex in the image processing apparatus and to be exclusively used for performing second processing for data; a printing unit configured to print on a printing medium; a setting unit configured to set said first controller as a single root complex in the image processing apparatus or an endpoint, and a shifting unit configured to shift an operation mode to a sleep mode in a case where no data has been received, or no operation has been performed on the image processing apparatus within a predetermined time, wherein while said second controller receives power supply, said first controller is operated as an endpoint of the Peripheral Component Interconnect Express by setting of said setting unit, and said second controller is operated as a single root complex in the image processing apparatus, in a case where power supply to said second controller and said printing unit is turned off, said first controller is operated as a single root complex in the image processing apparatus by setting of said setting unit, and in a case where said second controller operates as a single root complex in the image processing apparatus, the data for which the second processing has been performed is transferred from said second controller to said first controller via the Peripheral Component Interconnect Express bus.