Patent ID: 9529956
Filing Date: 2016-12-27
CPC Classification: G06F,H01L

Claim Text:
1. A method, comprising: providing a first integrated circuit design layout that includes a first active region, a second active region, a first contact feature, a second contact feature and an isolation feature, wherein a portion of the first active region is disposed between the first contact feature and the isolation feature, and a portion of the second active region is disposed between the second contact feature and the isolation feature; adding a first supplementary active region adjacent to the portion of the first active region disposed between the first contact feature and the isolation feature to form a second integrated circuit design layout, wherein a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm; determining whether a first distance between the portion of the second active region and the first supplementary active region is smaller than a threshold value; removing a portion of the first supplementary active region if the first distance is smaller than the threshold value; and forming an integrated circuit device by the second integrated circuit design layout.