Patent ID: 9406565
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method for fabricating an integrated circuit comprising: forming a gate electrode structure overlying a semiconductor substrate; forming sidewall spacers on opposite sides of the gate electrode structure; thermally oxidizing a surface of the semiconductor substrate to form a first sacrificial oxide layer overlying the semiconductor substrate, wherein the first sacrificial oxide layer is formed after forming the gate electrode structure and after forming the sidewall spacers, and wherein the sacrificial layer is only formed on the surface of the semiconductor substrate or epitaxially-formed semiconductor regions formed therein; patterning a first implant mask overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure; implanting conductivity determining ions into the semiconductor substrate, through the first sacrificial oxide layer; and removing the first implant mask and the first sacrificial oxide layer after implanting the conductivity determining ions into the semiconductor substrate.