Patent ID: 9385121
Filing Date: 2016-07-05
CPC Classification: G11C,H01L,H03K,H03L

Claim Text:
1. An integrated circuit, comprising: a plurality of first transistors having controllable source-drain current paths coupled between a first and second node, the first transistors having a source drain doping profile with extension regions that extend in a lateral direction under a gate electrode of the first transistors, the first transistors configured to selectively couple a first output node to the first or second node in response to one or more input signals, the first transistors being formed in a substrate and having drawn gate lengths of less than one micron; and at least one tipless transistor formed in the substrate and having a source-drain current path coupled between the first node and the second node, the tipless transistor having a source drain vertical doping profile without extension regions that extend in a lateral direction under a gate electrode of the tipless transistor, the tipless transistor being configured to selectively couple a second output node to the first or second node in response to the one or more input signals, the tipless transistor having a drawn gate length of less than one micron.