Patent ID: 9257336
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method of plating a through-substrate via (TSV) hole in a substrate, the TSV hole comprising an open end terminating at a conductive pad, a stack of wiring levels superimposed to one another positioned on top of the conductive pad, and a plurality of chip interconnects configured on a top surface of an upper wiring level, the method comprising: attaching a conductive handler to a plurality of temporary solder contacts that are connected to the plurality of chip interconnects such that an air gap is formed between the handler and the substrate; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive handler to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive handler, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.