Patent ID: 9407265
Filing Date: 2016-08-02
CPC Classification: G11C,H03K

Claim Text:
1. A circuit, comprising: signal assist circuitry configured to assist with pulling a signal on a signal line towards a logical low signal level and to assist with pulling the signal on the signal line towards a logical high signal level, wherein the signal on the signal line has one of the logical low signal level and the logical high signal level depending on an output of predetermined circuitry, wherein the signal assist circuitry comprises: a first assist circuit configured to couple a first node of the signal line to a first supply node for supplying the logical high signal level following a pullup transition of the signal from the logical low signal level towards the logical high signal level, and configured to provide a floating signal level to the first node following a pulldown transition of the signal from the logical high signal level towards the logical low signal level; and a second assist circuit configured to couple a second node of the signal line to a second supply node for supplying the logical low signal level following the pulldown transition, and configured to provide a floating signal level to the second node following the pullup transition; wherein the second assist circuit comprises a transistor having a plurality of terminals and a gate, wherein one of the plurality of terminals directly couples to the second node of the signal line.