Patent ID: 9396790
Filing Date: 2016-07-19
CPC Classification: G11C

Claim Text:
1. A system comprising: a plurality of isolated power domains comprising a memory cell power domain, a write power domain and a read power domain, wherein: a memory cell comprising a first inverter and a second inverter, a first node of the memory cell is electrically coupled to an input node of the second inverter and an output node of the first inverter and a second node of the memory cell is electrically coupled to an input node of the first inverter and an output node of the second inverter, a power supply node of the first inverter and the second inverter being electrically coupled to the memory cell reference voltage node; a write bit line electrically coupled to the first write domain node or the reference voltage of the memory cell power domain; a complementary write bit line electrically coupled to the second write domain node or the reference voltage of the memory cell power domain; a first write access transistor having a source electrically coupled to the first node, a drain electrically coupled to the write bit line and a gate electrically coupled to a write word line; a second write access transistor having a source electrically coupled to the second node, a drain electrically coupled to the complementary write bit line and a gate electrically coupled to the write word line; a read word line electrically coupled to the first read domain node; a read bit line electrically coupled to the second read domain node; a read port comprising stacked first and second read transistors, the first read transistor having a source electrically coupled to the read bit line, a drain electrically coupled to a source of the second read transistor, and a gate electrically coupled to the read word line, the second read transistor having a drain electrically coupled to ground and a gate electrically coupled to the second node of the static memory cell; and a sense transistor having a gate electrically coupled to the third read domain node, a drain electrically coupled to the fourth read domain node and a source electrically coupled to the read bit line.