Patent ID: 9336144
Filing Date: 2016-05-10
CPC Classification: G06F,Y02D

Claim Text:
1. A processor system, comprising: a plurality of chip layers which are physically conjoined to form a stacked structure, wherein at least one chip layer includes a plurality of processor cores, wherein at least two chip layers include caches that are physically connected through vertical connections between the at least two chip layers to form one or more cache hierarchies over the at least two chip layers, which am shared by the plurality of processor cores, wherein the one or more cache hierarchies each comprise an L2 cache and an L3 cache, and wherein each cache hierarchy comprises dynamically configurable directories which enables a directory of the L2 cache of a given cache hierarchy to be configured such that a single address in the directory of the L2 cache is mapped to a first cache line in the L2 cache and a second cache line in the L3 cache of the given cache hierarchy.