Patent ID: 9395994
Filing Date: 2016-07-19
CPC Classification: G06F

Claim Text:
1. A method comprising: providing a branch prediction unit in an instruction fetch stage of a processor pipeline, the instruction fetch stage further including an instruction fetch unit, the branch prediction unit including a branch target buffer having a plurality of entries to store a tag, a target address and last byte information, the branch prediction unit further including a prediction history buffer having a plurality of entries to store a branch identifier, last byte information, and a target address, wherein the branch prediction unit is to provide an index to the instruction fetch stage to enable the instruction fetch stage to use the index to lookup the prediction history buffer; and providing a return address stack in an instruction decode stage of the processor pipeline, the instruction decode stage coupled to an output of the instruction fetch stage and including an instruction decode unit and the return address stack, the return address stack structurally separated from the branch prediction unit.