Patent ID: 9264187
Filing Date: 2016-02-16
CPC Classification: H04L

Claim Text:
1. A receiver comprising: a data path including a first slicer to receive and sample an incoming analog signal and to determine a bit level for the incoming analog signal, the first slicer to provide a bit decision to a consuming logic; an analysis path including a second slicer to receive and sample the incoming analog signal and to determine a second bit level for the incoming analog signal; and a controller coupled to receive an output of the first slicer and an output of the second slicer to determine a bit error rate (BER) for the data path based on the first and second slicer outputs, wherein the controller is to dynamically sweep a reference voltage level for the second slicer, wherein a reference voltage level for the first slicer is to be static, the controller further to dynamically sweep a reference phase for the second slicer, wherein a reference clock for the first slicer is to be static.