Patent ID: 9424927
Filing Date: 2016-08-23
CPC Classification: G11C

Claim Text:
1. A memory system comprising: an integration unit configured to detect substrate currents flowing through a substrate of a non-volatile memory when the non-volatile memory with a memory cell which has binary or more is written/erased, the integration unit recording first integration values of the substrate currents detected by the integration unit into a storage; a prediction unit configured to predict a lifetime of the non-volatile memory based on the first integration values which are recorded on the storage; a controller configured to switch an operation mode with respect to the non-volatile memory to either one of two modes, one being a first mode with binary writing and the other being a second mode with multivalued writing being greater than the binary writing, wherein the prediction unit predicts, when the controller switches the operation mode from either one of the first mode and the second mode to the other mode, a remaining lifetime of the non-volatile memory in the switched other mode based on the first integration values recorded on the storage while predicting a remaining lifetime of the non-volatile memory for every write/erasure operation toward the non-volatile memory based on the first integration values recorded on the storage.