Patent ID: 9405872
Filing Date: 2016-08-02
CPC Classification: G06F

Claim Text:
1. A computerized method, implemented in a programmable system having at least a processing unit and a storage, for determination of signals to be used for achieving power consumption reduction of an integrated circuit (IC), the method comprising: receiving from storage by the programmable system a description of at least a portion of an IC, the received circuit description comprising a plurality of circuit modules (CMs); performing a power consumption simulation of the IC from the received description, by execution of instructions on a processing unit of the programmable system, so as to generate a power consumption time series for each CM; performing an analysis of the power consumption time series respective of each CM, by execution of instructions on the processing unit, so as to identify existence of any one or more idle periods for each CM; selecting, by execution of instructions on the processing unit, any CM having at least one idle period that is above a predetermined threshold value; and performing an analysis on all the input signals of each selected CM, by execution of instructions on the processing unit respective of each selected CM, so as to determine at least one input signal of all selected CM's input signals that are correlated to transitions of such selected CM between its idle and non-idle states.