Patent ID: 9384141
Filing Date: 2016-07-05
CPC Classification: G06F,G11C

Claim Text:
1. An apparatus for storing and decompressing configuration data in a multi-core microprocessor, the apparatus comprising: a shared fuse array, disposed on a die, said shared fuse array comprising a plurality of semiconductor fuses programmed with compressed configuration data, wherein said shared fuse array further comprises another plurality of semiconductor fuses programmed with uncompressed system hardware configuration data that is employed to initialize control circuit elements within a corresponding one of a plurality of microprocessor cores, and wherein said compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to said plurality of microprocessor cores; and said plurality of microprocessor cores, disposed on said die, wherein each of said plurality of microprocessor cores is coupled to said shared fuse array and is configured to access all of said compressed configuration data during power-up/reset, for initialization of elements within said each of said plurality of microprocessor cores, said each of said plurality of microprocessor cores comprising: