Patent ID: 9401183
Filing Date: 2016-07-26
CPC Classification: G11C,H01L,Y10S

Claim Text:
1. An apparatus comprising: a first integrated circuit; a second integrated circuit stacked with the first integrated circuit; a thermal diffusion bond layer physically joining the first and second integrated circuits and providing a primary means of attachment of the first and second integrated circuits; wherein at least one of the first integrated circuit and the second integrated circuit is substantially flexible and comprises a substantially flexible semiconductor substrate of one piece made from a semiconductor wafer, thinned by at least one of abrasion, etching and parting, and subsequently polished or smoothed after being thinned to form a polished or smoothed surface; and a plurality of vertical interconnects each of which extends through one of a plurality of holes in semiconductor material of the substantially flexible semiconductor substrate from a first surface of the substantially flexible semiconductor substrate to an opposite surface thereof and comprises within the one of the plurality of holes a conductive center portion and a silicon-based dielectric insulating portion surrounding the conductive center portion, wherein the vertical interconnects are closely arrayed.