Patent ID: 9501088
Filing Date: 2016-11-22
CPC Classification: G06F,H03K,H04L

Claim Text:
1. A clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit, coupled to the oscillator, operable to generate a plurality of output clocks according to the reference clock, and operable to stop or start outputting the output clocks according to a power control signal in which the output clocks have the same frequency but different phases; a sequential clock gating circuit, coupled to the multi-phase clock generating circuit, operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and the plurality of output clocks, and operable to maintain an output cycle number relation between the gated clocks after the multi-phase clock generating circuit stopped and then starts outputting the output clocks; and a clock operation control circuit, coupled to the multi-phase clock generating circuit and the sequential clock gating circuit, operable to provide the power control signal and the gate control signal.