Patent ID: 9438520
Filing Date: 2016-09-06
CPC Classification: H04L

Claim Text:
1. One or more computer hardware storage device having stored computer-executable instructions which, when executed by at least one computer hardware processor, cause a load balancer to implement a method that includes the following: monitoring a plurality of destination hosts for changes in an arrangement of the plurality of destination hosts; maintaining a destination host array that maps flow identifiers to destination hosts; prior to each array update, copying the destination host array to an old version of the destination host array; updating the destination host array at periodic intervals; providing the destination host array and the old version of the destination host array to a plurality of muxes; monitoring the plurality of muxes for changes; maintaining a primary ownership array mapping the flow identifiers to primary owner muxes; maintain a backup ownership array mapping the flow identifiers to backup owner muxes; providing the primary ownership array and the backup ownership array to the plurality of muxes; wherein each of the plurality of muxes is configured for: receiving packets from a router; formulating a flow identifier for each received packet based on information contained in the packet; identifying an appropriate destination host, from among the plurality of destination hosts, for the packet; and sending the packet to identified appropriate destination host.