Patent ID: 9349481
Filing Date: 2016-05-24
CPC Classification: G11C

Claim Text:
1. A method of operating a semiconductor memory device, comprising: performing a first program operation in order to raise threshold voltages of memory cells coupled to a selected word line; performing a program verification operation comprising a first sub-verification operation, a second sub-verification operation, a third sub-verification operation and a target verification operation for detecting first fast program memory cells having the threshold voltages risen higher than a second sub-verification voltage from a third sub-verification voltage or lower by the first program operation and second fast program memory cells having the threshold voltages risen higher than a first sub-verification voltage from the third sub-verification voltage or lower by the first program operation, by using a target verification voltage and the first sub-verification voltage, the second sub-verification voltage, and the third sub-verification voltage which are sequentially lower than the target verification voltage; and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells which is lower than the second sub-verification voltage is greater than an increment of each of threshold voltages of the first and the second fast program memory cells, wherein program permission voltages having different voltage levels are applied to bit lines of the first fast program memory cells and the second fast program memory cells, respectively, during the second program operation.