Patent ID: 9483243
Filing Date: 2016-11-01
CPC Classification: G06F

Claim Text:
1. A method of compiling a computer program, comprising: analysing said computer program and identifying loops within said computer program and converting scalar instructions within said loops to vector instructions, said vector instructions comprising vector data access instructions, each of said vector data access instructions specifying a plurality of elements, each of said elements indicating a data access to be performed; identifying a first vector data access instruction and a second vector data access instruction within said computer program where interleaving of data accesses from said first and second vector data access instructions, subject to a limited interleaving constraint, would not cause a data error; inserting a start limited interleaving instruction into said computer program prior to said first vector data access instruction, said start limited interleaving instruction providing an indication to a vector data access unit that data accesses from said first and second vector data access instructions can be interleaved subject to said limited interleaving constraint; said limited interleaving constraint being that a next data access indicated by an element from said second vector data access instruction is issued when a numerical position of said element within said plurality of elements of said second vector data access instruction subtracted from a numerical position of an element indicating a next data access of said first vector data access instruction is less than a predetermined value, and when it is not less than said predetermined value, a data access from said first vector data access instruction is issued; and transforming said computer program into code suitable for execution on a data processing system.