Patent ID: 9483406
Filing Date: 2016-11-01
CPC Classification: G06F

Claim Text:
1. A method, comprising: prefetching data, by a first hardware data prefetcher, into a microprocessor according to a first algorithm; prefetching data, by a second hardware data prefetcher, into the microprocessor according to a second algorithm, wherein the first and second algorithms are different; detecting, by the second prefetcher, that the second prefetcher is prefetching data into the microprocessor according to the second algorithm in excess of a first predetermined rate and, in response, sending a throttle indication to the first prefetcher; prefetching data, by the first prefetcher, into the microprocessor according to the first algorithm at below a second predetermined rate in response to receiving the throttle indication from the second prefetcher; wherein the first and/or second predetermined rate is dynamically determined based on utilization of a bus that interfaces the microprocessor to a system memory from which the first and second hardware data prefetchers prefetch data into the microprocessor; and wherein the utilization is determined based on a ratio of a clock rate of the bus and a clock rate of the first and second data prefetchers.