Patent ID: 9310866
Filing Date: 2016-04-12
CPC Classification: G06F,G08B,G11C

Claim Text:
1. A device comprising: a power gate controller electrically connected to a power supply line; a power gate electrically connected to the power supply line and the power gate controller; a CPU electrically connected to the power gate; and a sensor portion electrically connected to the power gate and the CPU, wherein the power gate controller comprises a timer and is configured to control the power gate with use of the timer, wherein the power gate is configured to allow or stop supply of power from the power supply line to the CPU and the sensor portion, in accordance with control by the power gate controller; wherein the sensor portion is configured to transmit a measurement value obtained by measuring a physical quantity to the CPU, wherein the CPU is configured to perform an arithmetic processing on the measurement value and transmit a signal based on an arithmetic result, wherein the CPU comprises a first memory portion and a second memory portion electrically connected to the first memory portion, wherein the first memory portion comprises a first transistor which comprises a first semiconductor, wherein the second memory portion comprises a second transistor which comprises a second semiconductor, the second semiconductor having a different band gap width from that of the first semiconductor, and wherein the CPU is configured to store data of the first memory portion in the second memory portion before the power gate stops the supply of power, and restore the data of the second memory portion to the first memory portion when the power gate allows to resume the supply of power.