Patent ID: 9342309
Filing Date: 2016-05-17
CPC Classification: G06F

Claim Text:
1. A circuit arrangement, comprising: first decode logic associated with a first type of execution unit and configured to receive an instruction and decode the instruction; and second decode logic associated with a second type of execution unit and configured to receive the instruction and decode the instruction, wherein the instruction is concurrently forwarded to the first and second decode logic; wherein the second decode logic is disposed within a designed, verified and tested core, wherein the first decode logic is disposed external to the designed, verified and tested core and is interfaced with the second decode logic through an interface, wherein the first decode logic has a higher priority than the second decode logic such that if the first and second decode logic respectively decode the instruction as a valid instruction for the first and second types of execution unit, the instruction is executed by a first execution unit of the first type of execution unit rather than by a second execution unit of the second type of execution unit, wherein the second execution unit is disposed within the designed, verified and tested core, wherein the first execution unit is disposed external to the designed, verified and tested core, wherein the designed, verified and tested core, the first decode logic and the first execution unit are disposed in an application specific hardware design, wherein the circuit arrangement further comprises first and second rename logic respectively associated with the first and second decode logic, wherein the first and second execution units have different register architectures, and wherein the first and second rename logic are configured to apply different renaming operations to the instruction based upon the respective register architectures of the first and second execution units.