Patent ID: 9230644
Filing Date: 2016-01-05
CPC Classification: G11C

Claim Text:
1. An electronic device comprising semiconductor memory, wherein the semiconductor memory comprises: a memory cell block including a first cell array and a second cell array, wherein the first cell array includes a word line, a first bit line crossing the word line, and a first variable resistance layer disposed between the word line and the first bit line, and wherein the second cell array includes the word line, a second bit line crossing the word line and the first bit line, and a second variable resistance layer disposed between the word line and the second bit line, the second variable resistance layer including a material different from that of the first variable resistance layer, the word line being shared by the first and second cell arrays; and a column control block configured to supply a first write bias for switching a resistance state of the first variable resistance layer to the first bit line and to supply a second write bias for switching a resistance state of the second variable resistance layer to the second bit line.