Patent ID: 9257439
Filing Date: 2016-02-09
CPC Classification: G06F,H01L

Claim Text:
1. An integrated circuit (IC) layout, comprising: a first rectangular region, wherein the first rectangular region has its longer sides in a first direction and its shorter sides in a second direction that is orthogonal to the first direction; and a first imaginary line through a geometric center of the first rectangular region in the first direction and a second imaginary line through the geometric center in the second direction divide the first rectangular region into a first, second, third, and fourth sub-regions in counter-clockwise order with the first sub-region located at an upper-right portion of the first rectangular region; at least eight first patterns located at a first layer of the IC layout, wherein each of the first patterns is a rectangular shape extending lengthwise in the second direction over the first rectangular region; the first patterns are spaced from each other in the first direction; a first, second, third, and fourth portions of the first patterns overlap with the first, second, third, and fourth sub-regions respectively; the first and second portions of the first patterns are mirror images of the respective fourth and third portions of the first patterns with respect to the first imaginary line; and the first and fourth portions of the first patterns are translations of the respective second and third portions of the first patterns; at least eight second patterns located at a second layer of the IC layout, wherein each of the second patterns is a rectangular shape extending lengthwise in the second direction, the second patterns are spaced from each other in the first direction, each of the second patterns partially overlaps with one of the first patterns and fully covers a longer side of the respective first pattern when the first and second layers are superimposed; and a plurality of third patterns located at a third layer of the IC layout, wherein each of the third patterns is a rectangular shape, the third patterns are spaced from each other, each of the third patterns partially overlaps with one of the first patterns and covers a portion of a longer side of the respective first pattern that is not covered by the second patterns when the first, second, and third layers are superimposed, wherein: the first, second, and third patterns are used for collectively defining a plurality of active regions for forming transistors; and the plurality of active regions are defined along longer sides of the first patterns that are not covered by the second and third patterns when the first, second, and third layers are superimposed.