Patent ID: 9419006
Filing Date: 2016-08-16
CPC Classification: G11C,H01L

Claim Text:
1. A method of forming a 3D NAND memory, comprising: forming a multi-layer slab on top of a semiconductor substrate with layers corresponding to structures of an array of vertically aligned NAND strings, and wherein the layers includes memory cell layers for forming memory cells of the NAND strings and for forming word lines with socket components; opening trenches in the multi-layer slab to expose the memory cell layers; forming grottoes at where memory cells are to be formed in the memory cell layers exposed by the trenches, each grotto having walls; forming in each grotto a socket component of a word hue by lining the walls with deposition of a word line material; depositing a layer of insulating material on the word line material lining the walls while leaving a remaining space in each grotto; filling the remaining space of each grotto with a floating gate material to form a floating gate embedded in each grotto; forming other structures of the NAND strings and a plurality of bit lines through the trenches; and partitioning the multi-layer slab by an isolation material into individual memory cells accessible by respective word lines and bit lines.