Patent ID: 9419058
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A memory device, comprising: a first bit line interconnect; a second bit line interconnect; a first plurality of electrically conductive local bit lines extending in a substantially vertical direction into a memory cell region, wherein each local bit line in the first plurality of electrically conductive local bit lines is electrically connected to the first bit line interconnect; a second plurality of electrically conductive local bit lines extending in the substantially vertical direction into the memory cell region and horizontally offset from the first plurality of electrically conductive local bit lines, wherein each local bit line in the second plurality of electrically conductive local bit lines is electrically connected to the second bit line interconnect; a first select transistor electrically connected to the first bit line interconnect, wherein the first select transistor is configured to select the first plurality of electrically conductive local bit lines; a second select transistor electrically connected to the second bit line interconnect, wherein the second select transistor is configured to select the second plurality of electrically conductive local bit lines; a plurality of word lines extending in a substantially horizontal direction into the memory cell region; and a plurality of memory cells located in the memory cell region; wherein: the plurality of word lines comprise a first, a second, a third and a forth word line comb; each word line comb comprises a plurality of electrically conductive fingers; the plurality of electrically conductive fingers for each word line comb electrically contact other electrically conductive fingers of the same word line comb and are electrically insulated from the electrically conductive fingers of the other word line combs; the fingers of the first and second word line combs extend in a first substantially horizontal direction from a first interconnect region into a first side of the memory cell region; the fingers of the third and forth word line combs extend in a second substantially horizontal direction from a second interconnect region into a second side of the memory cell region opposite to the first side of the memory cell region; and the fingers of the first, second, third and forth word line comb are alternately interdigitated in the memory cell region; wherein a row through the memory cell region along a horizontal direction substantially perpendicular to the first and the second substantially horizontal directions comprises at least four fingers of the word line combs, at least four local bit lines, and at least eight memory cells arranged in a following order: a first finger of the first word line comb; a first memory cell; a first local bit line of the first plurality of electrically conductive local bit lines; a second memory cell; a first finger of the third word line comb; a third memory cell; a first local bit line of the second plurality of electrically conductive local bit lines; a fourth memory cell; a first finger of the second word line comb; a fifth memory cell; a second local bit line of the first plurality of electrically conductive local bit lines; a sixth memory cell; a first finger of the fourth word line comb; a seventh memory cell; a second local bit line of the second plurality of electrically conductive local bit lines; and an eighth memory cell.