Patent ID: 9396135
Filing Date: 2016-07-19
CPC Classification: G06F

Claim Text:
1. An apparatus comprising: one or more processors or cores; a physical memory communicably coupled to the processor(s) or core(s), wherein each location within the physical memory has a physical memory address; one or more physical cache memories communicably coupled to the processor(s) and the physical memory; two or more address mappings associated with each physical cache memory, wherein each of the two or more address mappings divide the physical memory address into at least a first set of address bits and a second set of address bits, the first set of address bits comprising a combination of two or more address bits from the physical memory address that are used as a set index to locate a program object in the physical cache memory, the second set of address bits are used as a tag to correctly identify a data in the physical cache memory with the physical memory address, a total number of bits used as the set index is less than a total number of bits in the physical memory address and the set index for the two or more address mappings are different; an address decoder associated with each address mapping; and a programmable address mask register with each address decoder that extracts (a) the set index from the physical memory address of the program object using changeable mask values which identify the address bits of the set index, and (b) the tag from the physical memory address of the program object using a complement of the changeable mask values which identify the address bits of the tag.