Patent ID: 9269585
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A method for forming an integrated circuit (IC) structure, comprising: providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL; etching the ESL and the dielectric layer to form a trench, a surface of the MG exposed in the trench being oxidized to form a first oxide layer on the MG; removing the first oxide layer using a H transferring the IC structure to a deposition tool, the surface of the MG being oxidized to form a second oxide layer during the transfer; baking the IC structure under vacuum at a temperature in a range from about 50° C. to about 500° C.; and reducing the second oxide layer to a metal included in the MG using a reducing agent.