Patent ID: 9363412
Filing Date: 2016-06-07
CPC Classification: G06T,H04N

Claim Text:
1. An accelerator circuit for an image processing apparatus, the accelerator circuit comprising: a buffer circuit configured to obtain image data from N data sources and temporarily store the image data, N being a number greater than one; and an arithmetic circuit; the buffer circuit including each of the N buffer memories is configured to temporarily store image data obtained from a corresponding one of the N data sources, each of the N 2D registers is configured to temporarily store pixel data that is of an area of a first size and is a part of image data stored in a corresponding one of the N buffer memories, the selector is configured to select pixel data of the first size stored in one of the N 2D registers and send the selected pixel data to the arithmetic circuit under control of the control circuit, the arithmetic unit is configured to perform a first arithmetic operation on the selected pixel data of the first size, and the control circuit is configured to control the selector to perform the sending when pixel data is stored in one of the N 2D registers.