Patent ID: 9298868
Filing Date: 2016-03-29
CPC Classification: G06F

Claim Text:
1. A computer-implemented method for automatically generating pushdown structures when designing integrated circuits using an integrated circuit design tool, the method comprising: receiving a first set of circuit structures associated with an integrated circuit; receiving partition boundary information associated with the integrated circuit; performing a logical pushdown of the first set of circuit structures into a second set of circuit structures associated with the integrated circuit, wherein each circuit structure in the first set that is logically pushed down into the second set overlaps at least one circuit structure in the second set, and wherein the logical pushdown amends a logical description of each circuit structure in the second set; performing a physical pushdown of the first set of circuit structures into the the second set of circuit structures based one or more partition boundaries; and storing a data set corresponding to the second set of circuit structures, wherein the data set includes at least one logical pushdown structure and at least one physical pushdown structure corresponding to the at least one logical pushdown structure.