Patent ID: 9235251
Filing Date: 2016-01-12
CPC Classification: G06F,Y02D

Claim Text:
1. A method for conserving power in a computing device, comprising: setting a flag bit associated with a resource in a low power mode mask when the resource is not in use, wherein the resource is one of a plurality of resources; identifying the resources of the plurality of resources that may be placed in a low power resource mode based upon flag bit settings in the low power mode mask when a processor of the computing device is able to enter an idle state; determining a time that the processor is expected to remain in the idle state; registering a latency requirement for each of the identified resources in the low power mode mask; determining a latency budget for the computing device; evaluating on the computing device low power modes for each of the identified resources in the low power mode mask to eliminate any of the low power resource modes, or any combination of the low power resource modes, that have a combined latency requirement that exceeds the latency budget; determining potential power savings of each of the evaluated low power resource modes based upon a potential power savings per unit time at a current temperature times the determined expected idle time; selecting, by the processor, a combination of the low power resource modes that maximizes the potential power savings and has a total latency requirement that is less than or equal to the latency budget; and entering the selected combination of the low power resource modes by executing an enter function of each of the selected low power resource modes on each of the identified resources.