Patent ID: 9324672
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method of making a semiconductor device, comprising: providing a plurality of conductive pillars; disposing a first dual-active sided semiconductor die between the conductive pillars, the first dual-active sided semiconductor die including first and second opposing active surfaces with first contact pads on the first active surface and second contact pads on the second active surface, wherein a height of the conductive pillars is greater than a height of the first dual-active sided semiconductor die; depositing an encapsulant over the first dual-active sided semiconductor die and around the conductive pillars with the encapsulant covering the first active surface of the first dual-active sided semiconductor die, wherein a first surface of the encapsulant is coplanar with a surface of the conductive pillars; forming a plurality of vias through the first surface of the encapsulant with the vias extending from the first surface of the encapsulant through the encapsulant to the first contact pads of the first dual-active sided semiconductor die; depositing a conductive material in the vias to form a plurality of conductive vias in the encapsulant with the conductive vias extending from the first contact pads through the encapsulant to the first surface of the encapsulant; forming a first interconnect structure over the first surface of the encapsulant, wherein the first interconnect structure is electrically connected to the conductive pillars and through the conductive vias to the first contact pads of the first dual-active sided semiconductor die; and forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant with the second interconnect structure physically contacting the conductive pillars and the second contact pads of the first dual-active sided semiconductor die.