Patent ID: 9391624
Filing Date: 2016-07-12
CPC Classification: H03L

Claim Text:
1. A method comprising: receiving a reference clock signal; generating, by a digitally controlled oscillator, an output signal, wherein the reference clock signal has a first frequency, and wherein the digitally controlled oscillator is configured to generate the output signal at a second frequency; based on the output signal, generating a first feedback signal, wherein the first feedback signal is representative of a phase of the output signal relative to the reference clock signal; based on the first feedback signal, generating a second feedback signal, wherein generating the second feedback signal comprises, in response to the second frequency being an integer multiple of the first frequency, modifying the first feedback signal by forcing a least significant bit (LSB) of the first feedback signal to be maintained at a specific value to generate the second feedback signal, wherein the LSB in the second feedback signal is maintained at the specific value irrespective of a value of the LSB of the first feedback signal; and based on the second feedback signal, generating a control signal, wherein the output signal is generated by the digitally controlled oscillator based on the control signal.