Patent ID: 9349821
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate including a p-type metal-oxide-semiconductor (PMOS) region and an n-type metal-oxide-semiconductor (NMOS) region; a first gate stack formed on the PMOS region of the semiconductor substrate and comprising a first electrode structure; and a second gate stack formed on the NMOS region of the semiconductor substrate and comprising a second electrode structure, wherein each of the first electrode structure and the second electrode structure comprises: a polysilicon layer doped with resistance adjustment impurities; a polysilicon layer for adjusting grains formed in the polysilicon layer doped with the resistance adjustment impurities and doped with grain adjustment impurities; an ohmic metal layer formed on the polysilicon layer including the polysilicon layer for adjusting the grain; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer, wherein the existence of the polysilicon layer for adjusting the grain results in a reduced difference in the thickness between the ohmic metal layer of the first electrode structure and the ohmic metal layer of the second electrode structure.