Patent ID: 9391566
Filing Date: 2016-07-12
CPC Classification: G01R,H03F

Claim Text:
1. A method of testing a circuital arrangement, the method comprising: a) providing an electronic assembly on a die, the electronic assembly comprising a plurality of electronic assembly segments, each electronic assembly segment having an input and an output, and the plurality of electronic assembly segments having an overall output impedance; b) connecting a testing device external to the die to the electronic assembly such that, when testing, a test signal is adapted to pass through the electronic assembly; c) configuring at least one of the electronic assembly segments in such a way as to be able to activate or deactivate the at least one of the electronic assembly segments; d) deactivating one or more electronic assembly segments of the plurality of electronic assembly segments, while leaving the remaining assembly segments activated, thus increasing the overall output impedance of the electronic assembly; and e) applying the test signal from the testing device to the electronic assembly, thus testing the one or more electronic assembly segments which are activated.