Patent ID: 9312376
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: an interlayer insulating layer formed on a substrate and including a trench; a gate electrode formed in the trench and including a first metal layer and a second metal layer, the first metal layer formed along a side and a bottom surface of the trench and the second metal layer filling a space formed by the first metal layer; a gate dielectric film formed between the substrate and the gate electrode; a first gate spacer including silicon nitride formed on the sidewall of the gate electrode and the gate dielectric film; a second gate spacer formed on the first gate spacer and having a dielectric constant lower than the dielectric constant of silicon nitride; a third spacer formed on the second gate spacer; and an elevated source/drain formed in a recess formed in the substrate and including SiGe, wherein the first gate spacer directly contacts the gate dielectric film, and a top surface of the elevated source/drain is higher than a top surface of the gate dielectric film under the gate electrode.