Patent ID: 9312139
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A semiconductor element, comprising: a substrate; a plurality of doping strips formed in the substrate; a memory material layer formed on the substrate, the memory material layer comprising a memory area located on two sides of each of the plurality of doping strips; a plurality of conductive damascene structures formed on the memory material layer; a conductive layer formed between each of the plurality of conductive damascene structures and the memory material layer; and a dielectric structure formed on the each of the plurality of doping strips and between the each of the plurality of conductive damascene structures; wherein the each of the plurality of conductive damascene structures are extended in a direction perpendicular to a direction which the each of the plurality of doping strips are extended in, an end of the each of the plurality of conductive damascene structures is embedded in a corresponding conductive layer and the dielectric structure, and a bottom surface of the end is connected to a bottom surface of a concave region in the dielectric structure.