Patent ID: 9305134
Filing Date: 2016-04-05
CPC Classification: G06F

Claim Text:
1. A semiconductor device design method comprising: extracting voltage data associated with at least one electrical component in a layout of a semiconductor device, the voltage data based on a result of a simulation of an operation of the semiconductor device; extracting location data of at least one electrical component in the layout of a semiconductor device; incorporating, based on the extracted location data of the at least one electrical component, the extracted voltage data in the layout to generate a modified layout of the semiconductor device, the voltage data being incorporated in at least one marker layer of the modified layout; and performing a voltage-dependent design rule check (VDRC) on the modified layout, wherein the VDRC analyzes spacing rules associated with the at least one electrical component based on the extracted voltage data, wherein one or more operations of the method are performed by at least one processor.