Patent ID: 9287324
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A non-volatile memory, comprising: a substrate; a fin structure protruded from the substrate, wherein a first source/drain region and a second source/drain region are formed in the fin structure; a gate structure covering a top surface and two lateral surfaces of a part of the fin structure, wherein the gate structure is arranged between the first source/drain region and the second source/drain region; a transition layer in contact with the second source/drain region; and a metal layer in contact with the transition layer, wherein, an insulation layer is formed on a first part of the second source/drain region; a second part of the second source/drain region is exposed through a via in the insulation layer; a dielectric layer is formed on an inner wall and a bottom of the via; a barrier layer is formed on the dielectric layer; the metal layer is filled in the via; the dielectric layer and the barrier layer are reacted with each other to form the transition layer; and the transition layer is in contact with the second source/drain region and the metal layer; and wherein by setting or resetting the transition layer, a resistance value of the transition layer is correspondingly changed.