Patent ID: 9479004
Filing Date: 2016-10-25
CPC Classification: H02J

Claim Text:
1. A power bank circuit comprising: a voltage input (VIN) terminal; a voltage output (VOUT) terminal; at least one rechargeable battery, wherein the at least one rechargeable battery has an operating voltage range from a fully uncharged operating voltage VBATL to a fully charged operating voltage VBATH, wherein the operating voltage range is between a ground (GND) node and a battery (VBAT) node; a first field effect transistor S a second field effect transistor S an inductor coupled to conduct current between the SW node and a voltage output (VOUT) node; a capacitor having a first lead coupled to the VOUT node and a second lead coupled to the GND node; a third field effect transistor SA having a first terminal, a second terminal and a third terminal, wherein the first terminal of transistor SA is coupled to a voltage input (VIN) node; a fourth field effect transistor SB having a first terminal, a second terminal and a third terminal, wherein the first terminal of transistor SB is coupled to the second terminal of transistor SA, and wherein the second terminal of transistor SB is coupled to the VOUT node; and a control circuit that controls the transistor S