Patent ID: 9418743
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A memory device, comprising: a plurality of stacks of conductive strips alternating with insulating strips, including at least a bottom layer of conductive strips, a plurality of intermediate layers of conductive strips, and a top layer of conductive strips; a plurality of semiconductive vertical structures arranged orthogonally to the plurality of stacks; memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of semiconductive vertical structures; a first plurality of conductive lines controlling a plurality of transistor switches at the top layer of the conductive strips; a second plurality of conductive lines; a plurality of local word line driver switches controlled by signals on the second plurality of conductive lines; word line drivers; and a third plurality of conductive lines configured to receive word line signals from the word line drivers, and electrically coupled to the plurality of intermediate layers via the plurality of local word line driver switches.