Patent ID: 9397160
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate; a plurality of unit MISFET elements formed in a first MISFET formation region of a main surface of the semiconductor substrate and coupled in parallel to each other; an interconnect line structure formed over the semiconductor substrate and having a first interconnect line layer, and a second interconnect line layer located over the first interconnect line layer; and a drain back surface electrode formed over a back surface of the semiconductor substrate opposite to the main surface, wherein each of the unit MISFET elements is a trench-gate MISFET element and includes a gate electrode embedded in a trench of the semiconductor substrate, and a source region formed in a top surface layer portion of the semiconductor substrate, wherein the first interconnect line layer of the interconnect line structure includes a first source interconnect line and a first gate interconnect line, wherein the second interconnect line layer of the interconnect line structure includes a second source interconnect line and a second gate interconnect line, wherein each of the first source interconnect line and the first gate interconnect line has a thickness smaller than a thickness of each of the second source interconnect line and the second gate interconnect line, wherein the respective source regions of the unit MISFET elements are electrically coupled to each other via the first source interconnect line and the second source interconnect line, wherein the respective gate electrodes of the unit MISFET elements are electrically coupled to each other via the first gate interconnect line and electrically coupled to the second gate interconnect line via the first gate interconnect line, and wherein the first gate interconnect line extends over each of the gate electrodes.