Patent ID: 9460792
Filing Date: 2016-10-04
CPC Classification: G11C

Claim Text:
1. An apparatus, comprising: a first plurality of memory subblocks of a memory block; a second plurality of memory subblocks of the memory block; a first select gate control line associated with the first plurality of memory subblocks, the first select gate control line coupled to a first plurality of select gate switches of the first plurality of memory subblocks, the first plurality of select gate switches coupled to a source; a second select gate control line associated with the second plurality of memory subblocks, the second select gate control line coupled to a second plurality of select gate switches of the second plurality of memory subblocks, the second plurality of select gate switches coupled to the source; a first select gate drain control line associated with a first memory subblock of the first plurality of memory subblocks, the first select gate drain control line coupled to a select gate drain switch of the first memory subblock of the first plurality of memory subblocks; a second select gate drain control line associated with a second memory subblock of the first plurality of memory subblocks, the second select gate drain control line coupled to a select gate drain switch of the second memory subblock of the first plurality of memory subblocks; and a plurality of memory access lines, each memory access line of the plurality of memory access lines associated with each memory subblock of the first plurality of memory subblocks and each memory subblock of the second plurality of memory subblocks.