Patent ID: 9281074
Filing Date: 2016-03-08
CPC Classification: G11C,H01L

Claim Text:
1. A one time programmable (OTP) memory cell, comprising: a select gate transistor, having a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal; a following gate transistor, having a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal; and an antifuse varactor, having a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal; wherein each of the first source/drain extension areas has a first depth, and each of the second and third source/drain extension areas has a second depth deeper than the first depth.