Patent ID: 9343481
Filing Date: 2016-05-17
CPC Classification: G02F,H01L

Claim Text:
1. A Thin Film Transistor (TFT) array substrate having a plurality of pixels arranged in rows and columns, the TFT array substrate comprising: a substrate; a common electrode layer arranged on the substrate; a first insulating layer arranged on the common electrode layer; an array of pixel electrodes arranged on the first insulating layer; a plurality of via holes in the first insulating layer between at least some of adjacent pixels; and a plurality of common electrode lines between at least some of the rows and/or the columns of pixels and electrically connected with the common electrode layer through the via holes; wherein projections of data lines and/or gate lines superpose on projections of the common electrode lines in a direction perpendicular to the substrate and the via holes in the direction perpendicular to the substrate, and wherein perpendicular projections of the gate lines do not superpose on the data lines on the substrate.