Patent ID: 9319058
Filing Date: 2016-04-19
CPC Classification: H03M

Claim Text:
1. A multiple-input multiple-output (MIMO) filter comprising: a delay line including D delay cells that receives an input signal including M outputs of M sub-analog-to-digital converters (sub-ADCs) of an interleaved ADC, where D and M are integers greater than 1; a first selector that selects n of M outputs of a last one of the D delay cells; a second selector that selects n of M inputs of a first one of the D delay cells; a first multiplexer that multiplexes outputs of the first and second selectors and (D−1) of the D delay cells and that generates N outputs, where N=(D−1)M+2n, and 1≦n≦M; a third selector that has M output ports each selecting L of the N outputs, where L=N+1−M; M product generators each generating a product of an output of one of the M output ports and a corresponding coefficient; a second multiplexer that multiplexes M products of the M product generators and that generates a correction signal to correct errors in the input signal; and an adder that adds the correction signal to an output of one of the D delay cells to generate a corrected signal.