Patent ID: 9479463
Filing Date: 2016-10-25
CPC Classification: H04L

Claim Text:
1. A system on a chip (SoC) node comprising: a management processor configured to generate management information; an application processor coupled to the management processor; and a routing header unit configured to prepend a routing header to the management information to form a management information routing frame, wherein the routing header includes a management processor domain indicator which specifies that the management information routing frame is to remain within a management processor domain during routing; wherein the management processor is further configured to have access to a processor state of the application processor, access to a debug control of the application processor, and access to a memory and peripheral resources of the SoC node, wherein the management processor is further configured to run within a secure world security zone, and wherein the application processor in the plurality of nodes is configured to run within a normal world security zone.