Patent ID: 9293405
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: (a) a semiconductor chip having a surface on which a plurality of protruding electrodes are arranged; (b) a wiring board including a core layer, the core layer having a first front surface on which a plurality of terminals corresponding to the plurality of protruding electrodes are arranged, and a first back surface opposite the first front surface, the semiconductor chip being mounted over the first front surface so that the plurality of protruding electrodes are electrically connected to the plurality of terminals, respectively; and (c) a sealing resin filled between the semiconductor chip and the wiring board, wherein the plurality of protruding electrodes includes a plurality of first protruding electrodes and a plurality of second protruding electrodes, and the plurality of terminals includes a plurality of first terminals and a plurality of second terminals, wherein the core layer includes the plurality of first terminals, a plurality of first through-holes, and the plurality of second terminals, wherein the plurality of first terminals are arranged in a first area of the first front surface of the core layer, each of the plurality of first terminals being electrically connected to a respective first protruding electrode of the plurality of first protruding electrodes of the semiconductor chip, wherein the plurality of first through-holes are arranged in a second area of the first front surface of the core layer, the second area being closer to a center portion of the core layer than the first area is, wherein the plurality of second terminals are arranged in a third area of the first front surface of the core layer, the third area being closer to the center portion of the core layer than the second area is, each of the plurality of second terminals being electrically connected to a respective second protruding electrode of the plurality of second protruding electrodes of the semiconductor chip, wherein each of the plurality of first through-holes penetrates from the first front surface of the core layer to the first back surface of the core layer, wherein some of the plurality of first through-holes are electrically connected to respective first terminals of the plurality of first terminals, wherein, in a plan view, the plurality of protruding electrodes of the semiconductor chip are not overlapped with the plurality of first through-holes, wherein the plurality of first terminals include first supply terminals which are configured to supply a first power supply voltage or a first reference voltage from outside, and first signal terminals which are configured to transmit a signal voltage to the outside, and wherein the plurality of second terminals include only second supply terminals which are configured to supply a second power supply voltage or a second reference voltage from the outside.