Patent ID: 9262099
Filing Date: 2016-02-16
CPC Classification: G06F,G11C

Claim Text:
1. A non-volatile memory device comprising: a first NAND cell array comprising a first group of pages; a second NAND cell array comprising a second group of pages; a plurality of X-decoders at least one-to-one connected to the first and second NAND cell arrays; a plurality of page buffers at least one-to-one connected to the first and second NAND cell arrays so as to sense and latch data of the first and second NAND cell arrays; and a control logic for controlling the plurality of X-decoders to simultaneously sense data of a first page of the first group of pages wherein a start address pages is positioned in the first page, and data of a second page of the second group of pages, the second page subsequent to the first page wherein the control logic controls the plurality of X-decoders to sense data of a third page subsequent to the second page during the data of the first page from the start address and the data of the second page is sequentially output to an external apparatus.