Patent ID: 9443938
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A transistor, comprising: a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer, wherein the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, wherein the p-type III-N layer includes a first portion that is disposed in a device access region between the gate and the drain; and a field plate electrically connected to the source and to the first portion of the p-type III-N layer, wherein the first portion of the p-type III-N layer is electrically isolated from the drain.