Patent ID: 9476942
Filing Date: 2016-10-25
CPC Classification: G01R

Claim Text:
1. An integrated circuit comprising: A. logic circuitry including primary inputs, primary outputs, stimulus leads, and response leads; B. scan path circuitry including a scan data input lead, a scan data output lead, and scan cells, each scan cell including: C. a first scan path of serially coupled scan cells that is selectably divided into a first part of scan cells and a second part of scan cells, the scan data input of the first scan cell in each part being coupled to the scan data input lead, and each part including an output buffer having a data input coupled with the data output of the last scan cell in the part, a buffer enable input, and a data output coupled with the scan data output lead; D. a second scan path of serially coupled scan cells that is selectably divided into a first part of scan cells and a second part of scan cells, the scan data input of the first scan cell in each part being coupled to the scan data input lead, and each part including an output buffer having a data input coupled with the data output of the last scan cell in the part, a buffer enable input, and a data output coupled with the scan data output lead; and E. adaptor circuitry having a first clock lead coupled with the clock inputs of the first part of scan cells in the first and second scan paths, and a second clock lead coupled with the clock inputs of the second part of scan cells in the first and second scan paths.