Patent ID: 9396804
Filing Date: 2016-07-19
CPC Classification: G11C

Claim Text:
1. A memory programming method for a physical erasing unit of a rewritable non-volatile memory module, wherein the physical erasing unit comprises a plurality of word line layers and a plurality of bit line sets, the bit line sets are arranged along a first direction and separated from one another, each of the bit line sets comprises a plurality of bit lines, the bit lines of each bit line sets are extended along a second direction, arranged along a third direction and separated from one another, the word line layers are stacked along the second direction and the word line layers are separated from one another, a memory cell is provided at intersection of each of the word line layers and each of the bit lines of each of the bit line sets, at least one physical programming unit is constituted by the memory cells at intersection of one of the bit line sets and one of the word line layers, and the memory programming method comprises: programming a first data stream into at least one first physical programming unit of the physical erasing unit, wherein the at least one first physical programming unit is constituted by the memory cells at intersection of at least one first bit line set among the bit line sets and a first word line layer among the word line layers; and after programming the first data stream into the at least one first physical programming unit, programming another data stream into at least one another physical programming unit of the physical erasing unit, wherein the at least one another physical programming unit is constituted by the memory cells at intersection of the at least one first bit line set among the bit line sets and another word line layer among the word line layers.