Patent ID: 9397938
Filing Date: 2016-07-19
CPC Classification: H04L

Claim Text:
1. A circuit for managing transmittal of packets, the circuit comprising: a packet descriptor manager (PDM) circuit module configured to generate a metapacket from a command signal, the metapacket indicating a size and a destination of a packet to be transmitted by the circuit; a packet scheduling engine (PSE) circuit module configured to model transmission of the packet through a model of a network topology from the destination to the circuit, the model of the network topology including simulated instances of a plurality of nodes in the network topology between the destination and the circuit and connections between the plurality of nodes, the modeling being based on information indicated by the metapacket, the PSE determining an order in which to transmit the packet among a plurality of packets based on the model transmission; and a packet engines and buffering (PEB) circuit module configured to process the packet and cause the processed packet to be transmitted toward the destination according to the order determined by the PSE.