Patent ID: 9412589
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method for forming at least one NMOS transistor and at least one PMOS transistor, respectively, on different regions of a silicon-on-insulator (SOI) substrate, comprising: forming a first gate region on a first region of the SOI substrate, and a second gate region on a second region of the SOI substrate; forming a first lateral insulating layer on sidewalls of the first and second gate regions; forming on the first and second regions of the SOI substrate a respective pair of first faceted semiconductor blocks of a first semiconductor material adjacent the first lateral insulating layers, with a gap being formed between an inclined profile of each first faceted semiconductor block and a corresponding first lateral insulating layer, the first semiconductor material having a first type of conductivity for a first type of transistor; forming second and third lateral insulating layers on sidewalls of the first lateral insulating layer and on the first faceted semiconductor blocks for the first and second regions of the SOI substrate, with the second and third lateral insulating layers having a faceted profile and filling the gaps between the inclined profile of each first faceted semiconductor block and the corresponding first lateral insulating layer; removing, from the second region of the SOI substrate, the pair of first faceted semiconductor blocks and a portion of the second and third lateral insulating layers so that the remaining second and third lateral insulating layers have a faceted profile; and forming on the second region of the SOI substrate a pair of second faceted semiconductor blocks of a second semiconductor material at a location where the pair of first faceted semiconductor blocks were removed, with the pair of second faceted semiconductor blocks matching a faceted profile of the corresponding first lateral insulating region and the second and third lateral insulating layers, the second semiconductor material having a second type of conductivity opposite the first type of conductivity for a second type of transistor; with each pair of the first and second faceted semiconductor blocks having an upper surface coplanar with an upper surface of the third lateral insulating layer.