Patent ID: 9484311
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A chip package, comprising: a package substrate and a metal cap covering the package substrate; a silicon chip placement area arranged on an upper surface of the package substrate; a plurality of first conductive parts arranged on the upper surface of the package substrate in a peripheral area of the silicon chip placement area; and a plurality of second conductive parts, the second conductive parts being arranged on side walls of the package substrate, extended to the upper surface of the package substrate, and electrically connected to the first conductive parts, wherein an edge of the metal cap contacting the package substrate is electrically connected to the first conductive parts, wherein at least one first conductive part of the first conductive parts is electrically connected to a grounding part by using the metal cap, and the grounding part is arranged on the package substrate, and configured to ground the package substrate, the first conductive parts, the second conductive parts, and the metal cap forming a Faraday cage, the Faraday cage providing high-frequency electromagnetic shielding for the silicon chip placement area and inhibiting an edge radiation effect on the side walls of the package substrate with respect to an electromagnetic signal, and wherein a distance between at least two first conductive parts is selected according to a frequency of an electromagnetic signal to be shielded.