Patent ID: 9251868
Filing Date: 2016-02-02
CPC Classification: G11C,H01L

Claim Text:
1. A multilayered semiconductor device comprising: a substrate; and a plurality of core chips layered in a vertical direction relative to the planar direction of the substrate, wherein each of the core chips includes: an internal power supply generation circuit that generates an internal power supply voltage supplied to an internal circuit in the core chip; and an internal power supply penetration electrode that allows an output of the internal power supply generation circuit to be shared by the core chips, wherein the internal power supply penetration electrode possessed by each of the core chips includes: an internal power supply terminal arranged over an upper surface of the core chip; and an internal power supply bump arranged over an underside of the core chip at a position corresponding to that of the internal power supply terminal over the upper surface when the core chips are layered.