Patent ID: 9263501
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A memory device comprising: a first diffusion layer region on a substrate; a second diffusion layer region on the substrate, the second diffusion layer region being provided apart from the first diffusion layer region; a third diffusion layer region on the substrate, the third diffusion layer region being provided apart from the second diffusion layer region, the second diffusion layer region being provided between the first diffusion layer region and the third diffusion layer region; a first gate electrode between the first diffusion layer region and the second diffusion layer region through a first insulating layer provided on the substrate; a second gate electrode between the second diffusion layer region and the third diffusion layer region through a second insulating layer provided on the substrate; a first via contact group including a plurality of first via contacts arranged along a first direction, the first direction being parallel to a surface of the substrate; a second via contact group including a plurality of second via contacts arrange along the first direction, the second via contact group being provided apart from the first via contact group in a second direction, the second direction being orthogonal in the first direction in the surface of the substrate; and a variable resistance element electrically connected to the first diffusion layer region and the second diffusion layer region, at least one of the plurality of first via contacts being electrically connected to the first diffusion layer region with one end, at least one of the plurality of second via contacts being electrically connected to the third diffusion layer region with one end, the at least one of the plurality of first via contacts and the at least one of the plurality of second via contacts being electrically connected to the variable resistance element with the other ends respectively, the variable resistance element being electrically a first interconnect layer.