Patent ID: 9419100
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method for fabricating a metal gate electrode, comprising: forming a dielectric layer and a dummy gate layer over a substrate; etching the dummy gate layer to form a first trench and a second trench having a depth, the first trench having a first width and the second trench having a second width larger than the first width in the dielectric layer, wherein the first trench has a higher aspect ratio than the second trench; depositing one of an N-type or a P-type work-function metal layer over the dielectric layer and into both the first and second trenches wherein the work-function metal layer is in direct contact with the top surface of the dielectric layer; first depositing a first signal metal layer over the work-function metal layer to fill the second trench; and second depositing a second signal metal layer to fill the first trench.