Patent ID: 9342642
Filing Date: 2016-05-17
CPC Classification: G06F

Claim Text:
1. A method comprising: maintaining a set of local arrival time information and local required time information associated with a circuit layout; determining a candidate fix on a critical path in the circuit layout; determining an affected circuit portion that is affected by the candidate fix, wherein the affected circuit portion includes an affected path or a portion of an affected path that has a timing-related value that is changed due to the candidate fix, and that the change in the timing-related value due to the candidate fix exceeds a threshold; statistically determining a set of one or more adjusted local slacks associated with the affected circuit portion, wherein the set of one or more adjusted local slacks associated with the affected circuit portion is statistically determined based on one or more of: a variance of an arrival time associated with the affected circuit portion, a variance of a required time associated with the affected circuit portion, or a variance of a Clock Re-convergence Pessimism Removal (CRPR) time associated with the affected circuit portion; and in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accepting the candidate fix.