Patent ID: 9419221
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor integrated circuit, the method comprising: forming a lower electrode in a semiconductor substrate; forming an interlayer insulating layer; etching the interlayer insulating layer to form a hole for exposing the lower electrode; forming an insulating spacer on a sidewall of the hole; forming a first phase-change layer having a crystalline state along surfaces of the spacer and an exposed lower electrode; forming a second phase-change layer on the first phase-change layer based on crystallinity of the first phase-change layer to be filled in the hole under an amorphous deposition conditions; forming a resistive layer by planarizing the second phase-change layer and the first phase-change layer to be left in the hole; and forming an upper electrode on the resistive layer, wherein a bottom surface and a sidewall of the second phase-change layer are contacted with the first phase-change layer with maintaining the crystalline state and an upper surface of the second phase-change layer is contacted with the upper electrode.