Patent ID: 9305630
Filing Date: 2016-04-05
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising a memory element comprising: a first transistor; a second transistor; a third transistor; a first capacitor; a second capacitor; a first line; a second line; a third line; a fourth line; and a fifth line, wherein: one of a source and a drain of the first transistor is electrically connected to the first line; the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first capacitor; a gate of the first transistor is electrically connected to the second line; one of a source and a drain of the second transistor is electrically connected to the third line; the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one electrode of the second capacitor; the other of the source and the drain of the third transistor is electrically connected to the fourth line; a gate of the third transistor is electrically connected to the fifth line; and a channel formation region of the first transistor includes an oxide semiconductor, wherein a thickness of a gate insulating layer of the second transistor is larger than a thickness of a gate insulating layer of the third transistor.