Patent ID: 9324450
Filing Date: 2016-04-26
CPC Classification: G06F,G11C

Claim Text:
1. A method of operating a memory having a NAND flash memory array and a page buffer associated with the NAND flash memory array, comprising: selecting a page of the NAND flash memory array; storing data from the selected page in the page buffer; performing ECC computations on the data in the page buffer; outputting the data from the page buffer; and repeating the page selecting, data storing, ECC computation performing, and data outputting steps so that data output is continuous across page boundaries and from logically contiguous memory locations without wait intervals; wherein the page selecting step initially comprises selecting a default page in the NAND flash memory array, and subsequently comprises selecting successive sequential pages of the NAND flash memory array; wherein the page selecting, data storing, and ECC computation performing steps are initially performed automatically during power-up of the flash memory, and are subsequently performed in response to a read command; wherein the data outputting step is performed in response to the read command; wherein the memory further comprises a power-up detector, the method further comprising initiating the initially performed page selecting step and the initially performed data storing step from the power-up detector during power-up of the memory; and wherein the memory further comprises a buffer mode flag, the method further comprising setting the buffer mode flag into a continuous page read mode from the power-up detector upon power-up.