Patent ID: 9402311
Filing Date: 2016-07-26
CPC Classification: H01L,H05K,Y02P

Claim Text:
1. A semiconductor module comprising: a substrate made of a metal; an insulating layer formed on the substrate; a plurality of wiring patterns formed on the insulating layer; a bare-chip transistor mounted on one wiring pattern out of the plurality of wiring patterns via a solder; and a copper connector formed of a copper plate, the copper connector jointing an electrode formed on a top surface of the bear-chip transistor and another wiring pattern out of the plurality of wiring patterns via a solder, wherein the copper connector includes an electrode-jointing portion jointed to the electrode of the bare-chip transistor and a substrate-jointing portion arranged to face the electrode jointing portion in one direction and jointed to the another wiring pattern out of the plurality of wiring patterns, a width of the electrode-jointing portion in a direction perpendicular to the one direction is smaller than a width of the substrate-jointing portion in the direction perpendicular to the one direction, a stress-reducing portion is arranged between the electrode-jointing portion and the substrate jointing portion, the stress-reducing portion includes a flat plate portion, a first coupling portion bent down from one end of the flat plate portion, and a second coupling portion bent down from another end of the flat plate portion so as to form a bridge shape, the electrode-jointing portion is formed to be bent from the first coupling portion and to extend outward, and the substrate jointing portion is formed to be bent from the second coupling portion and to extend outward, and balancing rib portions is formed at both ends of the flat plate portion in the direction perpendicular to the one direction, respectively, the balancing rib portions being bent down from the both ends, respectively.