Patent ID: 9495320
Filing Date: 2016-11-15
CPC Classification: G06F

Claim Text:
1. A method comprising: receiving a sequence of bytes from at least one lane of a peripheral device bus, wherein the sequence of bytes combine to form packets, the packets including dead cycles and wherein each byte of the sequence of bytes is received in one of a sequence of clock cycles; identifying a byte of the sequence of bytes corresponding to the start of a packet; storing the byte corresponding to the start of the packet in a buffer; sending the byte corresponding to the start of the packet to a data link layer at least one clock cycle after it is received; identifying a dead cycle of the sequence of bytes received in a clock cycle after the start of the packet and before the end of the packet; and sending to the data link layer the byte corresponding to the clock cycle after the dead cycle during the clock cycle corresponding to the dead cycle.