Patent ID: 9361027
Filing Date: 2016-06-07
CPC Classification: G06F,G11C,H03K

Claim Text:
1. A device comprising: an address decoding logic component operable to output an enable signal based on an address signal; x bit registers including a first portion and a second portion, each of said x bit registers being operable to store one of x stored bits of data, respectively, said first portion having 0 x/2 write lines, each of which is operable to provide one of x/2 new bits of data into a corresponding one of said bit registers in said first portion, respectively; x/2 read lines, each of which is operable to output one of the stored bits of data from a corresponding one of said bit registers in said first portion, respectively; x/2 functional components, each of which is operable to provide a modified enable signal to a corresponding one of said bit registers in said first portion, respectively; and a masking component operable to generate x/2 masking signals and to provide one of the x/2 masking signals to a corresponding one of said functional components, respectively, wherein each modified enable signal is based on the enable signal and a corresponding masking signal, wherein each of said bit registers in said first portion is operable to modify a stored bit therein, respectively, based on the corresponding modified enable signal, respectively, and wherein x is an integer greater than or equal to 2.