Patent ID: 9256480
Filing Date: 2016-02-09
CPC Classification: G06F,G06K

Claim Text:
1. A method performable by a processor including an accumulator, the method comprising: selecting at least one event, thereby producing at least one selected event; generating a reset signal to the accumulator responsive to said at least one selected event; responsive to said reset signal, resetting the accumulator to zero or an initial value while avoiding breaking pipelined execution of the processor; and storing said at least one event in an event register; wherein said selecting said at least one event is performed by: logically ANDing a first input from said event register with a second input from an event selection register thereby producing a first AND output including a first plurality of outputs, and logically ORing together the first plurality of outputs, thereby producing a first OR output, wherein said generating a reset signal to the accumulator is responsive to said first OR output.