Patent ID: 9257535
Filing Date: 2016-02-09
CPC Classification: B82Y,H01L

Claim Text:
1. A method for forming a semiconductor device, comprising: providing a crystalline silicon layer overlying a first silicon dioxide layer, wherein the crystalline silicon comprises a first thickness; oxidizing a transistor channel region of the crystalline silicon to thin the crystalline silicon at the transistor channel region to a second thickness while a semiconductor source region and a semiconductor drain region remain unoxidized; forming a first patterned mask to cover the semiconductor source region, the semiconductor drain region, and the transistor channel region while other portions of the crystalline silicon remain exposed; oxidizing the exposed regions of the crystalline silicon while the semiconductor source region, the semiconductor drain region, and the transistor channel region are covered by the patterned mask; removing the first patterned mask after oxidizing the exposed regions of the crystalline silicon; forming a second patterned mask to cover the semiconductor source region and the semiconductor drain region, and leaving the transistor channel region exposed; etching silicon dioxide surrounding the transistor channel region to form a floating nanowire bridged between the semiconductor source region and the transistor channel region, while the semiconductor source region and the semiconductor drain region are covered by the second patterned mask, then removing the second patterned mask; forming a transistor gate oxide on the floating nanowire wherein, in a cross section of the floating nanowire, the transistor gate oxide completely surrounds the floating nanowire; forming a transistor gate metal on the transistor gate oxide; and forming semiconductor source, semiconductor drain, and transistor gate metallizations.