Patent ID: 9299618
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: providing a bulk silicon substrate comprising a first device region for a first semiconductor device of a first conductivity type and an adjacent second device region for a second semiconductor device of a second conductivity type; recessing an exposed portion of said bulk silicon substrate in said first device region to expose a sub-surface of said bulk silicon substrate, wherein a hard mask layer portion is present on said second device region during said recessing; forming a first semiconductor material stack of, from bottom to top, a semiconductor punch through stop layer comprising a first carbon-doped silicon layer containing at least one dopant of said second conductivity type which is opposite from said first conductivity type, a semiconductor diffusion barrier layer comprising a second carbon-doped silicon layer containing no n- or p-type dopant, and an epitaxial semiconductor layer comprising silicon or a silicon germanium alloy on said sub-surface of said bulk silicon substrate and in said first device region; removing said hard mask layer portion in said second device region; recessing said bulk silicon substrate in said second device region to expose another sub-surface of said bulk silicon substrate in said second device region; forming a second semiconductor material stack on said another sub-surface of said bulk silicon substrate and in said second device region, wherein said second semiconductor material stack comprises, from bottom to top, a first silicon germanium alloy layer containing at least one dopant of said first conductivity type, a second silicon germanium alloy er containing no further dopant, and another epitaxial semiconductor layer; and forming a plurality of first semiconductor fins in said first device region and a plurality of second semiconductor fins in said second device region, wherein each first semiconductor fin of said plurality of first semiconductor fins comprises, from bottom to top, a remaining portion of said semiconductor punch through stop layer, a remaining portion of said semiconductor diffusion barrier, and a remaining portion of said epitaxial semiconductor layer.