Patent ID: 9344090
Filing Date: 2016-05-17
CPC Classification: H01L,H03K

Claim Text:
1. A programmable logic device comprising a plurality of logic cells arranged in matrix, each of the logic cells comprising: a programmable switch comprising a first input terminal, a second input terminal, and an output terminal, and being configured to electrically connect the output terminal to one of the first input terminal and the second input terminal, and a logic circuit, wherein the programmable switch is able to keep configuration in absence of supply of a power supply potential to the programmable switch, and wherein the programmable switch comprises: wherein the third transistor comprises an oxide semiconductor layer overlapping with the third gate electrode, wherein the oxide semiconductor layer comprises a c-axis aligned crystalline oxide semiconductor film, wherein the programmable switch is configured such that, when the third transistor is in an on state, either one of a first configuration or a second configuration is formed, and that the one of the first configuration or the second configuration is maintained after the third transistor is turned off, wherein the first configuration allows a first signal that is input from the other of the first source electrode and the first drain electrode to be output to a terminal of the logic circuit by passing through the first transistor, and wherein the second configuration allows a second signal that is input from the other of the second source electrode and the second drain electrode to be output to the terminal of the logic circuit by passing through the second transistor.