Patent ID: 9262265
Filing Date: 2016-02-16
CPC Classification: G06F,G11C,H03M,H04L

Claim Text:
1. A storage system comprising: a plurality of flash memory packages; a system controller including: a first memory controller of the first flash memory that is configured to receive the new data for generating an intermediate parity from the new data and the old data and transfer the intermediate parity from the first flash memory package to the buffer memory, while the first memory controller maintains the new data and the old data as a valid status, wherein the processor is further configured to transfer the intermediate parity with an intermediate parity transmission command for generating a new parity to a second flash memory package storing an old parity via the buffer memory without storing the intermediate parity into the cache memory, wherein the storage system further comprises a second memory controller of the second flash memory package configured to receive the intermediate parity for generating the new parity from the intermediate parity and the old parity, and transfer a completion response regarding the intermediate parity transmission command for generating the new parity to the processor, and wherein the processor is further configured to transfer a commit command to the first flash memory package for invalidating the old data according to receiving the completion response from the second flash memory package so that the old data is deleted by the first memory controller after receiving the commit command.