Patent ID: 9436473
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. Apparatus for processing data comprising: a plurality of execution circuits configured to execute a common program as a respective plurality of threads of program execution; and scheduling circuitry configured to determine a next scheduled execution position within said common program corresponding to a next program instruction to be executed by at least one of said plurality of execution circuits while any of said plurality of execution circuits at a current execution position in an execution path through said common program not followed by said next scheduled position do not execute said next program instruction; wherein said scheduling circuitry is configured to: calculate a runner up execution position that would have been determined as said next scheduled execution position if said next program instruction was excluded from serving as said next scheduled execution position; determine said next scheduled execution position so as to follow an execution path corresponding to consecutive instructions in program counter order unless a point of full determination is detected by said scheduling circuitry whereupon said scheduling circuitry performs a full determination of said next scheduled execution position that provides for one or more possible execution paths not corresponding to consecutive instructions in program counter order; calculate said runner up execution position upon said detection of a current point of full determination; and detect a further point of full determination if said execution path reaches said runner up execution position.