Patent ID: 9438219
Filing Date: 2016-09-06
CPC Classification: H02M,H03K

Claim Text:
1. An apparatus, comprising, a first pulse width modulator and a controller to provide a first digital duty command to the first pulse width modulator, wherein the first digital duty command specifies a duty to within a fraction of a cycle of a system clock to the first pulse width modulator, and wherein the first pulse width modulator is configured to: generate a first digital delay value based on a value of the first digital duty command and a maximum value of the first digital duty command; assert an edge of a pulse based on most significant bits of the first digital delay value; select a first one of multiple phases of the system clock based on least significant bits of the first digital delay value; and re-time the edge of the pulse based on the first selected phase of the system clock to adjust a width of the pulse.