Patent ID: 9313894
Filing Date: 2016-04-12
CPC Classification: H01L,H05K,Y02P

Claim Text:
1. A wiring substrate comprising: a core including a first surface, a second surface, and a cavity, wherein the second surface is located at an opposite side of the first surface, and the cavity extends through the core in a thicknesswise direction and includes a first opening in the first surface and a second opening in the second surface; a first wiring layer formed on the first surface of the core; a second wiring layer formed on the second surface of the core; an electronic component partially accommodated in the cavity and including a projected portion projected from the first opening of the core; a first insulating layer covering over the first wiring layer and the first surface of the core, wherein the first insulating layer covers at least a portion of a side surface of the electronic component and fills a portion of the cavity; a second insulating layer that covers a first surface of the first insulating layer; a plurality of first via wires each extending through the first and second insulating layers in the thicknesswise direction, wherein the first wiring layer and the electronic component are electrically connected to different ones of the plurality of first via wires; a third insulating layer that covers the second surface of the core, wherein the remainder of the cavity that is not filled with the first insulating layer is filled with the third insulating layer; a third wiring layer formed on the second insulating layer and electrically connected to the electronic component and the first wiring layer through the different ones of the plurality of first via wires; a second via wire that extends through the third insulating layer; and a fourth wiring layer formed on the third insulating layer and electrically connected to the second wiring layer through the second via wire.