Patent ID: 9330755
Filing Date: 2016-05-03
CPC Classification: G11C

Claim Text:
1. A circuit, comprising: at least one two terminal element programmable between at least two impedance states; a write section configured to place the element into different impedance states in a write mode; and a read section configured to generate an output value corresponding to the impedance state of at least one element in a read mode; wherein the at least one element draws substantially no current in a standard mode that is different from the write and read modes, the read section includes at least one latch circuit configured to statically store the output value in response to the read mode, the latch circuit including an inverter having an inverter input coupled to at least one element, a first feedback transistor having a controllable impedance path coupled between the inverter input and a first power supply node, and a control terminal coupled to an inverter output, and an isolation transistor having a controllable impedance path in series with that of the first feedback transistor between the inverter input and a power supply node; wherein the isolation transistor is in a high impedance state in the standard mode.