Patent ID: 9396358
Filing Date: 2016-07-19
CPC Classification: G06F

Claim Text:
1. A method for securing an integrated circuit (IC), comprising: detecting a tamper condition via a circuit in the IC; placing the IC in a configurable state; switching a multiplexer internal to the IC from selecting settings for scan pins from one or more pins of the integrated circuit to selecting settings for scan pins from a controller circuit internal to the IC, thus disabling a scan chain interface in the IC while in the configurable state, wherein the disabling prevents external input to the scan chain interface and external output from the scan chain interface and enables sending an internal instruction from the controller circuit via the multiplexer and the scan chain interface; sending, from the controller circuit internal to the integrated circuit, the internal instruction via the scan chain interface, with the external input prevented, wherein the internal instruction directs erasing a specified sector of a memory module; initiating a power down operation in the IC; and powering down the IC.