Patent ID: 9230889
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A chip arrangement, comprising: a carrier; at least one chip comprising at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and a plurality of low temperature co-fired ceramic sheets disposed over a bottom side of the carrier, the carrier bottom side being opposite to the side over which the chip is disposed and wherein each of the plurality of low temperature co-fired ceramic sheets has an entirely exposed surface facing away from the carrier, the exposed surfaces being coplanar with each other, wherein the encapsulation material is formed over the at least one chip and over one or more sidewalls of the carrier so that at least one bottom surface of the encapsulation material abuts and is co-planar with the bottom side of the carrier, wherein at least one of the plurality of low temperature co-fired ceramic sheets is disposed directly on a portion of the bottom side of the carrier and directly on a portion of the at least one bottom surface of the encapsulation material that abuts and is co-planar with the bottom side of the carrier.