Patent ID: 9299447
Filing Date: 2016-03-29
CPC Classification: G11C

Claim Text:
1. A semiconductor device, comprising: a plurality of memory blocks, wherein each of the plurality of memory blocks comprises: a first select transistor electrically coupled to a common source line; a second select transistor electrically coupled to a bit line; a plurality of memory cells electrically coupled between the first and second select transistors; and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, applying a first positive voltage to gates of the first select transistors of unselected memory blocks of the plurality of memory blocks, and setting word lines coupled to gates of the memory cells of the unselected memory blocks to a floating state when an erase voltage is applied to the common source line during the erase operation.