Patent ID: 9496018
Filing Date: 2016-11-15
CPC Classification: G06F,G11C

Claim Text:
1. A memory, comprising: a plurality of non-volatile memory devices, each comprising a plurality of nonvolatile memory cells; a write controller configured to stream bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that optimize a speed of writing to the memory devices to provide writes at a first speed, wherein consecutive groups of bits are written to consecutive memory cells within respective memory devices; a self-referenced read controller configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel having read drivers, receivers, and read bus topology; and a bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.