Patent ID: 9472579
Filing Date: 2016-10-18
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate comprising: a substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer in the pad region of the substrate, the pad region configured to connect to a connection wiring of a flexible circuit board; an insulating layer extending over the substrate within the TFT formation region but not into the pad region; a second electrode layer directly on the first electrode layer in the pad region to cover the first electrode; and a conductive layer for connecting the second electrode to the connection wiring, wherein a lower surface of the second electrode layer in the pad region contacts the first electrode layer without the insulation layer between the lower surface of the second electrode layer and the first electrode layer, and wherein an upper surface of the second electrode layer in the pad region contacts the conductive laver, and wherein no dielectric layer is on the first and second electrodes in the pad region.