Patent ID: 9252226
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A thin film transistor array panel, comprising: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, wherein: the data wiring layer comprises a main wiring layer and an outermost capping layer in direct contact with an upper surface of the main wiring layer, the main wiring layer being disposed between the outermost capping layer and the oxide semiconductor layer; the main wiring layer comprises copper and the capping layer comprises a metallic copper alloy; a continuous thickness of the main wiring layer is greater than a continuous thickness of the capping layer; and a lateral side wall of the main wiring layer aligns substantially flush with an edge of a lateral side wall of the capping layer.