Patent ID: 9472283
Filing Date: 2016-10-18
CPC Classification: G11C,H01L

Claim Text:
1. A memory device comprising: a first conductive line extending in a first direction; second conductive lines each extending in a second direction intersect with the first direction; a third conductive line extending in a third direction intersect with the first and second directions; resistance change elements connected between the second conductive lines and the third conductive line respectively; a semiconductor layer connected between the first conductive line and one end of the third conductive line; a select field effect transistor (FET) having a select gate electrode, and using the semiconductor layer as a channel; and a control circuit which is configured to execute a set/reset of at least one of the resistance change elements, and execute an operation which sets the first conductive line to a first potential, sets the select gate electrode to a second potential, sets all of the second conductive lines connected with the resistance change elements to the third conductive line to a third potential, and sets at least one of the first potential or the third potential to higher than the second potential, after the set/reset.