Patent ID: 9396775
Filing Date: 2016-07-19
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor memory device, comprising: first and second memory cell arrays; a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array, wherein the control circuit includes a first pad through which the first information is output and a second pad through which the second information is output; and first and second caches that respectively hold data transferred from the first and second memory cell arrays, wherein when the first information indicates that the first memory cell array is in the ready state, the first cache is accessible from outside the device, when the second information indicates that the second memory cell array is in the ready state, the second cache is accessible from outside the device, and when the control circuit receives a first command to access the first memory cell array and a second command to access the second memory cell array after receiving the first command, the control circuit is configured to perform a process instructed by the first command and then perform a process instructed by the second command within a time period that is shorter than two times a time period for completing the process instructed by the first command.