Patent ID: 9236115
Filing Date: 2016-01-12
CPC Classification: G11C,H01L

Claim Text:
1. A circuit for improving process robustness of sub-threshold SRAM memory cells, wherein, the circuit serves as an auxiliary circuit for a sub-threshold SRAM memory cell, the output (V bp ) of the circuit is connected to a PMOS transistor of the sub-threshold SRAM memory cell and a substrate of the PMOS transistor in the circuit; the circuit comprises a detection circuit for a threshold voltage of the PMOS transistor and a differential input and single-ended output amplifier, wherein: the detection circuit for threshold voltage of the PMOS transistor comprises a first PMOS transistor (P a source terminal of the first PMOS transistor (P a source terminal and a substrate of the first NMOS transistor (N the differential input and single-ended output amplifier comprises a second PMOS transistor (P a drain terminal and a gate terminal of the second PMOS transistor (P a gate terminal of the second NMOS transistor (N substrates of the second NMOS transistor (N