Patent ID: 9491332
Filing Date: 2016-11-08
CPC Classification: G06F,G09G,H04N

Claim Text:
1. A clock transfer circuit which receives input data synchronized with a first clock and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock, comprising: a memory; a write address controller that generates a write address of the memory in which the input data is written, the write address controller operating according to the first clock; a read address controller that generates, in order of writing the input data, a read address of the memory from which the output data is read, the read address controller operating according to the second clock; a cycle comparator that compares a held first value and a second value obtained after the first value is held, the first and second values each indicating a time difference of a predetermined event between the input data and the output data; and a clock adjuster that adjust, based on a comparison result obtained by the cycle comparator, the frequency of the second clock such that the time difference is maintained constant.