Patent ID: 9443602
Filing Date: 2016-09-13
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A storage device, comprising: a storage medium; a DLL circuit that gives a predetermined amount of delay to an inputted clock signal; a latch circuit that latches data outputted from the storage medium according to the clock signal delayed by the DLL circuit; and a delay amount adjustment circuit that adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit, wherein the delay amount adjustment circuit confirms whether a latch timing by the latch circuit is normal or not based on a result of the latch circuit latching predetermined data series, and, in a case where the latch timing is abnormal, the delay amount adjustment circuit adjusts the delay amount over a plurality of times, confirms whether each latch timing corresponding to each delay amount after the adjustment is normal or not based on a result of the latch circuit latching the predetermined data series based on each delay amount after the adjustment, and selects a median of the delay amounts asserting normal latch timings as a final delay amount after the adjustment.