Patent ID: 9507896
Filing Date: 2016-11-29
CPC Classification: G06F

Claim Text:
1. A method for simulating a circuit design, the method comprising: identifying a specified region of a circuit design for manufacturing, the circuit design comprising a set of logic elements having common inputs corresponding to one or more inputs of the specified region of the circuit design; identifying one or more inputs of the specified region of the circuit design having a state change; selecting a subset of the identified one or more inputs of the specified region of the circuit design that have an input change; for each input of the selected subset of the identified one or more inputs of the specified region of the circuit design: determining a maximum logic level depth of the one or more logic elements coupled to the selected subset of inputs of the identified one or more inputs of the specified region of the circuit design from the computed logic level depths; scheduling for simulation, by one or more processors, one or more logic elements coupled to the selected subset of the identified one or more inputs of the specified region of the circuit design; and simulating in parallel, in accordance with the scheduled simulation of the simulation range of logic levels, the one or more logic elements coupled to the selected subset of the identified one or more inputs of the specified region of the circuit design.