Patent ID: 9471281
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A computer system for executing vectorized Galois field multiplication for first and second input operands, the system comprising: a memory; and a processor, communicatively coupled to said memory and comprising a single hardware tree including AND gates for partial products where adjacent bit elements for adjacent partial products are respectively generated from a first AND gate having input provided from first bit elements of the first and second input operands, and a second AND gate having input provided from the first bit element of the first input operand and a second bit element of the second input operand, the processor of the computer system being configured to perform a method comprising: subdividing the first and second input operands into vector elements of equal sizes with multiple modes defined such that a base mode has a size corresponding to a smallest vector element size, which is a factor of a size of the first and second input operands, and a higher mode has a size that is a multiple of the base mode size; modifying the vector elements of the first input operand with a bit mask based on a size of the vector elements; and inputting, by the processor, the modified vector elements of the first input operand and the vector elements of the second input operand into the single hardware tree configured for subdivision into staggered subtrees a size of each of which being based on the base mode size.