Patent ID: 9514831
Filing Date: 2016-12-06
CPC Classification: G11C,H03L

Claim Text:
1. A circuit for providing a plurality of clock signals of differing frequencies, comprising: a phase locked loop section connected to receive a reference clock value and provide a first clock signal, including a first voltage controlled oscillator connected to receive a first voltage level and generate therefrom the first clock signal, the first voltage level being generated by the phase locked loop section based upon the reference clock value and feedback from the first clock signal; and one or more second voltage controller oscillators, each connected to receive the first voltage level and a corresponding trim value and, concurrently with the generating of the first clock signal, generate therefrom a respective second clock signal having a frequency dependent upon the first voltage level and corresponding trim value, wherein one or more of the second voltage controlled oscillators is further connected to receive a corresponding control voltage, the respective second clock signal having a frequency further dependent upon the corresponding control voltage's level, and wherein the one or more second voltage controlled oscillators increase the frequency of the respective second clock signal in response to the corresponding control voltage's level increasing.