Patent ID: 9286981
Filing Date: 2016-03-15
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a memory block comprising a content addressable memory (CAM) cell array and a memory cell array, the CAM cell array that stores data for internal operation conditions of the semiconductor device; a page buffer that programs data in the memory block or reads the data programmed in the memory block and receives a page buffer power-supply signal after lapse of a predetermined time from initialization of latches of the page buffer; a control logic that activates a reset enable signal during a reset operation and outputs the activated reset enable signal; and a power-supply controller that activates a reset control signal to initialize the page buffer according to an external power-supply signal when the reset enable signal is activated, and provides the page buffer power-supply signal to the page buffer after the reset control signal is activated, wherein the power-supply controller provides the page buffer power-supply signal after initialization of the page buffer, and wherein the page buffer power-supply signal is generated in response to the external power-supply signal.