Patent ID: 9524912
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method for fabricating a CMOS inverter, comprising: providing a substrate; forming a first active region and a second active region in the substrate; forming a first isolation structure surrounding the first active region and a second isolation structure surrounding the second active region in the substrate; forming a first gate structure on the first active region and a second gate structure on the second region; forming a first connect structure connecting with the first gate structure and a second connect structure connecting with the second gate structure; and forming a plurality of first metal interconnect structure in the first active region and a plurality of the second metal interconnect structure in the second active region; wherein the first gate structure is a shunted gate structure having a plurality of parallel first parts and a plurality of parallel second parts sequentially connected with the first parts with a pre-determined angle; a portion of the second metal interconnect structure is formed in the second active region and the other portion of the second metal interconnect, structure is formed on the second isolation structure; and the first connect structure connects with the second connect structure.