Patent ID: 9251054
Filing Date: 2016-02-02
CPC Classification: G06F

Claim Text:
1. A computer program product for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration, the computer program product tangibly embodied in a non-transitory machine readable medium, said computer program product including instructions executed by a memory controller of a memory subsystem to cause the memory subsystem to perform the steps comprising: configuring a first buffer and a second buffer of the dual port DRAM; providing a respective validity counter with each of the first buffer and the second buffer; incrementing a validity counter for a receiving buffer with each respective data row from a transferring buffer being validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, and decrementing the validity counter for the transferring buffer; and reading data from and writing data to one of the respective first buffer or second buffer based upon a respective count value of the respective validity counters.