Patent ID: 9325601
Filing Date: 2016-04-26
CPC Classification: G06F,G11C,H04L

Claim Text:
1. A method that reduces a row cycle time of an individual memory module to an effective row cycle time shorter than the row cycle time using a plurality of memory modules having a circular sequence, including: initiating a set of read operations on different memory modules of the plurality of memory modules in the circular sequence from a first read operation initiated on a first module of the plurality of memory modules to a last read operation initiated on a second module; and after initiating each read operation of the set of read operations on a particular memory module of the plurality of memory modules and prior to initiating a next read operation in the set of read operations, initiating a set of write operations to write a same value to all of the plurality of memory modules in the circular sequence beginning one memory module after the particular memory module, wherein the set of write operations completes prior to the next read operation.