Patent ID: 9263399
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate on which a semiconductor element is formed; first and second pads; a first insulating film formed above the semiconductor substrate; a plurality of wiring lines embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer and electrically connected with the first pad; and a drain electrode connected with the semiconductor layer and electrically connected with the second pad, wherein the plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer, and wherein the semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.