Patent ID: 9444480
Filing Date: 2016-09-13
CPC Classification: H03M

Claim Text:
1. An analog-to-digital converter (ADC) circuit comprising: at least a first, a second, and a third ADC slice configured to sample an analog input signal and transmit a digitally converted signal thereof representative of a first, a second, and a third value of the analog input signal at a first, a second, and a third consecutively sampled time point thereof, respectively; at least one reference ADC slice configured to sample the analog input signal and transmit a digitally converted reference value to facilitate determining an error value; a first, a second, and a third register coupled to said first, second, and third ADC slices, and configured to store the first, second, and third values, respectively; a reference register coupled to said at least one reference ADC slice, and configured to store the reference value; a delay register comprising an input and an output, and configured to produce a sample time adjustment signal, wherein the sample time adjustment signal facilitates adjustment of a phase of a next time sampling of the analog input signal by said second ADC slice; and a plurality of computational circuit elements coupled to said input, said output, said first, second, and third registers, and said reference register, and configured to determine the error value, a value of an approximate time derivative of the analog input signal estimated from the third, the second, and the first sampled time point, and a value of the sample time adjustment signal.