Patent ID: 9263458
Filing Date: 2016-02-16
CPC Classification: G11C,H01L

Claim Text:
1. A non-volatile memory comprising: a substrate; and a plurality of cell blocks aligned on the substrate, each of the cell blocks including a plurality of first non-volatile memory cells connected in series, connecting a first end of a series of the first non-volatile memory cells to a bit line through a first selection transistor, and connecting a second end of the series of the first non-volatile memory cells to a source line through a second selection transistor, each of the plurality of first non-volatile memory cells comprising a first non-volatile memory cell comprising a first insulating film formed on a first silicon channel, a plurality of floating gates including a first floating gate formed on the first insulating film, a second insulating film formed on the first floating gate, a first gate electrode formed on the second insulating film, a first source layer and a first drain layer formed to sandwich the first silicon channel; and the first or the second selection transistor comprising a third insulating film formed on a second silicon channel, a second floating gate formed on the third insulating film, a fourth insulating film formed on the second floating gate, a second gate electrode formed on the fourth insulating film, a first contact to connect the second floating gate to a third gate electrode, a second source layer and a second drain layer formed to sandwich the second silicon channel, wherein an area S1 of the first insulating film at which the first floating gate is in contact with the first silicon channel is larger than an area S2 of the second insulating film at which the first floating gate is in contact with the first gate electrode, an air gap is provided between adjacent ones of the first non-volatile memory cells, and the air gap is vacuumed or injected with gas, and a capacitance ratio of a first capacitance between an adjacent pair of floating gates from the plurality of floating gates compared to a second capacitance between the first gate electrode and the first floating gate is 30% or less.