Patent ID: 9335856
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. A display device comprising: a display pixel allocated at a matrix state in a display area; an image-reading device which detects strength of capacitive coupling by a dielectric material coming close to or making contact with the display area; and a control portion which controls each transistor of the image-reading device, wherein the image-reading device comprises: a pre-charge gate line, a coupling pulse line and a readout gate line, these lines supplying a signal driving the image-reading device; a detection electrode which forms capacitance between the detection electrode and the dielectric material; a pre-charge line which applies a voltage to the detection electrode; a readout line which reads a detection signal from the detection electrode; a pre-charge transistor in which one of a source electrode and a drain electrode is electrically connected to the pre-charge line, and a gate electrode is electrically connected to the pre-charge gate line; an amplification transistor in which one of a source electrode and a drain electrode is electrically connected to an other one of the source and drain electrodes of the pre-charge transistor, and a gate electrode is electrically connected to the detection electrode; a readout transistor in which one of a source electrode and a drain electrode is electrically connected to an other one of the source and drain electrodes of the amplification transistor, and an other one of the source and drain electrodes is electrically connected to the readout line, and a gate electrode is electrically connected to the readout gate line; a compensation transistor in which one of a source electrode and a drain electrode is electrically connected to said other one of the source and drain electrodes of the amplification transistor, and an other one of the source and drain electrodes is electrically connected to the detection electrode, and a gate electrode is electrically connected to the pre-charge gate line; and a power-source switching transistor in which one of a source electrode and a drain electrode is electrically connected to said one of the source and drain electrodes of the amplification transistor, and an other one of the source and drain electrodes is electrically connected to the coupling pulse line, and a gate electrode is electrically connected to the readout gate line.