Patent ID: 9343166
Filing Date: 2016-05-17
CPC Classification: G11C

Claim Text:
1. A non-volatile semiconductor memory device comprising a plurality of word lines formed in a matrix to which either one of a charge storage gate voltage and a charge storage inhibition gate voltage is applied, a plurality of memory cells connected to the respective word lines, and a bit line that applies a selective voltage to the plurality of memory cells, a charge being stored in selected one of the plurality of memory cells due to a voltage difference between the charge storage gate voltage applied to the word line and the voltage applied to the bit line, further comprising power supply units respectively provided for word line columns and common wirings respectively provided for word line rows, each of the common wirings applying a predetermined common voltage to the power supply units on a word-line-row basis, each of the power supply units including switching mechanisms that are respectively provided for the word lines and respectively connect the word lines to the common wirings, and a unit wiring that uniformly applies different unit voltages to each of the switching mechanisms in the power supply unit depending on whether or not the selected memory cell exists in the word line column, wherein the switching mechanisms in each of the power supply units are turned on or off based on a voltage difference between the unit voltages applied to each of the power supply units and the common voltage, to individually apply the charge storage gate voltage or the charge storage inhibition gate voltage to each of the word lines via the power supply unit, and wherein the switching mechanisms respectively include at least a PMOS switch and an NMOS switch, and the PMOS switch and the NMOS switch are individually turned on or off based on a voltage difference between the common voltage and the unit voltages occurring when the common voltage and the unit voltage are respectively applied thereto.