Patent ID: 9356609
Filing Date: 2016-05-31
CPC Classification: H01Q,H03K,H03L

Claim Text:
1. A phase-locked loop (PLL) comprising: an oscillator configured to generate an output signal at an output of the PLL responsive to a reference signal input to the PLL, the oscillator including a primary control input and a separate auxiliary control input; a detector configured to compare the reference signal to a feedback signal to generate one or more PLL control signals, the feedback signal being derived by a feedback loop of the PLL from the output signal; and a phase control system configured to control a phase of the output signal to achieve a desired phase shift at the output of the PLL, the phase control system comprising: a phase skew circuit configured to execute closed-loop phase control of the PLL to maintain the phase of the output of the PLL at the desired phase shift by setting a time relationship between the reference signal and the feedback signal based on the desired phase shift.