Patent ID: 9374090
Filing Date: 2016-06-21
CPC Classification: H03K

Claim Text:
1. A circuit arrangement comprising: a level shifting stage configured to be coupled to a first reference voltage and a second reference voltage; a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage, the first input voltage configured to switch between a first logic state and a second logic state; a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage, the second input voltage configured to switch between the first logic state and the second logic state; an output stage coupled to the level shifting stage, the output stage comprising an output node, the level shifting stage configured to generate an output voltage above a predetermined output level at the output node due to the first reference voltage when the first input voltage is in the first logic state and the second input voltage is in the second logic state; and wherein the level shifting stage is further configured to generate the output voltage below the predetermined output level at the output node due to the second reference voltage when the first input voltage is in the second logic state and the second input voltage is in the first logic state; a feedback circuit coupled to the output stage and the level shifting stage; and a voltage stabilization circuit coupled to the level shifting stage; wherein the level shifting stage comprises a switching mechanism configured to cause an internal current above a predetermined current level to flow through the level shifting stage due to the first reference voltage and the second reference voltage when the switching mechanism is activated, the switching mechanism further configured to at least reduce the internal current flowing through the level shifting stage to below the predetermined current level when the switching mechanism is deactivated; wherein the feedback circuit comprises a feedback mechanism configured to be deactivated when the output voltage is above the predetermined output level, and the feedback mechanism is further configured to be activated when the output level is below the predetermined output level; wherein the switching mechanism is configured to be activated when the first input voltage is in the first logic state and when the feedback mechanism is activated; and wherein the switching mechanism is further configured to be deactivated when the first input voltage is in the first logic state and when the feedback mechanism is deactivated; and wherein the voltage stabilization circuit is configured to maintain the output voltage at above the predetermined output level when the internal current flowing through the level shifting stage is reduced.