Patent ID: 9436793
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. A method for tier based layer modification for a design layout, comprising: evaluating a metal scheme for a design layout to group metal layers of the design layout into a set of tiers based upon a resistivity associated with the respective metal layers; identifying a first net within the design layout, the first net comprising a first wire segment; determining a current performance for the first wire segment based upon a current tier, of the set of tiers, to which the first wire segment is assigned; determining a potential performance for the first wire segment based upon a potential tier, of the set of tiers, to which the first wire segment could be reassigned; evaluating the current performance and the potential performance to either retain an assignment of the first wire segment to the current tier or reassign the first wire segment to the potential tier; and forming the first wire segment within an integrated circuit according to the design layout, wherein: