Patent ID: 9240330
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor integrated circuit device comprising: preparing a semiconductor wafer having a device main surface and back surface; forming, from the device main surface of the semiconductor wafer to a semiconductor surface region of the semiconductor wafer, a plurality of holes reaching the inside thereof; forming an insulating film on the inner surface of the holes including the sides and the bottom portion of the holes; removing the insulating film at the bottom portion of the holes; burying a conductive member in the holes while covering, with the insulating film, the inner surface of the holes except for the bottom portion thereof, and thereby forming a plurality of through via electrodes; and after the operation of burying the conductive member in the holes but during a wafer process process, irradiating electron beams to the device main surface of the semiconductor wafer to test a conduction state of the through via electrodes.