Patent ID: 9514991
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a FinFET device, comprising: providing a substrate including a fin structure and shallow trench isolation (STI) features, the fin structure including a plurality of fins, the STI features being between each fin of the fin structure; forming a first gate structure over the fin structure; forming first gate spacers on sidewalls of the first gate structure; partially removing the first gate spacers, leaving portions of the first gate spacers within corners where the fin structure and the first gate structure meet; forming second gate spacers on sidewalls of the first gate structure; forming a dielectric layer over the fin structure, the first gate structure, and the second gate spacers; removing the first gate structure and the portions of the first gate spacers thereby exposing sidewalls of the second gate spacers; and forming a second gate structure over the fin structure in a region where the first gate structure and the portions of the first gate spacers have been removed.