Patent ID: 9411731
Filing Date: 2016-08-09
CPC Classification: G06F,G11C

Claim Text:
1. A system comprising: an interfacing module that comprises an input output (I/O) circuit and a transaction request processor; a memory module; a memory controller; a cache controller; and an interconnect that is coupled to the memory module and the memory controller, wherein the interfacing module is arranged to issue a read snoop command of a certain address to the cache controller, wherein the cache controller is arranged, if there is a cache hit and the certain address is marked as an address associated with a single producer and single consumer, to either invalidate a cache line that is located at the certain address or mark that cache line as clean, and wherein the cache controller is arranged to be prevented from invalidating the cache line if the read snoop command is associated with reading only a portion of a cache line, even if there is a cache hit and the certain address is marked as an address associated with a single producer and single consumer.