Patent ID: 9335372
Filing Date: 2016-05-10
CPC Classification: G01R

Claim Text:
1. An integrated circuit comprising: a plurality of delay lines configured to generate a plurality of delayed clock signals, wherein each of the plurality of delay lines comprises a plurality of delay circuits each having an input receiving a clock signal, wherein the clock signals are time-independent relative to each other, and wherein the inputs of the plurality of delay lines are arranged in parallel; a selection circuit including a plurality of inputs configured to receive at least the plurality of delayed clock signals, wherein the selection circuit is configured to generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs of the selection circuit based on a state of a selection control signal; and a delay comparison circuit configured to determine whether or not a manufacturing defect is present within one or more of the plurality of delay lines based on a comparison between a delay of the first output clock signal and a delay of the second output clock signal.