Patent ID: 9412849
Filing Date: 2016-08-09
CPC Classification: B82Y,H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming a first fin-type structure on a first region of a substrate, wherein the first fin-type structure comprises a first semiconductor pattern and a second semiconductor pattern alternately stacked on one another and extending in a first direction; forming a second fin-type structure on a second region of the substrate, wherein the second fin-type structure comprises a third semiconductor pattern and a fourth semiconductor pattern alternately stacked on one another and extending in a second direction; forming a first capping layer extending in a third direction different from the first direction on the first fin-type structure; forming a second capping layer on sidewalls and a top surface of the second fin-type structure, wherein the second capping layer extends in a fourth direction different from the second direction and comprises a semiconductor material; forming a first dummy gate electrode on the first capping layer and a second dummy gate electrode on the second capping layer; exposing the first capping layer and the second capping layer by removing the first dummy gate electrode and the second dummy gate electrode; forming a second wire pattern group comprising the third semiconductor pattern on the second region by removing the second capping layer and the fourth semiconductor pattern; and forming a first wire pattern group comprising the second semiconductor pattern on the first region by removing the first capping layer and the first semiconductor pattern.