Patent ID: 9455333
Filing Date: 2016-09-27
CPC Classification: H01L

Claim Text:
1. A thin film transistor array panel comprising: a substrate; a light blocking film disposed on the substrate; a buffer layer covering the light blocking film; a channel region disposed on the buffer layer; a source region and a drain region facing each other with respect to the channel region, the source region and the drain region being disposed in the same layer as the channel region and connected to the channel region; a gate insulating layer disposed on the channel region; a gate electrode overlapping the channel region, the gate insulating layer interposed between the gate electrode and the channel region; a passivation layer disposed on the gate electrode, the source region, the drain region, and the buffer layer; and a source electrode and a drain electrode disposed on the passivation layer, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.