Patent ID: 9466520
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, comprising the steps: providing a substrate comprising silicon-based single crystal semiconductor material extending to a top surface of the substrate; forming an isolation recess in the substrate; forming a buried isolation layer in the isolation recess, the buried isolation layer comprising dielectric material, so that a top surface of the buried isolation layer is substantially coplanar with the top surface of the substrate adjacent to the buried isolation layer; using a non-selective epitaxial process to form an epitaxial layer of silicon-based semiconductor material on the top surface of the substrate and on the top surface of the buried isolation layer so that the epitaxial layer includes a single-crystalline region on the substrate and a non-crystalline region on the buried isolation layer laterally contacting the single-crystalline region; heating the epitaxial layer by a radiantly-induced recrystallization process that heats the non-crystalline region to a higher temperature than the single-crystalline region so that the non-crystalline region recrystallizes so as to extend the single-crystalline region over the buried isolation layer; and planarizing a top surface of the single-crystalline region over the buried isolation layer.