Patent ID: 9389937
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. An apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: tracking a number of errors associated with a memory page, wherein tracking the number errors associated with the memory page comprises: determining whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting to retire the memory page; determining that the memory page has not been successfully retired because page retirement is not supported by an operating system or a hypervisor; and responsive to determining that the memory page has not been successfully retired because page retirement is not supported by the operating system or the hypervisor, generating a predictive failure alert; wherein determining whether the memory page has been successfully retired further comprises determining whether a new error has occurred at the memory page during a predetermined period of time.