Patent ID: 9401825
Filing Date: 2016-07-26
CPC Classification: H04L

Claim Text:
1. A channel estimation apparatus, comprising: a de-mapping circuit, receiving a plurality of preambles, and mapping the preambles corresponding to a plurality of channels into a real part (I) and an imaginary part (Q) of a quadrature phase shift keying coordinate according to a complex form; a Costas channel estimation circuit, comprising a binary frequency channel estimation circuit and a quadrature frequency channel estimation circuit adapted to respectively perform operations on the real part and the imaginary part according to one of a binary phase shift keying structure and a quadrature phase shift keying structure, wherein the binary frequency channel estimation circuit performs a calculation of “the imaginary part minus the real part” times “a sign value of the real part plus the imaginary part” ((Q−I)*Sign (I+Q)), and the quadrature frequency channel estimation circuit performs a calculation of “the imaginary part times a sign value of the imaginary part” minus “the real part times a sign value of the imaginary part” (Q*Sign (I)−I*Sign (Q)) to output an output value; a loop filter circuit, filtering the output value under a time domain; and a smooth circuit, receiving an output of the loop filter circuit to perform a smooth processing under a frequency domain, and outputting the preambles processed with the smooth processing to external, and feeding back the same to the de-mapping circuit, such that the de-mapping circuit, the Costas channel estimation circuit, the loop filter circuit and the smooth circuit continue channel estimation of a next loop; wherein in the next loop, phases of the preambles are adjusted according to a direction of the output value of the Costas channel estimation circuit approaching to zero.