Patent ID: 9396797
Filing Date: 2016-07-19
CPC Classification: G11C

Claim Text:
1. A program method of a memory device, comprising: loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; performing a second program operation on the second memory cells using the lower bit line; performing a first program verification operation by a first read operation after the first program operation is executed; and performing a second program verification operation by a second read operation after the second program operation is executed, wherein the bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal, and wherein the first and second read operations are both performed by a page data unit.