Patent ID: 9425107
Filing Date: 2016-08-23
CPC Classification: C23C,H01L

Claim Text:
1. A memory device comprising: an insulating surface; a transistor over the insulating surface, the transistor comprising a bit line, a semiconductor layer, a gate insulating layer, and a word line, the gate insulating layer being interposed between a side face of the semiconductor layer and the word line; and a capacitor overlapping the transistor, the capacitor comprising an insulating layer interposed between a capacitor electrode and a capacitor line, the capacitor electrode being in electrical contact with the semiconductor layer, wherein a top surface of the semiconductor layer, a top surface of the gate insulating layer, and a top surface of the word line are in a same horizontal plane, wherein the bit line, the semiconductor layer, the capacitor electrode, the insulating layer, and the capacitor line are stacked in this order, and wherein the semiconductor layer comprises a semiconductor material having a wider band gap than silicon.