Patent ID: 9454496
Filing Date: 2016-09-27
CPC Classification: G06F

Claim Text:
1. A memory system comprising: a memory device including a first memory space configured to be accessed using a first memory address and a second memory space configured to be accessed using a second memory address; and a memory controller configured to access the memory device, wherein the memory controller is configured to translate the first memory address into the second memory address mapped thereto in response to a request for access to the first memory space, access the second memory space using the translated second memory address, and access the second memory space using a non-translated second memory address, in response to a request for access to the second memory space, wherein a reserved area is set in the first memory space to which only a first device is accessible, and wherein the reserved area is a continuous reserved area that is mapped to a discontinuous area of the second memory space, and a shared area is set in the reserved area of the first memory space, a second device different from the first device can access a portion of the second memory space mapped to the shared area of the reserved area, and when the second device accesses a portion of the second memory space mapped to a portion other than the shared area of the reserved area, access violation is generated.