Patent ID: 9348740
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. A multi-core processor system comprising: a shared memory; a plurality of cores comprising, a first group of the plurality of cores configured to make a request concerning exclusive access to the shared memory and a second group of the plurality of cores configured to make a request for a purpose other than exclusive access; and a memory access controller configured to control an access from the plurality of cores to the shared memory on the basis of an access request from the plurality of cores and to detect a request for release from a standby state, the request being sent by a first core of the plurality of cores, wherein the memory access controller, upon detecting the request for release from the standby state, the request being sent by the first core of the first group, sends to the cores among the first group of cores excluding the first core, the notification of release from the standby state.