Patent ID: 9362277
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method comprising: forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural silicon-based (Si-based) layers in each cavity with an increasing percentage of germanium (Ge) or carbon (C) content or with an increasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fins having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and metal gate electrode over the plural Si-based layers.