Patent ID: 9373536
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a metal via over a substrate; depositing a first inter metal dielectric layer over the substrate; depositing a stress reduction layer over the first inter metal dielectric layer; depositing a second inter metal dielectric layer over the stress reduction layer; applying an etching process to the first inter metal dielectric layer, the stress reduction layer and the second inter metal dielectric layer and forming a trench over the metal via; filling the trench with a conductive material to form a metal structure; applying a chemical mechanical planarization process to the second inter metal dielectric layer and the stress reduction layer until the second inter metal dielectric layer is removed and the stress reduction layer is partially removed; and forming an etch stop layer on the stress reduction layer and an upper terminal of the metal structure, wherein the upper terminal of the metal structure has a triangular corner region surrounded by the etch stop layer and the stress reduction layer.