Patent ID: 9252790
Filing Date: 2016-02-02
CPC Classification: H03L

Claim Text:
1. A system including a phase-locked loop (PLL) circuit configured to lock multiple voltage-controlled oscillators (VCOs) for generating a plurality of local oscillator (LO) frequencies, the system comprising: a plurality of VCOs, each VCO generating an output signal of a particular frequency; a plurality of dividers, each divider configured to divide the output signal of a corresponding VCO, the plurality of dividers generating a plurality of divided VCO feedback signals; a phase-to-digital converter (PDC) configured to receive the plurality of divided VCO feedback signals from the plurality of dividers and a reference signal multiplied by a predetermined number indicating a number of the plurality of VCOs, and to generate the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals; a digital loop filter configured to receive and process the phase differences and generate a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and a digital-to-analog converter (DAC) configured to output control voltages for the plurality of VCOs based on the filter output.