Patent ID: 9406753
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method for making a semiconductor device comprising: forming an alternating stack of a plurality of superlattices and a plurality of bulk semiconductor layers on a substrate, each superlattice including a plurality of stacked group of layers, each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; doping bulk semiconductor layers between respective superlattices with alternating dopant conductivity types defining a p-n junction; forming spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattices and bulk semiconductor layers; and forming a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions and defining a depleted channel between the source and drain regions and above the p-n junction; wherein the semiconductor device is substantially devoid of an oxide layer between the channel and the substrate.