Patent ID: 9362895
Filing Date: 2016-06-07
CPC Classification: G01R,H02M,H03K

Claim Text:
1. A hybrid envelope detector and full-wave rectifier, comprising: a first P-channel Field Effect Transistor (PFET), having a source connected to a power supply voltage, having a gate, and having a drain connected to the gate; a second PFET, having a source connected to the power supply voltage, having a gate connected to the gate of the first PFET, and having a drain; a first N-channel Field Effect Transistor (NFET), having a source, having a gate for receiving a first input voltage, and having a drain connected to the drain of the first PFET; a second NFET, having a source connected to the source of the first NFET, having a gate for receiving a second input voltage, and having a drain connected to the drain of the first NFET; a third NFET, having a source connected to the source of the first NFET, having a gate at which a voltage V a fourth NFET, having a source connected to a ground potential, having a gate for receiving a first bias voltage, and having a drain connected to the source of the first NFET; a fifth NFET, having a source connected to the gate of the third NFET, having a gate connected to the drain of the second PFET, and having a drain connected to the power supply voltage; a controller, having an output bus; a variable transistor, having an input for receiving a second bias voltage, having an input bus connected to the output bus of the controller, and having a drain input connected to the gate of the third NFET; and a variable capacitor, having an input bus connected to the output bus of the controller, and having an output terminal connected to the gate of the third NFET.