Patent ID: 9368206
Filing Date: 2016-06-14
CPC Classification: G11C

Claim Text:
1. A capacitive circuit, comprising: a) a boundary cell having a resistive storage element that comprises a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; b) a plurality of resistive switching memory cells that form a functioning memory array, wherein the boundary cell is outside of the functioning memory array; c) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and d) a first capacitor comprising the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.