Patent ID: 9298055
Filing Date: 2016-03-29
CPC Classification: G02F,G09G

Claim Text:
1. An array substrate comprising: a plurality of gate signal lines extending in parallel at equal intervals; a plurality of source signal lines orthogonal to said plurality of gate signal lines and extending in parallel at equal intervals; a plurality of gate-driver mounting terminals connected to said plurality of gate signal lines via gate lead wires; a plurality of source-driver mounting terminals connected to said plurality of source signal lines via source lead wires; a plurality of gate-side array inspection terminals connected to said plurality of gate signal lines; a plurality of source-side array inspection terminals connected to said plurality of source signal lines; a common terminal for a gate lead wire disconnection inspection; a common terminal for a source lead wire disconnection inspection; a plurality of gate lead wire disconnection inspection circuits connected between said plurality of gate-driver mounting terminals and said common terminal for a gate lead wire disconnection inspection; and a plurality of source lead wire disconnection inspection circuits connected between said plurality of source-driver mounting terminals and said common terminal for a source lead wire disconnection inspection.