Patent ID: 9281246
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a gate stack over a semiconductor substrate; forming a gate spacer on a sidewall of the gate stack; implanting the semiconductor substrate to form a lightly doped drain/source region adjacent to the gate stack; after the gate spacer is formed and after the lightly doped drain/source region is formed, forming a source/drain region adjacent to the gate spacer; after the forming the source/drain region, etching the gate spacer to reduce a thickness of the gate spacer; forming an additional gate stack over the semiconductor substrate; forming an additional gate spacer on a sidewall of the additional gate stack; after the step of forming the additional gate spacer, etching the additional gate spacer to reduce a thickness of the additional gate spacer, wherein the etching the gate spacer and the etching the additional gate spacer are performed simultaneously, and wherein a remaining thickness of the gate spacer is different from a remaining thickness of the additional gate spacer; and forming a strained layer, wherein the strained layer comprises a portion on an outer sidewall of the gate spacer, and a portion over the gate stack.