Patent ID: 9312016
Filing Date: 2016-04-12
CPC Classification: G11C,H01L

Claim Text:
1. A read method executed by a multi-level cell memory device which is connected with a memory controller, the method comprising: receiving a first read command; reading, in response to receiving the first read command, first and second hard decision data by performing first and second hard decision read operations using a first hard decision read voltage and a second hard decision read voltage, respectively, the second hard decision read voltage being different from the first hard decision read voltage; selecting one of the first and second hard decision read voltages as a selected hard decision read voltage; reading first soft decision data by performing a first soft decision read operation using a plurality of soft decision read voltages corresponding to the selected hard decision read voltage and having respective voltage levels which are different from each other and the voltage level of the selected hard decision read voltage; providing the first soft decision data to the memory controller for first error correction code (ECC) decoding; reading, in response to receiving from the memory controller a signal indicating a failure of the first ECC decoding on the first soft decision data, second soft decision data by performing a second soft decision read operation using a plurality of soft decision read voltages corresponding to the non-selected one of the first and second hard decision read voltages and having respective voltage levels which are different from each other and the voltage level of the non-selected one of the first and second hard decision read voltages; and providing the second soft decision data to the memory controller for second ECC decoding.