Patent ID: 9385124
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method of forming a CMOS integrated circuit product comprised of a first transistor of a first type and a second transistor of a second type formed on a substrate, wherein said second type is opposite to said first type, the method comprising: forming a first gate structure for said first transistor and a second gate structure for said second transistor; forming a first spacer proximate both said first and second gate structures; forming an initial second spacer proximate said first spacer of said first transistor and a layer of second spacer material above said second transistor, said initial second spacer having an initial thickness; performing a first timed, wet etching process on both said first transistor and said second transistor so as to completely remove said layer of second spacer material from said second transistor and thereby expose said first spacer of said second transistor while leaving a first reduced thickness second spacer positioned adjacent said first spacer of said first transistor, wherein said first reduced thickness second spacer has a thickness that is less than said initial thickness of said initial second spacer; and forming a third spacer for said second transistor on and in contact with said first spacer of said second transistor.