Patent ID: 9432000
Filing Date: 2016-08-30
CPC Classification: G11C,H03F,H03G,H03K,H03M,H04B

Claim Text:
1. A buffer circuit comprising: a first input node to receive a first input signal; a second input node to receive a second input signal; a first connection node; a first supply node; a first transistor coupled to the first input node, the first supply node, and the first connection node; a second transistor coupled to the second input node and the first connection node; and a first bias circuit coupled to the second transistor; wherein the second input signal is a complement of the first input signal, wherein the first transistor, the second transistor and the first bias circuit have a respective plurality of design attributes, and wherein at least one of the respective plurality of design attributes is established to achieve a gain equal to a first target gain, the gain being defined by an output amplitude of a first output signal at the first connection node divided by an input amplitude of the first input signal, and wherein the first target gain is one.