Patent ID: 9275721
Filing Date: 2016-03-01
CPC Classification: G11C

Claim Text:
1. A memory array, comprising: memory bit cells being arranged in rows and columns with a common layout pitch height, the memory bit cells being divided into a plurality of sub-arrays, each column of each sub-array of memory bit cells being divided into a plurality of sections; a plurality of split bit lines coupled to a single column of memory bit cells, each split bit line of the plurality of split bit lines being coupled to a single section of memory bit cells, each section in the single column of memory bit cells being coupled to a single split bit line; and a sense amplifier coupled to the plurality of split bit lines and having more than two inputs for each of the plurality of sub-arrays, each input electrically connected to a section of memory bit cells by a split bit line of the plurality of split bit lines, the sense amplifier further comprising a first side logical gate comparator for comparing a plurality of split bit lines from a first sub-array of memory bit cells, and a second side logical gate comparator for comparing a plurality of slit bit lines from a second sub-array of memory bit cells, and a combination circuit for combining outputs of the first and second side logical gate comparators to form a global bit line signal on a global bit line, the combination circuit comprising a first transistor having a gate coupled to the output of the first side logical gate comparator and a second transistor having a gate coupled to the output of the second side logical gate comparator, drains of the first and second transistors being coupled together and to the global bit line, and sources of the first and second transistors being coupled together and to a VSS voltage supply.