Patent ID: 9455233
Filing Date: 2016-09-27
CPC Classification: G06F,H01L

Claim Text:
1. In a multi-layer integrated circuit (IC), a tamper detection system for protecting one or more circuits of the IC, the tamper detection system comprising: a first, static wire mesh formed in a first layer overlying the one or more circuits to provide static protection to the one or more circuits, wherein the static wire mesh comprises first wires connected to a power supply and second wires connected to ground; a second, active wire mesh comprising at least a third wire formed in a second layer overlying the one or more circuits to provide active protection to the one or more circuits; and a tamper detection module connected to the first and second wire meshes for detecting breaks in said meshes, wherein a first terminal of the third wire of the second mesh is connected to a first output terminal of the tamper detection module for receiving a first serial bit stream therefrom, and a second terminal of the third wire is connected to a first input terminal of the tamper detection module for providing the first serial bit stream back to the tamper detection module, wherein the tamper detection module actives a tamper detection signal when a break in one of the first and second wire meshes is detected.