Patent ID: 9460793
Filing Date: 2016-10-04
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells, a plurality of word lines and a plurality of bit lines; a page buffer block including N number of sub page buffer blocks, the sub page buffer blocks arranged in a bit line direction and each of the sub page buffer blocks include a plurality of page buffers arranged in a word line direction and a bit line direction; common internal data lines respectively corresponding to the sub page buffer blocks; and a page buffer decoder including page buffer selection units, the page buffer selection units electrically coupled between the page buffers, respectively, included in each sub page buffer block, and a common internal data line corresponding to the sub page buffer block, and the page buffer selection units configured to selectively electrically couple the page buffers, respectively, included in the sub page buffer block, to the common internal data line in response to bit line address signals.