Patent ID: 9343171
Filing Date: 2016-05-17
CPC Classification: G11C

Claim Text:
1. A method for operating a memory device, comprising: in response to a programming command involving a set of memory cells arranged in a plurality of NAND strings and connected to a plurality of word lines, programming memory cells of the set of memory cells which are connected to one or more word lines among the plurality of word lines, wherein the programming occurs according to a word line programming order of the plurality of word lines in which programming occurs first for memory cells connected to a particular word line of the plurality of word lines, and each memory cell of the set of memory cells comprises a gate and a channel; and in response to an erase command, after the programming, performing a plurality of erase-verify loops of an erase operation for the set of memory cells, wherein each erase-verify loop of the plurality of erase-verify loops comprises an erase portion in which a positive channel-to-gate voltage is provided for each memory cell in the set of memory cells followed by a verify test in which a first verify voltage is applied to the particular word line and, concurrently, a second verify voltage, higher than the first verify voltage is applied to remaining word lines of the plurality of word lines while sensing currents in the plurality of NAND strings, wherein the erase operation is completed when the verify tests indicates a completion criterion is met.