Patent ID: 9508745
Filing Date: 2016-11-29
CPC Classification: H01L

Claim Text:
1. A method of fabricating an array substrate, comprising the following steps of: providing a transparent substrate having a first portion and a second portion neighboring each other, and a first surface and a second surface facing each other; forming a buffer layer on the first surface of the transparent substrate, wherein the buffer layer is located on the first portion and the second portion; forming a first gate pattern and a second gate pattern on the buffer layer, wherein the first gate pattern and the second gate pattern are formed respectively on the first portion and the second portion; providing a transparent insulating layer covering the first gate pattern, the second gate pattern and the buffer layer; forming a first polysilicon pattern and a second polysilicon pattern on the transparent insulating layer, wherein the first polysilicon pattern has a first region and a second region adjacent to the first region, and the second polysilicon pattern has a third region and a fourth region adjacent to the third region; providing a photoresist layer covering the first polysilicon pattern, the second polysilicon pattern and the transparent insulating layer; providing an exposure light source in a direction from the second surface toward the first surface of the transparent substrate by using the first gate pattern and the second gate pattern as a light shielding layer, such that the photoresist layer forms a first photoresist pattern on the first region of the first polysilicon pattern and a second photoresist pattern on the third region of the second polysilicon pattern; and performing a first doping step to the first polysilicon pattern and the second polysilicon pattern in a direction from the first surface toward the second surface of the transparent substrate, such that the second region forms a first lightly doped polysilicon region and the fourth region forms a second lightly doped polysilicon region.