Patent ID: 9229830
Filing Date: 2016-01-05
CPC Classification: G06F

Claim Text:
1. A microcontroller comprising: a CPU; a command memory coupled to the CPU and configured to store commands to be processed by the CPU; a data memory configured to store data to be processed by the CPU; a peripheral circuit which incorporates a peripheral circuit register, which is configured to perform predetermined processing by the writing of the CPU to the peripheral circuit register, and which is configured to store processing results in the peripheral circuit register, data of the peripheral circuit register being capable of being read by the CPU; and a data access control circuit coupled between the CPU and the data memory and between the CPU and the peripheral circuit and configured to perform access control from the CPU to the data memory or to the peripheral circuit register, wherein the command memory is caused to store two threads, wherein the CPU executes the two threads to thereby perform duplexing processing, wherein a first address indicates a storage region of the data memory and the peripheral circuit register, wherein the data access control circuit generates an individual access from the CPU to the data memory or to the peripheral circuit register, by execution processing of the two threads, respectively, wherein the data access control circuit generates a shared access based on the execution processing of the two threads, from the CPU to the data memory or to the peripheral circuit register, and wherein the data access control circuit determines two types of the individual access and the shared access by the first addresses output from the CPU based on the execution processing of the two threads, respectively, and the duplexing processing to detect a failure of the CPU is performed by making a comparison between the commands and the first addresses, respectively, in the shared access based on the result of the execution processing of the two threads.