Patent ID: 9385002
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming an interlayer dielectric layer on a substrate; forming a storage node contact passing through the interlayer dielectric layer; forming a mold layer on the interlayer dielectric layer and the storage node contact; forming a mask pattern on the mold layer, the mask pattern comprising a hole exposing the mold layer; forming a noble metal pattern in the hole on the mold layer; and forming a storage node hole, laterally overlapping with the storage node contact, in the mold layer by etching the mold layer, wherein the noble metal pattern moves to directly on the storage node contact during the etching, wherein the etching the mold layer comprises etching the mold layer using the noble metal pattern as a catalyst, and wherein forming the noble metal pattern in the hole comprises: