Patent ID: 9401799
Filing Date: 2016-07-26
CPC Classification: H03K,H03L,H04L

Claim Text:
1. A synchronization method to synchronize a circuit with a synchronization signal, comprising: operating the circuit, said circuit exhibiting a time spread delay associated with a process, voltage, temperature (PVT) variation; applying a digital delay to the synchronization signal, the digital delay formed as an amount time up to said time spread delay; detecting a time offset between a signal output from said circuit and a timing signal; generating said digital delay with at least one set of cascaded delay elements, each cascaded delay element of the at least one set of cascaded delay elements having a respective delay value; and controlling said digital delay by selecting one or more of the cascaded delay elements included in said at least one set of cascaded delay elements, wherein controlling said digital delay includes selecting the at least one of the cascaded delay elements as a function of said detected time offset.