Patent ID: 9466531
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, comprising: forming a stack of N sets, each set of the N sets comprising an insulating material and a conductive material, N being an even number equal to or greater than 8, a topmost set of the N sets being defined as an Nth set, each of the N sets including a first region and a second region, the first regions of the N sets being vertically aligned with one another, the second regions of the N sets being vertically aligned with one another; removing the second region of the Nth set to expose the second region of an (N-1)th set; removing insulating material and conductive material from an upper portion of the N sets to produce a first intermediate structure in which steps in the first region of the N sets are formed respectively by (N-i)th sets, and steps in the second region of the N sets are formed respectively by (N-j)th sets, i being an even number inclusive of 0, j being an odd number; forming and patterning a chop mask over the first intermediate structure to cover respective first portions of the steps in the first and second regions of the N sets while leaving respective second portions of the steps in the first and second regions of the N sets uncovered; and removing insulating material and conductive material from the respective second portions of the steps in the first and second regions of the N sets of the first intermediate structure to form steps in a lower portion of the N sets.