Patent ID: 9418724
Filing Date: 2016-08-16
CPC Classification: G11C

Claim Text:
1. A memory system comprising: a memory including a first cell array including a plurality of first memory cells connected to a plurality of word lines, and a second cell array including a plurality of second memory cells connected to the plurality of word lines and a plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected, and wherein the memory is configured to generate an alert signal when the number of activations of the corresponding word line is equal to or greater than a reference number; and a memory controller configured to apply an excessive address and at least one adjacent address having a value adjacent to the excessive address, to the memory in a special refresh mode, wherein the excessive address corresponds to a word line of which the number of activation is equal or greater than the reference number.