Patent ID: 9268573
Filing Date: 2016-02-23
CPC Classification: G06F

Claim Text:
1. A method of encoding a program for a target processor, comprising: receiving and storing a program having a plurality of program instructions; generating a plurality of possible instruction encodings for each of the program instructions, wherein at least some of the possible instruction encodings for each program instruction have different lengths; fetching one of the possible instruction encodings into a fixed size decoder; converting, by the decoder, the instruction encoding into at least one execution operation; analyzing how many program cycles are required to dispatch the at least one execution operation from the decoder into an execution unit; identifying at least one execution operation dispatched during each program cycle; simulating the execution of the at least one execution operation dispatched during each program cycle, including delaying dispatch of at least one execution operation when a dispatch stall condition is simulated; repeating the steps of fetching, converting, analyzing, identifying and simulating with each possible instruction encoding until the number of program cycles required to dispatch the at least one execution operation corresponding to the instruction encoding is minimized; and selecting, for each program instruction, the instruction encoding that minimizes the number of program cycles used in the decoder.