Patent ID: 9347986
Filing Date: 2016-05-24
CPC Classification: G01R

Claim Text:
1. A device for monitoring a latency of electronic circuits based on microtechnology, nanotechnology, or both, the device comprising: electronic circuits to be tested being supplied with a power supply voltage, having a low level and a high level, for a detection of delay faults of said electronic circuits, a degradation device of type I placed between the high level of the power supply voltage and one or more elements of an electronic circuit among the electronic circuits to be tested, a degradation device of type II placed between the low level of the power supply voltage and one or more elements of said electronic circuit to be tested, the device of type I and the device of type II each comprising at least one low-latency electrical path, said low-latency electrical path being connected in parallel with a high-latency electrical path, said low-latency path causing a low latency operation of the electronic circuit when the power supply voltage is not degraded, and said high-latency path causing a high-latency operation of the electronic circuit when the power supply voltage is degraded, and the low-latency electrical paths being conductive when receiving a test signal while the high-latency electrical paths are always conductive.