Patent ID: 9509870
Filing Date: 2016-11-29
CPC Classification: H04N

Claim Text:
1. An apparatus having one or more processors executing instructions in one or more memories, wherein the instructions causing the one or more processors to function comprise: an acquisition unit configured to acquire at least one image group including at least one image; a creating unit configured to create a plurality of layout candidates, by selecting at least one image from an image group acquired by the acquisition unit, and arranging the at least one selected image; an evaluation unit configured to evaluate the layout candidates created by the creating unit; a deciding unit configured to decide a presentation order of layout candidates by selecting the layout candidates from the plurality of layout candidates, based on evaluation results from the evaluation unit and a predetermined rule different from evaluation, the predetermined rule being a rule for selecting a layout candidate based on evaluation results from the evaluation unit; and a presenting unit configured to present the selected layout candidates in the presentation order decided by the deciding unit; wherein the deciding unit decides the presentation order so that the presentation order is different from an evaluation order based on evaluation results from the evaluation unit, based on evaluation results of the evaluation unit.