Patent ID: 9240462
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A field-effect transistor with local source-drain insulation, having a semiconductor substrate; a source depression and a drain depression, which are formed in a manner spaced apart from one another in the semiconductor substrate; a depression insulation layer, having a depression bottom insulation layer which is formed at least across an entire bottom region of the source depression and of the drain depression; an electrically conductive filling layer, which is formed for realizing source and drain regions and for filling the source and drain depressions at a surface of the depression insulation layer; a gate dielectric, which is formed directly on a substrate surface between the source and drain depressions; and a gate layer, which is formed at a surface of the gate dielectric, wherein the depression insulation layer further has a depression sidewall insulation layer, which is formed in a sidewall region of the source and drain depressions but does not touch the gate dielectric, and wherein the depression sidewall insulation layer overlaps both a portion of the gate dielectric and a portion of the gate layer, overlaps with a spacer at a sidewall of the gate layer such that the conductive filling layer is free from overlap with said spacer, and extends to an isolation trench formed in the semiconductor substrate, the isolation trench having a bottom surface that is at the same depth as a bottom surface of the depression sidewall insulation layer or below a bottom surface of the depression sidewall insulation layer.