Patent ID: 9400656
Filing Date: 2016-07-26
CPC Classification: G06F

Claim Text:
1. A method for chaining data in an exposed-pipeline processing element, the method comprising: separating a multiple instruction word into a first sub-instruction and a second sub-instruction; receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element; issuing the first sub-instruction at a first time; issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction; performing, by a first pipeline, the first sub-instruction at a first clock cycle; communicating, by the first pipeline, the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline, the first pipeline and second pipeline being located in separate register file spaces; receiving, by the second pipeline, the second sub-instruction at the second clock cycle; and performing, by the second pipeline, the second sub-instruction at the second clock cycle, the performing based on receiving the first result via the chaining bus.