Patent ID: 9490027
Filing Date: 2016-11-08
CPC Classification: G11C,H01L

Claim Text:
1. An anti-fuse type one-time programmable (OTP) memory cell array including a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, the anti-fuse type OTP memory cell array comprising: a plurality of well regions respectively disposed in the plurality of rows, wherein each of the well regions is shared by the unit cells in the same row; a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the plurality of well regions; a plurality of source/drain regions respectively disposed in portions of the well regions between the plurality of anti-fuse gates; and a plurality of drain regions respectively disposed in the well regions located at one side of a last anti-fuse gate disposed in a last column, which is opposite to a first anti-fuse gate disposed in a first column, wherein each of the unit cells includes one anti-fuse transistor having a metal-oxide-semiconductor (MOS) transistor structure without a selection transistor.