Patent ID: 9299406
Filing Date: 2016-03-29
CPC Classification: G11C

Claim Text:
1. An apparatus, comprising: a control logic configured to provide a control signal indicative of a standby mode, wherein the control logic includes a logic configured to receive a first signal indicative of the standby mode and further receive a second signal indicative of activation of a memory section, the logic further configured to provide a logic output signal based at least in part on the first and second signals; a driver circuit coupled to the control logic and having an input and an output, wherein the driver circuit is configured to provide an output signal to a source of a transistor of a word line driver having a first voltage responsive to an input signal provided to the input; and a standby voltage circuit coupled to the output of the driver circuit and coupled to the control logic, wherein the standby voltage circuit is configured to increase a voltage of the output of the driver circuit to a second voltage during the standby mode and in an inactive state for the memory section responsive at least in part on the control signal indicating the standby mode, wherein the second voltage is non-zero and less than the first voltage.