Patent ID: 9490130
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a three-dimensional semiconductor memory device, comprising: forming a thin layer structure by alternately forming first and second material layers one on another on a substrate comprising semiconductor material; forming an opening through the thin layer structure and forming an indentation, contiguous with the opening, in a top surface of the semiconductor material of the substrate; forming an oxide layer between the thin layer structure and the substrate by oxidizing a surface of the semiconductor material of the substrate delimiting a side of the indentation such that a rounded boundary exists between the oxide layer and the substrate directly beneath the thin layer structure; forming a vertical insulation layer extending through the thin layer structure within the opening and into the indentation so as to extend over a surface defining a side of the indentation; and forming a semiconductor pattern on the vertical insulation layer in the opening and extending into the indentation of the substrate and beyond the vertical insulation layer.