Patent ID: 9263448
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a peripheral region in a semiconductor substrate, the peripheral region including a first region, a second region, and a third region; first active regions formed in the first region and the second region, the first active regions defined by recesses provided in device isolation films of the first region and the second region; a second active region defined by the device isolation film and provided in the third region; a buried metal layer buried in one or more of the recesses; a first conductive layer of a first type formed over a first portion of the first active regions and a first portion of the buried metal layer in the first region; and a second conductive layer of a second type formed over a second portion of the first active regions and a second portion of the buried metal layer in the second region, wherein the first type is different from the second type, wherein one of the first conductive layer and the second conductive layer is further formed over the second active region in the third region, and wherein a top surface of the buried metal layer is substantially coplanar with top surfaces of the first active regions.