Patent ID: 9379104
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A method comprising: forming plural fins on a substrate, with a shallow trench isolation (STI) region between adjacent fins; forming at least one dummy gate stack over and perpendicular to the fins, each gate stack including a dummy gate over a dummy gate insulating layer; forming sidewall spacers on opposite sides of each dummy gate stack; forming source/drain regions at opposite sides of each dummy gate stack; forming an interlayer dielectric (ILD) over the STI regions between fins; removing the dummy gate stacks forming gate cavities; forming a gate dielectric in each gate cavity; removing the gate dielectric from a gate cavity in a protection diode area, exposing an underlying fin, wherein a protection diode is formed in the protection diode area; implanting a dopant into the exposed fin; forming a replacement metal gate (RMG) in each gate cavity; forming a metal 1 layer over the ILD; and forming a second protection diode after forming the metal 1 layer.