Patent ID: 9331110
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate having a pixel region and a peripheral circuit region; a gate electrode formed on the substrate with a gate insulating layer being between the gate electrode and the substrate; two or more insulating layers that provide a silicide block, formed in the pixel region and the peripheral circuit region of the substrate so as to cover the gate electrode; a sidewall formed from at least a portion of the two or more insulating layers in the peripheral circuit region; a photodiode region formed from a first impurity region and a second impurity region in the pixel region and a third impurity region formed in the peripheral circuit region before the two or more insulating layers are formed; and a silicide layer formed on a surface of the third impurity region of the substrate, wherein the two or more insulating layers includes a silicon nitride layer and a silicon oxide layer, and wherein a region in which the second impurity region is formed is reduced in response to a degree of deterioration in pixel characteristic to be caused by a formation process in forming the second impurity region.