Patent ID: 9305914
Filing Date: 2016-04-05
CPC Classification: H01L,H02H

Claim Text:
1. An ESD protection circuit comprising: a trigger component; and a protection transistor with a gate electrode, wherein the trigger component is connected to the gate electrode and switches on the protection transistor when an overvoltage occurs, and wherein the protection transistor comprises: a substrate made of semiconductor material with an upper side; doped wells on the upper side, that comprise a first well of a first conductivity type provided for a drift section and a second well, of a second conductivity type opposite to the first conductivity type, provided for a channel region; a first contact area for a drain terminal in the first well; a second contact area for a source terminal in the second well; a gate dielectric on a region of the second well between the first contact area and the second contact area; and a gate electrode on the gate dielectric, wherein the substrate is not doped or is doped for the first conductivity type, wherein the protection transistor is a high-voltage transistor, wherein underneath the first contact area, a part of the second well is present between the first well and the semiconductor material of the substrate that is not doped or doped for the first conductivity type, wherein the second well is formed with a depth, measured from the upper side of the substrate into the substrate, that is smaller under the first contact area than under the second contact area, and wherein underneath the first contact area, the depth of the second well is less than twice the depth of the first well, to permit a dissipation of electric current from the first well to the substrate.