Patent ID: 9252098
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A semiconductor apparatus comprising: a multilayer interposer substrate having a connection terminal surface on one side and a chip mounting surface on another side, the interposer substrate including a power layer as an inner layer; a plurality of connection terminals provided on the connection terminal surface; and a semiconductor chip mounted on the chip mounting surface, wherein the plurality of connection terminals include power terminals, ground terminals, and signal terminals, wherein the power terminals are connected to a power pattern on the power layer and the semiconductor chip via power through holes, wherein the ground terminals are connected to the semiconductor chip via ground through holes, wherein the signal terminals are connected to the semiconductor chip via signal through holes, wherein the power, ground, and signal through holes go through the interposer substrate from the connection terminal surface to the chip mounting surface, wherein the ground and signal through holes are not formed in the power pattern on the power layer, and wherein the power pattern defines an area that surrounds only the power through holes.