Patent ID: 9230648
Filing Date: 2016-01-05
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a memory cell comprising: wherein a gate of the first transistor is electrically connected to a word line, wherein one of a source and a drain of the first transistor is electrically connected to a data line, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to an output signal line, wherein a gate of the third transistor is electrically connected to the data line, wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the fourth transistor, wherein a gate of the fifth transistor is electrically connected to the data line, wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor, and wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the fifth transistor.