Patent ID: 9385739
Filing Date: 2016-07-05
CPC Classification: H03M

Claim Text:
1. A circuit for converting between an analog input voltage and a corresponding digital representation of the analog input voltage, the circuit comprising: first, second and third capacitors, the first and second capacitors being matched, a first logic circuit coupled to one end of the first capacitor, a first switch coupled between another end of the first capacitor and one end of the second capacitor, a second switch coupled between the one end of the second capacitor and one end of the third capacitor, a discharge circuit coupled between the one end of the third capacitor and an opposite end of the second capacitor, such that when the second switch is closed the discharge circuit fully discharges the second capacitor onto the third capacitor, and a clock having a pulsating 2 phase output, the clock output controlling application of the analog input voltage to the first and second capacitors, wherein the logic circuit is coupled to the clock output to cause charge on the second capacitor to divide equally between the first and second capacitors when the analog input voltage is not greater than the reference voltage.