Patent ID: 9490845
Filing Date: 2016-11-08
CPC Classification: H03M,H04L

Claim Text:
1. A computing device, comprising: one or more processors configured to: receive information that identifies a design threshold associated with a low-density parity-check (LDPC) code; the permutation matrix including a group of rows, each row, of the group of rows, corresponding to a check node element of a group of check node elements associated with the LDPC code, the permutation matrix including a group of columns, each column, of the group of columns, corresponding to a variable node element of a group of variable node elements associated with the LDPC code, and the permutation matrix including a set of values, each value, of the set of values, corresponding to a particular check node element, of the group of check node elements, and a particular variable node element of the group of variable node elements, and each value, of the set of values, identifying a connection between the particular check node element and the particular variable node element; the parallelization factor being computed based on the set of values included in the permutation matrix; where the one or more processors, when computing the parallelization factor, are configured to: determine a group of column differences associated with the permutation matrix, each column difference, of the group of column differences, corresponding to a column of the group of columns, and being equal to a smallest difference between any two values included in the column; and identify the parallelization factor based on the group of column differences, the parallelization factor being equal to a smallest value included in the group of column differences.