Patent ID: 9312335
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method for fabricating a lateral bipolar transistor, comprising: providing a semiconductor substrate of a first conductivity type; forming a first buried layer of the first conductivity type and a second buried layer of a second conductivity type in the substrate, the second conductivity type being opposite the first conductivity type, the first buried layer being located under a trench isolation structure and the second buried layer being located under a base region; forming an epitaxial layer of the second conductivity type on the substrate; forming a dielectric layer over the epitaxial layer; forming first and second trenches in the dielectric layer and the epitaxial layer; forming first and second diffusion regions of the first conductivity type in the epitaxial layer surrounding only the sidewalls of respective first and second trenches; forming a lining oxide layer and a first polysilicon layer in a lower portion of each trench, the lining oxide layer and the first polysilicon layer filling only a portion of each trench, the first polysilicon layer being insulated from the sidewalls and trench bottoms of the trenches and being insulated from the respective first and second diffusion regions by the lining oxide layer; forming a second polysilicon layer at an upper portion of each trench, the second polysilicon layer being heavily doped with the first conductivity type and the second polysilicon layer of each trench being in electrical and physical contact with the respective diffusion region surrounding sidewalls of the respective trench and with the first polysilicon layer; and wherein forming the second polysilicon layer further comprises forming an extended portion of the second polysilicon layer of the first trench over the dielectric layer the extended portion of the second polysilicon layer being formed over the dielectric layer and extending beyond the first diffusion region formed surrounding the first trench and overlying at least a portion of the base region, the extended portion of the second polysilicon layer of the first trench formed over the dielectric layer functioning as a field plate for the base region to shield the base region from electrostatic build-up in the dielectric layer overlying the base region, wherein an emitter region is formed in the first and second polysilicon layers in the first trench and the first diffusion region, a collector region is formed in the first and second polysilicon layers in the second trench and the second diffusion region, the base region being formed in the epitaxial layer between the first and second diffusion regions associated with the first and second trenches.