Patent ID: 9348759
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. A computer system comprising: at least one processor; a memory coupled to the at least one processor, the memory having a plurality of real pages that have a corresponding plurality of real page numbers; a direct memory access (DMA) address translation table in the memory that includes a plurality of entries, each entry comprising: a pointer to one of the plurality of real page numbers; and a consecutive count field that defines a number of subsequent translation table entries that point to real page numbers sequential and subsequent to the one real page number; and a DMA address translation mechanism that adds an entry to the DMA address translation table and writes a value of zero to the consecutive count field for the entry when a subsequent entry immediately following the entry does not point to a next sequential real page number, and writes a value greater than zero to the consecutive count field for the entry when the subsequent entry points to the next sequential real page number.