Patent ID: 9530473
Filing Date: 2016-12-27
CPC Classification: G11C

Claim Text:
1. An apparatus, comprising: a command circuit configured to provide a command signal in an internal clock time domain based at least in part on a memory access command received in an external clock time domain; a command path delay configured to delay the command signal; a strobe generator circuit configured to receive the delayed command signal and a strobe signal, wherein a plurality of clock edges of the strobe signal correspond to received data associated with the memory access command, the strobe generator circuit configured to control input circuitry to capture the data associated with the memory access command based at least in part on the strobe signal and the delayed command signal, wherein the strobe generator circuit comprises logic configured to generate a pulse beginning at a clock edge of the strobe signal corresponding to a first bit of the data and ending at a clock edge of the strobe signal corresponding to a last bit of the data.