Patent ID: 9330922
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A stack gate structure for use in a non-volatile memory array comprising: a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction; a plurality of stack gate structures, each stack gate structure over an active region, with a first insulating material between each stack gate structure in a second direction perpendicular to the first direction; each stack gate structure comprising: a second insulating material over the active region; a charge holding gate over the second insulating material; a third insulating material over the charge holding gate; a first portion of a control gate over the third insulating material; a second portion of the control gate over the top surface of the first portion of the control gate and over the top surface of the first insulating material adjacent thereto extending in the second direction; and a fourth insulating material over the second portion of the control gate; wherein said first portion of the control gate is polysilicon and has a top surface that is substantially co-planar with the top surface of the first insulating material adjacent thereto; and a plurality of isolation regions in the semiconductor substrate, with each isolation region between a pair of the active regions, wherein each isolation region comprises: