Patent ID: 9313425
Filing Date: 2016-04-12
CPC Classification: H04N

Claim Text:
1. An image pickup device comprising: an image capturing unit that includes a plurality of pixels arrayed in a matrix form and each outputting a first pixel signal according to a reset level and a second pixel signal according to a signal level; a reference signal generation unit that generates a reference signal increasing or decreasing over time; a comparison unit that is disposed for each column or each plurality of columns, compares analog signals to the reference signal, and ends the comparison process at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signals; a clock generation unit that includes a delay circuit including a plurality of delay units connected to each other and outputs low-order phase signals configured with output signals of the plurality of delay units; a latch unit that is disposed for each column or each plurality of columns and retains the low-order phase signal as a latch signal at a timing related to the end of the comparison process; a count unit that is disposed for each column or each plurality of columns, counts a signal related to one of the low-order phase signals, and generates a high-order digital signal; a detection unit that is disposed for each column or each plurality of columns, and generates a low-order digital signal by sequentially comparing logic states of a plurality of bits of the latch signal retained by the corresponding latch unit and encoding the latch signal based on a comparison result of the logic states; and an arithmetic unit that is disposed for each column or each plurality of columns and performs an arithmetic process based on the high-order digital signal of the corresponding count unit and the low-order digital signal of the corresponding detection unit, and wherein the analog signals are the first and second pixel signals, the count unit generates a first high-order digital signal according to the first pixel signal and generates a second high-order digital signal according to the second pixel signal, the detection unit generates a first low-order digital signal according to the first pixel signal and generates a second low-order digital signal according to the second pixel signal, and the arithmetic unit performs subtraction between first digital data related to the first high-order digital signal and the first low-order digital signal and second digital data related to the second high-order digital signal and the second low-order digital signal.