Patent ID: 9455861
Filing Date: 2016-09-27
CPC Classification: G06F,H03M,H04B,H04L,H05K

Claim Text:
1. A system for generating check-to-variable messages during an iteration in decoding of codes represented by a parity check matrix, the system comprising: a de-mapper configured to receive a modulation signal comprising symbols, and convert the modulation signal into coded bit log-likelihood ratios; and at least one decoder coupled to the de-mapper, wherein the at least one decoder is configured to receive the coded bit log-likelihood ratios from the de-mapper and iteratively perform message passing decoding for a set of variable nodes identified in the check parity matrix so as to generate a decoded signal comprising bits, and wherein for at least one variable node in the set of variable nodes during the iteration, the at least one decoder is further configured to: a. calculate a check-to-variable message M b. identify two smallest absolute values, Min c. calculate a scaling factor where β is a non-negative number such that 0≦β≦1, d. scale the check-to-variable message M e. update check node i and variable node j with said scaled check-to-variable message M f. output the generated decoded signal.