Patent ID: 9401727
Filing Date: 2016-07-26
CPC Classification: G11C,H03K,H03M

Claim Text:
1. A time-interleaved, bootstrapped sample and hold apparatus comprising an input terminal and four output terminals, comprising: first, second, third, and fourth sample and hold circuits, each connected to the input terminal and a different output terminal, and mutually exclusively operative to sample a voltage at the input terminal in response to respective first, second, third, and fourth sample clock signals, each asserted for one different half-period of every two successive periods of a master clock signal; a first shared circuit operative to charge a first capacitance during one half-period of each period of a master clock signal; and a second shared circuit operative to charge a second capacitance during the other half-period of each period of a master clock signal; wherein the first and third sample and hold circuits are connected to the first shared circuit, and wherein the first capacitance is connected between the input terminal and a gate terminal of a sampling transistor in, alternately, one of the first and third sample and hold circuits, in response to the respective first and third sample clock signal, during half-periods of the master clock in which the first shared circuits is not charging the first capacitance; and wherein the second and fourth sample and hold circuits are connected to the second shared circuit, and wherein the second capacitance is connected between the input terminal and a gate terminal of a sampling transistor in, alternately, one of the second and fourth sample and hold circuits, in response to the respective second and fourth sample clock signals, during half-periods of the master clock in which the second shared circuit is not charging the second capacitance.