Patent ID: 9484353
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method for fabricating a memory device, comprising: providing a multilayers stack having a plurality of insulating layers and a plurality of sacrificing layers alternatively stacked with each other; forming at least one first through opening passing through the multilayers stack to partially expose the insulating layers and the sacrificing layers; performing a pull-back etching process to remove portions of the sacrificing layers through the first through opening, whereby a plurality of first recesses are defined by the remaining sacrificing layers and the insulating layers; partially oxidizing the remaining sacrificing layers to form an insulation layer in each of the first recess; forming a plurality of floating gate electrodes to respectively fill the first recess; forming a tunneling oxide layer to cover portions of the insulating layer and the floating gate electrodes exposed from the first through opening; forming a channel layer on the tunneling oxide layer; forming at least one second through opening passing through the multilayers stacks to partially expose the insulating layers and the remaining sacrificing layers; removing the remaining sacrificing layers to expose portions of the isolation layers, whereby a plurality of second recesses are defined by the insulating layers and the isolation layers; and forming a plurality of control gates to respectively fill in the second recesses.