Patent ID: 9520362
Filing Date: 2016-12-13
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate; a first interconnect layer disposed over the substrate; a second interconnect layer disposed over the first interconnect layer, wherein: the second interconnect layer includes a plurality of dielectric segments, a plurality of metal line components interleaving with the dielectric segments, and a plurality of dielectric barrier elements disposed between the dielectric segments and the metal line components; a plurality of vias disposed underneath a first subset of the metal line components; a plurality of dielectric components interleaving with the plurality of vias, wherein the dielectric components are disposed underneath a second subset of the metal line components different from the first subset, and wherein the plurality of vias and the plurality of dielectric components are disposed over the first interconnect layer; and an etch-stop layer disposed above the first interconnect layer but below the plurality of vias and the plurality of dielectric components.