Patent ID: 9501129
Filing Date: 2016-11-22
CPC Classification: G06F,Y02D

Claim Text:
1. A processor comprising: a variable frequency domain including a plurality of cores and a first portion of system agent circuitry separate from the plurality of cores, the first system agent circuitry portion including at least one cache memory, at least one cache controller, a memory coherency agent, an interrupt routing controller and an interconnect structure; and at least one fixed frequency domain including a power control unit (PCU), a first agent to communicate with one or more off-chip devices, a second agent to communicate off-chip via one or more links and a memory agent, wherein the PCU is to synchronize clock gating a plurality of clocks of the variable frequency domain and maintain alignment with one or more global clocks and thereafter cause a frequency change to the variable frequency domain without draining the first system agent circuitry portion of pending transactions from a plurality of sources including one or more of the plurality of cores, the first agent and the memory agent.