Patent ID: 9502484
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A thin film transistor (TFT) substrate comprising: a substrate comprising a first region, on which no TFT is disposed, and a second region; a TFT disposed on the second region of the substrate, the TFT including a semiconductor layer, a gate electrode, a source electrode electrically connected to the semiconductor layer through a first contact hole in an insulating layer covering the gate electrode, and a drain electrode electrically connected to the semiconductor layer through a second contact hole in the insulating layer, a remaining part of the source electrode outside the first contact hole and a remaining part of the drain electrode outside the second contact hole directly contacting an upper surface of the insulating layer; and a filling layer directly contacting at least one of a side surface of the source electrode and a side surface of the drain electrode, the side surface of the source electrode and the side surface of the drain electrode being above the insulating layer, wherein the filling layer does not cover either of a top surface of the source electrode and a top surface of the drain electrode, and wherein the filling layer does not directly contact the gate electrode, wherein a maximum height of the filling layer from a top surface of the substrate on the first region of the substrate is less than a maximum height of the filling layer from the top surface of the substrate on the second region of the substrate.