Patent ID: 9348345
Filing Date: 2016-05-24
CPC Classification: G05F,H02M

Claim Text:
1. A DC to DC converter control circuit, comprising: an analog carrier waveform generator circuit providing a periodic carrier signal waveform according to a clock input signal; a comparison circuit, including a first input receiving the periodic carrier signal waveform, a second input receiving an output error control signal, and an output providing a pulse output signal including a plurality of pulses individually corresponding to clock pulses of the clock input signal and having corresponding pulse widths varying at least partially according to the periodic carrier signal waveform and the output error control signal; a driver circuit providing at least one switching control signal to operate a corresponding switching device to selectively convert power from a DC input to provide DC output power to a load at least partially according to the pulse output signal from the comparison circuit; an error amplifier, including a first input receiving a feedback voltage signal representing an output voltage provided to the load, a second input receiving a reference voltage signal representing a desired output voltage, and an output providing the output error control signal to the comparison circuit representing an output voltage error at least partially according to the feedback voltage signal and the reference voltage signal; and an asynchronous pulse injection circuit operative to cause the comparison circuit to asynchronously inject at least one pulse into the pulse output signal in response to detection of an output load current transient condition indicating an unregulated drop in the output voltage, the asynchronous pulse injection circuit comprising: wherein the comparison circuit comprises a second output providing a PWM reset pulse output signal complementary to the pulse output signal, and wherein the reset circuit flip-flop comprises a set input receiving the binary comparator voltage output signal, a reset input receiving the PWM reset pulse output signal from the second output of the comparison circuit, and an output at least partially generating the output signal of the reset circuit to cause the comparison circuit to asynchronously inject the at least one pulse into the pulse output signal.