Patent ID: 9530365
Filing Date: 2016-12-27
CPC Classification: G02F,G09G

Claim Text:
1. A gate driving circuit comprising an integrated circuit driving module and a driving control module; wherein the driving control module comprises one or more first strobe units, one or more second strobe units, one or more gate connecting lines in a first layer, one or more gate connecting lines in a second layer, one or more first gate lines and one or more second gate lines; wherein the first strobe unit comprises a P-type Metal Oxide Semiconductor (PMOS) transistor and an N-type Metal Oxide Semiconductor (NMOS) transistor, a first control signal is applied to gates of the PMOS transistor and the NMOS transistor, and a gate connecting line in the first layer is connected to a drain of the NMOS transistor and a source of the PMOS transistor in the first strobe unit, the source of the NMOS transistor is directly connected to one end of one of the one or more first gate lines, the drain of the PMOS transistor is directly connected to one end of one of the one or more second gate lines; the second strobe unit comprises a PMOS transistor and a NMOS transistor, wherein a second control signal is applied to gates of the PMOS transistor and the NMOS transistor, a gate connecting line in the second layer is connected to a drain of the NMOS transistor and a source of the PMOS transistor in the second strobe unit, the source of the NMOS transistor is directly connected to the other end of one of the one or more first gate lines, the drain of the PMOS transistor is directly connected to the other end of one of the one or more second gate lines; the integrated circuit driving module generates gate driving signals and transmits the gate driving signals to the driving control module; wherein the gate connecting line in the first layer and the gate connecting line in the second layer are located in different layers of a Fan-out area on a display substrate, for connecting the gate driving signal and the gate line; the first gate line and the second gate line are two adjacent gate lines located in each gate line group in a valid display area, the number of the gate connecting line in the first layer, the number of the gate connecting line in the second layer and the number of the gate lines are the same.