Patent ID: 9374216
Filing Date: 2016-06-21
CPC Classification: H03K,H03L,H04L

Claim Text:
1. A method for generating a clock signal, comprising: receiving one or more signals from a multi-wire communication interface, wherein a sequence of symbols is encoded in the one or more signals; determining a first transition in the one or more signals, wherein the first transition comprises a rising edge; generating a first clock pulse on the clock signal responsive to the first transition and after a preconfigured first interval provided by delaying the first clock pulse using a first delay circuit; determining a second transition in the one or more signals, wherein the second transition comprises a falling edge; and generating a second clock pulse on the clock signal responsive to the second transition and after a preconfigured second interval provided by delaying the second clock pulse using a second delay circuit, wherein the preconfigured first interval and the preconfigured second interval have different durations.