Patent ID: 9288082
Filing Date: 2016-03-15
CPC Classification: H04L

Claim Text:
1. A circuit comprising: a first differential amplifier configured to generate a first difference signal between signals received on a first pair of selected inputs representing symbols of a vector signaling code word of an orthogonal vector signaling code received via a multi-wire communications bus, and a second differential amplifier configured to generate a second difference signal between signals received on a second pair of selected inputs representing symbols of the vector signaling code word of the orthogonal vector signaling code received via the multi-wire communications bus, the first pair of selected inputs and the second pair of selected inputs being disjoint; a summation circuit comprising load impedance elements connected to the first differential amplifier and the second differential amplifier, the summation circuit configured to generate a sum-of-differences output signal by combining the first difference signal and the second difference signal; and an output circuit for generating, based on the sum-of-differences output signal, a portion of a respective code identification result signal that fully identifies the received code word of the orthogonal vector signaling code.