Patent ID: 9368431
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A semiconductor apparatus having a configuration in which a plurality of metal wiring layers and a plurality of insulating layers are alternately layered, wherein the semiconductor apparatus comprises: a first wiring pattern formed in a first metal wiring layer, including a plurality of metal wiring members which are formed in parallel with predetermined intervals, and each of which has a rectangular shape extending in a first direction; and a second wiring pattern formed in a second metal wiring layer adjacent to the first metal wiring layer, including a plurality of metal wiring members which are formed in parallel with predetermined intervals, and each of which has a rectangular shape extending in a second direction orthogonal to the first direction, and wherein the region occupied by the first metal wiring pattern and the region occupied by the second metal wiring pattern at least overlap, and wherein the first wiring pattern and the second wiring pattern are electrically connected to each other so as to have the same electric potential.