Patent ID: 9524785
Filing Date: 2016-12-20
CPC Classification: G11C

Claim Text:
1. A memory unit, comprising: a first voltage passing device configured to output voltages according to operations of the memory unit, the first voltage passing device comprising a first passing gate transistor having a first terminal configured to receive an inhibit signal, a second terminal, and a control terminal configured to receive a passing gate control signal; and a first memory cell comprising: wherein: the first capacitance element and the first voltage passing device are disposed in a first N-well; the first terminal of the first capacitance element receives a first voltage outputted from the first voltage passing device during a program operation or an erase operation of the first memory cell and receives a second voltage outputted from the first voltage passing device during an inhibit operation of the first memory cell; the first voltage is greater than the second voltage; during the program operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from a fourth voltage to a third voltage, the inhibit signal is at the first voltage, the passing gate control signal is at a fifth voltage, and the first terminal of the first passing gate transistor receives the first voltage; during a program inhibit operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from the fourth voltage to the third voltage, the inhibit signal is at the second voltage, the passing gate control signal is at the fifth voltage, and the first terminal of the first passing gate transistor receives the second voltage; and the third voltage is smaller than the fourth voltage, the fourth voltage is smaller than the fifth voltage, and the fifth voltage is smaller than the second voltage.