Patent ID: 9292283
Filing Date: 2016-03-22
CPC Classification: G06F

Claim Text:
1. A method in an integrated circuit, the integrated circuit having a plurality of registers for storing operands, the method comprising: receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits; performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, wherein fewer load and store operations from the plurality of registers are required after the reorganizing; (iv) for each of the plurality of columns, adding all sub-elements within the respective one of the plurality of columns, the added sub-elements collectively identified as T2, and (v) yielding a final 512-bit squared result of the 512-bit value by adding the value of T2 twice with the value of T1 once; and wherein the (iv) adding all sub-elements within their respective columns, further includes: (a) adding a first of the four diagonals each of 7×1 sub-elements of the 64-bits in length in which one operand is loaded once and does not switch, (b) adding a second and a third of the four diagonals each of 7×1 sub-elements of the 64-bits in length in which only one operand is switched after an initial load, and (c) adding a fourth of the four diagonals each of 7×1 sub-elements of the 64-bits in length in which a plurality of operand switches occur after an initial load.