Patent ID: 9520986
Filing Date: 2016-12-13
CPC Classification: G06F,H03L,H04L

Claim Text:
1. An apparatus for converting a data interface format to enable data exchange between devices operating at different clock rates, the apparatus comprising: a clock up-converter configured to derive an up-converted clock signal from a first clock signal at a first clock rate of a first device and to transmit the up-converted clock signal to a second device, the up-converted clock signal having a phase controlled with respect to a phase of an associated first data signal; a clock down-converter configured to derive a down-converted clock signal from a second clock signal at a second clock rate of the second device and to transmit the down-converted clock signal to the first device, the down-converted clock signal having a phase controlled with respect to a phase of an associated second data signal, the second clock rate being different from the first clock rate; and a controller configured to align the up-converted and down-converted clock signals with the associated first and second data signals at startup of the first and second devices by causing the devices to transmit alignment patterns and adjust phases of the derived up-converted and down-converted clock signals as a function of the alignment patterns.