Patent ID: 9406721
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A memory device comprising: a plurality of bit lines, including first and second bit lines, extending in a first direction away from a substrate; a plurality of word lines, including first and second word lines, extending in a second direction crossing the first direction and substantially parallel to a surface of the substrate; an insulating material between the first and second word lines; a first layer made of a Group IV element, between the first word line and the insulating material and between the first word line and the first bit line; and a second layer made of a compound of a Group V element and a Group VI element, between the insulating material and the first bit line, wherein the first word line includes a first portion that is metallic and a second portion between the first portion and the first layer, and a variable resistance portion in contact with the first and second layers and the second portion of the first word line, contains the Group IV element and the compound of the Group V element and the Group VI element.