Patent ID: 9495102
Filing Date: 2016-11-15
CPC Classification: G06F

Claim Text:
1. An input/output (I/O) interceptor logic section, comprising: an I/O interface communicatively coupled with a storage stack and configured to intercept a plurality of write I/Os and a plurality of flush requests from an application; one or more temporary write holding buffers configured to receive the plurality of write I/Os from the I/O interface and to store the plurality of write I/Os; a re-order logic section communicatively coupled to the one or more temporary write holding buffers and configured to change an order of the plurality of write I/Os stored in the one or more temporary write holding buffers, and to combine the re-ordered plurality of write I/Os into a combined write I/O; and an intelligent flush control logic section configured to receive the plurality of flush requests from the I/O interface, to communicate write I/O completion of the plurality of write I/Os to the application without the plurality of write I/Os having been written to a non-volatile storage device, and to cause the combined write I/O to be written to the non-volatile storage device responsive to a predefined Nth flush request from among the plurality flush requests.