Patent ID: 9337107
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method for forming a semiconductor device, comprising: providing a substrate; forming a dielectric layer on the substrate, the dielectric layer having therein six openings including a first opening, a second opening, a third opening, a fourth opening, a fifth opening, and a sixth opening; forming a gate dielectric layer on sidewalls and a bottom surface of each opening of the six openings; forming a cap layer on the gate dielectric layer; forming a first work function layer on the cap layer in the first opening and in the second opening; forming a diffusion layer on the first work function layer in the first opening, and on the cap layer in both of the fifth opening and the six opening; performing an annealing process to diffuse a material of the diffusion layer into the first work function layer and the cap layer, to form a doped work function layer in the first opening and form a doped cap layer in the fifth opening and in the sixth opening; removing a remaining portion of the diffusion layer after the annealing process, and forming a second work function layer on the cap layer in the fourth opening and on the doped cap layer in the fifth opening, such that transistors respectively formed with the first opening, the second opening, and the third opening have threshold voltages different from each other, and transistors respectively formed with the fourth opening, the fifth opening, and the sixth opening have threshold voltages different from each other; and after forming the second work function layer, forming a third work function layer in the each opening; and forming a metal gate on the third work function layer.