Patent ID: 9257159
Filing Date: 2016-02-09
CPC Classification: G11C

Claim Text:
1. A memory device, comprising: at least one memory bank; interface circuitry to receive memory read requests from an external source and to responsively supply read data from the at least one memory bank to the external source, and to receive memory write requests and associated write data from the external source, wherein each memory read request is to specify a read request row corresponding to row address of memory cells in the at least one memory bank and a column address of memory cells within a row corresponding to the row address, and each memory write request is to specify a write row corresponding to a row address of memory cells in the at least one memory bank and a column address of memory cells within the write row, and wherein each memory read request and each memory write request is to be accompanied by bits that according to their states are to determine a variable amount of data to be exchanged with the external source; and logic responsive to the memory read requests and the memory write requests to, in dependence on state of the bits provided with each request, exchange the variable amount of data with the external source; wherein the bits are first bits and wherein the memory write requests are selectively accompanied by write mask bits, such that the memory device is to selectively perform a masked write according to write mask bits accompanying a given memory write request, and such that the memory device is to selectively write a subset of a column of memory, independent from any write mask bits accompanying the given memory write request, in dependence on respective states of the first bits accompanying the given memory write request.