Patent ID: 9235252
Filing Date: 2016-01-12
CPC Classification: G06F,Y02D

Claim Text:
1. A processor comprising: a plurality of domains including a core domain having at least one core to execute instructions; a power cost table to store a plurality of entries, each entry associating a leakage power level, a first dynamic power level and a second dynamic power level with one of the plurality of domains for a given frequency of operation; and a power controller to control power consumption of the processor, the power controller including a first logic to receive an indication of a priority domain of the plurality of domains and to dynamically allocate power to the plurality of domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication, wherein the first logic is to determine a power demand for a first operating level of the core domain based on a first number of cores at a peak demand level corresponding to the first dynamic power level, a second number of cores at an active demand level corresponding to the second dynamic power level, and a third number of cores at a leakage demand level corresponding to the leakage power level.