Patent ID: 9293380
Filing Date: 2016-03-22
CPC Classification: G01R,H01L

Claim Text:
1. A test system for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process, comprising: structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions; and derating factor selection circuitry coupled to said structural at-speed ATE and configured to employ results of said structural at-speed tests to identify performance deterioration in said samples, said performance deterioration indicating said derating factor to be employed in a subsequent wafer fabrication process, wherein said derating factor is applied to a ratio of high-voltage threshold (HVT) transistors to standard-voltage threshold (SVT) transistors.