Patent ID: 9495929
Filing Date: 2016-11-15
CPC Classification: G09G,G11C

Claim Text:
1. A shift register, comprising an initial stage, a first intermediate stage, a second intermediate stage, and a final stage, wherein: each of the first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor; the second intermediate stage includes a control circuit which is (i) connected to the setting circuit and (ii) supplied with a control signal; an operation period (i) starts at a time when a shift start signal supplied to the initial stage is activated and (ii) ends at a time when an output of the final stage changes from activation to inactivation; when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive; the first intermediate stage includes an adjustment circuit that is connected to the setting circuit; and the adjustment circuit includes an adjustment transistor with a control terminal that is supplied with a constant electric potential signal.