Patent ID: 9230854
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: depositing a dielectric layer over a substrate; depositing a hard mask layer over the dielectric layer; depositing a capping layer over the hard mask layer, wherein the capping layer has a selectivity relative to the dielectric layer of greater than about 1:5; applying a nitrogen free anti-reflection layer to the capping layer, wherein the nitrogen free-anti-reflection layer is a bottom anti-reflection coating; patterning the nitrogen free anti-reflection layer, the capping layer, and the hard mask layer into a first trench portion; patterning the capping layer and the hard mask layer into a second trench portion using a different process than the patterning the nitrogen free anti-reflection layer, the capping layer, and the hard mask layer into a first trench portion; patterning the dielectric layer into a first via portion through the first trench portion; patterning the dielectric layer into a second via portion through the second trench portion; and extending the first trench portion, the second trench portion, the first via portion, and the second via portion to form a first trench, a second trench, a first via, and a second via.