Patent ID: 9449897
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A chip package, comprising: a semiconductor substrate; a device region formed in the semiconductor substrate; at least one conducting pad disposed over a surface of the semiconductor substrate; a protection substrate disposed over the surface of the semiconductor substrate; a spacer layer disposed between the surface of the semiconductor substrate and the protection substrate, wherein the protection substrate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface; a dielectric layer disposed between the surface of the semiconductor substrate and the spacer layer, wherein the dielectric layer covers the device region and the spacer layer is disposed over the dielectric layer; and a portion of a sacrificial support layer disposed on the dielectric layer, wherein the portion of the sacrificial support layer is located between the spacer layer and a conducting pad of the at least one conducting pad which is closest to the spacer layer, and the portion of the sacrificial support layer is not in contact with the spacer layer.