Patent ID: 9431424
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method comprising: providing an insulator layer on an upper surface of a Si substrate and a Si layer on an upper surface of the insulator layer; forming shallow trench isolation (STI) regions at first through fourth sides of a rectangular active area of the Si layer, the first side opposing the third, wherein the STI regions extend vertically into the Si substrate; recessing the STI regions below the upper surface of the insulator layer; undercutting the active area of the Si layer, forming channels in the insulator layer along and under perimeter edges of the active area; conformally forming a high-k dielectric layer on all exposed surfaces; forming a metal layer on the high-k dielectric layer and filling the channels; removing the metal layer except for the filled channels and a portion over each of the STI regions at the first and third sides and overlapping the active area; and forming low-k spacers on exposed opposing sidewalls of the metal portions overlapping the active area, exposed vertical surfaces of the high-k dielectric layer on edges of the active area, and exposed surface of the filled channels.