Patent ID: 9438266
Filing Date: 2016-09-06
CPC Classification: H03M

Claim Text:
1. A calibrated-output analog-to-digital converter (“ADC”), comprising: a multi-level sigma-delta modulator including an N-level current-mode digital-to-analog converter (“I-DAC”) coupled to at least one output terminal of the modulator to provide a negative feedback loop in the modulator, the I-DAC implemented with (N−1)/2 switched current sources; mismatch measurement logic coupled between a modulator input terminal and the modulator output terminals to determine, from counts of occurrences of modulator output levels during (N−1)/2 mismatch measurement intervals, magnitudes of [(N−1)/2−1] mismatch errors (“δ a mismatch-correcting split decimator coupled to the modulator output terminals to apply a decimation filtering to output data from the sigma-delta modulator in order to generate an uncorrected ADC output data component, to multiply decimated counts of modulator output levels predetermined to be delta-influenced by a predetermined factor of at least one of δ