Patent ID: 9513334
Filing Date: 2016-12-06
CPC Classification: G01R

Claim Text:
1. A method for performing on-chip spatial debugging of a user circuit programmed into a user-programmable integrated circuit to be provided to a user, the method comprising: operating the integrated circuit in a system for which the user circuit was designed; halting during an Nth clock cycle an internal clock driving synchronous logic elements in the integrated circuit in response to an output state transition of a sequential logic element in the integrated circuit triggered by a clock transition occurring during the Nth clock cycle, the sequential logic element being arbitrarily selected from among all of the synchronous logic elements in the integrated circuit during performance of the on-chip spatial debugging of the user circuit; reading the states of at least some of synchronous logic elements programmed into the integrated circuit while the internal clock is halted; while the internal clock is halted, forcing an output of at least one synchronous logic element to an arbitrary desired state selected during performance of the on-chip spatial debugging of the user circuit; and restarting the internal clock.