Patent ID: 9379114
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate having a recess partially defined by a sidewall, the substrate having a top surface on which other device elements are formed; a device isolation layer provided in the recess, the device isolation layer having a top surface lower than an uppermost portion of the top surface of the substrate; a memory element disposed on the top surface of the substrate; one or more first contacts electrically connected to the memory element; and an isolation pattern provided overlying a corresponding device isolation region and arranged between adjacent ones of the first contacts, the isolation pattern being in direct physical contact with the adjacent ones of the first contacts, wherein at least one of the first contacts is in contact with the top surface of the substrate and is formed such that a portion of the first contact extends downwardly into the recess along the sidewall of the recess to increase a contact area between the first contact and the substrate.