Patent ID: 9257348
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method, comprising: performing at least one first etching process to remove a sacrificial gate structure for a transistor to thereby define a gate cavity defined by internal surfaces of spaced-apart sidewall spacers, said gate cavity having an opening having a first width; depositing at least one material layer in said gate cavity; forming a recessed sacrificial material layer in said gate cavity above said at least one material layer; performing at least one second etching process to remove said at least one material layer within said gate cavity above said recessed sacrificial material layer so as to thereby expose a portion of said internal surfaces of said spaced-apart sidewall spacers positioned above said recessed sacrificial material layer; performing a spacer trimming etch process on said exposed portions of said internal surfaces of said spaced-apart sidewall spacers to reduce a thickness of at least a portion of said sidewall spacers in the presence of said recessed sacrificial material layer and thereby increase a size of said opening to a second width that is greater than said first width; and removing said recessed sacrificial material layer from said gate cavity.