Patent ID: 9437277
Filing Date: 2016-09-06
CPC Classification: G06F,G11C,H03M,H04B

Claim Text:
1. An integrated circuit, comprising: enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state; clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the clock control circuitry is configured to provide the data rate clock as the filtered data rate clock while the clock enable is the first logic state; and a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data received by the enable circuitry.