Patent ID: 9356163
Filing Date: 2016-05-31
CPC Classification: G02B,H01L,Y02E,Y02P

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: providing a substrate comprising, from bottom to top, a handle substrate, a first insulator layer, a first semiconductor material layer, a second insulator layer, and a second semiconductor material layer; forming an opening that extends entirely through said second semiconductor material layer and entirely through said second insulator layer, and partially into said first semiconductor material layer; forming a third semiconductor material layer in said opening, said third semiconductor material layer having a bottommost surface that contacts a reduced thickness material portion of said first semiconductor material layer that is located under said opening; forming isolation structures in said semiconductor substrate to provide a waveguide device region, a photodetector device region and a logic device region, wherein during said forming said isolation structures, portions of said first semiconductor material layer, portions of said third semiconductor material layer and portions of said second semiconductor material layer are removed, and wherein said waveguide device regions comprises a first remaining portion of said first semiconductor material layer, said photodetector device region comprises a remaining portion of said third semiconductor material layer and said reduced thickness material portion of said first semiconductor material layer, and said logic device region comprises a remaining portion of said second semiconductor material layer, a remaining portion of said second insulator layer, and a second remaining portion of said first semiconductor material layer; and forming, in any order, a logic device on a surface of said remaining portion of said second semiconductor material layer in said logic device region, and a photodetector device in said third semiconductor material layer in said photodetector device region.