Patent ID: 9397639
Filing Date: 2016-07-19
CPC Classification: A61N,H03K

Claim Text:
1. Circuitry for generating a clock signal, comprising: a high reference voltage and a low reference voltage; toggle circuitry configured to produce the clock signal, wherein the toggle circuitry is configured to set the clock signal to a first logic state when a feedback voltage is lower than the low reference voltage, and wherein the toggle circuitry is configured to set the clock signal to a second logic state when the feedback voltage is higher than the high reference voltage; and an RC circuit configured to produce the feedback voltage, wherein the feedback voltage charges when the clock signal is in one of the first or second logic states, and discharges when the clock signal is in the other of the first or second logic states, wherein the high and low reference voltages are simultaneously adjustable symmetrically around a midpoint of a first power supply voltage to adjust a frequency of the clock signal.