Patent ID: 9298865
Filing Date: 2016-03-29
CPC Classification: G06F

Claim Text:
1. A method for simulating a design implemented in a semiconductor device, the method comprising: receiving first interconnect data, the first interconnect data indicating a first interconnect of a first logic design implemented within a circuit schematic, wherein the first interconnect is associated with a first combinational logic block; identifying, by a processor, a first node for the first combinational logic block, the first node having an output providing an input to the first combinational logic block; identifying, by the processor, a second node in a second logic design physically implemented in the semiconductor device, the second node having an output providing an input to a second combinational logic block, wherein the second combinational logic block physically implemented in the semiconductor device is a modified version of the first combinational logic block implemented within the circuit schematic, and the second node providing an input to the second combinational logic block corresponds to the first node providing an input to the first combinational logic block; configuring the semiconductor device such that the second logic design is modified to include a tap associated with the output of the second node; and simulating a signal associated with the first interconnect of the first logic design implemented within the circuit schematic based on data provided by the tap in the second logic design physically implemented in the semiconductor device.