Patent ID: 9318573
Filing Date: 2016-04-19
CPC Classification: B82Y,H01L

Claim Text:
1. A method of manufacturing a field effect transistor, the method comprising: forming an insulating layer and a first silicon layer on a silicon substrate; sequentially forming at least two alternating SiGe layers and second silicon layers on the first silicon layer after the forming an insulating layer and a first silicon layer; forming silicon oxide layers by oxidizing the first and second silicon layers and Si of the at least two SiGe layers on the silicon substrate, and forming at least two Ge nanorods from the at least two SiGe layers; forming a source electrode on one end of each of the at least two Ge nanorods, the one end of the at least two Ge nanorods being embedded in the source electrode; forming a drain electrode on another end of each of the at least two Ge nanorods, the one end of the at least two Ge nanorods being embedded in the drain electrode; forming a gate insulation layer that surrounds the at least two Ge nanorods in a region for forming a channel region between the source electrode and the drain electrode; and forming a gate electrode on the gate insulation layer.