Patent ID: 9379692
Filing Date: 2016-06-28
CPC Classification: H03K

Claim Text:
1. A comparator, comprising: a power input terminal fed to electricity power supply; a first to-be-compared voltage input terminal used to receive a first to-be-compared voltage; a second to-be-compared voltage input terminal used to receive a second to-be-compared voltage; an offset voltage adjusting circuit used to adjust an offset voltage; a comparative circuit used to receive the first to-be-compared voltage and the second to-be-compared voltage, to compare the first to-be-compared voltage and a third to-be-compared voltage which is a sum of the second to-be-compared voltage and the offset voltage, and to generate a comparative result; and a comparative result output terminal used to output the comparative result; wherein the comparative circuit is coupled with the power input terminal, the comparative result output terminal, the offset voltage adjusting circuit, the first to-be-compared voltage input terminal, and the second to-be-compared voltage input terminal; the comparative circuit comprises: wherein the first field effect transistor, the second field effect transistor, and the third field effect transistor are all P-channel metal-oxide-semiconductor field effect transistors; wherein the offset voltage adjusting circuit comprises: wherein the offset voltage adjusting circuit comprises: wherein the second adjusting portion comprises: