Patent ID: 9362407
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A finFET device comprising: a gate formed on top of a high-k dielectric layer, the high-k dielectric layer being disposed on a substrate; a first epitaxial layer disposed on the substrate, wherein a first spacer layer and a second spacer layer are positioned between the gate and the first epitaxial layer relative to a first side of the gate; and a second epitaxial layer disposed on the substrate; wherein the first spacer layer, the second spacer layer, and an intermediate spacer layer are positioned between the gate and the second epitaxial layer relative to a second side of the gate; wherein the intermediate spacer layer includes a dopant that diffuses into the second epitaxial layer during annealing; and wherein a width of the second epitaxial layer includes the dopant from the intermediate spacer layer, the width under the first spacer layer having been enlarged with the dopant from the intermediate spacer layer.