Patent ID: 9240492
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first oxide semiconductor layer over an insulating surface; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a source electrode and a drain electrode over and electrically connected to the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer; a first insulating layer over the third oxide semiconductor layer, the source electrode, and the drain electrode; and a first gate electrode over the first insulating layer, the first gate electrode overlapping with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer, wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer has a crystalline structure, wherein the third oxide semiconductor layer and a side surface of the second oxide semiconductor layer are in contact with each other, wherein the third oxide semiconductor layer and a side surface of the first oxide semiconductor layer are in contact with each other, wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises at least one of indium, zinc, and gallium, wherein a composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer are different from each other, and wherein a length of the third oxide semiconductor layer in a channel length direction is longer than a length of the first oxide semiconductor layer in the channel length direction.