Patent ID: 9236384
Filing Date: 2016-01-12
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device, comprising a memory transistor, a first control transistor and a second control transistor, wherein the first control transistor comprises a source electrode and a gate electrode coupled to a first bit line and a first word line, respectively, and a drain electrode, wherein the second control transistor comprises a drain electrode and a gate coupled to a second bit line and a second word line, respectively, and a source drain electrode, wherein the memory transistor comprises a gate electrode coupled to the drain electrode of the first control transistor, a drain electrode coupled to the source electrode of the second control transistor, and a source electrode coupled to ground, and wherein the memory transistor comprises an oxide heterojunction filed effect transistor and thus exhibits a gate electrode-controlled memory characteristic, wherein the oxide heterojunction field effect transistor comprises an oxide base layer on a semiconductor substrate, an oxide film being located on the oxide base layer and forming a heterojunction with the oxide base layer, and the oxide heterojunction filed effect transistor further comprises a gate electrode on the oxide film, and a source electrode and a drain electrode on opposite sides of the gate electrode and contacting a heterojunction interface.