Patent ID: 9473719
Filing Date: 2016-10-18
CPC Classification: H01L,H04N

Claim Text:
1. A method comprising: forming a plurality of photodiodes in a pixel-array region on a substrate; forming a plurality of transistor gate stacks in the pixel-array region and in a peripheral region; depositing a conformal protective layer over the photodiode and the plurality of transistor gate stacks; forming a photoresist layer over the conformal protective layer in the pixel-array region; etching the conformal protective layer in the peripheral region to form transistor gate spacers; removing the photoresist layer over the conformal protective layer; forming a patterned photoresist layer over the conformal protective layer to expose portions of the conformal protective layer over transistor source regions and drains regions in the pixel-array region; and forming transistor sources and drains in the pixel-array region by implanting through the conformal protective layer.