Patent ID: 9306730
Filing Date: 2016-04-05
CPC Classification: H03L,H04J,H04L

Claim Text:
1. An apparatus for clock and data recovery, comprising: a fractional-N phase-locked loop for receiving a reference signal, and for providing a proportional signal and an integral signal; a ring oscillator of the fractional-N phase-locked loop for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal; a data-to-frequency control word converter for receiving data input and the oscillation signal, and for providing a frequency control word; a fractional-N divider of the fractional-N phase-locked loop for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop; and the phase-frequency detector of the fractional-N phase-locked loop for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.