Patent ID: 9502348
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: providing a substrate having a first region and a second region; forming a first dielectric layer on a surface of the substrate; forming a second dielectric layer having a plurality of first openings exposing portion of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer in the second region and the first dielectric layer in the second region until the surface of the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer in the second region.