Patent ID: 9245766
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A semiconductor process for manufacturing particular patterns, comprising the steps of: sequentially forming a target layer and a plurality of evenly-spaced core bodies having uniform width on a substrate; conformally forming a spacer material layer on said target layer and said core bodies so that a plurality of recesses are formed between two adjacent said core bodies in said spacer material layer; forming a first photoresist on said spacer material layer, wherein said first photoresist covers a predetermined region encompassing at least two said core bodies and at least one said recess; performing a first etch process using said first photoresist as an etch mask to remove said spacer material layer outside the said predetermined region so that said core bodies outside said predetermined region are exposed; removing said exposed core bodies to expose underlying said target layer; forming a second photoresist on said spacer material layer in said predetermined region, wherein said second photoresist at least encompasses all of said recesses in said predetermined region; and performing a second etch process using remaining said spacer material layer and said second photoresist as an etch mask to pattern said target layer.