Patent ID: 9355692
Filing Date: 2016-05-31
CPC Classification: G11C

Claim Text:
1. A high frequency write through memory device comprising: a plurality of memory cells; a common signal path configured to receive an address signal, the address signal corresponding to the at least one of the plurality of memory cells of the write through memory device, wherein the common signal path includes a plurality of AND gates; a read data signal path which includes the common signal path and a first AND gate; a read enable signal path which includes the common signal path and a second AND gate; and a plurality of local evaluation circuits, wherein each of the plurality of local evaluation circuits is coupled to one of the plurality of memory cells; wherein each of the plurality of local evaluation circuits is configured to receive an output of the read data signal path and the read enable signal path and to responsively prevent the data stored in the coupled memory cell from being written to a latch node and to output an input data signal to the latch node during the write through operation based on the read enable signal being inactive and to responsively permit the data stored in the coupled memory cell to be written to the latch node during a read operation, which is indicated by the read signal being active and wherein the use of the common signal path by both the read data signal path and the read enable signal path minimizes a timing variation between the two paths.