Patent ID: 9489894
Filing Date: 2016-11-08
CPC Classification: G09G,H01L

Claim Text:
1. A pixel circuit comprising a driving transistor, a signal loading module, a light emitting control module and a storage capacitor, wherein a gate of the driving transistor is connected to a third terminal of the signal loading module and a second terminal of the storage capacitor; a first electrode of the driving transistor is connected to a second terminal of the signal loading module and a second terminal of the light emitting control module; a second electrode of the driving transistor is connected to a fourth terminal of the signal loading module and a third terminal of the light emitting control module; a first terminal of the storage capacitor is connected to a first terminal of the signal loading module and a first terminal of the light emitting control module; a fifth terminal of the signal loading module is configured to receive a data signal; both the first terminal of the light emitting control module and the first terminal of the signal loading module are configured to receive a first voltage signal; and a fourth terminal of the light emitting control module is configured to output a driving voltage signal; wherein the signal loading module comprises a first transistor, a second transistor and a third transistor; a gate of the first transistor is configured to receive a gate control signal for a present stage; a first electrode of the first transistor, as the third terminal of the signal loading module, is connected to the second terminal of the storage capacitor, the gate of the driving transistor and a second electrode of the second transistor; a second electrode of the first transistor, as the fourth terminal of the signal loading module, is connected to the second electrode of the driving transistor and the third terminal of the light emitting control module; a gate of the second transistor is configured to receive a gate control signal for a previous stage or a start signal; a first electrode of the second transistor is configured to receive the first voltage signal, and as the first terminal of the signal loading module, is connected to the first terminal of the storage capacitor and the first terminal of the light emitting control module; the second electrode of the second transistor, as the third terminal of the signal loading module, is connected to the first electrode of the first transistor, the second terminal of the storage capacitor and the gate of the driving transistor; a gate of the third transistor is configured to receive the gate control signal for the present stage; a first electrode of the third transistor is configured to receive a data signal; a second electrode of the third transistor, as the second terminal of the signal loading module, is connected to the first electrode of the driving transistor and the second terminal of the light emitting control module.