Patent ID: 9384084
Filing Date: 2016-07-05
CPC Classification: G06F

Claim Text:
1. An apparatus for verifying the completeness and compatibility of software components, the arrangement comprising: an electronic control unit (ECU) having memory comprising a memory circuit; a bootloader stored in the memory circuit; and a CompleteCompatible verification component stored in the memory, where the bootloader is arranged to, upon start-up of the ECU, verify the completeness and compatibility of the CompleteCompatible verification component; wherein, to verify the completeness and compatibility of the CompleteCompatible verification component, the bootloader is arranged to where the CompleteCompatible verification component is arranged to, upon performance thereof, check that a respective start and stop address as well as a version number for a further software component in the ECU is correct or calculate a checksum for the further software component and compare the calculated checksum with a reference value stored in associated memory in order to verify the completeness and compatibility of the further software component in the ECU before the further software component exercises control of the ECU; wherein the bootloader is arranged for verification of the CompleteCompatible verification component, and the CompleteCompatible verification component is arranged for verification of the further software component in the ECU without involvement of the bootloader in the verification of the further software component.