Patent ID: 9258107
Filing Date: 2016-02-09
CPC Classification: H04L

Claim Text:
1. A decision-directed phase lock loop for correcting phase error in a received signal, comprising: a first buffer configured to store a block of input symbols, the block of input symbols starting with a first pilot symbol and ending with a last pilot symbol; a phase rotator configured to apply a phase-noise compensation to the block of input symbols on a symbol-by-symbol basis; a feedback loop coupled to the phase rotator, the feedback loop providing a phase-noise compensation signal to the phase rotator; a first output buffer configured to store a first block of phase-noise-compensated symbols output from the phase-rotator, where the symbols in the first block of phase-noise-compensated symbols are sequentially received from the phase rotator starting with the first pilot symbol; a second output buffer configured to store a second block of phase-noise-compensated symbols output from the phase-rotator, where the symbols in the second block of phase-noise-compensated symbols are sequentially received from the phase rotator starting with the last pilot symbol; and a combiner configured to combine associated symbols from the first and second blocks of phase-noise-compensated symbols to create output symbols, wherein the associated symbols from the first and second blocks of phase-noise-compensated symbols are combined using a process selected from the group consisting of: weighted symbol-by-symbol combining using a Log-Likelihood Ratio (LLR) metric; and weighted symbol-by-symbol combining using a Minimum-Mean-Square Error (MMSE) error metric.