Patent ID: 9490262
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A method for fabricating a memory device, comprising: forming a stack comprising alternating control gate layers and dielectric layers, the control gate layers of the stack comprise a control gate layer for a first transistor above control gate layers for data memory cells; forming a memory hole in the stack, the memory hole having a sidewall; depositing a charge-trapping material, a tunneling material and a channel material along the sidewall, wherein the charge-trapping material is deposited before the tunneling material, and the tunneling material is deposited before the channel material; etching a slit in the stack; depositing a protective layer in the slit; etching down the protective layer to a height in the stack which is between the control gate layer for the first transistor and the control gate layers for the data memory cells, exposing a sacrificial material of the control gate layer for the first transistor to the slit and leaving a remaining portion of the protective layer which shields a sacrificial material of the control gate layers for the data memory cells from the slit; providing an etchant in the slit which etches away the sacrificial material of the control gate layer for the first transistor, creating a void in the control gate layer for the first transistor and exposing a portion of the charge-trapping material in the control gate layer for the first transistor; providing an etchant in the slit to etch away the portion of the charge-trapping material which is in the control gate layer for the first transistor; providing an etchant in the slit which etches away the remaining portion of the protective layer, exposing the sacrificial material of the control gate layers for the data memory cells to the slit; providing an etchant in the slit which etches away the sacrificial material of the control gate layers for the data memory cells, creating voids in the control gate layers for the data memory cells; depositing a metal in the slit, the metal fills the void in the control gate layer for the first transistor and the voids in the control gate layers for the data memory cells, wherein portions of the charge-trapping material in the control gate layers for the data memory cells remain in the memory device; and providing a blocking oxide layer between the charge-trapping material and the metal.