Patent ID: 9473088
Filing Date: 2016-10-18
CPC Classification: H03F,H03M

Claim Text:
1. A signal processing circuit, comprising: a chopper amplifier that generates a chopper output signal by amplifying differential input signals; and an adder circuit that generates an addition signal by addition of the chopper output signal, wherein the chopper amplifier includes: a modulation chopper circuit that has a first input node pair and a first output node pair; a differential amplifier circuit that has a second input node pair and a second output node pair; and a demodulation chopper circuit that has a third input node pair and a third output node pair, wherein in response to a control clock, the modulation chopper circuit interchanges the differential input signals applied to the first input node pair for the every first phase period of the control clock and second phase period of the control clock, and outputs modulation differential input signals from the first output node pair, wherein the differential amplifier circuit outputs modulation differential output signals from the second output node pair by amplifying the modulation differential input signals applied to the second input node pair, wherein in response to the control clock, the demodulation chopper circuit interchanges the modulation differential output signals applied to the third input node pair for the every first phase period and second phase period, and outputs the chopper output signal from the third output node pair, and wherein the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.