Patent ID: 9466716
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method for forming a semiconductor structure, the method comprising: forming a gate stack on a semiconductor substrate, the gate stack comprising a gate electrode formed over a gate dielectric layer; forming a pair of lightly doped source/drain (LDD) regions in the semiconductor substrate adjacent to and opposing the gate stack; after forming the pair of LDD regions, forming a first pair of gate spacers disposed on opposing sidewalls of the gate stack, the first pair of gate spacers at least partially covering the pair of LDD regions; forming a second pair of gate spacers on top surfaces of the pair of LDD regions and on the opposing sidewalls of the first pair of gate spacers; forming in the semiconductor substrate, a pair of first recesses adjacent the opposing sidewalls of the gate stack and spaced apart from the opposing sidewalls of the gate stack by a first distance; forming in the semiconductor substrate, a pair of second recesses adjacent the opposing sidewalls of the gate stack and spaced apart from the opposing sidewalls of the gate stack by a second distance less than the first distance; and after forming the pair of first recesses and the pair of second recesses, forming a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein forming the stressor comprises: