Patent ID: 9412760
Filing Date: 2016-08-09
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate including a base substrate, wherein the base substrate is divided into a pixel region and a peripheral circuit region, the pixel region comprises a gate electrode, a gate insulation layer, a semiconductor active layer, a pixel electrode, a source/drain electrode, a passivation layer and a common electrode sequentially located on the base substrate; the peripheral circuit region includes a first circuit line, the gate insulation layer, a second circuit line and the passivation layer sequentially located on the base substrate, an orthogonal projection area of the second circuit line on the base substrate is at least partly overlapped with orthogonal projection area of the first circuit line on the base substrate, and the second circuit line is directly electrically connected with the first circuit line through a via hole penetrating the gate insulation layer.