Patent ID: 9349632
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of forming a trench isolation structure in an integrated circuit comprising: forming a smaller isolation trench and a larger isolation trench in a semiconductor substrate, wherein said larger isolation trench has a greater width than said smaller isolation trench and the same depth as the smaller isolation trench; forming an oxide layer over said substrate and on all surfaces of said smaller and larger isolation trenches; forming a nitride layer over said oxide layer, said nitride layer completely filling said smaller isolation trench, but only lining said larger isolation trench; removing a portion of said nitride layer to form a recess in said nitride layer in said smaller isolation trench and to completely remove said nitride layer lining for said larger isolation trench; and forming a layer of high density plasma oxide over said substrate to fill said smaller and larger isolation trenches.