Patent ID: 9514975
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device comprising: etching a via into a silicon substrate from a first side toward a second side of the silicon substrate; forming an insulating material in the etched via; forming a seed material on the insulating material; blocking selected regions of the seed material located outside of the via with a photoresist; plating exposed regions of the seed material to fill the via with a conductive material, thereby forming a conductive interconnect in the etched via, the conductive interconnect having a first end proximate the first side of the silicon substrate and a second end proximate the second side of the silicon substrate; insulating the conductive interconnect with a dielectric material proximate the first side of the silicon substrate; and forming a metal routing structure on the dielectric material, the metal routing structure being at least partially in the dielectric material.