Patent ID: 9465640
Filing Date: 2016-10-11
CPC Classification: G06F

Claim Text:
1. An information processing apparatus comprising a processor that builds: a virtual machine including a driver that performs data input/output using an input/output device; and a hypervisor that manages the virtual machine and performs a synchronization process between the information processing apparatus and another information processing apparatus which form a pair, wherein the processor monitors an access made between a memory and the input/output device; notifies the hypervisor of detection of a reading access in a case where the reading access relating to data output from the memory to the input/output device is detected by the monitoring; and suppresses the data output from the memory to the input/output device, in a case where the hypervisor is during execution of the synchronization process when the hypervisor receives the notification, to prevent a synchronization state between the information processing apparatus and another information processing apparatus from being interrupted, wherein the information processing apparatus includes an interrupt factor flag configured to be set in a case where the processor generates an interrupt having detection of the reading access as a factor so as to cause the hypervisor to perform the synchronization process and to be cleared when the hypervisor ends the synchronization process, wherein the processor determines that the hypervisor is during execution of the synchronization process in a case where the interrupt factor flag is set and determines that the hypervisor is not during execution of the synchronization process in a case where the interrupt factor flap is not set.