Patent ID: 9230643
Filing Date: 2016-01-05
CPC Classification: G11C

Claim Text:
1. A system, comprising: a processor; and a non-volatile memory device coupled to the processor, the processor configured to transmit a memory read command to the non-volatile memory device, the non-volatile memory device comprising: an input/output interface configured to receive the memory read command from the processor, a phase change memory cell, a control circuit configured to control an application of a read or verify pulse to the phase change memory cell at least in part in response to the memory read command, wherein the read or verify pulse reaches a first voltage level for a first period of time, and a sensing circuit configured to detect a threshold event for the phase change memory cell during a sense window, wherein the sense window is a time period for which the sensing circuit is configured to detect the threshold event, wherein the sensing circuit is configured to open the sense window after the read or verify pulse reaches the first voltage level, wherein the control circuit is configured to maintain the read or verify pulse at or below the first voltage level while the sense window is open, and wherein the sensing circuit is configured to close the sense window after an expiration of the first period of time.