Patent ID: 9450050
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A semiconductor power device comprising: a semiconductor substrate comprising a super-junction structure including a plurality of alternating P-doped and N-doped layers extending laterally from a source column to a drain column wherein said source column and drain column extend downward in said semiconductor substrate through two opposite sides of said super-junction structure disposed in said semiconductor substrate; a gate column for applying a voltage thereon to control a current transmitted laterally through said super-junction structure between said source and said drain columns; wherein the semiconductor substrate is a P substrate and wherein the drain column is an N+ column to form a Zener diode at a junction of said drain column with said P substrate to function as a built-in avalanche clamp diode; source and drain graded N diffusion regions surrounding sidewalls of said source and drain columns respectively; and said gate column further comprises a trench P+ column connected to said P doped layers of said super-junction structure and disposed near said source column outside of an area between said source column and said drain column wherein said source column is segmented to have a gap area for said P+ gate column to apply a voltage to control a current transmitted through said super junction structure.