Patent ID: 9437587
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method of packaging a semiconductor device comprising: providing a die paddle having a first chip installation area and a second chip installation area; a notch; a recess area formed in the first chip installation area; and multiple metal pillars formed in the recess area; wherein the notch divides the first chip installation area into a transverse base portion extending transversely and a longitudinal base portion extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; providing a first pin; a second pin; and a third pin arranged near the first chip installation area; wherein the first pin includes a first external pin and a first pin soldering area connected to the first external pin, and the first pin soldering area includes a first transverse extending part and a first longitudinal extending part connected to the first transverse extending part; the second pin includes a second external pin and a second pin soldering area connected to the second external pin, and the second pin soldering area includes a second transverse extending part and a second longitudinal extending part connected to the second transverse extending part; the third pin includes a third external pin and a third pin soldering area connected to the third external pin; and wherein the second transverse extending part extends into a portion inside of the notch, the second longitudinal extending part is arranged along an edge of an interface between the notch and the second chip installation area, the first transverse extending part is arranged near the longitudinal base, and the first longitudinal extending part is adjacent to the second longitudinal extending part; and attaching a first semiconductor chip, being flipped, to the metal pillars and the second transverse extending part; wherein a first and a second electrodes disposed at a front side of the first semiconductor chip are attached to the second transverse extending part and the metal pillars respectively and a third electrode at a back side of the first semiconductor chip is connected by a first metal connecting piece to the first pin, the first metal connecting piece includes a first metal piece, a first connecting structure and a first soldering piece, wherein the first metal piece is attached to the third electrode of the first chip and the first soldering piece is attached to the first transverse extending part; attaching a second semiconductor chip to the first metal piece, piece; wherein a third electrode of the second semiconductor chip at a back side of the second semiconductor chip is attached on the first metal piece, a second electrode at a front side of the second semiconductor chip is connected through a second metal connecting piece to the third pin, the second metal connecting piece includes a second metal piece, a second connecting structure and a second soldering piece, the second metal piece is connected to the second electrode of the second semiconductor chip, the second soldering piece is connected to the third pin soldering area adjacent to the transverse base; and attaching a third semiconductor chip to the second chip installation area; wherein I/O pads arranged at a front side of the third semiconductor chip are, through bonding wires, respectively electrically connected to the first and the second longitudinal extending part, the second chip installation area, the second electrode and the first electrode of the second semiconductor chip at the back of the second semiconductor chip.