Patent ID: 9269709
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate of a first conductivity, wherein the substrate include a bulk semiconductor region; a first gate formed in a first trench in the bulk semiconductor region; a first drain/source region of the first conductivity; a second drain/source region of the first conductivity, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate in the bulk semiconductor region; a second gate formed in a second trench in the bulk semiconductor region; a third drain/source region of the first conductivity, wherein the third drain/source region and the second drain/source region are formed on opposing sides of the second gate in the bulk semiconductor region; and a channel region formed in the bulk semiconductor region, wherein the channel region extends from the first drain/source region to the second drain/source region and the channel region, the first drain/source region, the second drain/source region and the third drain/source region share a same polarity, and wherein the channel region, the first drain/source region, the second drain/source region and the third drain/source region form a junction-less transistor.