Patent ID: 9459960
Filing Date: 2016-10-04
CPC Classification: G06F,G11C,H04L

Claim Text:
1. A controller device to control the operation of an electrically erasable programmable memory chip, the controller device comprising: a transmitter circuit to transmit a read command and a first error detection code to the memory chip; a receiver circuit to receive read data and a second error detection code from the memory chip, the second error detection code encoded by the memory chip in connection with the read data; a circuit, coupled to the receiver, to detect an error in the received read data based on the second error detection code; and logic circuitry to signal an error condition in the event of the detected error, the controller device to re-receive the read data from the memory chip in the event that the logic circuitry signals the error condition; wherein the memory chip is to detect existence of error in the read command using the first error detection code; and wherein at least one of the first error code and the second error detection code is to be exchanged between the controller device and the memory chip using a link independent of a link used to receive the read data.