Patent ID: 9324707
Filing Date: 2016-04-26
CPC Classification: G03F,G06F,H01L

Claim Text:
1. An integrated circuit comprising: a transistor array comprising first gate lines disposed in a first region; first dummy gate lines disposed over a first isolation region adjoining the first region, each first dummy gate line disposed at a first distance to a next first dummy gate line; no first dummy gate line disposed in the first distance to a first peripheral gate line of the first gate lines and to a first peripheral dummy gate line of the first dummy gate lines; second dummy gate lines disposed over a second isolation region adjoining the first region, each second dummy gate line disposed at a second distance to a next second dummy gate line; and no second dummy gate line disposed in the second distance to a second peripheral gate line of the first gate lines and to a first peripheral dummy gate line of the second dummy gate lines.