Patent ID: 9472655
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method for producing a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate; (b) forming a gate insulating film and a control gate electrode in turn over a main surface of the semiconductor substrate; (c) forming a first insulating film including therein a charge holding portion over the semiconductor substrate to cover the control gate electrode; (d) forming a first sacrifice film in a side wall form over respective side walls of the control gate electrode on both sides of the control gate electrode to interpose a first insulating film between each of the side walls and the control gate electrode; (e) using, as a mask, a portion of the first sacrifice film that is adjacent to one of the side walls of the control gate electrode to implant impurity ions of a predetermined conductivity type into the main surface of the semiconductor substrate, thereby forming a first semiconductor region; (f) removing, after the step (e), the first sacrifice film; (g) forming a memory gate electrode at a position adjacent to one of the side walls of the control gate electrode, the side wall being the first-semiconductor-region-side side wall; (h) removing a portion of the first insulating film that is exposed from the memory gate electrode; (i) forming a second semiconductor region of the conductivity type over a region out of main surface regions of the semiconductor substrate that are adjacent to the control gate electrode, the region being a main surface region opposite to a memory-gate-electrode-positioned region of these main surface regions, and forming a third semiconductor region of the conductivity type over a main surface region of the semiconductor substrate, the region being between the memory gate electrode and the first semiconductor region; and (j) forming a fourth semiconductor region of the conductivity type over a main surface region of the semiconductor substrate, the main surface region being on a side of the control gate electrode and being opposite to the memory-gate-electrode-positioned region of the main surface; wherein the second and third semiconductor regions are smaller in impurity concentration than the first and fourth semiconductor regions; and wherein the first, second, third and fourth semiconductor regions, the control gate electrode, and the memory gate electrode are configured as a memory cell of a nonvolatile memory.