Patent ID: 9501608
Filing Date: 2016-11-22
CPC Classification: G01R,G06F

Claim Text:
1. A system, comprising a processor to: split a netlist or cross section of a circuit into sub-circuits; generate a timing model for each sub-circuit and build a timing graph by combining the timing models of the sub-circuits; determine a full set of dependencies based on each sub-circuit's dependent configuration parameters and configuration parameters that a load and inputs of the circuit are dependent on; generate a sample plan for each sub-circuit with dependencies based on the full set of dependencies; receive results from a simulation for each sub-circuit based on the sample plan for each sub-circuit; generate algebraic forms for an early delay, a late delay, and a slew by curve fitting the results from the simulation across the configuration parameters; determine a piecewise-linear minimum and a piecewise-linear maximum for each of the algebraic forms of arrival times from segments arriving at a common node in the timing graph and propagate the arrival times and slew in algebraic forms throughout the timing graph; and evaluate checks based on selected projections from the timing graph or over a complete set of configurations to determine a configuration with a worst slack.