Patent ID: 9443934
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor comprising a first region, a second region, and a third region provided between the first region and the second region; a source electrode over and in contact with a top surface of the first region; a drain electrode over and in contact with a top surface of the second region; a gate insulating film over the semiconductor; and a gate electrode facing the semiconductor with the gate insulating film therebetween, the gate electrode overlapping with the third region, wherein a length of the third region is shorter than a length of the first region and the second region, in a channel width direction, wherein the semiconductor has a depression, wherein a part of a bottom surface of the gate electrode and the depression are overlapped with each other, and wherein the part of the bottom surface of the gate electrode is positioned lower than the top surface of the first region and the top surface of the second region.