Patent ID: 9276005
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device, comprising: forming a memory cell on a substrate by: forming a first logic device on the substrate by: forming a second logic device on the substrate by: wherein the forming of the conductive word line gate, the forming of the conductive first logic gate, and the forming of the conductive second logic gate comprise forming a conductive metal material over the substrate; wherein the conductive second logic gate is insulated from the third channel region by a first insulation formed over the substrate and by a second insulation formed over the substrate; wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation; wherein the conductive erase gate is insulated from the first source region by the first insulation and by a third insulation, and not by the second insulation; wherein the conductive floating gate is insulated from the first portion of the first channel region by the first insulation and not by the second insulation and not by the third insulation; and wherein the conductive word line gate is insulated from the second portion of the first channel region by the first insulation and by the second insulation and not by the third insulation; and wherein the second insulation is a second layer of silicon dioxide and a layer of high K material.