Patent ID: 9515052
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a substrate having a first face and a second face opposite the first face, and having a recess formed in the first face; a first semiconductor chip disposed to a bottom of the recess; a second semiconductor chip disposed to the second face of the substrate; a third semiconductor chip disposed over the first face of the substrate and the first semiconductor chip; a fourth semiconductor chip disposed over the third semiconductor chip, wherein each of the first to fourth semiconductor chips comprises an active face and a back side opposite the active face, and the first to fourth semiconductor chips comprise first to fourth bonding pads arranged adjacently to an edge and another edge opposing the edge of each of the active faces, wherein the third semiconductor chip is disposed to the first face of the substrate through a plurality of flip chip bumps so that the active face of the third semiconductor chip faces the first face of the substrate and the back side of the first semiconductor chip, and wherein the fourth semiconductor chip is disposed over the back side of the third semiconductor chip so that the back side of the fourth semiconductor chip faces the back side of the third semiconductor chip, first to third bumps configured to electrically couple between the substrate and the first to third semiconductor chips; and a bonding wire configured to electrically couple the substrate and the fourth semiconductor chip.