Patent ID: 9502535
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method for integrating III-Nitride (III-N) transistors with different threshold voltages, comprising: patterning a III-N semiconductor structure to expose a gate region of a first transistor with a first threshold voltage VT selectively recessing the gate region of the first transistor by removing a first number of adjacent sublayers of the cap layer; patterning the III-N semiconductor structure to expose a gate region of a second transistor with a second threshold voltage V selectively recessing the gate region of the second transistor by removing a second number of adjacent sublayers of the cap layer, wherein the second number of adjacent sublayers is different from the first number of adjacent sublayers; forming gate electrodes for both the first and the second transistors; and forming ohmic contacts for both the first and the second transistors.