Patent ID: 9305129
Filing Date: 2016-04-05
CPC Classification: G06F

Claim Text:
1. A method of tuning an integrated circuit including a plurality of capacitive loads and a clock network, wherein the clock network includes a spine, one or more supporting ribs coupled to the spine, a plurality of base cells coupled to the ribs and one or more cross-links coupling pairs of the base cells that are on different ones of the ribs together, the method comprising: determining a collection of macrocells, wherein each of the macrocells is formed by one or more of the base cells and instantiated in the integrated circuit, wherein each of the macrocells have a drive strength determined by one or more base cells that form the macrocell, each of the base cells have an input pin and an output pin, and each of the macrocells are for driving one of the capacitive loads on the integrated circuit; representing each of the macrocells within a physical database as a group of the base cells that form the macrocell configured such that the group logically behaves as if the base cells were a single macrocell; choosing an input and an output of each of the macrocells by marking a location of an input pin of the input pins of the base cells of the macrocell and marking a location of an output pin of the output pins of the base cells of the macrocell and generating terminals at the marked locations; associating the terminals with the macrocells upon which the terminals are located in a table such that each macrocell is associated with a pair of the terminals that indicate the input and the output of the macrocell; and tuning the integrated circuit by adjusting the drive strength of one or more of the macrocells based on a size of the capacitive load that is driven by the macrocell in order to balance a parameter of the clock network, wherein the parameter is measured from one or both of the terminals of the macrocell.