Patent ID: 9361974
Filing Date: 2016-06-07
CPC Classification: G11C

Claim Text:
1. A method of operating a memory device comprising a plurality of memory cells arranged on regions where a plurality of first signal lines and a plurality of second signal lines cross each other, the method comprising: determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among the plurality of first signal lines; dividing a memory cell array comprising the plurality of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to the unselected second signal lines included in the n blocks, wherein each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.