Patent ID: 9384010
Filing Date: 2016-07-05
CPC Classification: G06F,Y02D

Claim Text:
1. A system comprising: a memory controller to perform memory control functions; a graphics processor coupled to the memory controller, the graphics processor to perform graphics processing; and a plurality of processor cores coupled to the memory controller, the plurality of processor cores including a first core and a second core to execute a program at different performance levels and different power levels; wherein the first core and the second core have different micro-architectures, including different pipeline depths, and wherein an instruction set of the first core and an instruction set of the second core are based on a single instruction set including single instruction multiple data (SIMD) instructions; and wherein the first core and the second core are integrated on a single die, and wherein the first core is to provide a first performance level when executing the program at a first power level and at a first frequency and the second core is to provide a second performance level higher than the first performance level when executing the program at a second power level higher than the first power level and at a second frequency higher than the first frequency; wherein, in response to a triggering event, the second core is to continue execution of the program at the second performance level after first core discontinues execution of the program.