Patent ID: 9384823
Filing Date: 2016-07-05
CPC Classification: G11C

Claim Text:
1. A static random access memory (SRAM) array comprising: multiple cell cores to store and retrieve word-wide organized data, wherein a cell core comprises a plurality of SRAM cells, and wherein at least two corresponding cell cores build a cell core row of the SRAM array, the SRAM array including at least two cell core rows, wherein the cell core row is configured to hold multiple storage words; a word decoder configured to decode one or more incoming address signals representing a storage address into a single word line, wherein one storage word uniquely identified by the single word line is activated within the cell core row, the word decoder comprising: a respective word line driver for each cell core row of the at least two cell core rows, configured to combine the upper portion of a word line select signal, of the one or more word line select signals, from the first decoding block of the decoding element corresponding to the cell core row and the lower portion of the word line select signal from the second decoding block of the decoding element corresponding to the cell core row to form a unique word line signal per storage address.