Patent ID: 9425815
Filing Date: 2016-08-23
CPC Classification: G04F,H03M

Claim Text:
1. An analog-to-digital converter (ADC) comprising: a first ADC stage, the first ADC stage comprises a successive approximation register (SAR), the first ADC stage is configured to convert an analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a digital output signal, and to generate a residual voltage corresponding to a voltage value difference between the analog input signal and the first digital signal; and a second ADC stage coupled with the first ADC stage, the second ADC stage comprises a plurality of time-to-digital converter (TDC) cells coupled in series, the second ADC stage is configured to convert the residual voltage into a plurality of second digital signals, wherein the second digital signals of the plurality of second digital signals collectively correspond to a least-significant-bits (LSB) portion of the digital output signal, and each TDC cell of the plurality of TDC cells is configured to generate a second digital signal of the plurality of second digital signals.