Patent ID: 9455348
Filing Date: 2016-09-27
CPC Classification: H01L

Claim Text:
1. A FinFET device for characterization, comprising: a dielectric material layer; a plurality of vertical active fins disposed directly over the dielectric material layer, each vertical active fin including a P+ contact area, a vertical P-type LDD fin, a vertical P-type body fin, a vertical N-type LDD fin, and an N+ contact area, wherein the vertical P-type LDD fin is formed between the P+ contact area and the vertical P-type body fin, and the vertical N-type LDD fin is formed between the vertical P-type body fin and the N+ contact area to provide a PN junction, wherein the vertical P-type LDD fin includes a p-type LDD doped feature and wherein the vertical N-type LDD fin includes an n-type LDD doped feature; a gate electrode formed over the plurality of vertical active fins and separated therefrom by a gate dielectric layer, a spacer layer including a first portion disposed directly over the vertical P-type LDD fin and a second portion disposed directly over the vertical N-type LDD fin, wherein the first and the second portions are formed on sidewalls of the gate electrode.