Patent ID: 9437472
Filing Date: 2016-09-06
CPC Classification: H01J,H01L

Claim Text:
1. A manufacturing method for a semiconductor isolation structure, comprising: patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a substrate by performing a first plasma etch at a first temperature; forming a trench having a sidewall angle greater than 88 degrees in the substrate correlated to the line feature by performing a second plasma etch at a second temperature; rounding a bottom of the trench by performing a third plasma etch at the second temperature; and filling the trench with isolation materials, wherein the first plasma etch is performed with at least two different plasma densities along a radial direction of the hard mask simultaneously, and the second plasma etch is performed with a uniform plasma density along the radial direction of the hard mask, and wherein the at least two different plasma densities are formed by applying a current ratio in a range of from about 0.5 to about 0.8 between the current entering a first set of magnetic coils close to a center of the wafer and the current entering a second set of the magnetic coils close to an edge of the wafer.