Patent ID: 9373403
Filing Date: 2016-06-21
CPC Classification: G11C,H01L

Claim Text:
1. A memory device, comprising: a plurality of horizontal structures on a substrate, the plurality of horizontal structures comprising conductive material, semiconductive material, or both; a plurality of vertical structures orthogonally arranged with the plurality of horizontal structures, the plurality of vertical structures comprising conductive material, semiconductive material, or both; a plurality of memory cells located at cross-points between the pluralities of vertical and horizontal structures; an indicator memory indicating which if any of the horizontal structures is to be excluded; and control circuitry coupled to the plurality of the horizontal structures, wherein for reading or programming of the memory device, the control circuitry which is responsive to the indicator memory applies a first control voltage to a selected one of the horizontal structures, applies a second control voltage to non-selected ones of the horizontal structures, and applies a third control voltage to an excluded one of horizontal structures.