Patent ID: 9281247
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A non-transitory computer readable medium for fabricating an integrated circuit structure, the computer readable medium having program instructions embodied therewith, the program instructions readable by at least one information processing system to cause the at least one information processing system to: pattern a strained silicon layer formed on a dielectric layer of a substrate into at least one N-type field-effect transistor (NFET) region comprising at least a first portion of the strained silicon layer; pattern the strained silicon layer into at least one P-type field-effect transistor (PFET) region comprising at least a second portion of the strained silicon layer; form a masking layer over the first portion of the strained silicon layer; transform, after forming the masking layer and while maintaining at least a top portion of the second portion of the strained silicon layer exposed, the second portion of the strained silicon layer into a relaxed silicon layer; epitaxially grow, after the second portion of the strained silicon layer has been transformed into the relaxed silicon layer, a silicon germanium layer on the relaxed silicon layer; and transform, while maintaining at least a top surface of the silicon germanium layer exposed, the relaxed silicon layer and the silicon germanium layer into a strained silicon germanium layer.