Patent ID: 9275720
Filing Date: 2016-03-01
CPC Classification: G11C,H03M

Claim Text:
1. A system comprising: a memory area comprising a plurality of cell groups of k memory cells in each cell group, wherein k is an integer greater than one; row and column decoder circuitry coupled to the memory area and configured to select at least one cell group; storage data encoder circuitry configured to encode an n-bit value, for an n>k, received at a data input of the system into a k-entry codeword of a voltage code the k-entry codeword representing a selection of a first permutation vector based on a first half of the n-bit value and a second permutation vector based on a second half of the n-bit value, wherein the first and second permutation vectors are weighted with first and second weights, respectively, and an element-by-element summation of the first and second permutation vectors, wherein each entry in the k entry codeword is one of three possible entry values; and storage data decoder circuitry configured to reconstruct the n -bit value from a k-entry vector read from the selected cell group by forming a k-length intermediate vector containing information about relative magnitudes of the elements of the read k-entry vector, the k-length intermediate vector determining the second half of the received n-bit value, forming a k-length difference vector by subtracting a weighted version of the first k-length intermediate vector from the read k-entry vector, the k-length difference vector determining the first half of the received n-bit value and outputting the reconstructed n-bit value.