Patent ID: 9501606
Filing Date: 2016-11-22
CPC Classification: G06F

Claim Text:
1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the method comprising: identifying a plurality of paths in the graph, each path starting from a timed source node and ending to a timed target node, each path comprising a plurality of clocked elements and a plurality of computational elements; optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths in the plurality of paths to satisfy a set of timing constraints; for each identified path, determining a ratio of data signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node; determining that the IC design fails a set of timing constraints when one or more of the paths have a ratio greater than one; identifying a path in the plurality of paths that has a maximum determined ratio as a cause for timing failure, wherein the ratio is calculated as a percentage value, and wherein the path that has the maximum determined ratio is identified as the path contributing a highest percentage to an overall timing failure of the IC design; generating a retimed design; and implementing the IC design using the retimed design.