Patent ID: 9318385
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A method for fabricating an apparatus comprising one or more semiconductor devices, the method comprising: (1) forming a workpiece, wherein forming the workpiece comprises: obtaining a substrate comprising a plurality of holes in a top surface of the substrate, each hole being a through-hole or a recess, the holes being spaced from each other, the top surface comprising a first surface portion not occupied by any of said holes and being above a bottom of each said hole; forming a separation layer over the substrate to separate the substrate from a subsequently formed conductive layer, the separation layer overlying the first surface portion and extending into each said hole; forming the conductive layer over the separation layer, the conductive layer extending into each said hole to provide in each said hole at least a part of an interconnect structure in the apparatus, the conductive layer being a different material than the separation layer, a top surface of the conductive layer having a recess over each said hole; forming a sacrificial layer covering the conductive layer, the sacrificial layer being a material different than the materials of the conductive layer and the separation layer; wherein a lowest point of the sacrificial layer is higher than a highest point of the separation layer; (2) polishing a top surface of the workpiece by a process in which: the sacrificial layer is removed over the first surface portion of the substrate and the conductive layer becomes exposed over the first surface portion of the substrate while the sacrificial layer remains over each said hole; then a remaining portion of the sacrificial layer is removed, and during a removal of the remaining portion of the sacrificial layer, at least part of the remaining portion of the sacrificial layer is polished simultaneously with polishing the conductive layer but at a lower polishing rate than the conductive layer, to provide the workpiece with a top surface having a protrusion of the conductive layer over each said hole; then the separation layer is polished away over the first surface portion of the substrate simultaneously with polishing of the conductive layer over each said hole.