Patent ID: 9430598
Filing Date: 2016-08-30
CPC Classification: G06F,H03K

Claim Text:
1. A method for designing a dual-mode logic circuit, wherein said logic circuit is selectably operational in static and dynamic modes, said method comprising: providing a basis library comprising a DML logic gate inverter and a plurality of dual-mode logic (DML) bicells, each of said DML bicells comprising: forming a pseudo-static library from said basis library by: forming a dynamic library from said basis library by specifying respective values of a plurality of dynamic timing parameters for said DML inverter and for each bicell of said basis library; defining a logic behavior of a required logic circuit; obtaining an initial logic circuit design by synthesis of said pseudo-static library and said defined logic behavior; and forming a dynamic circuit design by replacing modified pseudo-static library bicells in said initial logic circuit design with corresponding bicells from said dynamic library, wherein the synthesis of said pseudo-static library and said defined logic behavior is implemented by an electronic design automation system.