Patent ID: 9377501
Filing Date: 2016-06-28
CPC Classification: G01R,G09C,H04L

Claim Text:
1. A semiconductor wafer, having a die area and a scribe area, comprising: a die, formed on the die area of the semiconductor wafer, and having a main circuit; and a testing circuit, disposed on the scribe area of the semiconductor wafer, and electrically connected to the die for testing the main circuit, wherein the testing circuit further transmits test data to the main circuit, the main circuit transmits response data to the testing circuit when the main circuit receives the test data, and wherein the testing circuit determines whether the response data is equal to the test data, wherein the die further comprises a decryption circuit connected between the main circuit and the testing circuit, and wherein the testing circuit further encrypts the test data and transmits the encrypted test data to the decryption circuit, the decryption circuit decrypts the encrypted test data, and the main circuit transmits the response data according to the test data from the decryption circuit.