Patent ID: 9337121
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels, wherein the micro heat sink array comprises the substrate and an electrically conductive layer, wherein the substrate comprises: wherein the electrically conductive layer comprises: wherein the first electrically conductive layer includes a plurality of segments apart from each other, each segment including an upper surface facing the second surface, a lower surface opposite to the upper surface and a side surface connecting the upper surface and the lower surface, and wherein each of the sealing parts has a side surface coming in contact with the side surface of the plurality of segments.