Patent ID: 9362916
Filing Date: 2016-06-07
CPC Classification: H03K

Claim Text:
1. A circuit arrangement comprising: a level shifting stage coupled to a first reference voltage; a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage; a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage; an output electrode in electrical connection with the level shifting stage for providing one of a first output voltage and a second output voltage; and a feedback circuit coupled with the level shifting stage, the output electrode and a second reference voltage; wherein the first input voltage is configured to switch between a first logic state and a second logic state and the second input voltage is configured to switch between the second logic state and the first logic state; and wherein the level shifting stage is configured to generate the first output voltage when the first input voltage is in the first logic state and the second input voltage is in the second logic state and the level shifting stage is configured to generate the second output voltage when the first input voltage is in the second logic state and the second input voltage is in the first logic state; and wherein the feedback circuit is configured to maintain the first output voltage at the output electrode above a predetermined level when the first input voltage is in the first logic state and the second input voltage is in the second logic state; wherein the level shifting stage comprises a current mirror, the current mirror comprising: a second set of sequentially coupled pull-up and pull-down sub-circuits, the second set of sequentially coupled pull-up and pull-down sub-circuits coupled to the first set of sequentially coupled pull-up and pull-down sub-circuits to form the current mirror, wherein the first set of sequentially coupled pull-up and pull-down sub-circuits comprises: wherein the second set of sequentially coupled pull-up and pull-down sub-circuits comprises: a second pull-up transistor having a control electrode, a first controlled electrode and a second controlled electrode; a second pull-down transistor having a control electrode, a first controlled electrode and a second controlled electrode; and a current limiter sub-circuit having a first end and a second end;