Patent ID: 9384834
Filing Date: 2016-07-05
CPC Classification: G11C

Claim Text:
1. A storage device, comprising: a channel controller; and phase change memory integrated circuits (PCM ICs), arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which the at least one data bus line connects to the channel controller, wherein the channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a plurality of columns of the matrix configuration respectively corresponds to a plurality of the sub-channels, the plurality of the sub-channels forming a channel wherein each sub-channel corresponds to a respective finite state machine within the channel controller; and a plurality of rows of the matrix configuration respectively corresponds to a plurality of sub-banks, the plurality of sub-banks forming a bank, wherein each of the plurality of sub-banks comprises PCM ICs that each belong to distinct sub-channels of the plurality of the sub-channels.