Patent ID: 9331029
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method for fabricating a microelectronic package, the method comprising: placing a first semiconductor die on a temporary substrate; placing a first Surface Mount Device (SMD) on a backside of the first semiconductor die; after placing the first SMD on the backside of the first semiconductor die, forming an electrically-conducive trace to extend from the temporary substrate, along a sidewall of the first semiconductor die, and to a terminal of the first SMD; encapsulating the first semiconductor die, the first SMD, and the electrically-conductive trace within a molded panel; removing the temporary substrate to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed; and forming at least one redistribution layer over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.