Patent ID: 9281063
Filing Date: 2016-03-08
CPC Classification: G11C

Claim Text:
1. A flash memory, comprising a control circuit and a plurality of memory cells, wherein: each of the plurality of memory cells is a floating-gate Metal-Oxide-Semiconductor (MOS) transistor comprising a source, a gate, a drain, and a substrate; the control circuit is separately connected to the source, the gate, the drain, and the substrate of each memory cell and configured to output a control signal to the source, the gate, the drain, and the substrate of each memory cell, so as to implement a bitwise overwrite operation on at least one of the memory cells; and the control circuit is further configured to generate the control signal when data stored by any one of the plurality of memory cells is 0, so that the data stored by the one memory cell is overwritten from 0 to 1 according to the control signal, wherein the control signal is configured to control the substrate of the one memory cell to be grounded, the source to be connected to a negative Voltage of Programming Power (VPP), the drain to be connected to the negative VPP, and the gate to be connected to the negative VPP.