Patent ID: 9235244
Filing Date: 2016-01-12
CPC Classification: G06F,Y02D

Claim Text:
1. A processor comprising: a plurality of cores to independently execute instructions, each core including a decoder to decode instructions, at least one execution unit to execute instructions, and a retirement unit to retire executed instructions; a control register to store a single power domain indicator to indicate whether the plurality of cores are to be treated as a single power domain to operate at a common performance state; a voltage regulator to independently provide a regulated voltage to each of the plurality of cores to enable each of the plurality of cores to be an independent power domain and to operate at an independent performance state; and a power controller to cause the voltage regulator to provide a different regulated voltage to at least one of the plurality of cores to cause the at least one core to operate at the independent performance state based on a state of the single power domain indicator.