Patent ID: 9478534
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, comprising: depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first complementary metal-oxide semiconductor (CMOS) device and within a second recess located between sidewall spacers of a second CMOS device; depositing a dummy titanium nitride layer on the high-k dielectric layer; removing the high-k dielectric layer and the dummy titanium nitride layer from the second recess in the second CMOS device without removing the high-k dielectric and dummy titanium nitride layers from the first recess in the first CMOS device; depositing a silicon cap layer to fill the first recess and the second recess, the silicon cap layer being located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device; and implanting dopants into the silicon cap layer located in the second recess of the second CMOS device without implanting dopants into the silicon cap layer in the first recess of the first CMOS device.