Patent ID: 9355199
Filing Date: 2016-05-31
CPC Classification: G06F,H01L

Claim Text:
1. A computer-implemented method of camouflaging an application specific integrated circuit (ASIC) defined by camouflaged interconnected functional logic configured to perform an ASIC logical function, comprising the steps of: generating, in the computer, a first logical description describing a first plurality of interconnected logical cells together performing the ASIC logical function, wherein at least one of the first plurality of logical cells performs a cell logical function; generating, in the computer, a second logical description describing a second plurality of interconnected logical cells wherein the second plurality of interconnected logical cells includes a functionally inert camouflage element; generating, in the computer, a logical description of the camouflaged interconnected functional logic by associating the second logical description with the cell logical function to insert the second plurality of logical cells into the at least one of the interconnected first plurality of logical cells performing the cell logical function without modifying the ASIC logical function of the first plurality of logical cells; and generating, in the computer, a camouflaged ASIC design from the logical description of the camouflaged interconnected functional logic.