Patent ID: 9405711
Filing Date: 2016-08-02
CPC Classification: G06F,Y02D

Claim Text:
1. A method for traffic prioritization in a memory device, the method comprising: setting a first memory request priority register in a first processing element of a plurality of processing elements in the memory device to a first priority value based at least in part on a first load-to-use distance hint from a compiler and a first instruction execution rate associated with the first processing element; setting a second memory request priority register in a second processing element of the plurality of processing elements to a second priority value based at least in part on a second load-to-use distance hint from the compiler and a second instruction execution rate associated with the second processing element; sending a first memory access request comprising the first priority value from the first processing element to a crossbar interconnect in the memory device, the memory device further comprising: a plurality of memory controllers, each of the plurality of processing elements and each of the plurality of memory controllers being coupled to the crossbar interconnect, the plurality of memory controllers comprising a memory controller that comprises a queue that buffers a plurality of memory access requests to a memory stack comprising a plurality of memory dies stacked together, the plurality of memory access requests buffered in the queue comprising a second memory access request comprising the second priority value; routing the first memory access request through the crossbar interconnect to the memory controller; receiving the first memory access request at the memory controller; determining that the first priority value is greater than the second priority value, wherein the first priority value being greater than the second priority value indicates at least in part that the first instruction execution rate is less than the second instruction execution rate or that the second load-to-use distance hint is greater than the first load-to-use distance hint; and accessing, by the memory controller, the memory stack based on the first memory access request prior to accessing the memory stack based on the second memory access request.