Patent ID: 9330770
Filing Date: 2016-05-03
CPC Classification: G11C,H01L

Claim Text:
1. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a plurality of serially-connected nonvolatile memory cells, the method comprising: erasing the plurality of serially-connected nonvolatile memory cells by applying a plurality of word line erase voltages to the plurality of serially-connected nonvolatile memory cells via a plurality of word lines, the plurality of word lines being connected to the plurality of serially-connected nonvolatile memory cells respectively; and verifying the plurality of serially-connected nonvolatile memory cells, wherein the plurality of serially-connected nonvolatile memory cells are stacked on or above a substrate in a direction that is vertical to the substrate, and a level of each of the plurality of word line erase voltages is related with a distance between a corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate.