Patent ID: 9230990
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A silicon-on-insulator integrated circuit comprising: a semiconductor substrate layer; an oxide insulating material layer disposed over the substrate layer; a semiconductor layer formed over the insulating material layer; within the semiconductor layer, a plurality of parallel, spaced apart first shallow trench isolation (STI) structures that extend completely though the semiconductor layer to contact with the oxide insulating material layer; within the semiconductor layer, a plurality of parallel, spaced apart second STI structures that extend only part-way into the semiconductor layer, wherein at least two of the plurality of second STI structures are provided such that no first STO structure is provided therebetween; a plurality of body contact regions in the semiconductor substrate between at least one of the first and at least one of the second STI structures; source/drain regions in the semiconductor substrate between the at least two of the plurality of second STI structures; a gate structure having a first portion over the plurality of second STI structures and a second portion over the source/drain regions; and contact plugs to the body contact regions, to the source/drain regions, and to the gate structure.