Patent ID: 9239791
Filing Date: 2016-01-19
CPC Classification: G06F

Claim Text:
1. A circuit arrangement, comprising: a cache memory; a memory address translation data structure for use in performing a memory address translation for a memory access request initiated by a processing unit in communication with the cache memory, the memory address translation data structure including translation data that translates between a real memory address and an effective or virtual memory address for a memory page associated with the memory access request and at least one swizzle-related page attribute that indicates on a page basis whether data in the memory page associated with the memory access request should be swizzled; and control logic configured to cause data from the memory page to be stored in the cache memory in a swizzled format based upon the at least one swizzle-related page attribute in the memory address translation data structure, wherein at least a portion of the control logic is coupled intermediate the cache memory and a lower memory, and wherein the control logic is configured to cause the data to be stored in the cache memory in the swizzled format by swizzling the data to generate swizzled data and storing the swizzled data in the cache memory.