Patent ID: 9373622
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a CMOS device, comprising steps of: forming a plurality of NMOS gate trenches and a plurality of PMOS gate trenches on a substrate; forming a gate insulating layer in each NMOS gate trench and each PMOS gate trench; forming a first barrier layer, an etching stop layer, and a sacrificial layer containing a dopant in turn on the gate insulating layer in the plurality of NMOS gate trenches and the plurality of PMOS gate trenches; performing an annealing to force the dopants in the sacrificial layer at least partially into the first barrier layer; selectively removing the sacrificial layer in the plurality of NMOS gate trenches and the plurality of PMOS gate trenches by etching; selectively depositing a PMOS work function adjusting layer in the plurality of PMOS gate trenches; and forming an NMOS work function adjusting layer, a second barrier layer, and a filling layer in turn in the plurality of NMOS gate trenches and the plurality of PMOS gate trenches.