Patent ID: 9245644
Filing Date: 2016-01-26
CPC Classification: G11C

Claim Text:
1. An integrated circuit, comprising: a nonvolatile memory array with a plurality of memory groups including a first set of one or more memory groups, a second set of one or more memory groups, and a third set of one or more memory groups, wherein a same well is shared by: (i) the first set of one or more memory groups, and (ii) the second set of one or more memory groups, and wherein different wells are used by: (i) the first set of one or more memory groups, and (ii) the third set of one or more memory groups; and control circuitry to erase only the first set of one or more memory groups, and to apply a recovery bias arrangement that adjusts threshold voltages of memory cells to at least one memory group of the second set of one or more memory groups but not to the third set of one or more memory groups.