Patent ID: 9495490
Filing Date: 2016-11-15
CPC Classification: G06F

Claim Text:
1. A computer-implemented method for detecting active power dissipation in an integrated circuit, the computer-implemented method comprising: receiving a hardware design for the integrated circuit having one or more clock domains, wherein the hardware design comprises a local clock buffer for a first clock domain of the one or more clock domains, wherein the local clock buffer is configured to receive a clock signal and an actuation signal, wherein the local clock buffer is configured to pass the clock signal to logic elements in the first clock domain in response to the actuation signal being active; adding instrumentation logic to the hardware design for the first clock domain, wherein the instrumentation logic is configured to compare a first value of the actuation signal determined at a beginning point of a test period to a second value of the actuation signal determined at a time when the first clock domain is in an idle condition, wherein the instrumentation logic comprises a register coupled to store the actuation signal at the beginning point of the test period, wherein an output of the register is coupled to a first input of a compare logic, wherein a second input of the compare logic is coupled to receive the actuation signal at the time when the first clock domain is in the idle condition, wherein the compare logic is configured to output an indication of whether the first input equals the second input; detecting the first clock domain is without unintended active power dissipation, in response to the first value of the actuation signal being equal to the second value of the actuation signal; and detecting the first clock domain includes unintended active power dissipation, in response to the first value of the actuation signal not being equal to the second value of the actuation signal.