Patent ID: 9331677
Filing Date: 2016-05-03
CPC Classification: H03K,H03L

Claim Text:
1. A circuit comprising: a delay element having a delay and including an input and an output, the input being coupled to the output; a voltage adjust line configured to provide an adjusting voltage to the delay element to provide fine-adjusting of the delay of the delay element; and a controllable capacitance coupled to the output of the delay element, the controllable capacitance configured such that a change of the controllable capacitance provides coarse-adjusting of the delay of the delay element, wherein the course-adjusting of the delay of the delay element by the controllable capacitance results in discrete delays with a first delay being between two adjacent discrete delays, the fine-adjusting of the delay of the delay element by the adjusting voltage results in a range of delays with a range greater than the first delay, and the change of the controllable capacitance is independently adjustable from a change in the adjusting voltage.