Patent ID: 9264051
Filing Date: 2016-02-16
CPC Classification: H03K,H03L

Claim Text:
1. A clock generation circuit, comprising: a delay clock generation unit configured to generate a predetermined number of delay clock signals having different delay time periods for a reference clock signal; a low-speed clock generation unit configured to generate a low-speed clock signal having a lower frequency than the reference clock signal in accordance with a control signal that controls a phase; a control signal processing unit configured to perform, on the control signal, a quantization process in which a value of the control signal is quantized into the predetermined number of discrete values and a modulation process in which a quantization error occurred in the quantization process is distributed in a band of frequencies higher than a predetermined frequency; a selection unit configured to select any one of the predetermined number of delay clock signals in accordance with the control signal on which the quantization process and the modulation process are performed; and an output unit configured to output the low-speed clock signal in synchronization with the selected delay clock signal.