Patent ID: 9455007
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A memory comprising: a memory array comprising a plurality of rows and columns of array blocks disposed in array block areas, array blocks including sub-arrays of memory cells arranged in rows and columns with word lines disposed in a patterned gate layer along the rows and one or more patterned conductor layers including bit lines disposed along the columns; a plurality of sets of local word line drivers arranged in rows and columns, the sets of local word line drivers being disposed adjacent to corresponding array blocks, including conductors in the one or more patterned conductor layers connected to respective word lines in the corresponding array blocks; and a set of global word line drivers disposed in a global word line driver area connected to a corresponding set of global word lines, the global word line drivers in the set drive global word lines disposed in an overlying patterned conductor layer over the one or more patterned conductor layers, each global word line connected to a group of local word line drivers along a row of the sets of local word line drivers.