Patent ID: 9384853
Filing Date: 2016-07-05
CPC Classification: G09G,G11C

Claim Text:
1. A shift register comprising a plurality of stages, each of the stages outputting k composite pulses (where k is a natural number greater than 1), each of the composite pulses comprising an A-scan pulse and a B-scan pulse, wherein at least one of the stages comprises: an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse; at least one B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse based on the voltage at the B-set node, the voltage at the at least one B-reset node and any one BB-clock pulse; and a scan output controller for generating k A-scan pulses based on at least one of the voltage at the A-set node and the A-carry pulse and k A-clock pulses, generating k B-scan pulses based on the B-carry pulse and k B-clock pulses, and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as a corresponding one of the composite pulses.