Patent ID: 9336147
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. A method comprising: partitioning a cache into a plurality of cache partitions by a computing device, wherein the cache is part of a processor of the computing device and is separate from a memory associated with the computing device; receiving a cache allocation plan for a first entity and a second entity by the computing device, wherein the cache allocation plan is for the cache and is independent of a memory allocation plan for the memory that is associated with the first entity and the second entity; allocating a first subset of the plurality of cache partitions to the first entity, and a second subset of the plurality of cache partitions to the second entity according to the cache allocation plan by the computing device, wherein the first subset of the plurality of the cache partitions is greater than the second subset of the plurality of cache partitions, and wherein an amount of the cache that is allocated to the first entity is independent of an amount of the memory that is allocated to the first entity; allocating a first subset of a plurality of memory partitions of the memory to the first entity, and a second subset of the plurality of memory partitions to the second entity according to the memory allocation plan by the computing device, wherein the second subset of the plurality of memory partitions is greater than the first subset of the plurality of memory partitions, and wherein the second subset of the plurality of memory partitions is mapped to the first subset of the plurality of cache partitions; and providing the first entity access to the first subset of the plurality of cache partitions and providing the second entity access to the second subset of the plurality of cache partitions by the computing device.