Patent ID: 9269613
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device with a copper interconnect structure, comprising: providing a substrate; forming a sacrificial layer on the substrate; forming a photoresist layer on the sacrificial layer; forming a plurality of first windows in the photoresist layer by photolithography using a first mask; forming a plurality of first openings in the sacrificial layer by an etching process using the first windows as a mask; forming a plurality of second windows in the photoresist layer corresponding to the plurality of first windows, wherein a width of each of the second windows is greater than a width of the corresponding first window such that a portion of the sacrificial layer is exposed in the second windows; forming a plurality of second openings by an etching process using the second window as a mask such that the top portion of each of the second openings is in a shape of an inverted trapezoid; removing the photoresist layer; depositing a layer of dielectric material on the sacrificial layer and in the second openings; and forming the first interconnect dielectric layer by removing the deposited layer of dielectric material using a chemical mechanical polishing (CMP) process until a tip of the sacrificial layer between two second openings is also removed to form a releasing opening; removing the sacrificial layer to form cavities with corresponding releasing openings as the top of the cavities; depositing a second interconnect dielectric layer on the first interconnect dielectric layer such that the second interconnect dielectric layer seals the releasing openings without filling the cavities; forming a second photoresist layer on the second interconnect dielectric layer; forming a plurality of third windows in the second photoresist layer by photolithography using the first mask such that the third windows have a smaller window width than the first windows; and forming a plurality of conduits in the first interconnect dielectric layer and the second interconnect dielectric layer by an etching process using the third windows as a mask such that the cavities are maintained in the first interconnect dielectric layer; and depositing copper in the plurality of conduits to form a copper interconnect layer of the copper interconnect structure, wherein: the first interconnect dielectric layer, between neighboring conduits, contains the plurality of cavities each in a shape of a combination of a trapezoid and a rectangle such that dielectric constant of the first interconnect dielectric layer is reduced; the second interconnect dielectric layer seals the top of the cavities; the substrate forms a bottom surface of the cavities; and a width of the top of the cavities is less than a width of the bottom of the cavities; an upper portion of each cavity is in a shape of a trapezoid; a lower portion of each cavity is in a shape of a rectangle.