Patent ID: 9461078
Filing Date: 2016-10-04
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer sequentially formed on a base substrate, wherein the first metal layer includes a first connection pattern, the first insulating layer includes a first via-hole, the second metal layer includes a second connection pattern, the second insulating layer includes a transition via-hole and a second via-hole, the first via-hole corresponds to a position where the first connection pattern is located, the transition via-hole corresponds to a position where the first via-hole is located, the first metal layer is electrically connected to the first conductive layer through the first via-hole and the transition via-hole, the second via-hole corresponds to a position where the second connection pattern is located, and the second metal layer is electrically connected to the first conductive layer through the second via-hole.