Patent ID: 9384316
Filing Date: 2016-07-05
CPC Classification: G06F

Claim Text:
1. A method for reducing congestion in an integrated circuit design, the method comprising: identifying, by one or more computer processors, a first net, wherein the first net defines a path on one or more of a plurality of conducting layers in an integrated circuit and the first net has an associated signal transit time that depends, at least in part, on the path defined by the first net; identifying, by one or more computer processors, a first subnet of the first net in a congested area of the integrated circuit, wherein the first subnet of the first net has a first wire width and lies on a first conducting layer of the integrated circuit; modifying, by one or more computer processors, the first subnet of the first net, such that the congested area becomes less congested, wherein modifying the first subnet of the first net comprises decreasing the first wire width of the first subnet of the first net while keeping the first subnet of the first net in the first conducting layer; identifying, by one or more computer processors, a second subnet of the first net in an uncongested area of the integrated circuit, wherein the second subnet of the first net has a second wire width and lies on a second conducting layer of the integrated circuit; modifying, by one or more computer processors, the second subnet of the first net, such that the signal transit time of the first net decreases; identifying, by one or more computer processors, a second congested area of the integrated circuit design; identifying, by one or more computer processors, a second net that crosses the second congested area and has a greatest amount of positive slack of nets crossing the second congested area, wherein the second net defines a path from a signal source to a signal sink; modifying, by one or more computer processors, a first subnet of the second net to reduce slack on the second net; responsive to determining that after modifying the first subnet of the second net, the second net does not have positive slack, scanning, by one or more computer processors, the second net progressively from the signal source to the signal sink to identify a second subnet of the second net that lies in an uncongested area of the integrated circuit design; modifying, by one or more computer processors, the second subnet of the second net to increase slack on the second net; and responsive to determining that after modifying the second subnet of the second net, the second net does not have positive slack, iterating through and modifying each remaining subnet of the second net to increase slack on the second net until slack on the second net becomes positive or all subnets of the second net have been modified.