Patent ID: 9337420
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a variable resistance memory device, the method comprising: forming a multi-layered insulating layer by alternately forming a first insulating layer and a second insulating layer on a semiconductor substrate, on which a lower electrode is formed; forming a first hole exposing the lower electrode by etching the multi-layered insulating layer; forming an oxide layer by oxidizing a portion of the second insulating layer; removing the oxide layer so that the first insulating layer protrudes toward the inside of the first hole; forming a spacer material, including a void, in the first hole; forming a second hole, exposing the lower electrode, by removing a portion of the spacer material to a certain depth of the first hole; forming a variable resistance material layer in the second hole; and forming an upper electrode in a portion of the first hole from which the spacer material has been removed.