Patent ID: 9355052
Filing Date: 2016-05-31
CPC Classification: G06F

Claim Text:
1. A computer system comprising: at least one processor; a memory coupled to the at least one processor; a plurality of address translation tables in the memory that point to a corresponding plurality of direct memory access (DMA) windows, each of the plurality of DMA windows defining a contiguous block of addresses for a device driver of a corresponding I/O device; and a dynamic DMA window mechanism that determines when a change to a window size of a specified one of the plurality of DMA windows is needed when at least one of the following occurs: in response to determining the change to the window size of the specified DMA window is needed, the dynamic DMA window mechanism identifies a donor DMA window that is adjacent to the specified DMA window, dynamically shrinks the donor DMA window by a specified block, dynamically increases the specified DMA window to use the specified block that was formerly in the donor DMA window, invalidates a portion of at least one of the plurality of contiguous address translation tables that used to point to the specified block that was formerly in the donor DMA window, creates a new address translation table distinct from the plurality of contiguous address translation tables corresponding to the specified DMA window to point to the specified block, returns to a device driver of an I/O device that corresponds to the donor DMA window an address range corresponding to the shrunk donor DMA window, and returns to a device driver of an I/O device that corresponds to the specified DMA window an address range corresponding to the increased specified DMA window.