Patent ID: 9515172
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate; a fin region vertically protruding from an upper surface of the substrate and extending longitudinally in a first direction, the fin region comprising first and second fin subregions spaced apart from each other in the first direction; a discrete isolation insulating island disposed between the first and second fin subregions, a lower surface of the discrete isolation insulating island contacting a portion of the fin region and the discrete isolation insulating island comprising opposing sidewalls that are parallel to the first direction and exposed by the fin region; a first gate intersecting the first fin subregion and extending in a second direction different from said first direction; a second gate intersecting the second fin subregion and extending in the second direction; and a third gate intersecting the discrete isolation insulating island, extending in the second direction and covering the opposing sidewalls of the discrete isolation insulating island, wherein each of the first, second and third gates comprises a gate dielectric layer and a gate electrode, and wherein the gate dielectric layer of the third gate is between the gate electrode of the third gate and the discrete isolation insulating island.