Patent ID: 9431205
Filing Date: 2016-08-30
CPC Classification: G06F,H01J

Claim Text:
1. A semiconductor device fabrication method compromising: forming a dielectric layer upon a backside carrier; forming a field emission transistor trench within the dielectric layer; forming a conductive layer upon the field emission trench walls; filling the field emission trench with a gate contact dielectric; recessing the dielectric layer and the gate contact dielectric to expose a paired emitter portion and collector portion of the conductive layer; folding the exposed conductive layer paired portions inward; forming a self-aligned gate between the paired folded conductive layer portions; planarizing a backside of the dielectric layer to expose the gate contact dielectric; forming one or more backside dielectric layers upon the backside of the dielectric layer and upon the exposed gate contact dielectric; forming a gate contact trench within the one or more backside dielectric layers and within the gate contact dielectric to expose the gate, and; forming a gate contact within the gate contact trench.