Patent ID: 9300578
Filing Date: 2016-03-29
CPC Classification: H04L

Claim Text:
1. A system, comprising: a classifier engine configured to classify network segments based on a source address, a destination address, a source port and a destination port, wherein the classifier engine splits a network segment into a packet header and packet data, a first memory configured to store packet headers associated with the network segments, wherein the first memory is on-chip memory; a gather buffer configured to store packet data associated with the network segments based at least in part on a sequence number stored in each of the packet headers; and a processor configured for receiving the packet headers and generating a single packet header for the network segments that are in a predetermined sequence in response to a determination that the gather buffer storing the packet data for the network segments has reached a predetermined size, and the processor is further configured for generating another single packet header for previously gathered packet data in response to receiving a network segment that is not in a predetermined sequence wherein the processor is distinct from a central processing unit of a system on a chip and the processor, the first memory, and the classifier engine are embedded on the system on a chip.