Patent ID: 9385119
Filing Date: 2016-07-05
CPC Classification: H01L,H02M

Claim Text:
1. A semiconductor arrangement, comprising: a semiconductor body with a first active region, a second active region and an isolation region arranged between the first and the second active regions; at least one source region and at least one body region of a first transistor integrated in the first active region; at least one source region and at least one body region of a second transistor integrated in the second active region; and source and body regions of a third transistor integrated in the second active region; wherein the first transistor, the second transistor and the third transistor have a common drain electrode, wherein the isolation region is configured to act as an edge termination for the first transistor integrated in the first active region and the second and third transistors integrated in the second active region so that the first transistor and one of the second and third transistors can switch on independently.