Patent ID: 9362207
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, the metal wiring comprising: an isolator region; a first lower metal layer electrically connected to the semiconductor component; a first upper metal layer configured to be electrically connected to an external power supply; a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug formed in a via trench for providing an electrical connection between the first lower metal layer and the first upper metal layer; and a plurality of etching stop layers deposited on each of the plurality of inter-metal dielectric layers, wherein the plurality of inter-metal dielectric layers are each a continuous multilayer oxide film formed between adjacent etching stop layers or between the first upper or lower metal layer and its respective adjacent etching stop layer, wherein the plurality of inter-metal dielectric layers are each a multilayer oxide film comprising a plurality of alternating tensile stress oxide layers and compressive stress oxide layers.