Patent ID: 9345148
Filing Date: 2016-05-17
CPC Classification: H01L,H05K,Y02P

Claim Text:
1. A method of making a semiconductor device, comprising: providing a semiconductor die including a composite interconnect comprising a fusible portion and non-fusible portion formed over a surface of the semiconductor die, wherein a melting temperature of the fusible portion is less than a melting temperature of the non-fusible portion; providing a substrate including a conductive trace comprising an interconnect site formed over the substrate; forming a solder resist opening (SRO) over the interconnect site with a portion of the interconnect site extending outside the SRO; and reflowing the fusible portion of the composite interconnect, wherein the fusible portion of the composite interconnect overlaps an outer sidewall of the interconnect site and contacts a sidewall of the SRO outside a footprint of the interconnect site.