Patent ID: 9454851
Filing Date: 2016-09-27
CPC Classification: G06T

Claim Text:
1. A method in a processor, comprising: receiving a coarse disparity map; generating an intermediate disparity map from the coarse disparity map by performing a first number of refinement iterations on the coarse disparity map, wherein a pixel from the coarse disparity map is selected for each iteration based on iteration number and height and width of a reference image, wherein the refinement iterations are performed using an aggregation window for each of the selected pixels, wherein size of the aggregation window varies per selected pixel; and generating a final disparity map from the intermediate disparity map by performing a second number of joint bilateral up-sampling iterations on the intermediate disparity map, wherein a pixel from the intermediate disparity map is selected for each iteration based on the iteration number and the height and the width of the reference image.