Patent ID: 9368504
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate; a static random access memory cell including an access transistor, a drive transistor, and a load transistor; first and second wiring portions formed over the semiconductor substrate to extend in a first direction, while keeping a first space therebetween, the first wiring portion being associated with the access transistor, and the second wiring portion being associated with the drive transistor; third and fourth wiring portions formed above the first and second wiring portions to extend in a second direction intersecting the first direction, while keeping a second space therebetween, the third and fourth wiring portions each having an uppermost surface that is insulating, the third and fourth wiring portion being electrically coupled to the static random access memory cell; and a contact plug having an uppermost surface that is above the uppermost insulating surfaces of the third and fourth wiring portions, the contact plug extending between the third and fourth wiring portions and between the first and second wiring portions and reaching the semiconductor substrate, wherein the contact plug extends outwardly from the portion thereof located between the third and fourth wiring portions toward a position immediately above at least one of the third and fourth wiring portions to hang thereover and extends outwardly from the portion thereof located between the first and second wiring portions toward a position immediately above at least one of the first and second wiring portions to hang thereover.