Patent ID: 9500922
Filing Date: 2016-11-22
CPC Classification: G02F,G09G

Claim Text:
1. An array substrate, comprising: a substrate; a plurality of pixel regions disposed on the substrate and defined by a plurality of gate lines and a plurality of data lines; and a common electrode and a pixel electrode disposed in each of the plurality of pixel regions, two pixel regions at adjacent rows in a same column form a pixel set, a first gate line and a second gate line are disposed between the two pixel regions of the pixel set, and the data line is disposed on a same side of the two pixel regions, wherein a first switch transistor and a third switch transistor are disposed in one pixel region of the pixel set and at least a second switch transistor is disposed in another pixel region, wherein gate electrodes of the first and second switch transistors are respectively connected to the first gate line and the second gate line, source electrodes of the first and second switch transistors are both connected to a same data line, and drain electrodes of the first and second switch transistors are respectively connected to a pixel electrode in their respective pixel region, and wherein a gate electrode of the third switch transistor is connected to the first gate line, a source electrode of the third switch transistor is connected to a common electrode in the pixel region having the third switch transistor, and a drain electrode of the third switch transistor is connected to a pixel electrode in the pixel region having the second switch transistor.