Patent ID: 9372771
Filing Date: 2016-06-21
CPC Classification: G06F,G11C

Claim Text:
1. A method for modifying an integrated circuit (IC) design for built-in self-test (BIST) using an electronic design automation (EDA) tool, wherein the IC design includes a plurality of embedded memories and a testing unit that generates a first set of test vectors and a second set of test vectors, and wherein the EDA tool includes a system memory that stores the IC design and a processor in communication with the system memory, the method comprising: identifying a first set of memories of the plurality of embedded memories that have word counts in a common power of two range; identifying a first memory of the plurality of embedded memories that does not have a word count in the common power of two range; identifying a first subset of the first set of memories that has a common memory block count and a common column multiplexing factor; identifying a second memory of the first set of memories that does not have at least one of a common memory block count and a common column multiplexing factor; adding a common scrambling unit to the IC design for generating a first set of addresses for the first subset of the first set of memories for testing the first subset of the first set of memories; adding a first scrambling unit to the IC design for generating a second set of addresses for said second memory for testing said second memory; adding a second scrambling unit to the IC design for generating a third set of addresses for said first memory for testing said first memory; adding a common chip select unit to the IC design for selecting memories of the first set of memories for BIST; adding a common comparator to the IC design for comparing the first set of test vectors with a first set of response vectors generated by the first set of memories based on the first set of test vectors during BIST and generating a first set of comparison signals; adding a first comparator to the IC design for comparing the second set of test vectors with a second set of response vectors generated by said first memory based on the second set of test vectors during BIST and generating a second set of comparison signals; adding a common repairing unit to the IC design for repairing the first set of memories based on the first set of comparison signals; adding a first repairing unit to the IC design for repairing said first memory based on the second set of comparison signals, thereby generating a modified IC design; and storing the modified IC design in the system memory.