Patent ID: 9455023
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A memory device, comprising: a plurality of wordlines connected to a plurality of memory cells; wordline logic connected between the plurality of wordlines and a plurality of driver interconnects; power logic connected to a voltage source and the plurality of driver interconnects, and including a network of interconnects that electrically connect the plurality of driver interconnects together to form a virtual power network, wherein, in response to a memory request, the power logic connects the voltage source with the virtual power network to store an electric charge within the virtual power network, and wherein the wordline logic under-drives a requested wordline of the plurality of wordlines associated with the memory request by connecting the requested wordline with the virtual power network to share the electric charge stored in the virtual power network with the requested wordline, and wherein the wordline logic under-drives a voltage of the requested wordline to be lower than a source voltage provided by the voltage source.