Patent ID: 9524124
Filing Date: 2016-12-20
CPC Classification: G06F

Claim Text:
1. A semiconductor device comprising: a first memory cell array configured to store data according to a first address on a first basis; a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis; a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request; an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array; and a migration controller configured to migrate a portion of the data stored in the second memory cell array into the first memory cell array by referring to the address map table, wherein the address map table comprises: a first list comprising a first node corresponding to the first address; and a second list comprising a second node associated with the first list and the second address, and wherein the migration controller is configured to select data from the second memory cell array and to migrate the selected data into the first memory cell array when a residual space of the second memory cell array is equal to or less than a threshold value.