Patent ID: 9318204
Filing Date: 2016-04-19
CPC Classification: G11C

Claim Text:
1. A non-volatile memory, comprising: an array of memory cells; a plurality of word lines and bit lines for accessing the array of memory cells; and a programming circuit for programming a group of memory cells in parallel, the programming circuit comprising: word line driver circuitry for providing a programming voltage to a selected word line to the group of memory cells, the programming voltage comprising a series of pulses having increasing voltage levels; the group of memory cells having a number of program-enabled and program-inhibited memory cells that varies dynamically with each pulse of the series of pulses; and the word line driver circuitry including a control module to adjust an individual timing of a pulse of the series of pulses, responsive to relative numbers of program-enabled and program-inhibited memory cells in the group of memory cells associated with the pulse.