Patent ID: 9349725
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor layer having a first main surface and an opposing second main surface, the first main surface defining a plane containing a first axis and a second axis perpendicular to the first axis; a first gate disposed proximate the first main surface of the semiconductor layer and extending parallel to the first axis; a dielectric layer formed on the first main surface of the semiconductor layer and separating the first gate from the first main surface of the semiconductor layer; a first trench formed in the semiconductor layer proximate the first gate and extending from the first main surface of the semiconductor layer toward the second main surface of the semiconductor layer; a second trench formed in the semiconductor layer proximate the first gate and extending from the first main surface of the semiconductor layer toward the second main surface of the semiconductor layer, the first and second trenches being spaced apart from one another in a direction parallel to the first axis; a first plurality of contact windows formed in the dielectric layer and arranged in a first row extending between the first and second trenches in a direction parallel to the first axis, adjacent contact windows in the first row being separated from one another only by the dielectric layer, each of the first plurality of contact windows exposing a portion of the first main surface of the semiconductor layer, the first row being arranged substantially parallel to the first gate; a second plurality of contact windows formed in the dielectric layer and arranged in a second row extending between the first and second trenches parallel to the first row, adjacent contact windows in the second row being separated only by the dielectric layer, each of the second plurality of contact windows exposing a portion of the first main surface of the semiconductor layer, the second row being arranged substantially parallel to the first gate; a second gate disposed proximate the first main surface of the semiconductor layer on an opposite side of the first and second trenches from the first gate and extending parallel to the first axis, the first gate, and the first and second rows; a third trench formed in the semiconductor layer at an opposite side of the second gate from the first trench, the third trench extending from the first main surface of the semiconductor layer toward the second main surface of the semiconductor layer; and a fourth trench formed in the semiconductor layer at an opposite side of the second gate from the second trench, the fourth trench extending from the first main surface of the semiconductor layer toward the second main surface of the semiconductor layer, the third and fourth trenches being spaced apart from one another in a direction parallel to the first axis; a third plurality of contact windows formed in the dielectric layer and arranged in a third row extending between the third and fourth trenches in a direction parallel to the first axis, adjacent contact windows in the third row being separated from one another only by the dielectric layer, each of the third plurality of contact windows exposing a portion of the first main surface of the semiconductor layer, the third row being arranged substantially parallel to the second gate; and a fourth plurality of contact windows formed in the dielectric layer and arranged in a fourth row extending between the third and fourth trenches parallel to the third row, adjacent contact windows in the fourth row being separated only by the dielectric layer, each of the fourth plurality of contact windows exposing a portion of the first main surface of the semiconductor layer, the fourth row being arranged substantially parallel to the second gate.