Patent ID: 9299409
Filing Date: 2016-03-29
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor storage device comprising: (i) a cell array including: a plurality of resistance change elements formed above a semiconductor substrate, a plurality of first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements, a plurality of first gate electrodes included in the first cell transistors and extending in a first direction, first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction, second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction, and a plurality of first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle; and (ii) a bit line controller including: a plurality of second cell transistors formed on the semiconductor substrate and each having a current path with one end electrically connected to the first bit lines or the second bit lines, a plurality of second gate electrodes included in the second cell transistors and extending in the first direction, and a plurality of second active areas in which the second cell transistors are formed, and which extend in a direction crossing the first direction at a second angle.