Patent ID: 9448917
Filing Date: 2016-09-20
CPC Classification: G06F

Claim Text:
1. A verification method of a system on chip comprising: receiving, by a processor included in the system on chip, a test generator and an exception handler; generating, by the processor including the test generator, a test program including an exception-causing instruction based on a test template; executing, by the processor, a first instruction at a first operating state as the test program is executed; stopping, by the processor, the execution of the test program when the exception-causing instruction is executed during the execution of the test program; performing, by the processor, a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program, the fixed instruction sequence including storing context corresponding to the processor; and resuming the test program from a second instruction at a second operating state set after the fixed instruction sequence is performed, the second instruction having an address next to an address of the exception-causing instruction.