Patent ID: 9287196
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. An apparatus comprising: a stack including a plurality of integrated circuit die layers including at least a first die layer and an adjacent second die layer, each die layer including an active metal side and an opposite RDL (re-distribution layer); and a plurality of through silicon vias including a first set of through silicon vias formed through the first die layer and a second set of through silicon vias formed through the second die layer, wherein each of the first set of through silicon vias includes an inductive structure and each of the second set of through silicon vias includes a capacitive structure; wherein the apparatus includes a plurality of resonant circuits to carry clock signals, each of the resonant circuits including a first through silicon via of the first set of through silicon vias used as an inductive circuit element of the resonant circuit and a second through silicon via of the second set of through silicon vias used as a capacitive circuit element of the resonant circuit, the first through silicon via of each resonant circuit being coupled with the respective second through silicon via of the resonant circuit via the RDL of the first die layer; wherein each of the first set of through silicon vias is utilized both for transport of the clock signals between die layers, including transport of clock signals from the first die layer to the second die layer, and for the generation of inductance for the respective resonant circuit; and wherein each of the resonant circuits is shared between the first die layer and the second die layer, a clock grid of the first die layer resonating at a same frequency and being synchronous with a clock grid of the second die layer.