Patent ID: 9476926
Filing Date: 2016-10-25
CPC Classification: G01R,G11B

Claim Text:
1. A system, comprising a processor and logic integrated with and/or executable by the processor, the logic being configured to cause the processor to: build a slider delta comparison map using slider electrical and/or row bar quasi testing results, wherein row bar quasi testing is performed on row bars of multiple sliders, wherein slider electrical testing is performed on individual sliders, and wherein the slider delta comparison map comprises a visual representation of the slider electrical and/or row bar quasi testing results for a parent job to allow for pattern recognition of electrostatic discharge (ESD) problems; determine whether a test device in a parent job passes primary (ESD) delta criteria; flag the parent job of the test device as a reroute job and perform automatic actual parts rerouting for any jobs related to the parent job to pull parts from a test bin as opposed to a supply bin when the test device fails the primary ESD delta criteria; and create an automated report that includes relevant information regarding the failed test device.