Patent ID: 9411669
Filing Date: 2016-08-09
CPC Classification: G06F,G11C

Claim Text:
1. A method of identifying high error rate data in a block-erasable nonvolatile memory comprising: (a) maintaining individual write-erase cycle counts for a plurality of blocks of the nonvolatile memory; (b) selecting a first subset of the plurality of blocks for error rate sampling, the first subset consisting of blocks with the lowest write-erase cycle counts of the plurality of blocks; (c) sampling data stored in the first subset of the plurality of blocks to estimate a first error rate for the first subset of the plurality of blocks; (d) comparing the first error rate with a first limit; (e) in response to determining that the first error rate exceeds the first limit, expanding the first subset to include additional blocks with next lowest write-erase cycle counts of the plurality of blocks; and (f) repeating steps (c)-(e).