Patent ID: 9530497
Filing Date: 2016-12-27
CPC Classification: G11C

Claim Text:
1. A method of programming a memory device, comprising: programming a resistive memory storage element from an intermediate resistance state to a higher resistance state or a lower resistance state at least in part by applying a plurality of electrical pulses having peak pulse amplitudes that sequentially ramp in a first direction when the resistive memory storage element is being programmed to the higher resistance state and sequentially ramp in an opposite second direction when the resistive memory storage element is being programmed to the lower resistance state, wherein when programming the resistive memory storage element to the lower resistance state, programming comprises applying a forward-biased staircase pulse sequence having a first polarity, and wherein when programming the resistive memory storage element to the higher resistance state, programming comprises applying a reverse-biased staircase pulse sequence having a second polarity opposite from the first polarity.