Patent ID: 9312850
Filing Date: 2016-04-12
CPC Classification: H03K

Claim Text:
1. An integrated circuit, comprising: a voltage divider for receiving a first supply voltage and outputting a second supply voltage; a power-on-reset (POR) circuit connected to the voltage divider for receiving the second supply voltage and generating a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold; an inverter connected to the POR circuit for receiving the POR voltage signal and generating an inverted POR voltage signal; a level-shifter connected to the POR circuit and the inverter for receiving the POR voltage signal and the inverted POR voltage signal, respectively, and generating a level-shifted POR voltage signal; a buffer connected to the level-shifter for receiving the level-shifted POR voltage signal and providing a delayed level-shifted POR voltage signal; and a flip-flop having a data input terminal for receiving the first supply voltage, a clock input terminal connected to the buffer for receiving the delayed level-shifted POR voltage signal, a reset input terminal connected to the level-shifter for receiving the level-shifted POR voltage signal, and an output terminal for outputting a voltage-monitor signal.