Patent ID: 9524791
Filing Date: 2016-12-20
CPC Classification: G11C

Claim Text:
1. A data storage device comprising: a nonvolatile memory device including a memory cell array having one or more data cells and one or more flag cells, the flag cells being suitable for storing information denoting whether a most significant bit (MSB) data is programmed in the corresponding data cells; and a controller suitable for controlling the nonvolatile memory device to adjust a read voltage for the flag cells, in the case where recovery is made from a power failure to a normal state, wherein the controller controls the nonvolatile memory device to adjust the read voltage for the flag cells when a last programmed page at the power failure is an MSB page for storing the MSB data, and wherein the nonvolatile memory device adjusts the read voltage for the flag cells according to the control of the controller, and determines whether a program operation to the MSB page is completed based on data read from the flag cells using the adjusted read voltage for the flag cells.