Patent ID: 9379139
Filing Date: 2016-06-28
CPC Classification: G02F,H01L

Claim Text:
1. A display apparatus comprising: a thin film transistor substrate comprising a display area and a non-display area surrounding the display area, the display area comprising gate lines extending along a first direction and data lines extending along a second direction crossing the first direction and insulated from the gate lines; a gate driver at a first non-display area of the non-display area outside the display area along the second direction and configured to apply a gate signal to the gate lines; and a plurality of connection lines extending along the second direction and coupling the gate driver and the gate lines, wherein the plurality of connection lines comprises main connection lines and sub-connection lines, each of the gate lines being coupled to one of the main connection lines and one of the sub-connection lines, wherein a sum of resistance of an i-th main connection line (i being a positive integer number) of the main connection lines and an i-th sub connection line of the sub connection lines is substantially equal to a sum of resistance of a j-th main connection line (j being a positive integer number and j≠i) of the main connection lines and a j-th sub connection line of the sub connection lines, and wherein the i-th main connection line and the i-th sub connection line are coupled to a i-th gate line of the gate lines, and the j-th main connection line and the j-th sub connection line are coupled to an i-th gate line of the gate lines.