Patent ID: 9274993
Filing Date: 2016-03-01
CPC Classification: G06F

Claim Text:
1. An interface device for exchange of data between a first bus system and a second bus system, wherein an input/output device is connectable to the second bus system and the input/output device includes an addressable slot and an addressable subslot for outputting or accepting input/output data, the interface device comprising: a first transceiver device for data of the first bus system; a second transceiver device for data of the second bus system; a data transfer device including a transfer memory; a controller configured to control data storage and to coordinate write accesses in the data transfer device or at the data transfer device; a list storage device connected to the controller, the list storage device storing a data structure for addressing data for the input/output device, the data structure being predetermined for a plurality of subslots in a telegram format of telegrams of the first bus system, the list storage device including a memory offset related to a start address of the transfer memory and a data length of the input/output data, and each of the plurality of subslots in the data structure being assigned an index; wherein the control device is further configured to update the input/output data aided with by the index to coordinate the write accesses in the data transfer device byte-by-byte; wherein the transfer memory comprises a first transfer memory and a second transfer memory, the first and second transfer memories being connected to the control device such that a storage of data or a write access is implemented one of only to the first transfer memory and only to the second transfer memory; wherein the control device includes a blocking device configured to set the status indicator before a write access with output data to the output buffer or before a read access of input data to the input buffer; and wherein the control device is further configured such that the blocking device blocks a switch between the first transfer memory and the second transfer memory when the status indicator is set.