Patent ID: 9369308
Filing Date: 2016-06-14
CPC Classification: G06F,H04L

Claim Text:
1. A method of driving a signaling bus having a plurality of logical lanes, each logical lane physically adjacent to at least one other logical lane, each logical lane having an even signal path and an odd signal path, the method comprising: ensuring that a one cycle signal having a first transition direction transmitted on a first signal path in the signaling bus never encounters a one cycle signal having a second transition direction transmitted on an adjacent second signal path in the signaling bus; determining, for each logical lane, if a current data to be transmitted in each logical lane is different than an immediately previous data transmitted in the each logical lane; if different, then transmitting a one cycle signal having the first transition direction on the even signal path and transmitting a two cycle signal having the second transition direction on the odd signal path for even clock cycles, and transmitting a one cycle signal having the first transition direction on the odd signal path and transmitting a two cycle signal having the second transition direction on the even signal path for odd clock cycles; if not different, then not transmitting a one cycle signal having the first transition direction on either of the even signal path and the odd path.