Patent ID: 9229056
Filing Date: 2016-01-05
CPC Classification: G01R

Claim Text:
1. An integrated circuit die comprising: a bottom surface including bottom parallel test input signal contact points, bottom parallel test output signal contact points, a test clock in signal contact point, a test mode select in signal contact point, a test reset in signal contact point, a bottom test data in signal contact point, and a bottom test data out signal contact point; a top surface including top parallel test output signal contact points, top parallel test input signal contact points, a test clock out signal contact point, a test mode select out signal contact point, a test reset out signal contact point, a top test data out signal contact point, and a top test data in signal contact point; TAP lock circuitry having a test clock input coupled with the test clock signal contact point, a test mode select input coupled with the test mode select in signal contact point, a test reset input coupled with the test reset in signal contact point, a test clock output, and a test mode select output; test circuitry having a test clock input coupled to the test clock output of the TAP lock circuitry, a test mode select input coupled to the test mode select output of the TAP lock circuitry, an input coupled to the test reset in signal contact point, a test data input coupled to the bottom test data in signal contact point, and control outputs; and scan circuitry having an input coupled to the bottom test data in signal contact point, an output coupled to the bottom and top test data out signal contact points, and having control inputs coupled with the control outputs of the test circuitry.