Patent ID: 9319034
Filing Date: 2016-04-19
CPC Classification: H01L,H03K

Claim Text:
1. An integrated circuit, comprising: at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; a counter configured to generate a count value corresponding to the duration of the first pulse; a pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse; wherein the duration of the extended pulse is proportional to the duration of the first pulse; the at least one slew generator circuit includes an n-channel reference transistor and a p-channel reference transistor, each of the n-channel reference transistor and the p-channel transistor having a first threshold voltage setting; and the integrated circuit includes other circuits that include transistors fabricated with the same process as the n-channel and p-channel reference transistors, the other circuits having transistors wherein at least some transistors have a second threshold voltage setting.