Patent ID: 9407267
Filing Date: 2016-08-02
CPC Classification: G09G,H03K

Claim Text:
1. A liquid crystal display device, comprising: a pair of insulating substrates disposed so as to be opposed to each other with liquid crystal sandwiched therebetween, one of the pair of insulating substrates being a TFT substrate including a pixel region portion facing another of the pair of insulating substrates disposed in a region where pixels are arranged in matrix and a peripheral portion extending beyond the another of the pair of insulating substrates, the TFT substrate having a pixel arrangement structure formed on a surface of the pixel region portion thereof, the pixel arrangement structure including scanning wirings along respective rows of the pixels, video wirings along respective columns of the pixels, and thin film transistors provided for the respective pixels, the TFT substrate having a scanning line drive circuit for supplying a signal to the scanning wirings, a video line drive circuit for supplying a signal to the video wirings, and a level conversion circuit for supplying a rectangular wave to one of the scanning line drive circuit and the video line drive circuit formed on a surface of the peripheral portion thereof, the level conversion circuit being formed of transistors of a same channel conductivity type and is configured to carry out level conversion of an input signal as a rectangular wave between voltages supplied from a first power supply and a second power supply to generate an output signal having an amplified amplitude, the level conversion circuit comprising: a first level conversion portion configured to input the input signal from a first input node, generate an intermediate signal obtained by inverting the input signal, and to output the intermediate signal from a first output node; and a second level conversion portion configured to input the intermediate signal from a second input node connected to the first output node, generate the output signal obtained by inverting the intermediate signal, and to output the output signal from a second output node, wherein each of the first level conversion portion and the second level conversion portion comprises: wherein the load resistor of each of the first level conversion portion and the second level conversion portion comprises a bootstrap circuit including a fifth transistor, a sixth transistor, and a capacitor; a channel of the fifth transistor and a channel of the first transistor are connected in series, and a series connection of the fifth transistor and the first transistor is connected between the first power supply and the second power supply; a channel of the sixth transistor is connected between a gate of the fifth transistor and the second power supply; the capacitor is connected between a node between the first transistor and the fifth transistor and the gate of the fifth transistor; the bootstrap circuit generates voltage change of the control signal, which has an amplified amplitude with respect to an amplitude at the first or the second input node; and the level conversion circuit being formed together with the pixel arrangement structure in the pixel region portion in a step of forming the pixel arrangement structure.