Patent ID: 9401288
Filing Date: 2016-07-26
CPC Classification: H01L,Y10T

Claim Text:
1. A method for making an interconnection component, comprising the steps of: forming a redistribution layer on an in-process unit, the in-process unit including a first support portion having a plurality of openings extending from a first surface of the first support portion in a direction substantially perpendicular thereto, and the redistribution layer including routing circuitry in registration with the plurality of openings; joining a second support portion having first and second opposed major surfaces defining a thickness therebetween with the in-process unit such that the redistribution layer is disposed between the first and second support portions; and filling the first openings with a conductive material to form first conductive vias extending through the first support portion connected with the routing circuitry of the redistribution layer, and forming second conductive vias in the second support portion extending through the second support portion substantially perpendicular to the major surfaces and such that each of the second conductive vias has a first end and a second end, the first and second ends of the second conductive vias being substantially flush with the respective first and second surfaces of the second support portion, such that the first conductive vias extend through the first support portion and the second conductive vias extend through the second support portion, the first and second vias being electrically connected through the redistribution layer, wherein at least the second support portion is made from a semiconductor material, and wherein forming at least the second conductive vias includes forming holes in the second support portion defining a hole wall, depositing a dielectric lining along the hole wall, and filling the remainder of the hole with a conductive metal.