Patent ID: 9287109
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a layer of insulating material above a semiconductor substrate; forming a hard mask layer above said layer of insulating material; forming a blanket protection layer on said hard mask layer; forming a masking layer above said blanket protection layer; performing at least one etching process on said masking layer to form a patterned masking layer having an opening that stops on and exposes an upper surface portion of said blanket protection layer without exposing said underlying hard mask layer; while said blanket protection layer is covering said hard mask layer, confirming that said patterned masking layer is properly positioned relative to at least one underlying structure or layer; after confirming that said patterned masking layer is properly positioned, performing at least one etching process through said patterned masking layer to pattern said blanket protection layer and said underlying hard mask layer, said patterned hard mask layer exposing an upper surface portion of said layer of insulating material; removing said patterned blanket protection layer, and after removing said patterned blanket protection layer, forming one of a trench and an opening in said layer of insulating material through said patterned hard mask layer.