Patent ID: 9262293
Filing Date: 2016-02-16
CPC Classification: G01R,G06F

Claim Text:
1. An integrated circuit (IC) comprising: a plurality of hardware sectors, each hardware sector associated with a debug observability circuit that is served by a debug data bus of a debug circuit, wherein the plurality of hardware sectors includes one or more steady state sectors residing in an always on power domain that remains on whenever the debug circuit is operable; the plurality of hardware sectors including a controlled sector residing in a dynamically-controlled power domain that may be turned off while the power domain of another sector remains on; a debug data register configured to provide data to the debug observability circuit of the controlled sector via the debug data bus; a shadow register configured to receive and store the data provided to the debug observability circuit of the controlled sector; and control circuitry configured to utilize the data stored in the shadow register upon a restoration of power to the controlled sector to restore the debug observability circuit associated with the controlled sector to a state reflective of its state when the controlled sector was previously powered on.