Patent ID: 9257289
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a gate cavity laterally surrounded by a planarization dielectric material layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity; forming a U-shaped high-k gate dielectric layer having a dielectric constant greater than 3.9, a U-shaped metal cap layer and a sacrificial cap layer in said gate cavity; implanting ions into vertical portions of said U-shaped sacrificial cap layer to damage at least part of said vertical portions of said U-shaped sacrificial cap layer; removing said damaged portions of said U-shaped sacrificial cap layer to expose portions of said U-shaped metal cap layer located directly beneath said damaged portions of said U-shaped sacrificial cap layer; removing said exposed portions of said U-shaped metal cap layer to expose portions of said U-shaped high-k gate dielectric layer located directly beneath said exposed portions of said U-shaped metal cap layer; removing said exposed portions of said U-shaped high-k gate dielectric layer; and removing a remaining portion of said sacrificial cap layer.