Patent ID: 9354690
Filing Date: 2016-05-31
CPC Classification: G06F,Y02D

Claim Text:
1. A system for adjusting a core voltage of an integrated circuit, comprising: a ring oscillator on the integrated circuit for providing a ring oscillator signal; a clock external to the integrated circuit for providing a clock signal to control timing of circuitry on the integrated circuit; and compare logic on the integrated circuit configured to receive and compare the ring oscillator signal and the clock signal, the compare logic further configured to transmit a control signal for adjusting the core voltage based on a comparison of the ring oscillator signal and the clock signal, thereby adjusting a speed of the circuitry on the integrated circuit, such that a delay of a path of the ring oscillator is less than a period of the clock signal, wherein the delay of the path of the ring oscillator is at least as long as each other delay of a data path within the integrated circuit, and wherein by keeping the delay of the path of the ring oscillator less than the period of the clock signal, the compare logic is configured to ensure that timing errors associated with fluctuations in a speed of signal transitions within the integrated circuit are prevented.