Patent ID: 9379072
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A chip package, comprising: a first substrate, wherein a plurality of first conductive pads are disposed on a first side of the first substrate; a second substrate attached onto a second side opposite to the first side of the first substrate, wherein the second substrate comprises a micro-electric element, a dam and a plurality of second conductive pads corresponding to the plurality of first conductive pads, and wherein the plurality of second conductive pads are disposed on a first side of the second substrate and between the first substrate and the second substrate; an opening penetrating the second substrate, the plurality of second conductive pads and the first substrate to extend into the plurality of first conductive pads; a redistribution layer disposed on a second side opposite to the first side of the second substrate, wherein the redistribution layer penetrates the second substrate, the plurality of second conductive pads and the first substrate and extends into the plurality of first conductive pads to electrically connect the plurality of first conductive pads and the plurality of second conductive pads, wherein the redistribution layer is formed on sidewalls and a bottom of the opening, without completely filling the opening and without extending into the dam; and an insulating layer disposed on the second side of the second substrate to cover the redistribution layer, wherein the insulating layer penetrates the second substrate, the plurality of second conductive pads and the first substrate to extend into the plurality of first conductive pads, wherein the insulating layer further extends to penetrate the plurality of first conductive pads.