Patent ID: 9384313
Filing Date: 2016-07-05
CPC Classification: G06F

Claim Text:
1. A method to debug a RTL design in an FPGA-based emulation or co-emulation system, the method comprising the steps of: a. instrumenting the RTL design by inserting at least one dummy module for correlating a set of signals of the RTL design to corresponding gate-level signals; b. synthesizing the instrumented RTL design to generate a gate-level net-list targeting for the emulation or co-emulation system; c. fitting the gate-level net-list into the FPGA devices in the emulation or co-emulation system and generating location information of instances of the gate-level net-list in the FPGA devices; and d. extracting values of gate-level signals corresponding to the set of signals of the RTL design in an emulation or co-emulation run according to the location information of the instances that output the gate-level signals in the emulation or co-emulation system.