Patent ID: 9525831
Filing Date: 2016-12-20
CPC Classification: H03K,H04N

Claim Text:
1. A capacitor averaging comparator for comparing electrical signals from a plurality of pixels, each electrical signal having a signal voltage comprising: a plurality of signal switches, each signal switch corresponding to one of said electrical signals; a buffer amplifier connected to said signal switches; a first capacitor; a first capacitor switch connected between said buffer amplifier and said first capacitor; a second capacitor; a second capacitor switch connected between said first capacitor and said second capacitor; and a latching comparator connected to said second capacitor controlled by a comparator control voltage; a clock operably connected to said pixels to read said electrical signals at a clock rate having an integration time and a reset time; wherein when said signal switches are sequentially closed, each of said electrical signals is sequentially sent to said buffer amplifier, said first capacitor switch is closed, said buffer amplifier drives said first capacitor to store a first stored voltage that is proportional to said signal voltage, said first capacitor switch opens, said second capacitor switch closes and charge is transferred between said first and second capacitors, causing any prior stored voltage on said second capacitor and said first stored voltage on said first capacitor to form a weighted average voltage, and said comparator compares said weighted average voltage to said comparator control voltage; wherein said weighted average voltage is based on the ratio of capacitance between said first capacitor and said second capacitor, and wherein if any of said weighted average voltage for a preset number of pixels exceeds said comparator control voltage, then said latching comparator latches to a high value indicating said preset number of pixels are saturated; wherein if said weighted average voltage indicates that said preset number of pixels are saturated, said clock changes said clock rate to have a changed integration time and a changed reset time, wherein said changed integration time is less than said integration time and said changed reset time is greater than said reset time, and wherein if said weighted average voltage indicates that less than said preset number of pixels are unsaturated, said clock maintains said integration time and said reset time; wherein if said weighted average voltage indicates that a preset number of pixels are saturated while using said changed integration time and said changed reset time, said clock changes said clock rate to have a re-changed integration time and a re-changed reset time, wherein said re-changed integration time is shorter than said changed integration time and said re-changed reset time is longer than said changed reset time, and wherein if said weighted average voltage indicates that less than said preset number of pixels are unsaturated while using said changed integration time and said changed reset time, said clock rate will remain at said changed integration time and said changed reset time; whereby the reading of said electrical signals at said changed integration time and said re-changed integration time, extends dynamic range of said plurality of pixels.