Patent ID: 9412942
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method of forming a resistive memory cell, comprising: forming a plurality of bottom electrode connections; depositing a bottom electrode layer over the bottom electrode connections; performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface; forming an oxidation layer on each sloped surface of the remaining bottom electrode layer; performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip; removing the oxidation layer on each sloped surface; and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.