Patent ID: 9337126
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. An integrated circuit, comprising: a first substrate having at least one active device and a plurality of first metallic pads electrically connected to the active device, wherein the first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers; a second substrate having a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has a plurality of second metallic pads, wherein the second substrate does not include any active devices; and a plurality of bump pads sandwiched by the first substrate and the second substrate, wherein the active device and the first metallic pads of the first substrate are electrically connected to the second metallic pads of the second substrate through the bump pads.