Patent ID: 9362385
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method for tuning a threshold voltage of a semiconductor device with a metal gate structure, comprising: forming a high-k dielectric layer in a gate trench; forming an etch stop over the high-k dielectric layer; forming a work function adjusting layer over the etch stop by forming a tri-layer with a sequence of a grain boundary engineering layer configured to allow a dopant atom to penetrate there through, a doping layer configured to provide the dopant atom to the grain boundary engineering layer, and a capping layer configured to prevent the doping layer from oxidation; and filling a metal in the gate trench, wherein a degree of penetration of the dopant atom is controlled by adjusting a growth temperature within a range of from about 200 to about 350 degrees Celsius during forming the grain boundary engineering layer.