Patent ID: 9418190
Filing Date: 2016-08-16
CPC Classification: G06F,H04B,H04L

Claim Text:
1. A system to route connections of sub-networks in a design of an integrated circuit, the system comprising: a memory device configured to store instructions to route the connections of the sub-networks; and a processor configured to execute the instructions to determine a baseline route for each of the connections of each of the sub-networks, identify noise critical sub-networks in the integrated circuit design based on congestion, set a mean threshold length (MTL), segment the connections of the noise critical sub-networks based on the MTL, and re-route the baseline route based on segmenting, wherein the MTL indicates a maximum length of each segment of each connection, each segment includes a wirecode which is different from a wirecode of an adjacent segment, and each wirecode defines a width, a metal layer, and a spacing for each segment.