Patent ID: 9257282
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising: forming a dielectric layer over a substrate; forming an interlayer over the dielectric layer; forming a first photoresist (PR) layer over the dielectric layer; forming a second PR layer over the first PR layer; patterning the first and second PR layers to form a first opening in the second PR layer and a second opening in the first PR layer, wherein patterning the first and second PR layers includes performing a single exposure process to the first and second PR layers to form a first latent feature and a second latent feature in the first and second PR layers, respectively, and performing a development process to form the first and second openings by removing the second and first latent features, respectively; forming spacers along opposing sidewalls of the second opening; performing a first etching process to the interlayer to form a first trench extending through the first etched interlayer while using the spacers along the second opening as an etch mask, the first trench having a first width; performing a second etching process to the first etched interlayer to form a second trench extending through the second etched interlayer and into the dielectric layer; and performing a third etching process to the second etched interlayer to form a third trench in the dielectric layer that includes an upper portion having a second width and a lower portion having the first width that is different than the second width.