Patent ID: 9460797
Filing Date: 2016-10-04
CPC Classification: G11C,H01L,H02M

Claim Text:
1. A non-volatile memory cell structure, comprising: a substrate; a first well, disposed on the substrate; a second well, disposed on the substrate; a third well, disposed on the substrate; at least one first transistor, forming on the first well and having a first end coupled to a source line signal; a second transistor, forming on the second well, and having a first end coupled to a second end of the first transistor; and a third transistor, forming on the third well, and having a first end coupled to a second end of the second transistor, a second end coupled to a bit line signal, wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to a word line signal or a Y-decoding signal, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.