Patent ID: 9444509
Filing Date: 2016-09-13
CPC Classification: G06F,H04B

Claim Text:
1. An apparatus, comprising: a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits is to transmit data during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data during a second operational state; a first set of single-ended receiver circuits on a second die; a first plurality of conductive lines between the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched; a second set of single-ended receiver circuits on the first die; a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits is to transmit data during a third operational state and a subset of the second set of single-ended transmitter circuits is to transmit data during a fourth operational state; and wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist and wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width.