Patent ID: 9401312
Filing Date: 2016-07-26
CPC Classification: H01L,H03K

Claim Text:
1. A method comprising: forming a through silicon via (TSV) array between a bottom die and a top die of a three-dimensional (3D) integrated circuit (IC) stack, the TSV array having a row and a column of redundant TSVs, wherein each TSV in the TSV array is connected to a 2:4 Decoder in the bottom die and a 4:2 Priority Encoder in the top die; identifying a defective TSV of the TSV array; determining whether to shift a signal bit associated with or corresponding to the defective TSV in a first and/or a second direction towards the row or the column of redundant TSVs; and shifting the signal bit in the first and/or the second direction until the signal bit has been redirected to the row or the column of redundant TSVs.