Patent ID: 9299798
Filing Date: 2016-03-29
CPC Classification: G11C,H01L

Claim Text:
1. A method of forming a device comprising: providing a substrate prepared with at least a first transistor and a second transistor, each of the first and second transistors having a gate disposed on the substrate between first and second heavily doped source/drain (S/D) regions in the substrate, wherein the heavily doped S/D regions are disposed adjacent to first and second sides of the gate and partially underlaps the gate; forming a silicide block layer on the substrate, wherein the silicide block layer covers and in direct contact with the first and second sides and top surface of the gate and the first and second heavily doped S/D regions; patterning the silicide block layer to expose portions of the first and second heavily doped S/D regions of the first and second transistors; forming silicide contacts in the exposed portions of the first and second heavily doped S/D regions, wherein the patterned silicide block layer is in direct contact with sides and top surface of the gates when the silicide contacts are formed and the silicide contacts are displaced from the sides of the gates and sides of the first and second heavily doped S/D regions of the first and second transistors; forming a contact dielectric layer covering the at least first and second transistors: and forming contacts in the contact dielectric layer, wherein the contacts are in communication with the silicide contacts in the heavily doped S/D regions.