Patent ID: 9417927
Filing Date: 2016-08-16
CPC Classification: G06F

Claim Text:
1. A method for simultaneous multithreading (SMT) by a computer, the method comprising: managing, by an operating system or a second-level hypervisor of the computer, a logical core configuration for simultaneous multithreading, the operating system or the second-level hypervisor having control over a logical core and control over logical threads on the logical core; configuring, by the operating system or the second-level hypervisor of the computer, a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core; running the logical core on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core; determining core cycles operating at a thread density of 1 (C_ determining core instructions complete at the thread density of 1 (I_ determining core cycles operating at a thread density of 2 (C_ determining core instructions complete at the thread density of 2 (I_ wherein each physical core comprises one or more counters for determining core cycles operating at a thread density of 1 (C_ wherein for every clock cycle, a number of non-waiting threads on the physical core determines whether the one or more counters for determining core cycles operating at the thread density of 1 (C_ wherein for every completed instruction, the number of non-waiting threads on the physical core determines whether the one or more counters for determining core instructions complete at the thread density of 1 (I_