Patent ID: 9479193
Filing Date: 2016-10-25
CPC Classification: H03M

Claim Text:
1. An apparatus for performing a compression operation in a hash algorithm, comprising: one or more central processing units (CPUs) and one or more memory containing instructions to perform the following: receiving a message including 1024- or 2048-bit message (M=M[0]∥M[1]∥ . . . ∥M[31]) in which 32 32- or 64-bit sub messages (M[0], M[1], . . . , M[31]) are successively connected to each other, and chain variable data including 512- or 1024-bit chain variable data from an outside; receiving the message and generating 27 512- or 1024-bit extended messages (W_r=r[0]∥W_r[1]∥ . . . ∥W_r[15], 0≦r≦26) in each of which 16 32- or 64-bit sub extended messages (W_r[0], W_r[1], . . . , W_r[15]) are successively connected to each other from the message; converting the chain variable data into initial state data for a compression function; repeatedly computing extended message binding and step functions based on the initial state data and the plurality of extended messages, and performing combination with a final extended message, thereby computing final state data; and generating and outputting chain variable data, into which the chain variable data has been updated, using the final state data, wherein generating the extended messages based on the following equation: