Patent ID: 9298546
Filing Date: 2016-03-29
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A semiconductor memory device comprising: a memory chip; a first encoder/decoder (E/D) section configured to obtain a first error check code based on original data and a first error correction code based on the original data and the first error check code, the first error check code and the first error correction code being recorded on a first page of the memory chip; and a second encoder/decoder (E/D) section configured to obtain a second error check code and a third error correction code, the third error correction code being based on the second error check code and a redundant code generated from the original data, the second error check code being based on the redundant code, the second error check code and the third error correction code being recorded on a second page of the memory chip.