Patent ID: 9349654
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of forming a device comprising: providing a substrate prepared with isolation regions, wherein the substrate comprises at least first, second and third regions, the first region comprises a memory region, the second region comprises a high voltage (HV) region and the third region comprises a logic region; forming an additional dielectric layer in direct contact with the substrate and the isolation regions; selectively processing a first select region while protecting first non-select regions, wherein the first select region is one of the first, second and third regions, and wherein selectively processing the first select region comprises performing a removal process to remove the additional dielectric layer over the first select region and to reduce a height of the isolation regions in the first select region; and forming a first gate dielectric on the select region, wherein top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.