Patent ID: 9506981
Filing Date: 2016-11-29
CPC Classification: G01R,G06F,H03K

Claim Text:
1. A circuit configuration for detecting external manipulation of a clock in an integrated circuit comprising digital units and at least one clock detector monitoring frequency and duty cycle parameters of a clock signal, where in case of a deviation of either frequency or of a duty cycle parameter an alarm signal is generated at an output of said at least one clock detector, said configuration comprising: an arrangement of a plurality of clock detectors at critical points of the integrated circuit, said critical points being integrated in at least one portion of a digital unit of a digital block, which is clocked by a clock signal from an analog block, wherein the plurality of clock detectors are concealed in a digital block as standard cells, which each comprise a set of transistors interconnected together to implement a Boolean or a storage logic function in said integrated circuit.