Patent ID: 9397824
Filing Date: 2016-07-19
CPC Classification: H04L

Claim Text:
1. A method for providing clock data recovery (CDR) in a receiver, the method comprising: receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire a frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation of the CDR module; receiving at the NRZ-based PFD a first signal that comprises the received PAM signal after amplification and equalization using a continuous time linear filter; receiving at the PAM PD a second signal that comprises the first signal summed with a correction provided by a Decision Feedback Equalizer (DFE); and receiving at the PAM PD a third signal that comprises PAM data output from the DFE.