Patent ID: 9459318
Filing Date: 2016-10-04
CPC Classification: G01R,H01L

Claim Text:
1. A semiconductor chip comprising: an input pad and an output pad formed on the semiconductor chip; at least one bump formed on the semiconductor chip; and a test scan chain including: a plurality of drive buffers selectively driven by a selection signal; and a plurality of storage units electrically coupled in series, configured to store data received from the input pad and output the stored data to the output pad in response to a control clock, wherein each of the plurality of drive buffers includes: an input buffer configured to receive data from a node coupled to the bump and provide the received data to a corresponding storage unit; and an output buffer configured to be selectively driven by the select signal, and output the data of the corresponding storage unit to the node, and each of the plurality of drive buffers outputs the data stored in the plurality of storage units to the node when the output buffer is turned on, and floats the node for a predetermined time when the output buffer is turned off.