Patent ID: 9461143
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A semiconductor structure, comprising: a substrate comprising an active region and an isolation region; a plurality of gate structures, each having a portion disposed above the active region and a portion disposed above the isolation region of the substrate, wherein each of the plurality of gate structures comprises a gate cap dielectric layer on a top surface of the gate structure, the gate cap dielectric layer having an uppermost surface, wherein the gate cap dielectric layer comprises a first material; a plurality of source or drain regions disposed in the active region of the substrate, between the portion of each of the gate structures disposed above the active region; a plurality of trench contacts, each one of the plurality of trench contacts disposed on a corresponding one of the plurality of source or drain regions, wherein each of the plurality of trench contacts comprises a trench cap dielectric layer on a top surface of the trench contact, the trench cap dielectric layer having an uppermost surface co-planar with the uppermost surface of the gate cap dielectric layer of each of the plurality of gate structures, wherein the trench cap dielectric layer comprises a second material different than the first material; a gate contact via disposed on one of the plurality of gate structures, on the portion of the one of the plurality of gate structures disposed above the active region of the substrate; and a trench contact via disposed on one of the plurality of trench contacts.