Patent ID: 9436845
Filing Date: 2016-09-06
CPC Classification: G06F,G09C,G11C,H04L

Claim Text:
1. A method for providing an unclonable identifying chip comprising: forming a memory array consisting of memory cells arranged in a matrix, each of the memory cells having one NMOS transistor, wherein the NMOS transistors in each row are coupled to a wordline, and the NMOS transistors in each column are coupled to a bitline and to a source line, the source line having a voltage (VDD); activating the wordline and forcing the bitline to a predetermined voltage, the predetermined voltage being lower than the voltage VDD, wherein a threshold voltage of the NMOS transistor of the memory cell is increased by providing the NMOS transistor with a charge trapping in response to applying an elevated wordline voltage to the activated wordline, and providing a voltage higher than the voltage VDD to the source line and forcing a corresponding bitline to ground (GND) during the activation of the wordline; floating the bitline followed by precharging the bitline through the NMOS transistor coupled to the activated wordline; and sensing the bitline voltage, wherein random binary strings are generated by sensing results of the bitline voltage.