Patent ID: 9367248
Filing Date: 2016-06-14
CPC Classification: G06F,G11C,H01L,H04L

Claim Text:
1. A controller to control operations of a memory component, the controller comprising; a first circuit to transmit commands to the memory component, the commands including a read command that specifies data to be accessed from a memory core of the memory component; a second circuit to receive data sent by the memory component via an external bus, the data sent by the memory component in response to the read command; calibration circuitry, operable during calibration, to receive at least a first data pattern and a second data pattern from the memory component, the first data pattern and the second data pattern being provided from pattern register circuitry in the memory component, wherein, during the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the memory component onto the external bus in response to one of the commands.