Patent ID: 9514054
Filing Date: 2016-12-06
CPC Classification: G06F

Claim Text:
1. A method comprising: receiving a first write request directed to a first logical unit (LUN) connected to a server having a memory, the first write request having data, a first offset and a first length representing a first address range; matching the first address range to a first entry of an in-core metadata array, each entry of the metadata array indexing a cache block on a second LUN, the cache block on the second LUN copied from the first LUN, the second LUN connected to the server; storing on the second LUN a cache metadata block entry of a persistent cache, the cache metadata block entry having a number of accesses of the cache block, the cache metadata block entry indexing the cache block on the second LUN; invalidating the matching first entry of the in-core metadata array; and storing on the second LUN a first invalidate block entry of the persistent cache, the first invalidate block entry indexing the cache block on the second LUN, the first invalidate block entry invalidating the cache metadata block entry.