Patent ID: 9362287
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first transistor and a second transistor disposed in or on a silicon substrate; a first well disposed in a formation area of the first transistor, and a second well disposed in a formation area of the second transistor, wherein the second well surrounds the first well in a plan view of the silicon substrate; and a third well disposed under an entirety of the first well, but less than an entirety of the second well, and wherein the third well is electrically connected to the second well, wherein the semiconductor device does not include an element isolation structure including an element isolation film disposed in the silicon substrate between the first transistor and the second transistor, and wherein the first transistor is an N-type transistor, the second transistor is a P-type transistor, the first well is a P-well, the second well is an N-well, and the third well is an N-well.