Patent ID: 9355914
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A method comprising: providing a substrate having a surface that supports a plurality of fins comprised of Group IVA-based crystalline semiconductor material, the plurality of fins being spaced apart and generally parallel to one another; forming sacrificial gate structures on and orthogonal to the plurality of fins; for a first sub-set of the plurality of fins, forming PFET source/drains and performing a PFET source/drain anneal at a first temperature; for a second sub-set of the plurality of fins, forming an amorphized portion of the fins between two adjacent sacrificial gate structures; forming a dielectric layer that covers the fins between the sacrificial gate structures; removing the sacrificial gate structures and removing those portions of the second sub-set of fins that are exposed by the removal of the sacrificial gate structures; etching the amorphized portion of the fins to form a void bounded on two sides by Group IVA-based crystalline semiconductor material; growing from the two sides a nanowire, the nanowire being disposed laterally to the surface of the substrate and bridging the void; forming metal gate structures where the sacrificial gate structures were removed; removing the dielectric layer covering the second sub-set of fins; and forming over portions of the nanowire NFET source/drains and performing an NFET source/drain anneal at a second temperature, where the NFET source/drains are separated by a portion of the nanowire that underlies a metal gate structure.