Patent ID: 9406375
Filing Date: 2016-08-02
CPC Classification: G11C

Claim Text:
1. A memory array comprising: at least a first and a second six transistor static random access memory cell; and a first and a second address decoder, the first address decoder being electrically conductive connected to a first access transistor of each of the at least two memory cells via one or more first wordlines, the second address decoder being electrically conductive connected to a second access transistor of each of the at least two memory cells via one or more second wordlines, the first address decoder comprising at least a first latch, the second address decoder comprising at least a second latch, the first latch comprising a first and a second data input, the first latch being configured to selectively capture data from the first or the second data input, the respective first data input being electrically conductive connected to a first address data path for providing first address data, the respective second data input being electrically conductive connectable by a first multiplexer to a second address data path for providing second address data, the second latch comprising a first data input electrically conductive connected to the second address data path, and the first multiplexer and the at least two latches being configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array, in the first write mode the second data input of the first latch being electrically conductive connected to the second address data path by the first multiplexer, second address data being captured by the first latch from its second data input and by the second latch from its first data input, in the read mode first address data being captured by the first latch from its first data input and second address data being captured by the second latch from its first data input.