Patent ID: 9471088
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A processor comprising: a power controller to perform power management for the processor, the power controller to generate a restriction command responsive to a determination that at least one core of the processor is in operation within a threshold of a processor constraint and send the restriction command to the at least one core; and the at least one core to execute instructions, the at least one core including a plurality of units and a clock generation logic to receive and distribute a first clock signal to the plurality of units of the at least one core, a restriction logic to receive the restriction command and responsive to the restriction command to dynamically cause the clock generation logic to reduce delivery of the first clock signal to at least one of the plurality of units while the first clock signal is delivered to at least one other of the plurality of units of the at least one core without restriction, wherein the reduced delivery of the first clock signal is at a lower frequency than a frequency of the first clock signal, the at least one core further including a clock crossing logic to couple the at least one core to a system agent logic of the processor, wherein the clock crossing logic is to operate at the first clock signal without restriction, and a buffer coupled to the clock crossing logic, the buffer to be written according to the first clock signal with the reduced delivery and to be read according to the first clock signal without restriction.