Patent ID: 9230969
Filing Date: 2016-01-05
CPC Classification: H01L,Y10S

Claim Text:
1. A semiconductor device having a static random access memory cell, the device comprising: a plurality of element formation regions each defined on a main surface of a semiconductor substrate; access transistors including a first access transistor and a second access transistor, driver transistors including a first driver transistor and a second driver transistor, and load transistors including a first load transistor and a second load transistor, each formed in a prescribed element formation region of the element formation regions; a plurality of contact plugs formed so as to be electrically coupled to prescribed parts of the access transistors, the driver transistors, and the load transistors respectively; a plurality of first wirings each formed so as to be electrically coupled to a prescribed contact plug among the contact plugs; a plurality of first vias each formed so as to be electrically coupled to a prescribed contact plug among the contact plugs; a plurality of second wirings, each formed so as to be electrically coupled to a prescribed first via among the first vias, including a first bit line and a second bit line for inputting and outputting data and a voltage supply wiring; and a plurality of third wirings, each formed above and spaced from the second wirings so as to be electrically coupled to a prescribed second wiring among the second wirings, including a word line and a grounding wiring, wherein the first access transistor is electrically coupled between a first storage node for storing data and the first bit line, and the second access transistor is electrically coupled between a second storage node for storing data and the second bit line; wherein a gate of the first access transistor and a gate of the second access transistor are electrically coupled to the word line; wherein the first driver transistor is electrically coupled between the first storage node and the grounding wiring and the second driver transistor is electrically coupled between the second storage node and the grounding wiring; wherein the first load transistor is electrically coupled between the first storage node and the voltage supply wiring and the second load transistor is electrically coupled between the second storage node and the voltage supply wiring; and wherein among the contact plugs, at least one of a first contact plug located on a side of each of the access transistors for coupling to the bit line and a second contact plug located on a side of each of the load transistors for coupling to the voltage supply wiring and among the first vias, a first via first part for electrically coupling either the first contact plug or the second contact plug to a prescribed second wiring first part among the second wirings are electrically coupled so that the first via first part is in direct contact with either the first contact plug or the second contact plug.