Patent ID: 9317644
Filing Date: 2016-04-19
CPC Classification: G06F,H05K

Claim Text:
1. A computer-implemented method to simulate an electronic design layout comprising: retrieving an electronic design layout that identifies a plurality of signal conductors and a plurality of metal fills; positioning, by one or more processing devices, metal fill grid points on one or more of the plurality of metal fills; selecting one of the plurality of metal fills to establish a selected metal fill; assigning a metal fill surface potential variable to at least one of the metal fill grid points; generating, by the one or more of the processing devices, a zero charge equation for the selected metal fill, wherein the equation relates the metal fill surface potential variable to neighboring metal fill grid points around a metal fill boundary of the selected metal fill; generating, by the one or more of the processing devices, one or more capacitance values corresponding to one or more of the plurality of signal conductors using the zero charge equation; and simulating, by the one or more of the processing devices, the electronic design layout using the generated one or more capacitance values.