Patent ID: 9507939
Filing Date: 2016-11-29
CPC Classification: G06F

Claim Text:
1. A computer system comprising a first hardware processor, a first memory, a memory shadower, and an interrupt generator, wherein the memory shadower comprises a second memory and logic configured to take snapshots of the first memory, wherein each snapshot comprises a current content of a memory section of the first memory, wherein taking snapshots comprises copying the current content from the first memory to the second memory, wherein the computer system is configured to: employ the first hardware processor to execute a batch of code samples loaded into the first memory, the batch selected from a corpus prior to loading the batch into the first memory, wherein selecting the batch comprises: employ the interrupt generator to inject a hardware interrupt into the first hardware processor, the hardware interrupt causing the computer system to transition into a sleeping state, wherein the sleeping state is a state wherein the first hardware processor is not executing instructions and the first memory is powered; in response to the computer system transitioning into the sleeping state, employ the memory shadower to take a first snapshot of the first memory; and in response to taking the first snapshot, employ the memory shadower to transmit at least a part of the first snapshot to a second hardware processor, wherein the second hardware processor is configured to: