Patent ID: 9411730
Filing Date: 2016-08-09
CPC Classification: G06F

Claim Text:
1. A method for memory coherence in a multiple processor system, the method comprising: responsive to a memory operation from a processing core in a first processing node of the multiple processor system resulting in a cache miss, checking a private region table associated with the processing core, wherein the memory operation attempts to access a memory region stored in memory of a second processing node of the multiple processor system; responsive to determining the memory region corresponds to an entry in the private region table and the memory region is node-contained in the second processing node, performing the memory operation on the second processing node without snooping the entire multiple processor system, wherein the multiple processor system comprises a plurality of nodes, each node comprises a plurality of chips, each chip comprises a plurality of chiplets, and each chiplet comprises a processing core and a cache associated with the processing core, and wherein the private region table comprises a chiplet-level private region table and a chip-level private region table; and responsive to the chiplet-level private region table running out of space, moving a selected entry in the chiplet-level private region table to the chip-level private region table and adding a chiplet identifier to the selected entry.