Patent ID: 9431499
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: providing a heterostructure body with a first doped region, a second doped region spaced apart from the first doped region and a two-dimensional charge carrier gas channel between the first and second doped regions; and forming a gate structure on the heterostructure body for controlling the channel, the gate structure comprising a piezoelectric material and an electrical conductor in contact with the piezoelectric material, wherein the heterostructure body has a built-in stress induced by lattice mismatch between different layers of the heterostructure body, and wherein the piezoelectric material is formed on the heterostructure body with an orientation that counteracts the built-in stress in the heterostructure body so that the channel is disrupted below the piezoelectric material absent a voltage applied to the piezoelectric material.