Patent ID: 9312198
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A chip package, comprising: a first substrate; a first chip arranged over the first substrate; a second substrate arranged over the first chip on a top side of the first chip facing away from the first substrate, wherein the second substrate comprises one or more contacts and at least one electrically conductive line coupled to at least one of the one or more contacts, wherein the second substrate includes an overhanging lateral dimension section extending beyond a lateral dimension of the first chip; and a first encapsulation material at least partially embedding a second chip; a second encapsulation material at least partially encapsulating the first encapsulation material, the second chip, the second substrate and the first chip; one or more contact holes, each substantially vertically extending through the encapsulation material to electrically couple to at least one of the one or more contacts of the second substrate in the overhanging lateral dimension section of the second substrate; and wherein the second chip is arranged over and electrically connected to the second substrate at a non-overhanging lateral dimension so as to be in electrical connection with at least one of the one or more contact holes wherein a surface of the first chip facing the second chip is attached to and is electrically connected to a surface of the second substrate facing away from the second chip.