Patent ID: 9367309
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A processor comprising: a register attribute tracker configured to receive instruction operations corresponding to an instruction stream, and in response to receiving a first vector instruction operation that explicitly defines a vector attribute for a vector operated upon by the processor in response to executing the first vector instruction operation, the register attribute tracker is configured to track the vector attribute with respect to an output register of the first vector instruction operation; and wherein the register attribute tracker is configured to receive a second vector instruction operation that does not explicitly define the vector attribute, wherein the second vector instruction operation has the output register of the first vector instruction operation as an input register, and wherein the second vector instruction operation has a second output register, and wherein the register attribute tracker is configured to track a second vector attribute of the second output register responsive to the tracked vector attribute associated with the input register.