Patent ID: 9397081
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A fabrication method of a semiconductor package, comprising the steps of: providing a carrier having opposite first and second surfaces; forming at least an opening on the first surface of the carrier, wherein the opening has a bottom portion; forming a plurality of conductive traces on the first surface of the carrier, and the bottom portion and side walls of the opening; disposing a first semiconductor element in the opening, wherein the first semiconductor element has a first active surface with a plurality of first electrode pads and a first inactive surface opposite to the first active surface, and the first active surface faces the bottom portion of the opening so as for the first electrode pads to be electrically connected to the conductive traces; disposing a second semiconductor element on the first semiconductor element, wherein the second semiconductor element has a second active surface with a plurality of second electrode pads which are exposed from the opening, and a second inactive surface, opposite to the second active surface, attached to the first inactive surface of the first semiconductor element; and forming a redistribution layer structure on the first surface of the carrier and the second active surface of the second semiconductor element for being electrically connected to the conductive traces and the second electrode pads on the second active surface of the second semiconductor element.