Patent ID: 9306162
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method for fabricating a memory cell, the method comprising: etching a contact via into a dielectric layer; depositing a conductive material into the contact via, thereby forming a bulk plug in the contact via; removing a portion of the conductive material from the contact via to form a recess, wherein the recess has a width greater than or equal to a height of the recess; depositing an interface cap material in the recess to form an interface cap above the bulk plug, wherein the interface cap material rows planar from a bottom portion of the recess to a top portion of the recess and prevents formation of a keyhole in a center of the contact via, and the interface cap material includes a material having a resistivity that is less than a resistivity of the conductive material forming the bulk plug; and depositing active cell material on the interface cap, wherein the interface cap separates the active cell material and the conductive material in the contact via.