Patent ID: 9482719
Filing Date: 2016-11-01
CPC Classification: G01R

Claim Text:
1. A system for interfacing with a design under test (DUT), comprising: an on-chip clock controller (OCC) circuit configured to receive a test pattern and responsively generate one or more clock pulses in response to the test pattern; an OCC test circuit coupled to the OCC circuit and configured to detect the one or more clock pulses generated by the OCC circuit and generate corresponding OCC test outputs; a clipping test circuit configured to capture outputs generated by a plurality of pulse-width critical flip-flops of the DUT and generate corresponding pulse-width debug outputs; a test output logic circuit configured to receive the OCC test outputs and the pulse-width debug outputs; and a debug controller operable to configure the test output logic circuit to selectively map the OCC test outputs and the pulse-width debug outputs to a test output.