Patent ID: 9293576
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A semiconductor device fabrication process comprising: forming at least one gate upon a semiconductor substrate; forming a first gate cap upon the gate; forming a first interlayer dielectric layer upon the semiconductor substrate so that an upper surface of the first interlayer dielectric layer is coplanar with an upper surface of the first gate cap; forming a sacrificial gate cap upon the first gate cap; forming a second interlayer dielectric layer upon the first interlayer dielectric layer surrounding the sacrificial gate cap; forming a contact trench self aligned to the gate; forming a self-aligned contact by filling the contact trench with electrically conductive material, and; subsequent to forming the self aligned contact trench and prior to forming the self-aligned contact, forming a low-k gate cap upon the first gate cap, wherein the low-k gate cap is formed from a low-k material comprising a dielectric constant less than seven.