Patent ID: 9529547
Filing Date: 2016-12-27
CPC Classification: G06F

Claim Text:
1. A memory device comprising a memory controller; and a homogeneous memory accessible by the memory controller, the memory controller to divide the homogeneous memory into a first physical memory partition and a second physical memory partition, wherein a boundary between the first physical memory partition and the second physical memory partition is defined by a low starting address of a continuous sub address space of the second physical memory partition, the first physical memory partition is allocated to a first type of information comprising user data and ECC data for the user data, the ECC data being interleaved in the user data, the second physical memory partition is allocated to a second type of information comprising further user data, and in response to a defective memory unit being detected in the homogeneous memory, the memory controller to dynamically redivide the homogeneous memory to change the low starting address of the continuous sub address space of the second physical memory partition based on an address of the detected defective memory unit, wherein the detected defective memory unit is changed either from the first physical memory partition to the second physical memory partition or from the second physical memory partition to the first physical memory partition based on the change in the low starting address of the continuous sub address space of the second physical memory partition.