Patent ID: 9287001
Filing Date: 2016-03-15
CPC Classification: G09G,G11C

Claim Text:
1. A shift register circuit, comprising: a first pull-down control circuit; a first pull-down circuit electrically connecting to the first pull-down control circuit; a first inversed pulse signal coupling circuit configured to output a first inversed pulse signal; a first pull-up circuit configured to receive a first driving signal and a first pulse signal to output a first gate control signal; and a first main pull-down circuit electrically connecting to the first pull-up circuit and configured to control the first driving signal; wherein when a first control signal outputted by the first pull-down control circuit is at a first preset logic level, the first pull-down control circuit disables the first inversed pulse signal coupling circuit, and when the first control signal outputted by the first pull-down control circuit is not at the first preset logic level, the first inversed pulse signal coupling circuit outputs the first inversed pulse signal; and wherein the first inversed pulse signal coupling circuit comprises a first transistor, and the first transistor is configured to receive the first inversed pulse signal and via a first capacitor, couple the first inversed pulse signal to the first driving signal.