Patent ID: 9503666
Filing Date: 2016-11-22
CPC Classification: H04N

Claim Text:
1. An image sensor, comprising: a plurality of pixels arranged in rows and columns; and a plurality of readout circuits coupled to read out integrated light signals from the plurality of pixels via bitlines respectively, each of the plurality of readout circuits including a correlated double sampling (CDS) circuit, followed by an analog-to-digital converter (ADC), at least two pixels of the plurality of pixels of a row sharing a bitline and an associated readout circuit; wherein the ADC operates concurrently with the CDS circuit, such that their operating periods are substantially overlapped with each other; and wherein the CDS circuit comprises a first capacitor bank and a second capacitor bank, which are coupled in parallel between the bitline and the ADC, the first capacitor bank is activated in a first-half period under control of an enable signal, and the second capacitor bank is activated in a second-half period under control of an inverted enable signal.