Patent ID: 9231029
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A semiconductor memory device comprising: a plurality of global bit lines extending in a first direction and arranged with spacings in a second direction crossing the first direction; a plurality of word lines spaced in the first direction, extending in the second direction, and stacked via an interlayer insulating layer in a third direction crossing the first direction and the second direction, the word lines including a first word line and a second word line arranged adjacently to each other in the first direction; a plurality of bit lines arranged with spacings in the second direction between the word lines, and extending in the third direction, the bit lines including a first bit line and a second bit line arranged adjacently to each other in the first direction, the first bit line provided between the first word line and the second word line, the first word line provided between the first bit line and the second bit line; a plurality of resistance change films provided between the word lines and the bit lines, the resistance change films including a first resistance change film and a second resistance change film arranged adjacently to each other in the first direction, the first word line provided between the first bit line via the first resistance change film and the second bit line via the second resistance change film; a plurality of semiconductor layers provided between the global bit lines and the bit lines; a gate insulating film provided on a side surface of the semiconductor layers; and a plurality of gate electrodes provided via the gate insulating film between the semiconductor layers in the second direction and on the side surface of the semiconductor layers in the first direction, and extending in the second direction, spacing in the first direction between the plurality of semiconductor layers being larger than spacing in the second direction between the plurality of semiconductor layers, the plurality of gate electrodes being separated in the first direction, and in the first direction, a distance between the gate electrodes adjacently arranged being shorter than a distance between the first bit line and the second bit line.