Patent ID: 9350584
Filing Date: 2016-05-24
CPC Classification: G06F,H04L

Claim Text:
1. A method in an element selection unit for vector element selection, the element selection unit comprises a selector control circuit and a selector data path circuit, which selector data path circuit comprises a plurality of layers that each comprises a plurality of multiplexers, and wherein the method comprises: receiving an instruction to perform a selection of data elements from a source vector comprising at least one input vector, which instruction comprises information relating to the at least one input vector, information relating to at least one output vector, and information relating to a bit map; by means of the selector control circuit, generating a multiplexer control signal for each multiplexer of the plurality of multiplexers based on the bit map and on a plurality of relative offset values, each of which plurality of relative offset values is calculated for each of the data elements of the input vector based on an input offset value and based on the bit map; by means of the selector data path circuit, propagating the data elements comprised in the input vector through the plurality of layers of multiplexers towards the output vector based on the generated multiplexer control signals; and by means of the selector data path circuit, writing the propagated data elements to data elements of the output vector, wherein the bit map defines which data elements are selected by the selector data path circuit from the input vector and written to the output vector and which data elements are not selected by the selector data path circuit and not written to the output vector.