Patent ID: 9230392
Filing Date: 2016-01-05
CPC Classification: G06F,G07F,H05K

Claim Text:
1. A gaming machine comprising: an address bus; a main circuit coupled to said address bus, said main circuit comprising a main processor and a main memory, the main memory storing program code that allows a player of the gaming machine to play at least one game when executed by the main processor, the program code including authentication code that, when executed, causes the main processor to output challenge data and modify game play if valid response data is not received, and sub-routine code that, when executed, outputs sub-routine data; and an activatable auxiliary circuit removably attachable to said main circuit via said address bus, said activatable auxiliary circuit upon attachment and activation being in data communication with the main circuit via said address bus, and said activatable auxiliary circuit comprising an auxiliary processor configured to receive said challenge data from the main processor and to process said challenge data in order to output the valid response data to the main processor; an activatable additional function circuit partitioned separately from the activatable auxiliary circuit and the main circuit, said activatable additional function circuit upon activation being in data communication with the main circuit via the address bus, and said activatable additional function circuit, when activated, is responsive to receipt of the sub-routine data from the main processor to produce sub-routine outcome data; and an address decoder partitioned separately from the main circuit, the activatable auxiliary circuit and the activatable additional function circuit, the address decoder being in data communication with the main circuit, the activatable auxiliary circuit and the activatable additional function circuit via the address bus, and the address decoder being configured to receive address data from the main processor via the address bus and to activate the activatable auxiliary circuit when the activatable auxiliary circuit is attached to said main circuit, the activatable additional function circuit, or both the activatable auxiliary circuit when the activatable auxiliary circuit is attached to said main circuit and the activatable additional function circuit in dependence on the address data received via the address bus from the main processor.