Patent ID: 9276598
Filing Date: 2016-03-01
CPC Classification: H03M

Claim Text:
1. A trim-matched segmented digital-to-analog converter (“DAC”), comprising: a binary portion of a segmented voltage divider network of resistors arranged as an R-2R ladder network, resistors of a predetermined number of higher-order R-2R branches of the binary portion geometrically up-scaled by a factor corresponding to a binary weight of each of the predetermined number of higher-order R-2R branches in order to limit a closely-located resistance mismatch error in the binary portion to a selected tolerance, a largest-factor up-scaled single-R resistor coupled between a highest-order R-2R branch node and an output terminal of the DAC (“DAC_OUT”); a linear portion of the voltage divider network coupled to the binary portion, the linear portion to include a pre-determined number of linear branches, each linear branch coupled between DAC_OUT and a linear branch switched-to voltage rail as determined by a thermometer-decoded state of bits in a binary input word at a plurality of high-order bit positions associated with the linear portion, at least one linear branch (“DLB”) implemented as an R-2R network down-scaled from a scale of the binary portion by an integer down-scaling factor in order to decrease a semiconductor area utilization and to decrease a long-distance mismatch error associated with the DLB; and a trim circuit coupled to the DLB, the trim circuit to select at least one resistor (collectively, “RES_TRIM”) from a trim resistor network, RES_TRIM having a resistance value R_TRIM, the trim circuit to adjust a measured lumped resistance of the DLB to cause the adjusted lumped resistance of the DLB to better match a measured lumped resistance of the binary portion.