Patent ID: 9355924
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. An integrated circuit, comprising: a substrate having at least one depression on a top surface; at least one solder bump disposed over the substrate; a die disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump; and an underfill surrounding the at least one solder bump and formed between the substrate and the die, at least two second solder bumps disposed over the substrate and outside the underfill; wherein the at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression, the at least one depression being in the form of a channel that has a first part that substantially surrounds the underfill and a second part that extends between two of the at least two second solder bumps.