Patent ID: 9305918
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor structure, comprising: etching a semiconductor substrate to form a plurality trenches and define a plurality of fin active regions; filling in the plurality of trenches with a dielectric material to form shallow trench isolation (STI) features; recessing a first subset of the STI features in a first region by a first dimension; recessing a second subset of the STI features in a second region by a second dimension less than the first dimension; and forming a conductive feature on the STI features and the fin active regions, wherein the conductive feature covers the first subset of the STI features, wherein recessing the first subset of the STI features in the first region by the first dimension, and recessing the second subset of the STI features in the second region comprise: forming a patterned resist layer on the semiconductor substrate, wherein the patterned resist layer has openings exposing the first region and covering the second region:, performing a first STI etch to the first subset of the STI features in the first region through the openings of the patterned resist layer; removing the patterned resist layer; and performing a second STI etch to the first subset of the STI features in the first region and the second subset of the STI features in the second region, resulting in the first subset of the STI features being recessed from the second subset of the STI features.