Patent ID: 9425206
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. An integrated circuit (IC), comprising: a semiconductor substrate comprising a first region and a second region separated by a boundary region; a non-volatile memory (NVM) or a poly SiON (silicon oxy-nitride) CMOS device located over the first region; a periphery circuit disposed over the second region; one or more electrically inactive dummy structures laterally disposed between the NVM or the poly SiON CMOS device and the periphery circuit, wherein a bottom surface of the one or more electrically inactive dummy structures is disposed over a top surface of the semiconductor substrate; and a shallow trench isolation (STI) region comprising a first upper surface and a second upper surface that is recessed to a depth in comparison with the first upper surface to provide a recessed portion of the STI region, wherein the recessed portion of the STI region is laterally offset from the one or more electrically inactive dummy structures.