Patent ID: 9245633
Filing Date: 2016-01-26
CPC Classification: G06F,G11C

Claim Text:
1. A storage device, comprising: a memory comprising a plurality of cells, wherein each of the cells stores a plurality of bits, and the bits of the memory are arranged into a plurality of pages of the memory; and a controller coupled to the memory and receiving a host command for programming a first data into a first page of the memory, wherein when the first page does not consist of the most significant bits of the cells, the controller performs a first 2Plane programming to program the first data into the first page and backups the first data into a second page of the memory, wherein the first page and the second page are located in different planes of the memory, wherein when the host command is further for programming a second data into the second page and when both of the first page and the second page consist of the most significant bits of the cells, the controller performs a second 2Plane programming to program the first data into the first page and program the second data into the second page without backup for the first data and the second data in the memory.