Patent ID: 9348686
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. A computer system for collecting error data, the system including: a memory; and a processing unit, communicatively coupled to said memory, the computer system configured to perform a method comprising: identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication; organizing the plurality of error state devices as a single sequence; collecting a plurality of state indications by sequentially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, wherein the sampling includes serially shifting a data array through each error state device in the sequence and outputting the state indication; sequentially storing each state indication into a single linear data array according to the sequence; and outputting the linear data array as a data structure, the data structure including information regarding one or more error events based on one or more errors occurring in the processor.