Patent ID: 9245827
Filing Date: 2016-01-26
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor integrated circuit, comprising: a chip pad; a memory cell array; a decoder configured to select a cell of the memory cell array; and a first information path extending between the chip pad and at least one of the memory cell array and the decoder; a through substrate via extending from a chip terminal other than the chip pad to a node of the first information path to form a second information path comprising a portion of the first information path and the through substrate via; a chip identification programmable circuit having a chip identification output identifying the semiconductor integrated circuit as a master chip or a slave chip; a selection circuit responsive to the chip identification output identifying the integrated circuit as a master chip to select the first information path, including the chip pad, as a communication path for an external communication with respect to the integrated circuit, and responsive to the chip identification output identifying the integrated circuit as a slave chip to select the second information path, including the through substrate via, as a communication path for the external communication with respect to the integrated circuit.