Patent ID: 9419629
Filing Date: 2016-08-16
CPC Classification: H03K,H03L

Claim Text:
1. A delay-locked loop (DLL) circuit that receives an input clock signal and generates an output clock signal having a desired phase delay relative to the input clock signal, the DLL circuit comprising: a delay line that receives the input clock signal and a delay-line control signal and generates a plurality of fractional delay signals having different phase delays relative to the input clock signal whose magnitudes are based on the delay-line control signal; a phase frequency (PF) detector that receives the plurality of fractional delay signals from the delay line and generates UP and DOWN control signals based on the plurality of fractional delay signals; a charge pump that receives the UP and DOWN control signals and generates a pump current based on the UP and DOWN control signal; and a loop filter that receives the pump current and generates the delay-line control signal based on the pump current, wherein the PF detector comprises: