Patent ID: 9390782
Filing Date: 2016-07-12
CPC Classification: G06F,G11C

Claim Text:
1. An apparatus comprising: a memory controller chip; memory chips packaged with the memory controller chip to form a chip package, each memory chip having first storage rows having cells that exhibit retention times greater or equal to a first time interval, and second storage rows having cells that exhibit retention times less than the first time interval, wherein the second storage rows for a first one of the memory chips may comprise different row locations with respect to the second storage rows for a second one of the memory chips; storage configured to store information associated with the second storage rows of each memory chip, the information generated by a test process applied to the chip package; and refresh logic configured to refresh the first storage rows at a first refresh rate corresponding to the first time interval, and based on the information, refresh each of the second storage rows at a second refresh rate that is greater than the first refresh rate.