Patent ID: 9275951
Filing Date: 2016-03-01
CPC Classification: H01G,H01L,Y10T

Claim Text:
1. A method for reducing areas of high field density in an integrated circuit, the method comprising: forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit, wherein forming the first curvilinear wiring structure comprises forming a first set of concentric conductive annular structures having a first electrode and a second electrode; forming a second curvilinear wiring structure in a second interconnect layer of the integrated circuit, wherein the second curvilinear wiring structure is substantially vertically aligned with the first curvilinear wiring structure; and electrically connecting the first curvilinear wiring structure to the second curvilinear wiring structure, wherein electrically connecting the first curvilinear wiring structure to the second curvilinear wiring structure comprises: