Patent ID: 9437706
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A device, comprising: a transistor with a source region and a drain region; an interlayer dielectric layer adjacent the transistor; a trench through the first interlayer dielectric layer to at least one of the source region and the drain region; a conductive contact in the trench, the conductive contact being separated from the at least one of the source region and the drain region by a conformal insulating layer, wherein the conductive contact comprises a conformal conductive layer; a second interlayer dielectric layer; a first metallization layer adjacent the second interlayer dielectric layer and having a plurality of conductive vias and a plurality of conductive lines; a third interlayer dielectric layer over the second interlayer dielectric layer; a second metallization layer adjacent the third interlayer dielectric layer and having a plurality of conductive vias and a plurality of conductive lines; and wherein at least some of the plurality of conductive vias and the plurality of conductive lines of the first metallization layer and at least some of the plurality of conductive vias and the plurality of conductive lines of the second metallization layer are conductively connected to the conductive contact.