Patent ID: 9484207
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method for forming a semiconductor device structure, comprising: providing a wafer having a central portion and a peripheral portion surrounding the central portion; forming a first dielectric layer over the central portion, wherein the first dielectric layer has a plurality of first contact openings exposing a plurality of conductive regions of the wafer, and the first contact openings are spaced apart from each other; after the formation of the first dielectric layer, forming a protective layer over the peripheral portion; after forming the protective layer, performing a metal silicide process to form a plurality of metal silicide structures over the conductive regions of the wafer; after the metal silicide process, forming a plurality of first contact plugs in the first contact openings to electrically connect to the conductive regions via the metal silicide structures, respectively, wherein the formation of the first dielectric layer comprises: forming a dielectric material layer over the central portion and the peripheral portion; and removing the dielectric material layer over the peripheral portion and portions of the dielectric material layer over the central portion; before the formation of the dielectric material layer, forming a contact etch stop layer over the central portion and the peripheral portion, wherein the dielectric material layer is formed over the contact etch stop layer; and forming a second dielectric layer over the first dielectric layer; forming a plurality of second contact openings in the second dielectric layer to expose the first contact plugs, respectively; and forming a plurality of second contact plugs in the second contact openings to electrically connect to the first contact plugs.