Patent ID: 9419012
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a device, comprising: forming a stack of alternating layers comprising first material layers and second material layers over a substrate; forming a plurality of memory stack structures through the stack of alternating layers; forming a trench through the stack of alternating layers; replacing the second material layers with electrically conductive materials to form electrically conductive layers; removing the first material layers selective to the electrically conductive layers; depositing a dielectric material employing an anisotropic atomic layer deposition process in which supply of an active reactant gas species is spatially limited over a sidewall of the trench and first portions of the horizontal surfaces of the electrically conductive layers that are proximal to the trench to form a contiguous dielectric material layer while not depositing the dielectric material over second portions of the horizontal surfaces of the electrically conductive layers that are more distal from the trench than the first portions; forming an insulating spacer in the trench by anisotropically etching the contiguous dielectric material layer; and forming a backside contact via structure within the insulating spacer.