Patent ID: 9373413
Filing Date: 2016-06-21
CPC Classification: G09G,G11C

Claim Text:
1. A shift register unit, comprising: a capacitor having two electrodes, a first electrode of the two electrodes being directly connected with an output terminal; a first transistor, a gate thereof being directly connected with a signal input terminal, a drain thereof being directly connected with a first level terminal, and a source thereof being directly connected with a second electrode of the capacitor; a second transistor, a gate thereof being directly connected with a resetting terminal, a drain thereof being directly connected with the source of the first transistor, and a source thereof being directly connected with a second level terminal; a third transistor, a gate thereof being directly connected with the source of the first transistor, a drain thereof being directly connected with a first clock signal terminal, and a source thereof being directly connected with the output terminal; a fourth transistor, a gate thereof being directly connected with a second clock signal terminal, a drain thereof being directly connected with the output terminal, and a source thereof being directly connected with a low level terminal; a fifth transistor, a drain thereof being directly connected with the drain of the second transistor, and a source thereof being directly connected with the low level terminal; a sixth transistor, a gate thereof being directly connected with a gate of the fifth transistor, a drain thereof being directly connected with the drain of the fourth transistor, and a source thereof being directly connected with the source of the fourth transistor; a voltage pulling-down control module directly connected with the second clock signal terminal, the low level terminal, the gate of the fifth transistor, the source of the first transistor, a frame start signal terminal and a third level terminal, wherein in the case that the frame start signal terminal and the third level terminal of the voltage pulling-down module are at high levels simultaneously, the voltage pulling-down control module outputs a high level at the gate of the fifth transistor, and the fifth transistor is in a turn-on state so as to pull down a gate voltage of the third transistor, and the sixth transistor is also in the turn-on state so as to pull down a voltage at the output terminal.