Patent ID: 9269717
Filing Date: 2016-02-23
CPC Classification: G11C,H01L

Claim Text:
1. A method for forming an EEPROM device, comprising: providing a semiconductor substrate formed with a plurality of active regions therein, wherein each active region extends along a first direction, and the plurality of active regions are arranged one after another along a second direction vertical with the first direction; forming float gate polycrystalline silicon layers extending along the first direction and respectively disposed on the active regions, where each float polycrystalline silicon layer has a width larger than that of the active region disposed thereunder; forming control gate dielectric material layers respectively overlaying the float gate polycrystalline silicon layers; forming a control gate polycrystalline silicon layer overlaying exposed part of the semiconductor substrate and the control gate dielectric material layers; forming a hard mask layer disposed on the control gate polycrystalline silicon layer and having a plurality of first openings formed therein, wherein each of the first openings extends along the second direction and exposes a part of a top surface of the control gate polycrystalline silicon layer, wherein the first openings are arranged one after another along the first direction; forming first spacers respectively on sidewalls of each of the first openings; etching the control gate polycrystalline silicon layer, the control gate dielectric material layers, and the float gate polycrystalline silicon layers by taking the first spacers of the first openings and the hard mask layer as masks, so as to form second openings; forming an isolation oxide layer overlaying inner surfaces of each second opening; forming a word line in each second opening and on the isolation oxide layer; removing the hard mask layer; and etching, by taking the first spacers and the word lines as masks, the control gate polycrystalline silicon layer, the control gate dielectric material layers, and the float gate polycrystalline silicon layers, so as to form a memory unit corresponding to each word line, wherein the remained float gate polycrystalline silicon layers disposed on two sides of the word line constitute two float gates of the memory unit, the remained control gate dielectric material layers disposed on two sides of the word line and respectively on the two float gates constitute two control gate dielectric layers of the memory unit, and the remained control gate polycrystalline silicon layers disposed on two sides of the word line and respectively on the two control gate dielectric layers constitute two control gates of the memory unit.