Patent ID: 9484409
Filing Date: 2016-11-01
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate including a well dopant layer having a first conductivity type; a gate electrode on the well dopant layer; a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, the channel dopant layer having the first conductivity type; a channel region between the gate electrode and the channel dopant layer, the channel region having the first conductivity type; and source/drain regions in the well dopant layer at both sides of the gate electrode, the source/drain regions having a second conductivity type, wherein a concentration of dopants having the first conductivity type in the channel dopant layer is higher than a concentration of dopants having the first conductivity type in the channel region, wherein each of the source/drain regions comprises: an upper portion adjacent to the channel region; and a lower portion adjacent to the channel dopant layer, and wherein a dopant concentration of the upper portion is substantially equal to a dopant concentration of the lower portion.