Patent ID: 9234940
Filing Date: 2016-01-12
CPC Classification: G01R

Claim Text:
1. A fan-out wafer comprising: a first IC die having at least a first boundary scan cell (BSC) and a second BSC, the first BSC coupled to a first demultiplexer, the second BSC coupled to a first pad; a second IC die having at least a third BSC coupled to a second demultiplexer, and a second pad connected to the first pad; a first master path connecting the first demultiplexer to the second demultiplexer; and a first slave path connecting the first demultiplexer to the second demultiplexer, wherein the first pad and the second pad are located between the first master path and the first slave path, wherein the first master path includes a first master pad on the first die connected to a first slave pad on the second die, the first master pad and the first slave pad connected between the first demultiplexer and the second demultiplexer; and the first slave path includes a second slave pad on the first die connected to a second master pad on the second die, the second slave pad and the second master pad connected between the first demultiplexer and the second demultiplexer.