Patent ID: 9401800
Filing Date: 2016-07-26
CPC Classification: H04L,H04N

Claim Text:
1. A clock data recovery system, comprising: a continuous time linear equalizer receiving a received signal and generating a first equalized signal; an adder for superposing the first equalized signal and a feedback equalization signal with each other, thereby generating a superposed signal; a first error slicer for slicing the superposed signal according to a clock signal and a first slicing voltage, thereby generating a first error signal; a second error slicer for slicing the superposed signal according to the clock signal and a second slicing voltage, thereby generating a second error signal; a data slicer for slicing the superposed signal according to the clock signal and a third slicing voltage, thereby generating a data signal; a clock data recovery circuit receiving the data signal and the second error signal, and generating the clock signal to the data slicer, the first error slicer and the second error slicer; an adaptive filter receiving the data signal and the first error signal, and generating a reference voltage to the first error slicer and generating a decision feedback equalizer coefficient set, wherein the reference voltage is equal to the first slicing voltage; and a decision feedback equalizer receiving the data signal and the decision feedback equalizer coefficient set, and generating the feedback equalization signal to the adder.