Patent ID: 9362917
Filing Date: 2016-06-07
CPC Classification: H03K,H04L

Claim Text:
1. An LVDS (Low Voltage Differential Signaling) driving circuit generating a differential signal at a first node and a second node according to a data signal, comprising: a first transistor, comprising a first terminal coupled to a supply voltage and a second terminal coupled to the first node, wherein the first transistor and a first driver form a first current mirror when the data signal is at a high logic level and do not form the first current mirror when the data signal is at a low logic level, wherein when the first current mirror is formed, a current passing through the first transistor when a XOR result of the data signal and a delayed data signal is logical high is higher than the current passing through the first transistor when the XOR result of the data signal and the delayed data signal is logical low; a second transistor, comprising a first terminal coupled to the supply voltage and a second terminal coupled to the second node, wherein the second transistor and a second driver form a second current mirror when the data signal is at the low logic level and do not form the second current mirror when the data signal is at the high logic level, wherein when the second current mirror is formed, a current passing through the second transistor when the XOR result of the data signal and the delayed data signal is logical high is higher than the current passing through the second transistor when the XOR result of the data signal and the delayed data signal is logical low; a third transistor, comprising a first terminal coupled to a ground voltage and a second terminal coupled to the first node, wherein the third transistor and a third driver form a third current mirror when the data signal is at the low logic level and do not form the third current mirror when the data signal is at the high logic level, wherein when the third current mirror is formed, a current passing through the third transistor when the XOR result of the data signal and the delayed data signal is logical high is higher than the current passing through the third transistor when the XOR result of the data signal and the delayed data signal is logical low; and a fourth transistor, comprising a first terminal coupled to the ground voltage and a second terminal coupled to the second node, wherein the fourth transistor and a fourth driver form a fourth current mirror when the data signal is at the high logic level and do not form the fourth current mirror when the data signal is at the low logic level, wherein when the fourth current mirror is formed, a current passing through the fourth transistor when the XOR result of the data signal and the delayed data signal is logical high is higher than the current passing through the fourth transistor when the XOR result of the data signal and the delayed data signal is logical low, wherein the delayed data signal is generated by delaying the data signal with a time delay.