Patent ID: 9348681
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. An apparatus for detecting a fault of a processor that includes a plurality of processor cores connected to a memory, each processor core having a fetch unit, a decoding unit, and an execution unit, the apparatus comprising: a fetch fault control unit configured to detect a fault occurring in any of the fetch units of the plurality of processor cores; a decoding fault control unit configured to detect a fault occurring in any of the decoding units of the plurality of processor cores; and an execution fault control unit configured to detect a fault occurring in any of the execution units of the plurality of processor cores, the execution fault control unit being configured to execute a same instruction in the plurality of processor cores, to determine a processor core in which a fault has occurred to be a faulty processor core, and to provide a notification of the faulty processor core to the fetch fault control unit and the decoding fault control unit.