Patent ID: 9484296
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A structure comprising: at least one via level dielectric layer overlying a substrate; at least one line level dielectric layer located above the at least one via level dielectric layer; and an integrated line and via structure comprising a first line structure and a via structure in contact with each other, wherein: the first line structure comprises a conductive material contacting sidewalls of the at least one line level dielectric layer and a top surface of the at least one via level dielectric layer; the via structure comprises a conductive material contacting a sidewall of the at least one via level dielectric layer, a sidewall of the at least one line level dielectric layer, and a sidewall of the first line structure; the integrated line and via structure further comprises a second line structure contacting the conductive via liner and additional sidewalls of the at least one line level dielectric layer; the via structure is embedded between edge sidewalls of the first and the second line structures to electrically connect the first and the second line structures together to form a bit line; bottom surfaces of the first and the second line structures are located above a bottom surface of the via structure; a bottom surface of the via structure physically contacts an underlying device; and the bottom surfaces of the first and the second line structures do not physically contact the semiconductor or electrically conductive layer of the underlying device.