Patent ID: 9450056
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate of a first conductivity; a first region of a second conductivity formed over the substrate; a second region of the second conductivity formed in the first region; a third region of the first conductivity formed in the first region; a first dielectric layer with a first thickness formed over the first region, wherein a first side of the first dielectric layer is adjacent to the second region and an edge of the first side of the first dielectric layer is vertically aligned with an edge of the second region; a second dielectric layer with a second thickness formed with a first side adjacent to a second side of the first dielectric layer, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form a step; a first gate formed over the first dielectric layer, wherein a width of the first dielectric layer is greater than a width of the first gate and the first gate occupies a middle portion of the first dielectric layer, and wherein edge regions of the first dielectric layer are free of the first gate thereon; and a second gate formed above the second dielectric layer, wherein the second gate is separated from the first gate by a gap and a width of the second dielectric layer is greater than a width of the second gate, and wherein the step is free of a gate material thereon.