Patent ID: 9293193
Filing Date: 2016-03-22
CPC Classification: G11C

Claim Text:
1. A memory circuit comprising: a latch unit; a first switch unit between a first signal line and the latch unit; a second switch unit between a second signal line and the latch unit; and a third switch unit between the latch unit and a power supply line, wherein the latch unit comprises a first inverter and a second inverter, an input terminal of the first inverter is electrically connected to an output terminal of the second inverter, and an input terminal of the second inverter is electrically connected to an output terminal of the first inverter, wherein the first inverter comprises a field-effect transistor, and wherein each of a gate of the field-effect transistor, the first switch unit, the second switch unit, and the third switch unit is supplied with a control signal.