Patent ID: 9450025
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A resistive memory device comprising: a plurality of memory cell pillars spaced in a line in one direction and each comprising a memory layer, a top electrode layer electrically connected to the memory layer, and a selection device; bottom conductive lines each extending in another direction crossing said one direction; a top conductive line having protrusions at its bottom and pockets in its bottom, wherein the bottom conductive lines are electrically connected to the memory cell pillars at first parts of the bottom conductive lines, respectively, the selection device of each of the memory cell pillars is interposed between the memory layer of the memory cell pillar and a respective one of the bottom conductive lines, the pockets are defined by and between the protrusions in said one direction such that the pockets and protrusions are alternately disposed along said one direction, whereby the top conductive line has an uneven bottom surface, the protrusions are connected to the memory cell pillars at tops of the memory cell pillars, respectively, and each of the protrusions is electrically connected to the memory layer of a respective one of the memory cell pillars through the top electrode layer of the memory cell pillar; and a plurality of insulating pillars occupying insulating spaces defined by side surfaces of the memory layer and top electrode layer, the insulating pillars extending into the pockets in the bottom of the top conductive line, respectively.