Patent ID: 9431079
Filing Date: 2016-08-30
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a self-timed pulse generator configured to receive a clock signal and generate a self-timed pulse having a first edge corresponding to a rising edge of the clock signal and a second edge; first input latch circuitry configured to receive the self-timed pulse and a memory operation command and generate an internal memory operation command set to a latched state corresponding to the first edge of the self-timed pulse; read/write control circuitry configured to receive the self-timed pulse and internal memory operation signal and perform a read operation and a write operation for at least one memory address, the read operation being performed corresponding to one of the first edge and second edge of the self-timed pulse, and the write operation being performed corresponding to one of the first edge and second edge of the self-timed pulse, wherein the read/write control circuitry is configured to control row and column addresses of the at least one memory address using section address data that is separate from a read pulse during the read operation; and second input latch circuitry configured to receive the self-timed pulse and a memory address and generate an internal address signal set to a latched state corresponding to the first edge of the self-timed pulse, wherein the section address data is used to synchronize memory operations associated with the row and column addresses propagating into and out of the memory; wherein the self-timed pulse generator is further configured to adjust a width of the self-timed pulse to ensure the completion of the read operation; and wherein the read/write control circuitry is configured to align write address timing and data timing associated with the write operation via: