Patent ID: 9230851
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming at least one trench from a top side of a semiconductor surface, wherein said trench is lined with a trench dielectric liner and filled by a first polysilicon layer; etching a surface of said trench dielectric liner, wherein dips are formed relative to a top surface of said first polysilicon layer which form a polysilicon protrusion comprising said first polysilicon layer; etching said first polysilicon layer to remove at least a portion of said polysilicon protrusion; forming a second dielectric layer over at least said trench after etching said first polysilicon layer; depositing a second polysilicon layer, and etching said second polysilicon layer to remove said second polysilicon layer over said trench and provide a patterned second polysilicon layer without substantially recessing from said top side of said semiconductor surface.