Patent ID: 9520392
Filing Date: 2016-12-13
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device comprising: forming a first fin corresponding to a field effect transistor (FET) on a first region of a semiconductor substrate and forming a second fin corresponding to a varactor on a second region of the semiconductor substrate; recessing the first region with respect to the second region so as to increase a physical height of the first fin with respect to a physical height of the second fin; and doping the first fin and the second fin so as to form a finFET in the first region and a fin varactor in the second region, wherein recessing the first region further comprises: depositing a masking layer atop the first and second regions so as to cover the first fin and the second fin, and selectively patterning the masking layer to expose the first region while maintaining coverage of the second region; depositing a conformal spacer layer atop the first region and the second region, the conformal spacer layer covering sidewalls and an upper surface of the first fin and an upper masking surface of the masking layer; performing a first etching process selective to the conformal spacer layer so as to expose the semiconductor substrate of the first region; and performing a second etching process selective to the semiconductor substrate so as to recess the first region with respect to the second region.