Patent ID: 9478542
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate having at least one well region implanted with a first dopant by a first well implantation and a non-doped section blocked from the first well implantation; at least one semiconductor fin structure formed on the substrate, the at least one semiconductor fin structure having a channel stop region and a channel region above the channel stop region, the channel stop region having at least a portion of the non-doped section and at least a portion of the well region, the at least one semiconductor fin structure having a planar channel formed at an interface between the at least a portion of the non-doped section and the channel region for additional current flow between source and drain regions of the at least one semiconductor fin structure; an isolation layer disposed adjacent to and in contact with at least the well region and the channel stop region; and a gate structure disposed on at least a portion of the isolation layer and around at least a portion of the channel region.