Patent ID: 9318612
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. An array substrate comprising: a substrate including a pixel region; a thin film transistor in the pixel region, the thin film transistor including a gate electrode, an oxide semiconductor layer and source and drain electrodes spaced apart from each other, wherein a first insulating layer of an inorganic insulating material is disposed between the gate electrode and the oxide semiconductor layer, and wherein a second insulating layer of an inorganic insulating material is disposed between the oxide semiconductor layer and the source and drain electrodes; a passivation layer on the thin film transistor, the passivation layer having a drain contact hole exposing the drain electrode; a first electrode on the passivation layer in the pixel region, the first electrode connected to the drain electrode through the drain contact hole; and a first hydrogen absorbing layer on at least one of top and bottom surfaces of the first insulating layer, at least one of top and bottom surfaces of the second insulating layer, or at least one of top and bottom surfaces of the passivation layer, the first hydrogen absorbing layer including a plurality of particles spatially and electrically separated from each other, the plurality of particles including one of nickel, palladium and platinum, wherein the oxide semiconductor layer directly and physically contacts the first hydrogen absorbing layer.