Patent ID: 9425311
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A method for fabricating MOS transistors, comprising: providing a semiconductor substrate having at least a first region and a second region; forming PMOS transistors on the semiconductor substrate in the first region and the second region, wherein source/drain regions of the PMOS transistors are configured as SiGe growth regions; and a first density of the SiGe growth regions in the first region is smaller than a second density of the SiGe growth regions in the second region; after forming the PMOS transistors in the first region and the second region, separately forming dummy SiGe growth regions of dummy PMOS transistors in the first region to increase the first density, such that a total density of the SiGe growth regions from both the PMOS transistors and the dummy PMOS transistors in the first region equals to the second density of the SiGe growth regions from the PMOS transistors in the second region; forming trenches by etching the SiGe growth regions in the first region and the second region and the dummy SiGe growth regions in the first region; and forming embedded source/drain regions of the PMOS transistors and dummy SiGe regions by forming SiGe in the trenches.