Patent ID: 9509284
Filing Date: 2016-11-29
CPC Classification: H01L,H03K

Claim Text:
1. An electronic circuit, comprising: a transistor arrangement with a first type transistor device and at least one second type transistor device, each comprising a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel; and a drive circuit coupled to the control node of the first type transistor device and the control node of the second type transistor device, and configured to receive an input signal, wherein each of the first type transistor device and the second type transistor device comprises a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG, wherein the field plate of the first type transistor device is connected to one of the control node and the second load node of the first type transistor device, wherein the drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate the at least one second type transistor device based on the load signal, wherein the first type transistor device and the at least one second type transistor device are integrated in a common semiconductor body, wherein the 2DEG of the first type transistor device is insulated from the 2DEG of the at least one second type transistor device by an insulation region, wherein the insulation region includes a damaged crystal region.