Patent ID: 9311982
Filing Date: 2016-04-12
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: a memory cell comprising a first transistor, a second transistor, and a capacitor; a first wiring; and a second wiring, wherein: the memory cell is capable of retaining a charge corresponding to a data voltage at a node, the node is electrically connected to one of electrodes of the capacitor, the node is electrically connected to a gate of the first transistor, the node is electrically connected to one of a source and a drain of the second transistor, a step of reading out and transferring the data voltage to the first wiring comprises a first step, a second step, and a third step, the first step comprises a step of precharging the first wiring, the second step comprises a step of discharging a potential of the first wiring to the second wiring through the first transistor in accordance with the data voltage, the third step comprises a step of changing the potential of the first wiring close to a first potential, the first potential is the sum of a potential of the node and a threshold voltage of the first transistor, and in the second step, a potential of the second wiring is switched in accordance with change in the potential of the first wiring.