Patent ID: 9356127
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A layout structure of heterojunction bipolar transistors (HBTs), comprising: one or more HBTs formed on a substrate, each comprising a base electrode, an emitter electrode, and a collector electrode; a passive layer formed on the HBTs, comprising a first metal layer, an emitter pad and a collector pad, wherein the first metal layer is made essentially of Au and containing no Cu and formed on the bottom of the passive layer connecting to the base electrode, the emitter electrode, and the collector electrode, the emitter pad is electrically connected to each of the one or more emitter electrodes through the first metal layer, and the collector pad is electrically connected to each of the one or more collector electrodes through first metal layer; a first dielectric layer covering on the passive layer, comprising one or more emitter via holes formed on the emitter pad through the first dielectric layer and one or more collector via holes formed on the collector pad through the first dielectric layer; a collector redistribution layer formed on the first dielectric layer and extending into the one or more collector via holes to form an electrical connection to the collector pad; one or more emitter copper pillars, each disposed on at least one of the one or more emitter via holes and filling therein to form an electrical connection to the emitter pad; one or more collector copper pillars, each disposed on the collector redistribution layer to form an electrical connection to the collector redistribution layer; and an emitter redistribution layer formed on the first dielectric layer and extending into at least one of the one or more emitter via holes below one of the one or more emitter copper pillars and forms an electrical connection to the emitter pad.