Patent ID: 9432058
Filing Date: 2016-08-30
CPC Classification: H03M

Claim Text:
1. An error correction apparatus, applied to a digital signal received at a signal reception terminal, comprising: a first error correction module, configured to perform first error correction on an input signal to generate an intermediate signal satisfying a termination condition, wherein the input signal corresponds to the digital signal; and a second error correction module, coupled to the first error correction module, for receiving and selectively performing second error correction on the intermediate signal to generate a corrected signal; wherein, the termination condition is associated with a maximum error correction capability of the second error correction, wherein the first error correction is a low-density parity check (LDPC), wherein the termination condition is that an error level of the intermediate signal is smaller than a threshold, the error level is a parity check sum generated by the first error correction module according to the input signal and a parity check matrix, and the threshold is associated with the maximum error correction capability of the second error correction, and wherein when the intermediate signal is determined to be error-free, not performing the second error correction on the intermediate signal and outputting the intermediate signal as the corrected signal, wherein the second error correction is Boss-Chaudhuri-Hocquenghem (BCH) error correction, and the maximum error correction capability is associated with a maximum recovery bit count of the second error correction, wherein the termination condition is that an error level of the intermediate signal is smaller than the threshold, which is a product of the maximum error correction capability and a predetermined weighting, and wherein as a result of the threshold being calculated with respect to the maximum error correction capability, the second error correction completely corrects the intermediate signal.