Patent ID: 9379088
Filing Date: 2016-06-28
CPC Classification: H01L,H02M,Y10T

Claim Text:
1. A method for fabricating a stacked package of a voltage regulator, comprising: forming a first chip by integrating a gate driving circuit with a first power switch, forming a second chip having a second power switch, arranging a plurality of terminals on a front surface of said first chip and on a front surface of said second chip, and arranging a plurality of terminals on a back surface of said second chip; forming a group of bumps corresponding to said plurality of terminals on said front surface of said first chip and on said front surface of said second chip; forming a non-conductive layer and conductive layer side by side on said back surface of said second chip, for electrically insulating said first chip from said second chip and electrically coupling said first chip to said second chip respectively; providing a first leadframe and a second leadframe each having at least a group of leads, all of said leads of said first leadframe being electrically coupled to said terminals on said front surface of said first chip by means of said bumps of said first chip, and some of said leads of said second leadframe being electrically coupled to said terminals on said front surface of said second chip by means of said bumps of said second chip; electrically coupling said back surface of said first leadframe to said back surface of said second chip; electrically coupling said leads of said first leadframe to the corresponding ones of said second leadframe by using a group of electrical wires so that said leads of said second leadframe may be coupled to an external circuit; and encapsulating said first chip, said second chip, said conductive layer, said non-conductive layer, said plurality of bumps, said first leadframe, said second leadframe and said group of electrical wires in a stacked package.