Patent ID: 9391021
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A chip package comprising: a first semiconductor chip having a first surface, said first semiconductor chip comprising a passivation layer defining an opening exposing a contact pad; a first polymer layer having a planar surface and a polymer surface opposite said planar surface, in which a portion of said first polymer layer is coupled to said first surface and sidewalls of said first semiconductor chip; a first conductive interconnect having a coupling surface for coupling to said contact pad and a second surface opposite said coupling surface, in which said second surface of said first conductive interconnect is co-planar with said polymer surface of said first polymer layer opposite said first surface of said first semiconductor chip, wherein said first conductive interconnect comprises an adhesion/barrier layer directly on said first polymer layer and said contact pad, a conductive seed layer directly on said adhesion/barrier layer and an electroplated conductive layer directly on said seed layer, wherein a first sidewall of said electroplated conductive layer is flush with a first sidewall of said adhesion/barrier layer and a first sidewall of said seed layer, and a second sidewall opposite said first sidewall of said electroplated conductive layer is flush with a second sidewall of said adhesion/barrier layer and a second sidewall of said seed layer; a second polymer layer coupled to said first polymer layer on said polymer surface; a conductive layer having conductive elements within and directly on a surface of said second polymer layer and directly on said second surface opposite said coupling surface of said first conductive interconnect, and across an edge of said first semiconductor chip; and a third polymer layer on said conductive layer, on said second polymer layer and across said edge of said first semiconductor chip.