Patent ID: 9294260
Filing Date: 2016-03-22
CPC Classification: H04L

Claim Text:
1. An apparatus comprising: an input to receive a serial data signal; an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal; a clock and data recovery (CDR) circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal; a phase adjustment circuit to generate phase lead/lag adjustment data; a decision feedback equalization (DFE) loop to provide equalization to the CDR circuit based, at least in part, on pre-cursor and post-cursor data samples of the serial data signal captured by a pre-cursor tap and a post-cursor tap, respectively, of the DFE loop, wherein the phase adjustment circuit is to generate the phase lead/lag adjustment data based, at least in part, on one of the pre-cursor or the post-cursor data samples captured by the DFE loop.