Patent ID: 9525940
Filing Date: 2016-12-20
CPC Classification: H03M,H04R

Claim Text:
1. A processing system comprising: a plurality of processing paths including a first processing path and a second processing path, wherein: the first processing path comprises a first analog front end, and a first digital processing subsystem having a first analog-to-digital converter, wherein the first analog front end includes an inverting amplifier configured to amplify an analog input signal to generate a first amplified analog signal and the first digital processing subsystem is configured to convert the first amplified analog signal into a first digital signal; the second processing path comprises a second analog front end, and a second digital processing subsystem having a second analog-to-digital converter, wherein the second analog front end includes a non-inverting amplifier configured to amplify the analog input signal to generate a second amplified analog signal and the second digital processing subsystem is configured to convert the second amplified analog signal into a second digital signal; and a magnitude of a gain of the non-inverting amplifier is substantially larger than a magnitude of a gain of the inverting amplifier; the magnitude of gain of the first digital processing subsystem is substantially smaller than the magnitude of gain of the second digital processing subsystem; and a first path gain equal to the product of a magnitude of the gain of the inverting amplifier and a magnitude of a gain of the first digital processing subsystem is substantially equal to a second path gain equal to the product of a magnitude of gain of the non-inverting amplifier and a gain of the second digital processing subsystem; and a controller configured to select one of the first digital signal and the second digital signal as a digital output signal of the processing system based on a magnitude of the analog input signal.