Patent ID: 9348393
Filing Date: 2016-05-24
CPC Classification: G06F,Y02D

Claim Text:
1. A method comprising: activating a processor from a low power mode to a higher power mode; responsive to activating the processor, providing a feedback loop with data indicating a first amount of time that the processor was in the low power mode and that exceeded a second amount of time that the feedback loop indicated for the low power mode at a time that the processor entered the low power mode, wherein the feedback loop controls processor power consumption based on estimated processor power consumption over time; responsive to activating the processor, determining a number of iterations of the feedback loop that correspond to the first amount of time; responsive to activating the processor, exercising the feedback loop for the number of iterations to account for the first amount of time; and during exercising the feedback loop for the number of iterations, setting the estimated processor power consumption provided to the feedback loop to zero; and determining a duty cycle for a power on/power off time of the processor by the feedback loop, wherein a power on portion of the duty cycle is lengthened responsive to the exercising.