Patent ID: 9263516
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. An integrated circuit product, comprising: a plurality of trenches in a semiconducting substrate that define first, second and third fins in said substrate, wherein said first, second and third fins are positioned side-by-side, and wherein said second fin is positioned between said first and third fins; a layer of insulating material positioned in said plurality of trenches such that a desired height of said first, second and third fins is positioned above an upper surface of said layer of insulating material; a recess defined in said second fin structure that at least partially defines a cavity in said layer of insulating material; an SDB isolation structure positioned in said cavity on said recessed portion of said second fin, wherein said SDB isolation structure has an upper surface that is positioned at a level that is above a level of said upper surface of said layer of insulating material; and a gate structure for a transistor positioned above said SDB isolation structure.