Patent ID: 9502333
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; a first buffer layer formed as a first buffer ring on the insulating layer at peripheries of the end portions of the conductive vias, wherein an inner surface of the insulating layer is aligned with inner surfaces of the conductive vias, and an inner surface of the first buffer layer is aligned with the inner surface of the insulating layer and the inner surfaces of the conductive vias; and a second buffer layer formed as a second buffer ring at a periphery of the insulating layer in plan view to surround the first buffer layer formed on the insulating layer at the peripheries of the end portions of the conductive vias.