Patent ID: 9471812
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A method comprising: erasing a first memory block, wherein the first memory block includes a first non-volatile memory storage location and a second non-volatile memory storage location; asserting a first indicator at the first non-volatile memory storage location of an integrated circuit to place a memory of the integrated circuit in a censorship mode of operation, wherein, as a result of being in the censorship mode, access requests from a debug module of the integrated circuit to access the memory need to be authenticated, while access requests from an instruction-based processor to access the memory of the integrated circuit do not need to be authenticated, wherein the erasing the first memory block occurs prior to the asserting the first indicator; and asserting a second indicator at a first one-time programmable (OTP) non-volatile memory location to place the memory in a permanent censorship mode of operation, wherein as a result of being in the permanent censorship mode instructions executed at the instruction-based processor are prevented from erasing the first storage location, wherein asserting the second indicator occurs after asserting the first indicator, wherein the second indicator comprises a plurality of bits, and asserting the second indicator comprises programming at least a predetermined number of the plurality of bits irrespective of a value of the second indicator; and authenticating a first access request of the access requests from the debug module based on a secure access key stored at the second non-volatile memory storage location of the integrated circuit, wherein as a result of being in the permanent censorship mode the instructions executed at the instruction-based processor are prevented from erasing the second storage location.