Patent ID: 9448953
Filing Date: 2016-09-20
CPC Classification: G06F,Y02D

Claim Text:
1. A computer system comprising a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, and a DDR memory connected to the memory controller via a DDR-PHY interface (DFI), the computer system comprising: a bus monitor connected to the system bus to monitor a frequency of access requests from the CPU to the memory subsystem, the bus monitor including an up/down counter for counting a number of access requests and a number of requests other than access requests, the up/down counter counts an access request as plus one (+1) and a request other than an access request and a system bus idle state as minus one (−1) after a cycle end signal has been received from the system bus; a latency changing means for sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor, the latency changing means includes a register, and a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in the register, and in response to the comparison result of the comparator, the latency changing means generates clock gate signals to decimate an operating clock of the memory controller, generates CKE gate signals to decimate an operating clock of the DDR memory, and generates dummy cycle signals to delay the timing of the signal data output from the memory controller to the system bus.