Patent ID: 9257435
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A manufacturing method for a semiconductor device having a memory circuit and a logic circuit over a substrate, the method comprising the steps of: forming an insulating layer over the substrate, forming a wiring groove in the insulating layer, and forming a metal film embedding the wiring groove; forming a cap film over the metal film after planarizing the metal film; forming a concave part by removing a part of the cap film and the insulating layer, wherein the concave part is configured by a hole and a wiring groove which is continuously located outside of the hole, the wiring groove disposed above the hole; embedding a lower part electrode, a capacitor insulating film and an upper part electrode in the concave part, and forming a metal film for an upper part coupling wiring in the concave part and over the cap film; and forming an upper part coupling wiring by selectively removing the metal film for the upper part coupling wiring over the cap film such that an upper surface of the upper part coupling wiring and an upper surface of the cap layer are in a same plane, the capacitance element being embedded in the hole, the upper part coupling wiring being embedded in the wiring groove and in the hole physically contacting the upper electrode part both in the wiring groove and in a lower region of the hole.