Patent ID: 9444462
Filing Date: 2016-09-13
CPC Classification: H03K

Claim Text:
1. An integrated circuit comprising: an output buffer having an output buffer delay, a signal input and a signal output, the output buffer having a variable number of a plurality of output drivers that are on, in response to output driver control signals; and a plurality of sequential circuits receiving as input first and second timing signals, wherein relative timing of the first and second timing signals determines the variable number of output drivers; a control circuit: (i) using a first circuit to generate the first timing signal with a first delay, (ii) using a second circuit to generate the second timing signal with a second delay that correlates with the output buffer delay, (iii) using the plurality of sequential circuits to generate the output driver control signals, and (iv) causing the variable number of the plurality of output drivers to be on, in response to the output driver control signals.