Patent ID: 9275589
Filing Date: 2016-03-01
CPC Classification: G09G

Claim Text:
1. A gate drive circuit, comprising: a plurality of shift register units each having a signal output end, wherein the signal output end of one of the plurality of shift register units except the last one is connected to the signal input end of the next one; L arithmetic units each having a plurality of input ends, wherein L is an integer equal to or larger than 2, and one of the plurality of input ends of each of the L arithmetic units is connected to the signal output end of a respective shift register unit; and a clock generation unit having a plurality of clock output ends for outputting different clock signals, wherein at least one of the plurality of clock output ends is connected to at least one of the other input ends of a respective arithmetic unit except the one input end connected to the signal output end of the shift register unit, so that the L arithmetic units output L different drive signals, wherein the clock generation unit comprising: wherein at least one of the first clock output ends and the second clock output ends is connected to the at least one of the other input ends of each of the L arithmetic unit, so that L clock output ends of the clock generation unit consist of first clock output ends of the sub clock generation unit and second clock output ends of the sub shift register unit.