Patent ID: 9236097
Filing Date: 2016-01-12
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: two memory cell arrays; two column switch arrays respectively coupled to the two memory cell arrays; a sense amplifier shared by the two memory cell arrays and the two column switch arrays; and a control circuit configured to control data readout from the two memory cell arrays; wherein each of the two memory dell arrays includes: wherein the n bit lines of each of the two memory cell arrays and coupled to the same sense amplifier via the respective one of the column switch arrays and a common bit line that is commonly coupled to the n bit lines via the respective one of the column switch arrays, wherein when the control circuit reads data from one memory cell array of the two memory cell arrays, the control circuit activates the dummy word line included in other memory cell array of the two memory cell arrays and generates, with the dummy cell included in the other memory cell array, a reference level of the sense amplifier; and wherein: each of the two column switch arrays includes: the sense amplifier is coupled to the two memory cell arrays via the common bit lines; and when the control circuit reads data from the one memory cell array, the control circuit switches a selected column switch corresponding to the memory cell, from which the data is to be read, out of the n column switches in the one memory cell array and the n column switches in the other memory cell array to a conductive state to activate the word line corresponding to the memory cell, from which the date is to be read, in the one memory cell array and the dummy word line in the other memory cell array.