Patent ID: 9484445
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: an active region including: an edge termination structure portion surrounding the outer periphery of the active region; a second conductivity type collector layer provided on a second main surface side of the first conductivity type semiconductor substrate; a second conductivity type isolation layer provided in an outer peripheral portion of the edge termination structure portion so as to link the first main surface and the second main surface of the first conductivity type semiconductor substrate and electrically connected to the second conductivity type collector layer; and a first conductivity type low lifetime adjustment region provided separated from the second conductivity type base region and second conductivity type collector layer in a position inside the drift region deeper than the bottom surface of the second conductivity type base region from the one main surface of the first conductivity type semiconductor substrate, wherein the first conductivity type low lifetime adjustment region is provided from the active region to the second conductivity type isolation layer, wherein the center in the depth direction of the first conductivity type low lifetime adjustment region is positioned in a depth range of within 20 μm to the second conductivity type collector layer side from the bottom surface of the outermost second conductivity type base region in the active region wherein, after the insulated gate structure and a required metal electrode film are formed on the first main surface side of the first conductivity type semiconductor substrate, the first conductivity type low lifetime adjustment region is formed by protons being implanted from the other main surface side of the first conductivity type semiconductor substrate, and a thermal annealing process is performed, and wherein the protons are implanted in a dose range of 5.0×10