Patent ID: 9299678
Filing Date: 2016-03-29
CPC Classification: H01L,H05K

Claim Text:
1. A semiconductor package comprising: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure, wherein the warpage preventing member is made of silicon, glass, ceramic, or compound semiconductor, wherein the wiring structure includes a plurality of wiring layers and a plurality of insulating layers, which are alternately stacked, with at least one of the plurality of wiring layers being electrically connected to the semiconductor chip, and a via that passes through the plurality of insulating layers and electrically connects the plurality of wiring layers to each other, wherein the warpage preventing member is spaced and electrically independent from the plurality of wiring layers of the wiring structure, the via of the wiring structure, and the semiconductor chip, wherein the warpage preventing member is disposed in one of the insulating layers so as to face the semiconductor chip, and wherein the warpage preventing member is a dummy chip.