Patent ID: 9524827
Filing Date: 2016-12-20
CPC Classification: H01G,H05K

Claim Text:
1. A multilayer ceramic capacitor, comprising: a ceramic body in which dielectric layers having first via holes are stacked in a thickness direction; first internal electrodes having second via holes disposed in positions corresponding to those of the first via holes and exposed to all of the side surfaces of the ceramic body; second internal electrodes having third via holes disposed in positions corresponding to those of the first and second via holes; a via electrode passing through the first to third via holes to thereby be exposed to upper and lower surfaces of the ceramic body, and connected to the third via holes; and a first external electrode disposed on all of the side surfaces of the ceramic body to be connected to a portion of the first internal electrode exposed to an exterior of the ceramic body, wherein the first internal electrodes are respectively disposed on a plurality of first planes, and the second internal electrodes are respectively disposed on a plurality of second planes, each of which is apart from the plurality of first planes, wherein an area of a region defined by an outline of the first internal electrode having the second via hole is greater than that of a region defined by an outline of the second internal electrode having the third via hole, and a size of the second via hole is greater than that of the third via hole, wherein an interior region defined by an outline of the second via hole is filled only with a combination of the via electrode and a dielectric material, wherein an entire outer edge of the second internal electrode overlap with the first internal electrode in the thickness direction, and wherein the second internal electrode directly contacts the via electrode.