Patent ID: 9299408
Filing Date: 2016-03-29
CPC Classification: G06F,G11C,H01L,H03K,H03L,Y02D

Claim Text:
1. A memory system, comprising: a memory controller; a memory device; a first signal line to couple a first set of pins on the memory controller with a first set of pins on the memory device, wherein the first signal line carries a clock signal having a clock signal frequency; a second signal line to couple a second set of pins on the memory controller with a second set of pins on the memory device, wherein the second signal line carries a data signal whose bits are timed according to the clock signal; wherein the memory controller includes circuitry to modify the clock signal frequency from a first frequency value to a second frequency value, wherein bits of the data signal continue to be timed according to the clock signal while the clock signal frequency changes from the first frequency value to the second frequency value.