Patent ID: 9379031
Filing Date: 2016-06-28
CPC Classification: G02F,G09G,H01L

Claim Text:
1. A display panel, comprising: a plurality of gate lines and data lines; an active area having a plurality of pixels, each of which is defined at an intersection area between a respective gate line and data line; a plurality of signal pads arranged in a non-active area, each signal pad configured so as to apply a gate signal or a data signal to a respective gate line or data line; a test wiring portion arranged opposite to the active area relative to a cutting line of the display panel, the test wiring portion electrically connected to the plurality of signal pads in order to be used in a test of the display panel; a plurality of jumping wirings, each jumping wiring being interposed between a respective signal pad and the test wiring portion and electrically connecting the signal pad with the test wiring portion, the jumping wirings being formed of a material different from that of the signal pads and the test wiring portion, and the jumping wirings being on a layer different from that of the signal pads and the test wiring portion, wherein the signal pads and the test wiring portion are formed of a gate metal material or a source/drain metal material, and the jumping wirings are formed of a material of a pixel electrode.