Patent ID: 9461852
Filing Date: 2016-10-04
CPC Classification: G06K,H04B,H04L

Claim Text:
1. A signal demodulation apparatus, comprising: a clock generation device, arranged to generate a clock signal according to an inputting modulation signal; and a demodulation device, arranged to demodulate the inputting modulation signal to generate a demodulation signal according to the clock signal; wherein a signal edge of the clock signal substantially aligns to a turning point of the inputting modulation signal; wherein the clock generation device comprises: a comparator, having a first input terminal for receiving the inputting modulation signal; a first transistor, having a first connecting terminal for receiving the inputting modulation signal, a second connecting terminal coupled to a second input terminal of the comparator, and a controlling terminal coupled to an output terminal of the comparator; a second transistor, having a controlling terminal coupled to the output terminal of the comparator, and a first connecting terminal coupled to a reference voltage; a resistor, having a first terminal coupled to a second connecting terminal of the second transistor, and a second terminal coupled to the second connecting terminal of the first transistor; and a capacitor, having a first terminal coupled to the second connecting terminal of the first transistor, and a second terminal coupled to the reference voltage; wherein the clock signal is a signal on the output terminal of the comparator.