Patent ID: 9424924
Filing Date: 2016-08-23
CPC Classification: G11C,H01L

Claim Text:
1. A non-volatile semiconductor memory device including one or more memory cells each provided with a memory transistor having a floating gate into which carriers can be injected and a transistor sharing the floating gate with the memory transistor, wherein: the memory transistor includes an N-type or P-type impurity diffusion layer formed in an active region, and a P-type or N-type opposite polarity type impurity diffusion layer formed in the active region and having a polarity opposite to the polarity of the impurity diffusion layer; a gate electrode serving as the floating gate is arranged, via a gate insulating film, on the active region between the impurity diffusion layer and the opposite polarity type impurity diffusion layer; the impurity diffusion layer is electrically connected to a program/erase line; the opposite polarity type impurity diffusion layer is short-circuited with the active region and is not electrically connected to the program/erase line; and a channel region between the impurity diffusion layer and the opposite polarity type impurity diffusion layer is made conductive, and thereby carriers are injected into the floating gate by potential generated at the boundary between the channel region and the opposite polarity type impurity diffusion layer, and wherein the transistor has a depletion-type channel region and an enhancement-type channel region formed in a region under the floating gate.