Patent ID: 9460969
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A method of fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices, the method comprising: fabricating the macro according to a fabrication process, the macro being a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas; performing optical critical dimension (OCD) spectroscopy to obtain the measurements of the n-p bumps on the macro; determining an amount of chemical mechanical polishing to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro; performing chemical mechanical polishing to remove the n-p bumps on the macro; and utilizing the amount previously determined for the macro to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.