Patent ID: 9356511
Filing Date: 2016-05-31
CPC Classification: H02M

Claim Text:
1. A control circuit, comprising: a hysteresis comparator configured to receive an error voltage and to generate first and second logic signals that become logically active respectively when the error voltage is below a lower threshold and above a higher threshold; a set/reset flip-flop configured to generate a regulator control signal according to the logic values assumed by said first and second logic signals; a first monostable multivibrator configured to output a first logic value for a minimum time interval starting from an active edge of said first logic signal, and to otherwise output a second logic value; a second monostable multivibrator configured to output a third logic value for a maximum time interval starting from the active edge of said first logic signal and to otherwise output a fourth logic value; and logic gates configured to reset said set/reset flip-flop when said second logic signal is active and said first monostable multivibrator outputs the second logic value to prevent reset of said set/reset flip-flop by said second logic signal before the minimum time interval has elapsed from the active edge of said first logic signal, the logic gates are configured to reset said set/reset flip-flop when said second monostable multivibrator outputs the fourth logic value to ensure reset of said set/reset flip-flop by the end of the maximum time interval from the active edge of the first logic signal.