Patent ID: 9377510
Filing Date: 2016-06-28
CPC Classification: G01R

Claim Text:
1. A method for testing an integrated circuit, said method comprising: multiplexing a test clock with a functional clock on said integrated circuit at a root of a clock tree to produce a second clock signal; dividing the second clock signal into multiple branches, wherein each branch is operable to be delayed by a plurality of delay elements, and wherein each branch is delayed by a different number of delay elements of the plurality of delay elements to produce a plurality of lines with variable delay; routing each line of said plurality of lines with variable delay to a respective plurality of cores and a cache on said integrated circuit, wherein each of the plurality of cores and the cache is operable to be subdivided into a plurality of partitions; and staggering a third clock signal received by each of the plurality of cores and the cache during a scan shift cycle, wherein the third clock signal is derived from the second clock signal and routed using a respective line of said plurality of lines.