Patent ID: 9449672
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A DRAM memory interface for transmitting signals between a memory controller device and a DRAM memory device, the DRAM memory interface comprising: data lines for transmitting data signals; one or more control lines for transmitting control signals; one or more address lines for transmitting address signals; for each line, a transmitter device connected to a first end of the line and a receiver device connected to a second end of the line; wherein each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line; wherein at the first end of the line a first impedance and a first transistor selectively connect the line to a second reference voltage line higher than the first reference voltage line, whereby actuation of the transistor is operative to transmit a signal by driving the line between two digital states represented by voltage levels; and wherein at the second end of the line a second impedance is connected between the line and the first reference voltage line, and wherein return current flows through the second impedance when a signal is transmitted on the line.