Patent ID: 9342404
Filing Date: 2016-05-17
CPC Classification: G06F

Claim Text:
1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of first memory cells, and the decoding method comprises: reading the first memory cells according to a first read voltage to obtain a plurality of first verification bits; performing a first hard bit mode decoding procedure according to the first verification bits, and determining whether the first hard bit mode decoding procedure generates a first valid codeword by a first correcting circuit; if the first valid codeword is generated by the first hard bit mode decoding procedure, outputting the first valid codeword; if the first valid codeword is not generated by the first hard bit mode decoding procedure, performing a second hard bit mode decoding procedure according to the first verification bits, and determining whether the second hard bit mode decoding procedure generates a second valid codeword by a second correcting circuit, wherein a precision of the first correcting circuit is less than a precision of the second correcting circuit; if the second valid codeword is generated by the second hard bit mode decoding procedure, outputting the second valid codeword.