Patent ID: 9461054
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A memory cell of a memory device comprising: a first pull-up transistor and a first pull-down transistor coupled at a first node and connected in series between a first voltage source and a second voltage source, gates of the first pull-up transistor and the first pull-down transistor coupled at a second node; a first access transistor coupled between the first node and a first bit line of the memory device, a gate of the first access transistor coupled to a word line of the memory device; a second pull-up transistor and a second pull-down transistor coupled at the second node and connected in series between the first voltage source and the second voltage source, gates of the second pull-up transistor and the second pull-down transistor coupled to the first node; and a second access transistor coupled between the second node and a second bit line of the memory device, a gate of the second access transistor coupled to the word line of the memory device; wherein the first pull-up transistor, the first pull-down transistor, the second pull-up transistor and the second pull-down transistor each comprise vertical channel transistors having channel regions that extend in a vertical direction relative to a substrate of the memory device, and each comprise gate electrodes at sidewalls of the vertically extending channel regions; wherein the first access transistor and the second access transistor each comprise horizontal channel transistors having channel regions that extend in a horizontal direction of the substrate, and each comprise gate electrodes on the channel regions; and wherein the gate electrodes of the first pull-up transistor, the first pull-down transistor, the second pull-up transistor and the second pull-down transistor and the gate electrodes of the first access transistor and the second access transistor comprise portions of a same layer of material.