Patent ID: 9349588
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method for fabricating a quasi-SOI source/drain field effect transistor device, comprising the steps of: 1) forming an active region of the device on a first semiconductor material, which functions as a substrate, via an isolation technology; 2) depositing a gate dielectric layer and a gate material layer sequentially on the substrate, and forming a gate stack structure of the device via a pre-gate process or a post-gate process, wherein the gate stack structure formed via the pre-gate process is a real gate, and the gate stack structure formed via the post-gate process is a dummy gate; 3) doping a source/drain extension region via implantation technology, and forming a first layer of side wall, with a width of L1, at two sides of the gate stack structure; 4) forming a U-type, Σ-type or S-type recessed source/drain structure; 5) depositing a quasi-SOI source/drain isolation layer via chemical vapor deposition technology, planarizing the quasi-SOI source/drain isolation layer via chemical mechanical polishing technology to stop at the gate material layer, and then forming a quasi-SOI source/drain isolation layer with a thickness of H4 on the recessed source/drain structure by etching back the quasi-SOI source/drain isolation layer via anisotropic dry etching or via isotropic wet etching, wherein the material of the quasi-SOI source/drain isolation layer is different from the material of the first layer of side wall; 6) forming a source/drain by in-situ doping an epitaxial second semiconductor material and activating by annealing; 7) if the pre-gate process is employed in step 2), directly proceeding to step 8); and if the post-gate process is employed, removing the gate stack structure that functions as a dummy gate sacrificial layer and re-depositing a high-k metal gate, including first removing the dummy gate sacrificial layer via wet etching, next re-forming a gate dielectric layer having a high dielectric constant via atomic layer deposition, then re-forming a gate material layer via atomic layer deposition or physical vapor deposition, and finally planarizing the gate material layer via chemical mechanical polishing technology; 8) forming contacts and metal interconnections, so that the fabrication of the quasi-SOI source/drain silicon field effect transistor device is completed.