Patent ID: 9348390
Filing Date: 2016-05-24
CPC Classification: G06F,H02J

Claim Text:
1. A method for reducing power disturbance failover in a storage system by a processor device in a computing environment, comprising: dynamically adjusting power line disturbance hold up times prior to the commencement of the power disturbance failover based on battery capacity of a plurality of batteries in a plurality of racks of the storage system as the plurality of batteries are one of failing, being repaired, and being added to the storage system having at least one uninterruptible power supply (UPS); determining which one of the plurality of racks has a fewest number of remaining batteries of the plurality of batteries having the battery capacity; and determining an amount of the power line disturbance the one of the plurality of racks, having the fewest number of remaining batteries of the plurality of batteries with the battery capacity, is able to support.