Patent ID: 9293225
Filing Date: 2016-03-22
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a first data input/output (I/O) portion suitable for storing data inputted thereto through a first pad in a first cell block in synchronization with a test data strobe signal or a first data strobe signal and suitable for outputting the data stored in the first cell block to the first pad; a second data I/O portion suitable for storing data inputted thereto through a second pad in a second cell block in synchronization with the test data strobe signal or a second data strobe signal and suitable for outputting the data stored in the second cell block to the second pad; and a connection portion suitable for directly connecting the first and second pads to each other in a test mode, wherein the first data I/O portion includes a third pad to which the first data strobe signal is applied when a write operation of the first cell block is executed out of the test mode; and wherein the second data I/O portion includes a fourth pad to which the second data strobe signal is applied when a write operation of the second cell block is executed out of the test mode.