Patent ID: 9472308
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a normal cell region having normal cells; a redundancy cell region having first redundancy cells which are replaced with repair target cells of the normal cells and second redundancy cells which are not replaced with the repair target cells; a fuse unit suitable for programming repair information including replacement information and one of state information and a repair address of the repair target cells; a boot-up unit suitable for performing a boot-up operation to output the repair information programmed in the fuse unit, resetting the repair information based on a test control signal, and performing a reboot-up operation to output the reset repair information; an information update unit suitable for generating the test control signal based on the replacement information and the state information which are outputted through the boot-up operation; a test control unit suitable for generating a test address based on the reset repair information outputted through the reboot-up operation, during a redundancy test operation; and a test unit suitable for selectively testing the second redundancy cells based on the test address.