Patent ID: 9312124
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming a field region defining an active region in a substrate; forming a gate trench in which the active region and the field region in the substrate are partially exposed; forming a gate insulating layer on a surface of the active region exposed in the gate trench, wherein forming the gate insulating layer includes forming a first gate oxide layer by primarily oxidizing the surface of the active region, and forming a second gate oxide layer between the surface of the active region and the first gate oxide layer by secondarily oxidizing the surface of the active region; conformally forming a gate barrier layer including metal on the gate insulating layer and the partially exposed field region; forming a gate electrode layer including metal on the gate barrier layer; and forming a gate capping layer; wherein the gate capping layer is in contact with the gate insulating layer in the gate trench, wherein the gate capping layer is in contact with the gate barrier layer in the gate trench, and wherein the gate capping layer is in contact with the gate electrode layer in the gate trench.