Patent ID: 9379061
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. An integrated circuit device, comprising: a semiconductor substrate; an inter-level dielectric layer arranged over the semiconductor substrate; and an etch-stop layer arranged over the inter-level dielectric layer and having a lower surface that directly contacts an upper surface of the inter-level dielectric layer, the etch-stop layer comprising silicon oxide, silicon nitride, or silicon oxynitride, and having a density greater than or equal to 2.15 g/cm a protective layer arranged over the etch stop layer and having a lower surface that directly contacts an upper surface of the etch stop layer and having an upper surface that directly contacts a low-k dielectric layer; and a conductive plug extending downward though the inter-level dielectric layer and having an upper surface that is co-planar with the lower surface of the protective layer.