Patent ID: 9465896
Filing Date: 2016-10-11
CPC Classification: G01R,G06F

Claim Text:
1. A design for test integrated circuit comprising: a compressor-decompressor (CoDec), wherein the decompressor is constructed by dividing tester input pins into a first set of (p+1) inputs and a second set of q inputs; wherein odd combinations of the first set of (p+1) inputs form first axis inputs in a 2-dimensional grid; wherein second axis inputs for the 2-dimensional grid comprise (i) all combinations of the second set of q inputs, and (ii) for any combinations of the second set of q inputs resulting in an odd number of terms, the combination is replaced by the Exclusive-Or of the second set of q inputs having an odd number of terms and a first input of the first set of (p+1) inputs; and a plurality of scan chains, wherein one of the plurality of scan chains is coupled to an Exclusive-Or gate coupled to intersections of the first axis inputs and the second axis inputs.