Patent ID: 9391207
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a low-temperature polysilicon thin film transistor, comprising the following steps of: 1) forming a polysilicon semiconductor thin film on a substrate; 2) after step 1) is completed, forming a pattern including an active layer on the substrate by a patterning process, wherein the active layer includes a source contact region, a drain contact region, and a semiconductor region provided between the source contact region and the drain contact region, the source contact region and the drain contact region are both conductive, and both of the source contact region and the drain contact region include a semiconductor substrate and ions distributed in the semiconductor substrate; and 3) after step 2) is completed, forming a pattern including a source electrode and a drain electrode of the thin film transistor on the substrate, wherein the source electrode covers the source contact region directly, and the drain electrode covers the drain contact region directly; wherein the step 2) comprises: 21) coating photoresist having a first thickness on the substrate on which the polysilicon semiconductor thin film is formed, exposing and developing the substrate coated with the photoresist having the first thickness, and forming a pattern including a semiconductor substrate, such that a middle region of the semiconductor substrate corresponds to the photoresist having the first thickness, regions at both sides of the semiconductor substrate respectively correspond to photoresist having a second thickness, and the first thickness is larger than the second thickness; 22) performing ashing on the substrate after step 21) is completed, so as to remove the photoresist having the second thickness respectively corresponding to the regions at both sides of the semiconductor substrate, and make the photoresist having the first thickness corresponding to the middle region of the semiconductor substrate become photoresist having a third thickness, wherein the third thickness is equal to the difference between the first thickness and the second thickness; and 23) performing ion implantation on the substrate after step 22) is completed, such that regions on the semiconductor substrate which are not covered by the photoresist having the third thickness become conductor regions, thereby forming a pattern including the active layer, said regions on the semiconductor substrate which are not covered by the photoresist having the third thickness being the source contact region and the drain contact region, and the regions on the semiconductor substrate which are covered by the photoresist having the third thickness being the semiconductor region provided between the source contact region and the drain contact region.