Patent ID: 9293563
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor memory device, comprising: forming, on a silicon substrate, a stacked structure part in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked one on top of another alternately; forming a cell trench in the stacked structure part so as to attain the surface of the substrate; forming a block insulating film, a charge storage layer, and a tunnel insulating film in that order along the sidewall of the cell trench; forming a silicon layer in the cell trench so as to be buried in contact with the tunnel insulating film; forming an element isolating trench in the gate electrode layer and interlayer insulating film in the vicinity of the cell trench; isolating the charge storage layer in a direction perpendicular to the surface of the substrate by etching the interlayer insulating film, block insulating film, charge storage layer, and tunnel insulating film with the control gate electrode as a mask after the formation of the element isolating trench; and forming a new interlayer insulating film in a part where the interlayer insulating film, block insulating film, charge storage layer, and tunnel insulating film have been etched so as to be buried in the part.