Patent ID: 9336004
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. An apparatus, comprising: first rename logic configured to map up to a predetermined number of architectural registers to corresponding first physical registers that hold first values associated with the architectural registers, wherein the mapping is responsive to a transaction modifying at least one of the first values associated with the architectural registers; second rename logic configured to map the architectural registers to second physical registers that hold second values of the architectural registers, wherein the first values are values associated with the corresponding architectural register prior to modification by the transaction and the second values are values associated with the corresponding architectural register following modification by the transaction; and microcode configured to write contents of the first physical registers to a memory in response to the transaction modifying first values associated with a number of the architectural registers that is larger than the predetermined number, and wherein the predetermined number is equal to a number of entries in the first rename logic.