Patent ID: 9424949
Filing Date: 2016-08-23
CPC Classification: G09G,G11C

Claim Text:
1. A shift register circuit, comprising: a first transistor, comprising a first terminal, a second terminal and a control terminal, the first transistor being configured to have the first terminal thereof for receiving a Nth-stage clock signal, and the second terminal thereof functioned as an output terminal of the shift register circuit and for outputting a Nth-stage gate pulse; a capacitor, comprising a first terminal and a second terminal, the capacitor being configured to have the first terminal thereof electrically coupled to the control terminal of the first transistor; a pull-up control circuit, configured to receive a (N−2)th-stage gate pulse and transmit the (N−2)th-stage gate pulse to the control terminal of the first transistor; a first pull-down circuit, configured to determine, according to a (N+2)th-stage gate pulse, whether to pull down a voltage level at the output terminal of the shift register circuit to a preset low voltage level or not and whether to electrically couple the control terminal of the first transistor to the output terminal of the shift register circuit or not; a second pull-down circuit, configured to determine, according to a pull-down control signal, whether to electrically couple the control terminal of the first transistor to the output terminal of the shift register circuit or not and determine whether to pull down a voltage level at the second terminal of the capacitor and a voltage level at the output terminal of the shift register circuit to the preset low voltage level or not; a pull-down control circuit, configured to provide the pull-down control signal and determine a voltage level of the pull-down control signal according a voltage level at the control terminal of the first transistor; and a compensation circuit, configured to generate a compensation pulse and determine whether to output the compensation pulse to the second terminal of the capacitor according a voltage level at the control terminal of the first transistor, wherein an enabled period of one pulse of the Nth-stage clock signal is located in an enabled period of the compensation pulse and the enabled period of the compensation pulse is longer than the enabled period of the pulse of the Nth-stage clock signal.