Patent ID: 9280479
Filing Date: 2016-03-08
CPC Classification: G06F

Claim Text:
1. A memory system for receiving and providing data to a load store unit, the memory system comprising: a first level data cache coupled to the load store unit; a first level write combining queue for the first level data cache coupled to the first level data cache; a second level write merging buffer coupled to the first level write combining queue; a second level data cache coupled to the first level data cache, the first level write combining queue, and the second level write merging buffer; and a third level memory unit coupled between the second level write merging buffer and the second level data cache, the third level memory unit comprises a third level data cache and a forth level memory unit, wherein the memory system determines a destination for data in the second level write merging buffer based on a transaction type of a first write command and a flag entry of the second level write merging buffer that indicates whether each data byte of the second level write merging buffer comprises valid data, wherein the destination is the level two data cache when at least one data byte of the second level write merging buffer comprises invalid data, the destination is the third level data cache when each data byte of the second level write merging buffer comprises valid data and the first write command is not a block write command, and the destination is the forth level memory unit when each data byte of the second level write merging buffer comprises valid data and the first write command is a block write command.