Patent ID: 9368161
Filing Date: 2016-06-14
CPC Classification: G11C,H01L

Claim Text:
1. A nonvolatile memory (NVM) cell, comprising: a semiconductor substrate having therein an N well; a first oxide define (OD) region and a second oxide define (OD) region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the PMOS select transistor and being disposed over the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the N well, wherein an induced voltage coupled from the assistant gate is controlled by a bias of the N Well, wherein the PMOS floating gate transistor serves as a charge storage element of the NVM cell.