Patent ID: 9484457
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a stack of doped semiconductor layers above a doped semiconductor region of a first conductivity type, said stack comprising a top layer of said first conductivity type and a bottom layer of a second conductivity type, said bottom layer forming a PN junction with said doped semiconductor region; forming first trench isolation regions in said stack of doped semiconductor layers; forming combined word lines in said stack of doped semiconductor layers and said first trench isolation regions, said combined word lines extending substantially transversely to said first trench isolation regions; forming second trench isolation regions in said stack of doped semiconductor layers, said second trench isolation regions extending substantially transversely to said first trench isolation regions and laterally delineating, in combination with said first trench isolation regions and said combined word lines, a plurality of pillar structures comprising said top and bottom layers; forming a word line trench isolation region in each of said combined word lines so as to form a first split word line and a second split word line from each of said combined word lines, said word line trench isolation region including an excess material portion extending above said top layer; forming spacers on said excess material portion; etching said plurality of pillar structures using said spacers and said excess material portion as an etch mask to form trenches in said plurality of pillar structures; filling said trenches with an insulating material to form third isolation trenches extending substantially parallel to said first trench isolation regions and further delineate said plurality of pillar structures; and removing said excess material portion and said spacers.