Patent ID: 9407248
Filing Date: 2016-08-02
CPC Classification: H03K

Claim Text:
1. A method for measuring combinatorial path delays between one or more source flip-flops and one or more target flip-flops, given an old clock period and a current clock period, both greater than a normal operating clock period, the method comprising: a. executing one or more diagnostic tests at the current clock period; b. if no failure occurs, setting the old clock period to the current clock period, decrementing the current clock period, and going to a; c. setting a number of clock cycles to 1; d. executing a failed diagnostic test of the one or more diagnostic tests for the number of clock cycles; e. scanning out the contents of the one or more target flip-flops and comparing the scanned out contents with good diagnostic values, and if no mismatch is detected, incrementing the number of clock cycles and going to d; f. for each target flip-flop with a scanned out value that does not match a corresponding good diagnostic value, selecting one or more source flip-flops that, when the values stored in the one or more source flip-flops are toggled, cause a simulated value of the target flip-flop to change, and assigning a delay value equal to the old clock period to a combinatorial path between the source flip-flop and the target flip-flop; and g. decrementing the current clock period, and if the current clock period is greater than a limit, going to a.