Patent ID: 9508846
Filing Date: 2016-11-29
CPC Classification: H01L

Claim Text:
1. A MOS semiconductor device, of a vertical type, comprising: a functional layer, which has a first type of conductivity and is configured to provide a first current-conduction region of said device; first and second gate structures positioned above said functional layer, each gate structure including a dielectric region and an electrode region; first and second body wells, which have a second type of conductivity, are formed within said functional layer, and are separated from one another by a surface separation region of said functional layer; first and second source regions, which have said first type of conductivity, are formed respectively within said first and second body wells, are positioned laterally and partially underneath the first and second gate structures, respectively, and are configured to provide a second current-conduction region of said device, wherein the first and second gate structures extend directly above the first and second body wells, respectively and do not overlap the surface separation region of said functional layer; a first shield structure, arranged at an active area between the first and second gate structures and above the surface separation region of said functional layer; wherein said first shield structure includes a first conductive region configured to be set at a same potential as said source regions; a dielectric layer covering the first and second gate structures and the first shield structure; a first shield contact region positioned in a first hole in the dielectric layer; and a source-metallization layer electrically connected to the conductive region of the first shield structure through the first shield contact region and electrically connected to the first and second source regions.