Patent ID: 9502408
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising: forming a plurality of fins on a substrate by patterning a semiconductor layer to a first thickness and a first height; forming a sacrificial gate stack on portions of the fins in a channel region of the FinFET device; forming source drain junctions in a source drain region of the FinFET device using ion implantation; forming a dielectric layer on the substrate; removing the sacrificial gate stack to expose the portions of the fins in the channel region, wherein the dielectric layer covers remaining portions of the fins in the source drain region; thinning the exposed portions of the fins to a second thickness less than the first thickness, and reducing the exposed portions of the fins to a second height less than the first height, wherein the thinning removes about 50% to about 60% of the first thickness, and wherein each of a resulting height and thickness of the remaining portions of the fins in the source drain region is greater than each of a resulting height and thickness of the portions of the fins in the channel region such that an entirety of the patterned semiconductor layer comprising the fins in the source drain region are at the first height and the first thickness achieved prior to the thinning and reducing; forming a gate stack on the thinned and reduced exposed portions of the fins to replace the removed sacrificial gate stack; etching a plurality of contact holes in the dielectric layer; and filling the contact holes with a conductive material to form contact bars extending across the plurality of fins; wherein the contact bars couple respective portions of the plurality of fins together without epitaxial regions to merge adjacent fins.