Patent ID: 9307611
Filing Date: 2016-04-05
CPC Classification: G09G

Claim Text:
1. A pixel circuit implementing a circuit diagram comprising: a first transistor; a second transistor; a display element; and a memory comprising a first output terminal and a second output terminal, wherein: in the circuit diagram, the first output terminal is directly connected to a gate of the first transistor; in the circuit diagram, the second output terminal is directly connected to a gate of the second transistor; in the circuit diagram, the display element is electrically connected to one of a source and a drain of the first transistor; in the circuit diagram, the display element is electrically connected to one of a source and a drain of the second transistor; in the circuit diagram, the one of the source and the drain of the first transistor is directly connected to the one of the source and the drain of the second transistor; in the circuit diagram, the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the second transistor; and a polarity of the first transistor is different from a polarity of the second transistor.