Patent ID: 9437506
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method of semiconductor manufacture, comprising: in a computer for analyzing a wafer having a number of die (N), counting a number (H) of the die that are included in both a subset of the N die, with a number (D) members, having a defect, as identified from an inspection layer analysis of the wafer, and which also are included in a subset of the N die, which are failing, having a number of failing die (F) identified from a fault test of the wafer; in the computer, dividing H into a number (Hk) of die that are postulated to have a defect that caused a die failure and into a number (Hb) of the die that are postulated to have a defect that did not cause a die failure, wherein the division is based upon the numbers H, D, F, and N, and H=Hk+Hb; in the computer, calculating a number (Hr) of die that has the same proportionality to F as does D to N; in the computer, computing a probability (P(H)) of H occurring and a probability (P(Hr)) of Hr occurring; and adjusting a wafer manufacturing step based at least on P(H) and P(Hr).