Patent ID: 9245898
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A method of forming a nonvolatile memory integrated circuit comprising: depositing a floating gate layer of doped polysilicon across a cell area and across a peripheral area of a substrate; depositing an inter-poly dielectric layer over the floating gate layer in the cell area and in the peripheral area of the substrate; depositing a P+ doped polysilicon layer over the inter-poly dielectric layer in the cell area and in the peripheral area of the substrate; forming a plurality of openings in the P+ doped polysilicon layer and the inter-poly dielectric layer in the peripheral area of the substrate; depositing an N+ doped polysilicon layer over the P+ doped polysilicon layer in the cell area and in the peripheral area of the substrate, the N+ doped polysilicon layer deposited to at least a minimum thickness over the P+ doped polysilicon layer that is sufficient to maintain N+ doping at an upper surface of the N+ doped polysilicon layer; subsequently masking the peripheral area of the substrate while leaving the cell area exposed; subsequently removing material of the N+ doped polysilicon layer from the cell area while leaving the N+ doped polysilicon layer in place in the peripheral area; and subsequently depositing a metal layer over the P+ doped polysilicon layer in the cell area and over the upper surface of the N+ doped polysilicon layer in the peripheral area, a first contact resistance between the metal layer and the upper surface of the N+ doped polysilicon layer being less than a second contact resistance along an interface between the P+ doped polysilicon layer and the metal layer in the cell area.