Patent ID: 9391647
Filing Date: 2016-07-12
CPC Classification: H03M,H04L

Claim Text:
1. A min-sum algorithm low density parity-check code decoder, configured to decode coding data having bit nodes and check nodes, comprising: a calculation module, configured to divide the coding data into a plurality of data groups, comprising: a plurality of calculation units, wherein each calculation unit configured to operatively calculate a respective data group of the data groups, comprises: a check node unit, configured to operatively generate a calculating result in a stored-form by calculating the respective data group; and a first message re-constructor, coupled to the check node unit, configured to operatively reconstruct the calculating result to a calculated-form and summing the calculating result with a following data group; and a second message re-constructor, coupled to the check node unit, configured to operatively reconstruct the calculating result from the stored-form into a outputted-form; and a memory, coupled to the calculation module, comprising: a plurality of memory units, wherein each memory unit is coupled to a respective calculation unit of the calculation units, and configured to store the calculating result generated from the respective calculation unit.