Patent ID: 9471321
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle: determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets; logically ORing a result of testing for a first condition, a second condition, and a third condition to control fetch-ahead of a next Fetch Set, wherein the first condition comprises the number of VLES groups available for dispatch is less than a predetermined starvation threshold, the second condition comprises the number of VLES groups available for dispatch is indicative of going below a predetermined upper limit threshold, and the third condition comprises the number of VLES groups available for dispatch is indicative of being between the predetermined starvation threshold and the predetermined upper limit threshold, and a fetch-ahead of a Fetch Set occurred in an immediately previous cycle; and requesting fetch-ahead of the next Fetch Set in a next cycle only if one or more of the results of testing for the first condition, the second condition, and the third condition is true.