Patent ID: 9530495
Filing Date: 2016-12-27
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device, comprising a plurality of resistive switching memory cells, wherein each resistive switching memory cell comprises: a) a programmable impedance element having an anode and a cathode; b) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; c) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and d) a diode having a cathode at the first diffusion region, and an anode at the third diffusion region, wherein the diode is turned on during an erase operation on the programmable impedance element.