Patent ID: 9343507
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A device comprising one or more field effect transistors, each field effect transistor comprising: an elongated drain contact line comprising an electrically conductive material extending along a first horizontal direction; a drain comprising a first conductivity type semiconductor region overlaying the drain contact line; a source comprising a first conductivity type semiconductor region located above the drain; a gate extending vertically between the drain and the source, wherein: a first channel and a second channel, each comprising a second conductivity type semiconductor region different from the first conductivity type, wherein: the first channel extends vertically from the drain to the source and is located on the first vertical side of the gate and is electrically insulated from the gate by the gate insulating material contacting the first vertical side of the gate; the second channel extends vertically from the drain to the source and is located on the second vertical side of the gate and is electrically insulated from the gate by the gate insulating material contacting the second vertical side of the gate; and the source, the first channel and the second channel collectively constitute a pillar having a single continuous top surface such that a first sidewall surface of the pillar that adjoins a periphery of the top surface of the pillar includes a surface of the first channel and a first surface of the source, and a second sidewall surface of the pillar that adjoins the periphery of the top surface of the pillar includes a surface of the second channel and a second surface of the source.