Patent ID: 9331048
Filing Date: 2016-05-03
CPC Classification: B81C,C25D,H01L

Claim Text:
1. A method comprising: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, wherein the second wafer stack comprises through-silicon vias; applying a second bonding layer to a first surface of the second wafer stack, wherein the through-silicon vias extend from the first surface through the second wafer stack and to the second bonding layer; bonding the second bonding layer to the first bonding layer; and applying a seed layer on a second surface of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the through-silicon vias, and (ii) extends over the first surface and past edges of the second wafer stack and onto the first bonding layer.