Patent ID: 9455725
Filing Date: 2016-09-27
CPC Classification: H03K,H03L

Claim Text:
1. A phase detector, comprising: a plurality of sampling circuits, for respectively using a plurality of clock signals with different phases to sample at least a data signal so as to generate a plurality of sampling results; a logic circuit, coupled to the plurality of sampling circuits, and configured to generate N phase-leading signals and N phase-lagging signals according to the plurality of sampling results; a plurality of demultiplexers, coupled to the logic circuit, and configured to perform demultiplex operations on the N phase-leading signals and the N phase-lagging signals so as to generate M phase-leading output signals and M phase-lagging output signals, respectively, wherein M is bigger than N, M is a positive integral multiples of N, and frequencies of the M phase-leading output signals and the M phase-lagging output signals are lower than frequencies of the N phase-leading signals and N phase-lagging signals; and a decision circuit, coupled to the plurality of demultiplexers, and configured so as to generate a final phase-leading signal and a final phase-lagging signal according to the M phase-leading output signals and the M phase-lagging output signals.