Patent ID: 9330925
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a thin-film transistor, comprising: providing a gate electrode over a substrate; providing an insulating layer over the gate electrode; providing a first amorphous silicon layer over the insulating layer, the first amorphous silicon layer including a channel region between a source region and a drain region; providing an etching protection layer on the channel region of the first amorphous silicon layer; providing a second amorphous silicon layer on the first amorphous silicon layer, the second amorphous silicon layer covering the etching protection layer; providing a source electrode directly on the second amorphous silicon layer and over the source region of the first amorphous silicon layer, the source electrode comprising Ni and a metal other than Ni, the source electrode containing the Ni approximately evenly at a predetermined concentration; providing a drain electrode directly on the second amorphous silicon layer and over the drain region of the first amorphous silicon layer, the drain electrode comprising Ni and a metal other than Ni, the drain electorde containing the Ni approximately evenly at the predetermined concentration; heating the first amorphous silicon layer to a first temperature during a first heating process to diffuse impurities from the second amorphous silicon layer to the first amorphous silicon layer; and distributing the approximately evenly distributed Ni from the source electrode and the drain electrode into the first amorphous silicon layer and the second amorphous silicon layer by heating the thin-film transistor in a furnace to a second temperature during a second heating process to promote uniformity of crystallization, the Ni of the source electrode and the drain electrode diffusing into the first amorphous silicon layer and the second amorphous silicon layer thereby accelerating crystallization of the first amorphous silicon layer and the second amorphous silicon layer into one of a polycrystalline and a microcrystalline semiconductor, wherein the first temperature is lower than the second temperature, outer arcs of the insulating layer, the first amorphous silicon layer, the second amorphous silicon layer, the source electrode, and the drain electrode are not inwards of a periphery of the gate electrode, and extend outside the periphery of the gate electrode, the outer arcs of the insulating layer, the first amorphous silicon layer, the second amorphous silicon layer, and one of the source electrode and the drain electrode being concentric, and the source electrode and the drain electrode are not provided on side surfaces of the first amorphous silicon layer and the second amorphous silicon layer to promote uniformity of crystallization, the side surfaces being perpendicular to a top surface of the substrate.