Patent ID: 9257972
Filing Date: 2016-02-09
CPC Classification: H03K

Claim Text:
1. A flip-flop circuit comprising: a pull-up and a pull-down circuit, wherein each of the pull-up and pull-down circuits is coupled to a data input and is configured to be activated responsive from a clock signal transitioning from a first portion of a clock cycle to a second portion of a clock cycle; a write circuit configured to write data into a latch of the flip-flop circuit responsive to activation of one of the pull-up and pull-down circuits; an output driver circuit including a dynamic portion and a static portion, wherein the dynamic portion is configured to drive an output signal during the second portion of the clock cycle, and wherein the static portion is configured to drive the output signal during the first and second portions of the clock cycle; wherein the write circuit is configured to write input data into the latch concurrent with the dynamic portion of the output driver circuit driving the output signal.