Patent ID: 9373641
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: forming multiple semiconductor bodies comprising at least a first semiconductor body for a first field effect transistor and a second semiconductor body for a second field effect transistor parallel to said first semiconductor body; forming an elongated gate that traverses said multiple semiconductor bodies and that is laterally surrounded by a gate sidewall spacer, said elongated gate comprising a gate conductor layer; and after said forming of said elongated gate, forming an isolation region in a portion of said elongated gate between said first semiconductor body and said second semiconductor body, said isolation region comprising: an opening that extends vertically into said portion of said elongated gate and that cuts at least said gate conductor layer into discrete segments, said opening having a width that is less than a distance between said first semiconductor body and said second semiconductor body and a length that traverses said gate conductor layer; and an isolation layer within said opening positioned laterally between and immediately adjacent to said discrete segments, said isolation region segmenting said elongated gate into a first gate for said first field effect transistor and a second gate for said second field effect transistor and electrically isolating said first gate from said second gate.