Patent ID: 9397306
Filing Date: 2016-07-19
CPC Classification: B82Y,H01L,Y10S

Claim Text:
1. A method of making a thin film transistor, the method comprising: providing an insulating substrate; forming a gate electrode on the insulating substrate, wherein the gate electrode comprises a first carbon nanotube layer with a first film resistor that is smaller than or equal to 10 kΩ per square; applying an insulating layer on the gate electrode; forming a source electrode and a drain electrode on the insulating layer, wherein the source electrode and the drain electrode are spaced from each other, and each of the source electrode and the drain electrode comprises a third carbon nanotube layer, and a film resistor of the third carbon nanotube is smaller than or equal to 10 kΩ per square; forming a semiconductor layer on the insulating layer, wherein the semiconductor layer is in contact with the source electrode and the drain electrode, and the semiconductor layer comprises a second carbon nanotube layer with a second film resistor greater than or equal to 100 kΩ per square; exposing a part of the insulating layer to form a channel by etching a portion of the second carbon nanotube layer that is between the source electrode and the drain electrode, wherein a ratio of a length and a width of the channel is greater than 1.