Patent ID: 9356019
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A planar diode, comprising: a substrate; a diode region including a portion of the substrate, the diode region being electrically isolated from other substrate regions; a first doped layer in the diode region above the substrate; a second doped layer in the diode region above the first doped layer and above a middle undoped layer; the middle undoped layer in the diode region above at least part of the first doped layer; and an external undoped layer outside of the diode region, wherein the external undoped layer comprises a portion of at least one CMOS device in at least one of the other substrate regions, the first doped layer, the second doped layer, the middle undoped layer, and the external undoped layer each being epitaxial layers having a single respective crystal oriented by an orientation of the substrate, the middle undoped layer and the external undoped layer having been formed simultaneously.