Patent ID: 9342415
Filing Date: 2016-05-17
CPC Classification: G06F,H04L

Claim Text:
1. A method of providing a bypass fail open mode for an inline intrusion prevention system comprising the steps of: executing by one or more processors a primary process utilizing a first single logical core as a control plane, the primary process; configuring one or more logical core pools, two or more network ports, and a bypass option; starting one or more bypass threads on at least one logical core separate from the first single logical core, wherein the bypass threads provide a fail-open communications processing between the network ports; and spawning a secondary process; while the primary process owns and performs frame processing using one or more bypass data plane threads: opening an interprocess communication channel by a secondary process control plane with the primary control plane; initializing and invoking by the secondary process one or more intrusion prevention threads comprising an intrusion prevention system data plane, wherein the one or more intrusion prevention threads are executed by one or more logical cores separate from the first logical core to process frames between the network ports; and notifying the primary process by the secondary process via the interprocess communication channel of readiness of the intrusion detection threads; and responsive to receiving the notification, the primary process relinquishing ownership of the network ports and frame processing operations and entering into a quiescent state such that mutual exclusivity between the primary process and the secondary process is achieved in the first logical core.