Patent ID: 9379892
Filing Date: 2016-06-28
CPC Classification: G06F,H04L

Claim Text:
1. A digital processor security device comprising: a central processor unit; a first data bus in data communication with the central processor unit, the first data bus disposed between the central processor and a southbridge controller; a controller hub in data communication with the central processor unit via the first data bus; and a police bridge disposed between the central processing unit and the controller hub on the first data bus, the police bridge operable to passively monitor a state of data communicated via the first data bus by sniffing a state of the bus by hardware logic operating independently of the central processor unit; the police bridge including a trusted certificate manager operable in accordance with encryption protocols associated with a monitored state of the first data bus; the police bridge further operable to generate key data in accordance with a data transmission protocol associated with the state of the first data bus; the police bridge further operable to generates a memory control signal in accordance with a monitored state of the first data bus relative to a generated key; and a second police bridge disposed between the southbridge controller and a super input/output controller.