Patent ID: 9401363
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A vertical transistor device, comprising: a line of active area adjacent a line of dielectric isolation; a buried data/sense line obliquely angling relative to the line of active area and the line of dielectric isolation; a pair of gate lines outward of the buried data/sense line and obliquely angling relative to the line of active area and the line of dielectric isolation, a vertical transistor channel region within the active area between the pair of gate lines; and an outer source/drain region in the active area above the channel region and an inner source/drain region in the active area below the channel region, the inner source/drain region being electrically coupled to the buried data/sense line, the inner source/drain region extending to under a base of the buried data/sense line and being directly against the base of the buried data/sense line.