Patent ID: 9378779
Filing Date: 2016-06-28
CPC Classification: G05F,G11C,H03K

Claim Text:
1. An integrated circuit, comprising: a first circuit stage having an input node coupled to a first supply voltage node and configured to receive a first supply voltage, the input node coupled to an inverter having an output node; a second circuit stage having a first auto-sequencing circuit configured to generate a first holding signal and a second auto-sequencing circuit configured to generate a second holding signal; and a third circuit stage having a pull-up circuit controlled by the first holding signal and configured to hold the output node at a second supply voltage corresponding to a second supply voltage node until the first supply voltage exceeds a threshold and a pull-down circuit controlled by the second holding signal and configured to hold the output node at a reference voltage corresponding to a reference node until the first supply voltage falls below a second threshold.