Patent ID: 9362184
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device comprising the steps of: forming an insulating layer on a semiconductor substrate; and forming at least one layer of Cu wiring in the insulating layer via a composite layer including a barrier layer and a seed layer on the barrier layer and which is provided between the Cu wiring and the insulating layer, where the barrier layer includes Ta crystal and the seed layer includes an alloy crystal layer of Cu and Al, where 60% or more of all grain boundaries configuring crystals of the Cu wiring are coincidence boundaries of Sigma value 27 or less in at least one cross section of the Cu wiring, and where an orientation of a (111) plane is 93% and an orientation of a (200) plane is 1% in the Cu wiring.