Patent ID: 9496418
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A fabricating method of a non-volatile memory, comprising: forming a first conductive layer and a second conductive layer separated from each other on a substrate, wherein a patterned hard mask layer is formed on the first conductive layer and on the second conductive layer, and the patterned hard mask layer exposes a sharp tip of the first conductive layer; forming a first doped region in the substrate at one side of the first conductive layer away from the second conductive layer; forming a second doped region in the substrate at one side of the second conductive layer away from the first conductive layer; and forming a third conductive layer at one side of the first conductive layer away from the second conductive layer, wherein the third conductive layer is located on a portion of the first conductive layer and covers the sharp tip, and the third conductive layer and the first conductive layer are isolated from each other, wherein the first doped region is disposed at least directly below the third conductive layer, and wherein a forming method of the first conductive layer and the second conductive layer comprises: