Patent ID: 9263140
Filing Date: 2016-02-16
CPC Classification: G11C

Claim Text:
1. A non-volatile semiconductor storage device comprising: a memory cell array having an electrically rewritable non-volatile memory cell arranged therein; and a control unit configured to perform controlling of repeating an erase operation to apply an erase pulse voltage to the memory cell for data erase and an erase verify operation to verify whether data erase is completed, the erase pulse voltage including a first erase pulse voltage generated in a first one of the erase operations as an initial one and a second erase pulse voltage generated thereafter in a second one of the erase operations, the control unit being configured to, when control of repeating the erase operation and the erase verify operation is performed, cause the erase pulse voltage to increase by a certain step-up voltage in the erase operation if it is verified that data erase is not completed in the erase verify operation, and the control unit being configured to control the erase pulse voltage such that: at least a voltage wave shape of the first erase pulse voltage when a vertical axis thereof denotes a voltage and a lateral axis denotes time has a blunted wave-shape portion that is continuous to a saturation value thereof, the blunted wave-shape portion being defined by a period in which a gradient at a first point of time is not larger than a gradient at a second point of time before the first point of time in the voltage wave shape through the period; and the first erase pulse voltage is longer than the second erase pulse voltage with respect to a width of the blunted wave-shape portion.