Patent ID: 9276112
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a gate stack disposed on a substrate, wherein said gate stack is comprised of a metal gate electrode above a channel region in said substrate, and a high-k gate dielectric layer between said metal gate electrode and said channel region and along sidewalls of said metal gate electrode; an inter-layer dielectric film directly adjacent to portions of said high-k gate dielectric layer along the sidewalls of said metal gate electrode; a pair of source/drain regions in said substrate on either side of said channel region, wherein said pair of source/drain regions is in direct contact with said high-k gate dielectric layer, and wherein a lattice constant of said pair of source/drain regions is different than a lattice constant of said channel region, said pair of source/drain regions having an undercut profile of approximately 55 degrees with respect to a horizontal axes; and regions of boron out-diffusion in said substrate and adjacent to a periphery of said pair of source/drain regions, wherein the regions of boron out-diffusion have a concentration of boron atoms approximately in the range of 1×10