Patent ID: 9318185
Filing Date: 2016-04-19
CPC Classification: G11C

Claim Text:
1. A memory module comprising: first through N-th memory devices, each of the first through N-th memory devices being divided into first through M-th regions, each of the first through N-th memory devices including a max-count address generator, wherein for each of the max-count address generators, the max-count address generator is configured to count a number of accesses to a row address included in respective J-th regions of the first through N-th memory devices and is configured to output a max-count address information when the number of the counted accesses reaches a threshold value, where M and N are integers equal to or greater than 2, and J is a natural number equal to or less than M; and a buffer unit configured to receive the max-count address information from the first through N-th memory devices and configured to output a target row address to refresh memory cells of the target row address of the first to N-th memory devices corresponding to the max-count address information, wherein each of the max-count address generators is configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.