Patent ID: 9449694
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A non-volatile memory circuit, comprising: an array of non-volatile memory cells fainted according to a NAND architecture as a plurality of blocks, each block formed of a plurality of NAND strings having multiple memory cells connected in series and connected along word lines; bias circuitry providing bias voltage levels for use in the operation of the array; and decoding circuitry whereby the bias circuit is connectable to the array to selectively apply the bias voltage levels thereto, wherein, when performing a programming operation on a selected word line, the decoding circuitry applies a programming voltage to the selected word line while applying a pass voltage to the other word lines of the block to which the selected word line belongs, the programming voltage being higher that the pass voltage, and wherein, when performing a multi-word line stress operation on a first plurality of selected word lines of a first block in which the first plurality of selected word lines are a contiguous group of word lines of the first block, the decoding circuitry applies a stress voltage concurrently to the first plurality of selected word lines while applying the pass voltage to non-selected word lines of the first block, the stress voltage being higher than the pass voltage.