Patent ID: 9437799
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, the method comprising: providing a substrate including silicon-based semiconductor material; forming isolation trenches in the substrate between active areas of the integrated circuit to laterally isolate active areas for an NMOS transistor and a PMOS transistor in an area for CMOS transistors of the integrated circuit, and for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit, the n-type thermoelectric elements and the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position; subsequently implanting n-type dopants into the substrate to form an n-type region having a doping density of at least 1×10 subsequently forming dielectric material in the isolation trenches to provide field oxide of the integrated circuit; and forming a metal interconnect structure which connects upper ends of the n-type thermoelectric elements and the p-type thermoelectric elements to a thermal node.