Patent ID: 9343662
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A method of forming a device comprising: providing a substrate; performing front end of line processing to form circuit components on the substrate; and performing back end of line processing to form an uppermost inter level dielectric (ILD) layer of the device, the uppermost ILD layer includes a metal level over a via level, wherein the metal level comprises first and second metal lines having top surfaces which are coplanar with a top surface of the uppermost ILD layer; forming a pad level over the uppermost ILD layer, wherein forming the pad level comprises providing a storage unit of a memory cell in the pad level, wherein a bottom surface of the storage unit completely contacts the top surface of the first metal line of the uppermost ILD layer without covering the entire first metal line, and wherein top surface of the storage unit is coplanar with top surface of the intermediate dielectric layer; and forming a cell interconnect and a pad interconnect in the pad level, wherein forming the cell interconnect and the pad interconnect comprises