Patent ID: 9330212
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. a non-transitory computer-readable recording medium in which a circuit simulator program of a simulation of a circuit using design data of the circuit is stored, the program instructing a computer to execute a process comprising: obtaining a number of longest continuous bits that continues a same value the longest in a test pattern previously set for generating an eye pattern of the circuit; simulating a rising step response to a rising step signal input into the circuit; simulating a falling step response to a falling step signal input into the circuit; analyzing a result of the simulating of the rising step response and the falling step response; generating, based on the number of longest continuous bits and a result of the analyzing the rising step response and the falling response, an upper part test pattern that defines a shape of an upper part of an eye of the eye pattern and a lower-part test pattern that defines a shape of a lower part of the eye of the pattern, wherein in the generating of the upper-part test pattern, the program instructs the computer to execute a process further comprising calculating, based on the result of the analyzing of the falling step response, a falling peak time width from a falling start time of the falling step response to a time when the falling step response reaches a minimum within a longest continuous bit time that is the product of the number of longest continuous bits and a time for one bit; and simulating a response to the upper-part test pattern and the lower-part test pattern both input into the circuit.