Patent ID: 9324428
Filing Date: 2016-04-26
CPC Classification: G11C

Claim Text:
1. An operation method for a memory device, including: determining an operation state of the memory device; when the memory device is determined to be operated in a first operation state, applying a reset pulse to the memory device; when the memory device is determined to be operated in a second operation state, applying the reset pulse and at least a first incremental pulse set verification current to the memory device, an allowable maximum current of the first incremental pulse set verification current being lower than a melt current; when the memory device is determined to be operated in a third operation state, applying the reset pulse and at least a first identical pulse set verification current to the memory device, an allowable maximum current of the first identical pulse set verification current being lower than the melt current; and when the memory device is determined to be operated in a fourth operation state, applying a set pulse to the memory device.