Patent ID: 9418901
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a stack of semiconductor layers over a substrate, each semiconductor layer in the stack of semiconductor layers having a different band gap than an adjacent semiconductor layer in the stack of semiconductor layers; forming a capping layer over the stack of semiconductor layers, the capping layer comprising a first source opening, a first drain opening, a second source opening, and a second drain opening; simultaneously forming first and second source and drain features in the respective first and second source and drain openings; forming a first gate opening in the capping layer between the first source feature and the first drain feature; forming a gate dielectric layer in the first gate opening; after forming the gate dielectric layer, forming a second gate opening in the capping layer between the second source feature and the second drain feature; and simultaneously forming a gate electrode layer in the first gate opening and the second gate opening.