Patent ID: 9472463
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a plurality of semiconductor fins on a substrate; forming a gate structure over a portion of each of the plurality of semiconductor fins; forming a first organic planarization layer (OPL) over the substrate to cover the plurality of semiconductor fins and the gate structure; recessing the first OPL to expose an upper portion of the gate structure, wherein remaining portions of the first OPL on opposite sides of the gate structure have uppermost surfaces located above top surfaces of the plurality of semiconductor fins; forming a second OPL over the remaining portions of the first OPL and the gate structure; forming a hard mask layer over the second OPL; patterning a stack of the hard mask layer, the second OPL and the remaining portions of the first OPL to expose portions of a first set of the plurality of semiconductor fins that are not covered by the gate structure and to leave a second set of the plurality of semiconductor fins covered; removing remaining portions of the hard mask layer; removing remaining portions of the second OPL; and implanting a first type dopant into portions of the exposed portions of the first set of the plurality of semiconductor fins on opposite sides of the gate structure to form source and drain regions in the first set of the plurality of semiconductor fins.