Patent ID: 9412620
Filing Date: 2016-08-09
CPC Classification: C23C,H01L

Claim Text:
1. A method for fabricating three-dimensional integrated circuits, the method comprising: etching crystalline substrate within an area of a substrate side of a donor semiconductor wafer, the substrate side having a substrate thickness and being located opposite a donor wafer membrane comprising a device layer of the donor semiconductor wafer and a buried insulating layer, to remove at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface; and supporting the donor semiconductor wafer with a supporting structure, the supporting structure allowing the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching wherein the method further comprises: before the etching, coating the device layer of the donor semiconductor wafer with a first polymer film that is resistant to etching chemistries.