Patent ID: 9274168
Filing Date: 2016-03-01
CPC Classification: G01R,G06F

Claim Text:
1. A method to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1, each clock domain having one or more clocks and one or more scan cells; said method comprising the steps of: (a) generating and shifting-in test stimuli to said scan cells within two or more said N clock domains in said integrated circuit or circuit assembly during a shift operation; (b) applying one or more first capture clock pulses to the scan cells within a first clock domain, followed by applying another one or more second capture clock pulses to the scan cells in a next clock domain during a capture operation such that solely said first capture clock pulses and said second capture clock pulses are included in the capture window, wherein each selected clock must contain at least one said capture clock pulse, and when detecting or locating selected delay faults within a clock domain, said selected clock controlling the clock domain contains two or more consecutive capture clock pulses; and (c) analyzing output responses of said scan cells to detect or locate said faults therein.