Patent ID: 9405586
Filing Date: 2016-08-02
CPC Classification: G06F,G06T,G09G

Claim Text:
1. A multiple graphics processing unit (GPU) system comprising: a hardware hub including a hub router positioned on a bus between a chipset and a plurality of GPUs for routing data and commands over a graphic pipeline between the chipset and one or more display units; a software hub driver for issuing commands for controlling said hub router and determining one or more parallelization modes of operation; wherein said hub router routes said data and commands according to the parallelization mode determined by the software hub driver, said parallelization mode supporting one of: (a) an object division mode; (b) an object division mode and an image division mode; (c) an object division mode and a time division mode; (d) an object division mode and an image division mode and a time division mode; wherein the software hub driver is configured to issue commands to execute one of: (a) or (b) or (c) or (d); and wherein said hardware hub additionally comprises an auxiliary memory for storing data and wherein the stored data comprises intermediate processing results from one or more GPUs of said plurality of GPUs, composition data, and processed data for display.