Patent ID: 9263277
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness, and wherein a sidewall of the first sidewalls in closest proximity to the N-gate structure and a sidewall of the second sidewalls in closest proximity to the P-gate structure are laterally separated from each other; and a dummy work function metal layer over the isolation region, the dummy work function metal layer comprising a third bottom portion and third sidewalls, wherein a first height of the first sidewalls of the P-work function metal layer and a second height of the second sidewalls of the N-work function metal layer are less than a third height of the third sidewalls of the dummy work function metal layer.