Patent ID: 9236321
Filing Date: 2016-01-12
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor chip comprising a principal surface and a plurality of MIS (Metal Insulator Semiconductor) type FETs (Field Effect Transistors) formed in said principal surface; and a plurality of metal plate wires, each of which has a pectinate shape, formed so as to cover said principal surface so that the pectinate parts are allocated alternately in a planar view, and said plural metal plate wires are electrically coupled to a plurality of terminals located outside said semiconductor chip, wherein said plural metal plate wires include a first metal plate wire, a second metal plate wire, and a third metal plate wire; said plural terminals include an input terminal, an output terminal, and aground terminal; said first metal plate wire is electrically coupled to said input terminal, said second metal plate wire is electrically coupled to said output terminal, and said third metal plate wire is electrically coupled to said ground terminal, respectively; and said input terminal, said output terminal, and said ground terminal are located outside said semiconductor chip, respectively.