Patent ID: 9449660
Filing Date: 2016-09-20
CPC Classification: G11C,H03L

Claim Text:
1. A sampling circuit module, comprising: a delay-locked loop, comprising: a control circuit, configured to receive a reference clock signal to output a first control signal; and a delay circuit, coupled to the control circuit and comprising: a sampling circuit, coupled to the delay-locked loop and configured to receive the third delay clock signal and sample a data signal according to the third delay clock signal to obtain sampled data, wherein a first delay stage of the first delay line circuit is changed from a first stage to a second stage when the first delay line circuit is in an idle state and the third delay clock signal is outputted, wherein a second delay stage of the second delay line circuit is changed from a third stage to a fourth stage when the second delay line circuit is in the idle state and the third delay clock signal is outputted.