Patent ID: 9472263
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a column driver; a bit line; a word line; a memory cell comprising a first transistor and a capacitor; and a second transistor including a back gate, wherein a source of the first transistor is electrically connected to the bit line, wherein a drain of the first transistor is electrically connected to one electrode of the capacitor, wherein a gate of the first transistor is electrically connected to the word line, wherein a drain of the second transistor is electrically connected to the bit line, wherein a source of the second transistor is electrically connected to the column driver, wherein a potential of the back gate of the second transistor is lower than a minimum potential of the word line, and wherein each of the first transistor and the second transistor comprises a semiconductor with a bandgap of 2.5 electron volts or more.