Patent ID: 9401725
Filing Date: 2016-07-26
CPC Classification: H03M

Claim Text:
1. A circuit arrangement for suppressing offset, offset drift, and 1/f noise during analog/digital conversion, the circuit arrangement comprising: an analog/digital converter configured to convert an analog input signal into output data; an inverter configured to invert the input signal; at least one switching element connected upstream of the analog/digital converter and downstream of the inverter and configured to periodically change over between the input signal and the inverted input signal at a predefinable switching frequency, wherein the predefinable switching frequency is higher than a 1/f noise frequency and less than a conversion frequency of the analog/digital converter; and a switchable negator circuit connected downstream of the analog/digital converter and configured to periodically negate the output data from the analog/digital converter at the same predefinable switching frequency, wherein the output data is negated when the inverted input signal is applied to the analog/digital converter, wherein the offset, the offset drift, and the 1/f noise are converted into a high-frequency alternating signal without offset and without an imaging effect for a magnetic resonance high-field system.