Patent ID: 9455009
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A semiconductor device, comprising: memory blocks including select transistors electrically coupled to local select lines and memory cells electrically coupled to local word lines; a first connection circuit configured to electrically couple the local select lines of a selected memory block and global select lines according to a block select signal, and formed in a first well region of a substrate; and a second connection circuit configured to electrically couple the local word lines of the selected memory block and global word lines according to the block selection signal, and formed in a second well region of the substrate, wherein the first well region is isolated from the second well region, and the first connection circuit and the second connection circuit comprise NMOS transistors, each of the first well region and the second well region comprises a P well, and the P well of the first well region and the P well of the second well region are formed in a same N well.