Patent ID: 9443871
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device structure, the method comprising: providing a substrate with a semiconductor-on-insulator (SOI) configuration, said SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate; forming trench isolation structures delineating a first region and a second region within said SOI substrate; removing said semiconductor layer and said BOX layer in said first region for exposing said semiconductor bulk substrate within said first region; forming a first semiconductor device with an electrode in and over said exposed semiconductor bulk substrate in said first region; forming a second semiconductor device in said second region, said second semiconductor device comprising a gate structure disposed over said semiconductor layer and said BOX layer in said second region; and performing a polishing process for defining a common height level to which said electrode and said gate structure both substantially extend.