Patent ID: 9397200
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A method of forming a transistor device comprised of source/drain regions and a channel region, the method, comprising: forming a sacrificial gate structure above a substantially vertically oriented structure, said structure extending across said source/drain regions and said channel region and comprising a first sacrificial semiconductor material and a second semiconductor material positioned above said first sacrificial semiconductor material; forming a sidewall spacer adjacent said sacrificial gate structure; after forming said sidewall spacer, forming epi semiconductor material in said source/drain regions; performing at least one etching process to remove said sacrificial gate structure so as to define a replacement gate cavity and to expose at least said first and second semiconductor materials within said gate cavity; with said epi semiconductor material in position in said source/drain regions, performing an etching process through said replacement gate cavity to selectively remove said exposed first sacrificial semiconductor material within said gate cavity relative to said exposed second semiconductor material so as to define a gap under said second semiconductor material within said gate cavity; filling said gap with an insulating material; and forming a replacement gate structure in said gate cavity around at least a portion of said second semiconductor material.