Patent ID: 9495930
Filing Date: 2016-11-15
CPC Classification: G09G,G11C

Claim Text:
1. A shift register, comprising: multi-level shift register units, in which control signal input ends of odd-number-level shift register units are inputted with a first control signal and control signal input ends of even-number-level shift register units are inputted with a second control signal; a first connecting thin film transistor (“TFT”) set, in which first electrodes of the TFTs in the first connecting TFT set are connected to gate electrode signal output ends of the odd-number-level shift register units, gate electrodes of TFTs in the first connecting TFT set are connected to a timing controller and configured to receive the first control signal transmitted by the timing controller, second electrodes of the TFTs in the first connecting TFT set are connected to gate electrode signal output ends of the even-number-level shift register units; and a second connecting TFT set, in which first electrodes of the TFTs in the second connecting TFT set are connected to gate electrode signal output ends of the even-number-level shift register units, gate electrodes of TFTs in the second connecting TFT set are connected to the timing controller and configured to receive the second control signal transmitted by the timing controller, second electrodes of the TFTs in the second connecting TFT set are connected to gate electrode signal output ends of the odd-number-level shift register units, wherein each shift register unit in the multi-level shift register units comprises: a first capacitor, a pre-charging module, a pulling-up module, a reset control module and a pulling-down module; wherein the pre-charging module is connected to a start signal input end, the pulling-down module, a first end of the first capacitor, the pulling-up module respectively, configured to pre-charge the first capacitor in a first stage; the pulling-up module is connected to a first clock signal input end, the first capacitor, the pre-charging module, the pulling-down module and the gate electrode signal output end respectively, and configured to control the pate electrode signal output end to output a gate electrode driving signal in a second stage; the reset control module is connected to a reset signal input end, a control signal input end, a first level signal input end, the pulling-down module respectively, and configured to control the pulling-down module to be in an OFF state in a third stage; the pulling-down module is connected to a second clock signal input end, the first level signal input end, the gate electrode signal output end, the pre-charging module, the first capacitor, the pulling-up module and the reset control module respectively, and configured to control pulling down a potential of the gate electrode signal output end and discharging the first capacitor in a fourth stage.