Patent ID: 9418049
Filing Date: 2016-08-16
CPC Classification: G03F,G06F,H01J

Claim Text:
1. A method for establishing a parametric model of a semiconductor process, comprising: generating a first intermediate result according to layout data and a non-parametric model of the semiconductor process; obtaining a first response according to the first intermediate result; selecting a specific mathematical function from a plurality of mathematical functions, and obtaining the parametric model according to the specific mathematical function; generating a second intermediate result according to the layout data and the parametric model; obtaining a second response according to the second intermediate result; and determining whether the parametric model is an optimal model according to the first and second responses; fabricating a semiconductor wafer according to the layout data and the optimal model of the semiconductor process, wherein the first intermediate result represents a first energy intensity distribution scattered within a resist layer by predicting a particle beam passing through the resist layer according to a non-parametric mode, and the second intermediate result represents a second energy intensity distribution scattered within the resist layer by predicting the particle beam passing through the resist layer according to a parametric mode.