Patent ID: 9343154
Filing Date: 2016-05-17
CPC Classification: G11C

Claim Text:
1. A nonvolatile memory device, comprising: a plurality of memory strings including a first memory cell string that includes at least two serially-connected selection transistors and a plurality of serially-connected nonvolatile memory cells, the at least two serially-connected selection transistors being connected between a first bit-line and the plurality of serially-connected nonvolatile memory cells, the plurality of serially-connected nonvolatile memory cells being stacked in a direction that is perpendicular to a substrate, the at least two serially-connected selection transistors including a first string selection transistor and a second string selection transistor; and a control logic configured to perform a program operation for setting a threshold voltage of at least one of the first string selection transistor and the second string selection transistor, wherein the first string selection transistor is connected to the first bit-line and has a first threshold voltage, and the second string selection transistor is disposed between the first string selection transistor and the plurality of serially-connected nonvolatile memory cells, the second string selection transistor having a second threshold voltage.