Patent ID: 9268627
Filing Date: 2016-02-23
CPC Classification: G06F

Claim Text:
1. A system, comprising: a halt detection component configured to abort a transaction that is pending execution on a processor in response to a determination that the processor has not entered a debug mode within a defined duration of time after receipt of a halt command that instructs the processor to transition to the debug mode, wherein the halt detection component is further configured to initiate at least one of a timer or a counter in response to receipt of the halt command, and to abort the pending transaction and transition the processor to the debug mode in response to a determination that the processor has not transitioned to the debug mode at a time that the at least one of the timer or the counter becomes equal to a defined value; and a scoreboard component configured to log an instruction identifier and processor state information associated with the transaction, the processor state information comprising a machine state and a program counter value.