Patent ID: 9276079
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device, the method comprising: providing a substrate; forming a gate stack at each device location on said substrate, the gate stack including a metal gate conductor on a gate dielectric layer disposed on a device channel; forming a gate spacer extending from the substrate about the sides of the gate stack, the thickness of said gate spacer being as thick as said gate stack; forming source/drain regions adjacent said gate spacer at each end of said gate stack; forming silicide regions on each of said source/drain regions; depositing a stress liner comprising a nitride layer on said substrate overlying the metal gate and extending from said substrate between the gate spacers, said stress liner separating each silicide region at said substrate from a respective said gate spacer; forming a dielectric layer over said stress liner, the combined thickness of said dielectric layer and said stress liner over said gate stack and said silicide regions being at least 3 times as tall as said gate stack; and forming contacts through said combined thickness to said metal gate and the silicide regions, each gate contact being above said device channel and narrower than said gate stack.