Patent ID: 9387613
Filing Date: 2016-07-12
CPC Classification: B29C,B29L,H01L

Claim Text:
1. A semiconductor package formation arrangement, the arrangement comprising: a mold housing comprising an interior cavity, the cavity comprising a top side spaced apart from a bottom side and first and second end sides extending between the top and bottom sides, a gate for transferring liquefied molding material into the cavity, the gate arranged in the mold housing and extending to the first end side of the cavity; and a lead frame comprising a top surface, a rear surface opposite the top surface and a mold flow modifier, the lead frame positioned in the interior cavity so as to form a first cavity section between the top surface and the top side and a second cavity section between the rear surface and the bottom side; a semiconductor chip mounted on the top surface; and electrical conductors arranged between conductive terminals of the semiconductor chip and the top surface, wherein a topology of the lead frame is such that that the liquefied molding material fills the first cavity section at a first rate and fills the second cavity section at a second rate that is different than the first rate, and wherein the mold flow modifier extends away from the lead frame so as to compensate for the difference between the first and second rates, wherein the semiconductor chip and electrical conductors retard the flow of liquified molding material across the top surface such that the first rate is less than the second rate, and wherein the mold flow modifier extends away from the rear side of the lead frame and is configured to compensate for the difference between the first and second rates by retarding the flow of liquefied molding material in the second cavity section.