Patent ID: 9384787
Filing Date: 2016-07-05
CPC Classification: G06F,G11C

Claim Text:
1. A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising: sequentially passing a voltage signal from each of a plurality of voltage sense line pairs to a voltage feedback line of a voltage regulator to a memory system, wherein the voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of memory modules, and wherein the plurality of voltage sense line pairs are in different locations within the memory system; identifying, for each voltage sense line pair, a memory margin of the memory system based on memory operation while regulating voltage to the memory system responsive to the voltage signal from the voltage sense line pair, wherein the memory margin of the memory system is equal to the lowest memory margin for any of the memory modules, and wherein the memory margin for each memory module is the difference between the minimum and maximum voltage at which the memory module can run; identifying a voltage sense line pair that provides a greatest memory margin; and then causing the voltage regulator to control the memory system responsive to the identified voltage sense line pair.