Patent ID: 9362928
Filing Date: 2016-06-07
CPC Classification: H03L

Claim Text:
1. A method for mitigating fractional spurious signals in an output signal of a fractional N-frequency divider, the method comprising: generating, by an accumulator of a fractional N-frequency divider, a substantially jitter-free calibration time window defined by a carryout signal of the accumulator, a multi-modulus frequency divider output signal of the fractional N-frequency divider and a fraction word input to the accumulator; determining a period of a first oscillator circuit by counting the number of cycles of the first oscillator circuit during the calibration time window; calibrating a second oscillator circuit relative to the first oscillator by adjusting a period of the second oscillator circuit until a difference between the period of the first oscillator circuit and a period of the second oscillator circuit is equal to a desired differential period between the first oscillator circuit and the second oscillator circuit; calculating, for each of a plurality of accumulator control words from the accumulator, a calibration control word using the first oscillator circuit, the calibrated second oscillator circuit and a phase compensation circuit of the fractional N-frequency divider; and calibrating the phase compensation circuit of the fractional N-frequency divider using the calibration control word to modify each of the plurality of accumulator control words to generate a modified control word that is used to reduce the fractional spurious signals in the output signal of the fractional N-frequency divider.