Patent ID: 9268729
Filing Date: 2016-02-23
CPC Classification: G06F,H04L,Y02D

Claim Text:
1. A processing device, comprising: a housing; a chip housed in the housing; a first processing agent housed in the housing and connected to the chip; and a network interface operable to connect the processing device to an external network that is external to the housing, wherein the chip comprises: an interconnect; a second processing agent communicatively connected to the interconnect, the second processing agent comprising a plurality of general purpose processor cores and a cache memory; a network adapter communicatively connected to the interconnect and to the network interface, the network adapter being operable to receive and classify protocol packets received from the network interface; and an accelerating agent communicatively connected to the interconnect, the accelerating agent being adapted to perform acceleration operations, wherein the network adapter is configured red such that in response to receiving a packet comprising a header and a payload, the network adapter uses the interconnect to store the payload in the cache memory of the second processing agent.