Patent ID: 9305618
Filing Date: 2016-04-05
CPC Classification: G06F,G11C

Claim Text:
1. A memory system for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration comprising: a DRAM includes a first partition and a second partition; a memory controller, said memory controller determining if memory requirements are above or below a usage threshold; said memory controller responsive to the memory requirements being below the usage threshold, partitioning the DRAM into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine; said memory controller responsive to the memory requirements being above the usage threshold, using the entire DRAM for reads and writes; and said memory controller responsive to the memory requirements being above the usage threshold, temporarily stop data flow and commands into the DRAM to transition from the dual port configuration to a single port configuration.