Patent ID: 9391064
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate; an NMOS transistor, comprising: a ground voltage wiring electrically connected to the plurality of sources through a plurality of source wirings; an input voltage wiring electrically connected to the plurality of drains through a plurality of drain wirings; a plurality of gate wirings for electrically connecting the ground voltage wiring to the plurality of gates, respectively; a wiring extending from a ground voltage pad used for external connection, the wiring being electrically connected to one end of the ground voltage wiring; and a wiring extending from an input voltage pad used for external connection, the wiring being electrically connected to another end of the input voltage wiring, the one end of the ground voltage wiring and the another end of the input voltage wiring opposed to each other across a center of the NMOS transistor, and the wiring formed at the one end extending from the ground voltage pad used for external connection, and the wiring formed at the another end extending from the input voltage pad used for external connection, each being formed in parallel to a channel length direction of the NMOS transistor.