Patent ID: 9437512
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. An integrated circuit (IC) package structure, comprising: a first integrated circuit (IC) package, comprising: a first sub-package, comprising: a first package substrate, having opposite first and second surfaces; a first semiconductor chip disposed over a first portion of the first surface of the first package substrate; an encapsulant layer disposed over top and sidewall surfaces of the first semiconductor chip and the first portion of the first surface of the first package substrate; and a plurality of first solder bumps disposed over the second surface of the first package substrate; and a second sub-package stacked on top of the first sub-package, the second sub-package comprising: a second package substrate, having opposite third and fourth surfaces; a second semiconductor chip disposed over a portion of the third surface of the second package substrate, wherein the second semiconductor chip has a function different from that of the first semiconductor chip; and a plurality of second solder bumps disposed between the fourth surface of the second package substrate and the first surface of the first package substrate; a printed circuit board (PCB), having opposite fifth and sixth surfaces, wherein the first IC package is disposed over the fifth surface of the PCB and electrically connected to the first IC package via the plurality of first solder bumps; a second IC package disposed over the fifth surface of the PCB; and a plurality of bus lines formed in the fifth surface of the PCB electrically connecting the first semiconductor chip to the second IC package such that the first sub-package, the second sub-package, and the second IC package are configured in a side-by package on package (side-by POP) IC package structure; wherein the first semiconductor chip is a microprocessor chip, and the second semiconductor chip is an integrated chip comprising a volatile memory device.