Patent ID: 9367689
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. An apparatus for protecting a basic input/output system (BIOS) in a computing system, the apparatus comprising: a BIOS read only memory (ROM), comprising: a tamper detector, disposed within a microprocessor and operatively coupled to said BIOS ROM, configured to access said BIOS contents and said encrypted message digest upon reset of said microprocessor, and configured to direct a crypto/hash unit within said microprocessor to generate a second message digest corresponding to said BIOS contents and a decrypted message digest corresponding to said encrypted message digest using said symmetric key algorithm and said key, and configured to compare said second message digest with said decrypted message digest, and configured to preclude operation of said microprocessor when said second message digest and said decrypted message digest are not equal, and configured to allow operation of said microprocessor when said second message digest and said decrypted message digest are equal; and a random number generator, configured to generate a random number for entry into a tamper at completion of a periodic BIOS hack check to set a following interval for a next BIOS hack check.