Patent ID: 9496221
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: providing a semiconductor device having a bond pad arranged over a first dielectric layer and a fuse layer arranged within the first dielectric layer; forming a coating on an upper surface of the bond pad; forming a second dielectric layer over the bond pad; performing an etch using a mask to remove a portion of the second dielectric layer to form a bond pad opening and to thin a portion of the first dielectric layer to form a fuse opening, the fuse opening defining a fuse window; and exposing the upper surface of the bond pad by removing the coating on the upper surface of the bond pad by a solution having an etching selectivity that removes the coating and that does not substantially remove the first dielectric layer; wherein the second dielectric layer is formed along sidewall and upper surfaces of the bond pad and the coating, and does not overlie the fuse layer prior to performing the etch.