Patent ID: 9244791
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. A test system apparatus for measuring a plurality of multiple test modalities and determining a defective or counterfeit microelectronic device, comprising: an electronic test board or fixture having a plurality of I/O pins adapted to couple with a device under test (DUT), said electronic test board or fixture further comprises a sensor array including a plurality of electromagnetic EM sensors adapted to be movable to cover specific areas of interest of said DUT; a first testing modality apparatus comprising a plurality of differential amplifiers comprising a time domain and signal domain signal analysis section, wherein the said differential amplifier coupled to an oscilloscope used to measure power signature data (PSD) as current versus time across a resistor in series with said DUT and a power supply during interrogation; a second testing modality apparatus comprising a plurality of electrical automatic test equipment (ATE) providing stimulation to said DUT through said test board or fixture, said ATE is operable to acquire internal timing properties, voltage thresholds, and correct functional operation characteristics from said DUT; a third testing modality comprising a plurality of E-field or H-field probes that measure a particular EM emission pattern generated from said DUT, the EM signature data comprising a field emission map in a frequency or time domain; a fourth testing modality comprising a plurality of infrared (IR) imagers that captures a plurality of thermal signature data of said DUT surface; a fifth testing modality comprising a plurality of voltmeters providing a plurality of current versus voltage curve data by injecting voltage into one or more sections of said DUT and measuring a resulting current; a sixth testing modality comprising a plurality of electrostatic discharge (ESD) test equipment which can apply a pulse for measurement by one or more said EM sensors coupled with said DUT or with said oscilloscope providing one or more per pin pulse responses; and an seventh testing modality comprising a plurality of JTAG controllers used to set or read levels on said I/O pins via boundary scan, initiate logic built-in self-test (LBIST) or program internal memory.