Patent ID: 9240415
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate including an isolation region, a first region disposed at one side of the isolation region and a second region disposed at an opposite side of the isolation region, the first region and the second region arranged in a first direction; a trench disposed in the isolation region; an insulation layer pattern structure disposed in the trench; a buried conductive pattern enclosed by the insulation layer pattern structure, the buried conductive pattern having a top surface lower than a top surface of the substrate, the buried conductive pattern extended in a second direction crossing the first direction; a first gate insulation layer disposed on the substrate; a common gate pattern disposed on the first gate insulation layer, the common gate pattern extended in the first direction, and the common gate pattern overlapped with the first region, the isolation region and the second region; a first source region and a first drain region disposed in upper portions of the first region, the first source region disposed at one side of the common gate pattern, the first drain region disposed at an opposite side of the common gate pattern, the first source region and the first drain region having impurities of a first conductivity type; and a second source region and a second drain region disposed in upper portions of the second region, the second source region disposed at the one side of the common gate pattern, the second drain source region disposed at the opposite side of the common gate pattern, the second source region and the second drain region having impurities of a second conductivity type.