Patent ID: 9489143
Filing Date: 2016-11-08
CPC Classification: G06F

Claim Text:
1. A method for accessing a flash memory, wherein the flash memory is a Triple-Level Cell flash memory and each word line of the flash memory constitutes a least significant bit (LSB) page, a central significant bit (CSB) page and a most significant bit (MSB) page, each storage unit of each word line of the flash memory is implemented by a floating-gate transistor, and each storage unit supports at least eight write voltage levels, the method comprising: generating dummy data according to data of a first page and a second page corresponding to a specific word line of the flash memory, wherein the dummy data is going to be written in a third page corresponding to the specific word line, wherein the first page is one of the LSB page, the CSB page and the MSB page corresponding to the specific word line, the second page is another one of the LSB page, the CSB page and the MSB page corresponding to the specific word line, and the third page is the other one of the LSB page, the CSB page and the MSB page corresponding to the specific word line; and writing the data and the dummy data into the flash memory; wherein the step of generating the dummy data according to the data of the first page and the second page corresponding to the specific word line of the flash memory comprising: