Patent ID: 9236292
Filing Date: 2016-01-12
CPC Classification: C23C,H01L

Claim Text:
1. A method of fabricating an interconnect structure for an integrated circuit, the method comprising: providing a previous layer metallization structure comprising an alternating metal line and dielectric line first grating pattern having a first direction; forming a dielectric line second grating pattern above the previous layer metallization structure, the dielectric line second grating pattern having a second direction, perpendicular to the first direction; forming a sacrificial structure above the first grating pattern and between the dielectric lines of the second grating pattern; replacing portions of the sacrificial structure above and aligned with the metal lines of the first grating pattern with a first dielectric layer, and replacing portions of the sacrificial structure above and aligned with the dielectric lines of the first grating pattern with a second dielectric layer; forming, by using a selective metal deposition process, one or more conductive vias in the first dielectric layer, on exposed portions of the metal lines of the first grating pattern; recessing portions of the first and second dielectric layers; and forming a plurality of metal lines in the recessed portions of the first and second dielectric layers, coupled with the one or more conductive vias, the plurality of metal lines having the second direction.