Patent ID: 9361423
Filing Date: 2016-06-07
CPC Classification: G06F

Claim Text:
1. A method comprising: selecting a process corner from an RC map comprising a typical process corner, a worst-capacitance global process corner, a best-capacitance global process corner, a worst-RC global process corner different from the worst-capacitance global process corner, and a best-RC global process corner different from the best-capacitance global process corner; for the selected process corner, determining model parameters for forming an integrated circuit; generating a file using the model parameters for the process corner, and wherein the file comprises at least two of a first capacitance table, a second capacitance table, and a third capacitance table, and wherein: generating a layout of the integrated circuit using at least the file, wherein at least one of the selecting the process corner, the determining the model parameters, the generating the file, and the generating the layout is performed using a computer; and forming the integrated circuit using the layout.