Patent ID: 9390221
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. A computer-implemented method for displaying an output of a timing violation fixing in a circuit design for manufacturing of an integrated circuit, the method comprising: determining, by an analysis tool a plurality of timing violations in the circuit design of the integrated circuit, each timing violation associated with a timing path, each timing path including a plurality of cells, the plurality of timing violations comprising a first timing violation and a second timing violation, wherein the plurality of timing violations are identified responsive to determining that the plurality of timing violations cannot be fixed by replacing one or more cells of the timing path associated with the timing violation; determining, for a first timing path associated with the first timing violation, a reason why one or more cells of the first timing path cannot be automatically replaced by the analysis tool; determining a priority for fixing, in the circuit design, each of the plurality of timing violations; and outputting information describing the plurality of timing violations, the outputting comprising: outputting information for the first timing violation and information for the second timing violation, and an indication of the priority of the first timing violation compared to the priority of the second timing violation, and outputting an indication of the reason why the one or more cells of the first timing path associated with the first timing violation cannot be automatically replaced by the analysis tool.