Patent ID: 9466605
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a non-volatile memory, comprising: providing a substrate comprising a first region and a second region; performing a first patterning process to the first region to form a plurality of gate stack structures in the first region, and forming a first sidewall oxide layer to cover sidewalls and an upper surface of each of the plurality of gate stack structures after forming the plurality of gate stack structures; forming a first high-temperature deposition layer on the first sidewall oxide layer after the first sidewall oxide layer is formed; forming a protective layer on the first high-temperature deposition layer after the first high-temperature deposition layer is formed; performing an ion implantation process to the second region after forming the protective layer; forming a gate material layer in the second region after performing the ion implantation process to the second region; removing the protective layer in the first region to expose the underlying first high-temperature deposition layer after the gate material layer is formed in the second region; etching the first high-temperature deposition layer to form first spacers on the sidewalls of the plurality of gate stack structures covered with the first sidewall oxide layer and to expose a part of the first sidewall oxide layer on the upper surfaces of the plurality of gate stack structures; performing a second patterning process to the second region to form the plurality of gate structures in the second region after the first spacers are formed; and forming a second sidewall oxide layer to cover sidewalls of each of the plurality of gate structures.