Patent ID: 9305823
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method of forming a transistor device, comprising: providing a mask layer on a semiconductor substrate; patterning the mask layer to form an opening in the mask layer to expose a surface portion of the semiconductor substrate; forming a trench in the semiconductor substrate by etching along the opening; forming a first dielectric layer in the trench, wherein the first dielectric layer has a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate; forming an epitaxial layer on the uncovered sidewall surface of the trench in the semiconductor substrate and on the first dielectric layer, wherein the epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer; and forming a second dielectric layer on the exposed surface portion of the first dielectric layer to fill the spacing in the epitaxial layer, wherein: the first and second dielectric layers form an isolation structure for the transistor device, and a channel width of the transistor device is a total width including a width of a portion of the semiconductor substrate located between neighboring isolation structures plus a total width of the epitaxial layer on both sides of the isolation structure.