Patent ID: 9285821
Filing Date: 2016-03-15
CPC Classification: G05F

Claim Text:
1. A negative reference voltage generating circuit, comprising: a clamp-type reference voltage circuit which is connected between a node of a first negative voltage which is a ground voltage or lower than the ground voltage and a node of a predetermined second negative voltage which is lower than the first negative voltage, the clamp-type reference voltage circuit formed by connecting a first circuit and a second circuit in parallel, wherein a differential amplifier which has an output terminal connected to the gates of the plurality of first PMOS transistors and the gate of the second PMOS transistor, the differential amplifier amplifying the difference between a voltage of a node connecting the drains of the plurality of first PMOS transistors with the second resistor and a voltage of a node connecting the drain of the second PMOS transistor with the third resistor, and outputting a predetermined negative reference voltage.