Patent ID: 9229055
Filing Date: 2016-01-05
CPC Classification: G01R

Claim Text:
1. Electronic scan circuitry comprising: a decompressor; a plurality of scan chains fed by the decompressor; a masking circuit fed by the plurality of scan chains, the scan chains scannable to scan them out in scan out cycles through the masking circuit; and a scannable masking qualification circuit coupled to the masking circuit and operable both to select at least one of the plurality of scan chains for disqualification and to execute the disqualification on a selected scan out cycle, the scannable masking qualification circuit including a scan-programmable shift register fed by the decompressor and accommodating at least a number n of scan programming bits and having substantially m=log 2 (N/n) cells for each of a number n of sets among all N of the scan chains masked by the masking circuit.