Patent ID: 9514049
Filing Date: 2016-12-06
CPC Classification: G06F

Claim Text:
1. A method of data processing in a data processing system including a system memory and a plurality of processor cores including a processor core supported by a higher and lower level caches, the method comprising: in response to receipt at the higher level cache of a transactional store request of the processor core generated by execution of a transactional store instruction within a memory transaction, the transactional store request specifying a target real address of a target cache line and store data: in response to a conflicting access to the transaction footprint prior to completion of the memory transaction, the higher level cache signaling failure of the memory transaction to the processor core, invalidating the updated target cache line in the higher level cache, and causing the backup copy of the target cache line in the lower level cache to be restored as a current version of the target cache line; wherein the transmitting includes transmitting the backup copy of the target cache line to the lower level cache only in response to the target cache line having a dirty coherence state in the higher level cache and not already being recorded as belonging to the transaction footprint.