Patent ID: 9431376
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A substrate comprising: multiple power transistors mounted thereon; a first metallization, on which the power transistors are commonly mountable with their collector or emitter, and which extends in at least one line on the substrate; a second metallization, which extends in an area next to the at least one line of the first metallization, for connection to other ones of the emitters or collectors of the power transistors; and a third metallization for connection to gate contact pads of the power transistors, wherein the third metallization includes at least two gate metallization areas, which are interconnectable through bonding means, whereby the gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line; at least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization, wherein the second metallization is adapted for mounting multiple power transistors with their collectors or emitters thereon, whereby the power transistors have the same orientation like the power transistors mounted on the first metallization; a fourth metallization, which extends in an area next to the second metallization, for connection to the other ones of the emitters or collectors of the power transistors mountable on the second metallization; and a fifth metallization for connection to gate contact pads of the power transistors mountable on the second metallization, wherein the fifth metallization includes at least two gate metallization areas, which are interconnectable by way of bonding means, and the at least two gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line; and at least one gate metallization area is provided as a gate island surrounded on the substrate by the fourth metallization.