Patent ID: 9384165
Filing Date: 2016-07-05
CPC Classification: G06F,H04L

Claim Text:
1. An apparatus, comprising: a multicore processor comprising a plurality of processor tiles, each processor tile comprising a processor core, the multicore processor having edge processor tiles; an interconnection mesh network having input/output ports that interconnect the plurality of processor tiles and enable transfer of data among the processor cores, with each of the input/output ports of the interconnection mesh network associated with one of the processor tiles such that the associated input/output port of the interconnection mesh network sends input data to the associated processor tile and receives output data from the associated processor tile, with the interconnection mesh network having data paths that connect peripheral ones of the plurality of processor tiles; and a configurable, extension network that comprises a plurality of network links added between each of a plurality of peripheral devices and the interconnection mesh network, with the plurality of network links coupled between the plurality of peripheral devices and the interconnection mesh network, according to a mapping scheme, the network links added between the interconnection network at edge ones of the processor tiles and respective ones of the plurality of peripheral devices according to the mapping scheme to connect via the mapping input/output ports of the interconnection mesh network to input/output ports of the plurality of peripheral devices to off load to the extension network data transfers between edge processor cores and input/output ports of one or more of the peripheral devices from the interconnection mesh network.