Patent ID: 9269611
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. An integrated circuit comprising: a gate electrode structure overlying a base substrate, wherein the gate electrode structure comprises a gate electrode and a cap disposed over the gate electrode; sidewall spacers disposed adjacent to sidewalls of the gate electrode structure; a source region and a drain region formed in the base substrate adjacent the gate electrode structure; a silicide layer disposed over the source region and the drain region; a nitride layer formed over the sidewall spaces and the silicide layer; a first dielectric layer disposed adjacent to the sidewall spacers, wherein the sidewall spacers, the cap, and the nitride layer is disposed between the first dielectric layer and the sidewall spaces and the silicide layer; a protecting layer disposed over the recessed surfaces of the sidewall spacers, the cap; and the nitride layer; a second dielectric layer disposed over the first dielectric layer and over the protecting layer; electrical interconnects disposed through the first dielectric layer and the second dielectric layer and in electrical communication with the respective source region and the drain region.