Patent ID: 9484897
Filing Date: 2016-11-01
CPC Classification: H01L,H02M,H03K

Claim Text:
1. A level shifter configured to control a high voltage device capable of withstanding a voltage higher than a first voltage, comprising: a circuital arrangement comprising transistor devices, each transistor device configured to withstand a second voltage substantially lower than the first voltage; a first supply terminal of the circuital arrangement, configured to carry a first switching voltage, the first switching voltage switching between a reference voltage and a voltage higher than the first voltage; a second supply terminal of the circuital arrangement, configured to carry a second switching voltage as a function of the first switching voltage, the second switching voltage substantially corresponding to a sum of the first switching voltage and the second voltage; an input terminal of the circuital arrangement, the input terminal configured to receive input timing control signals for controlling the high voltage device, the timing control signals configured to be coupled to the transistor devices of the circuital arrangement by way of a non-galvanic coupling; and an output terminal of the circuital arrangement, the output terminal configured to provide an output timing control signal at a voltage higher than the first voltage to the high voltage device, the output timing control signal being based on the coupled input timing control signals.