Patent ID: 9466530
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming an opening in at least one layer of insulating material positioned above a conductive contact that is conductively coupled to a transistor device so as to thereby expose at least a portion of said conductive contact; performing a selective metal silicide formation process to selectively form a metal silicide layer in said opening and on said conductive contact, wherein performing said selective metal silicide formation process comprises generating a plasma environment at a temperature of 400° C. or less and introducing a silicon-containing precursor gas into said plasma environment; depositing at least one conductive material above said selectively formed metal silicide layer so as to over-fill said opening; and performing at least one planarization process so as to remove excess materials positioned outside of said opening and thereby define a conductive via that is positioned in said opening and conductively coupled to said selectively formed metal silicide layer and to said conductive contact.