Patent ID: 9379159
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A method of fabricating an image system, the method comprising: forming a pixel array in an imaging region of a semiconductor substrate; forming a trench in a peripheral region of the semiconductor substrate after forming the pixel array, wherein the peripheral region is on a perimeter of the imaging region; filling the trench with an insulating material; forming an interconnect layer spanning the imaging region and the peripheral region after filling the trench with the insulating material, wherein a first wafer includes the interconnect layer and the semiconductor substrate, and wherein the insulating material is planarized prior to forming the interconnect layer; bonding the first wafer to a second wafer; thinning a backside of the semiconductor substrate to expose the insulating material; forming a via cavity through the insulating material, wherein the via cavity extends down to a second interconnect layer of the second wafer; and filling the via cavity with a conductive material to form a via, wherein the insulating material electrically insulates the conductive material from the semiconductor substrate.