Patent ID: 9312862
Filing Date: 2016-04-12
CPC Classification: G06F,H01L,H03K,H03L

Claim Text:
1. A system, comprising: a first functional block; a first latch circuit, coupled to an output of the first functional block; a second functional block; a second latch circuit, coupled to an input of the second functional block; a logic path that couples a data output of the first latch circuit and a data input of the second latch circuit; a clock path coupled at a first endpoint to a clock input of the first latch circuit and at a second endpoint to a clock input of the second latch circuit; and a feedback path, coupled between a tap point of the clock path and the first endpoint of the clock path, wherein the first latch circuit is configured to receive a system clock at its clock input and to sample the output of the first functional block according to the system clock, to send data clocked according to the system clock over the logic path, wherein the second latch circuit is configured to receive the system clock at its clock input and to sample its data input according to the system clock, to receive the data from the logic path; and wherein the clock path and the feedback path are configured to receive a same supply voltage as the logic path.