Patent ID: 9305650
Filing Date: 2016-04-05
CPC Classification: G11C,H01L

Claim Text:
1. A field-effect floating gate memory device comprising: a channel region having a conductivity type and adjoining an electrically insulating substrate; doped source and drain regions operatively associated with and having the same conductivity type as the channel region; a control gate; a floating gate for storing carriers from the channel region, the floating gate being positioned between the channel region and the control gate, the floating gate having a doping type opposite to the conductivity type of the channel region; a first, high-k dielectric layer thinner than five nanometers between the channel region and the floating gate and positioned to facilitate the direct tunneling of majority carriers from the channel region into the floating gate, the first, high-k dielectric layer being configured to provide a lower barrier for the tunneling of majority carriers from the channel region into the floating gate compared to that for minority carriers in the channel region, and a second dielectric layer between the control gate and the floating gate, wherein the channel region is comprised of n-type silicon, the first, high-k dielectric layer having at least one of a lower conduction band-offset with the channel region than its valence band-offset with the channel region and a lower effective mass for electrons than holes.