Patent ID: 9262098
Filing Date: 2016-02-16
CPC Classification: G06F

Claim Text:
1. A controller that controls data input/output (I/O) for a semiconductor memory device, the controller comprising: a first buffer configured to perform data transmission between an interface and the semiconductor memory device at a first pipeline stage of a plurality of pipeline stages, wherein a first external request occupies the first pipeline stage; a second buffer configured to transmit and receive data to and from the first buffer; a first control unit configured to generate an internal command corresponding to a second external request to read data from the semiconductor memory device or to write data into the semiconductor memory device at a second pipeline stage of the plurality of pipeline stages, wherein the second external request occupies the second pipeline stage; a pipeline register unit configured to store information on processing states of the first external request and information on processing states of the second external request; and a second control unit configured to control the first buffer to perform the data transmission corresponding to the first external request at said first pipeline stage and to control the first control unit to generate the internal command at said second pipeline stage, by referring to the information on the processing states of the first and second external requests stored in the pipeline register unit, wherein the second and first external requests are sequentially input to the controller, wherein external requests flow from the first pipeline stage to the second pipeline stage, wherein the second control unit controls said first pipeline stage to perform the data transmission and said second pipeline stage to generate the internal command at the same time, and wherein, when the second control unit is configured to sequentially perform the plurality of pipeline stages for a certain external request among the external requests including the first and second external requests, the plurality of pipeline stages for the certain external request further comprises a third pipeline stage, at the first pipeline stage for the certain external request, the first buffer is allocated according to the certain external request, at the second pipeline stage for the certain external request, it is determined whether or not data of an address corresponding to the certain external request exists in the second buffer and data transmission is performed between the first and second buffers if the data of the address corresponding to the certain external request is determined to exist in the second buffer, and at the third pipeline stage for the certain external request, data transmission is performed between the semiconductor memory device and the first buffer according to the certain external request if the data of the address corresponding to the certain external request is determined not to exist in the second buffer.