Patent ID: 9292640
Filing Date: 2016-03-22
CPC Classification: G06F

Claim Text:
1. A hardware functional verification system comprising a plurality of emulation chips, at least one of the emulation chips comprising: a first data memory having a first memory read port to provide a memory output; a lookup table (LUT) to run a plurality of instructions to generate a plurality of processor output bits at a processor output; a first selection circuit, comprising an output coupled to a first select port of the LUT, a first input coupled to the first memory read port to receive the memory output, and a second input to receive a plurality of prior processor output bits, wherein one of the memory output and a prior processor output bit of the plurality of prior processor output bits is provided at the output according to a first selection signal; a second selection circuit having a first input of a plurality of inputs coupled to the first memory read port to select the memory output when the prior processor output bit is provided at the output of the first selection circuit.