Patent ID: 9324723
Filing Date: 2016-04-26
CPC Classification: B82Y,G11C,H01L

Claim Text:
1. A method of forming a semiconductor device, comprising: forming a semiconductor substrate, forming a first gate electrode and a second gate electrode spaced along a first direction in a first main surface of the semiconductor substrate, forming a first gate insulation film formed between the first gate electrode and the semiconductor substrate, forming a second gate insulation film formed between the second gate electrode and the semiconductor substrate, forming a first insulation film formed over the first gate electrode, forming a second insulation film formed over the second gate electrode, forming a third gate electrode arranged opposite to the second gate electrode across the first gate electrode, and adjacent to the first gate electrode, forming a fourth gate electrode arranged opposite to the first gate electrode across the second gate electrode, and adjacent to the second gate electrode, forming a third gate insulation film formed between the third gate electrode and the semiconductor substrate, and between the first gate electrode and the third gate electrode, and including a first charge storage part in an inside portion of the third gate insulation film, and forming a fourth gate insulation film formed between the fourth gate electrode and the semiconductor substrate, and between the second gate electrode and the fourth gate electrode, and including a second charge storage part in an inside portion of the fourth gate insulation film, wherein the first gate electrode, the first gate insulation film, the first insulation film, the third gate electrode, and the third gate insulation film form a first memory cell, wherein the second gate electrode, the second gate insulation film, the second insulation film, the fourth gate electrode, and the fourth gate insulation film form a second memory cell, wherein in the first main surface, a length of the first insulation film in the first direction is shorter than a length of the first gate electrode, and wherein in the first main surface, a length of the second insulation film in the first direction is shorter than a length of the second gate electrode.