Patent ID: 9306046
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor element provided with a plurality of gates linearly formed in a plan view, an emitter pattern insulated from the plurality of gates and an emitter electrode formed on the emitter pattern, the semiconductor element being formed in such a way that a main current flows into the emitter electrode via the emitter pattern; a first solder formed on a part of the emitter electrode; a second solder formed on a part of the emitter electrode apart from the first solder; and a terminal connected to the emitter electrode by means of the first solder and the second solder, wherein the semiconductor element comprises a first solder region in which the first solder is formed, a second solder region in which the second solder is formed and an intermediate region which is a region between the first solder region and the second solder region, a density of the plurality of gates in the first solder region, a density of the plurality of gates in the second solder region and a density of the plurality of gates in the intermediate region are equal to each other, and the semiconductor element is formed so that a current density of the main current in the intermediate region is lower than current densities of the main current in the first solder region and the second solder region.