Patent ID: 9436794
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the method comprising: identifying a plurality of paths in the graph, each path starting from a timed source node and ending to a timed target node, each path comprising a plurality of clocked elements and a plurality of computational elements; optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths in the plurality of paths that fails to satisfy a set of timing constraints; identifying a path in the plurality of paths that (i) comprises a set of edge-triggered clocked elements and (ii) does not satisfy the set of timing constraints; replacing each edge-triggered clocked element in the identified path with a level-sensitive clocked element; after said replacing, optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in said identified path; and implementing the IC design using the optimized IC design.