Patent ID: 9443576
Filing Date: 2016-09-13
CPC Classification: G11C

Claim Text:
1. A memory system comprising: an array of memory cells arranged in rows and columns; a first set of word-lines, wherein each of the first set of the word-lines is coupled to a first plurality of memory cells in at least one row; a first set of bit-lines, wherein each of the first set of the bit-lines is coupled to a second plurality of memory cells in at least one column; wherein each of the first plurality of the memory cells and each of the second plurality of the memory cells comprises: at least one inductive-shunt coupled in parallel to the at least one memory storage element, wherein the inductive-shunt is configured to after the read operation, remove at least a substantial portion of the bit-line current provided to the at least one memory storage element without requiring removal of an entirety of the bit-line current applied to the at least one of the first set of the bit-lines during the read operation.