Patent ID: 9455352
Filing Date: 2016-09-27
CPC Classification: G11C,H01L

Claim Text:
1. A dual-bit memory cell comprising: a charge trapping dielectric stack disposed overlying an essentially planar upper surface of a semiconductor substrate; a poly gate disposed overlying the charge trapping dielectric stack; p-type pocket implant regions having a first portion under a peripheral portion of the charge trapping dielectric stack and a second portion adjacent to the charge trapping dielectric stack and disposed in a bit line opening; spacers laterally adjacent the charge trapping dielectric stack and poly gate, wherein a first portion of each spacer overlies the second portion of each pocket implant region; a bit line implant region disposed in the semiconductor substrate adjacent the charge trapping dielectric stack and under the bit line opening wherein the bit line implant region has an upper surface congruent with the upper surface of the semiconductor surface; and a word line.