Patent ID: 9400537
Filing Date: 2016-07-26
CPC Classification: G06F

Claim Text:
1. A power supply impedance optimizing apparatus for optimizing impedance of a power supply of a printed board on which a semiconductor device is mounted, comprising: a first noise detecting circuit adapted to detect noise of a first power supply by magnetic field coupling between a bonding wire of the first power supply and a bonding wire for first noise detection that is connected at a position adjacent to the bonding wire of the first power supply; a second noise detecting circuit adapted to detect noise of a second power supply by magnetic field coupling between a bonding wire of the second power supply and a bonding wire for second noise detection that is connected at a position adjacent to the bonding wire of the second power supply, wherein the bonding wire of the second power supply has a same voltage as the first power supply and is separated from the first power supply; a first switch connected between a node of a pad of the first power supply and a node of a pad of the second power supply on a semiconductor chip of the semiconductor device; a second switch connected between a lead of a pin of the first power supply and a lead of a pin of the second power supply in a package of the semiconductor device; and a noise determining circuit adapted to: