Patent ID: 9355207
Filing Date: 2016-05-31
CPC Classification: G06F

Claim Text:
1. A method comprising: obtaining, using a computing system, gate-level circuit design data that describes a gate-level circuit design, the gate-level circuit design data including one or more instances of each of a plurality of cells, wherein each cell of the plurality of cells is associated with a corresponding default cell static timing data, which is stored in a timing library, and a corresponding default cell stress data; selecting, using the computing system, one of the instances of one of the plurality of cells; determining, using the computing system, in-design stress data that describes one or more in-design stress parameters associated with the selected instance in the gate-level circuit design; determining, using the computing system, whether the in-design stress data is not within a tolerance of the default cell stress data associated with the selected instance; in response to the in-design stress data not being within the tolerance of the default cell stress data, the method further comprises: