Patent ID: 9324845
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. An ESD protection structure, comprising: a plurality of first doped regions of a first conductivity type forming first terminals of a plurality of transistors, wherein the plurality of first doped regions are formed in a substrate, a plurality of second doped regions of the first conductivity type forming second terminals of the plurality of transistors, wherein the plurality of second doped regions are formed in the substrate, wherein each of the plurality of first doped regions is arranged adjacent to one of the plurality of second doped regions in an alternating pattern in a first dimension, and each of the plurality of first doped regions is further arranged adjacent to another one of the plurality of second doped regions in an alternating pattern in a second dimension different than the first dimension, and a third doped region of a second conductivity type opposite the first conductivity type formed in the substrate and surrounding a plurality of doped regions to form a common third terminal of the plurality of transistors, wherein all doped regions surrounded by the third doped region are the plurality of first doped regions and the plurality of second doped regions, wherein the plurality of first doped regions are coupled to each other to form a first terminal of the ESD protection structure, and wherein the plurality of second doped regions are coupled to each other to form a second terminal of the ESD protection structure.