Patent ID: 9349755
Filing Date: 2016-05-24
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising gate lines, data lines, and a plurality of pixel units defined by intersecting the gate lines and the data lines, the gate lines, the data lines and the pixel units being formed on a substrate, wherein each pixel unit comprises a thin film transistor (TFT), in an overlapping area between an active layer and a source of the TFT, the active layer comprises at least two first tabs protruding beyond a gate of the TFT, the at least two first tabs are disposed on both sides of a central line of the active layer parallel to the gate line respectively and have a same width in a direction of gate line; the at least two first tabs are arranged in symmetry; the farther from a gate driver side of the array substrate is, the width of the first tabs in the direction of gate line has an increasing tendency.