Patent ID: 9306574
Filing Date: 2016-04-05
CPC Classification: H03K,H03L

Claim Text:
1. A circuit comprising: a dividing circuit coupled to receive an input clock signal and a plurality of divisor select signals, and further configured to generate a plurality of periodic signals including first, second, and third periodic signals; a synchronization circuit coupled to receive a first periodic signal from the dividing circuit, wherein the synchronization circuit is configured to receive input control signals and further configured to generate the divisor select signals responsive to a falling edge of the first periodic signal and a multiplexer select signal responsive to a rising edge of the first periodic signal; and a selection circuit coupled to receive the second and third periodic signals and the multiplexer select signal, wherein the selection circuit is configured to provide an output clock signal based on at least one of the second and third periodic signals and the multiplexer select signal, wherein a frequency of the input clock signal is an integer multiple of a frequency of the output clock signal.