Patent ID: 9298389
Filing Date: 2016-03-29
CPC Classification: G06F

Claim Text:
1. A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics, wherein the different operational characteristics comprise an expected amount of times a memory module may be written to prior to wearing out or failing; allocate a spare block of memory in each memory tier; identify a data characteristic for each of one or more blocks of data in the plurality of memory tiers; migrate frequently in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier, the data in the first memory_tier less than or equal to the size of the spare block of memory in the second memory tier; and migrate frequently in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in the second memory tier to the spare block of memory in the first memory tier, the data in the second memory tier less than or equal to the size of the spare block of memory in the first memory tier, wherein the different operational characteristics of each memory tier further comprises an amount of time required to service a memory access request in each memory tier.