Patent ID: 9437327
Filing Date: 2016-09-06
CPC Classification: G06F,G11C

Claim Text:
1. A combined rank and linear address incrementing utility for a computer system, comprising: a memory address map register configured to selectively store memory address maps for a plurality of different types of memory configurations; a rank register configured to store a plurality of rank address bits mapped from the memory address map register corresponding to one or more rank address fields of the memory address map register, wherein the rank register maps to rank address fields of the selected memory address register that are not contiguous; a non-rank register configured to store a plurality of non-rank address bits mapped from the memory address map register corresponding to one or more non-rank address fields of the memory address map register, wherein the non-rank register maps to non-rank address fields of the selected memory address register that are not contiguous; a selected address register configured to define a range of selected memory addresses within the selected address register based on a sequence of bits mapped from the rank register and the non-rank register; a control register for selectively setting the utility in a linear mode or a rank mode; and increment logic configured to increment the rank register and the non-rank register to sequentially generate ranges of addresses corresponding to address spaces of the different memory configurations for testing those memory configurations, wherein the increment logic is further configured to selectively operate in the linear mode for generating addresses corresponding to a selected rank, or in the rank mode for generating addresses corresponding to a plurality of ranks on a rank-by-rank basis.