Patent ID: 9324270
Filing Date: 2016-04-26
CPC Classification: G09G,G11C

Claim Text:
1. An emission driving unit, comprising: an input signal generating circuit configured to receive a frame line mark (FLM) signal according to a first clock signal, to receive a second clock signal according to the FLM signal, and to output a sequential input signal; an inverter circuit configured to receive the FLM signal according to the first clock signal, and to invert the FLM signal to generate an inverter output signal according to the second clock signal different from the first clock signal; and an output switching circuit configured to output a first voltage having a logic high level or a second voltage having a logic low level as an emission signal in response to the inverter output signal, wherein the input signal generating circuit, the inverter circuit, and the output switching circuit are implemented by transistors of only N-type or P-type, and wherein the input signal generating circuit is further configured to generate and output the sequential input signal according to the inverter output signal.