Patent ID: 9312266
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method of forming a memory, comprising: forming a plurality of first memory cells over a first surface of a semiconductor, wherein forming a plurality of second memory cells over a second surface of the semiconductor, facing in a direction opposite to the first surface, wherein forming each second memory cell comprises: forming a first select gate coupled to at least one of the first memory cells and forming a second select gate coupled to at least one of the second memory cells; forming a single source/drain region in the semiconductor that extends from the first surface of the semiconductor to the second surface of the semiconductor and that is coupled to the first select gate and the second select gate; and forming a single data line electrically coupled to the single source/drain region so that the single source/drain region commonly couples both the first and the second select gates to the single data line.