Patent ID: 9291671
Filing Date: 2016-03-22
CPC Classification: G01R

Claim Text:
1. A semiconductor integrated circuit comprising: a first variable delay circuit; a first delay control circuit including a first digital analog conversion circuit configured to convert a digital signal to the amount of current and controlling the delay of the first variable delay circuit by voltage according to the amount of current; and a first test circuit for the first delay control circuit, wherein the first digital analog conversion circuit includes a plurality of unit current sources selected according to the value of a digital signal and the first test circuit determines that the value of a current flowing into each of the plurality of the unit current sources falls within a predetermined range to determine whether the first delay control circuit is normal or abnormal, wherein the first test circuit includes a third digital analog conversion circuit configured to convert a digital signal to the amount of current and a current adjustment circuit configured to increase or decrease the amount of current of the first digital analog conversion circuit by a predetermined amount, and wherein the amount of current flowing into the third digital analog conversion circuit is compared with a first amount of current in which the amount of current flowing into the first digital analog conversion circuit is increased by the current adjustment circuit by a predetermined amount and a second amount of current in which the amount of current flowing into the first digital analog conversion circuit is decreased by the current adjustment circuit by a predetermined amount to determine whether the value of current flowing into the unit current source falls within a predetermined range.