Patent ID: 9449658
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A semiconductor apparatus comprising: a first memory bank configured to store data transmitted through a first data line; and a precharge block configured to not supply a voltage or supply a first voltage to the first data line based on a write signal, wherein the precharge block comprises a detector configured to enable a write detection signal when a first enable period of a write signal is generated, until a predetermined time later after the first enable period is generated and keep enabling the write detection signal when a second enable period of the write signal is generated within the predetermined time after the first enable period is generated, until the predetermined time later after the second enable period is generated, wherein the precharge block interrupts a voltage supply to the first data line based on the write detection signal which is enabled so that the first data line is not precharged during the interruption of the voltage supply.