Patent ID: 9477547
Filing Date: 2016-10-25
CPC Classification: G06F,H03M,H04L

Claim Text:
1. A controller device to control the operation of a solid state memory device, the controller device comprising: a link interface configurable in a first configuration and a second configuration, the first configuration to be for bidirectional communication via the link interface, the second configuration to be for unidirectional communication via the link interface, wherein the link interface includes: an encoder to generate third error-detection information corresponding to the received group of read data bits; and, logic circuitry to determine an error condition based on a comparison between the second error-detection information and the third error-detection information, the controller to perform a remedial action in the event that the logic circuitry determines the error condition, the remedial action including instructing the solid state memory device to re-transmit the group of read data bits to the controller.