Patent ID: 9336346
Filing Date: 2016-05-10
CPC Classification: G06F,H01L

Claim Text:
1. A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer, said method of arrangement forming base cells within a plurality of logic standard cells in a CMOS process technology comprising conventional, symmetric CMOS transistors having different threshold voltages distinguished by junction implants forming the electrical junctions directly adjacent to the gate; said asymmetrically doped CMOS transistors having a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors, whereby the regions defined by the electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by: said asymmetrical transistors being arranged into base cells such that patterns for source and drain regions formed on the relevant implant masks form a regular array which is achieved by mirroring adjacent base cells such that like regions of source or drain are directly adjacent for each pair of base cells; wherein each base cell contains exactly one asymmetric NMOS transistor and one asymmetric PMOS transistor, each formed on an individual active area, such that the gate and vertical position of the active area are aligned between said NMOS and PMOS transistors and such that the edges of the relevant implant masks forming each of the electrical junctions adjacent to the gate are aligned with the centre of the gate.