Patent ID: 9398700
Filing Date: 2016-07-19
CPC Classification: H01L,H05K,Y10T

Claim Text:
1. A method of forming a microelectronic assembly, comprising: assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; prior to assembling the first and second components, forming the first metal connection elements by a method comprising: forming at least one of first metal vias extending in the first direction of the first thickness between first and second major surfaces of the first component, or first metal pads at the first major surface of the first component, forming a first seed layer overlying the first major surface of the first component and electrically connected to the at least one of the first metal vias or first metal pads, and plating first plated metal regions above the at least one of first metal vias or first metal pads, the first plated metal regions extending in the first direction at least above the first major surface of the first component, the first seed layer electrically connecting each first plated metal region to a corresponding first metal via or first metal pad; plating a plurality of metal connector regions each connecting and extending continuously in the first direction between a respective first surface of the first plated metal region and a corresponding second surface of the second metal connection element opposite the respective first plated metal region, each metal connector region plated between corresponding exposed portions of the first and second surfaces; and removing portions of the first seed layer to electrically separate adjacent first metal connection elements.