Patent ID: 9379122
Filing Date: 2016-06-28
CPC Classification: G11C,H01L

Claim Text:
1. A memory device, comprising: first and second active patterns that extend parallel to each other along a first direction; a tunnel insulating layer pattern and a floating gate pattern that are stacked sequentially on each of the first and second active patterns; an insulating layer pattern that fills a space between the first and second active patterns; first and second liner patterns formed along side surfaces of the first and second active patterns the second liner pattern having an etching selectivity with respect to the insulating layer pattern; a first air gap pattern that is formed on the second liner pattern to extend along the first direction; and a blocking insulating layer pattern and a control gate pattern that are stacked sequentially on the floating gate pattern and extend along a second direction intersecting the first direction, wherein the first air gap pattern comprises a third air gap pattern that is formed on a first side of the first active pattern and a fourth air gap pattern that is formed on a second side of the second active pattern and is separated from the third air gap pattern by the insulating layer pattern.