Patent ID: 9397644
Filing Date: 2016-07-19
CPC Classification: H03K

Claim Text:
1. A frequency doubler comprising: a voltage controlled oscillator configured to output N signals having a first period and having different phases, N being a natural number; an XOR circuit configured to receive the N signals and output a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node, wherein the first unit block set comprises a first output inverter connected to a drain of a first PMOS transistor of the XOR gate and including a third PMOS transistor and a fifth NMOS transistor; and a second output inverter connected to a drain of a second PMOS transistor of the XOR gate and including the third PMOS transistor and a sixth NMOS transistor that is different from the fifth NMOS transistor.