Patent ID: 9437568
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device comprising: forming a first interconnection layer on a first substrate, the first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer; forming a second interconnection layer on a second substrate, the second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer; forming a first resist layer on a predetermined area of a surface of the first insulating layer exposed from the surface of the first interconnection layer; forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than a surface of the first conductive layer by etching the first insulating layer exposed from the first resist layer, the partial area containing surroundings of the first conductive layer; and electrically connecting the surface of the first conductive layer and a surface of the second conductive layer and also bonding the surface of the first insulating layer excluding the first non-bonded surface and a surface of the second insulating layer.