Patent ID: 9423824
Filing Date: 2016-08-23
CPC Classification: G06F,G11C,H01L

Claim Text:
1. A microelectronic package, comprising: a substrate having first and second opposed surfaces, first and second opposed edges extending between the first and second surfaces, and first and second apertures extending between the first and second surfaces, the apertures having first and second parallel axes extending in directions of the lengths of the respective apertures, the second surface having a central region between the first and second axes and first and second peripheral regions between the central region and the respective first and second edges; first and second microelectronic elements each having a surface facing the first surface of the substrate and contacts exposed at the surface of the respective microelectronic element and aligned with at least one of the apertures, each microelectronic element having memory storage array function; terminals exposed at the second surface and configured for connecting the microelectronic package to at least one component external to the microelectronic package; and leads electrically connected between the contacts of each microelectronic element and the terminals, each lead having a portion aligned with at least one of the apertures, wherein the terminals include first terminals configured to carry address information, the first terminals including a first set thereof disposed in the first peripheral region and a second set thereof disposed in the second peripheral region, and wherein the first terminals of the first set are electrically connected with the first microelectronic element and not electrically connected with the second microelectronic element, and the first terminals of the second set are electrically connected with the second microelectronic element and not electrically connected with the first microelectronic element.