Patent ID: 9362372
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method for forming a semiconductor device, comprising: providing a substrate; a first layer of a first dielectric material and a second dielectric material layer are formed on a surface of the substrate in sequence; patterning the first layer of the first dielectric material and the second dielectric material layer; removing a portion of the substrate using the patterned first layer of the first dielectric material and the patterned second dielectric material layer as a hard mask to form an isolation trench; forming an isolation structure in the isolation trench to define an active region of the substrate; entirely forming a second layer of the first dielectric material on the hard mask and the isolation structure; forming a mask pattern on the second layer of the first dielectric material in the active region to define a field plate region in the active region; performing an etching process to remove the second layer of the first dielectric material not covered by the mask pattern to form a second layer pattern of the first dielectric material, wherein the patterned second dielectric material layer serves as an etching stop layer for the etching process; and removing the patterned first layer of the first dielectric material and the patterned second dielectric material layer not covered by the second layer pattern of the first dielectric material to form a step gate dielectric structure on the substrate in the field plate region.