Patent ID: 9318199
Filing Date: 2016-04-19
CPC Classification: G06F,G11C

Claim Text:
1. An apparatus comprising a memory block, the memory block comprising: strings of memory cells formed in a plurality of tiers; access lines shared by the strings, each access line coupled to the memory cells corresponding to a respective tier of the plurality of tiers, the memory cells corresponding to at least a portion of the respective tier comprising a respective page of a plurality of pages; and data lines shared by the strings, the data lines comprising a plurality of subsets of data lines, each subset of data lines being mapped into a respective partial page of a plurality of partial pages of the respective page, each partial page independently selectable from other partial pages within the respective page, wherein a particular page of the plurality of pages includes a first partial page and a second partial page, memory cells corresponding to the first partial page are coupled to a particular access line of the access line via a first string driver, and memory cells corresponding to the second partial page are coupled to the particular access line via a second string driver.