Patent ID: 9472272
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising a plurality of resistive switching memory cells, wherein each resistive switching memory cell comprises: a) a programmable impedance element having an anode and a cathode; b) a word line pair configured to control access to the programmable impedance element, wherein the word line pair comprises first and second word lines; c) a word line driver configured to independently control the first and second word lines; d) a PMOS transistor having a first source/drain terminal coupled to the cathode, a second source/drain terminal coupled to a bit line, and a gate coupled to the first word line; and e) an NMOS transistor having a first source/drain terminal coupled to the bit line, a second source/drain terminal coupled to the cathode, and a gate coupled to the second word line, wherein the programmable impedance element is configured to be accessed when a first voltage across the first source/drain terminal and the gate of the PMOS transistor reaches a predetermined value greater than a threshold voltage of the PMOS transistor, or a second voltage across the gate and the first source/drain terminal of the NMOS transistor reaches the predetermined value greater than a threshold voltage of the NMOS transistor.