Patent ID: 9490013
Filing Date: 2016-11-08
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array including guarantee blocks, normal blocks, and redundancy blocks; a latch circuit configured to store a bad block address and indication information, wherein the bad block address indicates which block from the guarantee blocks and the normal blocks is defective, and the indication information indicates whether the bad block address belongs to the guarantee blocks or to the normal blocks; a control logic configured to supply a request block address together with associated block type information, wherein the block type information indicates whether the request block address belongs to the guarantee blocks or to the normal blocks; and a comparator configured to enable a match signal when the block type information matches the indication information, and the request block address matches the bad block address, wherein an enablement of the match signal allows the defective block to be replaced with one block from the redundancy blocks.