Patent ID: 9467152
Filing Date: 2016-10-11
CPC Classification: G06F,H03L

Claim Text:
1. An output circuit comprising: an output portion which includes a plurality of output blocks each of which converts 2-bits parallel data to 1-bit serial data and outputs the converted serial data; a control signal generation circuit which generates a latency adjustment signal, a first phase adjustment signal and a plurality of second phase adjustment signals according to a reference clock; a first clock generation portion which generates a first clock according to the reference clock based on the first phase adjustment signal; and a plurality of second clock generation portions which individually generate second clocks in synchronization with the first clock and inverted second clocks, which are inverted of the second clocks, individually based on the plurality of second phase adjustment signals, wherein each of the plurality of output blocks includes: a latency expansion circuit which sequentially latches the 2-bits parallel data according to the reference clock and an inverted reference clock, which is inverted of the reference clock, selects two from the latched data signals based on the latency adjustment signal, and outputs the selected two; and a two-clocks flip-flop circuit which is arranged with respect to the latency expansion circuit, which latches one of two outputs from the latency expansion circuit in synchronization with the second clock corresponding to the output block and holds the output for a half of a cycle of the second clock, and which latches the other of the two outputs from the latency expansion circuit in synchronization with the inverted second clock corresponding to the output block and holds the output for a half of a cycle of the inverted second clock.