Patent ID: 9490274
Filing Date: 2016-11-08
CPC Classification: G02F,H01L

Claim Text:
1. A thin film transistor array panel, comprising: a first substrate; a gate line lengthwise extended in a first direction and a data line lengthwise extended in a second direction intersecting with the first direction, on the first substrate; a storage electrode line on the first substrate, wherein a constant voltage is applied thereto; a first thin film transistor which is connected to the gate line and the data line, and comprises a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor which is connected to the gate line and the data line, and comprises a second gate electrode, a second source electrode and a second drain electrode; a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line, and comprises a third gate electrode, a third source electrode and a third drain electrode; a first subpixel electrode which is connected to the first thin film transistor; and a second subpixel electrode which is connected to the second thin film transistor, wherein the first, second and third gate electrodes are defined extended in the second direction from a same gate line to overlap the first, second and third drain electrodes, respectively, the second and third thin film transistors are spaced apart from each other in the first direction in which the gate line is lengthwise extended, the third source electrode of the third thin film transistor is directly connected to the second drain electrode of the second thin film transistor, and the second drain electrode and third source electrode directly connected to each other define lengthwise extensions thereof in the first direction in which the second and third thin film transistors are spaced apart from each other, the lengthwise extension in the first direction overlapping the second gate electrode of the second thin film transistor and the third gate electrode of the third thin film transistor which is spaced apart from the second thin film transistor in the first direction, respectively.