Patent ID: 9281071
Filing Date: 2016-03-08
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: a first transistor, a first end of the first transistor being electrically connected to a first power supply; a plurality of memory cells being electrically connected between a second end of the first transistor and a second power supply; and a controller configured to perform a read sequence, the read sequence including a first operation and a read operation, the first operation being performed before he read operation, the controller being configured to progressively increase a voltage of a gate of the first transistor to a first voltage in a first period of the first operation, the controller being configured to progressively increase a voltage of a gate of the first transistor from the first voltage to a second voltage in a second period of the first operation, the second voltage being higher than the first voltage, the controller being configured to perform the read operation on a condition that either of the first voltage or the second voltage is applied to the gate of the first transistor.