Patent ID: 9471324
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A processor, comprising: an instruction issue unit configured to issue vector program instructions for execution, where each vector program instruction operates on one or more vectors, each vector including a plurality of data elements, wherein each vector program instruction operates on one of a plurality of possible element sizes, wherein the plurality of possible element sizes includes a maximum element size; and a functional unit configured to execute a single instance of a given vector program instruction that operates on the maximum element size; wherein the functional unit is further configured to concurrently execute a plurality of vector program instructions that each operate on an element size that is less than the maximum element size; wherein for at least two of the plurality of vector program instructions that each operate on an element size that is less than the maximum element size, the at least two vector program instructions: implement different computational operations, execute with different latencies, operate on data elements of different sizes, execute in different subunits of the functional unit, or any combination thereof; and wherein a maximum number of data elements per vector on which the functional unit is configured to concurrently operate is independent of a number of vector program instructions the functional unit is configured to concurrently execute.