Patent ID: 9263575
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a plurality of active regions, each configured to have a first sidewall and a second sidewall, the plurality of the active regions being separated from one another by trenches; a side contact configured to be connected to the first sidewall; a cell junction formed at a portion of each active region on the side of the first sidewall to be connected to the side contact; a diffusion barrier region formed at a portion of each active region on the side of the second sidewall; and metal bit lines, each configured to be connected to the side contact and fill a portion of each trench, wherein the diffusion barrier region is counter-doped with an impurity which is different from an impurity doping the cell junction, wherein the active regions have a stacked structure of a first conductive layer pattern with the cell junction and the diffusion barrier region formed therein and a second conductive layer pattern formed over the first conductive layer pattern.