Patent ID: 9335997
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. A processor, comprising: one or more processor cores, wherein to execute a particular instruction, a given one of the one or more processor cores is configured to: receive an operand vector, a basis vector, a selection vector, and a control vector; evaluate the selection vector to identify a first active element position of the selection vector; select an element of the basis vector as a basis value dependent upon the first active element position; and generate a result vector dependent upon the basis value; wherein each of the operand vector, the basis vector, the selection vector, the control vector, and the result vector respectively includes a set of N elements that occupy N ordered element positions; wherein for a given element position of the result vector, a corresponding given element position of the selection vector, and a corresponding given element position of the control vector, to generate the result vector, the given processor core is further configured to: in response to a determination that both the selection vector and the control vector are active at the given element position, set the basis value and the given element position of the result vector to an element of the operand vector immediately preceding the given element position of the result vector.