Patent ID: 9531332
Filing Date: 2016-12-27
CPC Classification: H03F,H04B

Claim Text:
1. A distortion-compensation apparatus comprising: a first multiplication section that obtains a first multiplication signal by multiplying an input signal by a first pre-distortion coefficient selected from a plurality of first coefficient candidates in accordance with the input signal; a second multiplication section that obtains a second multiplication signal by multiplying a delay signal of the input signal by a second pre-distortion coefficient; an adding section that obtains an addition signal by adding the first multiplication signal and the second multiplication signal and outputs the addition signal to a predetermined circuit; and an update-processing section that updates the first pre-distortion coefficient and the second pre-distortion coefficient by convergence calculation using an iteration scheme based on the input signal and the output signal outputted from the predetermined circuit, wherein, the update-processing section updates the first pre-distortion coefficient, then updates the second pre-distortion coefficient, and after then updates both of the first updated pre-distortion coefficient and the second updated pre-distortion coefficient.