Patent ID: 9270287
Filing Date: 2016-02-23
CPC Classification: H03L,H04L

Claim Text:
1. A method for sampling a bit stream, comprising: generating a bias voltage corresponding to a bit frequency of the bit stream; receiving the bit stream and, in response to a transition in the bit stream, generating a select pulse, wherein the select pulse has a pulse width; receiving the bias voltage and, in response, generating a multi-phase clock signal, wherein the multi-phase clock signal includes a zero phase clock signal, a first phase-shifted clock signal, a second phase-shifted clock signal and a third phase-shifted clock signal; and generating a multi-phase sampling clock based on the multi-phase clock signal, wherein generating a multi-phase clock signal is configured to receive the select pulse and, in response, synchronizing the generating of the multi-phase clock signal, and wherein synchronizing the generating of the multi-phase clock signal is configured to align the multi-phase sampling clock with the bit stream.