Patent ID: 9401360
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first gate structure and a second gate structure on a substrate; a first source/drain region adjacent the first gate structure and a second source/drain region adjacent the second gate structure; a first etching stop film on the first source/drain region, the first etching stop film exposing an upper surface of the first gate structure; a second etching stop film on the second source/drain region, the second etching stop film exposing an upper surface of the second gate structure; a first contact plug that is electrically connected to the first source/drain region; and a second contact plug that is electrically connected to the second source/drain region, wherein a portion of the first etching stop film directly contacts the first source/drain region, and a portion of the second etching stop film directly contacts the second source/drain region, and wherein the portion of the first etching stop film comprises a top surface that is at a first level above a bottom surface of the substrate, the portion of the second etching stop film comprises a top surface that is at a second level above the bottom surface of the substrate, and the second level is different from the first level.