Patent ID: 9478280
Filing Date: 2016-10-25
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells configured to store program data; a sensor configured to generate sensing data by sensing the program data from the memory cell array; a condition determination unit configured to compare the program data and the sensing data and generate a result of the comparison; and a control logic unit configured to selectively perform a first verification operation when the comparison result has a first value and a second verification operation when the comparison result has a second value that is different from the first value, wherein: the first verification operation boosts a verification voltage applied to the memory cell array, during a predetermined period, from a first voltage to a second voltage, which differs from the first voltage, and the second verification operation boosts the verification voltage applied to the memory cell array, during the predetermined period, from the second voltage to a third voltage, which differs from each of the first and second voltages.