Patent ID: 9269606
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A method for forming an active isolation structure in a semiconductor integrated circuit die, the method comprising: depositing a first hard mask layer on a surface of a semiconductor substrate; removing portions of the first hard mask layer to form at least one trench, each trench defining side walls and an open bottom exposing the semiconductor substrate surface; depositing a spacer layer over the first hard mask and extending into each said trench to cover the exposed semiconductor substrate surface in each said trench; removing portions of the spacer layer, including portions of the spacer layer covering the exposed semiconductor substrate surface in each said trench, such that remaining portions of the spacer layer define spacer layer side walls covering the side walls of each said trench, the spacer layer side walls having upper, rounded portions; depositing a second hard mask layer extending into each trench between opposing spacer layer side walls in each respective trench; after depositing the second hard mask layer, performing a material removal process that removes (a) upper portions of the first hard mask layer, (b) upper portions of the second hard mask layer, and (c) the upper, rounded portions of the spacer layer side walls to expose lower, non-rounded surfaces of the spacer layer side walls, after performing the material removal process, removing the spacer layer side walls such that remaining portions of the first and second hard mask layers define a mask pattern; transferring the mask pattern to the semiconductor substrate by removing portions of the semiconductor substrate to form openings in the semiconductor substrate; and filling the openings in the semiconductor substrate with an isolation material.