Patent ID: 9318071
Filing Date: 2016-04-19
CPC Classification: G09G

Claim Text:
1. A display device, comprising: a display panel including a plurality of pixels connected to a plurality of data lines and a plurality of gate lines; a gate driver configured to provide gate signals through the plurality of gate lines to the plurality of pixels; a data driver configured to provide data signals through the plurality of data lines to the plurality of pixels; a level shifter element configured to provide a first boosted gate clock signal to the gate driver; and a timing controller configured to provide a plurality of control signals for controlling the level shifter element, the gate driver, and the data driver, wherein the level shifter element comprises: a first level shifter configured to provide one of a first gate-on voltage and a gate-off voltage as a first gate clock signal in response to a gate pulse signal received from the timing controller; and a second level shifter configured to receive the first gate clock signal, configured to provide the first boosted gate clock signal based on the first gate clock signal, and configured to provide one of a second gate-on voltage and the first gate clock signal as the first boosted gate clock signal in response to a first control signal received from the timing controller, wherein the second gate-on voltage is higher than the first gate-on voltage, and wherein the gate driver is configured to provide one or more of the gate signals in response to the first boosted gate clock signal.