Patent ID: 9337089
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate including an active region defined by an isolation layer; forming a gate line defining a bit line contact region in the active region and extending in one direction; forming a dielectric layer over the semiconductor substrate and the gate line formed in the semiconductor substrate; forming a bit line contact hole formed in the dielectric layer and exposing the bit line contact region; forming a spacer on a sidewall of the bit line contact hole; forming a bit line contact to fill the bit line contact hole including the spacer formed in the bit line contract hole; forming a bit line structure coupled to the bit line contact and extending in a direction crossing the gate line; and removing the spacer formed on the sidewalls of the bit line contact hole after the forming of a bit line structure.