Patent ID: 9442775
Filing Date: 2016-09-13
CPC Classification: G06F

Claim Text:
1. A computer system for salvaging a hardware transaction, the computer system comprising: a memory; and a processor in communications with the memory, wherein the computer system is configured to perform a method, the method comprising: recording information about an about-to-fail handler for transactional execution of a code region; recording information about a lock elided to begin transactional execution of the code region in a location that is accessible to the about-to-fail handler; detecting a pending point of failure in the code region during the transactional execution; based on the detecting, stopping transactional execution after completing an execution of a first instruction at an instruction address in the code region; based on the detecting, executing the about-to-fail handler in the transactional code region using the information about the about-to-fail handler; acquiring the lock in the transaction, by executing the about-to-fail handler in the transaction, using the information about the lock; committing speculative state of the stopped transactional execution; and starting non-transactional execution at a second instruction in the code region, the second instruction being the next instruction to be executed following the first instruction.