Patent ID: 9380231
Filing Date: 2016-06-28
CPC Classification: H04N

Claim Text:
1. A correlated double sampling (CDS) circuit, comprising: a sampling circuit configured to perform a CDS operation on a reset component of an input signal and an image component of the input signal based on a ramp signal and configured to generate an output signal, the input signal being provided from a pixel array; and a switching circuit including an auto-zero switch configured to connect a first input terminal of the switching circuit to an output node in response to an auto-zero control signal during an auto-zero interval, the switching circuit being configured to connect a first terminal of the auto-zero switch to a reference voltage and to cutoff a leakage current flowing to the auto-zero switch in response to a first boosting control signal during a first comparison interval and a second comparison interval, the auto-zero interval preceding the first comparison interval, wherein a first comparison operation is performed on the ramp signal and the reset component during the first comparison interval, a second comparison operation is performed on the ramp signal and the image component during the second comparison interval, the input signal is applied to the first input terminal of the switching circuit, and the output signal is provided to the output node.