Patent ID: 9418911
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A three-dimensional semiconductor device comprising: a structure including a plurality of interconnection patterns and interlayer molds which are stacked alternately and vertically on a substrate; a plurality of active patterns penetrating the structure; and a plurality of sidewall molds spaced apart from the active patterns and disposed on sidewalls of the interconnection patterns, each of the sidewall molds disposed between the interlayer molds vertically adjacent to each other and being in contact with the adjacent ones of the interlayer molds, wherein the sidewall molds are formed of a different insulating material from the interlayer molds, the sidewall molds and the interconnection patterns are located at substantially the same level from the substrate, and a thickness of each of the sidewall molds is less than a vertical distance between immediately adjacent interlayer molds in regions in which the interconnection patterns are disposed.