Patent ID: 9360920
Filing Date: 2016-06-07
CPC Classification: G06F,Y02D

Claim Text:
1. A processor comprising: a core including a plurality of execution units to execute instructions, the plurality of execution units including a fused multiply-add (FMA) unit to perform FMA instructions and add-like instructions, the FMA unit including a multiplier and an adder coupled to an output of the multiplier, the adder of a width having a plurality of segments each independently controllable to be powered on or off, and a tracker coupled to the adder to cause all segments of the adder to be powered on during execution of a first instruction in the FMA unit following a FMA instruction, wherein the first instruction is not to use the all segments of the adder, and otherwise to cause a corresponding segment to be powered on only if the segment is to be used during execution of an instruction.