Patent ID: 9430372
Filing Date: 2016-08-30
CPC Classification: G06F,G11C,Y02D

Claim Text:
1. An apparatus comprising: a processor that comprises one or more cores; a non-volatile memory (NVM) coupled to the processor via an I/O interface by the processor, the NVM having stored thereon a compressed Basic Input and Output System (BIOS) image; a cache within the processor; and a non-volatile random accessible memory (NVRAM) coupled to the processor and being byte-rewritable and byte-erasable by the processor, the NVRAM having stored thereon an uncompressed BIOS image, which is produced by the processor from the compressed BIOS image during a Pre-Extensible Firmware Interface (PEI) phase of a boot process, wherein execution of the uncompressed BIOS image places the cache in a write-back mode during the PEI phase of the boot process.