Patent ID: 9430239
Filing Date: 2016-08-30
CPC Classification: G06F,H04L

Claim Text:
1. A network processor, comprising: a plurality of processing cores to process data packets; a processing mode mechanism configurable to configure the processing cores between a pipeline processing mode and a parallel processing mode; a plurality of interfaces arranged with the plurality of processing cores, each interface including an input and an output; a dispatcher configured to distribute data packets to one or more of the interfaces; and a reorder module configured to receive processed data packets from the processing cores and to assemble or reorder the data packets in accordance with the processing mode, wherein the processing mode mechanism is configured to interconnect the plurality of interfaces, the dispatcher, the reorder module, and the plurality of processing cores to operate in the pipeline processing mode by coupling the input of a first of the plurality of interfaces to an output of a first of the plurality of processing cores and decoupling the input of a second of the plurality of interfaces from the dispatcher and the plurality of processing cores; and to operate in the parallel processing mode by coupling the input of the first of the plurality of interfaces to the dispatcher, coupling the input of the second of the plurality of interfaces to an output of the first of the plurality of processing cores, and coupling the output of the second of the plurality of interfaces to the reorder module.