Patent ID: 9461068
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A semiconductor arrangement, comprising: a semiconductor on insulator (SOI) substrate, comprising a base substrate, a buried dielectric layer, and a SOI layer; a back gate formed on the SOI substrate and passing through the buried dielectric layer to be in electric contact with the base substrate; fins formed from the SOI layer on opposite sides of the back gate; back gate dielectric layers interposed between the back gate and the respective fins; and a gate stack formed on the buried dielectric layer and intersecting the fins and the back gate, wherein the gate stack is isolated from the back gate by a dielectric layer, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer formed on the gate dielectric layer, wherein the gate dielectric layer is in contact with a side surface opposite to the back gate and a top surface of each of the fins and wherein the gate stack is operative to create a conductive channel at both the side surface and the top surface.