Patent ID: 9406401
Filing Date: 2016-08-02
CPC Classification: G11C

Claim Text:
1. A three-dimensional (3-D) memory, comprising: a plurality of memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies; wherein, in a synchronous test, any one of the memory dies is selected as a master die, the BIST circuit on the master die sends an enable signal to other memory die or dies via the channels, and the BIST circuits in the plurality of the memory dies test the memory banks on one same memory die or on different memory dies, wherein the plurality of the BIST circuits in the plurality of memory dies have the same circuit configuration; and wherein the BIST circuit on the master die has the same circuit configuration as the BIST circuits on other memory dies.