Patent ID: 9508599
Filing Date: 2016-11-29
CPC Classification: H01L,H03F

Claim Text:
1. A method for forming a monolithic microwave integrated circuit having an input terminal, an output terminal and a reference terminal, the method comprising: providing a high resistivity initial semiconductor substrate having an initial thickness between a first surface and an initial second surface, and having a bulk resistivity equal to or greater than 100 Ohm-cm; forming at least one transistor in and over the initial semiconductor substrate, wherein the at least one transistor has a control terminal, an output terminal, and a source region proximate the first surface; forming a dielectric layer over the first surface and overlying the source region; forming one or more conductor filled substrate vias extending through the dielectric layer and into the initial semiconductor substrate through the first surface; forming an interlayer via in the dielectric layer; forming electrical interconnections overlying the front surface of the semiconductor substrate to electrically couple the interlayer via with at least some of the multiple conductor filled substrate vias so that at least one of the substrate vias is electrically coupled to the source region of the transistor through the interlayer via and at least one of the electrical interconnections; forming one or more planar capacitors over the first surface of the initial substrate, each capacitor having first and second terminals; forming one or more planar inductors over the first surface of the initial substrate, wherein the first terminal or the second terminal of the one or more planar capacitors is coupled to a first terminal or a second terminal of the one or more planar inductors wherein other terminals of the one or more planar inductors are coupled to the substrate vias, to one or more terminals of the transistor or to one or more terminals of the microwave integrated circuit; reducing the initial thickness, thereby creating a new rear surface of a thinned substrate on which inner ends of the substrate vias are exposed; and applying a conductor to the new rear surface of the thinned substrate so that the exposed inner ends of the substrate vias are electrically connected to the conductor, and so that the source region is electrically connected to the conductor through the interlayer via, at least one of the electrical interconnections, and at least one of the substrate vias.