Patent ID: 9425060
Filing Date: 2016-08-23
CPC Classification: B82Y,H01L

Claim Text:
1. A method for fabricating multiple layers of ultra narrow silicon wires, wherein the method comprises the following steps: A. fabricating wet-etch masking layers for silicon, wherein multiple layers of wet-etch masking layers are formed at sidewalls of a fin-shaped silicon island Fin that is to be formed by step B3, wherein the step comprises: B. forming the Fin and source/drain regions located at both ends thereof by an epitaxy process, wherein the epitaxy process is performed on the silicon substrate to form the Fin and source/drain regions connected to both ends thereof, and wherein the step comprises: C. forming the multiple layers of ultra narrow silicon wires, wherein anisotropic wet etch is performed from the sidewalls of the Fin, so that the wet-etch self-stops at (111) crystal plane under protection of the wet-etch masking layer at the sidewalls, and multiple layers of ultra narrow silicon wires each having a polygonal cross section are formed, and then the area of the cross section is further reduced by sacrificial oxidation to form a circular cross section, and wherein the step comprises: