Patent ID: 9513687
Filing Date: 2016-12-06
CPC Classification: G06F,Y02D

Claim Text:
1. A microprocessor, comprising: a plurality of semiconductor dies; a bus, coupling the plurality of semiconductor dies; a plurality of processing cores, wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies; wherein each die of the plurality of semiconductor dies comprises: wherein collectively all of the control units are configured to simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores; wherein each die of the plurality of semiconductor dies comprises: wherein to collectively simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores, each of the control units is configured to turn on the clock signals to the subset of cores of its die after the value has been written to all of the control registers of its die; and wherein each control unit is configured to delay updating the control register of its die with the value written by the respective core such that the value is simultaneously written to the corresponding control register on the other of the plurality of dies.