Patent ID: 9478600
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device comprising: providing an upper semiconductor layer on a dielectric layer, wherein said dielectric layer is present on a base semiconductor layer; forming an etch mask on a surface of said upper semiconductor layer, wherein said etch mask comprises a contact opening having a first width and a capacitor opening having a second width, wherein said first width is of a dimension that is greater than 2 times said value of said second width; etching a contact trench and a capacitor trench into contact with said base semiconductor layer; forming a conformal dielectric layer on said contact trench and said capacitor trench; recessing said conformal dielectric layer within said contact trench and said capacitor trench with an anisotropic etch, wherein a first remaining portion of said conformal dielectric layer that is present in said contact trench is below said upper surface of base semiconductor layer to expose a sidewall portion of said base semiconductor layer within said contact trench, and a second remaining portion of said conformal dielectric layer that is present in said capacitor trench is present on an entirety of said sidewalls and base portions of said capacitor trench that is present in said base semiconductor layer; and filling said contact trench and said capacitor trench with a conductive material.