Patent ID: 9373591
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a lower pad; an upper pad which is formed above the lower pad; an insulation layer which is formed between the lower pad and the upper pad; a Via net for electrically connecting the lower pad and the upper pad in the insulation layer, the Via net having a net shape in which a unit grid comprising a conductive metal is connected with its adjacent unit grids comprising a conductive metal to form a conductive metal net structure in a plan view; a plurality of Via holes in the unit grid of the Via net for electrically connecting the lower pad and the upper pad, a first Via hole among the plurality of Via holes being disposed in a center of the unit grid, wherein proportions of conductive metal forming the Via net and the plurality of Via holes in each unit grid of the Via net are from approximately 10% to 75% of entire area of each unit grid.