Patent ID: 9281192
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A method of manufacturing an integrated circuit device, comprising: processing a wafer through a series of operations to form a topographically variable layer of a material on the wafer, wherein the topographically variable layer varies in height across the wafer; spin coating a monomer-containing solvent solution over a surface of the topographically variable layer; heating the wafer to within a first temperature range; maintaining the wafer within the first temperature range while a majority of the solvent evaporates from the solution; heating the wafer to within a second temperature range that is above the first temperature range; maintaining the wafer within the second temperature range until the monomers have polymerized to form a polymer coating and the polymers in the coating have cross-linked; performing chemical mechanical polishing (CMP) to remove a first portion of the polymer coating; and etching to effectuate a top-down recessing of the polymer coating.