Patent ID: 9425817
Filing Date: 2016-08-23
CPC Classification: H03M

Claim Text:
1. A delta sigma modulator of at least second order, operating at an operating clock rate, having an input and producing an output in response to the input, comprising: at least two state variables; a quantizer having an input responsive to one of the state variables and providing a feedback signal and a modulator output signal; a function block configured to apply nonlinear functions to the feedback from the quantizer to form two mutually nonlinear feedback signals; and an adder block configured to add one of the nonlinear feedback signals to the input of one of the state variables, wherein the nonlinear functions applied by the function blocks are substantially linear functions when viewed at a clock rate which is a multiple of the operating clock rate, and wherein at least one of the nonlinear functions applied by the function block comprises approximately zero when the modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer.