Patent ID: 9293212
Filing Date: 2016-03-22
CPC Classification: G11C

Claim Text:
1. A nonvolatile semiconductor memory device comprising: a memory cell array comprising a plurality of NAND strings arranged therein, each NAND string comprising a memory string comprising a plurality of memory cells connected in series, and a first select transistor and a second select transistor connected to respective two ends of the memory string, a plurality of word lines connected to respective control gate electrodes of the memory cells; a plurality of bit lines connected to respective first ends of the NAND strings; a source line connected to second ends of the NAND strings; and a control circuit performing reading of data of the memory cells, the memory cell array comprising a ROM area for data read and a normal storage area capable of arbitrary write/erase of data, the control circuit being configured to apply, when reading data of a first selected memory cell provided in the ROM area, a first read voltage to a first selected word line connected to the first selected memory cell, and apply to a first non-selected word line connected to a first non-selected memory cell provided in the ROM area, a first read pass voltage for rendering conductive regardless of data held in the first non-selected memory cell, thus allowing for a ROM area reading operation of reading a threshold voltage set in the first selected memory cell, the control circuit being also configured to apply, when reading data of a second selected memory cell provided in the normal storage area, a second read voltage to a second selected word line connected to the second selected memory cell, and apply to a second non-selected word line connected to a second non-selected memory cell provided in the normal storage area, the second non-selected memory cell storing data of a same bit number as data of the first non-selected memory cell, a second read pass voltage for rendering conductive regardless of data held in the second non-selected memory cell, thus allowing for a normal storage area reading operation of reading a threshold voltage set in the second selected memory cell, and the first read pass voltage being lower than the second read pass voltage.