Patent ID: 9471317
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A processor, comprising: a plurality of execution units, at least one of the execution units is configured to: determine, based on a field of a first instruction, a number of additional instructions to execute prior to completion of execution of the first instruction; wherein the at least one execution unit is configured to determine, based on the field of the first instruction, a number of additional instructions to execute without interruption with the first instruction; wherein other execution units in the plurality of execution units execute the additional instruction; wherein the field of the first instruction specifies at least one of: a first number of additional instructions to be executed without interruption with the first instruction; a second number of additional instructions to be executed with the first instruction wherein the second number of additional instructions maybe interrupted; a third number of additional instructions that are to be executed subsequent to execution of the first number of additional instructions wherein the third number of additional instructions maybe interrupted; and a fourth number of additional instructions that are to be executed without interruption subsequent to the execution of the second number of additional instructions.