Patent ID: 9337644
Filing Date: 2016-05-10
CPC Classification: H02H

Claim Text:
1. An electrostatic discharge (ESD) protection circuit, comprising: a first resistor having a first end coupled to a power line, and a second end coupled to a pad, avoiding swing voltage of signal at the pad influencing power voltage of the power line, wherein the first resistor is not on a discharging path; a first clamp unit coupled between the second end of the first resistor and a ground line; a second clamp unit coupled between the first resistor and the pad, conducting an ESD current caused by positive voltage ESD pulses from the pad to the first clamp unit; a third clamp unit coupled between the pad and the ground line, conducting an ESD current by negative voltage ESD pulses from the ground line to the pad; and a bias unit coupled to the pad, providing a bias voltage at the pad, wherein no ESD current flows through the first resistor when an ESD event occurs at the pad, wherein the bias unit comprises: a third resistor coupled between the power line and the pad; and a fourth resistor coupled between the pad and the ground line, wherein the bias voltage is determined according to the third and fourth resistors.