Patent ID: 9424174
Filing Date: 2016-08-23
CPC Classification: G06F,Y02D

Claim Text:
1. A control apparatus for controlling a memory having a plurality of banks, comprising: an allocation unit configured to allocate the plurality of banks to a first region for interleaving access or a second region for non-interleaving access, respectively; a memory access unit configured to perform data transfer to a plurality of banks in the first region by interleaving access, and perform data transfer to at least one bank in the second region by non-interleaving access; and a control unit configured to set the plurality of banks in the first region and the at least one bank in the second region independently to one of a low-power state and a normal operation state in accordance with the respective regions to which the plurality of banks are allocated by the allocation unit, wherein the control unit sets all of the plurality of banks in the first region to the low-power state if at least one bank in the first region is set to the low-power state, and sets the at least one bank in the second region independently to the low-power state in the bank unit if the at least one bank in the second region is set to the low-power state, and wherein the control unit sets all of the plurality of banks in the first region to the normal operation state if the at least one bank in the first region is set to the normal operation state, and sets the at least one bank in the second region independently to the normal operation state in the bank unit if the at least one bank in the second region is set to the normal operation state.