Patent ID: 9404964
Filing Date: 2016-08-02
CPC Classification: G01R,H03K

Claim Text:
1. A semiconductor integrated circuit, comprising: a first buffer circuit which includes a plurality of buffers connected in series; a second buffer circuit which includes a plurality of buffers connected in series, a number of the plurality of buffers included in the second buffer circuit being the same as a number of the plurality of buffers included in the first buffer circuit; and a control circuit which includes a second output terminal connected to an input of the first buffer circuit, a first input terminal connected to an output of the first buffer circuit, a first output terminal connected to an input of the second buffer circuit, and a second input terminal connected to an output of the second buffer circuit, wherein when a first operation is set, the control circuit outputs a signal whose logic is the same as that of a signal input into the first input terminal, from the first output terminal, and outputs a signal whose logic is different from that of a signal input into the second input terminal, from the second output terminal, and when a second operation is set, the control circuit simultaneously outputs signals with different logics from the first output terminal and the second output terminal at a time of a start of an oscillation operation, outputs a signal whose logic is the same as that of the signal input into the first input terminal, from the first output terminal, and outputs a signal whose logic is the same as that of the signal input into the second input terminal, from the second output terminal.