Patent ID: 9443113
Filing Date: 2016-09-13
CPC Classification: G06F,G11C

Claim Text:
1. A method comprising: receiving a tamper-attempt indication corresponding to a memory device that includes an array of memory cells, wherein each memory cell in the array of memory cells is written to a first state using a first current flowing in a first direction through the memory cell and written to a second state using a second current flowing in a second direction through the memory cell, wherein the second direction is substantially opposite the first direction; disabling a memory operation within the memory device based on the tamper-attempt indication received, wherein disabling the memory operation includes adjusting at least one bias voltage corresponding to circuitry on the memory device used in the memory operation such that the memory operation disabled; and generating a current on the memory device in response to an attempt to perform the memory operation that is disabled, wherein generating the current includes performing a mock memory operation, wherein the current generated has a magnitude that approximates a magnitude of current that is generated by circuitry on the memory device during performance of the memory operation when the memory operation is not disabled.