Patent ID: 9263548
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate with an active area surrounded by an isolation structure; sequentially forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure on top of the active area; sequentially forming a composite dielectric layer, a second polysilicon layer, and a second capping layer covering the gate structure and the semiconductor substrate; defining a patterned photo-resist layer on the second capping layer; patterning the second capping layer, the second polysilicon layer and the composite dielectric layer to form an interconnect structure, wherein the interconnect structure comprising the remaining part of the second capping layer, the second polysilicon layer and the composite dielectric layer; forming a composite spacer surrounding the sidewalls of the gate structure; exposing a surface of the substrate within an active area; removing the photo-resist layer over the interconnect structure located partially on the isolation structures; forming a third polysilicon layer covering the gate structure, the interconnect structure and the exposed surface within the active area; making blanket removal of the third polysilicon layer over the first capping layer, the second capping layer and a shallow trench isolation area to leave a renaming third polysilicon layer having intimate contacts to the exposed surface within the active area and the second polysilicon layer of the interconnect structure; removing the first and the second capping layer; defining the gate, source and drain area on the gate structure, the second polysilicon layer of the interconnect structure and the remaining third polysilicon layer lithographically for the proper dopant introduction; applying proper thermal treatment to activate and drive-in the dopants to form gate, source and drain with the proper conductivity; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.