Patent ID: 9490254
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. An integrated circuit, comprising: a semiconductor substrate; a dielectric layer disposed over the semiconductor substrate; a semiconductor fin extending upwardly from the semiconductor substrate through an opening in the dielectric layer, wherein a base portion of the semiconductor fin is surrounded by sidewalls of the opening and an upper portion of the semiconductor fin extends out of the opening and is disposed directly on the base portion of the fin; a gate electrode straddling the upper portion of the semiconductor fin and separated from the upper portion of the semiconductor fin by a gate dielectric; and first and second source/drain regions disposed directly on the base portion of the semiconductor fin on opposite sides of the gate electrode, wherein the first and second source/drain regions are spaced apart from one another by the upper portion of the fin and have respective lower surfaces that extend below an upper surface of the dielectric layer.