Patent ID: 9430205
Filing Date: 2016-08-30
CPC Classification: G06F

Claim Text:
1. An apparatus for controlling an execution of a binary code by multiple threads, comprising a central processing unit that is configured to: detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception; and to maintain a state where a page which is a memory area to store at least part of the first part and include an instruction modified by the self-modifying code is mapped to a virtual page to which page protection is not applied and which is not used, while specifying the second part and correcting the second part.