Patent ID: 9349692
Filing Date: 2016-05-24
CPC Classification: H01L,H05K

Claim Text:
1. A stacked integrated circuit (IC), comprising: a first semiconductor IC having a first active circuitry configured to receive a regulated voltage from a voltage regulator; a second semiconductor IC coupled to the first semiconductor IC, an active portion of the voltage regulator integrated in the second semiconductor IC and coupled to a first set of interconnects in the second semiconductor IC, the first set of interconnects operable to couple the active portion of the voltage regulator to a plurality of passive components of the voltage regulator, the plurality of passive components embedded in a packaging substrate coupled to the second semiconductor IC, the second semiconductor IC having an input/output area including a second set of interconnects, the second set of interconnects configured to enable communication between the first active circuitry on the first semiconductor IC and the packaging substrate, the first active circuitry of the first semiconductor IC facing a second active circuitry of the second semiconductor IC; and a redistribution layer on at least one of the first semiconductor IC or the second semiconductor IC, the redistribution layer configured to distribute the regulated voltage from the active portion of the voltage regulator to at least one of the first semiconductor IC or the second semiconductor IC.