Patent ID: 9524242
Filing Date: 2016-12-20
CPC Classification: G06F

Claim Text:
1. A cache memory, comprising: an N-way set-associative memory structure including N cache ways, each cache way of the N-way set associative memory structure comprising a plurality of tag memory fields and a corresponding plurality of data fields; an additional cache way comprising a plurality of tag memory fields and a corresponding plurality of data fields; a control circuit including multiplexing circuitry coupled to the data fields, said control circuit configured to operate, in an instance of a simultaneous read-write operation defined by a read memory address including a read tag portion and a read index portion, wherein the read tag portion has a value that solely identifies one of the N cache ways of the N-way set associative memory structure, and a write memory address including a write tag portion and a write index portion, wherein the write tag portion has a value that solely identifies one of the N cache ways of the N-way set associative memory, to: