Patent ID: 9299718
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A three-dimensional semiconductor device, comprising: a substrate including a cell region and a connection region; gate electrodes stacked on top of each other on the cell region of the substrate, the gate electrodes including a lowermost gate electrode; a vertical channel structure penetrating the gate electrodes on top of the lowermost gate electrode, the vertical channel structure including a first gate dielectric pattern; pads extended from the gate electrodes, the pads stacked on top of each other on the connection region of the substrate, the pads including a lowermost pad; a dummy pillar penetrating at least some of the pads on top of the lowermost pad, the dummy pillar including a second gate dielectric pattern; a first semiconductor pattern between the vertical channel structure and the substrate, the first gate dielectric pattern of the vertical channel structure on the first semiconductor pattern, the first semiconductor pattern penetrating the lowermost gate electrode; and a second semiconductor pattern between the dummy pillar and the substrate, the second semiconductor pattern penetrating the lowermost pad, the second gate dielectric pattern of the dummy pillar covering a whole top surface of the second semiconductor pattern.