Patent ID: 9331052
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. An electronic package assembly comprising: a solder mask layer having one or more openings; a plurality of pads coupled to the solder mask layer, wherein each of at least two pads of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion of each of the at least two pads is configured to receive a package interconnect structure through the one or more openings in the solder mask layer, wherein the package interconnect structure is configured to route electrical signals between a die and an electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion of each of the at least two pads is configured to receive one or more electrical connections from the die; and a die pad configured to receive the die, wherein the plurality of pads includes (i) a first row of pads disposed adjacent to the die pad and (ii) a second row of pads disposed adjacent and parallel to the first row of pads, the first row of pads being disposed closer to the die pad than the second row of pads, and wherein a first pad of the at least two pads is disposed in the first row of pads and a second pad of the at least two pads is disposed in the second row of pads.