Patent ID: 9305651
Filing Date: 2016-04-05
CPC Classification: G11C

Claim Text:
1. An event counter circuit formed on an integrated circuit, comprising: a first counter having a first capacity connected to count a number of occurrences of a first sub-set of a first event; a second counter having a second capacity connected to count a number of occurrences of a second sub-set of the first event; and logic circuitry connected to the first and second counters, wherein the logic circuitry provides the count of the number of occurrences of the first event as a sum of values of the first and second counters when neither of the first counter or the second counter has reached a respective capacity, and in response to a first one of the first and second counters reaching its respective capacity, the other of the first and second counters is used as an extension of the first one of the first and second counters, wherein the logic circuitry provides the count of the number of occurrences of the first event as the values of the first one of the first and second counters scaled according to the counters' relative capacities.