Patent ID: 9292899
Filing Date: 2016-03-22
CPC Classification: G06T,H04N

Claim Text:
1. An apparatus, comprising: a block processing pipeline comprising a plurality of stages each configured to perform one or more operations on a block of pixels from a frame passing through the pipeline, wherein the pipeline is configured to process each block according to a corresponding region of a reference frame, the region including a plurality of blocks of pixels from the reference frame; wherein the apparatus is configured to process blocks of pixels from the frame in the block processing pipeline according to row groups each including two or more rows of blocks from the frame; a memory configured to store a window including a plurality of columns of blocks of pixels from the reference frame for access by at least one of the stages, wherein the window covers two or more overlapping regions from the reference frame each corresponding to a block from a row group currently being processed in the pipeline; and wherein the apparatus is further configured to advance the window by one column of blocks from the reference frame at each rth block, where r is the number of rows in a row group.