Patent ID: 9305941
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A display for an electronic device comprising: an array of pixels, each pixel comprising: a portion of a first thin-film transistor (TFT) disposed over a substrate, wherein the portion of the first TFT comprises a first source, a first drain, and a first channel disposed adjacent to the first source and the first drain; a portion of a second TFT disposed over the substrate, wherein the portion of the second TFT comprises a second source, a second drain, and a second channel disposed adjacent to the second source and the second drain; a first via directly and electrically coupled to the first drain of the first TFT; a first insulator layer disposed over the portion of the first TFT and the portion of the second TFT; a first gate of the first TFT disposed over the first insulator layer; a second insulator layer disposed over the first insulator layer and the first gate of the first TFT; a contact disposed over the second insulator layer and directly and electrically coupled to the via; and a second gate of a second TFT disposed over the second insulator layer and directly and electrically coupled to the contact; wherein the deposition of the second gate of the TFT over the second insulator layer reduces a capacitance between the second gate and the second channel; wherein an accuracy of a gray level control of the pixel is increased due to the reduced capacitance; and wherein the deposition of the contact and the second gate of the TFT over the second insulator layer reduces a width of the electrical coupling between the contact and the second gate, thereby allowing an increased pixel aperture ratio.