Patent ID: 9496270
Filing Date: 2016-11-15
CPC Classification: G11C,H01L

Claim Text:
1. A memory cell comprising: a thin gate insulator; a bulk region of a first conductivity type in contact with a first side of the thin gate insulator; a polysilicon gate electrode of the first conductivity type in contact with a second side of the thin gate insulator; and a source region of a second conductivity type in contact with the bulk region at a junction, wherein the second conductivity type is different from the first conductivity type, further wherein the junction forms a diode for the memory cell and the junction is laterally spaced from the thin gate insulator and does not directly underlie the thin gate insulator; wherein the bulk region is in an active layer of a semiconductor-on-insulator structure comprising a buried insulator and a substrate layer; and wherein the thin gate insulator is blown upon application of a programming voltage addressed to the memory cell across the polysilicon gate electrode and the source region.