Patent ID: 9293186
Filing Date: 2016-03-22
CPC Classification: G11C

Claim Text:
1. A memory device comprising: a first transistor, a second transistor, a storage capacitor, a selection circuit, a memory circuit, and an inverter circuit, wherein one of a source and a drain of the first transistor is electrically connected to one of terminals of the storage capacitor and one of a source and a drain of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the memory circuit through the inverter circuit, wherein the other of the source and the drain of the second transistor is electrically connected to a first input terminal of the selection circuit, wherein an output terminal of the selection circuit is electrically connected to an input terminal of the memory circuit, wherein the memory circuit is electrically connected between the selection circuit and the inverter circuit, wherein the first transistor includes an oxide semiconductor layer that includes a channel formation region, and wherein the second transistor includes an oxide semiconductor layer that includes a channel formation region.