Patent ID: 9529597
Filing Date: 2016-12-27
CPC Classification: G06F,Y02D

Claim Text:
1. A multi-thread processor comprising: a plurality of hardware threads each of which generates an independent instruction flow; a first thread scheduler that continuously outputs a thread selection signal uniformly in a first period of a cycle of the first schedule pattern in accordance with a first schedule pattern or continuously outputs the thread selection signal uniformly in a second period of a cycle of the second schedule pattern in accordance with a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads; a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads; and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the first thread scheduler selects the first schedule pattern, and when the multi-thread processor is in a second state, the first thread scheduler selects the second schedule pattern, wherein the first thread scheduler comprises: wherein the first period and the second period are a same in duration.