Patent ID: 9347989
Filing Date: 2016-05-24
CPC Classification: G01R

Claim Text:
1. A test device for testing a bottom chip of a package-on-package (PoP) stacked-chip, an upper surface of the bottom chip having a plurality of soldering points for electrically connecting a plurality of corresponding soldering points of a top chip of the PoP stacked-chip, the test device comprising: a test head, having the top chip installed inside; a test arm, capable of moving in a vertical direction, having a lower end for installing the test head; a vacuum absorbing module, installed on a side of the test arm, and capable of moving to the lower end of the test arm to cover the test head, for vacuum absorbing the bottom chip, wherein the vacuum absorbing module comprises: a plurality of test contacts, installed on a lower surface of the test head, and electrically connected to the plurality of corresponding soldering points of the top chip inside the test head, wherein when the lower surface of the test head contacts the upper surface of the bottom chip, the plurality of test contacts is electrically connected to the plurality of soldering points for testing the bottom chip.