Patent ID: 9337330
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit containing an extended drain MOS transistor, comprising: forming a field oxide hard mask layer over a substrate of the integrated circuit; forming a field oxide photoresist pattern over the field oxide hard mask layer, so that an area in the field oxide hard mask layer for a drain field oxide element in the extended drain MOS transistor is exposed; performing a field oxide hard mask etch process which removes at least half of material in the field oxide hard mask layer in the drain field oxide element area; removing the field oxide photoresist pattern; forming a drain implant photoresist pattern over the integrated circuit, so that a drain implant area overlapping the drain field oxide element area is exposed; ion implanting a first set of drain dopants into a first drain implanted region in the substrate under the drain implant area, so that the field oxide hard mask layer under the drain implant area reduces a depth of the first drain implanted region under the field oxide hard mask layer by at least half a thickness of the field oxide hard mask layer compared to under the drain field oxide element area; removing the drain implant photoresist pattern; performing a drain thermal drive operation, which heats the substrate so that dopants of the first set of drain dopants in the first drain implanted region are diffused laterally and vertically to form a first diffused drain region, the first diffused drain region including a drift region adjacent to the drain field oxide element area; and forming a drain field oxide element in the drain field oxide element area.