Patent ID: 9335784
Filing Date: 2016-05-10
CPC Classification: G06F,H03L

Claim Text:
1. A clock distribution circuit comprising: a global delay locked loop (DLL) configured to receive a global clock input signal, a lead/lag input signal and to output a clock signal; a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag input signal and to output a leaf node clock signal, wherein each clock distribution block further comprises a local DLL; wherein the global DLL is further configured to align one of the plurality of leaf node clock signals, output by one of the plurality of clock distribution blocks, to a reference clock, the lead/lag input signal of the global DLL connected to the lead/lag input signal of the one of the plurality of clock distribution blocks; wherein each clock distribution block is further configured to align its leaf node clock signal to the reference clock based on its lead/lag input signal.