Patent ID: 9412291
Filing Date: 2016-08-09
CPC Classification: G09G

Claim Text:
1. A display device comprising: a plurality of pixels arranged in m rows and n columns (m and n are natural numbers larger than or equal to 4); first to m-th scan lines each one of which is electrically connected to the n pixels arranged in a corresponding one of the first to m-th rows; first to m-th inverted scan lines each one of which is electrically connected to the n pixels arranged in the corresponding one of the first to m-th rows; and a shift register which is electrically connected to the first to m-th scan lines and the first to m-th inverted scan lines, wherein the shift register includes: wherein the s-th (s is a natural number smaller than or equal to (m−2)) pulse output circuit, to which a start pulse is input (only when s is 1) or a shift pulse output from the (s−1)-th pulse output circuit is input, from which a selection signal is output to the s-th scan line, and from which a shift pulse is output to the (s+1)-th pulse output circuit, includes a first transistor which is on in a first period from a start of an input of the start pulse or the shift pulse output from the (s−1)-th pulse output circuit until a shift period ends, and outputs, from a source of the first transistor, a same or substantially same potential as a potential of a first clock signal input to a drain of the first transistor, by using a capacitive coupling between a gate and the source of the first transistor in the first period, wherein the (s+1)-th pulse output circuit, to which a shift pulse output from the s-th pulse output circuit is input, from which a selection signal is output to the (s+1)-th scan line, and from which a shift pulse is output to the (s+2)-th pulse output circuit, includes a second transistor which is on in a second period from a start of an input of the shift pulse output from the s-th pulse output circuit until the shift period ends, and outputs, from a source of the second transistor, a same or substantially same potential as a potential of a second clock signal input to a drain of the second transistor, by using a capacitive coupling between a gate and the source of the second transistor in the second period, and wherein the s-th pulse output circuit, to which a shift pulse output from the s-th pulse output circuit is input, to which the second clock signal is input, and from which a selection signal is output to the s-th inverted scan line, includes a third transistor which is off in a third period from a start of an input of the shift pulse output from the s-th pulse output circuit until a potential of the second clock signal changes, and outputs, from a source of the third transistor, a selection signal to the s-th inverted scan line after the third period.