Patent ID: 9318493
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A semiconductor construction, comprising: an array of vertically-oriented transistors; individual of the transistors comprising a bottom source/drain region, a top source/drain region, and a channel region between the top and bottom source/drain regions; the array comprising rows and columns; access lines extending along rows of the array to interconnect transistors along said rows, the access lines extending across the channel regions and forming gates across the transistors to gatedly couple the top and bottom source/drain regions through the channel regions; digit lines extending along columns of the array to interconnect transistors along said columns, the digit lines being electrically coupled to the bottom source/drain regions of the transistors and being comprised entirely of one or more metal-containing materials; each transistor of the array being uniquely addressed by a combination of an access line and a digit line; and wherein the digit lines directly contact semiconductor material of a deck directly under the digit lines; the semiconductor material directly under the digit lines being first doped stripes doped to a first dopant type; the semiconductor construction further comprising second doped stripes directly between the first doped stripes and doped to a second dopant type opposite to the first dopant type.