Patent ID: 9362187
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A chip package comprising: an integrated circuit chip; a first group of terminal pads of the chip package electrically connected to the integrated circuit chip, wherein the terminal pads of the first group are aligned to contacts of a burn-in test socket; a second group of terminal pads of the chip package electrically connected to the integrated circuit chip, wherein the terminal pads of the second group are aligned to contacts of a functional test socket; and a third group of terminal pads of the chip package electrically connected to the integrated circuit chip, wherein no terminal pad of the third group is aligned to contacts of the burn-in test socket, wherein the first, second and third groups of terminal pads are arranged on a common terminal surface of the chip package, wherein a pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads, and wherein a pad size of a terminal pad of the third group of terminal pads is smaller than the pad size of the terminal pad of the second group of terminal pads.