Patent ID: 9524884
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor package, the method comprising: providing a substrate; mounting a plurality of first semiconductor devices on the substrate; stacking a plurality of second semiconductor devices on the plurality of first semiconductor devices; forming a molding member that covers a top surface of the substrate, sidewall surfaces of the plurality of first semiconductor devices, and top surfaces and sidewall surfaces of plurality of second semiconductor devices; sawing the molding member and the substrate using a “V”-shaped cutter such that a planar area of a bottom surface of each of the sawn molding members is greater than a planar area of a top surface of each of the sawn molding members, a planar area of a bottom surface of each of the sawn substrates is greater than a planar area of a top surface of each of the sawn substrates, and sidewall surfaces of the sawn molding members and the sawn substrates have sloped profiles; and forming an antistatic layer that covers sidewall surfaces and a top surface of each of the sawn molding members and sidewalls of each of the sawn substrates.