Patent ID: 9443771
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a first titanium nitride (TiN) layer on side and bottom surfaces of each of a n-type field effect transistor (nFET) and a p-type FET (pFET) replacement metal gate (RMG) trench; forming a first amorphous silicon (a-Si) layer over the first TiN layer; implanting a first oxygen gas (O removing the first a-Si layer and first TiN layer from the side surfaces of the RMG trenches followed by the first a-Si layer from the bottom surfaces of the RMG trenches; forming a second TiN layer on the side and bottom surfaces of the RMG trenches; forming a second a-Si layer over the second TiN layer; implanting a second O removing sequentially the second a-Si layer and second TiN layer from the side surfaces of the RMG trenches, the second a-Si layer from the bottom surfaces of the RMG trenches, and a remainder of the second TiN layer from only the nFET RMG trench; forming a Ti layer on side and bottom surfaces of the RMG trenches; implanting aluminum (Al) or carbon (C) in the Ti layer vertically and annealing; and filling the RMG trenches with Al or tungsten (W).