Patent ID: 9312359
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method for forming a semiconductor structure, comprising: providing a substrate with a gate structure disposed on said substrate and with at least one recess disposed in said substrate and adjacent to said gate structure; forming a doped epitaxial material layer filling up said at least one recess; performing a doping step to form a lightly doped drain region disposed within said doped epitaxial material and at a top of said doped epitaxial material layer; forming a cap layer comprising an undoped epitaxial material, disposed on said lightly doped drain region and covering said lightly doped drain region; forming an outer spacer surrounding said gate structure and standing astride said cap layer, wherein said outer spacer partially covers said cap layer; after forming said outer spacer, performing a heavily doping step to form a source/drain region in said cap layer and in said doped epitaxial material layer; and forming an interlayer dielectric layer to cover said cap layer and said gate structure.