Patent ID: 9507744
Filing Date: 2016-11-29
CPC Classification: G06F

Claim Text:
1. A backplane controller of a backplane and for handling two serial general purpose input/output (SGPIO) channels by using one SGPIO decoder, comprising: a backplane controller chip; a first SGPIO channel interface in communication with a first SGPIO channel for receiving control commands and control data from a user at a host computer for a first group of drive slots on the backplane; a second SGPIO channel interface in communication with a second SGPIO channel for receiving control commands and control data from the user at the host computer for a second group of drive slots on the backplane, wherein the first SGPIO channel and the second SGPIO channel are provided at an SGPIO interface at a host bus adapter (HBA), wherein the first SGPIO channel interface and the second SGPIO channel interface at the backplane controller are in communication with the first SGPIO channel and the second SGPIO channel at the HBA, respectively; an SGPIO decoder in communication with the first group of drive slots and the second group of drive slots in an alternating base according a clock signal; a first SGPIO output configured to connect with the output of the SGPIO decoder to the first group of drive slots; a second SGPIO output configured to connect with the output of the SGPIO decoder to the second group of drive slots; a timer; and firmware of the backplane controller.