Patent ID: 9503093
Filing Date: 2016-11-22
CPC Classification: G06F,H03K

Claim Text:
1. A programmable integrated circuit (IC), comprising: a configuration memory; a plurality of programmable resources including programmable logic circuits and programmable routing resources, wherein in response to a configuration datastream being loaded into the configuration memory, the programmable resources are configured to concurrently implement two or more different user designs of a plurality of user designs specified in the configuration datastream using respective subsets of the programmable resources; a plurality of shareable logic circuits coupled to the plurality of programmable resources, wherein the plurality of sharable logic circuits are exclusive from the respective subsets of the programmable resources used to implement the two of more user designs; a virtualization circuit configured to manage sharing of access to the plurality of shareable logic circuits between the two or more user designs according to a resource allocation policy derived from the configuration datastream; and wherein the plurality of user designs are communicatively isolated from one another on the programmable IC.