Patent ID: 9240165
Filing Date: 2016-01-19
CPC Classification: G09G

Claim Text:
1. A display driver integrated circuit (DDI), comprising: a distributor configured to receive display data at a first frequency of an external clock, to interleave the display data into N (N is an integer greater than 2) and to output the interleaved display data at a second frequency of the external clock, wherein the distributor includes a cache memory or a direct memory access; a plurality of first-in first-out (FIFO) memories configured to receive all of the interleaved display data from the distributor at the second frequency of the external clock and output all of the interleaved display data at a third frequency of an internal clock; and a plurality of graphics memories configured to receive all of the interleaved display data from the FIFO memories, wherein the second frequency is equal to or higher than a frequency obtained by dividing the first frequency by N, and wherein the second frequency is less than the first frequency.