Patent ID: 9244484
Filing Date: 2016-01-26
CPC Classification: G06F,H03L

Claim Text:
1. A fractional-N spread spectrum clock (SSC) generator for a computer system, comprising: a fractional-N phase locked loop frequency multiplier (PLL) configured to receive a reference clock signal as an input and applying a variable multiplication factor to the reference clock signal to produce an output clock signal having a variable output frequency; and a spread spectrum clock (SSC) state machine configured to produce a single clock gating signal fed into the PLL for controlling the multiplication factor of the PLL to vary the output clock signal of the PLL; wherein the multiplication factor is set to a nominal value N and the single clock gating signal defines a modulation waveform that drives the variable multiplication factor to cause the PLL the generate a fractional-N spread spectrum output clock signal defined by digital programming input to the SSC state machine; and wherein the digital programming input to the SSC state machine comprises a modulation definition signal and an SSC rate signal.