Patent ID: 9287162
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A method to form trenches and vias in a semiconductor structure, the method comprising: forming a structure including a non-conductive layer with at least one metal line, a first dielectric layer formed over the non-conductive layer, a first etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the first etch stop layer, and an upper etch stop layer formed over the second dielectric layer; forming a first photoresist layer over the upper etch stop layer to develop at least one via pattern; patterning the first photoresist layer selectively to form the at least one via pattern in the upper stop layer; removing the first photoresist layer; forming a second photoresist layer over the upper etch stop layer to develop at least one trench pattern, the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern and a trench portion that is a remaining part of the trench pattern other than the via-trench portion; and etching the structure until the via-trench portion reaches the metal line in the non-conductive layer.