Patent ID: 9449998
Filing Date: 2016-09-20
CPC Classification: G02F,H01L

Claim Text:
1. A method of manufacturing a pixel structure, comprising: forming a patterned first conductive layer on a substrate to form a scan line, a gate electrode and a linear transmitting part, the gate electrode connected to the scan line, and the linear transmitting part and the scan line separated from each other, wherein an extending direction of the scan line is crossed to an extending direction of the linear transmitting part; forming a first insulating layer on the substrate to cover the scan line, the gate electrode and the linear transmitting part; forming an oxide channel on the first insulating layer above the gate electrode; forming a second insulating layer on the first insulating layer and the oxide channel, wherein the second insulating layer comprises an etching blocking pattern located on the oxide channel and the gate electrode, and an isolation pattern located on the linear transmitting part, wherein the etching blocking pattern is located within a boundary of the gate electrode and not in direct contact with the first insulating layer, the isolation pattern contacts the first insulating layer, and the etching blocking pattern and the isolation pattern of the second insulating layer are not continuous and do not directly contact each other; forming a patterned second conductive layer on the second insulating layer to form a source electrode, a drain electrode, a cross-line transmitting part and a common electrode, the source electrode and the drain electrode located at two sides of the oxide channel, the cross-line transmitting part crossing over the scan line, and the common electrode disposed on the isolation pattern above the linear transmitting part; and forming a first pixel electrode on the substrate to be connected to the drain electrode.