Patent ID: 9267986
Filing Date: 2016-02-23
CPC Classification: G01R,H01L

Claim Text:
1. A test method for a three-dimensional integrated circuit in which a first chip is layered on a second chip, comprising the steps of: forming a series connection between a first connection and a second connection, formed in the first chip, by connecting the first connection and the second connection with a conductor; transmitting a first test signal from a first test signal generation circuit formed in the first chip to one end of the series connection, receiving the first test signal from the other end of the series connection with a first test result judgment circuit formed in the first chip, and detecting a conducting state of the series connection in accordance with a state of the first test signal; removing the conductor from the series connection, layering the first chip on the second chip, and electrically connecting the first chip to the second chip through the first connection and the second connection; transmitting a second test signal from the first test signal generation circuit to the first connection, receiving the second test signal from the first connection with a second test result judgment circuit formed in the second chip, and detecting a conducting state between the first connection and the second chip in accordance with a state of the second test signal; and transmitting a third test signal from a second test signal generation circuit formed in the second chip to the second connection, receiving the third test signal from the second connection with the first test result judgment circuit, and detecting a conducting state between the second connection and the second chip in accordance with a state of the third test signal.