Patent ID: 9251059
Filing Date: 2016-02-02
CPC Classification: G06F

Claim Text:
1. A storage system comprising: one or more arrays of physically-addressed solid state disk (paSSD), each connected to a bus that conforms to Peripheral Component Interconnect Express (PCIe) protocol standards, through a connector, the one or more arrays of paSSDs being addressable using physical addresses associated with data, the data to be stored in the paSSD in blocks, the one or more arrays of paSSD including one or more stripes with each stripe having a segment, at least some of the segments including data and at least some of the segments including parity; and a non-volatile memory module coupled to a central processing unit (CPU) subsystem and the CPU subsystem coupled to the one or more arrays of paSSD, the non-volatile memory module located externally to the one or more arrays of paSSD and to the CPU subsystem, the non-volatile memory module including flash tables used by the CPU subsystem to manage blocks in the one or more arrays of paSSD, the flash tables including tables used to map logical-to-physical blocks addresses, the logical block addresses being host-provided and the physical block addresses for identifying the location of stored data in the paSSD, wherein the data to be written to a stripe is kept in the non-volatile memory module until a full stripe is available for writing the data to the paSSD regardless of the number of writes with no partial stripe writes being performed.