Patent ID: 9360915
Filing Date: 2016-06-07
CPC Classification: G06F,Y02D

Claim Text:
1. An apparatus comprising: a register configured to store a set of bits arranged in a clocking pattern, wherein the clocking pattern is configured to be applied to a first clock signal to generate a second clock signal for clocking a component of the apparatus; a rule enforcement logic configured to enforce at least one user defined rule on the clocking pattern, by: a selector configured to select a bit of the set of bits in the register in response to receiving an edge of the first clock signal such that, with each edge of the first clock signal, the selector selects a next bit in the clocking pattern; and a clock gate configured to: wherein the rule enforcement logic comprises: a shifting history buffer configured to store a predetermined number of previously selected bits from the register, wherein the rule enforcement logic is configured to compare contents of the shifting history buffer to the at least one user defined rule that is stored to determine if the clocking pattern violates the at least one user defined rule.