Patent ID: 9305896
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A process for fabricating pre-applied underfill on C 4 areas of panel sized semiconductor substrates comprising: a) forming chip soldering structures on said C b) applying an underfill to said C c) B-stage curing said patterned underfill to form a B-stage cured patterned underfill; d) cutting said panel sized semiconductor substrates which has said B-stage cured patterned underfill into singulated, B-stage coated singulated semiconductor substrates; progressively curing said B-staged patterned underfill through stages comprising a liquid stage and a substantially solid stage during upward temperature excursions in a flip chip assembly process comprising chip to laminate fabrication where said laminate includes laminate soldering structures, wherein said chip soldering structures and said laminate soldering structures comprise solderable metal columns with height-to-diameter ratios of greater than about 1.5:1 up to about 5:1 aligned with a solderable surface, whereby the Processing window in said flip chip assembly process is broadened.