Patent ID: 9395990
Filing Date: 2016-07-19
CPC Classification: G06F

Claim Text:
1. A processor comprising: a register having a width; a decode unit to receive a partial width load instruction, the partial width load instruction to indicate a memory location of a memory as a source operand and to indicate the register as a destination operand; a memory subsystem coupled with the decode unit, the memory subsystem, in response to the partial width load instruction, to load data from the indicated memory location to the processor; and a register write unit coupled with the memory subsystem and the register, the register write unit, in response to the partial width load instruction, to write at least a portion of the loaded data to a partial width of the register, and to finish writing the register with a set of bits stored in a remaining width of the register that have bit values that depend on a partial width load mode of the processor, the partial width load instruction not to indicate the partial width load mode.