Patent ID: 9330034
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. In a memory controller for controlling a plurality of memory devices including at least a first memory device and a second memory device, respectively, a method comprising: determining a skew between timings when first data and second data are received from the first memory device and the second memory device, respectively, the first data read from the first memory device according to a first clock signal forwarded from the memory controller via a first communication channel and the second data read from the second memory device according to a second clock signal forwarded from the memory controller via a second communication channel; and generating, by the memory controller, an advanced first clock signal that is advanced relative to the second clock signal by a phase corresponding to the determined skew, the advanced first clock signal generated based on the determined skew; transmitting, by the memory controller, the advanced first clock signal to the first memory device and the second clock signal to the second memory device; and simultaneously receiving third data from the first memory device and fourth data from the second memory device; wherein the first memory device and the second memory device simultaneously read the third data and the fourth data from the first memory device and the second memory device, respectively, according to the advanced first clock signal and the second clock signal, respectively, and the reading of the third data and the fourth data is distinct from the first memory device and the second memory device simultaneously transmitting the third data and the fourth data to the memory controller.