Patent ID: 9509317
Filing Date: 2016-11-29
CPC Classification: H03L,H04L

Claim Text:
1. A circuit comprising: a plurality of M+1 latches each coupled to receive data through a common data input, wherein the data received through the common input is synchronized to a first clock signal in a first clock domain; a multiplexer having a M+1 inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is a one-hot multiplexer configured to select one of its inputs to be coupled to the output; a control circuit configured to cause the multiplexer to sequentially select outputs of selected ones of the M+1 latches responsive to N successive clock pulses, and further configured to cause the selected ones of the M+1 latches to sequentially latch data received through the common data input, wherein the control circuit includes a first shift register configured to generate clock pulses to each of the M+1 latches such that only one of the M+1 latches is transparent at a given time, and a second shift register configured to generate selection signals provided to the multiplexer, such that only one selection signal is asserted at a given time, wherein the first and second shift registers are each synchronized to a second clock signal in a second clock domain; and a flip-flop coupled to receive the output of the multiplexer, wherein the flip-flop is synchronized to the second clock signal in the second clock domain.