Patent ID: 9429625
Filing Date: 2016-08-30
CPC Classification: G01R

Claim Text:
1. A circuit comprising: a first circuit under test; an analog test network comprising a first conductor and a first multiplexer circuit; an analog-to-digital converter circuit, wherein the first multiplexer circuit is enabled in response to a first enable signal being asserted to provide a first analog signal from a node of the first circuit under test that is selected based on a first select signal through the first conductor to the analog-to-digital converter circuit, wherein the analog-to-digital converter circuit generates a first digital signal based on the first analog signal, and wherein the first multiplexer circuit is disabled from providing the first analog signal from the first circuit under test through the first conductor to the analog-to-digital converter circuit in response to the first enable signal being de-asserted; a control circuit to generate a second digital signal based on the first digital signal; and a digital-to-analog converter circuit to generate a second analog signal based on the second digital signal, wherein the first conductor is coupled to provide the second analog signal from the digital-to-analog converter circuit to the first circuit under test.