Patent ID: 9374810
Filing Date: 2016-06-21
CPC Classification: H04W

Claim Text:
1. An apparatus in a communications network comprising: at least one processor; and at least one memory including computer program code, wherein the at least one processor, in response to execution of the computer program code, is configured to cause the apparatus to perform at least the following: generating a downlink control signal scheduling a downlink data resource in a first time slot; providing the downlink control signal over a downlink control resource in an earlier time slot wherein the earlier time slot is chronologically earlier than the first time slot and wherein the downlink control signal comprises a downlink index indicating the time slot in which the downlink data resource is to be scheduled; mapping a respective state of the downlink index to the first time slot, wherein the mapping is semi-statically configured; and transmitting the downlink control signal to a user equipment in the communications network.