Patent ID: 9455855
Filing Date: 2016-09-27
CPC Classification: H01Q,H03G,H03K,H04B

Claim Text:
1. A method comprising: selecting, by control hardware, a first output from a phased locked loop; sending, by the control hardware, the selected first output from the phased locked loop to a first device under test and a second device under test in communication with the first device under test, the first device under test and the second device under test comprising respective transceivers of a phased array antenna; adjusting, by the control hardware, a first phase rotator connected to the first device under test to a first rotator phase value of zero; determining, by the control hardware, a collection of phase detector values of a phase detector connected to the second device under test by: determining, by the control hardware, a phase detector gain of the phase detector by averaging the collection of phase detector values; storing, by the control hardware, the phase detector gain in memory hardware; and determining, by the control hardware, a quadrature error of at least one of the first device under test or the second device under test based on the phase detector gain.