Patent ID: 9385752
Filing Date: 2016-07-05
CPC Classification: H03M

Claim Text:
1. An encoder for error correction code encoding input data words (D) into codewords (Z 1 , Z 2 ), comprising: an encoder input configured to receive input data words (D) each comprising a first number K an encoder configured to encode an input data word (D) into a codeword (Z wherein said encoder is configured to wherein said encoder is configured to blockwise generate said basic parity symbols and said auxiliary parity symbols by use of a group of subsequent information symbols, wherein each information symbol i of said group of subsequent information symbols is accumulated at a set of different parity symbol addresses y, wherein the set of parity symbol addresses, at which the first information symbol of said group is accumulated, is taken from a predetermined address table and wherein the symbol addresses, at which the subsequent information symbols of said group are accumulated, are determined from said set of parity symbol addresses according to said first or said second address generation rule, respectively, wherein a separate set of parity symbol addresses is taken from said address table for generating each new block of basic parity symbols and auxiliary parity symbols, and wherein said encoder is configured to subsequently take a new row of the following address table as a new set of different parity symbol addresses y for accumulating a new group of subsequent information symbols, said address table for Q