Patent ID: 9325314
Filing Date: 2016-04-26
CPC Classification: G11C,H03K

Claim Text:
1. An integrated circuit comprising: a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level; and a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level, the memory circuit comprising a circuit configured to interface with the logic circuit, wherein the circuit is configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level, wherein the circuit comprises a clocked gate configured to be driven by the second power supply voltage level and configured to generate the output signal of the circuit in response to the signal and a clock signal, wherein the circuit further comprises an interface circuit configured to receive the signal having the first power supply voltage level, and wherein the interface circuit comprises: