Patent ID: 9330781
Filing Date: 2016-05-03
CPC Classification: G11C

Claim Text:
1. A nonvolatile memory device comprising: a memory cell array including memory cells connected to word lines and bit lines; an anti-fuse cell array configured to store setting information for controlling the memory cell array, the anti-fuse cell array including anti-fuse cells connected to the bit lines; a sense amplifier connected to the bit lines, the sense amplifier being configured to sense the memory cells or the anti-fuse cells; a page buffer configured to store data that is read out from the memory cells or from the anti-fuse cells; a control logic configured to control the sense amplifier and the page buffer to read out the data from the memory cells or the anti-fuse cells; a reference voltage supply circuit configured to supply a same reference voltage to the sense amplifier irrespective of whether the data stored in the memory cells are read or the data stored in the anti-fuse cells are read; and a bias current supply circuit configured to supply a first bias current to the sense amplifier when the data stored in the memory cells are read, and to supply a second bias current different from the first bias current to the sense amplifier when the data stored in the anti-fuse cells are read.