Patent ID: 9412845
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method for forming a dual gate structure for a vertical TFT, comprising: forming one or more layers of polysilicon; etching a plurality of trenches extending through the one or more layers of polysilicon; forming a plurality of oxide pillars by filling the plurality of trenches with an insulating material; performing a first etching process, the first etching process includes etching a first set of oxide pillars of the plurality of oxide pillars to a first initial depth, the plurality of oxide pillars includes a second set of oxide pillars different from the first set of oxide pillars; performing a second etching process subsequent to the performing the first etching process, the second etching process forms a first set of trenches by etching the first set of oxide pillars from the first initial depth to a first depth and forms a second set of trenches by etching the second set of oxide pillars to a second depth higher than the first depth; forming a plurality of gate dielectrics within the first set of trenches and the second set of trenches; and forming a first set of gate structures and a second set of gate structures, the forming the first set of gate structures and the second set of gate structures includes filling the first set of trenches and the second set of trenches with a gate material subsequent to the forming the plurality of gate dielectrics.