Patent ID: 9262577
Filing Date: 2016-02-16
CPC Classification: G06F

Claim Text:
1. A method comprising: checking a graph of a layer of an integrated circuit having circuit patterns, the graph including two or more loops, to determine whether any node within the graph is included in a respective single odd loop of the graph, and identifying each node that is included in a single odd loop as an independent node; identifying, as a safe independent node, any said independent node not closer than a threshold distance from any other one of said independent nodes in another odd loop of the graph; identifying any odd loop of the layout of the layer of the IC having at least one safe independent node; and assigning a respective circuit pattern represented by a single one of the at least one safe independent node in each identified odd loop to a first one of at least three masks, such that each circuit pattern assigned to the first one of the at least three masks has no design rule violation, wherein at least one of the steps of checking, identifying as a safe independent node, identifying any odd loop or assigning is performed by a computer.