Patent ID: 9397112
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. An integrated capacitor, comprising: a first capacitor electrode disposed over a substrate; a charge trapping dielectric layer disposed onto the substrate at a position adjacent to the first capacitor electrode, wherein the charge trapping dielectric layer comprises an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction different than the first direction; a second capacitor electrode arranged onto the lateral component and separated from the first capacitor electrode by the vertical component, wherein an upper surface of the first capacitor electrode is substantially aligned with an upper surface of the second capacitor electrode; and wherein the first capacitor electrode and the second capacitor electrode are disposed over the substrate at positions that are laterally separated from a split-gate flash memory cell by a boundary region comprising one or more isolation structures arranged within the substrate and a dummy structure comprising a dummy select gate and a dummy control gate arranged laterally separated from the first capacitor electrode by a dielectric material overlying the substrate.