Patent ID: 9484396
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. An array substrate, comprising a plurality of sub-pixel regions arranged in a matrix form, wherein each sub-pixel region at least comprises a first thin film transistor (TFT) and a second thin film transistor; the first thin film transistor comprises a first gate electrode, a first source electrode and a first drain electrode; and the second thin film transistor comprises a second gate electrode, a second source electrode and a second drain electrode, wherein the first gate electrode and at least one of the second source electrode and the second drain electrode are provided on a same layer; the second gate electrode and at least one of the first source electrode and the first drain electrode are provided on a same layer; the second gate electrode and at least one of the first source electrode and the first drain electrode are integrated together, or the first gate electrode and at least one of the second source electrode and the second drain electrode are integrated together; and wherein the first thin film transistor further comprises a first active layer, the second thin film transistor further comprises a second active layer, and the first active layer and the second active layer are provided on a same active layer.