Patent ID: 9442391
Filing Date: 2016-09-13
CPC Classification: G01B,G03F,G06F,G16Z,H01L

Claim Text:
1. A method of wafer alignment, comprising: defining a layout-based wafer map by determining designed locations of a plurality of alignment structures with a layout tool; obtaining a measured surface topography of a wafer surface of a wafer as a function of wafer position with a surface measuring tool; defining a modeled wafer map comprising modeled alignment structure locations by projecting the layout-based wafer map onto the measured surface topography; defining a measured wafer map comprising measured alignment structure locations by measuring a subset of alignment structure locations on the wafer with an alignment tool; and adjusting the measured wafer map and the modeled wafer map to minimize disagreement between the measured alignment structure locations and the modeled alignment structure locations.