Patent ID: 9257393
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method for fabricating a Fan-Out Wafer Level Package (FO-WLP), comprising: electrically coupling an Embedded Ground Plane (EGP) to a backside contact of a first microelectronic device through a backside EGP interconnect structure; electrically coupling the backside EGP interconnect structure between the EGP and a backside contact of a second microelectronic device; forming a molded package body around the first microelectronic device, the second microelectronic device, the EGP, and the backside EGP interconnect structure, the molded package body having a frontside at which the EGP is exposed; and producing one or more Redistribution Layers (RDLs) over the frontside of the molded packaged body, the one or more RDLs containing at least one interconnect line electrically coupled to the backside contact of the first microelectronic device through the EGP and the backside EGP interconnect structure.