Patent ID: 9478487
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A semiconductor package comprising: a substrate comprising connection pads; a first semiconductor chip stacked on an upper surface of the substrate, wherein the first semiconductor chip comprises a layer of electrically conductive pads constituting bonding pads, a layer of routing wires extending lengthwise in directions parallel to the upper surface of the substrate in a routing area of the first semiconductor chip, and a layer of electrically conductive pads constituting non-bonding pads; and conductive wires connected to the bonding pads and the connection pads, wherein the bonding pads are arrayed in at least one column along a first side of the first semiconductor chip, the bonding pads in each said column being spaced from each other in a first direction parallel to the upper surface of the substrate, the layer of routing wires in the routing area of the first semiconductor chip is located, in the first direction, between respective ones of the bonding pads, the non-bonding pads are arrayed in at least one column, the non-bonding pads in each said column thereof being spaced from each other in a second direction parallel to the upper surface of the substrate but different from the first direction, the non-bonding pads are not in contact with the conductive wires, and the layer of electrically conductive pads constituting the bonding pads, the layer of routing wires, and the layer of electrically conductive pads constituting the non-bonding pads are all disposed at the same level from the substrate.