Patent ID: 9507230
Filing Date: 2016-11-29
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: a first substrate; and a plurality of gate lines and a plurality of the data lines provided on the first substrate, wherein the plurality of gate lines and the plurality of the data lines cross each other to define a plurality of pixel units arranged into a matrix form, and each of the plurality of pixel units comprises: wherein in each pixel unit, the first electrode and the second electrode form a horizontal electric field for driving in operation, the gate line for the pixel unit and the thin film transistor switch are arranged between regions of the first electrode, and the thin film transistor switch is controlled by the gate line to operate each region of the first electrode, wherein for two adjacent rows TFT switches, drain electrodes of one row TFT switches are in a linear shape and source electrodes thereof are in a U shape, and drain electrodes of the other row TFT switches are in a U shape, and source electrodes thereof are in a linear shape.