Patent ID: 9390644
Filing Date: 2016-07-12
CPC Classification: G09G

Claim Text:
1. A defect detecting device using a demultiplexer connecting corresponding ones of a plurality of data lines to a plurality of lines, the defect detecting device comprising: first to third DC lines supplied with first to third DC voltages; a plurality of first switches connected to the first to third DC lines and configured to transmit one of the first to third DC voltages to a plurality of first data lines among the plurality of data lines according to a first gate signal; and a plurality of second switches connected to the first to third DC lines and configured to transmit one of the first to third DC voltages to a plurality of second data lines among the plurality of data lines according to a second gate signal, wherein the demultiplexer includes: a plurality of first TFTs connecting first terminals of the plurality of lines and the plurality of first data lines, and a plurality of second TFTs connecting the first terminals of the plurality of lines and the plurality of second data lines, wherein second terminals of the plurality of lines are in floating state, wherein the defect detecting device is configured to detect a short defect in the plurality of lines in a state when the plurality of the first switches and the plurality of the second switches are in an on state, and only one of the plurality of first TFTs or the plurality of second TFTs are in an on state.