Patent ID: 9412626
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a chip arrangement, the method comprising: disposing a chip over a carrier, the carrier comprising a first carrier side and a second carrier side, wherein the chip has a top side facing away from the first carrier side and a bottom side opposite the top side, wherein the top side comprises one or more contact pads and the bottom side comprises one or more contact pads; electrically connecting the bottom side of the chip to the first carrier side via the one or more contact pads of the bottom side; disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, wherein the first encapsulation material comprises a thermoset material; and disposing a second encapsulation material over the second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side, wherein the second encapsulation material comprises a thermal interface material.