Patent ID: 9257344
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a first and a second plurality of shallow trench isolation (STI) regions in a semiconductor substrate, wherein a first portion of the semiconductor substrate between the first plurality of STI regions is configured as a first semiconductor strip, and a second portion of the semiconductor substrate between the second plurality of STI regions is configured as a second semiconductor strip; recessing the first semiconductor strip to form a first recess having a first depth; performing a first epitaxy to grow a first epitaxy strip in the first recess; recessing the second semiconductor strip to form a second recess having a second depth different from the first depth; performing a second epitaxy to grow a second epitaxy strip in the second recess; and recessing the first plurality of STI regions and the second plurality of STI regions to form a first semiconductor fin and a second semiconductor fin, respectively, wherein the first semiconductor fin comprises a top portion of the first epitaxy strip, and the second semiconductor fin comprises a top portion of the second epitaxy strip.