Patent ID: 9390781
Filing Date: 2016-07-12
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate; a transistor including an impurity region formed in the semiconductor substrate, a gate insulation film located on the semiconductor substrate, and a gate electrode located on the gate insulation film; a first insulation film formed above the semiconductor substrate; a first capacitor located on the first insulation film, wherein the first capacitor includes a lower electrode, a ferroelectric, and an upper electrode, and one of the lower electrode and the upper electrode is electrically connected to the impurity region so that the transistor and the first capacitor form a memory cell; and a second capacitor located on the first insulation film, wherein the second capacitor includes a first electrode, a first dielectric, a second electrode, a second dielectric, and a third electrode, and the transistor and the second capacitor are in an electrically independent state; wherein the lower electrode and the first electrode are formed from the same material, the ferroelectric and the first dielectric are formed from the same material, and the upper electrode and the second electrode are formed from the same material.