Patent ID: 9303953
Filing Date: 2016-04-05
CPC Classification: F41G,G05B,H01L,Y10T

Claim Text:
1. A tamper detection system comprising: a launch clock replica circuit receiving a clock signal at an input and generating a launch clock signal at an output; a waveform generator register having a latch input connected to said output of said launch clock replica, an input and an output; an inverter having an input connected to said output of said waveform generator and an output connected to said input of said waveform generator; a critical path replica circuit having an input connected to said output of said waveform generator and an output, said critical path replica circuit having a delay corresponding to a delay of a critical path of a circuit to be protected; a variable delay circuit having an input connected to said output of said critical path replica circuit and an output, said variable delay circuit having a specified delay; a capture clock replica circuit receiving a clock signal at an input and generating a capture clock signal at an output; a register having a latch input connected to said output of said capture clock replica circuit, an input connected to said output of said variable delay circuit and an output; an exclusive NOR gate having a first input connected to said output of said waveform generator, a second input connected to said output of said register and an output; a counter having an enable input connected to said output of said exclusive NOR gate, a clock input connected to said output of said capture clock replica circuit and an overflow output, said counter counting clock signals at said clock input when said exclusive NOR indicates said output of said waveform generator does not match said output of said register and generating an overflow signal at said overflow output indicating tampering upon overflow.