Patent ID: 9337079
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. An integrated circuit structure that includes a transistor, comprising: an isolation region filled with a dielectric material, the isolation region extending through an active semiconductor layer and through an overlying a buried oxide layer on a substrate and into the substrate, the active semiconductor layer being electrically isolated from the substrate by the buried oxide layer that is positioned between them; an epitaxial region of the active semiconductor layer protruding into a sidewall of the dielectric material in the isolation region to form a protrusion having a curved profile; a gate dielectic overlying the active semiconductor layer at location spaced away from the epitaxial region protrusion; a gate electrode overlying the gate dielectric; a source/drain region overlying and abutting in physical and electrical contact with the active semiconductor layer; and a conductive material being in physical and electrical contact with the source/drain region to form a source/drain contact.