Patent ID: 9502420
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: providing a material stack of, from bottom to top, a relaxed and n-type doped silicon germanium alloy layer and a relaxed silicon germanium alloy layer, each layer having a uniform germanium content, on a surface of a relaxed and graded silicon germanium alloy buffer layer that is located within a pFET device region of a semiconductor substrate; patterning said relaxed silicon germanium alloy layer to provide at least one relaxed silicon germanium alloy fin having said uniform germanium content on said relaxed and n-type doped silicon germanium alloy layer; and forming a strained germanium layer on exposed sidewall surfaces and a topmost surface of said at least one relaxed silicon germanium alloy fin, and on a portion of, but not an entirety of, a topmost surface of said relaxed and n-type doped silicon germanium alloy layer.