Patent ID: 9229524
Filing Date: 2016-01-05
CPC Classification: G06F,Y02B,Y02D

Claim Text:
1. A processor comprising: a front end unit to decode incoming instructions; a timer coupled to the front end unit to count a number of cycles in which the front end unit does not decode an instruction of a first type; a first execution unit of a core of the processor to execute instructions of the first type; a first local power gate circuit coupled to the first execution unit to power gate the first execution unit while a second execution unit of the processor core is to execute instructions of a second type; an interface lock to isolate the first execution unit from a remainder of the core when the first execution unit is power gated; and a controller coupled to the first local power gate circuit to cause the first local power gate circuit to power gate the first execution unit in a first low power state when an instruction stream to be executed in the core does not include the first type of instructions, and to cause the first local power gate circuit to isolate the first execution unit and provide a retention voltage in a second low power state, wherein the controller is to cause a state of the first execution unit to be saved prior to entry of the first execution unit into the first low power state and to not save the state of the first execution unit prior to entry of the first execution unit into the second low power state.