Patent ID: 9443881
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A thin film transistor array panel comprising: a gate line; a gate insulating layer that covers the gate line; a semiconductor layer that is disposed on the gate insulating layer; a data line and drain electrode that are disposed on the semiconductor layer; a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode; and a pixel electrode that is electrically connected to the drain electrode through the contact hole, wherein the data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed, wherein the gate insulating layer has a first portion that has a first thickness and a second portion that has a second thickness that is smaller than the first portion, wherein the pixel electrode overlaps upper surfaces of the first and second portions that are adjacent one another, wherein part of the upper surface of the first portion overlapping the pixel electrode contacts the passivation layer.