Patent ID: 9324709
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method comprising: depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, said layer of metal having a first region and a second region; forming a first mask of a dual height gate pattern over said second region of said layer of metal, and etching said layer of metal in said first region that is not covered by said first mask, to lower a height of said first region of said layer of metal; forming an insulating layer over said first region of lowered height, said insulating layer being formed to have a top surface coplanar with said second region of said layer of metal; forming a dielectric layer on said insulating layer and said second region of said layer of metal; removing a portion of said dielectric layer positioned directly on said second region of said layer of metal to create a via, wherein said removing includes forming a second mask of said dual height gate pattern on top of said dielectric layer, said second mask being positioned vertically over said first region of said layer of metal, and wherein said portion of said dielectric layer is defined by said dual height gate pattern; and forming at least one contact to a source/drain region of said one or more transistors and at least one gate contact within said via.