Patent ID: 9395985
Filing Date: 2016-07-19
CPC Classification: G06F

Claim Text:
1. A processor, comprising: an instruction fetch unit including an instruction pre-fetch buffer, the instruction fetch unit configured to fetch instructions from memory into the instruction pre-fetch buffer; and an instruction decode unit coupled to the instruction pre-fetch buffer, the instruction decode unit, upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction; wherein, upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from the memory beginning at an address after the N instruction words.