Patent ID: 9419781
Filing Date: 2016-08-16
CPC Classification: G06Q,H04L

Claim Text:
1. An integrated circuit receiver to receive a signal comprising data symbols from an external source, and to generate at least one recovered clock from the signal, the integrated circuit receiver comprising: an edge sampler to sample the signal at an expected edge crossing time between adjacent ones of the data symbols, to generate binary edge samples; a data sampler to sample each data symbol at a data sampling time and to produce a corresponding multi-bit digital value, each multi-bit digital value representing a corresponding voltage magnitude of the signal; processing circuitry to receive and process each multi-bit digital value, and to produce a respective bit of binary output data therefrom dependent on comparison with a decision threshold; and clock generation circuitry to receive the binary edge samples and the binary output data, to detect from the binary output data a logic level transition between adjacent ones of the data symbols, and to adjust timing of the recovered clock dependent on binary edge samples which correspond to the transitions; wherein the expected edge crossing time and the data sampling time are each dependent on timing of a recovered clock of the at least one recovered clock.