Patent ID: 9437283
Filing Date: 2016-09-06
CPC Classification: G11C

Claim Text:
1. A semiconductor storage device comprising: a plurality of memory cells provided in a matrix form; a plurality of word lines provided to correspond respectively to the rows of the memory cells; a first power supply for the memory cells, which is provided to retain data in the memory cells; a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells; and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply, wherein each of the memory cells comprises access transistors which are coupled to one of the word lines and serve for executing data reading or writing from/to the memory cells, wherein the word line level fixing circuit comprises: a plurality of level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential; and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply, and wherein the level fixing control circuit makes the level fixing transistors conductive in accordance with turn-on of the first power supply, when the second power supply is not yet turned on.