Patent ID: 9325322
Filing Date: 2016-04-26
CPC Classification: H03K,H03L

Claim Text:
1. A synchronization system, comprising: a frequency divider circuit that generates a divided clock by dividing a reference clock in a first division ratio set by a division ratio setting signal; a first device that operates in synchronization with the reference clock; a second device that operates in synchronization with the divided clock; a division ratio detection circuit that, for each period of the divided clock, outputs a count value counted in synchronization with the reference clock, and detects a division ratio of the divided clock based on the count value and output the division ratio as a second division ratio; and a decoder that generates a strobe signal, which is for controlling a timing at which the first device transmits and receives a signal to and from the second device, based on the count value and the second division ratio, wherein the first device communicates with the second device through a bus, which operates in synchronization with the divided clock, based on the strobe signal.