Patent ID: 9459865
Filing Date: 2016-10-04
CPC Classification: G06F

Claim Text:
1. A method comprising: executing a single instruction to, for each data lane of a source vector register, calculate a horizontal and cross addition or subtraction between packed data elements of the source vector register where the decision of whether to add or subtract is dependent upon a bit in an immediate value of the instruction, wherein the instruction includes a destination vector register operand, the source vector register operand, the immediate, and an opcode; and storing a result of each a horizontal and cross addition or subtraction between packed data elements into the destination register, wherein for the least significant data element position of the destination register, the result stored is the least significant data element of the source register being added to or subtracted from the second most least significant data element of the source register wherein the decision of addition or subtraction is based on the least significant bit of the immediate; wherein for the second most least significant data element position of the destination register, the result stored is the result of the third most least significant data element of the source register being added to or subtracted from the fourth most least significant data element of the source register wherein the decision of addition or subtraction is based on the third most least significant bit of the immediate; wherein for the third most least significant data element position of the destination register, the result stored is the result of the second most least significant data element of the source register being added to or subtracted from the least significant data element of the source register wherein the decision of addition or subtraction is based on the second most least significant bit of the immediate; and wherein for the fourth most significant data element position of the destination register, the result stored is the result of the fourth most least significant data element of the source register being added to or subtracted from the third most least significant data element of the source register wherein the decision of addition or subtraction is based on the fourth most least significant bit of the immediate.