Patent ID: 9357648
Filing Date: 2016-05-31
CPC Classification: G06F,G11C,H01L,H05K,Y02D,Y10T

Claim Text:
1. A multi-layer interposer substrate, comprising: multiple layers of single interposer substrates stacked to form the multi-layer interposer substrate, each single interposer substrate, comprising: a first array of interposer interconnects in the single interposer substrate, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects; a second array of interposer interconnects in the single interposer substrate, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate; and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects, the conductive trace arranged to have a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects; and an array of connections for a peripheral circuit on each single interposer connected to the at least one conductive trace.