Patent ID: 9230987
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A monolithic three-dimensional memory device comprising: a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate; at least one dielectric material layer overlying the lower stack structure; an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the at least one dielectric material layer; a memory opening extending through the second stack, the at least one dielectric material layer, and the first stack; a memory film and at least one semiconductor channel located within the memory opening; at least one via contact structure vertically extending through the upper stack structure, the at least one dielectric material layer, and a portion of the lower stack structure, and electrically shorted to at least one conductive structure located in, or underneath, the first stack; and a plurality of dielectric pillar structures comprising a stress-compensating dielectric material and extending through first stepped surfaces of the first stack, wherein: the at least one via contact structure comprises: a second via contact portion embedded within the upper stack structure; the lower stack structure further comprises a first dielectric material portion located on, and over, first stepped surfaces of the first stack; the upper stack structure further comprises a second dielectric material portion located on, and over, second stepped surfaces of the second stack; the at least one via contact structure extends through the first dielectric material portion and the second dielectric material portion; and at least two of the plurality of dielectric pillar structures pass through different numbers of layers among the first electrically insulating layers, and the stress-compensating dielectric material and the electrically conductive layers apply stresses of opposite types to the substrate.