Patent ID: 9390800
Filing Date: 2016-07-12
CPC Classification: G11C

Claim Text:
1. A semiconductor memory comprising: a plurality of memory cell units, each of the memory cell units including a plurality of memory cells to which a current path is connected in series and to which i-value (i is an integer of 2 or more) data is writable; a plurality of word lines, each of the word lines being connected to gates of the memory cells arranged in a row direction among the memory cells; a source line connected to one end of the memory cell units; a plurality of bit lines each connected to the other end of the memory cell units; and a control circuit which controls an operation of the memory cell units, wherein during writing to selected cells connected to a selected word line which is selected as a write target of first k-level data (k is an integer of 2 or more) among the word lines, in a first unselected adjacent word line adjacent to the selected word line on the source line side and a second unselected adjacent word line adjacent to the selected word line on the bit line side, the control circuit applies a first unselect voltage corrected in accordance with a result of reading of data from first unselected cells connected to the first unselected adjacent word line to the first unselected adjacent word line and a second unselect voltage corrected in accordance with a result of reading of data from second unselected cells connected to the second unselected adjacent word line to the second unselected adjacent word line during reading from the selected cells and applies a read voltage to the selected word line to read first (k−1)-level data from the selected cells, and a number of voltage values included in the first unselect voltage is less than a number of voltage values included in the second unselect voltage, and the control circuit writes data to the selected cells in accordance with the read first (k−1)-level data and the first k-level data to be written.