Patent ID: 9530758
Filing Date: 2016-12-27
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor die pair, the method comprising: bonding an active side of each of a plurality of singulated first dies to an active side of a corresponding one of a plurality of second dies on a wafer to form wafer-level first and second die pairs, each of the plurality of singulated first dies smaller in area than the corresponding one of the plurality of second dies; forming a molding layer above the wafer-level first and second die pairs; grinding the molding layer to expose each of the plurality of singulated first dies and interconnect bumps of each of the plurality of second dies; and subsequent to grinding the molding layer, singulating the first and second die pairs to form a plurality of singulated first and second die pairs, wherein forming the plurality of singulated first and second die pairs comprises forming each singulated first and second die pair comprising a first semiconductor die having an active side with a surface area, the first semiconductor die comprising no through silicon vias (TSVs), and a second semiconductor die having an active side with a surface area larger than the surface area of the first semiconductor die, the active side of the first semiconductor die facing and conductively coupled to the active side of the second semiconductor die, and the second semiconductor die comprising interconnects that bypass, and are adjacent to, the first semiconductor die, wherein the interconnects of the second semiconductor die of each of the plurality of singulated first and second die pairs comprise a plurality of bumps that extend from the active side of the second semiconductor die, and are at least partially adjacent to the first semiconductor die, and further to a plurality of solder balls, and wherein the first semiconductor die, the plurality of bumps, and the plurality of solder balls are housed in the molding layer.