Patent ID: 9286267
Filing Date: 2016-03-15
CPC Classification: G06F

Claim Text:
1. A processor comprising: a controller to receive a round instruction of an instruction set architecture (ISA) having a format including a source operand, a destination operand and an immediate data element, wherein the controller is to decode the immediate data element to determine if a default round mode is to be overridden based on an override indicator of the immediate data element, and if the default round mode is to be overridden to decode a round mode field of the immediate data element; an execution unit coupled to the controller to execute a round operation responsive to the round instruction, wherein the execution unit is to execute the round operation according to the round mode field of the immediate data element if the default round mode is to be overridden based on the override indicator; and a configuration register, wherein when the configuration register is set for denormal numbers as zero and the source operand is a denormal number, the processor is to convert the source operand to zero before execution of the round operation.