Patent ID: 9448795
Filing Date: 2016-09-20
CPC Classification: G06F

Claim Text:
1. A processor comprising: a plurality of packed data registers; a decode unit to decode an instruction that is to indicate a source packed data register of the plurality of packed data registers that is to have at least four packed memory indices, which are each to have no more than 16-bits, and the instruction to indicate a destination packed data register of the plurality of packed data registers; and an execution unit coupled with the decode unit and coupled with the packed data registers, the execution unit operable, in response to the instruction, to store a packed data result in the destination packed data register, the packed data result to have at least four data elements that are each to have been loaded from a memory location, in only a limited range of a memory, that is to have been indicated by a different corresponding one of the at least four packed memory indices.