Patent ID: 9443848
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a first gate, a second gate, and a third gate disposed on a substrate; a first hard mask arranged on a top surface of the first gate, a second hard mask arranged on a top surface of the second gate, and a third hard mask arranged on a top surface of the third gate; a dielectric layer disposed on the substrate and between the first gate and the second gate, and between the second gate and the third gate; a first contact opening that extends through the dielectric layer between the first gate and the second gate; a second contact opening that extends through the dielectric layer between the second gate and the third gate; and a conductive material disposed in the first contact opening and the second contact opening; wherein the first contact opening extends from a sidewall of the first gate to a sidewall of the second gate, has a sidewall that is substantially perpendicular to the first gate and the second gate, and a top surface of the first contact opening is substantially flush with a top surface of the first hard mask of the first gate, and the second contact opening extends from a sidewall of the second gate to a sidewall of the third gate, has a sidewall that is substantially perpendicular to the second gate and third gate, and a top surface of the second contact opening is substantially flush with a top surface of the second hard mask of the second gate.