Patent ID: 9305607
Filing Date: 2016-04-05
CPC Classification: G11C

Claim Text:
1. An electronic memory component, comprising: at least one two-dimensional matrix including a plurality of unitary memory cells, each of said unitary memory cells including two terminals, said unitary memory cells are each realized at the intersection of a first conductor defining a column and a second conductor defining a row within said matrix, and are each connected to said first and second conductors; and column selection means outside said matrix, said column selection means arranged according to a binary logic to selectively activate at least one column conductor connected to at least one defined cell that must be subjected to read or write processing, the column selection means including at least two transistors for each column, which are each arranged to connect at least said column conductor selectively to a first potential or to a second potential different from said first potential, wherein the connection of said column conductor to said first potential cooperates with read management means or write management means of at least one defined row to pass a read current, or a write current to one state in one direction, through a cell belonging to said column and to said row, and wherein the connection of said column conductor to said second potential cooperates with write management means of said at least one row in order to pass a write current to the other state through said cell in the other direction.