Patent ID: 9343499
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. An integrated circuit system, comprising: a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first dielectric layer; a second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second dielectric layer; a wafer bonding region disposed at an interface of a front side of the first dielectric layer of the first device wafer and a front side of the second dielectric layer of the second device wafer such that wafer bonding region bonds the first device wafer to the second device wafer, wherein the wafer bonding region includes dielectric material having a higher silicon concentration than a dielectric material of the first and second dielectric layers of the first and second device wafers; and a conductive path coupling the first conductor to the second conductor, wherein the conductive path is formed in a cavity etched through the wafer bonding region between the first conductor and the second conductor.