Patent ID: 9437483
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method of fabricating a memory device comprising: providing a plurality of insulation layers on a substrate extending in a horizontal direction; providing a plurality of conductive layers, each of at least two of the conductive layers between a neighboring lower insulation layer and a neighboring upper insulation layer; providing a plurality of vertical channels of semiconductor material extending in a vertical direction through the plurality of insulation layers and the plurality of conductive layers; providing a gate insulating layer between each of the at least two of the conductive layers and the vertical channels that insulates the at least two of the conductive layers from the vertical channels; etching the at least two of the conductive layers to form at least two conductive patterns and conductive contact regions of the at least two of the conductive patterns, the conductive contact regions of the at least two of the conductive patterns being in a stepped configuration so that a contact region of a neighboring lower conductive pattern extends in the horizontal direction beyond a contact region of a neighboring upper conductive pattern; and providing an etch stop layer on the conductive contact regions, the etch stop layer having a first portion on a first one of the plurality of conductive patterns and having a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.