Patent ID: 9318489
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: an unstrained substrate layer; a dielectric layer located within a top surface region of the unstrained substrate layer; a first strained fin structure located on the dielectric layer, the first strained fin structure having a first strain characteristic; an unstrained fin structure located on the dielectric layer, the unstrained fin structure located adjacent to the first strained fin structure; a second strained fin structure located on the dielectric layer between the first strained fin structure and the unstrained fin structure, the second strained fin structure having a second strain characteristic; a third strained fin structure located on the dielectric layer adjacent to the first strained fin structure, the third strained fin structure having the second strain characteristic; and a fourth strained fin structure located on the dielectric layer adjacent to the at least one unstrained fin structure, the fourth fin structure having a second strain characteristic; wherein the first strained fin structure, the second strained fin structure, the third strained fin structure, the fourth strained fin structure, and the unstrained fin structure are formed from a multilayer lattice matched structure.