Patent ID: 9240234
Filing Date: 2016-01-19
CPC Classification: G05F,G11C,H01L,H03M,H04N

Claim Text:
1. A column driver integrated circuit (IC) having a channel buffer block, wherein the channel buffer block comprises: a first differential amplifier having a first bias circuit configured to generate a first bias current inversely proportional to a first bias voltage and a first transistor pair configured to amplify a difference between input voltages using the first bias current; a second differential amplifier having a second bias circuit configured to generate a second bias current proportional to a second bias voltage and a second transistor pair configured to amplify the difference between the input voltages using the second bias current; a first coupling capacitor configured to decrease the first bias voltage using a first control voltage during a slewing interval; and a second coupling capacitor configured to increase the second bias voltage using a second control voltage during the slewing interval.