Patent ID: 9438234
Filing Date: 2016-09-06
CPC Classification: G11C,H03K

Claim Text:
1. A logic circuit comprising: a first circuit; a first retention circuit; a second retention circuit; and a second circuit, wherein each of the first retention circuit and the second retention circuit comprises a first switch and a second switch electrically connected to each other in series and a capacitor electrically connected to a connection portion of the first switch and the second switch, wherein each of the first switch and the second switch of each of the first retention circuit and the second retention circuit is a transistor comprising a channel formation region comprising an oxide semiconductor, wherein the first circuit is configured to generate complementary data from a piece of input data, wherein the first retention circuit and the second retention circuit are configured to retain the complementary data, and wherein the second circuit is configured to amplify the complementary data retained in the first retention circuit and the second retention circuit.