Patent ID: 9437444
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: forming a plurality of first hard mask patterns separated by a plurality of trenches on a target layer; forming a plurality of second hard mask patterns by filling the plurality of trenches; forming a plurality of first opening units in the plurality of second hard mask patterns; forming a plurality of second opening units in the plurality of first hard mask patterns; and forming a plurality of patterns corresponding to the plurality of first opening units and the plurality of second opening units by etching corresponding portions of the target layer, wherein forming the plurality of first opening units comprises: wherein forming the plurality of second opening units comprises: wherein a width of each of the plurality of first opening units is substantially equal to a width spacing apart the plurality of second opening units, and a width of each of the plurality of second opening units is substantially equal to a width spacing apart the first opening units.