Patent ID: 9496385
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a first dielectric layer over a substrate; forming a gate structure over a first portion of the first dielectric layer, wherein the gate structure includes a gate electrode; forming a sidewall spacer over a second portion of the first dielectric layer and on the gate structure; converting the second portion of the first dielectric layer and an exposed third portion of the first dielectric layer to a first portion of a second dielectric layer and a second portion of the second dielectric layer, respectively, wherein the second dielectric layer is more etch resistant than the first dielectric layer; removing the second portion of the second dielectric layer and a portion of the substrate to form a recess in the substrate adjacent the sidewall spacer; forming a source/drain (S/D) feature in the recess; and removing the gate electrode and the first portion of the first dielectric layer to form a gate trench, wherein the first portion of the second dielectric layer prevents lateral etch towards the S/D feature during the removing of the gate electrode and the first portion of the first dielectric layer.