Patent ID: 9450610
Filing Date: 2016-09-20
CPC Classification: G06F,H03M

Claim Text:
1. A method comprising: storing one or more two-index Log-Likelihood Ratio (LLR) look-up table in a memory controller, the one or more two-index LLR look-up table including a LLR, the hard-and-soft-decision bits associated with the LLR and the neighboring cell read pattern associated with the LLR; performing a plurality of reads of a target cell of a nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits associated with a bit stored in the target cell, wherein the bit stored in the target cell is part of a codeword stored in the nonvolatile memory storage module; performing reads of a plurality of neighboring cells to the target cell of the nonvolatile memory storage module to generate a plurality of neighboring cell reads, each of the neighboring cells in the plurality of neighboring cells adjoining the target cell; combining the results of the neighboring cell reads to generate a neighboring cell read pattern that corresponds to the pattern of the neighboring cell reads; and accessing the one or more two-index LLR look-up table using the plurality of target cell hard-and-soft-decision bits and the generated neighboring cell read pattern to identify the corresponding LLR; and sending the identified LLR to a Low-Density Party Check (LDPC) decoder for decoding of the codeword stored in the nonvolatile memory storage module.