Patent ID: 9330983
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device), each having sidewall spacers on opposite sidewalls of a dummy gate, and source drain regions adjacent to the sidewall spacers; conformally forming a first liner on the sidewall spacers of both the pFET device and the nFET device; depositing a fill material directly above and in direct contact with the first liner, such that an upper surface of the fill material is substantially flush with an upper surface of a portion of the first liner above the dummy gates of both the pFET device and the nFET device; removing a portion of the fill material and a portion of the first liner to expose only the pFET device, an etch rate of the first liner is substantially different from an etch rate of the sidewall spacers of the pFET device, such that the portion of the first liner is removed in its entirety selective to the sidewall spacers of the pFET device; conformally forming a second liner above and in direct contact with the pFET device and along a vertical sidewall of a remaining portion of the fill material above the nFET device; depositing a first inter level dielectric above the second liner; removing the remaining portion of the fill material and a remaining portion of the first liner to expose the nFET device, the etch rate of the first liner is substantially different from an etch rate of the sidewall spacers of the nFET device, such that the remaining portion of the first liner is removed in its entirety selective to the sidewall spacers of the nFET device; and conformally forming a third liner above and in direct contact with the nFET device and in direct contact with a vertical portion of the second liner.