Patent ID: 9520863
Filing Date: 2016-12-13
CPC Classification: H03K

Claim Text:
1. A dual-port negative level sensitive preset data retention latch comprising: a clocked inverter configured to receive a first data bit, a first clock signal, a second clock signal, a preset control signal and a first retention mode control signal wherein the first clock signal, the second clock signal, the preset control signal and the first retention mode control signal determine whether a data output from the clocked inverter is the binary compliment of the first data bit or an indeterminate value; a dual-port latch configured to receive the data output of the clocked inverter, a second data bit, the first clock signal, the second clock signal, the first retention mode control signal, a second retention mode control signal, the preset control signal, a first latch control signal and a second latch control signal wherein the first clock signal, the second clock signal, the first retention mode control signal, the second retention mode control signal, the preset control signal, the first latch control signal and a second latch control signal determine whether the data output of the clocked inverter or the second data bit is latched in the dual-port latch; wherein the output of the clocked inverter is received by the dual-port latch when the first clock signal changes from a high logical signal to a low logical signal; and wherein the dual-port latch is latched when the first clock signal changes from a low logical signal to a high logical signal.