Patent ID: 9501376
Filing Date: 2016-11-22
CPC Classification: G01R,G06F

Claim Text:
1. A method for testing an I/O (input/output) interface, comprising: receiving a test data sequence at a hardware interface of a device under test from a test source separate from the device under test; distributing each bit of the test data sequence concurrently to each signal line of a group of multiple signal lines, each signal line interfacing a hardware I/O buffer of the device under test, wherein the multiple signal lines of the group share a common timing signal; testing for errors at each hardware I/O buffer, including detecting an error for any signal line when the signal line does not receive a bit of the test data sequence correctly for a given timing setting; accumulating pass/fail data for all signal lines of the group at the device under test based on the detected errors; and sending a pass/fail indication value to the test source from the device under test only after accumulating pass/fail information for all bits of the test data sequence for all the signal lines of the group.