Patent ID: 9355691
Filing Date: 2016-05-31
CPC Classification: G06F,G11C

Claim Text:
1. A memory controller for reading data from a memory, wherein the memory has an access latency of ‘L’ memory clock cycles, where L is a positive integer, the controller comprising: a FIFO (first in first out) buffer for receiving data read from the memory; a clock module for providing a memory clock signal to the memory and to the FIFO buffer; a control signal generation module for asserting a control signal and applying said control signal to the memory; a counter for determining an assertion time of said control signal as a function of a number ‘N’ of cycles of the memory clock signal, where N is a positive integer; and a data sampling module coupled to the counter and to the FIFO buffer for sampling an output of the FIFO buffer at a point in time that is a function of N and L.