Patent ID: 9336865
Filing Date: 2016-05-10
CPC Classification: G11C

Claim Text:
1. A multi-port SRAM module, comprising: a memory cell array which comprises a plurality of memory cells, wherein each memory cell comprises at least a first port and a second port; a first word line, coupled to a plurality of memory cells of a target row, for controlling whether the first port is open or not; a second word line, coupled to the plurality of memory cells of the target row, for controlling whether the second port is open or not; and a switch, coupled to the first word line and the second word line, for determining whether to couple the second word line to a reference voltage level according to a voltage level of the first word line; wherein, when the first word line is disabled and the second word line is enabled, the second word line has a first enabling voltage level, and when the first word line and the second word line are enabled at the same time, the second word line has a second enabling voltage level different form the first enabling voltage level.