Patent ID: 9355952
Filing Date: 2016-05-31
CPC Classification: H01L,H05K

Claim Text:
1. A method of forming an integrated circuit (IC) package substrate, the method comprising: laminating a dielectric layer over a first metal feature; laser drilling a via hole in the dielectric layer to expose the first metal feature; laser patterning a trace recess in the dielectric layer laterally displaced from the via hole; electrolytically plating a fill metal into the via hole and the trace recess; planarizing the fill metal to a top surface of the dielectric layer to form a metallized via and a metallized trace; laminating and patterning dry resist film to expose the metallized via without exposing the metallized trace; plating a surface finish metal over the exposed metallized via; removing the dry resist film; and exposing the dielectric layer between the metallized via and the metallized trace.