Patent ID: 9312230
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A semiconductor die comprising: a substrate; a passivation layer having a metal contact opening over the substrate; a bond pad having a first portion inside the metal contact opening and a second portion overlying the passivation layer, the second portion of the bond pad having a first width; a buffer layer disposed over the bond pad, the buffer layer having a pillar contact opening with a second width to expose a portion of the bond pad; and a conductive pillar having a first portion inside the pillar contact opening and a second portion disposed over the buffer layer, the second portion of the conductive pillar having a third width, wherein a ratio of the second width to the first width is between about 0.35 and about 0.65, and a second ratio of the second width to the third width is between about 0.35 and about 0.65.