Patent ID: 9262269
Filing Date: 2016-02-16
CPC Classification: G06F,H03M,H04L

Claim Text:
1. A module comprising: an electrically erasable programmable memory chip, the memory chip to receive a read command and transmit a plurality of data bits, along with a corresponding first error detection code, in response to the read command; a plurality of signal lines coupled to the memory chip, the plurality of signal lines to carry the plurality of data bits in parallel, the plurality of data bits time multiplexed with the first error detection code; and a memory controller coupled to the memory chip, the memory controller to send the read command to the memory chip, and receive the plurality of data bits along with the first error-detection information from the memory chip via the plurality of signal lines, the memory controller comprising a circuit to generate second error-detection information corresponding to the received plurality of data bits and signal an error condition based on a comparison between the first error-detection information and the second error-detection information, the memory controller to instruct the memory chip to re-transmit the plurality of data bits over the plurality of signal lines in the event of the error condition.