Patent ID: 9373526
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method for forming a chip package, comprising: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming one or more conducting bumps on a lower surface of the conducting plate and below at least one of the conducting pads, and the conducting bumps are not formed below each one of the conducting pads; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulate from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads; wherein the step of patterning the conducting plate comprises performing an etching process on the lower surface of the conducting plate to remove the portion of the conducting plate, and the conducting bumps serve as a etching mask during the etching process.