Patent ID: 9281817
Filing Date: 2016-03-08
CPC Classification: H03K

Claim Text:
1. An integrated circuit comprising: sequential logic operable to store and output a plurality of data, wherein a respective location of each of said plurality of data in said sequential logic is assigned a respective address represented by a plurality of digits; sequence generation logic operable to generate an address sequence that comprises a sequence of addresses of said plurality of data in said sequential logic; and a multiplexer structure comprising a plurality of levels of multiplexers arranged in a hierarchical order, each level comprising one or more multiplexers, wherein said multiplexer structure is coupled with an output of said sequential logic and is further operable to control an output sequence of said plurality of data from said sequential logic in accordance with said address sequence, wherein said address sequence is generated based on reducing an aggregate number of transistor switching activities across said multiplexer structure during outputting said plurality of data from said sequential logic.