Patent ID: 9348184
Filing Date: 2016-05-24
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate comprising gate lines, data lines and a plurality of pixel units defined by intersecting of the gate lines and the date lines, each of which comprises a pixel electrode, wherein barrier structures are disposed on both sides of the data lines or the gate lines, the barrier structures do not overlap with the data lines or the gate lines in a direction vertical to the array substrate, and the barrier structures extend to below an end, which is close to the data lines or the gate lines, of the pixel electrode and overlap part of the pixel electrode in the direction vertical to the array substrate, the pixel electrode is formed on a passivation layer which is arranged on the gate lines or the data lines, an upper surface of the passivation layer is a flat surface, and the barrier structures are concave structures and are formed in the passivation layer; in a direction parallel to the upper surface of the passivation layer, the concave structures are formed between the pixel electrode and the data lines or the gate lines; and a peripheral portion, of the concave structures, away from the data lines or the gate lines overlaps the end of the pixel electrode.