Patent ID: 9401407
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A transistor comprising: a gate electrode layer; a gate insulating layer in contact with the gate electrode layer; a semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed between the semiconductor layer and the gate electrode layer; a source electrode layer in a comb shape, including electrode tooth portions arranged adjacently at a predetermined interval and a connection portion for connecting the electrode tooth portions; and a drain electrode layer in a comb shape, including electrode tooth portions arranged adjacently at a predetermined interval and a connection portion for connecting the electrode tooth portions, wherein the source electrode layer and the drain electrode layer are disposed such that the electrode tooth portions of the source electrode layer and the electrode tooth portions of the drain electrode layer face each other without interdigitating with each other, wherein a part of an end of a first electrode tooth portion of the electrode tooth portions of one of the source and drain electrode layers and a part of the connection portion adjacent to the first electrode tooth portion face an end of one of the electrode tooth portions of the other of the source and drain electrode layers, wherein the end of the first electrode tooth portion overlaps the gate electrode layer, and wherein the connection portion does not overlap the gate electrode layer.