Patent ID: 9263577
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method of forming a plurality of ferroelectric field effect transistors, comprising: forming a plurality of trenches into semiconductive material, the trenches being parallel and longitudinally elongated relative to horizontal; forming inner dielectric over sidewalls of the trenches and over semiconductive material that is between the trenches; forming first inner conductive material over the inner dielectric, bases of the trenches, the trench sidewalls, and the semiconductive material that is between the trenches, the first inner conductive material being continuous within and between the trenches at least in a direction orthogonal to a horizontal longitudinal running direction of the parallel trenches; forming second inner conductive material over and electrically coupled to the first inner conductive material; the second inner conductive material being formed elevationally thicker over the semiconductive material that is between the trenches than any that is formed elevationally centrally over the trench bases; in at least one common etching step, anisotropically etching both: after the etching, forming outer ferroelectric material elevationally over the first inner conductive material that is over the semiconductive material that is between the trenches; forming outer conductive material elevationally over the outer ferroelectric material; and forming source/drain regions in the semiconductive material that is between the trenches on opposing sides of the first inner conductive material that overlies the semiconductive material that is between the trenches.