Patent ID: 9324568
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device, comprising: forming a drain region and a channel region on the drain region; forming a plurality of trenches at intervals, the trenches having a depth reaching the drain region and penetrating through the channel region; forming a gate insulating layer on an exposed portion of the channel region and the drain region; forming a gate conductor within the trench such that a surface of the gate conductor is deeper than a surface of the channel region; transforming an upper part of the channel region to form a source region; forming an insulating layer on an exposed portion of the gate conductor and the gate insulating layer; selectively removing the gate insulating layer and the insulating layer such that the source region includes an exposed protrusion higher than a surface of the insulating layer buried within the trench by a protrusion amount of 25 nm to 125 nm; and forming a source electrode by silicidizing an interface between the source electrode and the source region, the source electrode including an adhesion layer formed of a metal layer having a film thickness of 150 Å or smaller to restrain or prevent creation of a void during a thermal treatment, and the source electrode being connected to the source region.