Patent ID: 9524755
Filing Date: 2016-12-20
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device, comprising: a semiconductor substrate; a stacked body provided on the semiconductor substrate, including insulating films and electrode films, each of the insulating films and each of the electrode films being stacked alternately in the stacked body; a semiconductor pillar provided inside the stacked body, the semiconductor pillar extending in a stacking direction of the insulating films and the electrode films, a lower end of the semiconductor pillar being connected to the semiconductor substrate; a charge storage film provided between the semiconductor pillar and one of the electrode films; an electrode member provided inside the stacked body, the electrode member extending in the stacking direction, a lower end of the electrode member being connected to the semiconductor substrate; and a control circuit setting an upper end of the semiconductor pillar to a floating state, applying a first potential to the semiconductor substrate, applying a second potential to the electrode member, and applying a third potential to the one of the electrode films, the second potential being lower than the first potential, the third potential being lower than the second potential.