Patent ID: 9391097
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A thin film transistor array substrate, comprising: a substrate and a thin film transistor formed on the substrate, wherein the thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor active layer, an etch stop layer, a source electrode and a drain electrode, wherein, the gate insulating layer is interposed between the gate electrode and the semiconductor active layer, the etch stop layer covers the semiconductor active layer, and has a first via hole and a second via hole formed therein which expose a part of the semiconductor active layer, the source electrode of the thin film transistor contacts with the semiconductor active layer through the first via hole, and the drain electrode of the thin film transistor contacts with the semiconductor active layer through the second via hole, wherein, a peripheral edge pattern of the etch stop layer and the pattern of the semiconductor active layer are consistent with each other, wherein, the peripheral edge of the etch stop layer is aligned with a peripheral edge of the semiconductor active layer, wherein, the etch stop layer does not extend beyond the pattern of the semiconductor active layer, wherein the thin film transistor array substrate further comprises a gate line, a gate line lead wire, a data line and a data lead wire, the gate line and the gate line lead wire are located on the same layer as the gate electrode; and the data line and the data lead wire are located on the same layer as the source electrode and the drain electrode, wherein the thin film transistor array substrate further comprises an assistant gate line lead wire which is located on the same layer as the data line and above the gate line lead wire, the gate line lead wire contacts with the assistant gate line lead wire through a third via hole, and wherein the thin film transistor array substrate comprises a display region and a peripheral wiring region, the thin film transistor, the gate line and the data line are disposed in the display region, the gate line lead wire, the assistant gate line lead wire and the third hole are disposed in the peripheral wiring region.