Patent ID: 9275874
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A method for fabricating an integrated circuit, the method comprising: forming a trench with a first sidewall and a second sidewall; filling the trench with a metal and forming an overburden portion of the metal outside of the trench; performing a first planarization process with an etching slurry to remove the overburden portion of the metal; and performing a second planarization process with an abrasiveless etching slurry to recess the metal within the trench, form a recessed surface extending from the first sidewall to the second sidewall, and expose a portion of the first sidewall and a portion of the second sidewall; wherein performing the second planarization process with the abrasiveless etching slurry comprises lowering a surface of the metal within the trench by about 5 nm to about 15 nm to the recessed surface.