Patent ID: 9324650
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a first metal line and a second metal line in a first inter-level dielectric (ILD); forming a first recessed opening by recessing the first metal line below a top surface of the first ILD; forming a cap on the first ILD and in the first recessed opening; forming a second ILD on the cap; forming a higher level hardmask on the second ILD; forming a metal trench hardmask on the higher level hardmask; forming a metal trench pattern in the metal trench hardmask, wherein a portion of the metal trench pattern is above a portion of the first recessed opening; forming a via pattern material on the metal trench hardmask and in the metal trench pattern; forming a first via pattern in the via pattern material, the first via pattern is located above a portion of the metal trench pattern and above the portion of the first recessed opening, wherein the first via pattern is self aligned to the metal trench pattern; removing the via pattern material; forming a first higher level trench in the higher level hardmask and in the second ILD, wherein the first higher level trench includes a first via opening, wherein the first via opening is the first via pattern transferred to a lower level; and forming a third metal line and a first via in the first higher level trench and in the first via opening, respectively, wherein the via connects the first metal line to the third metal line.