Patent ID: 9397146
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a device comprising: providing a substrate; forming an inter-layer dielectric (ILD) layer over the substrate; forming, on the ILD layer, a vertical structure having a plurality of memory with one or more selectors, the vertical structure is made of a plurality of conductive stacks, wherein a conductive stack of the plurality of conductive stacks is formed by forming and stacking a successive conductive stack by repeating steps (a)-(e) over a preceding conductive stack formed by steps (a)-(e) to form the vertical structure on the ILD layer; etching an opening through a middle portion of the plurality of conductive stacks which form the vertical structure and the ILD layer after forming the plurality of conductive stacks; and filling the opening with a conductor layer.