Patent ID: 9368674
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor structure, comprising: designating a street between a first portion of a wafer and a second portion of the wafer, wherein the street has a center, a first side and a second side; forming at least two slots in the wafer, wherein a first slot is formed between the first side of the street and the center of the street and a second slot is formed between the second side of the street and the center of the street, wherein the first slot has an inner wall directly abutting a first electrical device formed in the wafer and an outer wall facing the center of the street; wherein the second slot has an inner wall directly abutting a second electrical device formed in the wafer and an outer wall facing the center of the street; wherein the first slot and the second slot electrically isolate the first electrical device and the second electrical device from the center of the street; at least partially filling the first slot and the second slot with a protective material; cutting along the center of the street, for at least partially singulating the wafer, while leaving a first portion of the wafer between the outer edge of the first slot and the center of the street and while leaving a second portion of the wafer between the outer edge of the second slot and the center of the street; and removing the protective material from the first slot and the second slot.