Patent ID: 9496175
Filing Date: 2016-11-15
CPC Classification: H01L,H04N

Claim Text:
1. A semiconductor device including a substrate and an insulating layer, the substrate having a cell area and a peripheral area, unit circuits being arranged in a matrix in the cell area, the peripheral area being arranged around the cell area, and the insulating layer being arranged on the substrate, wherein in a plan view of a surface of the substrate, the insulating layer comprises: a first region located on the cell area and having a rectangular outer edge including two sides along a row direction of the unit circuits and two sides along a column direction of the unit circuits; a second region located on the peripheral area and having a rectangular inner edge including two sides along a row direction of the cell area and two sides along a column direction of the cell area; a third region located on an intermediate area between the cell area and the peripheral area; and a fourth region located on the intermediate area, located between the second region and the third region, and forming a boundary with the third region, wherein a conductive member is embedded in the first region and the third region, and no conductive member is embedded in the fourth region, and the boundary has a curved portion.