Patent ID: 9477594
Filing Date: 2016-10-25
CPC Classification: G06F,Y02D

Claim Text:
1. A semiconductor device comprising: a first flash memory configured to store a plurality of first instructions; a second flash memory configured to store a plurality of second instructions to be executed according to a predetermined control instruction included in the first instructions; an access control unit configured to control access to the first flash memory and the second flash memory; a memory interface configured to select one of the first flash memory and the second flash memory and to provide a CPU with an instruction which is sequentially read out from the selected flash memory, wherein the memory interface further comprises an instruction detecting unit configured to determine whether the instruction is a first control instruction, and, when determined to be the first control instruction, acquire a first jump destination address value indicated by the first control instruction; and a program counter monitoring unit configured to compare a value of a program counter of the CPU with the first jump destination address value acquired by the instruction detecting unit and to output a first trigger signal when, as a result of the comparison, the value of the program counter matches the first jump destination address value, wherein the access control unit performs control so as to put the second flash memory into a state of being ready for read-out operation in accordance with the first jump destination address value acquired by the instruction detecting unit, and wherein the memory interface selects the second flash memory based on the first trigger signal output from the program counter monitoring unit.