Patent ID: 9466686
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a substantially flat surface on which the channel is formed; depositing a second dielectric layer over the bilayer graphene layer, wherein the bilayer graphene layer provides a substantially flat surface on which the second dielectric layer is deposited; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.