Patent ID: 9240472
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device that has a transistor region and a surge-protector region, comprising: a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer in the transistor region; a source electrode and a drain electrode formed on the second semiconductor layer in the transistor region, a whole bottom of the source electrode, and a whole bottom of the drain electrode contacting with the second semiconductor layer; a surge-protector first electrode formed on the third semiconductor layer in the surge protection region; a surge-protector second electrode, and a surge-protector third electrode formed on the second semiconductor layer in the surge-protector region, a whole bottom of the surge-protector second electrode, and a whole bottom of the surge-protector third electrode contacting with the second semiconductor layer, wherein the source electrode and the surge-protector second electrode are connected to each other, wherein the drain electrode and the surge-protector third electrode are connected to each other, wherein the surge-protector first electrode is formed between the surge-protector second electrode and the surge-protector third electrode, wherein a distance between the surge-protector first electrode and the surge-protector third electrode is smaller than a distance between the gate electrode and the drain electrode, and wherein the width of the third semiconductor layer under the gate electrode is wider than the width of the third semiconductor layer under the surge-protector first electrode.