Patent ID: 9269710
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a region of semiconductor material having a first conductivity type; an isolation region about the entire periphery of the region of semiconductor material, wherein the isolation region electrically insulates the region of semiconductor material; a stressor region formed in the region of semiconductor material and comprising a first stressor region; a first gate structure, a second gate structure, and a third gate structure formed overlying the region of semiconductor material, wherein the stressor region is disposed between the first gate structure and the second gate structure; a second stressor region formed in the region of semiconductor material between the second gate structure and the third gate structure; a first source/drain region having a second conductivity type formed in a first portion of the region of semiconductor material disposed between the first gate structure and the isolation region, the first source/drain region being adjacent to a channel region underlying the first gate structure; and a second source/drain region having the second conductivity type formed in the stressor region, the second source/drain region being adjacent to the channel region underlying the first gate structure; wherein the first gate structure, the second gate structure, and the third gate structure are in electrical communication with shared source/drain regions disposed therebetween.