Patent ID: 9294592
Filing Date: 2016-03-22
CPC Classification: H04J,H04L,H04N

Claim Text:
1. A system comprising: a serializer comprising a framing circuit that in turn comprises header insertion circuitry, filler bits insertion circuitry, a buffer, and control circuitry, wherein: said header insertion circuitry is operable to generate frame headers; said filler bits insertion circuitry is operable to generate filler bits; said buffer is operable to buffer bits of an input datastream; said control circuitry is operable to select, at any given time, whether bits from said header insertion circuitry, bits from said filler bits insertion circuitry, or bits from said buffer are placed into a serial output stream; and said selection is such that filler bits are periodically inserted into said output stream at times determined based on a value of a parameter stored in said serializer.