Patent ID: 9252792
Filing Date: 2016-02-02
CPC Classification: H03K,H03L

Claim Text:
1. An oscillator, comprising: a digital-to-analog converter that is arranged to receive a tuning code, to select one or more individual capacitors in a capacitor bank in response to the received tuning code, and to generate a frequency control signal in response to the selected one or more individual capacitors in the capacitor bank and in response to one or more phase control signals; an amplifier that is arranged to generate an integrated control signal in response to the frequency control signal and in response to a selected current; an oscillator that is arranged to generate an output frequency signal in response to the integrated control signal; and a clock generator that is arranged to generate the one or more phase control signals in response to the output frequency signal; wherein the capacitor bank is a split capacitor bank that includes a higher-weight capacitor bank, a bridge capacitor, and a lower-weight capacitor bank, wherein a first terminal of the bridge capacitor is coupled to a first terminal of each of the individual capacitors of the higher-weight capacitor bank, and wherein a second terminal of the bridge capacitor is coupled to a first terminal of each of the individual capacitors of the lower-weight capacitor bank; wherein the split capacitor bank is arranged to couple a voltage reference signal to the first terminal and a second terminal of each individual capacitor in the higher-weight capacitor bank during a first phase that is determined by the one or more phase control signals, to couple the voltage reference signal to the first terminal of the bridge capacitor during the first phase, and to couple the voltage reference signal to a second terminal of each individual capacitor in the lower-weight capacitor bank during the first phase.