Patent ID: 9368573
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device, the method comprising: forming a first source/drain region within a first well region; forming a second source/drain region within a second well region; forming an active region electrically coupled between the first source/drain region and the second source/drain region, wherein the active region comprises a region of lower doping concentration disposed between the first well region and the second well region, wherein the region of lower doping concentration has a doping concentration lower than a doping concentration of each of the first well region and the second well region; forming a trench disposed between the second source/drain region and at least a portion of the active region; forming a first isolation layer on a bottom and sidewalls of the trench; forming electrically conductive material in the trench, wherein the electrically conductive material is disposed over the first isolation layer; forming a second isolation layer above the active region; and forming a gate region above the second isolation layer; wherein the electrically conductive material is coupled to the gate region, and wherein the first well region is spaced apart from the second well region by the active region.