Patent ID: 9332628
Filing Date: 2016-05-03
CPC Classification: H01L,H05K

Claim Text:
1. A microelectronic structure comprising: a first dielectric layer located over a substrate; a plurality of conductor layers located embedded and planarized within the first dielectric layer and including a plurality of apertures interposed between the plurality of conductor layers; a liner layer incompletely filling the plurality of apertures; a second dielectric layer located upon the liner layer and enclosing a plurality of voids interposed between the liner layer and the second dielectric layer, and separating the plurality of conductor layers; a plurality of barrier layers located upon bottom and sidewall portions of the plurality of conductor layers; a plurality of capping layers aligned upon top surfaces of the plurality of conductor layers; and a plurality of spacers adjoining a sidewall of the plurality of capping layers and having a thickness greater than a width of the barrier layer.