Patent ID: 9489296
Filing Date: 2016-11-08
CPC Classification: G06F

Claim Text:
1. A solid state drive controller, comprising: a processor configured to couple to a plurality of non-volatile memory devices, each configured to store a plurality of physical pages; and a first volatile memory configured to store a logical-to-physical address translation map configured to enable the controller to determine a physical location of logical pages stored within one or more of the plurality of physical pages; wherein the processor is further configured to: maintain, in the plurality of non-volatile memory devices, a plurality of journals defining physical-to-logical page correspondences and comprising a plurality of journal entries, each entry associating one or more physical pages to a logical page, at least one of the plurality of journals containing last-in-time updates to logical pages and stale entries that no longer point to valid logical pages, wherein each of the plurality of journals covers a predetermined physical region of the non-volatile memory, the predetermined physical region comprising a predetermined range of the plurality of physical pages, and each of the plurality of journals comprises an identification number based on address information of a physical page covered by the journal; create a journal entry directly into one of the plurality of journals each time a logical page in the logical-to-physical address translation map is updated; and perform garbage collection, wherein garbage collection comprises: