Patent ID: 9373589
Filing Date: 2016-06-21
CPC Classification: G02F,H01L

Claim Text:
1. A display substrate comprising a base substrate and a thin film transistor arranged on the base substrate, the thin film transistor comprising a gate, a gate insulating layer, an oxide semiconductor active layer as well as a source electrode and a drain electrode arranged on the base substrate sequentially, wherein the display substrate further comprises an ultraviolet blocking layer, the ultraviolet blocking layer comprising a first portion arranged between the base substrate and the oxide semiconductor active layer, and wherein the display substrate further comprises a gate line arranged on the base substrate and a data line located above the gate line and electrically connected with one of the source electrode and the drain electrode of the thin film transistor, wherein an oxide semiconductor active cushion is arranged between the gate line and the data line at the crossover of the gate line and the data line, and the ultraviolet blocking layer further comprises a second portion arranged between the base substrate and the oxide semiconductor active cushion.