Patent ID: 9293198
Filing Date: 2016-03-22
CPC Classification: G11C,H01L

Claim Text:
1. A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising: reading a memory cell to be programmed, before programming, to obtain an indication of cell-state; applying a programming signal between the source and drain of the memory cell to program the cell to a desired cell-state; and only when programming the cell from a crystalline state to the RESET state, as determined by indicating the crystalline state from the reading of the cell, applying a bias voltage to the gate of the cell to increase the cell resistance; and reprogramming the cell in the amorphous RESET state to the RESET state, as determined by indicating the amorphous RESET state from the reading of the cell, wherein the bias voltage is not applied to the gate of the cell at any time during the reprogramming, and wherein the reprogramming includes applying the programming signal between the source and drain of the memory cell to reprogram the cell to the RESET state while there is no voltage applied to the gate of the cell.