Patent ID: 9336162
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. In a system-on-chip (SoC) with a processor, a method for pre-fetching packet data prior to processing, the method comprising: accepting a plurality of packets; writing each packet into a memory; deriving a message for each packet, where each message includes a packet descriptor with a pointer to an address of the packet in the memory; adding each message to a tail of a first-in first-out (FIFO) queue; a pre-fetch module examining a first message if the first message reaches a first capacity threshold of the FIFO queue; if the first message reaches the first capacity threshold, the pre-fetch module reading a first packet associated with the first message, from the memory; loading the first packet into cache memory; a processor reading the first message from a head of the FIFO queue; and, in response to reading the first message, the processor reading the previously loaded first packet from cache memory.