Patent ID: 9406693
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method for fabricating a memory device, comprising: forming a stack comprising a first set of sacrificial layers above a second set of sacrificial layers, wherein the first set of sacrificial layers comprise a first sacrificial material and are arranged alternatingly with respective dielectric layers, the second set of sacrificial layers comprise a second sacrificial material and are arranged alternatingly with respective dielectric layers, and no two sacrificial layers comprising the first sacrificial material in the first set of sacrificial layers have a sacrificial layer comprising the second sacrificial material between them; forming a memory hole in the stack, the memory hole having a sidewall; depositing a charge-trapping material, a tunneling material and a channel material along the sidewall, wherein the charge-trapping material is deposited before the tunneling material, and the tunneling material is deposited before the channel material; etching a slit in the stack; providing an etchant in the slit which is more selective of the first sacrificial material than the second sacrificial material to etch away the first sacrificial material, creating a first set of voids and exposing a portion of the charge-trapping material in each void of the first set of voids; providing an etchant in the slit to etch away the portion of the charge-trapping material which is exposed in each void of the first set of voids; providing an etchant in the slit to etch away the second sacrificial material, creating a second set of voids; depositing a metal in the slit, the metal fills the first set of voids and the second set of voids, wherein portions of the charge-trapping material adjacent to the second set of voids remain in the memory device; and providing a blocking oxide layer between the charge-trapping material and the metal.