Patent ID: 9397651
Filing Date: 2016-07-19
CPC Classification: H01L,H03K

Claim Text:
1. A switch circuit, comprising: an NMOS transistor, including: a diode having a cathode terminal connected to the n-well and an anode terminal connected to a circuit node that receives one of an upper supply voltage and a boosted voltage higher than the upper supply voltage; a first p-well switch configured to selectively connect the p-well to the source in response to the enable phase of the first switching signal; and a second p-well switch configured to selectively connect the p-well to a lower supply voltage in response to an enable phase of a second switching signal, wherein the enable phases of the first and second switching signals are non-overlapping, and wherein the diode passively turns on during the enable phase of the second switching signal and passively turns off during the enable phase of the first switching signal.