Patent ID: 9299426
Filing Date: 2016-03-29
CPC Classification: G11C

Claim Text:
1. A nonvolatile semiconductor memory device, comprising: a cell array including a plurality of MATs (unit cell arrays) arranged in a matrix, each of the MATs including a plurality of bit lines, a plurality of word lines intersecting the bit lines, and a plurality of memory cells connected at intersections of the bit lines and the word lines between both lines, each of the memory cells including an electrically erasable programmable variable resistive element; a data I/O buffer configured to input/output various data from/to an external; a controller configured to manage input/output of data writing/erasing/reading data to/from the cell array based on command data supplied from the data I/O buffer; a pulse generating circuit configured to generate and output pulses under the control of the controller; a plurality of column control circuits, each of the column control circuits being connected to one of the MATs, and configured to select and control one of the bit lines of a corresponding one of the MATs based on address data supplied from the data I/O buffer and the pulses supplied from the pulse generating circuit under the control of the controller; and a plurality of row control circuits, each of the row control circuits being connected to one of the MATs, and configured to select and control one of the word lines of the corresponding MAT based on the address data supplied from the data I/O buffer and the pulses supplied from the pulse generating circuit under the control of the controller, each of the column control circuits and the row control circuits being configured to access the same number of the memory cells in the corresponding MAT simultaneously under the control of the controller, and a plurality of the memory cells accessed simultaneously comprising at least one group, the memory cells belonging to the group being physically separated apart more than one memory cell from each other.