Patent ID: 9390778
Filing Date: 2016-07-12
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cell rows coupled to a plurality of word-lines; a plurality of sub word-line drivers coupled to the plurality of word-lines; and a plurality of power selection switches coupled to the plurality of sub word-line drivers, wherein each power selection switch is configured to control a deactivation voltage level of a first word-line activated from the plurality of word-lines and an off-voltage level of a second word-line adjacent to the first word-line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage, wherein the off-voltage level of the second word-line after deactivation of the first word-line is controlled to have different voltage level from the off-voltage level of the second word-line during an activation interval in which the first word-line is activated, wherein the ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.