Patent ID: 9373632
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A memory device on a substrate, comprising: a multilevel stack of conductive layers, each of the layers being oriented parallel to the substrate; a plurality of pillars oriented orthogonally to the substrate, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the conductive layers; a plurality of string select lines oriented parallel to the substrate and above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective select gate of the pillar; and a plurality of parallel bit line conductors in a layer parallel to the substrate and above the string select lines, each of the bit line conductors superposing a respective distinct subset of the pillars, each of the pillars underlying one of the bit line conductors, wherein the pillars in the plurality of pillars are arranged on a regular grid having two perpendicular lateral dimensions, neither of the dimensions being parallel to or orthogonal to the bit line conductors.