Patent ID: 9240392
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A method of fabricating embedded die packages comprising: obtaining an array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket; Placing said array with framework on a transparent tape so that an underside of the array of chip sockets contacts said transparent tape; positioning a chip terminal side down in each chip socket so that undersides of said chips contact said transparent tape; Aligning said chips with said via posts by optical imaging through the tape; Applying a packing material over and around said chips in said array, and curing the packing material to embed the chips on five sides; Thinning and planarizing the packing material to expose upper ends of said vias on upper side of said array; Removing the transparent tape; Applying a feature layer of conductors on said underside of said array of chip sockets and said undersides of the chips, to couple at least one terminal of each die to at least one through via; Applying a feature layer of conductors on over side of said array of chip sockets such that at least one conductor extends from a through via at least partway over each chip, and dicing said array to create separate dies comprising at least one embedded chip having a contact pad coupled to a through via adjacent said chip.