Patent ID: 9412598
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a tunneling dielectric region on a substrate; forming a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region by depositing a nitride or silicon rich nitride layer, forming an oxide layer on the nitride or silicon rich nitride layer, etching back the oxide layer and a portion of the nitride or silicon rich nitride layer, and then oxidizing a portion of the remaining nitride or silicon rich nitride layer to form an oxynitride or silicon oxynitride layer on a final nitride or silicon rich nitride layer; nitridating a surface of the blocking dielectric region; forming a gate region on the nitridated blocking dielectric region; and oxidizing the gate region to form a sidewall dielectric layer, wherein edge encroachment of the gate region during oxidizing the gate region to form the sidewall dielectric layer is suppressed by the nitridated blocking dielectric region.