Patent ID: 9529594
Filing Date: 2016-12-27
CPC Classification: G06F

Claim Text:
1. A processor, comprising: an instruction miss buffer comprising a plurality of miss entries, each of which is configured to store thread state information corresponding to a respective instruction cache miss, wherein the processor is configured to execute instructions for a plurality of threads; wherein the instruction miss buffer is configured to store, at a given point in time, two or more sets of thread state information in two or more of the plurality of miss entries; wherein the plurality of miss entries includes a dynamic portion having one or more dynamically allocable entries, wherein each of the one or more dynamically allocable entries is allocable to a given one of a group of two or more of the plurality of threads; wherein the plurality of miss entries includes a dedicated portion having at least one entry reserved, respectively, for use by each active thread of the plurality of threads; and wherein the instruction miss buffer is configured to: