Patent ID: 9455031
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A Non-Volatile Resistive memory comprising: a plurality of voltage reference cells, wherein a first one of the plurality of voltage reference cells has a first voltage reference cell output and a first voltage reference cell link and a second one of the plurality of voltage reference cells has a second voltage reference cell output and a second voltage reference cell link; a first array of bitcells, wherein the first array of bitcells has a first voltage reference line coupled to the first voltage reference cell output through the first voltage reference cell link; a second array of bitcells, wherein the second array of bitcells has a second voltage reference line coupled to the second voltage reference cell output through the second voltage reference cell link; a voltage reference line coupling link coupled between the first voltage reference line and the second voltage reference line; and a plurality of sense amplifiers, wherein a first one of the plurality of sense amplifiers is coupled to the first voltage reference line and a second one of the plurality of sense amplifiers is coupled to the second voltage reference line.