Patent ID: 9461654
Filing Date: 2016-10-04
CPC Classification: H03L,H03M,H04L

Claim Text:
1. A receiver comprising: a first analog to digital converter (ADC) circuit to convert an analog input signal into first digital samples under control of a first sampling clock; a first clock generator circuit to adjust a phase of the first sampling clock based on one or more first phase control signals; a second ADC circuit to convert the analog input signal into second digital samples under control of a second sampling clock; a second clock generator circuit to adjust a phase of the second sampling clock based on one or more second phase control signals; a decision circuit to recover data based on the first digital samples and the second digital samples; and feedback circuitry to generate the one or more first phase control signals for the first clock generator circuit based on the recovered data and to generate the one or more second phase control signals for the second clock generator circuit based on the one or more first phase control signals.