Patent ID: 9401417
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate having at least a gate region and at least a source/drain region adjoining the gate region; forming at least an epitaxial layer on the semiconductor substrate within the source/drain region; forming a fluorine-containing layer on a surface of the epitaxial layer, whereby a top surface of the gate structure is not covered by the fluorine-containing layer during the step of forming the fluorine-containing layer; forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer; forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure; forming at least a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer; and forming at least a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole, wherein the fluorine-containing layer is disposed on a periphery of the metal silicide layer after the step of forming the metal silicide layer.