Patent ID: 9389944
Filing Date: 2016-07-12
CPC Classification: G01R,G06F

Claim Text:
1. A die comprising test circuitry for testing the die, interconnections between the die and an adjacent die when the die is stacked, or both the die and interconnections, the test circuitry comprising: a first input port configured to receive test stimuli and test control instructions; a first output port configured to send test responses, test stimuli and test control instructions, the first input port and the first output port being located at a first side of the die, wherein there is a data signal path within the die between the first input port and the first output port; a second input port configured to receive test responses, test stimuli, and test control instructions from another die, wherein there is a data signal path within the die between the second input port and the first output port; a second output port configured to send test stimuli and test control instructions to the another die, the second input port and the second output port being located at a second side of the die, wherein there is a data signal path within the die between the first input port and the second output port; a third input port configured to receive one or more test control signals; and test control circuitry, the test control circuitry accepting the one or more test control signals and producing a block/unblock signal derived from the one or more test control signals, the test control circuitry accepting data from either the first input port or the second input port depending on the block/unblock signal.