Patent ID: 9432013
Filing Date: 2016-08-30
CPC Classification: G06F,H01F,H01L,H03H,H03K

Claim Text:
1. An integrated circuit comprising: first and second inductor arrangements; and buffer circuitry adapted to receive and buffer four clock signals being the four phases of a four-phase clock signal, wherein: each said inductor arrangement comprises four inductors adjacently located in a group and arranged to define two rows and two columns; the integrated circuit is configured, for each said inductor arrangement, to cause two of the four inductors which are diagonally opposite from one another in that arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those four inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase; and the first and second inductor arrangements are connected to the buffer circuitry such that the electromagnetic fields of the first and second inductor arrangements are generated from respective said clock signals whereby the first and second phases of the first inductor arrangement are substantially in quadrature with the first and second phases, respectively, of the second inductor arrangement.