Patent ID: 9305824
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a hard mask film over a first main surface of a semiconductor wafer and making a first opening in the hard mask film in a first region over the first main surface; (b) forming sidewall insulating films on the side surfaces of the hard mask film of the first opening, respectively; (c) forming a first shallow trench in a semiconductor region surface of the first main surface in the first opening, with the hard mask film and the sidewall insulating films as masks; (d) after the step (c), oxidizing at least an exposed portion of an inner surface of the first shallow trench and the semiconductor region surface of the first main surface in the first opening; (e) after the step (d), filling the first shallow trench and the first opening with an insulating film; (f) after the step (e), removing the insulating film outside the first shallow trench so as to leave the insulating film outside the first shallow trench in the first opening and thereby forming a drain offset STI insulating film inside and outside the first shallow trench, and (g) after the step (f), forming a first gate electrode from an upper portion of a gate insulating film in a first active region contiguous to the drain offset STI insulating film to an upper portion of the drain offset insulating film.