Patent ID: 9530876
Filing Date: 2016-12-27
CPC Classification: B82Y,H01L

Claim Text:
1. A semiconductor structure comprising: an insulator layer including two pedestal portions that protrude above a top surface of said insulator between said two pedestal portions; a contiguous semiconductor material portion including a first semiconductor pad portion overlying one of said two pedestal portions, a second semiconductor pad portion overlying another of said two pedestal portions, and a semiconductor nanowire adjoined to sidewalls of said first and second semiconductor pad portions and suspended over said top surface; at least one stress-generating material portion entirely embedded in a trench within one of said first semiconductor pad portion and said second semiconductor pad portion, said at least one stress-generating material portion having a topmost surface that is coplanar with a topmost surface of said one of said first semiconductor pad portion and said second semiconductor pad portion, wherein said semiconductor nanowire is strained along a lengthwise direction by a stress generated by said at least one stress-generating material portion.