Patent ID: 9355903
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, the method comprising: forming a plurality of conductive structures including first conductive patterns over a substrate; forming a dielectric layer over the conductive structures; etching the dielectric layer to define openings between the conductive structures; forming sacrificial spacers over sidewalls of the openings; forming second conductive patterns recessed in the openings over the sacrificial spacers; removing the sacrificial spacers to define air gaps; forming third conductive patterns which are separated from the first conductive patterns by the air gaps, and cover sidewalls and top surfaces of the second conductive patterns; and forming fourth conductive patterns which cap the air gaps over the third conductive patterns, wherein the forming third conductive patterns comprises: forming a metal layer over an entire surface to gap-fill the air gaps; performing an annealing process to react the metal layer with the first conductive patterns, and form a silicide layer: and removing an unreacted metal layer.