Patent ID: 9350572
Filing Date: 2016-05-24
CPC Classification: H04L

Claim Text:
1. An apparatus, comprising: a first adder configured to generate a first superposed signal in response to a first feedback equalization signal and an input signal; a second adder configured to generate a second superposed signal in response to a second feedback equalization signal and the first superposed signal; an edge slicer configured to generate an edge signal by slicing the first superposed signal according to a first clock signal; a data slicer configured to generate a data signal by slicing the second superposed signal according to a second clock signal; an error slicer configured to generate an error signal by slicing the second superposed signal according to the second clock signal and a reference signal; a clock and data recovery (CDR) circuit configured to generate the first clock signal and the second clock signal in response to the data signal and the edge signal; an adaptive filter configured to generate the reference signal and a set of equalizer coefficients in response to the data signal and the error signal; and an equalizing unit configured to generate the first feedback equalization signal and the second feedback equalization signal in response to the data signal and the set of equalizer coefficients.