Patent ID: 9299438
Filing Date: 2016-03-29
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a first string which is coupled with a first bit line, the first string including first memory cells coupled between a first selection transistor and a second selection transistor in series; a second string which is coupled with a second bit line and is adjacent to the first string, the second string including second memory cells coupled between a third selection transistor and a fourth selection transistor in series, wherein gates of the first and third selection transistors are coupled in common and gates of the second and fourth selection transistors are coupled in common; and a controller which controls access to the memory cells, wherein the controller executes writing first data into the first memory cells in the first string and writing second data into the second memory cells in the second string simultaneously, and the controller reads data from the first and second strings after writing the first and second data.