Patent ID: 9305937
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method of fabricating a memory device, comprising: forming a stack including an alternating plurality of material layers and insulator layers over a substrate; forming a memory opening extending through the stack; forming a first blocking dielectric layer in the memory opening and over the stack; forming a second blocking dielectric layer on the first blocking dielectric layer; forming a sacrificial liner over the first blocking dielectric layer, wherein the sacrificial liner is formed on the second blocking dielectric layer; forming an opening through a horizontal portion of the sacrificial liner; etching a horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the sacrificial liner, whereby a semiconductor surface of the substrate is physically exposed at a bottom of the memory opening; removing the sacrificial liner without removing the first blocking dielectric layer after the semiconductor surface of the substrate is physically exposed; and forming a memory material layer and a tunneling dielectric layer within the memory opening.