Patent ID: 9449656
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A memory including a plurality of bit cells, each bit cell comprising: a bit line; a first storage cell comprising a first plurality of PMOS transistors; a second storage cell comprising a second plurality of PMOS transistors, wherein the first storage cell and the second storage cell are coupled to the bit line; a first pass transistor coupled to each of the first plurality of PMOS transistors of the first storage cell; a second pass transistor coupled to each of the second plurality of PMOS transistors of the second storage cell; a first header PMOS transistor coupled to each of the first plurality of PMOS transistors of the first storage cell and a second header PMOS transistor coupled to each of the second plurality of PMOS transistors of the second storage cell; a common supply voltage line coupled to the first storage cell and the second storage cell, wherein the first header PMOS transistor is interjacent the common supply voltage line and each of the first plurality of PMOS transistors of the first storage cell, and wherein the second header PMOS transistor is interjacent the common supply voltage line and each of the second plurality of PMOS transistors of the second storage cell; and a header control circuit coupled to provide a first header control signal to the first header PMOS transistor and a second header control signal to the second header PMOS transistor, wherein the header control circuit is configured to provide the first header control signal such that a ratio of a first pass current of the first pass transistor to a first pull-up current of the first plurality of PMOS transistors is between about 0.05 to about 0.1 during a write operation of the first storage cell, wherein the header control circuit is configured to provide the second header control signal such that a ratio of a second pass current of the second pass transistor to a second pull-up current of the second plurality of PMOS transistors is between about 0.05 to about 0.1 during a write operation of the second storage cell.