Patent ID: 9348777
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. A hardware apparatus for a system, comprising: an interface configured to connect the hardware apparatus to a system bus, the system bus being usable by the hardware apparatus to communicate with at least one of (i) a central control unit in the system, and (ii) another hardware apparatus in the system; and a direct memory access device configured (i) to directly access a main memory of the central control unit, (ii) to set an identifier in the main memory of the central control unit for data flow control when the direct memory access device has terminated direct access to a main memory of the system, and (iii) reset the identifier in the main memory in response to the central control unit executing an operation for at least one of (i) reading associated data in the main memory, and (ii) editing the associated data in the main memory.