Patent ID: 9450843
Filing Date: 2016-09-20
CPC Classification: H04L

Claim Text:
1. A switch, provided with M physical ports on its main panel, and each physical port of the M physical ports comprising N channels, thus the switch comprises M*N channels, where N≧2 and M≧2, wherein the main panel is provided with M port indicators one-to-one corresponding to the M physical ports, and the main panel is provided further with N channel indicators, the N channel indicators being respectively corresponding to the N channels of each physical port, and the M port indicators and the N channel indicators are used to indicate states of the M*N channels; wherein the switch further comprises a main chip and a control component, wherein the main chip is provided with M*N logical ports corresponding to each of the M*N channels, and the control component comprises a signal parsing module, an enable signal controlling module, and an indicator controlling module, wherein: the signal parsing module is configured to receive a port state indication signal from the main chip and parse the port state indication signal to obtain usage state information of each logical port; the enable signal controlling module is configured to generate N enable signals and control at most one enable signal to be valid at any time point; and the indicator controlling module is configured to control the states of the N channel indicators by using the N enable signals sent from the enable signal controlling module, and control the state of each port indicator according to the N enable signals and the usage state information of each logical port.