Patent ID: 9373389
Filing Date: 2016-06-21
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern, the device comprising: a plurality of read word lines, each of which is provided for an associated one of the rows of the memory cell array and connected in common to a plurality of memory cells that form the associated row; a plurality of read bit lines, each of which is provided for an associated one of the columns of the memory cell array and connected in common to a plurality of memory cells that form the associated column; and a plurality of read source lines, each of which is provided for an associated one of the columns of the memory cell array and connected in common to a plurality of memory cells that form the associated column, wherein each of the plurality of memory cells includes: first and second inverters which are cross-coupled to each other; a first transistor which is connected between a read bit line and a read source line that are associated with the memory cell and of which the gate is connected to the output terminal of the first inverter; and a second transistor which is connected in series to the first transistor and of which the gate is connected to a read word line that is associated with the memory cell.