Patent ID: 9484955
Filing Date: 2016-11-01
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A semiconductor memory apparatus comprising: a cyclic redundancy check (CRC) circuit block configured to receive a first data from a first pad and generate internal CRC information; a training determination block configured to compare the internal CRC information with external CRC information and generate a read training result signal, and generate a combination pulse in response to the read training result signal and a first read pipe latch control pulse; a write pipe latch block configured to receive and latch the first data, and output a latched first data; a first selection block configured to electrically couple an output node of the write pipe latch block with an input node of a read pipe latch block in response to a training control signal; the read pipe latch block configured to receive and latch a second data inputted through the input node thereof and output a latched second data to the first pad, in response to a pipe input signal and a pipe output signal; and a read pipe latch control block configured to generate the pipe input signal and the pipe output signal in response to a second read pipe latch control pulse and the combination pulse.