Patent ID: 9450086
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate; a first semiconductor layer of a first conductivity type, which is formed on a first main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is formed over the first semiconductor layer and which is different from the first conductivity type; a first trench portion which penetrates through the second semiconductor layer to thereby reach the first semiconductor layer; a second trench portion, in plan view, which is disposed spaced apart from the first trench portion, and which penetrates through the second semiconductor layer to thereby reach the first semiconductor layer; a first gate insulating film formed on an inner wall of the first trench portion; a second gate insulating film formed on an inner wall of the second trench portion; a first gate electrode formed so as to be embedded in the first trench portion over the first gate insulating film; a second gate electrode formed so as to be embedded in the second trench portion over the second gate insulating film; a first semiconductor region of the first conductivity type, which is in contact with the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion and in contact with the first gate insulating film; a second semiconductor region of the first conductivity type, which is in contact with the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion and in contact with the second gate insulating film; a third semiconductor region of the second conductivity type, which is formed in the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion; and a fourth semiconductor region of the second conductivity type, the whole fourth semiconductor region is formed separated from the third semiconductor region in the second semiconductor layer and the whole fourth semiconductor region is formed in a portion of the second semiconductor layer positioned between the third semiconductor region and the second trench portion, wherein a first transistor is formed by the first semiconductor layer, the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion, the first gate insulating film, the first gate electrode, and the first semiconductor region, wherein a second transistor is formed by the first semiconductor layer, the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion, the second gate insulating film, the second gate electrode, and the second semiconductor region, and wherein both an impurity concentration of the second conductivity type in the third semiconductor region and an impurity concentration of the second conductivity type in the fourth semiconductor region are greater than an impurity concentration of the second conductivity type in the second semiconductor layer.