Patent ID: 9525041
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A semiconductor process for forming gates with different pitches and different dimensions, comprising: forming a gate layer on a substrate having a first area and a second area; forming a first mandrel on the gate layer of the first area and a second mandrel on the gate layer of the second area; forming a first spacer material in the first area to conformally cover the first mandrel but exposing the second area, wherein the step of forming the first spacer material in the first area to conformally cover the first mandrel but exposing the second area comprises: covering a patterned hard mask in the second area while exposing the first area; and covering the first spacer material in the first area; forming a second spacer material in the first area and the second area to conformally cover the first spacer material and the second mandrel; etching the first spacer material and the second spacer material to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously; removing the first mandrel and the second mandrel; and transferring layouts of the first spacer and the second spacer to the gate layer, thereby a first gate and a second gate being formed.