Patent ID: 9304812
Filing Date: 2016-04-05
CPC Classification: G06F,G06T,Y02D

Claim Text:
1. A multithreaded single instruction multiple data (SIMD) microprocessor, comprising: a scheduler circuit operable for scheduling execution of phases of program instructions, from programs, wherein the phases of program instructions from each program have a predetermined relative order of execution, and a respective first phase of each program initially is to execute on a respective plurality of data instances, and each subsequent phase of each program is to process a respective subset of the respective plurality of data instances, the subset determined based on results of feedback from executing a respective preceding phase of that program, the feedback indicating which data instances are to be processed by which subsequent phase of the program, and the scheduler circuit is configured to: create, during scheduling of each subsequent phase of the same program, one or more threads to process data instances from the respective subset of data instances to be processed by that phase, a number of threads created for each subsequent phase being determined according to a SIMD ratio for that subsequent phase and the results of executing the respective preceding phase of the same program, receive an indication of execution completion of each thread, and maintain a count of threads remaining to be completed for the phase of a program to which a respective thread of the count of threads belongs, and responsive to the count of threads indicating that all threads for that phase are completed, allow a subsequent phase of that program to be scheduled; and a plurality of resources for executing the one or more threads created for scheduled phases, the plurality of resources comprising an execution pipeline configurable to process a plurality of data instances by a single thread according to the SIMD ratio for the phase of the program to which that single thread belongs and to produce the results.