Patent ID: 9349860
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device, the method comprising: forming a first source/drain feature and a second source/drain feature on a substrate; forming a first dielectric layer on the first source/drain feature and the second source/drain feature; patterning the first dielectric layer to form a first opening and a second opening therein, the first opening exposing the first source/drain feature and the second opening exposing the second source/drain feature; epitaxially growing a first nanowire in the first opening and a second nanowire in the second opening, the first nanowire extending vertically from an upper surface of the first source/drain feature and the second nanowire extending vertically from an upper surface of the second source/drain feature; forming a second dielectric layer on the first dielectric layer and surrounding the first nanowire and the second nanowire; patterning the second dielectric layer to form a third opening therein, the third opening exposing at least a portion of the first nanowire and at least a portion of the second nanowire; and forming a third nanowire in the third opening, the third nanowire extending form an upper end of the first nanowire to an upper end of the second nanowire.