Patent ID: 9384055
Filing Date: 2016-07-05
CPC Classification: G06F

Claim Text:
1. A computer implemented method comprising: taking one or more measurements of processor utilization, each measurement indicative of utilization of a plurality of a processing units collectively; calculating, by a computer, a utilization ceiling, wherein the utilization ceiling is indicative of a likelihood of a failure of a load in a next interval based on an available processing unit (PU) capacity, wherein the failure of the load is caused by the load exceeding the available PU capacity; adding, automatically, one or more processing units responsive to determining that the utilization ceiling is greater than the available PU capacity; and removing, automatically, one or more processing units responsive to determining that the utilization ceiling is at least one PU less than the available PU capacity, wherein the one or more processing units are physical processors, wherein the utilization ceiling is a sum of a mean processor utilization and a scaled standard deviation of processor utilization, wherein the scaled standard deviation is obtained by scaling a standard deviation of processor utilization by a scaling factor based on a received acceptable failure rate.