Patent ID: 9478259
Filing Date: 2016-10-25
CPC Classification: G11C,H01L

Claim Text:
1. An integrated circuit comprising: a 3D NAND array of memory transistors; a plurality of bit lines electrically coupled to the 3D NAND array; a plurality of transistor pairs with a stack of semiconductor layers, different layers in the stack of semiconductor layers including source/drain terminals of different transistor pairs of the plurality of transistor pairs, each of the plurality of transistor pairs including first and second transistors with first, second, and third source/drain terminals, wherein: the first transistor includes the first and the third source/drain terminals, and the second transistor includes the second and the third source/drain terminals the first source/drain terminal is electrically coupled to an erase voltage line, the second source/drain terminal is electrically coupled to a corresponding one of a plurality of program/read voltage lines, and the third source/drain terminal is electrically coupled to a corresponding one of the plurality of bit lines; a first gate controls all of the first transistors of the plurality of transistor pairs; and a second gate controls all of the second transistors of the plurality of transistor pairs.