Patent ID: 9349952
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising: depositing a poly-silicon layer on a substrate; depositing a carbon layer above the poly-silicon layer; patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer; performing a modified photolithography process on the photo resist layer after etching back the first spacer layer creating sidewalls; etching the sidewalls by using the sidewalls as a mask to create a photo-resist pattern; depositing a second spacer layer on the carbon layer; etching back the second spacer layer; exhuming the carbon layer leaving pairs of carbon sidewalls; performing an etching process to form trenches; stripping all layers except the poly-silicon layer and the substrate, forming stacks topped with poly-silicon; implanting a bottom electrode in each of the trenches; and implanting a top electrode in each of the stacks.