Patent ID: 9313878
Filing Date: 2016-04-12
CPC Classification: H05K

Claim Text:
1. A method for mitigating voltage stresses on a printed circuit board (PCB), comprising: forming a multi-terminal condenser structure on a multi-layered PCB and the multi-terminal condenser structure is configured to by-pass electric fields of an alternating current (AC) voltage applied to the multi-terminal condenser structure, which powers circuitries external to the multi-terminal condenser structure, wherein the multi-terminal condenser structure itself is free from having PCB components mounted thereon, wherein: the multi-terminal condenser structure is formed by overlapping a plurality of conductive traces disposed between board layers of the multi-layered PCB, a corresponding dielectric layer is disposed between the plurality of overlapping conductive traces of the board layers, wherein the plurality of overlapping conductive traces comprise: mitigating voltage stresses on the PCB utilizing the multi-terminal condenser structure to by-pass the AC currents from the applied AC voltage to the ground point.