Patent ID: 9373720
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method of forming a transistor comprising a source/drain region, the method comprising: forming a plurality of spaced apart fins comprised of a semiconductor material; after forming said plurality of spaced apart fins, forming a dielectric material layer between each of said plurality of spaced apart fins, said dielectric material layer covering a lower sidewall surface portion and exposing an upper sidewall surface portion of each of said plurality of spaced apart fins; forming a common gate structure above said dielectric material layer and across said plurality of fins; after forming said common gate structure, forming a continuous merged source region material and a continuous merged drain region material on said plurality of fins and above said dielectric material layer on opposite sides of said common gate structure, wherein said continuous merged source region material and said continuous merged drain region material are each laterally spaced apart from said common gate structure and extend between and physically contact said plurality of fins, each of said continuous merged source region and drain region materials comprising a first portion having a first sidewall surface that faces toward said common gate structure and a second portion having a second sidewall surface that is opposite of said first sidewall surface and faces away from said common gate structure; performing at least one etching process to remove said first portions of said respective continuous merged source region and drain region materials including said respective first sidewall surfaces thereof while leaving said second portions of said respective continuous merged source region and drain region materials including said respective second sidewall surfaces thereof in place between and in direct physical contact with said plurality of fins so as to thereby define first and second spaces, respectively, on opposite sides of said common gate structure, said first and second spaces exposing respective first and second surface portions of said dielectric material layer formed between each of said plurality of spaced apart fins; and forming a material in said first and second spaces.