Patent ID: 9256545
Filing Date: 2016-02-09
CPC Classification: G06F,Y02D

Claim Text:
1. A method, comprising: defining a first mapping, which translates between specific logical addresses and respective specific physical storage locations in a memory with a first mapping unit size, for accessing the memory by a first processing unit serving as a host processor having an internal data caching space; defining a second mapping, which translates between the specific logical addresses and the respective specific physical storage locations with a second mapping unit size that is different from the first mapping unit size, for accessing the memory by a second processing unit of a network interface card (NIC) serving the host processor, wherein the NIC has a smaller internal storage space than the host processor; and exchanging data between the first and second processing units via the memory, while accessing the memory by the first processing unit using the first mapping and by the second processing unit using the second mapping, wherein defining the first mapping comprises identifying a constraint of the second processing unit in accessing the memory, and defining the first mapping unit size so as to enable the second processing unit to follow the constraint.