Patent ID: 9299820
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor layer; a gate trench formed in the semiconductor layer; a gate electrode filled via a gate insulating film in the gate trench; a dummy trench formed spaced at a predetermined interval lateral to the gate trench; an n a p a buried insulating film filled in the dummy trench, the buried insulating portion having an upper surface at a bottom side of the dummy trench with respect to the front surface of the semiconductor layer such that a part of the p-type base region is exposed at a side surface of the dummy trench as a contact region; a contact electrode filled in a region over the buried insulating film of the dummy trench, connected to the contact region on the side surface of the dummy trench; a first buried electrode filled via an insulating film in a region under the buried insulating film of the dummy trench, the first buried electrode being electrically connected with the n a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches, the trench unit being formed in plural numbers in a transverse direction along the front surface of the semiconductor layer; a plurality of emitter trenches formed between the trench units adjacent to each other; a second buried electrode filled via an insulating film in the emitter trench, electrically connected with the n a p-type floating region formed between the dummy trench of the trench unit and the dummy trench of the trench unit next thereto.