Patent ID: 9385233
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, comprising: forming an N+ doped silicon layer on a semiconductor substrate; forming an undoped SiGe layer on the N+ doped silicon layer; forming a silicon channel layer on the undoped SiGe layer; forming a plurality of fins by performing a fin etch on the semiconductor structure; depositing an oxide layer on the semiconductor structure and in between each of the plurality of fins; forming a thermally formed oxide region by performing an anneal on the semiconductor structure; forming a gate on the semiconductor substrate; performing an anisotropic etch into the semiconductor structure adjacent to the gate, and extending into the N+ doped silicon layer; and forming P+ doped SiGe regions adjacent to the gate and thermally formed oxide region, and extending into the N+ doped silicon layer.