Patent ID: 9419594
Filing Date: 2016-08-16
CPC Classification: H03K,H04L

Claim Text:
1. A clock data recovery system, comprising: a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving the summed input signal associated with clock recovery and generating at least one error sample of the summed input signal; an equalization and adaptation logic for determining a phase associated with the error sample; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked error comparators, wherein the feedback signal is generated by the equalization and adaptation logic.