Patent ID: 9397165
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a crystalline silicon substrate; a germanium region disposed within the silicon substrate; a silicon oxide gate dielectric layer disposed directly on the germanium region; a metal gate electrode disposed above the silicon oxide gate dielectric layer; a pair of dielectric sidewall spacers adjacent the gate electrode; a high-k gate dielectric layer disposed on the silicon oxide gate dielectric layer directly between the silicon oxide gate dielectric layer and the metal gate electrode, and disposed along sidewalls of the pair of dielectric sidewall spacers directly between the pair of dielectric sidewall spacers and the metal gate electrode; a pair of source/drain regions disposed in the germanium region on either side of the gate electrode; and a channel region disposed in the germanium region between the pair of source/drain regions.