Patent ID: 9244631
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. A method of operating a block-erasable nonvolatile memory array comprising: receiving data to be programmed in the block-erasable nonvolatile memory array from a host; determining, prior to programming the data in the block-erasable nonvolatile memory array, whether the data is burst data; if the data is burst data, programming the burst data as only lower page data along three or more word lines of at least one block configured as a Multi Level Cell (MLC) block; subsequently, only after the burst data from the host is programmed, copying additional data from outside the MLC block to fill upper pages of the MLC block while maintaining the burst data as lower page data in the MLC block; and if the data is not burst data, programming the data in Multi Level Cell (MLC) blocks as both lower page data and upper page data along word lines of the MLC blocks in accordance with a programming sequence in which lower page data is programmed one word line ahead of upper page data.