Patent ID: 9287179
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor layer disposed over a substrate, the semiconductor layer having a first fin-like structure and a second fin-like structure; a gate dielectric layer wrapped around at least a portion of both the first fin-like structure and the second fin-like structure on the semiconductor layer; a gate layer disposed over and in contact with the gate dielectric layer over the first fin-like structure in a substantially conformal manner, wherein the gate layer has a substantially constant thickness, wherein the gate layer does not extend over the second fin-like structure; and a metal gate layer disposed over the gate layer and the second fin-like structure, the metal gate layer being in direct contact with the gate dielectric layer over the second fin-like structure an interlayer dielectric layer feature disposed adjacent the metal gate layer, the interlayer dielectric layer formed over the first fin-like structure and the second fin-like structure, wherein the interlayer dielectric feature comprises: