Patent ID: 9335759
Filing Date: 2016-05-10
CPC Classification: G05B,H01L,Y02P

Claim Text:
1. A method of performing a laser anneal on a substrate including a plurality of semiconductor chips, said method comprising: providing data for in-substrate chip coordinates and measured values of an anneal-activated parameter for a plurality of semiconductor chips on a semiconductor substrate to a computing means, said computing means including one or more processors in communication with memory; generating a plurality of anneal plans for a laser anneal for said semiconductor substrate, each of said anneal plans including a simulated path for a laser beam to impinge on a corresponding set of target semiconductor chips and collaterally irradiated additional semiconductor chips during transit of said laser beam between target semiconductor chips, wherein each set of target semiconductor chips is a subset selected from a set of all semiconductor chips in said semiconductor substrate having measured values for said anneal-activated parameter within a predetermined subset of out of specification ranges; simulating, employing said computing means, an estimated net yield enhancement for each of said plurality of anneal plans, said estimated net yield enhancement being a difference between a total number of estimated changes from an out of specification value to an in-specification value for said anneal-activated parameter less a total number of estimated changes from an in-specification value to an out of specification value for said anneal-activated parameter according to a corresponding anneal plan among said plurality of anneal plans; determining an anneal plan that provides a greatest value for said estimated net yield enhancement; and controlling a laser anneal apparatus to perform said laser anneal on said substrate based on the anneal plan determined to provide the greatest value for said estimated net yield enhancement.