Patent ID: 9379163
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A resistance variable memory, comprising: a plurality of first wires arranged at intervals in a first direction on a substrate and arranged at intervals in a second direction; a plurality of second wires arranged at intervals in a third direction crossing in the first and second directions and arranged in the second direction alternately with the first wires; a memory cell which is arranged at each crossing point with the first wires and third wires, and includes a first variable resistance element; access controllers which include a second variable resistance element connected in series to the memory cell via the first wire and change a resistance of the second variable resistance element in accordance with a voltage applied to the memory cell connected in series; and a first contact plug and a second contact plug which alternatively drive the plurality of first wires aligned in the second direction via the corresponding access controller.