Patent ID: 9299425
Filing Date: 2016-03-29
CPC Classification: G06F,G11C

Claim Text:
1. A hybrid non-volatile memory cell system, the system including a plurality of hybrid non-volatile memory cells, each cell comprising: one or more transistors, wherein the one or more transistors are Complementary Metal Oxide Semiconductor (CMOS); a memristor for storing a data based on a resistance value; a word line for accessing the hybrid non-volatile memory cell; and a set of at-least two bit lines for transferring the data from the hybrid non-volatile memory cell; wherein the memristor is connected to the at-least one or more transistors, and wherein gate terminals of the at-least one or more transistors are coupled together, wherein the at-least one or more transistors comprises a first transistor and a second transistor, wherein a first terminal of the memristor is connected to a second terminal of the first transistor and a second terminal of the memristor is connected to a first terminal of the second transistor, wherein the set of at-least two bit lines includes a first bit line and a second bit line, wherein a first terminal of the first transistor is connected to the first bit line, and wherein a second terminal of the second transistor is connected to the second bit line, and wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled, wherein the coupled gate terminals of the first transistor and the second transistor are used as a word line, wherein the word line provides an access to the hybrid non-volatile memory cell.