Patent ID: 9287251
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: forming a first opening in a first insulating interlayer on a first substrate; forming a first diffusion prevention insulation layer on an inner wall of the first opening and on the first insulating interlayer; anisotropically etching the first diffusion prevention insulation layer to form a first diffusion prevention insulation pattern on the inner wall of the first opening; forming a first conductive pattern structure in the first opening provided with the first diffusion prevention insulation pattern therein, the first conductive pattern structure having a planarized top surface; forming a second opening in a second insulating interlayer on a second substrate; forming a second diffusion prevention insulation layer on an inner wall of the second opening and on the second insulating interlayer; anisotropically etching the second diffusion prevention insulation layer to form a second diffusion prevention insulation pattern on the inner wall of the second opening; forming a second conductive pattern structure in the second opening provided with the second diffusion prevention insulation pattern therein; performing a plasma treatment process on at least one of the first and second substrates provided with the first and second conductive pattern structures thereon, respectively; and contacting the first and second conductive pattern structures to each other to bond the first and second substrates.