Patent ID: 9418714
Filing Date: 2016-08-16
CPC Classification: G11C

Claim Text:
1. A sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, the sense amplifier comprising: a cross-coupled inverter stage having opposing first and second transistors, the cross-coupled inverter stage configured to sense and amplify the voltage differential when applied between a gate of the first transistor and a gate of the second transistor, and to store the logic state based on the amplified voltage differential; and a compensation stage configured to poise source voltages of the first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors, wherein the compensation stage includes first and second capacitors having first plates coupled, respectively, to source terminals of the first and second transistors, the first and second capacitors coupled to a common voltage node at second plates that are opposite the first plates, and wherein the compensation stage is further configured to store the offset voltage level of the first transistor on the first capacitor and the offset voltage level of the second transistor on the second capacitor, the common voltage node driven to a voltage higher than ground voltage in response to assertion of a first control line when the offset voltage level of the first transistor is stored on the first capacitor and the offset voltage level of the second transistor is stored on the second capacitor, wherein assertion of the first control line also triggers a predetermined delay during which the source voltages of the first and second transistors remain at their respective offset voltage levels; wherein upon expiration of the predetermined delay, a second control line is asserted to initiate sensing and amplification of the voltage differential by the sense amplifier in a read operation.