Patent ID: 9401431
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A method of forming thin film electronic circuits comprising the steps of: providing a substrate and designing the substrate with sufficient area to have fabricated thereon a selected one of a light emitting diode display, an image sensor array, a biosensor array, a pressure sensing array or a touch sensing array, the substrate having a front surface, and determining alignment and deformation tolerances of the substrate dictated by tools and process steps used during fabrication; incorporating at least one double self-aligned metal oxide TFT into the selected one of the active matrix liquid crystal display, the light emitting diode display, the image sensor array, the biosensor array, the pressure sensing array or the touch-sensing array, and fabricating the at least one double self-aligned metal oxide TFT on the substrate comprising the steps of: depositing opaque gate metal on the front surface of the substrate so as to define an opaque metal gate and a gate area for the TFT, depositing a gate dielectric layer overlying the substrate and the opaque metal gate and gate area, and depositing a metal oxide active layer overlying the gate dielectric layer; forming first self-aligning passivation material in a passivation area overlying the opaque metal gate and using the passivation material defining a channel area in the metal oxide active layer, the first self-aligning passivation material including one of an inorganic or organic dielectric material comprising oxygen; further defining an overlap area between the gate area and the first self-aligned passivation material wherein the overlap area is a portion of the gate area extending beyond horizontal limits of the passivation area on each side of the passivation area a distance equal to the alignment and deformation tolerances of the substrate, the gate area including the horizontal width of the channel area and overlap area distance on each side of the passivation area; and defining second self-aligning source/drain areas at a surface of the metal oxide active layer and positioning second self-aligned source/drain conductors therein, the second self-aligned source/drain conductors defining an overlap between each of the source/drain conductors and the first self-aligned passivation material with the width of the passivation area being larger than a distance between the overlap of the source/drain conductors.