Patent ID: 9406750
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate; an epitaxial layer in contact with a top surface of the substrate; a drain layer in the substrate; a body region within a top portion of the epitaxial layer; a source region within a top portion of the body region; a vertical gate structure substantially along at least one outer edge of the body region; two trenches on opposite sides of the body region in the top portion of the epitaxial layer, the trenches filled with a dielectric material, wherein corners of at least one of the two trenches are rounded to lower a contribution of the body region to an output capacitance of the semiconductor device with a reduced effect on a current flow through the body region; a conductive shield layer that substantially covers a top surface of the epitaxial layer and at least one of the two trenches; an oxide layer in contact the conductive shield layer; a dielectric layer in contact with the oxide layer; one or more interlayer dielectric layers in contact with the dielectric layer; and a contact layer, wherein a first portion of the contact layer is in contact with the vertical gate structure and a second onion of the contact layer is in contact with the source region and the shield layer.