Patent ID: 9240351
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A replacement-gate field effect transistor device with improved carrier mobility, comprising: a semiconductor substrate with NMOS and PMOS regions, wherein the NMOS region and the PMOS region are isolated from each other; a source region and a drain region belonging to the NMOS region and a source region and a drain region belonging to the PMOS region formed in the semiconductor substrate; an interlayer dielectric layer on a semiconductor layer, and a first truncation and a second truncation belonging respectively to the NMOS region and the PMOS region and being formed in the interlayer dielectric layer; a first gate stack formed within the first truncation and a second gate stack formed in the second truncation, wherein the first gate stack comprises: a first gate dielectric layer; and a first metal gate layer and a first stress layer with compressive stress on the first gate dielectric layer, wherein the first stress layer fills a space within the first metal gate layer; and the second gate stack comprises: a second gate dielectric layer; and a second metal gate layer and a second stress layer with tensile stress on the second gate dielectric layer, wherein the second stress layer fills a space within the second metal gate layer; a third stress structure with tensile stress on a sidewall of the first gate stack; and a fourth stress structure with compressive stress on a sidewall of the second gate stack, wherein the third stress structure is in direct contact with the first gate dielectric layer which is in direct contact with the first metal gate layer, and a portion of an upper surface of the third stress structure directly above the first gate stack is coplanar with another portion of the upper surface of the third stress structure directly above the source region and the drain region belonging to the NMOS region, wherein the fourth stress structure is in direct contact with the second gate dielectric layer which is in direct contact with the second metal gate layer, and a portion of an upper surface of the fourth stress structure directly above the second gate stack is coplanar with another portion of the upper surface of the fourth stress structure directly above the source region and the drain region belonging to the PMOS region, wherein the third stress structure further comprises portions covering a top of the interlayer dielectric layer, and the fourth stress structure further comprises portions covering a top of the interlayer dielectric layer.