Patent ID: 9385123
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming an isolation layer between a plurality of caps on a plurality of fins, wherein an upper surface of the isolation layer is substantially flush with an upper surface of the plurality of caps; forming a patterning layer on the isolation layer and on the plurality of caps; removing a portion of the patterning layer to form an opening above one of the plurality of fins to expose at least a portion of one of the plurality of caps; removing the one of the plurality of caps selective to the patterning layer, the isolation layer, and the one of the plurality of fins to expose the one of the plurality of fins; removing one of the plurality of fins from a fin field effect transistor (FINFET) device using a selective etching process to form a fin trench in the isolation layer, the fin trench extending from an upper surface of the isolation layer to an upper surface of a semiconductor substrate; forming an isolation trench in the semiconductor substrate directly below the fin trench, the isolation trench having a width that is approximately equal to a width of the one of the plurality of fins; and filling the isolation trench and the fin trench with an insulating material to form an isolation region, the isolation region having an upper surface that is substantially flush with the upper surface of the isolation layer.