Patent ID: 9280671
Filing Date: 2016-03-08
CPC Classification: G06F,H04L

Claim Text:
1. A semiconductor device comprising: a central processing unit (CPU) having a first operation mode and a second operation mode; an electrically rewritable first nonvolatile memory provided with a first region and a second region, the first region being forbidden to access from the CPU in the second operation mode; an electrically non-rewritable second nonvolatile memory provided with a third region and a fourth region, the third region being operable to store an encryption code as at least one of an encrypted instruction and encrypted data; and a decrypter, wherein the first nonvolatile memory is provided with a plurality of distributed address areas in the first region, for holding a plurality of split keys composing an encryption key for decrypting the encryption code, wherein the decrypter holds the encryption key, and in the second operation mode, the decrypter is operable to decrypt the encryption code read from the third region of the second nonvolatile memory with the use of the encryption key, and operable to supply the decrypted encryption code to the CPU, and wherein the second nonvolatile memory holds an encryption key reading program in the fourth region, which is executed by the CPU in the first operation mode to restore the encryption key and to supply it to the decrypter, by reading and reconfigurating the split keys held in the first nonvolatile memory in a distributed manner.