Patent ID: 9368454
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate comprising electrical circuitry, an inter-metal dielectric layer over the electrical circuitry, and a contact pad formed on and in contact with the inter-metal dielectric layer; a passivation layer overlying the inter-metal dielectric layer; a first protective layer overlying the passivation layer; a post-passivation interconnect (PPI) structure overlying the first protective layer and comprising at least one signal line and a first ground line spaced apart from the signal line; a first shielding layer interposed between the inter-metal dielectric layer and the passivation layer, wherein the first shielding layer extends on and in contact with the inter-metal dielectric layer such that the first shielding layer is between the signal line and the electrical circuitry, and the first shielding layer is substantially equi-potentially connected to the first ground line of the PPI structure; a second protective layer covering the PPI structure and in contact with the first protective layer, wherein both the first and the second protective layers are made of polymeric material; and a second shielding layer formed over and in contact with the second protective layer, wherein the second shielding layer overlaps the first shielding layer and is physically connected to the first ground line, and wherein the signal line and the first ground line are interposed between first shielding layer and the second shielding layer.