Patent ID: 9378142
Filing Date: 2016-06-28
CPC Classification: G06F,G11C

Claim Text:
1. A multi-level memory system comprising: a processor having a plurality of cores to execute instructions and process data and one or more processor caches to cache instructions and data according to a first cache management policy; a first-level memory having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and a second-level memory having a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, non-volatility such that the second level memory is to maintain its content when power is removed, random access and memory subsystem addressability such that instructions or data stored therein may be accessed at a granularity equivalent to a memory subsystem of a computer system; a memory controller to receive memory requests and to distribute the memory requests between the first and the second level memories, the memory controller to designate a plurality of different modes of operation for the first level memory including a first mode in which the first-level memory operates as a memory cache for the second-level memory and a second mode in which the first-level memory is allocated a first address range of a system address space with the second-level memory being allocated a second address range of the system address space, wherein in the first mode, the first-level memory is organized into different cache regions that provide caching for respective system address ranges, where, the respective system address ranges are aligned with the respective system address ranges of specific physical memory devices of the second-level memory.