Patent ID: 9322877
Filing Date: 2016-04-26
CPC Classification: G01R,G06F

Claim Text:
1. An integrated circuit, comprising: (a) test access port circuitry having a TDI input lead, a TMS input lead, a TCK input lead, a TDO output lead, a trace data output, a trace data input, and a trace control output; (b) trace domain circuitry having a trace domain data input coupled to the trace data output, a trace domain data output coupled to the trace data input, and a trace domain control input coupled to the trace control output; and (c) controller circuitry having a TMS/TDI input lead, a clock input lead, and a TDO output lead, the controller circuitry being connected to the test access port circuitry by a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead of the test access port circuitry and to the TDO output lead of the controller circuitry, the controller circuitry including: