Patent ID: 9513871
Filing Date: 2016-12-06
CPC Classification: G06F

Claim Text:
1. A method performed by a processor comprising: receiving, at a decode unit of the processor, and decoding with the decode unit, a floating point round-off amount determination instruction of an instruction set of the processor, the floating point round-off amount determination instruction indicating a source of one or more floating point data elements, indicating a number of fraction bits after a radix point, and indicating a destination storage location which is a register of the processor; and storing, with an execution unit of the processor, a result including one or more result floating point data elements in the destination storage location which is the register of the processor in response to the floating point round-off amount determination instruction, each of the one or more result floating point data elements including a difference between a corresponding floating point data element of the source in a corresponding position and a rounded version of the corresponding floating point data element of the source that has been rounded to the indicated number of the fraction bits.