Patent ID: 9281325
Filing Date: 2016-03-08
CPC Classification: G02F,H01L

Claim Text:
1. A method of manufacturing an array substrate, wherein, a common electrode and a pixel electrode are formed at the same time through a single process; comprising: sequentially forming a gate metal layer and a gate insulating layer on a base substrate, the gate metal layer comprising patterns of a gate electrode and a gate line; forming a pattern of an active layer on the substrate formed with the gate insulating layer; forming patterns of a data line, a source electrode and a drain electrode on the substrate formed with the active layer, and forming a pattern of a conductive layer having at least one slit in a pixel region; forming a pattern of a passivation layer on the substrate formed with the data line, the source electrode, the drain electrode and the conductive layer, the passivation layer having a passivation layer slit in a one-to-one correspondence with the slit in the conductive layer; forming a transparent conductive layer on the substrate formed with the passivation layer, the transparent conductive layer comprising two layers, one of which is formed over the passivation layer to form a common electrode, and the other of which is located in the slit region, in the same layer as and electrically connected to the conductive layer to form a pixel electrode.