Patent ID: 9348764
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. A system on chip (SoC) comprising: one or more processors configured to output requests corresponding to a plurality of working sets, respectively, each of the plurality of working sets including virtual addresses from among a plurality of virtual addresses such that no virtual address, from among the plurality of virtual addresses, is included in more than one working set, from among the plurality of working sets; a memory management unit (MMU) module including a plurality of MMUs, each of the plurality of MMUs being allocated to at least one working set, from among the plurality of working sets, such that there is no working set, from among the plurality of working sets, to which more than one MMU, from among the plurality of MMUs, is allocated, each of the plurality of MMUs being configured to translate, into physical addresses, only virtual addresses included in the working sets to which the MMUs are allocated, based on at least one of the requests; and a first bus interconnect configured to connect the MMU module with a memory device and to transmit the requests, on which address translation has been performed by one or more MMUs from among the plurality of MMUs, to the memory device.