Patent ID: 9524933
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor structure, comprising: providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer using a first patterned mask layer; forming first conductive vias by filling the plurality of first through holes using a first metal material and forming first conductive lines over the first conductive vias also using the first metal material; forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer using a second patterned mask layer; and forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and forming second conductive lines over the second conductive vias also using the second metal material, wherein: the anti-electromigration ability of the second metal material is greater than the anti-electromigration ability of the first metal material; the first conductive vias and the first conductive lines are configured as signal lines of the semiconductor structure; and the second conductive vias and the second conductive lines are configured as power lines of the semiconductor structure.