Patent ID: 9362377
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a trench in an interlayer dielectric (ILD) on a substrate; forming a high-k dielectric layer and a work function (WF) layer sequentially on sidewall and bottom surfaces of the trench; forming a cobalt (Co) layer on the WF layer on the sidewall and bottom surfaces of the trench; reflowing a portion of the Co layer from the WF layer on the sidewall surfaces of the trench to the WF layer on the bottom surface of the trench; removing a remainder of the Co layer from the WF layer on the sidewall surfaces of the trench, above an upper surface of the reflowed Co layer; recessing the WF layer to the upper surface of the reflowed Co layer, forming a cavity above the reflowed Co layer; and filling the cavity with metal to form a gate electrode.