Patent ID: 9330733
Filing Date: 2016-05-03
CPC Classification: G11C

Claim Text:
1. A method for memory access in a programmable logic device, the method comprising: receiving a logical memory block configuration layout; identifying, based on the logical memory block configuration layout, at least two potential mappings of a plurality of embedded memory blocks from the programmable logic device, wherein: selecting one of the at least two potential mappings based on power consumption of each potential mapping, wherein the power consumption of each potential mapping is determined based on determining a number of embedded memory blocks, a number of ports in the plurality of memory ports that are associated with the potential mapping, and a size of associated logic circuits, and the power consumption of the selected potential mapping is less than the power consumption of at least one unselected potential mapping; implementing the logical memory block configuration layout using the selected potential mapping; and disabling a first memory port from the plurality of memory ports in response to a determination that the first memory port is unused in the implementation.