Patent ID: 9520407
Filing Date: 2016-12-13
CPC Classification: H01L

Claim Text:
1. A semiconductor memory device comprising: a connecting member including a semiconductor material; a first electrode film provided at least above the connecting member; a first insulating film provided on the first electrode film; a stacked body provided on the first insulating film, the stacked body including second electrode films and second insulating films, each of the second electrode films and each of the second insulating films being alternately stacked; three or more semiconductor pillars arrayed along two or more directions different from one another, extending in a stacking direction of the second electrode films and the second insulating films, piercing through the stacked body and the first insulating film, and connected to the connecting member; a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film; and a charge storage layer provided at least between one of the second electrode films and the third insulating film, the semiconductor pillars and the connecting member being integrally formed.