Patent ID: 9293359
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. An array of memory devices, comprising: a substrate of semiconductor material having a first conductivity type and a top surface; spaced apart isolation regions formed in the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; each of the isolation regions includes a trench formed into and extending below the top surface of the substrate and an insulation material formed in the trench, wherein at least portions of a top surface of the insulation material are recessed below the top surface of the substrate; each of the active regions including a column of memory cells, wherein each of the memory cells comprises: wherein the select gates are formed as continuous word lines each extending in a second direction perpendicular to the first direction and each forming the select gate for one of the memory cells in each of the columns of memory cells, and wherein portions of each of the word lines extend down into the trenches and over the insulation material in the isolation regions such that for each memory cell: wherein each of the floating gates is conductive material disposed over and insulated from the top surface of the substrate without any portion thereof extending into any of the trenches.