Patent ID: 9425202
Filing Date: 2016-08-23
CPC Classification: G11C,H01L

Claim Text:
1. An integrated circuit with a memory array, comprising: a plurality of active strip stacks with memory cells of the memory array, active strip stacks in the plurality of active strip stacks having first ends and second ends; and a plurality of active strip stack selection structures electrically coupled to the plurality of active strip stacks at positions between the first ends and the second ends, the plurality of active strip stack selection structures selecting particular ones of the plurality of active strip stacks for operations, the plurality of active strip stack selection structures are double gate structures, the plurality of active strip stack selection structures including: a first set of active strip stack selection structures on a first side of a plurality of word lines; and a second set of active strip stack selection structures on a second side of the plurality of word lines, and wherein a particular active strip stack of the plurality of active strip stacks has: