Patent ID: 9450547
Filing Date: 2016-09-20
CPC Classification: H01L,H03F

Claim Text:
1. A semiconductor device comprising: a substrate with a surface; a first circuit on the substrate and comprising a plurality of electrical components, including a first transistor, and a first wire bond array electrically coupled between the first transistor and a first lead; a second circuit on the substrate and comprising a plurality of electrical components, including a second transistor, and a second wire bond array electrically coupled between the second transistor and a second lead; encapsulation material covering the surface of the substrate, the first and second transistors, the first and second wire bond arrays, and portions of the first and second leads; and an isolation wall formed of electrically conductive material located in the encapsulation material between the first circuit and the second circuit, the isolation wall formed of a rectangular body of material that extends perpendicularly from the surface of the substrate above a height of the first and second wire bond arrays, wherein the body of material also extends parallel to the surface of the substrate at least between the first and second wire bond arrays, the isolation wall being configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit, and wherein the isolation wall includes a plurality of holes through which the encapsulation material may flow during a process of making the semiconductor device.