Patent ID: 9269722
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A method of fabricating a three-dimensional (3D) semiconductor device comprising: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate, the substrate including a cell array region, a first pad region adjacent to the cell array region in a first direction, and a second pad region adjacent to the cell array region in a second direction perpendicular to the first direction, forming a mask pattern covering the cell array region, the mask pattern having a first sidewall located on the first pad region and a second sidewall located on the second pad region performing an etching process using the mask pattern as an etch mask on the stack structure; and after performing the etching process, performing a process of enlarging the area of the mask pattern, wherein the performing the process of enlarging the area of the mask pattern includes laterally moving the first sidewall of the mask pattern by a first distance and laterally moving the second sidewall of the mask pattern by a second distance less than the first distance.