Patent ID: 9287286
Filing Date: 2016-03-15
CPC Classification: G11C,H01L

Claim Text:
1. A three-dimensional nonvolatile memory device, comprising: a plurality of word lines stacked over a substrate; a first vertical hole and a second vertical hole vertically passing through the word lines; a first vertical channel layer formed in the first vertical hole; a second vertical channel layer formed in the second vertical hole, wherein the second vertical channel layer is coupled to the first vertical channel layer through a pipe channel layer; tunnel insulating layers, charge trap layers and charge blocking layers surrounding the first vertical channel layer and the second vertical channel layer in each of the first vertical hole and the second vertical hole; a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, wherein the pad and the contact plug are vertically in alignment with the first vertical channel layer, and a width of the pad is greater than that of the first vertical hole and that of the contact plug; and a common source line formed over the second vertical channel layer.