Patent ID: 9368551
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first fin-shaped semiconductor layer on a semiconductor substrate; a first insulating film around the first fin-shaped semiconductor layer; a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer; a first gate insulating film around the first pillar-shaped semiconductor layer; a first gate line around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer; a diffusion layer in a lower portion of the first pillar-shaped semiconductor layer; a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer; a first contact electrode surrounding the third gate insulating film, wherein an upper portion of the first contact electrode is electrically connected to the upper portion of the first pillar-shaped semiconductor layer; and a first magnetic tunnel junction memory element electrically connected to the upper portion of the first pillar-shaped semiconductor layer.