Patent ID: 9331036
Filing Date: 2016-05-03
CPC Classification: H01L,H05K

Claim Text:
1. A semiconductor device, comprising: (a) a wiring board including: a first insulating layer including a first surface, and a second surface opposite to the first surface, a first pattern formed on the second surface, a plurality of second patterns formed on the second surface and also arranged around the first pattern in plan view, and a second insulating layer formed over the second surface of the first insulating layer; (b) a semiconductor chip mounted over the first surface of the first insulating layer, and also including: a plurality of pads (PD) electrically connected with the plurality of second patterns, respectively, wherein the second insulating layer has a plurality of first apertures and a plurality of second apertures, wherein the plurality of first apertures expose a plurality of first parts of the first pattern and a plurality of first parts of the first insulating layer, respectively, and wherein the plurality of second apertures expose the plurality of the second patterns and a plurality of second parts of the first insulating layer, respectively.