Patent ID: 9312366
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method of processing an integrated circuit (IC) structure for metal gate replacement, the method comprising: providing a structure including a first semiconductor fin and a second semiconductor fin positioned over a buried insulator layer of a silicon-on-insulator (SOI) substrate, and a gate structure positioned over the first and second semiconductor fins, wherein the gate structure includes a gate dielectric layer and a metal layer positioned over the gate dielectric layer; forming a planarizing resist over the first and second semiconductor fins, wherein the planarizing resist includes: removing a portion of the second OPL to create an exposed portion of the first OPL positioned over the second semiconductor fin, wherein the removing substantially terminates before removal of the exposed portion of the first OPL, based on the etch selectivity of the second OPL being greater than the etch selectivity of the first OPL; removing at least the exposed portion of the first OPL and a portion of the metal layer positioned over the second semiconductor fin to expose the gate dielectric layer over the second semiconductor fin; and forming a replacement metal gate (RMG) over the gate dielectric layer over the second semiconductor fin.