Patent ID: 9514848
Filing Date: 2016-12-06
CPC Classification: G06F,G11C

Claim Text:
1. A solid state drive, connected to a host through an external bus, comprising: a processing circuit, connected to the external bus for receiving a read command from the host, wherein the processing circuit further comprises an error check and correction (hereinafter, ECC) controller; a flash memory, connected to the processing circuit; and a buffer, connected to the processing circuit, wherein a read data and a corresponding ECC code are retrieved from the flash memory and temporarily stored to the buffer by the processing circuit, and the ECC controller verifies the read data according to a predetermined algorithm and the ECC code, wherein when an error of the read data is uncorrectable, a retry action is performed according to a retry table, wherein a usage order of a plurality of algorithms is defined in the retry table, wherein, the plurality of algorithms includes at least two different ECC algorithms for being executed by the ECC controller, wherein, during the retry action, one of the ECC algorithms is selected according the usage order and executed by the ECC controller to correct the error of the read data.