Patent ID: 9496415
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A method of fabricating a transistor device, comprising: forming a light transparent insulating layer on a substrate; selectively etching an opening in the light transparent insulating layer to the substrate, wherein the opening exposes a top surface of the substrate and includes sidewalls extending from the bottom surface to an upper surface of the light transparent insulating layer; conformally depositing a liner layer onto the light transparent insulating layer including the sidewalls of the opening and the top surface of the substrate defined by the opening; depositing a metal conductive layer onto the substrate including partial deposition of the metal conductive layer into the opening; and chemically mechanically polishing or anisotropically etching the metal conductive layer and the liner layer overlaying the upper surface of the light transparent insulating layer, wherein the liner layer and the metal conductive layer define a metal gate in the opening, wherein the metal gate has a concave shape defined by three faces; conformally depositing a gate insulating layer onto the light transparent layer and the metal gate; conformally depositing an amorphous metal oxide layer onto the gate insulating layer; depositing onto the amorphous metal oxide layer a sacrificial insulator layer and reflowing the sacrificial insulator layer to form a planar surface; pattern etching the amorphous metal oxide layer and the sacrificial insulator layer, wherein the patterned amorphous metal oxide layer defines a channel and the patterned sacrificial insulator layer has sidewalls coinciding with sidewalls of the channel; selectively etching the patterned sacrificial insulator layer to expose end portions of the channel and define a self-aligned step width (t); conformally depositing a conductive metal layer and forming source/drain regions on the exposed end portions of the channel by removing portions of the conductive metal layer overlaying the selectively etched sacrificial insulator layer, thereby effecting source and drain regions; and removing the selectively etched sacrificial layer.