Patent ID: 9515250
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. An electronic device comprising a semiconductor memory unit that includes: a first interlayer dielectric layer which is formed over a substrate; a variable resistance pattern formed over the first interlayer dielectric layer; a protective layer formed over the substrate to cover the variable resistance pattern and the first interlayer dielectric layer; and a contact plug formed adjacent to the variable resistance pattern over the substrate and configured to be located outside the protective layer to penetrate through the first interlayer dielectric layer to be coupled with the substrate, wherein the protective layer includes (1) a first protective layer that has a uniform thickness and is in contact with the variable resistance pattern and the first interlayer dielectric layer and (2) a second protective layer that is in contact with the first protective layer to cover the first protective layer, has a spatially varying thickness in different parts of the second protection layer to include an overhang portion in contact with an upper portion of a sidewall of and a top portion above the variable resistance pattern to protect the variable resistance pattern from oxidation.