Patent ID: 9312156
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first wiring layer; a gate insulating layer covering the first wiring layer; a semiconductor layer over the gate insulating layer, overlapping the first wiring layer, and comprising a channel formation region; first and second impurity semiconductor layers on the semiconductor layer, the first and second impurity semiconductor layers being configured to be a source region and a drain region; and second wiring layers over the first and second impurity semiconductor layers; wherein the semiconductor layer includes a pair of first regions each having a first width along a channel formation region width direction and a second region provided between the pair of first regions and having a second width along the channel formation region width direction, the second width being larger than the first width, wherein the second wiring layers overlap with at least a portion of the second region, and wherein each of edges of the first and second impurity semiconductor layers is in direct contact with the semiconductor layer on the first wiring layer.