Patent ID: 9448109
Filing Date: 2016-09-20
CPC Classification: G01J,H03M

Claim Text:
1. An analog-to-digital conversion circuit comprising: a plurality of comparators, each configured to output a comparing result signal indicating a result of comparing an analog signal with a reference signal having a signal level changing with elapse of time; a plurality of memories, each arranged correspondingly to one of the plurality of comparators; a counter configured to generate a count signal having a plurality of bits in Gray code by counting a clock signal; and a plurality of first signal wirings, each configured to transmit one of the plurality of bits of the count signal from the counter to the plurality of memories, wherein each of the plurality of memories holds the count signal according to a signal level change of the comparing result signal of corresponding one of the plurality of comparators, to convert the analog signal to a digital signal, and wherein each of the plurality of memories has a plurality of bit memories, each storing one bit of the plurality of bits, the analog-to-digital conversion circuit further comprises a plurality of second signal wirings, each connecting between the bit memories of the plurality of memories, each of the plurality of second signal wirings is connected to one of the plurality of first signal wirings, and the plurality of first signal wirings and/or the plurality of second signal wirings include a signal wiring transmitting a signal of least significant bit in the count signal arranged between the other signal wirings each transmitting a signal of a bit different from the least significant bit in the count signal.