Patent ID: 9502335
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A package structure, comprising: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires positioned on the conductive connection portions, respectively, wherein each of the conductive wires has opposite first and second ends and the conductive wires are bonded to the conductive connection portions via the first ends thereof, wherein a certain number of the conductive wires are formed in a vertical line shape by wire bonding and another certain number of the conductive wires are formed in a curved shape by wire bonding; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein the encapsulant has opposite first and second surfaces and a side surface adjacent to the first and second surfaces, the encapsulant is bonded to the chip carrier and the conductive connection portions via the first surface thereof, the second ends of the conductive wires in the vertical line shape are exposed from the second surface of the encapsulant, and the second ends of the conductive wires in the curved shape are exposed from the side surface of the encapsulant; a redistribution layer (RDL), an under bump metallization (UBM) layer, an anisotropic conductive film (ACF) layer, or an organic solderability preservative (OSP) layer formed on the side surface of the encapsulant and in contact with the exposed second ends of the conductive wires in the curved shape; and a circuit layer formed on the second surface of the encapsulant and electrically connected to the exposed second ends of the conductive wires in the vertical shape.