Patent ID: 9390058
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. A processor comprising: a register attribute tracker configured to receive instruction operations corresponding to an instruction stream, and in response to receiving a first instruction operation specifying a plurality of input registers, wherein the plurality of input registers are each configured to store a vector to be operated upon during execution of the first instruction operation, and further in response to the register attribute tracker having associated a tracked attribute with a first input register of the plurality of input registers, the register attribute tracker is configured to associate a second attribute to a second input register specified by the first instruction operation based on the tracked attribute of the first input register, wherein the tracked attribute and the second attribute specify vector size information, and wherein the register attribute tracker is configured to operate on the first instruction operation prior to issuance of the first instruction operation for execution in the processor, and wherein the register attribute tracker is configured to track different attributes with respect to different registers at a given point in time.