Patent ID: 9389956
Filing Date: 2016-07-12
CPC Classification: G06F,G11B,G11C,H03M

Claim Text:
1. A flash memory system for implementing (Error Correction Codes) ECC control comprising: a flash memory; a flash test and maintenance engine (FTME) coupled to each flash chip in the flash memory system; a memory controller, said memory controller comprising; a VT (threshold voltage) monitor monitoring in a background process to determine VT degradation of cells and blocks in the flash memory with the FTME used to measure and process VT measurement and determine VT degradation of the of cells and blocks in each flash chip in the flash memory system; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer delay than the first ECC engine; a logic receiving a read request to a particular cell/block, comparing the determined VT degradation with a threshold, and, using the determined VT degradation, to use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.