Patent ID: 9417920
Filing Date: 2016-08-16
CPC Classification: G06F

Claim Text:
1. A method comprising: decoding a received instruction from a first thread executing on a processor to produce a decoded instruction, wherein in response to a first determination that each of the first set of instruction queues is full after decoding the received instruction from the first thread, in response to a second determination that no empty queue is available to be allocated to the first thread after decoding the received instruction from the first thread, in response to the first thread having a higher fairness indicator than the second thread: in response to the first thread not having a higher fairness indicator than the second thread: dispatching the decoded instruction to the first allocated queue becoming the candidate queue, in response to the first allocated queue being no longer full; re-allocating the second allocated queue becoming the candidate queue to the first thread, in response to the second allocated queue becoming empty; and dispatching the decoded instruction to the second allocated queue, in response to the re-allocating the second allocated queue.