Patent ID: 9318208
Filing Date: 2016-04-19
CPC Classification: G11C,H01L

Claim Text:
1. A method for operating a small-area electrically erasable programmable read only memory array, wherein said small-area electrically erasable programmable read only memory (EEPROM) array comprises a plurality of parallel bit lines; a plurality of parallel word lines; a plurality of parallel common source lines; and a plurality of sub-memory arrays, and wherein said bit lines are divided into a plurality of bit line groups including a first bit line group and a second bit line group, and wherein said word lines are vertical to said bit lines and include a first word line, and wherein said common source lines are parallel to said word lines and include a first common source line, and wherein each said sub-memory array is connected with two said bit line groups, one said word line and one said common source line, and wherein each said sub-memory array includes a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, and wherein said first memory cell is connected with said first bit line group, said first common source line and said first word line, and wherein said second memory cell is connected with said second bit line group, said first common source line and said first word line, and wherein said first memory cell and said second memory cell are arranged symmetrically and disposed at an identical side of said first common source line, and wherein said third memory cell is connected with said first bit line group, said first common source line and said first word line, and wherein said third memory cell and said first memory cell are symmetrically arranged with said first common source line being a symmetric axis, and wherein said fourth memory cell is connected with said second bit line group, said first common source line and said first word line, and wherein said fourth memory cell and said second memory cell are symmetrically arranged with said first common source line being a symmetric axis, and wherein said fourth memory cell said third memory cell are symmetrically arranged, and wherein a first group consisting of said first memory cell and said second memory cell and a second group consisting of said third memory cell and said fourth memory cell are respectively arranged at two different sides of said first common source line, and wherein each of said first memory cell, said second memory cell, said third memory cell and said fourth memory cell includes an N-type field-effect transistor (FET) formed in a P-type substrate or a P-type well, and wherein said first memory cell, said second memory cell, said third memory cell and said fourth memory cell all function as operation memory cells, and wherein in operating all said operation memory cells, said method is characterized in that a substrate voltage V sub is applied to said P-type substrate or said P-type well, which is connected with all said operation memory cells, and that a bit voltage V b , a word voltage V w and a common source voltage V s are respectively applied to all said bit lines, said word lines and said common source lines, which are connected with all said operation memory cells, wherein the common source voltage V s and the bit voltage V b are equal to one another in both writing and erasing operations, and that in writing, following conditions must be satisfied: that in erasing, following conditions must be satisfied: