Patent ID: 9412462
Filing Date: 2016-08-09
CPC Classification: G11C,H01L

Claim Text:
1. A 3D stacked memory array comprising: a plurality of active lines formed at regular intervals in a first horizontal direction with a plurality of semiconductor layers vertically stacked having insulating films between upper and lower layers on a substrate; a plurality of word lines formed at regular intervals in a second horizontal direction to be vertically aligned to each of the active lines and to pass by the plurality of semiconductor layers with insulating layers including a charge storage layer between each of the word lines and the semiconductor layers; and a plurality of string selection lines formed at regular intervals in the second horizontal direction to be parallel to each of the word lines on one side of the plurality of word lines and to pass by the plurality of semiconductor layers with insulating layers including a charge storage layer between each of the string selection lines and the semiconductor layers, wherein each of the string selection lines forms a plurality of string selection transistors vertically stacked passing by the plurality of the semiconductor layers, and wherein the plurality of string selection transistors vertically stacked have a sum of threshold voltages or threshold voltage state numbers distributed along each of the semiconductor layers in the second horizontal direction to be equal between the layers by programming the charge storage layer of each of the string selection transistors.