Patent ID: 9379857
Filing Date: 2016-06-28
CPC Classification: H04J,H04L

Claim Text:
1. An integrated circuit comprising: memory that stores a first orthogonal matrix and a second orthogonal matrix, each of which is a matrix with N rows and N columns where N is a natural number equal to or larger than 2, the second orthogonal matrix generated by cyclically shifting chips of particular rows of the first orthogonal matrix; mapping circuitry coupled to the memory, wherein the circuitry, in operation, multiplies demodulation reference signals for a first layer group with the first orthogonal matrix to obtain first multiplying results; superposingly maps the first multiplying results in a same time period of a first subcarrier group in a resource block; multiplies demodulation reference signals for a second layer group with the second orthogonal matrix to obtain second multiplying results; and superposingly maps the second multiplying results in a same time period of a second subcarrier group which is different from the first subcarrier group in the resource block, each of the first layer group and the second layer group comprising N layers; and transmitting circuitry which, in operation, transmits the resource block on which the multiplied demodulation reference signals for the first layer group and the multiplied demodulation reference signals for the second layer group are mapped, the mapped demodulation reference signals to be used by a communication partner apparatus to demodulate data signals that are superposed in each layer of the first layer group and the second layer group in the resource block.