Patent ID: 9324402
Filing Date: 2016-04-26
CPC Classification: G11C,H01L

Claim Text:
1. A memory array comprising: a first row comprising two or more bit cells; a first bit cell of the first row comprising a memory element with three terminals and an access transistor; a common gating transistor for the first row coupled to a first voltage, the common gating transistor to enable read and write operations for the first row, wherein the common gating transistor is coupled to a first terminal of the memory element; a bit line coupled to a drain/source terminal of the access transistor; and a word line for the first row coupled to a gate terminal of the access transistor; wherein a second terminal of the memory element is coupled to a second bit cell in the first row and a third terminal of the memory element is coupled to a source/drain terminal of the access transistor, wherein the memory element comprises a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT)-switched magnetic tunnel junction (MTJ).