Patent ID: 9384858
Filing Date: 2016-07-05
CPC Classification: G11C

Claim Text:
1. An integrated circuit system comprising: a plurality of memory cells organized in groups and addressable to allow reading and writing of binary values to the memory cells; a voltage control system independently applying a controllable voltage to the memory cells of different groups; a memory reliability circuit communicating with the memory cells and voltage control system to, for a given group: (a) reduce the voltage applied to the given group using the voltage control system to less than an operating voltage applied to other memory cells of other groups to simulate aging of the given group; (b) write a test vector to the memory cells of the given group; (c) read the test vector from the memory cells of the given group as a modified test vector change by any memory cell failure; (d) compare the test vector to the modified test vector; and (e) provide an output indicating predicted failure of the given group when the test vector does not match the modified test vector.