Patent ID: 9256534
Filing Date: 2016-02-09
CPC Classification: G06F

Claim Text:
1. A method of orchestrated shuffling of data in a non-uniform memory access device that includes a plurality of processing nodes, each processing node directly connected to at least one memory device and indirectly connected to at least one of the other memory devices via at least one of the other processing nodes, the method comprising: running an application on a plurality of threads executing on the plurality of processing nodes; identifying, by the threads, data to be shuffled from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes; registering, by the plurality of threads, the data to be shuffled among threads by transferring the data from source memory devices directly connected to the source processing nodes to target memory devices directly connected to the target processing nodes; generating a plan for orchestrating the shuffling of the data among all memory devices associated with the plurality of threads; disabling cache coherency of cache memory associated with the plurality of processing nodes; performing the shuffling of the data among all memory devices upon disabling the cache coherency, based on the plan for orchestrating the shuffling; and restoring the cache coherency of the cache memory based on completing the shuffling of the data among all memory devices.