Patent ID: 9285415
Filing Date: 2016-03-15
CPC Classification: G01R

Claim Text:
1. A test system, comprising: a test device configured to generate a plurality of test signals that correspond to each of a plurality of test parameters; a built-off test module configured to duplicate the test signals, to apply a plurality of duplicated test signals to each of a plurality of devices under test through each of corresponding channels, and to provide a plurality of decision signals based upon a plurality of final test result signals received from each of the devices under test; and a test board connected to the built-off test module through the channels, the devices under test being mounted on the test board, wherein the built-off test module includes a plurality of built-off test units, each of the built-off test units comprises a respective signal processing block configured to duplicate corresponding ones of the test signals, to apply a plurality of duplicated test signals to each of devices under test, and to provide a plurality of decision signals based upon a plurality of test result signals from the corresponding device under test, and wherein each signal processing block includes a plurality of signal processing units, each signal processing unit comprising a signal processing block buffer that duplicates the test signal applied to the respective signal processing blocks, the signal processing block buffer being provided with first and second power supply voltages such that a voltage level of the respective duplicated test signals is adjustable according to the first and second power supply voltages.