Patent ID: 9331084
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: forming a fin structure on a semiconductor substrate; forming a well region in the semiconductor substrate by ion implantation so as to form transistors, wherein the transistors include a pull-up (PU) transistor, a transfer gate (PG) transistor, and a pull-down (PD) transistor of a static random-access memory (SRAM) cell; the ion implantation being used to adjust threshold voltages of the transistors, wherein standard threshold voltage (SVt) ion implantation conditions are used to adjust a first threshold voltage of the PU transistor and a second threshold voltage of the PG transistor, and low threshold voltage (LVt) ion implantation conditions are used to adjust a third threshold voltage of the PD transistor; forming a gate electrode for each transistor; and performing lightly doped drain (LDD) ion implantation and pocket area (PKT) ion implantation on the PU, PG, and PD transistors of the SRAM cell, wherein P-type high-threshold voltage (PHVT) ion implantation conditions are used for the LDD ion implantation and PKT ion implantation of the PU transistor; N-type standard threshold voltage (NSTV) ion implantation conditions are used for the LDD ion implantation and PKT ion implantation of the PG transistor; and N-type low-threshold voltage (NLVT) ion implantation conditions are used for the LDD ion implantation and PKT ion implantation of the PD transistor.