Patent ID: 9349851
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate having an active region and a device isolation layer that defines the active region; a gate electrode having first and second sidewalk on the active region; a source/drain region at a side of the gate electrode; first and second sidewall spacers on the respective sidewalls of the gate electrode; a buffer insulating layer on the device isolation layer between the first sidewall spacer and the source/drain region; an etch stop layer on the buffer insulating layer and extending onto the gate electrode and the source/drain region; a first interlayer insulating layer on the etch stop layer; and a first contact and a second contact each penetrating the first interlayer insulating layer and the etch stop layer, the first contact contacting the source/drain region, the second contact contacting the buffer insulating layer, and the first and second contacts spaced apart from each other, wherein the etch stop layer is on a planar top surface of the buffer insulating layer and on a planar sidewall of the buffer insulating layer.