Patent ID: 9419015
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a shallow trench isolation (STI) region and a fin-type field-effect transistor (FinFET) region in a silicon (Si) substrate, the FinFET region having first and second adjacent sections; forming a nitride layer and a silicon layer, respectively, on an upper surface of the STI region and the first and second sections of the FinFET region; removing a first section of the silicon layer and the nitride layer through a mask to expose the first section of the FinFET region; implanting the first section of the FinFET region with a dopant; removing remaining sections of the mask; removing a second section of the silicon layer and the nitride layer through a second mask to expose the second section of the FinFET region; implanting the second section of the FinFET region with another dopant; removing remaining sections of the second mask; and forming a thin-film transistor (TFT) on an upper surface of the silicon layer above the STI region, wherein the TFT channel comprises the silicon layer.