Patent ID: 9466249
Filing Date: 2016-10-11
CPC Classification: G09G

Claim Text:
1. A display comprising: a display panel; a timing controller; and a plurality of source drivers coupled to the timing controller and the display panel, the source drivers being coupled to one another, wherein the timing controller outputs a plurality of training packets to the source drivers for locking a clock of the timing controller, and latch signal is enabled during locking the clock of the timing controller, so as to trigger the source drivers to re-position voltages output by the source drivers, when the source drivers lock the clock of the timing controller based on the training packets, a lock signal is output to the timing controller, the timing controller outputs a plurality of color data packets and the latch signal to the source drivers based on the lock signal when the timing controller receives the lock signal, the source drivers respectively output a plurality of pixel voltages corresponding to the color data packets to the display panel based on the latch signal, and the training packets and the color data packets are serially transmitted to the source drivers, wherein the timing controller transmits a first start packet to the source drivers after the source drivers lock the clock of the timing controller to signal the transmission of control packets, the timing controller transmits a second start packet to the source drivers after the source drivers receive the control packets to signal the transmission of the color data packets, and the timing controller enables the latch signal after the color data packets are received by the source drivers, so as to determine a timing at which the source drivers output the pixel voltages, wherein the timing controller outputs the plurality of control packets to the source drivers based on the lock signal, and each of the control packets comprises two start bits, two end bits, and a control code located between the start bits and the end bits.