Patent ID: 9405683
Filing Date: 2016-08-02
CPC Classification: G06F

Claim Text:
1. A processor comprising: a processor core for processing an instruction; a cache configured to transceive data to/from the processor core via a single port, and store data accessed by the processor core; and a Scratch Pad Memory (SPM) configured to transceive data to/from the processor core via at least one port from among a plurality of ports, wherein an instruction executed in the processor core is allocated to one of the cache and the SPM, and the instruction comprises at least one of a load instruction and a store instruction, wherein the processor core profiles a program to obtain an execution count of each configuration of the load instruction and the store instruction, and a data closure of the load instruction and the store instruction; wherein the processor core searches for, from among all combinations of maximal data closures of each of the load instructions and the store instructions, a combination that increases a sum of execution counts of extra configurations, wherein the processor core further determines a combination of remaining data closures and the found combination, allocates the found combination to the SPM, and allocates the set of remaining data closures to the cache, and wherein the processor core partitions the accessed data based on profiling information, a data interference graph, and a size of the SPM.