Patent ID: 9306576
Filing Date: 2016-04-05
CPC Classification: H03K

Claim Text:
1. A Gray code counter stage of an n-bit Gray code counter circuit, comprising: a first OR gate for receiving (n-4)th and (n-5)th Gray code bits and generating a first intermediate signal at an output terminal thereof; a first AND gate connected to the output terminal of the first OR gate for receiving the first intermediate signal and a first enable signal, wherein the first AND gate generates a second enable signal at an output terminal thereof, wherein the first enable signal is generated based on a parity bit and a zeroth Gray code bit; a first CGIC connected to the output terminal of the first AND gate for receiving the second enable signal and a clock signal and generating a first gated clock signal; a first counter circuit connected to the first CGIC for receiving the first gated clock signal and a first direction bit and generating a (n-4)th Gray code bit and the (n-3)th Gray code bit; a second CGIC for receiving a third enable signal and the clock signal and generating a second gated clock signal; a first flip-flop having an input terminal for receiving an inverted first direction bit, a clock input terminal connected to the second CGIC for receiving the second gated clock signal, and an output terminal connected to the first counter circuit, wherein the first flip-flop generates the first direction bit at the output terminal thereof; a first NOT gate connected to the output terminal of the first flip-flop for receiving the first direction bit, and connected to the input terminal of the first flip-flop, wherein the first NOT gate generates the inverted first direction bit; a NOR gate for receiving the zeroth Gray code bit, and first through (n-4)th Gray code bits and generating a second intermediate signal at an output terminal thereof; a second AND gate connected to the output terminal of the NOR gate for receiving the second intermediate signal and the parity bit, wherein the second AND gate generates the third enable signal at an output terminal thereof, wherein the output terminal is connected to the second CGIC for providing the third enable signal; a third CGIC connected to the output terminal of the second AND gate for receiving the third enable signal and the clock signal and generating a third gated clock signal; and a second counter circuit for receiving a second direction bit and the third gated clock signal and generating (n-1)th and (n-2)th Gray code bits.