Patent ID: 9502557
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. An LDMOSFET comprising: a source comprising an n+ source region in a laterally diffused pwell, the n+ source region contacting a source electrode; a drain comprising an n− drain region lateral to an n+ drain region, the n+ drain region contacting a drain electrode, the n− drain region located between the n+ source region and the n+ drain region but separated from the n+ source region by the pwell; a first gate positioned to regulate a channel in the pwell, the channel between the n+ source region and the n− drain region; a first gate oxide layer formed under the first gate, the first gate oxide layer having a first thickness associated therewith; a second gate positioned to regulate a resistance of the n− drain region; and a second gate oxide layer formed under the second gate, the second gate oxide layer having a second thickness under a first portion of the second gate and having a third thickness under a second portion of the second gate, the second and third thicknesses being different relative to one another.