Patent ID: 9312029
Filing Date: 2016-04-12
CPC Classification: G11C

Claim Text:
1. A memory device, comprising: a memory cell array having a plurality of memory cells; a sensing unit, electrically connected to the memory cell array, for sensing a characteristic of a memory cell among the plurality of memory cells; a controller, electrically connected to the sensing unit, for determining whether the characteristic of the memory cell deviates and accordingly controlling the memory cell array; and a pulse generator, electrically connected to the memory cell array, for applying at least one testing pulse to the memory cell before the sensing unit senses the characteristic of the memory cell, wherein when the at least one testing pulse is applied to the memory cell during a reset operation, a duration of the at least one testing pulse is shorter than that of a reset pulse, and an amplitude of the at least one testing pulse is smaller than that of the reset pulse.