Patent ID: 9247654
Filing Date: 2016-01-26
CPC Classification: H05K

Claim Text:
1. A carrier substrate, comprising: a dielectric layer having a first surface and a second surface opposite to each other and a plurality of blind vias; a first circuit layer embedded in the first surface of the dielectric layer and having an upper surface and a lower surface opposite to each other, the upper surface exposed from the first surface of the dielectric layer, wherein the blind vias extend from the second surface to the first circuit layer and expose a portion of the lower surface of the first circuit layer; an insulation layer having a third surface and a fourth surface opposite to each other and disposed on the first surface of the dielectric layer through the fourth surface and covers a portion of the upper surface of the first circuit layer, the insulation layer having a plurality of first openings extending from the third surface to the fourth surface, wherein the first openings expose another portion of the upper surface of the first circuit layer, an aperture of each first opening is increased gradually from the third surface to the fourth surface, and the apertures of the first openings on the fourth surface are greater than a width of the exposed first circuit layer; a plurality of conductive blocks respectively disposed in the first openings of the insulation layer and connected with another portion of the upper surface of the first circuit layer exposed by the first openings; and a first conductive structure disposed on the second surface of the dielectric layer and comprising a plurality of conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.