Patent ID: 9496883
Filing Date: 2016-11-15
CPC Classification: H03M

Claim Text:
1. A chip, comprising: an analog-to-digital converter; a memory unit configured to store a look up table, wherein the look up table is configured to store a plurality of first digital code differences, and is configured to be calibrated according to a variation parameter, wherein the first digital code differences are generated, according to a first predetermined voltage and a second predetermined voltage, by the analog-to-digital converter at a plurality of gains respectively; and a digital-to-analog converter configured to generate the first predetermined voltage and the second predetermined voltage and output the same to the analog-to-digital converter to measure a second digital code difference generated by the analog-to-digital converter at a first gain among the plurality of the gains; wherein the variation parameter is a ratio of the second digital code difference and one of the first digital code differences.