Patent ID: 9268563
Filing Date: 2016-02-23
CPC Classification: G06F

Claim Text:
1. A computer program product for verification of a vector execution unit design, the computer program product comprising: one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising: program instructions to issue an instruction into a first instance of a vector execution unit; program instructions to issue the instruction into a second instance of the vector execution unit; program instructions to issue a random operand into a first lane of the first instance of the vector execution unit; program instructions to issue the random operand into a second lane of the second instance of the vector execution unit; program instructions to input one or more random operands into one or more unused lanes of the first and the second instance of the vector execution unit; program instructions to receive results from execution of the instruction and the random operand in the first instance of the vector execution unit and results from execution of the instruction and the random operand in the second instance of the vector execution unit; and program instructions to compare the received results.