Patent ID: 9389876
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. A semiconductor device, comprising: a first chip and a second chip, which are physically conjoined in a stacked structure; the first chip comprising functional circuitry; the second chip comprising: wherein functional circuitry of the first chip is connected to the I/O interface; wherein the calibration control circuitry on the second chip automatically configures the functional circuitry on the first chip to an initial system state using stored calibration data from said memory upon power-up of the semiconductor device; wherein the second chip further comprises gating control circuitry connected to the I/O interface; wherein the gating control circuity comprises a network of interconnected multiplexers and demultiplexers connected to the functional circuity of the first chip through the I/O interface; and wherein the gating control circuitry is configured to dynamically reconfigure electrical connections between components of the functional circuitry, in response to control signals from the calibration control circuity.