Patent ID: 9477104
Filing Date: 2016-10-25
CPC Classification: G02F,G09G

Claim Text:
1. A source driver with reduced number of latch devices, comprising: a master latch device, having a first transmission gate, a first inverter, a second inverter, a first enable gate, and a second enable gate wherein an output of the second inverter connected to an input of the first inverter; and slave latch device, having a second transmission gate, a third inverter with an input connected to an output of the second transmission gate, and a fourth inverter with an input connected to an output of the third inverter and an output connected to the input of the third inverter, wherein the first transmission gate of the master latch device is connected to receive a first input signal and the second transmission gate of the slave latch device is connected to receive a second input signal; the first enable gate and the second enable gate are directly connected to the fourth inverter of the slave latch device, when the first enable gate receives a latch enable signal and the second enable gate receives a complementary latch enable signal, the master latch device and the slave latch device are driven to concurrently latch the first input signal and the second input signal, respectively.