Patent ID: 9281036
Filing Date: 2016-03-08
CPC Classification: G06F,G11C

Claim Text:
1. A memory device comprising: a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address; at least one row address buffer for holding a selected row address of a set of successive selected row addresses; a set of row data buffers for holding respective contents of selected rows corresponding to the set of successive selected row addresses; a row decoder coupled to the at least one row address buffer and to the memory array for receiving the selected row address and for decoding the selected row address to access a selected row of the memory array; an array of sense amplifiers coupled to the memory array and coupled to the set of row data buffers for reading the selected row and transmitting content of the selected row to one of the row data buffers, and for writing the content of the selected row back to the selected row; a demultiplexer coupled to the array of sense amplifiers and the set of row data buffers for providing the content of the selected row from the array of sense amplifiers to the one of the row data buffers; and a control circuit for receiving and decoding a first command, the first command including a specified row address and a row mode indicator specifying a number of rows to be open, the control circuit comprising a memory mode register for holding the row mode indicator.