Patent ID: 9349639
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method for manufacturing contact structure electrically connecting a semiconductor device, the method comprising: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device comprises a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, wherein the stripe hole is disposed directly above the source/drain region; forming a stripe-shaped mask layer on the substrate during the step of forming the patterned mask layer, wherein the stripe-shaped mask layer is spaced apart from the source/drain region and the patterned mask layer, and the stripe-shaped mask layer has the shape of stripe when viewed from a top down perspective; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed directly above the source/drain region and wherein the longest side of each of the slot holes is parallel to the longest side of the stripe hole, and a width of the stripe hole is greater than a width of each slot hole; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, wherein the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.