Patent ID: 9449708
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array configured to have NAND strings arranged therein, each of the NAND strings including: a memory string configured to have a plurality of memory cells connected in series therein; and a first select transistor and a second select transistor respectively connected to two ends of the memory string; a plurality of word lines respectively connected to control gate electrodes of the plurality of memory cells; a plurality of bit lines each connected to a first end of the memory string included in the NAND strings via the first select transistor; a source line connected to a second end of the memory string via the second select transistor; and a control circuit configured to apply a verify voltage to a selected word line, apply a read pass voltage that renders conductive an unselected memory cell regardless of cell data to an unselected word line, and apply a bit line voltage of a certain value to a selected bit line, to execute a write verify operation that determines whether a selected memory cell has a desired threshold voltage or not, the selected memory cell being included in one of the NAND strings that includes one of the memory cells before undergoing execution of a write operation, the control circuit being configured to change a voltage value of the bit line voltage based on a position of the selected word line among the plurality of word lines relative to the NAND string during the write verify operation, and the control circuit being configured to apply different values of the read pass voltage for an unselected word line connected to the memory cell where the write operation has been performed and an unselected word line connected to the memory cell where the write operation has not been performed.