Patent ID: 9450057
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A split gate memory device disposed over a semiconductor substrate comprising: a common source/drain region disposed in the semiconductor substrate; first and second select gate structures arranged on opposite sides of the common source/drain region; first and second silicide-blocking caps comprising a first material on upper surfaces of the first and second select gate structures, respectively; first and second memory gate structures arranged on an opposite side of the first and second select gate structures as the common source/drain region, respectively; a first contact etch stop layer (CESL) comprising a second material and covering an inner sidewall of the first select gate structure facing the common source/drain region, an outer sidewall of the first memory gate structure facing away from the common source/drain region, and an upper surface of the first memory gate structure; and a second CESL comprising the second material and covering an inner sidewall of the second select gate structure facing the common source/drain region, an outer sidewall of the second memory gate structure facing away from the common source/drain region, and an upper surface of the second memory gate structure.