Patent ID: 9269702
Filing Date: 2016-02-23
CPC Classification: G06F,H01L

Claim Text:
1. A semiconductor device, comprising: a plurality of cells, wherein each of the plurality of cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner, and wherein each of the plurality of cells includes circuitry for performing one or more logic functions, the circuitry including a plurality of conductive features defined in one or more levels of the cell, and wherein at least one instance of a given cell is defined on the semiconductor device in accordance with any one of multiple versions of the given cell or combination thereof including, a first version of the given cell having an encroachment region defined within a particular cell level adjacent to a first segment of the outer cell boundary and a spacing allowance region defined within the particular cell level adjacent to a second segment of the outer cell boundary located opposite the given cell from the first segment, a second version of the given cell having the encroachment region defined within the particular cell level adjacent to both the first and second segments of the outer cell boundary, and a third version of the given cell having the spacing allowance region defined within the particular cell level adjacent to both the first and second segments of the outer cell boundary, wherein the encroachment region is defined as a peripheral region of the particular cell level of the given cell within which at least one encroaching feature is positioned to encroach by an encroachment distance into an exclusion zone, wherein the exclusion zone occupies an area within the given cell defined by an exclusion distance extending perpendicularly inward into the given cell from the outer cell boundary adjacent to the encroachment region, wherein the exclusion distance is based on a design rule distance, and wherein the spacing allowance region is defined to extend perpendicularly inward into the given cell from the outer cell boundary by a spacing allowance distance equal to at least the encroachment distance plus the exclusion distance, wherein the spacing allowance region within the particular cell level does not include any conductive features.