Patent ID: 9324424
Filing Date: 2016-04-26
CPC Classification: G11C

Claim Text:
1. A memory device comprising: a plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction crossing the first direction; and a plurality of memory cells each coupled to corresponding two of the word lines and corresponding two of the bit lines, wherein each of the memory cells includes a memory element and two select transistors having a first select transistor and a second select transistor disposed along the first direction, the memory element being configured to store information on the basis of changes in resistance, wherein one terminal of the memory element is coupled to one of the two bit lines corresponding to the memory cell, wherein the other terminal of the memory element is coupled to respective drains of the two select transistors, wherein respective sources of the two select transistors are coupled to the other of the two bit lines corresponding to the memory cell, wherein a gate of one of the two select transistors is coupled to one of the two word lines corresponding to the memory cell, wherein a gate of the other of the two select transistors is coupled to the other of the two word lines corresponding to the memory cell, and wherein a first column and a second column are formed by repeatedly arranging a first and a second group of the memory cells, respectively, along the first direction, and wherein the second column is disposed adjacent to the first column and the first group of memory cells is displaced with respect to the second group of memory cells in the first direction such that, in the second direction, the first transistor in respective memory cells in the first column is aligned with the second transistor in respective memory cells in the second column.