Patent ID: 9245998
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A process of forming an integrated circuit containing an LDNMOS transistor with multiple vertical current channels and a horizontal current channel, comprising the steps: forming a buried n-type buried diffusion on a p-type substrate; forming a p-type buried diffusion contained in the n-type buried diffusion; forming a plurality of vertical n-type extended drain diffusions over the p-type buried diffusion and between a LDNMOS transistor gate and the LDNMOS drain; implanting pwell dopant to form the body of the LDNMOS and to form a plurality of vertical pwell finger diffusions between the vertical n-type extended drain diffusions; implanting p-type dopant at low energy into the channel of an NMOS transistor to set a turn on voltage of the NMOS transistor and into a channel of the LDNMOS transistor to set a turn on voltage; forming an NMOS transistor gate, a PMOS transistor gate, and the LDNMOS transistor gate; forming dielectric sidewalls on the NMOS transistor gate, the PMOS transistor gate, and the LDNMOS transistor gate; forming source and drain diffusions of the NMOS transistor self-aligned to the dielectric sidewalls on the NMOS transistor gate; and forming an LDNMOS source self-aligned to the dielectric sidewalls on the LDNMOS transistor gate and forming an LDNMOS drain wherein the plurality of vertical n-type extended drain diffusions form a plurality of vertical LDNMOS channels between the source and the drain and wherein a horizontal LDMOS channel is formed between the LDNMOS source and LDNMOS drain in the buried n-type diffusion which lies under the buried p-type diffusion and over the p-type substrate.