Patent ID: 9430353
Filing Date: 2016-08-30
CPC Classification: G06F

Claim Text:
1. A computer implemented method, comprising: receiving information regarding a plurality of logical cores each having a corresponding memory in a multiple core processor; receiving a plurality of context switch records generated by recording context switches developed from executing a plurality of threads in a concurrent application on the multiple core processor during a course of time; generating a plurality of thread execution segments from the information and the context switch records, wherein each of the thread execution segments associates an instance of an executing thread on a corresponding logical core with respect to the course of time; and presenting the plurality of thread execution segments in a visualization configured to indicate which thread is executing on which logical core over the course of time for each of the plurality of threads to display thread migration in the concurrent application, the logical cores arranged along an axis of the visualization relative to their distance to each other's memory.