Patent ID: 9438351
Filing Date: 2016-09-06
CPC Classification: H03H,H04B

Claim Text:
1. An adjustable delayer for adjustably delaying an input signal based on a delay adjustment input information describing a desired delay, to obtain an output signal, the adjustable delayer comprising: a plurality of series-connected tunable delay circuits, wherein a first of the tunable delay circuits is configured to receive the input signal; a closed-loop control circuit configured to provide a first delay tuning information to tune a combined delay of the plurality of tunable delay circuits; and a combiner configured to combine the first delay tuning information with a second delay tuning information based on the delay adjustment input information to obtain a combined delay tuning information; wherein the adjustable delayer is configured to tune a delay of one or more of the tunable delay circuits based on the combined delay tuning information.