Patent ID: 9406567
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method for fabricating multiple transistor devices on a substrate with a plurality of threshold voltages, comprising: forming a first device in a substrate, the first device including a screen layer with a first dopant concentration, a threshold voltage layer with a second dopant concentration less than the first dopant concentration, and a substantially undoped epitaxial channel with a first thickness thereon, the screen layer, threshold voltage layer, and undoped epitaxial channel of the first device underlying a first gate; forming a second device in the substrate electrically isolated from the first device, the second device having a screen layer with a third dopant concentration, a threshold voltage layer with a fourth dopant concentration less than the third dopant concentration, and a substantially undoped epitaxial channel with a second thickness thereon, the screen layer, threshold voltage layer, and undoped epitaxial channel of the second device underlying a second gate, the second thickness being different than the first thickness such that the first and second devices have different threshold voltages; wherein a top surface of the substantially undoped epitaxial channel of the first device is substantially coplanar with a top surface of the substantially undoped epitaxial channel of the second device adjacent respective gates of the first and second devices.