Patent ID: 9323122
Filing Date: 2016-04-26
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: a substrate, data lines and gate lines which are provided on the substrate and intersect with each other, and sub-pixel units which are defined by surrounding of the data lines and the gate lines and are arranged in an array form; wherein two gate lines for respectively driving the sub-pixel units in two adjacent rows are located between the sub-pixel units in the two adjacent rows, and wherein each sub-pixel unit comprises a thin film transistor (TFT) and a pixel electrode, the TFT and the pixel electrode are electrically connected so as to function as a switch element, and a connection area of the TFT and the pixel electrode is located between the two gate lines adjacent to the sub-pixel unit and has no overlapping area with a projection of the two gate lines in a perpendicular direction of the array substrate.