Patent ID: 9397102
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate having a plurality of fins extending therefrom, including first and second fins, each fin including a channel region; a gate electrode over each channel region, wherein a gate dielectric layer is provided between each gate electrode and the corresponding channel region; p-type source/drain regions at least one of in and on the first fin and adjacent to the corresponding channel region and comprising silicon, germanium, or silicon germanium; n-type source/drain regions at least one of in and on the second fin and adjacent to the corresponding channel region and comprising silicon, germanium, or silicon germanium; a doped III-V semiconductor material layer on at least a portion of the p-type source/drain regions and a portion of the n-type source/drain regions; and at least one metal contact on the III-V semiconductor material layer.