Patent ID: 9425807
Filing Date: 2016-08-23
CPC Classification: H03L,H04L

Claim Text:
1. A timing synchronization circuit for a digital receiver structure, comprising: a timing error detection module comprising a phase difference calculation unit arranged for calculating a phase difference between incoming samples of a digital data stream, and a timing error estimator arranged for determining a timing error estimate based on the calculated phase difference, and for generating, based on the determined timing error estimate, a signal indicative of timing error detection; and a timing error control module arranged for receiving the signal indicative of timing error detection, for evaluating a number of received signals indicative of timing error detection, and for outputting, responsive to a comparison of the number of received signals indicative of timing error detection with a threshold value, a sampling adjustment command for adjusting sampling instants applied for obtaining the digital data stream, and wherein the timing error detection module is arranged for receiving the sampling adjustment command.