Patent ID: 9325542
Filing Date: 2016-04-26
CPC Classification: G06F,H04L

Claim Text:
1. A parallel, receiver interface comprising: a plurality of parallel data receivers, each parallel data receiver being configured to receive input data; a clock receiver configured to receive a forwarded clock; a phase interpolator, the input of which is coupled to the output of the dock receiver, and the output of which is coupled to each of the parallel receivers; multiple parallel clock delay elements within each of the parallel data receivers, the multiple parallel clock delay elements including a clock delay element having no phase adjustment capabilities, a clock delay element having phase adjustment capabilities for providing fractional unit interval deskew, and a clock delay element providing 360° phase adjustment capabilities; and a multiplexer circuit within each of the parallel data receivers, inputs of the multiplexer circuit being coupled to the outputs of each of the parallel clock delay elements within a respective parallel data receiver, and an output of the multiplexer circuit being coupled directly to a data sampler within the respective parallel data receiver, the multiplexer circuit being configured to be controlled by a logic signal.