Patent ID: 9391014
Filing Date: 2016-07-12
CPC Classification: H01L,H04L,H05K,Y10T

Claim Text:
1. An interconnect array comprising: a first plurality of conductive lines arranged in a substrate, the first plurality of conductive lines extending along a first direction to define respective rows; an insulator layer disposed on the first plurality of conductive lines; a second plurality of conductive lines arranged in the insulator layer, the second plurality of conductive lines extending along a second direction perpendicular to the first direction to define respective columns, wherein portions of the second plurality of conductive lines overlap portions of the first plurality of conductive lines; and a plurality of vias defined by the insulator layer, the plurality of vias arranged in a random pattern, the plurality of vias include at least one connected via and at least one disconnected via, the at least one connected via contacting at least one of the first plurality of conductive lines and the second conductive lines, and the at least one disconnected via that does not contact the first plurality of conductive lines and the second conductive lines.