Patent ID: 9489205
Filing Date: 2016-11-08
CPC Classification: G06F

Claim Text:
1. A system for producing a compiler-assisted look-ahead instruction fetch and branch prediction (CLIB) system for a microprocessor system comprising: a compiler-assisted look-ahead code (CLC) generation system; a single or plurality of compiler-assisted look-ahead instruction memory (CLIM) system; a single or plurality of look-ahead instruction prefetch/fetch/branch prediction (LIB) system; a single or plurality of modified frontend microprocessors for the CLIB system; and a single or plurality of backend microprocessors in prior arts; wherein the system for producing the CLIB system is operable to: recognize each compiler-assisted look-ahead instruction (CLI) representing an entire or a part of basic block from executable code compiled from application software and/or operating system for generating CLI code and compatible native instruction (CNI) code wherein the basic block is an instruction segment with only one entry and only one exit in the program and the native instruction (NI) is the instruction discovered from the program compiled by compiler or the instructions available in the target instruction set; compose the CLI code comprising CLIs, CNIs, and/or additional information to retrieve a single or plurality of the CNIs of the CLIs during the CLI/CNI prefetch and fetch operations; compose the CNI code comprising NIs and/or additional information to access NIs in programmed order and to terminate accessing a single or plurality of the NIs in a CNI during the CNI prefetch and fetch operations; fetch the CLIs from the CLI code to a single or plurality of the microprocessors before initiating to fetch the CNIs from the CNI code to the microprocessors according to the CNI fetch order obtained from the associated CLI; fetch a single or plurality of the CLIs representing conditional branches to a branch predictor for predicting a single or plurality of locations of the next CLIs in the CLI code and start to fetch the next CLIs to the microprocessors while continuously fetching the CNIs of the previous or current CLIs fetched to the microprocessors; and receive a single or plurality of branch prediction results of the CLIs produced by a branch predictor in prior arts even before completely fetching the associated CNIs; wherein the CLIB system is further operable to: generate CLIs and associated CNIs of applications and/or operating system programmed in high-level programming languages, assembly program compiled with instruction sets, or executable code for microprocessors by the CLC generation system; disassemble NIs in an executable code or assembly code to CLI code and CNI code; compose a CLI comprising a single or plurality of another CLIs, NIs, and/or additional information to access associated CNIs; compose a single or plurality of CLIs representing a single or plurality of levels of loops in the executable code or assembly code; compose a CNI comprising a single or plurality of NIs and/or another CNIs; compose a single or plurality of CNIs representing a single or plurality of levels of loops in the executable code or assembly code; allocate CLIs and CNIs to the sequentially and/or concurrently accessible main CLI memory (CLIM) and main CNI memory (CNIM), respectively; access CLIs and CNIs from the sequentially and/or concurrently accessible main CLIM and main CNIM to the sequentially, concurrently, and/or a single or plurality of times quickly accessible CLI cache (CLIC) and CNI cache (CNIC), wherein the plurality of times quickly accessible caches are two or more times faster than the clock speed of the microprocessors; retrieve the NIs from the CNI code and/or CLI code during the CNI and/or CLI fetch operation via a single or plurality of the LIB system; perform pipelined and/or parallel look-ahead CLI and CNI prefetch/fetch/branch prediction operations; prefetch the CLIs and the CNIs, respectively, from the main CLIM and/or level-2 (L2) CLIC to level-1 (L1) CLIC and from the main CNIM and/or L2 CNIC to L1 CNIC via compiler-assisted look-ahead instruction prefetch (CLIP) system in the LIB system; terminate the CLI prefetch after continuously prefetching the CLIs from both of the branched and fall-through paths one or more times to the CLICs in the CLIP system; prefetch the CLIs addressed by the LIB system to the CLICs whenever a single or plurality of branch target addresses is obtained from a single or plurality of the LIB system or the modified frontend microprocessors for the CLIB system; decode the prefetched CLIs for prefetching the associated CNIs and for prefetching variable-length NIs via CLI decoder in the CLIP system; perform look-ahead fetch operations of the CLIs addressed by compiler-assisted look-ahead instruction fetch (CLIF) system in the LIB system to the modified frontend microprocessors whenever a single or plurality of branch target addresses is obtained from a single or plurality of the LIB system or the modified frontend microprocessors for the CLIB system; decode the fetched CLIs for look-ahead fetching the associated CNIs and for look-ahead fetching fixed- and/or variable-length NIs via the CLIF system to the modified frontend microprocessors; perform look-ahead branch prediction operations of the CLIs received with a branch predictor regardless of fetching the associated CNIs; perform next look-ahead prefetch and fetch operations of CLIs and NIs of the CNIs according to the branch prediction results; identify a CLI representing a single or plurality of loops by the CLI decoder in order to reuse the same CLI representing the loops for the look-ahead branch prediction while holding further CLI fetch operation; handle any disrupted prefetch and/or fetch operations of CLIs and/or NIs of the CNIs caused by branch predictors, interrupt processors, or any other units in the microprocessors or the LIB system for look-ahead prefetch and fetch operations; resume the prefetch and/or fetch operations of the CLIs and/or NIs of the CNIs by recovering the information of the prefetch and/or fetch operations of the CLIs and/or NIs of the CNIs after completing the disrupted prefetch and/or fetch operations; access a fixed or a variable number of NIs of the CNIs from the main CNIMs via the associated L1 and L2 CNICs; access each of CLI and the NIs of each CNI, respectively; access CLIs and NIs of the un-associated CNIs of the CLIs concurrently; overlap the CLI access time and NIs of the CNI access time for enhancing instruction fetch bandwidth; access only NIs that need to be fetched via the L1 and L2 CLICs and CNICs in a pipelined parallel manner for accurate instruction fetch; determine how many NIs need to be fetched to the microprocessor within fewer cycles via the CLIB system assisted by the CLIs; employ L1 and/or L2 CLICs and CNICs as small, simple, and fast primary caches with a half or less cycle latency of the microprocessor clock cycle latency; construct a larger size of L1 or L2 CLICs and CNICs with the same cycle latency by bundling a plurality of primary caches; maintain the same latency of the various sizes of CLICs and CNICs in the CLIM system for further performance enhancement; exclude a branch predictor for prefetching CLIs and NIs of the CNIs from the CLIM system.