Patent ID: 9292464
Filing Date: 2016-03-22
CPC Classification: G06F,Y02D

Claim Text:
1. A multiprocessor system, comprising: a plurality of processors, each comprising a plurality of processor ports; a plurality of memories; a plurality of routers, wherein the plurality of routers form a primary interconnection network; wherein the plurality of processors, the plurality of memories and the plurality of routers are coupled together in a interspersed fashion; a plurality of interface units, wherein each interface unit is coupled to a respective processor and a respective router; wherein the plurality of interface units are coupled together to form a secondary interconnection network; a bus controller coupled to at least one specified interface unit, wherein the bus controller is configured to send data to and receive data from the at least one specified interface unit; wherein the bus controller is configured to arbitrate requests for access to the at least one specified interface unit; a processor interface block coupled to the bus controller and also coupled to a specified router associated with the at least one specified interface unit, wherein the processor interface block is configured to allow any of a plurality of processors in the multiprocessor system to use the primary interconnection network to access the secondary interconnection network through the specified router.