Patent ID: 9430985
Filing Date: 2016-08-30
CPC Classification: G09G

Claim Text:
1. A display device comprising: a display panel including gate and data lines that cross each other; a first control signal generation unit that generates a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal; a second control signal generation unit that starts to count a number of clocks of a fixed-frequency clock signal at a point of time at which a logic high state of the source output enable signal ends, and outputs a second gate output enable signal when the counted number of the clocks becomes equal to a reference value, wherein the fixed-frequency clock signal is generated by a clock signal generation unit that is not influenced by the spread frequency clock signal; an output control unit that outputs the first gate output enable signal as a gate output enable signal when a status of a current frame is judged to be abnormal under which a charging time of a horizontal line overlaps an output time of image data of a next horizontal line if the second gate output enable signal is applied in the current frame, and outputs the second gate output enable signal as a gate output enable signal when a status of the current frame is judged to be normal under which the charging time of the horizontal line does not overlap the output time of image data of the next horizontal line if the second gate output enable signal is applied in the current frame; and a gate driving unit that controls an outputting of a gate signal to the gate line using the second gate output enable signal.