Patent ID: 9520409
Filing Date: 2016-12-13
CPC Classification: G11C,H01L

Claim Text:
1. A method of manufacturing a three-dimensional nonvolatile memory device, the method comprising: depositing a plurality of interlayer insulating layers and a plurality of sacrificial layers in a stacked configuration along first vertical channel layers and second vertical channel layers, wherein the first and second vertical channel layers extend from a substrate; etching portions of the plurality of the interlayer insulating layers and the plurality of sacrificial layers to form a slit, wherein portions of the sacrificial layers are exposed through a sidewall of the slit; removing the portions of the sacrificial layers exposed by the slit to form recesses between the interlayer insulating layers; filling the recesses with conductive layers to form a plurality of word lines; forming pads having a generally island shape over the first vertical channel layers; forming a common source line having a generally rectangular shape over the second vertical channel layers; forming contact plugs over the pads; and forming a bit line over the contact plugs; wherein a width of the pad is greater than that of the first vertical channel layer and that of the contact plug.