Patent ID: 9424952
Filing Date: 2016-08-23
CPC Classification: G11C

Claim Text:
1. A circuit for measuring threshold voltages of transistors in a memory device bitcell, comprising: a multiplexer that has a plurality of pairs of inputs, each connected to a different pair of bitlines of the memory device, and that has an output connected to a pair of bitline terminals; a first plurality of interconnected switches that are connected to a ground, a test voltage, a sense voltage node (V a second plurality of interconnected switches that are connected to the test voltage, the ground, the sense voltage node (V a zero-V wherein, when in a first configuration of the multiplexer, the first plurality of interconnected switches, and the second plurality of interconnected switches, a gate of a first transistor of the bitcell and one of a drain and a source of the first transistor of the bitcell are coupled to the test voltage, another of the drain and the source of the first transistor of the bitcell is coupled to the drain of the zero-V