Patent ID: 9257438
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A semiconductor device structure, comprising: a substrate, wherein the substrate has a cell region and a logic region; an isolation feature formed in the substrate; a first gate stack structure formed on the isolation feature and at the cell region; a second gate stack structure formed on the isolation feature and at the cell region, wherein the first gate stack structure is adjacent to the second gate stack structure; and a capping layer formed on the isolation feature between the first gate stack structure and the second gate stack structure, wherein the entire capping layer has a height that is less than half the height of the first gate stack structure, and a lateral external sidewall of the entire capping layer is in direct contact with a lateral sidewall of the first gate stack structure, and a top of the lateral external sidewall of the entire capping layer is below a top of the lateral sidewall of the first gate stack structure, wherein the isolation feature between the first gate stack structure and the second gate stack structure has a substantially planar topography.