Patent ID: 9401202
Filing Date: 2016-07-26
CPC Classification: G06F,G11C

Claim Text:
1. A memory device, comprising: an array of memory elements including discrete re-writable non-volatile two-terminal resistive memory elements disposed between word lines and subsets of bit lines; an access signal generator configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a discrete re-writable nonvolatile two-terminal resistive memory element associated with a word line and first one of the subsets of bit lines; a tracking signal generator configured to track the modified magnitude of the signal at a distance from the access signal generator and to apply a tracking signal to other discrete re-writable non-volatile two-terminal resistive memory elements associated with others of the subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal; and a line monitor electrically coupled with the word line and configured to sample the modified magnitude of the signal, and to generate a monitoring signal responsive to the sampled magnitude of the signal, wherein the line monitor is coupled to provide the monitoring signal to the tracking signal generator for tracking the modified magnitude of the signal.