Patent ID: 9306446
Filing Date: 2016-04-05
CPC Classification: H02H,H02M

Claim Text:
1. A fault controller circuit comprising: an output node configured to deliver an output waveform for driving a switch; an input node configured to receive an input voltage and an input current; an under voltage lock out (UVLO) module coupled to the input node; an initial switching (IS) mode module configured to activate an initial switching mode and generate a first output waveform; a normal switching (NS) mode module coupled to the IS mode module and configured to activate a normal switching mode and generate a second output waveform; a first shut down (FSD) mode module coupled to the UVLO and the IS mode and the NS mode modules and configured to activate a first shut down mode, wherein the FSD mode module is enabled when the UVLO module receives a voltage below a first threshold voltage (V a second shut down (SSD) mode module coupled to the IS mode and the NS mode modules and configured to activate a second shut down mode; a fault detection module coupled to the SSD mode module and configured to receive fault events; and a gate driver (DR) module coupled to the output node and the IS and the NS mode modules and configured to receive the first output waveform or the second output waveform and to deliver the received output waveform at the output node, wherein the circuit transitions from the IS mode or the NS mode to the SSD mode and enables the SSD mode module when a fault event by the fault detection module is received, the second shut down mode including: disabling the IS and NS mode modules, disabling the output waveform of the circuit and driving a second shut down mode current (I 2 ) from the input node of the circuit, wherein I 2 is greater than I 1 .