Patent ID: 9431417
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor structure, comprising: forming a plurality of stacks on a substrate; forming a conformal memory layer over the stacks; forming a conformal channel layer over the conformal memory layer; forming a spacer layer on the conformal channel layer; and separating the spacer layer, the conformal channel layer and the conformal memory layer so as to form a plurality of memory layers, a plurality of channel layers and a plurality of spacers, wherein the memory layers are respectively formed on sidewalls of the stacks, the channel layers are respectively formed on the memory layers, a surface of each of the channel layers is exposed, and the spacers are respectively formed on the channel layers and expose the surface of each of the channel layers; and forming a plurality of connecting portions connecting the surface of each of the channel layers to the substrate, respectively, wherein the connecting portions are selective epitaxial growing layers.