Patent ID: 9466575
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a silicon substrate; a first interlayer insulating film having a specific dielectric constant of 3 or less formed over the silicon substrate; a second interlayer insulating film having a specific dielectric constant of 3 or less formed on the first interlayer insulating film; a passivation film formed over the second interlayer insulating film; a seal ring formed within said first interlayer insulating film and the second interlayer insulating film so as to surround a circuit formation region of a semiconductor chip; and a dummy pattern which includes a first single dummy metal formed within said first interlayer insulating film, a second single dummy metal formed within said second interlayer insulating film, and a plurality of dummy vias formed within the second interlayer insulating film, each of the dummy vias connecting the first single dummy metal and the second single dummy metal in a dicing region of said semiconductor chip such that a plurality of dummy vias connect the first single dummy metal and the second single dummy metal, the seal ring contacts both the silicon substrate and the passivation film.