Patent ID: 9418011
Filing Date: 2016-08-16
CPC Classification: G06F

Claim Text:
1. A processor comprising: a cache; a first core coupled to the cache to execute a page tracker buffer handler; and a page tracker buffer (PTB) having a plurality of entries, each to store an address of a page of a memory, an access signature to indicate lines of the page that were accessed by the first core in a prior access to the page, and a reuse signature to indicate lines of the page that were accessed at least twice by the first core in the prior access, wherein the page tracker buffer handler, responsive to a miss in a translation lookaside buffer (TLB) for a first page, is to load a first entry into the PTB, prefetch one or more lines of the first page according to the reuse signature of the first entry, and cause a first line of the first page to remain in the cache according to a replacement policy responsive to identification of the first line as having been accessed at least twice by the first core in the reuse signature of the first entry, wherein the first entry corresponds to the first page.