Patent ID: 9281315
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a memory structure, comprising: forming a plurality of stacks on a substrate, wherein the stacks are separated from each other by a plurality of trenches, and each of the stacks comprises alternately stacked conductive stripes and insulating stripes; forming a plurality of memory layers conformally covering the stacks respectively; forming a conductive material in the trenches and on the stacks, the conductive material having a top portion; forming one or more holes in the conductive material in each of the trenches; and defining a plurality of predetermined regions for respectively forming a plurality of conductive lines in the top portion of the conductive material, wherein each of the predetermined regions comprises a first predetermined region and a second predetermined region connected to each other, the first predetermined region extends along a direction perpendicular to an extending direction of the stacks, and the second predetermined region extends along the extending direction of the stacks.