Patent ID: 9299436
Filing Date: 2016-03-29
CPC Classification: G11C

Claim Text:
1. A semiconductor memory system comprising: a first nonvolatile memory chip; and a second nonvolatile memory chip; wherein each of the first nonvolatile memory chip and the second nonvolatile memory chip comprises a plurality of I/O pads, the plurality of I/O pads of the first nonvolatile memory chip are respectively connected to corresponding I/O pads of the second nonvolatile memory chip, at least one of the plurality of I/O pads outputs a busy signal in response to a first input command; and wherein an initialization operation is performed in the first nonvolatile memory chip and the second nonvolatile memory chip, the busy signal is set to a first voltage corresponding to a first busy state as long as the initialization operation is performed in at least one of the first nonvolatile memory chip and the second nonvolatile memory chip, the busy signal is set to a second voltage corresponding to a second busy state after the initialization operation is completed in both the first nonvolatile memory chip and the second nonvolatile memory chip, the first busy state is different from the second busy state, and the first voltage is different from the second voltage.