Patent ID: 9419736
Filing Date: 2016-08-16
CPC Classification: H03K,H04J,H04L

Claim Text:
1. A transmitter comprising: a main multiplexer configured to generate a main data signal by multiplexing parallel signals and to output the main data signal, when two neighboring quarter phase clock signals among multiphase clock signals overlap, wherein the main multiplexer comprises a plurality of cascaded N-channel metal oxide semiconductor (NMOS) transistors and adjustable pseudo P-channel metal oxide semiconductor (pseudo-PMOS) loads and the cascaded NMOS transistors are driven by differential input data and the two neighboring quarter phase clock signals; a secondary multiplexer configured to generate a post data signal by multiplexing the parallel signals and to output the post data signal when the two neighboring quarter phase clock signals overlap; and a main driver and a post driver configured and arranged for receiving the main data signal and the post data signal, respectively, wherein an output of the main driver associated with an input DIN[n] of the main driver is connected with an output of the post driver associated with a differential input /DIN[n−1] of the post driver to generate a first output /OUT, and an output of the main driver associated with an input /DIN[n] of the main driver is connected with an output of the post driver associated with a differential input DIN[n−1] of the post driver to generate a second output OUT, wherein a pre-emphasized output signal is generated by summing the first output /OUT and the second output OUT.