Patent ID: 9324789
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A memory device, comprising: a plurality of stack structures, located on a substrate, wherein the stack structures are arranged along a first direction and extend along a second direction, and each of the stack structures comprises a plurality of first conductive layers and a plurality of dielectric layers that are alternately stacked along a third direction; a plurality of conductive pillars, wherein each of the conductive pillars is located on the substrate between two adjacent stack structures; a plurality of charge storage layers, wherein each of the charge storage layers is located between the stack structures and the conductive pillars; and a plurality of third conductive layers, wherein each of the third conductive layers extends along the first direction, overlaps the stack structures at a plurality of overlapped regions, and covers a portion of top parts of the stack structures and the conductive pillars, wherein each of the overlapped regions where the stack structures and the third conductive layers overlap has an air gap, and the air gap extends along the third direction.