Patent ID: 9318196
Filing Date: 2016-04-19
CPC Classification: G11C

Claim Text:
1. A non-volatile semiconductor memory device comprising a non-volatile static random access memory (SRAM) memory cell including an SRAM including a first load transistor and a first drive transistor having their respective one ends connected to each other, a first storage node being provided between the first load transistor and the first drive transistor, a second load transistor and a second drive transistor having their respective one ends connected to each other, a second storage node being provided between the second load transistor and the second drive transistor, a power supply line being connected to respective other ends of the first load transistor and the second load transistor, and a reference voltage line being connected to respective other ends of the first drive transistor and the second drive transistor, and a non-volatile memory unit including a first memory cell having a first memory transistor and a first switch transistor connected in series with the first memory transistor in which a voltage is applied to one end of the first switch transistor from one of the first storage node and the second storage node and a second memory cell having a second memory transistor and a second switch transistor connected in series with the second memory transistor in which a voltage is applied to one end of the second switch transistor from the other one of the second storage node and the first storage node, the SRAM further including a first access transistor having one end connected to respective gates of the second load transistor and the second drive transistor and the first storage node, the other end connected to a complementary first bit line, and a gate connected to a word line, and a second access transistor having one end connected to respective gates of the first load transistor and the first drive transistor and the second storage node, the other end connected to a complementary second bit line, and a gate connected to the word line, and a thickness of a gate insulating film of each of the first access transistor, the second access transistor, the first load transistor, the second load transistor, the first drive transistor, and the second drive transistor is set to 4 [nm] or less.