Patent ID: 9291673
Filing Date: 2016-03-22
CPC Classification: G01R

Claim Text:
1. A semiconductor apparatus comprising: an output timing test unit configured to receive an output data applied from an input/output pad at a first time according to an edge triggering method and output the output data as output timing test data, during an output timing test mode; and a test output unit configured to receive the output timing test data and output the output timing test data to a probe pad, wherein the output timing test unit comprises: a reference clock generator configured to generate a reference clock signal having an activated pulse width at the first time; a delay amount controller configured to control a delay amount of the reference clock signal in response to a delay amount select signal and generate the delayed reference clock signal; and a data detector configured to output the output data in synchronization with the delayed reference clock signal and output the output data as the output timing test data.