Patent ID: 9299638
Filing Date: 2016-03-29
CPC Classification: B82Y,H01L

Claim Text:
1. A method for fabricating one or more conductive lines in an integrated circuit, the method comprising: providing a layer of a semiconductor material; providing a layer of a transition metal upon the layer of semiconductor material, wherein the layer of the transition metal comprises a non-copper transition metal; patterning the layer of the transition metal to form the one or more conductive lines, wherein the layer of the transition metal forms a non-switchable conduit for conducting a majority of an electrical current between devices in the integrated circuit, and wherein the one or more conductive lines have sub-eighty nanometer line widths; and depositing a protective cap on at least some of the one or more conductive lines, wherein the protective cap is deposited to a thickness that reduces a resistivity of the at least some of the one or more conductive lines to within a range of thirty-two to four hundred micro ohm-centimeters.