Patent ID: 9524780
Filing Date: 2016-12-20
CPC Classification: B41J,G11C,H01L

Claim Text:
1. An EPROM memory cell suitable for an EEPROM array, the EPROM memory cell comprising: a drain including a top and a bottom, wherein the drain is formed of an N+ doped region; a channel that surround the drain and includes a first rounded closed curve structure around an entire surface area of the drain including a surface area of the bottom of the drain, wherein the channel is formed of a P doped region, wherein the first rounded closed curve structure increases uniformity of the length of the channel throughout the width of the channel relative to a rectangular channel; a control gate situated over the channel; and a floating gate capacitively coupled to the control gate, wherein the floating gate is situated over the channel and includes a second rounded closed curve structure over the channel to form the EPROM memory cell.