Patent ID: 9401412
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A method of fabricating a diode comprising a plurality of regions of a first conductivity type in a semiconductor substrate, the method comprising: forming a buried region of a second conductivity type in the semiconductor substrate; performing a first dopant implantation procedure to form an intermediate region of the plurality of regions; and performing a second dopant implantation procedure in addition to the first dopant implantation procedure to form a contact region of the plurality of regions; wherein the first and second dopant implantation procedures are configured such that the intermediate region is electrically connected with the contact region; wherein the first and second dopant implantation procedures are configured such that the buried region extends laterally across the contact region and the intermediate region to establish first and second junctions of the diode, respectively, and such that the first junction has a lower breakdown voltage than the second junction.