Patent ID: 9318582
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: etching a semiconductor substrate to form a plurality of fin structures, each of the plurality of the fin structures having a dielectric fin cap atop the fin structure; forming a sacrificial gate structure over the dielectric fin caps; forming a gate spacer on each sidewall of the sacrificial gate structure; forming a dielectric fin cap portion by removing portions of each of the dielectric fin caps that are not covered by the sacrificial gate structure or the gate spacer; laterally etching each of the dielectric fin cap portions to provide an undercut region underneath each gate spacer; forming a dielectric liner portion within each of the undercut regions; forming an epitaxial source region and an epitaxial drain region on portions of the fin structures that are not covered by the sacrificial gate structure, the gate spacers and the dielectric liner portions; removing the sacrificial gate structure to expose remaining portions of the dielectric fin cap portions; and removing the remaining portions of the dielectric fin cap portions to form a gate cavity, wherein the dielectric liner portions remain in the undercut regions during said forming the epitaxial source region and the epitaxial drain region.