Patent ID: 9519583
Filing Date: 2016-12-13
CPC Classification: G06F,G11C

Claim Text:
1. A computer system, the computer system comprising: a first processor comprising hardware; a first main memory associated with the first processor; a first L1 cache associated with the first processor; a first L2 cache associated with the first processor; a second processor comprising hardware; a second main memory associated with the second processor; a second L1 cache associated with the second processor; a second L2 cache associated with the second processor; and a dedicated memory structure for holding data indicating a plurality of available worker threads, the dedicated memory structure being distinct from each of the first main memory, the first L1 cache, the first L2 cache, the second main memory, the second L1 cache and the second L2 cache; wherein the first processor is configured to access, in the dedicated memory structure, the data, wherein the first processor is configured to detect from the data at least one first available worker thread, and wherein the first processor is configured to inform the detected at least one first available worker thread of at least one first task to execute and wherein the second processor is configured to access, in the dedicated memory structure, the data, wherein the second processor is configured to detect from the data at least one second available worker thread, and wherein the second processor is configured to inform the detected at least one second available worker thread of at least one second task to execute.