Patent ID: 9270228
Filing Date: 2016-02-23
CPC Classification: G03F,G06F,H01L,H03B,H03K

Claim Text:
1. Wafer masks for laying out a semiconductor device, comprising: a first pattern for laying out a first plurality of clocked devices on a semiconductor wafer; a second pattern for laying out a second plurality of clocked devices on a semiconductor wafer; and a third pattern for laying out a clock distribution system on a semiconductor wafer, the clock distribution network having a first clock buffer driving a first clock tree with a first plurality of conductors that are connected to the first plurality of clocked devices, a first LC network adjacent a first clocked device of the first plurality of clocked devices, and a second LC network adjacent a second clocked device of the first plurality of clocked devices, the clock distribution network further including a second clock buffer driving a second clock tree with a second plurality of second conductors connected to a second plurality of clocked devices and a third LC network adjacent a first clocked device of the second plurality of clocked devices; wherein the third pattern is for producing an unsymmetrical first clock tree; wherein the third pattern is for producing a first clock tree and an asymmetrical second clock tree; wherein the third pattern is for producing a resonant first LC network; wherein the third pattern is for producing a resonant second LC network; and wherein the third pattern is for producing a resonant third LC network.