Patent ID: 9263446
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method of forming replacement gate structures for first and second transistor devices that are formed in and above adjacent first and second active regions, respectively, that are separated by an isolation region, said first and second transistor devices comprising a shared gate structure, wherein the method comprises: performing at least one etching process to remove a sacrificial gate structure for said first and second transistor devices to thereby define a shared gate cavity that spans across said isolation region and is positioned above said first and second active regions; forming at least one layer of material in said shared gate cavity above said first and second active regions and above said isolation region; forming a first masking layer that covers portions of said shared gate cavity positioned above said first and second active regions while exposing a portion of said shared gate cavity positioned above said isolation region; with said first masking layer in position, performing at least one first etching process to remove at least a portion of said at least one layer of material in the exposed portion of said shared gate cavity above said isolation region; and removing said first masking layer.