Patent ID: 9299813
Filing Date: 2016-03-29
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: a bit line; a source line; a word line; and a memory cell comprising a first transistor and a second transistor, wherein the first transistor is a p-channel transistor, wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising crystalline silicon, wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including a second channel formation region, wherein the first gate is electrically connected to one of the second source and the second drain, wherein one of the first source and the first drain and the other of the second source and the second drain are electrically connected to the bit line, wherein the other of the first source and the first drain is electrically connected to the source line, and wherein the second gate is electrically connected to the word line.