Patent ID: 9343543
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device comprising: providing a semiconductor structure; providing a first dielectric layer on the semiconductor structure; providing a second dielectric layer on the first dielectric layer opposite the semiconductor structure; forming a first opening in the first and second dielectric layers to expose an area of the semiconductor structure and thereby provide an exposed area of the semiconductor structure; forming spacers adjacent to sidewalls of the first opening in the first and second dielectric layers, the spacers defining a second opening between the spacers that has a length that is substantially less than a length of the first opening; providing a gate contact within the second opening such that a proximal end of the gate contact is on a portion of the exposed area of the semiconductor structure that is exposed by the second opening; and removing the spacers and the second dielectric layer such that, for each sidewall of the gate contact, an air region separates the sidewall of the gate contact from the first dielectric layer.