Patent ID: 9270265
Filing Date: 2016-02-23
CPC Classification: H03K

Claim Text:
1. A power on reset circuit comprising: a startup circuit configured to keep an operation signal in an operating state in a predetermined period of time during which a power supply rises, configured not to affect the operation signal after the predetermined period of time ends, and configured not to cause a constant current to flow; a bias circuit configured to start an operation of itself when the operation signal enters an operating state in the predetermined period of time, and configured to keep the operation signal in the operating state after starting the operation; a BGR circuit configured to be activated when the operation signal enters the operating state, and configured to output a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit configured to generate a divided voltage of a power supply voltage and to output the divided voltage as a reference voltage; an activation detection circuit configured to generate a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage output by the BGR circuit reaches a predetermined level; a comparator circuit configured to activate when the control signal becomes active, configured to compare the fixed voltage output by the BGR circuit with the reference voltage and to output a power on signal, and configured to detect as the power on signal in the case where the reference voltage is greater than the fixed voltage; and a switch configured to turn on and fix an output of the comparator circuit to an inactive logical value while the control signal is inactive, and configured to turn off and not to affect the power on signal output from the comparator circuit while the control signal is active.