Patent ID: 9385128
Filing Date: 2016-07-05
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: a first line; a second line; a third line; and a first transistor and a second transistor each including a first gate, a second gate, a source, a drain, and a semiconductor layer, wherein the semiconductor layer of the first transistor is positioned between the first gate of the first transistor and the second gate of the first transistor, wherein the semiconductor layer of the second transistor is positioned between the first gate of the second transistor and the second gate of the second transistor, wherein the first gate of the first transistor is electrically connected to the first line, wherein the second gate of the first transistor is electrically connected to the second line, wherein one of the source and the drain of the first transistor is electrically connected to the third line, wherein one of the source and the drain of the second transistor is electrically connected to the third line, and wherein the other of the source and the drain of the first transistor is electrically connected to the second gate of the second transistor.