Patent ID: 9239782
Filing Date: 2016-01-19
CPC Classification: G06F,G11C

Claim Text:
1. A nonvolatile memory device, comprising: a nonvolatile memory including a plurality of wordlines; and a controller configured to control the nonvolatile memory, wherein the controller controls the nonvolatile memory such that an LSB program operation on a first wordline of the plurality of wordlines is performed and then an LSB program operation on a second wordline of the plurality of wordline is performed; and wherein while the LSB program operation on the second wordline is performed, the nonvolatile memory stores information about LSB data programmed at the first wordline in spare memory cells on the second wordline in a spare area of the nonvolatile memory, wherein the information indicates the LSB data is invalid when the LSB data programmed at the first word line is invalid, and wherein if a power-off occurred during a MSB program operation on the first word line, the controller controls the nonvolatile memory to skip a LSB recovery operation on the LSB data stored at the first wordline when the information indicates the LSB data programmed at the first wordline is invalid.