Patent ID: 9438243
Filing Date: 2016-09-06
CPC Classification: H03K

Claim Text:
1. A programmable logic circuit comprising: a plurality of first wiring lines; a plurality of second wiring lines intersecting with the first wiring lines in intersecting areas; a plurality of cells disposed in the intersecting areas, at least one of the cells including a programmable device with a first terminal and a second terminal, the first terminal of the programmable device being connected to one of the first wiring lines, and the second terminal being connected to one of the second wiring lines; a plurality of first cut-off transistors each including a source and a drain, one of the source and the drain being connected to the one of the second wiring lines; and a plurality of first CMOS inverters each corresponding to one of the first cut-off transistors, each of the first CMOS inverters including an input terminal, the input terminal being connected to the other of the source and the drain of the corresponding one of the first cut-off transistors, wherein at most one of the programmable devices connected to one of the second wiring lines is programmed.