Patent ID: 9343355
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a wiring structure, comprising: forming a first conductive pattern on a substrate; forming a hardmask on the first conductive pattern; forming a first spacer on sidewalls of the first conductive pattern and the hardmask, the first spacer having a top surface substantially higher than a top surface of the first conductive pattern; forming a first sacrificial layer pattern on a sidewall of the first spacer; performing a first anisotropic etching process on the first sacrificial layer to expose an upper surface of the substrate; forming a second sacrificial layer on the first sacrificial layer and the upper surface of the substrate; partially removing upper portions of the first sacrificial layer and the second sacrificial layer to form a first sacrificial layer pattern and a second sacrificial layer pattern, respectively; removing the second sacrificial layer pattern to expose the upper surface of the substrate; forming, by performing a second anisotropic etching process, a second spacer on a sidewall of the first sacrificial layer pattern, while exposing the upper surface of the substrate, the second spacer having a top surface substantially lower than the top surface of the first spacer; removing the first sacrificial layer pattern; and forming a third spacer on the second spacer, the third spacer contacting an upper portion of the sidewall of the first spacer and defining an air gap in association with the first and second spacers.