Patent ID: 9263555
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a plurality of trenches in a semiconductor substrate so as to define a fin; performing a plurality of epitaxial deposition processes to form first, second and third layers of epi semiconductor material around an exposed portion of said fin; performing at least one process operation to remove said first, second and third layers of epi semiconductor material from above an upper surface of said fin so as to thereby expose said fin; performing an etching process to selectively remove said fin relative to said first, second and third layers of epi semiconductor material so as to thereby define two fin structures comprised of said first, second and third layers of epi semiconductor material; and forming a gate structure around a portion of at least one of said fin structures comprised of said first, second and third layers of epi semiconductor material.