Patent ID: 9337213
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed over the gate electrode; an oxide layer which is formed on the gate insulating layer and which includes a first semiconductor region and a first conductor region, wherein the first semiconductor region overlaps at least partially with the gate electrode with the gate insulating layer interposed between them; a source electrode formed to contact with the upper surface of the first semiconductor region of the oxide layer; a drain electrode which is formed to contact with the upper surface of the first semiconductor region of the oxide layer and which is electrically connected to the first conductor region; and a conductive layer which is formed to contact with the upper surface of the oxide layer and which has a plurality of holes or notches, wherein the oxide layer includes a plurality of second conductor regions, and each of which has an upper surface exposed inside respective one of the plurality of holes or notches of the conductive layer; the conductive layer includes a line, and the line includes at least some of the plurality of holes or notches; and the semiconductor device further includes an insulating layer covering the conductive layer such that, in the at least some of the plurality of holes or notches of the line, at least some of the plurality of second conductor regions are in direct contact with the insulating layer.