Patent ID: 9419103
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method comprising: fabricating a field-effect transistor, the fabricating comprising: providing a gate structure disposed over a substrate; and forming a source and drain region within the substrate separated by a channel region, the channel region underlying, at least partially, the gate structure, and the forming comprising implanting at least one dopant at a pre-selected temperature into the source and drain region to facilitate increasing a concentration of the at least one dopant within the source and drain region, wherein the implanting of the at least one dopant at the pre-selected temperature facilitates reducing contact resistance of the source and drain region and increasing charge carrier mobility through the channel region; exposing the channel region below the gate structure and implanting the at least one dopant at the pre-selected temperature into the exposed channel region to facilitate modulating an intrinsic stress disposed within the exposed channel region; wherein the at least one dopant comprises a first dopant of a first conductivity type, and the forming further comprises forming an epitaxially grown source and drain region having the first dopant of a first conductivity type disposed therein, and the fabricating further comprises, subsequent to the forming, implanting a second dopant of a second conductivity type at the pre-selected temperature into an upper surface of the epitaxially grown source and drain region.