Patent ID: 9304854
Filing Date: 2016-04-05
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor device comprising: a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred, wherein the second memory device is configured to store an error address where the multi-bit error occurred at the first memory device prior to receiving the request and a normal data corresponding to the error address, wherein the controller processes the request for the first memory device when a single-bit error has occurred at the requested address of the first memory device, and registers multi-bit error occurrence information corresponding to the request address when a multi-bit error exists in data outputted from the first memory device, and wherein the second memory device is configured to store single-bit error occurrence information, and the controller removes soft error information in the single-bit error occurrence information stored in the second memory device.