Patent ID: 9437694
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A process, comprising: forming a gate stack on top of a semiconductor layer, said gate stack including a gate dielectric and a gate electrode; forming a sacrificial sidewall spacer on each side of the gate stack; epitaxially growing raised source-drain regions on each side of the gate stack adjacent the sacrificial sidewall spacers; removing the sacrificial sidewall spacers to produce openings between each raised source-drain region and the gate stack; and filling the openings with a dielectric material having a dielectric constant k<5, wherein the dielectric material having the dielectric constant k<5 is selected from the group consisting of: a silicon oxycarbonitride (SiOCN) material, a silicon carbon oxide (SiCO) material, a silicon carbon nitride (SiCN) and a silicon boron carbon nitride (SiBCN) material.