Patent ID: 9437693
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A transistor comprising: a surface region; a gate disposed on the surface region, the gate having a first sidewall and a second sidewall, wherein the first sidewall aligns with a source side boundary that defines a source side of the surface region, and the second sidewall aligns with a drain side boundary that defines a drain side of the surface region, wherein the source and drain side boundaries define lateral boundaries for a channel region within the surface region underlying the gate; a drain dopant region disposed within the surface region on the drain side; a drift dopant region disposed within the surface region between the drain side boundary and the drain dopant region; a set of electrically conductive shield plates that includes at least a first shield plate overlying a portion of the drift dopant region; and a shield plate dopant region disposed within the drift dopant region and underlying the set of shield plates.