Patent ID: 9263440
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A power transistor arrangement, comprising: a carrier comprising at least a main region and a first terminal region and a second terminal region, the main region, the first terminal region and the second terminal region being electrically isolated from each other; a first power transistor having a control electrode and a first power electrode and a second power electrode, the first power transistor being arranged over the main region of the carrier such that the first power electrode of the first power transistor is facing towards the main region of the carrier and is electrically coupled to the main region of the carrier; a second power transistor having a control electrode and a first power electrode and a second power electrode, the second power transistor being arranged over the first terminal region and the second terminal region such that the control electrode of the second power transistor and the first power electrode of the second power transistor are facing towards the terminal regions of the carrier, wherein the control electrode of the second power transistor is electrically coupled to the first terminal region of the carrier, and wherein the first power electrode of the second power transistor is electrically coupled to the second terminal region of the carrier; wherein the control electrode of the first power transistor is electrically coupled to one of the first terminal region and the second terminal region; and wherein the second power electrode of the first power transistor and the second power electrode of the second power transistor are electrically coupled with each other.