Patent ID: 9405880
Filing Date: 2016-08-02
CPC Classification: G06F

Claim Text:
1. A method of forming a semiconductor arrangement comprising: determining a first delay for a first buffer in an interconnection arrangement, where the interconnection arrangement comprises a first connection between a driver and a receiver and the first buffer is disposed along the first connection between the driver and the receiver; determining a second delay for a second buffer in the interconnection arrangement, where the second buffer is disposed along the first connection between the driver and the receiver; determining a first score for the first buffer based upon the first delay; determining a second score for the second buffer based upon the second delay; selecting the first buffer to be a first selected buffer based upon the first score or selecting the second buffer to be the first selected buffer based upon the second score; rerouting the interconnection arrangement such that the driver is connected to the receiver by a second connection that bypasses the first selected buffer; at least one of: at least one of: