Patent ID: 9288099
Filing Date: 2016-03-15
CPC Classification: H03F,H04B,H04L

Claim Text:
1. A predistortion circuit for countering interference affecting a digital signal during transmission over a transmission link between a mapper at a transmitter side and a demapper at a receiver side, wherein the predistortion circuit is arranged for receiving a digital symbol selected from a predefined constellation used for mapping a bit stream, and comprises at least one correction stage arranged for: determining an output value of a transmission link model receiving an input symbol, which is the selected digital symbol for a first correction stage and an output of a previous correction stage for any following correction stage; determining a correction term as a function of said output value and a target constellation symbol; wherein the predistortion circuit further comprises an adder after each correction stage arranged for adding said correction term to said digital symbol received by that correction stage and for outputting to a following correction stage or to an output of the predistortion circuit in case the correction stage is a last one, a result of said adding as an updated version of said digital symbol, and wherein said target constellation symbol is a symbol of the target constellation corresponding to said digital symbol, said target constellation being derived from said predefined constellation and said transmission link model and having a position of the target constellation points determined by calculating a mass point for groups of output values of said transmission link model, each output value of a same group corresponding to a same digital symbol of said predefined constellation.