Patent ID: 9424953
Filing Date: 2016-08-23
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor memory device, comprising: a first data bus; a second data bus being independent from the first data bus, the number of lines of the first data bus being different from that of the second data bus; and a data transfer unit to transfer data by connecting the first data bus with bit lines, the number of which is equal to the number of lines of the first data bus, from among a plurality of bit lines when data is transferred to/from memory cells during a first operation mode and transfers data by connecting the second data bus with bit lines, the number of which is equal to the number of lines of the second data bus, from among the plurality of bit lines when data is transferred to/from memory cells during a second operation mode, wherein the data transfer unit comprises: a first page buffer to latch data of a normal bit line connected to a normal memory cell; a second page buffer to latch data of a parity bit line connected to a parity memory cell; and a third page buffer that is replaced together with a normal memory cell and a normal bit line when a normal memory cell or a normal bit line connected to the first page buffer is defective, or is replaced together with a parity memory cell and a parity bit line when a parity memory cell or a parity bit line connected to the second page buffer is defective, wherein the first data bus is connected to the first, second, and third page buffers and the second data bus is connected to the first and third page buffers.