Patent ID: 9330035
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. A data processing device comprising: a plurality of system registers, comprising a set of interrupt handling registers for controlling handling of an incoming interrupt; processing circuitry configured to execute software at a plurality of execution levels, interrupt controller circuitry configured to route said incoming interrupt to interrupt handling software configured to run at one of said plurality of execution levels; register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon said one of said plurality of execution levels at which said interrupt handling software is configured to run, such that interrupt handling software configured to run at said execution level has access to said at least some of said interrupt handling registers for handling said incoming interrupt, and such that said interrupt handling software configured to run at said execution level does not have access to interrupt handling registers for handling a second incoming interrupt routed to an interrupt handling software run at a more privileged execution level.