Patent ID: 9343160
Filing Date: 2016-05-17
CPC Classification: G11C

Claim Text:
1. A non-volatile storage device comprising: a plurality of NAND strings having non-volatile storage elements; a plurality of bit lines, each of the NAND strings is associated with a bit line of the plurality of bit lines; and managing circuitry in communication with the plurality of NAND strings and the plurality of bit lines, the managing circuitry is configured to apply an erase signal to a group of the plurality of NAND strings, the managing circuitry is configured to sense the group of NAND strings at a strict reference level after applying the erase signal, the strict reference level is lower than a target reference level to which the group of the plurality of NAND strings are to be erased, the managing circuitry is configured to determine a first set of the group of NAND strings that were erased to the strict reference level and a second set of the NAND strings were not erased to the strict reference level, the managing circuitry is configured to apply first verify conditions to the first set of the NAND strings that prevents the first set of NAND strings from conducting a substantial current during an erase verify, the managing circuitry is configured to apply second verify conditions to the second set of the NAND strings that does not prevent the second set of NAND strings from conducting a current during the erase verify, the managing circuitry is configured to sense the second set of the NAND strings during the erase verify while the first set of NAND strings are prevented from conducting a current to determine which of the second set of NAND strings were erased to the target reference level.