Patent ID: 9490759
Filing Date: 2016-11-08
CPC Classification: H03F

Claim Text:
1. An apparatus, comprising: a first positive channel metal oxide semiconductor (PMOS) transistor having a source connected to a first node, a drain connected to a second node, and a gate connected to a third node; a second PMOS transistor having a source connected to the first node, a drain connected to a fourth node, and a gate connected to a fifth node; a first negative channel metal oxide semiconductor (NMOS) transistor having a source connected to a sixth node, a drain connected to the second node, and a gate connected to a seventh node; a second NMOS transistor having a source connected to the sixth node, a drain connected to the fourth node, and a gate connected to an eighth node; a first metal oxide semiconductor (MOS) differential neutralization device connected between the third node and the fourth node; a second MOS differential neutralization device connected between the fifth node and the second node; a third MOS differential neutralization device connected between the seventh node and the fourth node; and a fourth MOS differential neutralization device connected between the eighth node and the second node, wherein the first through fourth MOS differential neutralization devices comprise PMOS capacitors.