Patent ID: 9244766
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. An apparatus comprising: a memory comprising a plurality of solid-state non-volatile memory cells; and a processing circuit connected to the memory and configured to direct execution of a plurality of read error recovery routines responsive to at least one uncorrectable read error in a data set retrieved from the memory, the recovery routines executed in a selected order based on an elapsed recovery time parameter for each the recovery routines and an estimated probability of success for each of the recovery routines, the processing circuit further configured to generate and store in a local memory a correction table that lists the plurality of read error recovery routines in the selected order, the processing circuit further configured to measure an elapsed time interval during which each of the read error recovery routines is executed and to record, in the local memory, an indication value indicating whether said execution was successful in correcting the at least one uncorrectable read error.