Patent ID: 9489258
Filing Date: 2016-11-08
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A DRAM Translation Layer (DTL) driver method to buffer accesses to a flash memory device comprising: controlling access to the flash memory device and to a dynamic-random-access memory (DRAM) buffer in response to IO request packets that indicate host reads and host writes, the IO request packets received by a file system filter; wherein the flash memory device is block-erasable and page-writeable; using a driver to write host data to the DRAM buffer; creating a DTL in the DRAM buffer that is controlled by the driver and using the DTL to provide temporary storage to buffer flash accesses; creating mapping tables to manage data stored in the DTL; using the mapping tables to distribute data in the DRAM buffer to form a buffer of data for storage in a flash memory device; during a host write, sending a logical address from the host to a logical-to-DTL mapping table that looks up the logical address to locate a DTL entry for storing data having the logical address from the host; during a host read, using the logical-to-DTL mapping table and a DTL status table to read data from the DRAM buffer when valid data exists or to read data from the flash memory device when no valid data exists; and during a flush operation, using a DTL-to-Logical mapping table that stores a logical address of data stored at a DTL entry to locate valid data in the DRAM buffer.