Patent ID: 9530737
Filing Date: 2016-12-27
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device, comprising: forming a dielectric layer over a substrate; forming a first pattern and a second pattern in the first interlayer dielectric layer, the first pattern having a width greater than a width of the second pattern; forming a first metal layer in the first pattern and the second pattern; forming a second metal layer in the first pattern; and performing a planarization operation on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed, wherein: a metal material of the first metal layer is different from a metal material of the second metal layer, the first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer, and the metal material of the first metal layer includes at least one of Co, Ru and Ag.