Patent ID: 9384808
Filing Date: 2016-07-05
CPC Classification: G11C

Claim Text:
1. An address input circuit of a semiconductor device comprising: an address latch unit configured to generate latch addresses, by latching addresses according to different edges of a clock signal and selecting and latching one of latched signals according to an address input mode signal and a command decoding signal; and a command decoder configured to generate the command decoding signal by decoding a command provided from the external, wherein the address latch unit comprises: a first latch section configured to latch the addresses according to a first edge of a clock signal and generate a first latch signal; a second latch section configured to latch the addresses according to a second edge of the clock signal and generate a second latch signal; a third latch section configured to latch the first latch signal according to the first edge of the clock signal and generate a third latch signal; a fourth latch section configured to latch the first latch signal according to the second edge of the clock signal and generate a fourth latch signal; a first selection section configured to select one of the third latch signal and the fourth latch signal according to the address input mode signal and generate a first selection signal; a second selection section configured to select one of the first latch signal and the second latch signal according to the address input mode signal and generate a second selection signal; a fifth latch section configured to latch the first selection signal according to the command decoding signal and generate a first latch address; and a sixth latch section configured to latch the second selection signal according to the command decoding signal and generate a second latch address.