Patent ID: 9300316
Filing Date: 2016-03-29
CPC Classification: H03M

Claim Text:
1. A circuit comprising: a first input of a comparator for an analog to digital converter (ADC), the first input being coupled to a first capacitive network; and a second input of the comparator for the ADC, the second input being coupled to a second capacitive network, wherein: the first capacitive network includes a first set of capacitors, wherein a first plate of the first set of capacitors is selectively coupled to a single-ended input signal and a second plate of the first set of capacitors is selectively coupled to a direct current (DC) reference bias of the single-ended input signal, the second capacitive network includes a second set of capacitors, wherein a second plate of the second set of capacitors is selectively coupled to the single-ended input signal and a first plate of the second set of capacitors is selectively coupled to the DC reference bias of the single-ended input signal, and the first plate of the first set of capacitors and the first plate of the second set of capacitors are opposite plates from the second plate of the first set of capacitors and the second plate of the second set of capacitors.