Patent ID: 9281274
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A method of manufacturing an integrated circuit substrate via system comprising: providing a substrate having a substrate via in the substrate, the substrate via has a top surface and a bottom surface exposed from the substrate; patterning a photoresist layer over the substrate; patterning a buffer layer over the substrate via in the photoresist layer, the buffer layer has a planar surface; patterning a substrate via cap over the buffer layer in the photoresist layer, the substrate via cap has a planar surface based on the planar surface of the buffer layer; removing the photoresist layer; and patterning the substrate via cap and patterning the buffer layer include reducing a thickness of an adhesive layer of the substrate via cap to increase conductivity of the substrate via cap to compensate for increased resistivity of the buffer layer.