Patent ID: 9471713
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A method for handling regular expression patterns, comprising: scanning by a finite state machine, an input stream; accessing by a result processor, a result table for an entry associated with a predetermined sub-expression of a regular expression in response to the finite state machine finding the predetermined sub-expression in the input stream; executing by the result processor an instruction associated with the entry of the result table, the instruction comprising an operation to be performed on one or more bits in a bit vector register, the operation comprising setting a bit or testing the bit in the bit vector register, the bit vector register created to test conditions related to an order in which the sub-expression is detected, the bit vector register operated on based on the instruction by setting a bit position in the bit vector to a value or by testing whether the bit position in the bit vector register is set to the value; and determining as a function of said one or more bits in the bit vector register whether the regular expression has been found in the input stream, wherein responsive to determining as a result of the testing that the bit position in the bit vector register is set to the value, determining that the regular expression with a desired order of the sub-expression has been found, wherein the result processor comprises the result table, an instruction execution logic and the bit vector register.