Patent ID: 9397646
Filing Date: 2016-07-19
CPC Classification: G11C,H03K

Claim Text:
1. A delay circuit, comprising: a first delay path having an input coupled to an input of the delay circuit, and an output wherein the first delay path comprises a first plurality of delay gates coupled in series; a second delay path having an input coupled to the input of the delay circuit, and an output, wherein the second delay path comprises a second plurality of delay gates coupled in series; a plurality of switches, wherein each switch is coupled between an output of a different one of the first plurality of delay gates and an output of a different one of the second plurality of delay gates, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals; and a multiplexer having a first input coupled to the output of the first delay path, a second input coupled to the output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.