Patent ID: 9450615
Filing Date: 2016-09-20
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A processor apparatus for performing multi-bit error correction based on a BCH code, comprising: a syndrome value generation module adapted for shifting each bit of the BCH code on which error correction is to be performed rightward by 1 bit while filling a bit vacated due to the rightward shifting in the BCH code with 0, and calculating syndrome values corresponding to the shifting of the BCH code; a modified syndrome value generation module in communication with the syndrome value generation module, wherein the modified syndrome value generation module is adapted for, corresponding to each rightward one bit shifting of the BCH code on which error correction is to be performed, calculating modified syndrome values corresponding to the shifting of the BCH code, wherein the modified syndrome values are those corresponding to a case that the current rightmost bit of the BCH code under the shifting is changed to an inverse value; and an error number determination module in communication with the modified syndrome value generation module, wherein the error number determination module is adapted for, corresponding to each rightward one bit shifting of the BCH code on which error correction is to be performed, determining a first error number in the BCH code under the shifting based on the syndrome values calculated by the syndrome value generation module, and determining a second error number in the BCH code under the shifting based on the modified syndrome values calculated by the modified syndrome value generation module.