Patent ID: 9349480
Filing Date: 2016-05-24
CPC Classification: G11C

Claim Text:
1. A device comprising: a memory array including a plurality of memory cells; an erase pulse circuit configured to supply the memory array with a first erase pulse in response to a first control information and with a second erase pulse in response to a second control information, the second erase pulse being higher in voltage level than the first erase pulse; and a control circuit configured to produce the first control information a first number of plural and programmable times in total in order to bring each of the memory cells of the memory array into an erased state, the control circuit being further configured to produce the first control information at least one more time when at least one of the memory cells has not been brought into the erased state, the control circuit being further configured to produce the second control information when at least one of the memory cells has not still been brought into the erased state irrespective of having been supplied with the first erase pulse twice or more times, wherein the control circuit comprises a content addressable memory that is configured to store the first number and enable a change of the first number by using a fuse line in the content addressable memory.