Patent ID: 9344272
Filing Date: 2016-05-17
CPC Classification: H03L,H04L

Claim Text:
1. An apparatus comprising: a first clock and data recovery circuit having an input and an output, wherein the input is coupled to an input node, wherein the first clock and data recovery circuit has a first phase detector with at least one of an adjustable offset or an adjustable gain; a second clock and data recovery circuit having an input and an output, wherein the input is coupled to the input node, wherein the second clock and data recovery circuit has a second phase detector with at least one of an adjustable offset or an adjustable gain; and a control circuit communicatively coupled to each of the first clock and data recovery circuit and the second clock and data recovery circuit for control of at least one or the offset or the gain settings of phase detectors of the clock and data recovery circuits, wherein the control circuit is coupled to at least the output of the second clock and data recovery circuit; wherein the output of the first clock and data recovery circuit is at least temporarily configured to provide recovered data as an input to circuits other than the control circuit while at least one of the one or more configurable characteristics of the second clock and data recovery circuit is being adaptively adjusted by the control circuit, wherein the second clock and data recovery circuit is not configured to provide recovered data as an input to circuits that would use the recovered data other than the control circuit.