Patent ID: 9240241
Filing Date: 2016-01-19
CPC Classification: G11C

Claim Text:
1. A three-dimensional (3D) non-volatile memory device, comprising: a substrate; a plurality of alternating horizontal insulating layers and horizontal conductive layers above the substrate; a plurality of vertically oriented NAND strings above the substrate in a block, each NAND string comprising a plurality of non-volatile storage elements, each NAND string comprising a channel that extends vertically through the alternating insulating layers and conductive layers, the channel having a first end and a second end, wherein the block comprises pseudo blocks that each comprise at least one storage element of each of the NAND strings, wherein each of the NAND strings is a member of each of the pseudo blocks; and a control circuit in communication with the NAND strings, the control circuit is configured to erase the non-volatile storage elements in a selected pseudo block by applying an erase voltage to the first end of the channel of the NAND string, wherein a magnitude of the erase voltage depends on the location of the selected pseudo block with respect to the plurality of horizontal conductive layers.