Patent ID: 9361958
Filing Date: 2016-06-07
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a plurality of data pads; a plurality of data buffers each suitable for buffering a signal inputted through a first input node using a voltage inputted through a second input node, and outputting the buffered signal; and a calibration control unit suitable for generating a test signal in a calibration mode, adjusting the level of the test signal, receiving outputs of the plurality of data buffers while adjusting the level of the test signal, and adjusting offsets of the data buffers such that the logical values of the outputs of the data buffers transit when the test signal has a target level, wherein data of the corresponding data pad is inputted to the first input node, and a reference voltage is inputted to the second input node, and in the calibration mode, the test signal is inputted to the first input node, and a test voltage is applied to the second input node.