Patent ID: 9373697
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device, the method comprising: forming a sacrificial gate over a channel region on a semiconductor substrate; depositing a conformal dielectric layer covering the sacrificial gate and the semiconductor substrate; forming, using etching processes, the conformal dielectric layer into one or more spacers, wherein the one or more spacers are formed adjacent to sidewalls of the sacrificial gate; growing and forming a raised source region and a raised drain region on opposing sides of the sacrificial gate; depositing a second dielectric material layer covering the sacrificial gate, the one or more spacers, the source region, the drain region and the semiconductor substrate; forming one or more additional spacers, wherein the one or more additional spacers are formed adjacent to the previously formed one or more spacers using directional etching processes on the second dielectric material layer; subsequent to forming the one or more additional spacers, removing the one or more spacers and the one or more additional spacers using etching processes selective to the sacrificial gate, the source region and the drain region, thereby creating a void between the source region and the sacrificial gate and between the drain region and the sacrificial gate; and subsequent to removing the one or more spacers and the one or more additional spacers, depositing a second conformal layer of a third dielectric material, wherein the third dielectric material conforms in a uniform layer to the source region, the drain region and the sacrificial gate, and fills the void between the source region and the sacrificial gate, and the void between the drain region and the sacrificial gate.