Patent ID: 9270443
Filing Date: 2016-02-23
CPC Classification: H04L

Claim Text:
1. A transmission circuit for transmitting serial data with a superimposed clock signal, comprising: an encoder configured to scramble parallel data of information to be transmitted and apply a predetermined coding scheme to generate D symbols having a clock signal embedded therein, and also configured to output alternately a continuous predetermined number of the D symbols and one of K symbols, the K symbols being synchronization control codes for the scrambling; and a parallel-to-serial converter configured to convert the D symbols and the K symbols output from the encoder into serial data, wherein, for each period of the scrambling, the encoder outputs a plurality of the K symbols, each of which is allocated to one of a first code, a second code, and a second code, wherein the first code indicates a beginning of the period of the scrambling, wherein the second code is allocated at an equal interval among remaining ones of the K symbols other than that for the first code; and wherein the third code is allocated among remaining ones of the K symbols other than those for the first code and the second code.