Patent ID: 9437731
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: forming first and second pillars each vertically extending from a semiconductor substrate and each having a first conductivity type; forming a recess region by etching the semiconductor substrate between the first and the second pillars; forming a stress providing layer in the recess region; forming a gate insulating layer extending from over a sidewall of the first pillar, over the stress providing layer to over a sidewall of the second pillar; forming a source region in the semiconductor substrate, wherein the source region extends from under the first pillar, under the stress providing layer to under the second pillar by using an impurity having a second conductivity type opposite to the first conductivity type; forming a drain region in upper portions of the first and the second pillars using the impurity having the second conductivity type; forming a first gate electrode over the gate insulating layer to surround the first pillar; and forming a second gate electrode over the gate insulating layer to surround the second pillar.