Patent ID: 9373621
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. An analog integrated circuit comprising: an analog circuit cell array including a plurality of transistor cells arranged in an array, each of the transistor cells comprising: wherein the analog integrated circuit comprises a transistor pair arranged in a common centroid configuration by using 2*2 transistor cells located in a center area of the array in which the transistor cells are arranged, such that the first gate electrode and the second gate electrode of a given transistor cell in the 2*2 transistor cells are connected to the first gate electrode and the second gate electrode of another transistor cell arranged diagonally from the given transistor cell, and wherein the first gate electrode and the second gate electrode of a transistor of the transistor pair are connected to a common drain region of a transistor cell, of the plurality of transistor cells, located outside of the center area of the array, and wherein a first gate electrode, a second gate electrode, a first source region and a second source region of the transistor cell, of the plurality of transistor cells, located outside of the center area of the array, are connected together.