Patent ID: 9236416
Filing Date: 2016-01-12
CPC Classification: H01L

Claim Text:
1. Memory cell comprising: a thin film transistor comprising a semiconductor layer, a gate width, and a terminal; a plurality of resistive memory elements, each resistive memory element comprising an element width and two stable resistance states; and a plurality of conductive lines overlapping the terminal at a plurality of intersection regions and independently electrically coupled to the plurality of resistive memory elements at their first ends, wherein the plurality of resistive memory elements is jointly electrically coupled to the terminal at their second ends, and wherein the gate width is substantially larger than the element width, wherein the resistive memory element is a magnetoresistive element, wherein the magnetoresistive element comprises: a free ferromagnetic layer comprising a reversible magnetization direction; a pinned ferromagnetic layer comprising a fixed magnetization direction; and a tunnel barrier layer disposed between the free ferromagnetic layer and the pinned ferromagnetic layer, wherein the resistive memory element is a chalcogenide element and further comprising: a first electrode; a heater layer; a storage layer; and a second electrode, wherein the storage layer is disposed between the heater layer and the second electrode.