Patent ID: 9490362
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a planar semiconductor layer formed on a semiconductor substrate; first and second pillar-shaped semiconductor layers formed on the planar semiconductor layer; a first gate insulating film formed around the first pillar-shaped semiconductor layer; a first gate electrode having a laminated structure constituted by a metal film and a polysilicon film formed around the first gate insulating film; a second gate insulating film formed around the second pillar-shaped semiconductor layer; a second gate electrode having a laminated structure constituted by a metal film and a polysilicon film formed around the second gate insulating film; a gate line connected to the first and second gate electrodes; an oxide film formed between the gate line and the planar semiconductor layer and having a thickness larger than that of the gate insulating film; a first n-type diffusion layer formed in an upper portion of the first pillar-shaped semiconductor layer; a second n-type diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer and an upper portion of the planar semiconductor layer; a first p-type diffusion layer formed in an upper portion of the second pillar-shaped semiconductor layer; and a second p-type diffusion layer formed in a lower portion of the second pillar-shaped semiconductor layer and an upper portion of the planar semiconductor layer, wherein a thickness of the polysilicon film is smaller than a half of a distance between the first pillar-shaped semiconductor layer and the second pillar-shaped semiconductor layer, a height of an upper surface of the metal film is more than a height of an upper surface of the polysilicon film, and a height of an upper surface of the gate line is less than a height of upper surfaces of the first and second gate electrodes.