Patent ID: 9343178
Filing Date: 2016-05-17
CPC Classification: G09G,G11C,H03K

Claim Text:
1. A shift register comprising: a first input terminal configured to receive a first clock signal; a second input terminal configured to receive a second clock signal; a third input terminal configured to receive a third clock signal; a first input signal terminal configured to receive a first input signal; a second input signal terminal configured to receive a second input signal; a pull-up circuit coupled to a first node, the first input signal terminal and the second input signal terminal for pulling up a voltage level of the first node according to the first input signal, the second input signal, a first selective control signal, and a second selective control signal; a driving circuit coupled to the first input terminal, an output terminal of the shift register, and the first node for controlling an electrical connection between the first input terminal and the output terminal according to the voltage level of the first node; a stability pull-down control circuit comprising: a stability pull-down circuit coupled to the first node, the second node, the output terminal and the system voltage terminal for controlling an electrical connection between the first node and the output terminal and an electrical connection between the output terminal and the system voltage terminal according to a voltage level of the second node.