Patent ID: 9285778
Filing Date: 2016-03-15
CPC Classification: G04F,H03L,H03M

Claim Text:
1. A time to digital converter comprising: a phase-frequency detection circuit having a pair of inputs respectively receiving first and second signals, said phase-frequency detection circuit generating both an up and a down control signal at corresponding outputs thereof, one of said up and down control signals having a pulse width representing a time difference between leading edges of said first and second signals, one relative to the other; a capacitor digital to analog converter operatively coupled to the outputs of said phase-frequency detection circuit, said capacitor digital to analog converter having a pair of capacitor arrays each redistributing charge in correspondence to said pulse width of a corresponding one of said up and down control signals and sequentially switching selected capacitors of at least one of said pair of capacitor arrays to establish respective voltage output for each of said pair of capacitor arrays; a successive approximation logic and timing unit coupled to said capacitor digital to analog converter for controlling the sequential switching of said selected capacitors, said successive approximation logic and timing unit including a successive approximation register; and a comparator unit operatively coupled to said pair of capacitor arrays for comparing voltage outputs thereof and operatively coupled to said successive approximation logic and timing unit, said comparator unit having an output coupled to said successive approximation register, said comparator generating a bit value respectively for each of a plurality of bit conversion states established by said successive approximation logic and timing unit and outputting said bit values to the successive approximation register to form a digital representation of the time difference between leading edges said first and second signals.