Patent ID: 9390765
Filing Date: 2016-07-12
CPC Classification: G11C,H01L

Claim Text:
1. An SRAM comprising a plurality of memory cells arranged in a matrix form, each memory cell including: (a) a substrate with MOSFET formed therein; (b) a contact for forming an electrical connection with the MOSFETs; (c) a first wiring line which is electrically connected with the contact, and formed by a first wiring layer having a metal layer of titanium or tantalum in a plane in touch with the contact, and which has a width as large as a minimum line width in the first wiring layer; (d) a first via which has a tungsten plug and is electrically connected with the first wiring line; (e) a second wiring line which is electrically connected with the first via, and formed by a second wiring layer having a metal layer of titanium or tantalum in a plane in touch with the first via, and which has a width as large as a minimum line width in the second wiring layer; and (f) a second via which is electrically connected with the second wiring line, and which has a tungsten plug and has one side as large as the minimum line width in the second wiring layer, wherein the second wiring line extends in the same direction as that of the first wiring line extending in a row or column direction, and has a length of two to three times the minimum line width in the second wiring layer, and in a plane in parallel with the substrate, the first via is disposed in a position between the contact and the second via, said contact, first via, and second via being displaced with respect to each other in a length direction of the second wiring line so that the distance between the first via and the contact is shorter than the distance between the contact and the second via, and the distance between the first and second vias is shorter than the distance between the contact and the second via.