Patent ID: 9319072
Filing Date: 2016-04-19
CPC Classification: H03M,H04L

Claim Text:
1. A bit interleaving method for interleaving bits of a codeword generated based on a quasi-cyclic low-density parity check coding scheme, including a repeat-accumulate quasi-cyclic low-density parity check coding scheme, the bit interleaving method comprising: a bit permutation step of applying a bit permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; and a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, wherein N is not a multiple of M, the bit permutation rule includes a first rule and a second rule, the first rule being applied to N′=N−X cyclic blocks, the second rule being applied to X cyclic blocks, the first rule and the second rule differing from each other, where X is a remainder of N divided by M, and the first rule defines the reordering of the bits of the codeword, such that the Q bits in each of the N′=N−X cyclic blocks are each allocated to a bit of an identical bit index in Q constellation words and the Q constellation words are each made up of one bit in each of M cyclic blocks, the M cyclic blocks being common to the Q constellation words.