Patent ID: 9245949
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a heavily doped semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the heavily doped semiconductor substrate, the semiconductor layer comprising a plurality of trenches formed therein, the trenches extending close to, up to, or into the semiconductor substrate, the trenches forming mesas in the semiconductor layer; a first epitaxial layer of the second conductivity type formed on sidewalls of the trenches, adjacent the mesas; a second epitaxial layer of the first conductivity type formed on the first epitaxial layer; a first dielectric layer formed in the remaining trenches, adjacent the second epitaxial layer, the first dielectric layer filling at least part of the trenches; a gate dielectric layer formed on the sidewalls of the trenches above the first dielectric layer; and a gate conductive layer formed in a first trench above the first dielectric layer and adjacent the gate dielectric layer, wherein the first epitaxial layer and the second epitaxial layer form adjacent doped regions along the sidewalls of the trenches, the second epitaxial layer having a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the semiconductor layer together having a second thickness and a second average doping concentration, the first and second thicknesses and the first and second doping concentrations being selected to achieve charge balance in operation.