Patent ID: 9240442
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A method for fabricating a capacitor of a semiconductor device, comprising: forming a plurality of storage node contact plugs penetrating through an inter-layer dielectric layer formed over a substrate; forming a mold layer over the plurality of storage node contact plugs and the inter-layer dielectric layer; forming a plurality of preliminary openings by selectively etching the mold layer; forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer over sidewalls of the plurality of preliminary openings; and forming a plurality of storage nodes in the plurality of openings, wherein a linewidth of each of the plurality of preliminary openings is wider than the given linewidth of each of the openings and a linewidth of each of the plurality of storage node contact plugs.