Patent ID: 9520181
Filing Date: 2016-12-13
CPC Classification: G11C

Claim Text:
1. A JMRAM memory cell comprising: a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary state and a second binary state in response to a write current provided during a data write operation and to provide a superconducting phase based on the stored digital state; a directional write element configured to provide a directional bias current during the data write operation to provide the superconducting phase of the PHMJJ in a predetermined direction corresponding to the first binary state; and at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current that is provided during a read operation.