Patent ID: 9247615
Filing Date: 2016-01-26
CPC Classification: G02F,G09G,H01L

Claim Text:
1. A display panel comprising: a substrate comprising an active area; a plurality of first signal lines disposed parallel to each other on the substrate and extending in a first direction; a plurality of second signal lines disposed parallel to each other on the substrate and extending in a second direction that is substantially perpendicular to the first direction to intersect the first signal lines, wherein there are more of the second signal lines than the first signal lines, and the intersection of the first signal lines with the second signal lines defines a plurality of pixel blocks; a plurality of pixel units respectively disposed within the pixel blocks, and respectively electrically connected to the first signal lines and respectively electrically connected to the second signal lines; a plurality of first transmission lines disposed parallel to each other on the substrate, respectively electrically connected to some of the second signal lines, crossing through two opposite sides of the active area, and parallel to the first signal lines; a plurality of second transmission lines disposed parallel to each other on the substrate, respectively electrically connected to the rest of the second signal lines that the first transmission lines are not electrically connected to, crossing through two opposite sides of the active area, and parallel to the first signal lines; a plurality of dummy lines evenly disposed on the substrate, parallel to the first transmission lines and the second transmission lines, the dummy lines extending through the two opposite sides of the active area; and a driver IC chip comprising: wherein the first pins and the second pins are evenly disposed and interleaved with each other, such that the first signal lines, the first transmission lines and the second transmission lines electrically connected to the first pins and the second pins do not cross over each other, and the first transmission lines and the second transmission lines are evenly disposed on the substrate; wherein the intersection of the first signal lines with the second signal lines forms an array of the pixel blocks, each of the pixel blocks being defined by one of the first signal lines and an immediately adjacent one of the second signal lines at corners of the array of the pixel blocks, an immediately adjacent two of either the first signal lines or the second signal lines and an immediately adjacent one of either the first signal lines or the second signal lines at outer areas of the array of the pixel blocks except at the corners thereof, and an immediately adjacent two of the first signal lines and an immediately adjacent two of the second signal lines at all other areas of the array of the pixel blocks; wherein the array of the pixel blocks comprises a plurality of columns of pixel blocks extending in the first direction, one of the first transmission lines and one of the second transmission lines passes through each of select columns of the pixel blocks, and one of the first transmission lines and one of the dummy lines passes through each of remaining columns of the pixel blocks.