Patent ID: 9368508
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A memory device, comprising: a peripheral circuit region including a plurality of circuit elements disposed on a first substrate, the first substrate including: a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, the second region of the first substrate extending from the upper surface of the first region to contact a lower surface of the second substrate; and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate, and wherein a cross-sectional width of the upper surface of the second substrate is less than or equal to 30 times a cross-sectional width of the second region of the first substrate parallel to the upper surface of the second substrate, the first and second regions of the first substrate including a same material.