Patent ID: 9245628
Filing Date: 2016-01-26
CPC Classification: G11C

Claim Text:
1. A non-volatile semiconductor memory device comprising: a semiconductor layer of a first conductivity type; a plurality of first wells of a second conductivity type formed on the first semiconductor layer, the first wells being arranged in a first direction; a plurality of memory blocks arranged in each of the first wells, each memory block comprising a plurality of NAND cell units arranged therein, each NAND cell unit including a plurality of memory cells and select transistors connected in series; a plurality of word lines, each word line being commonly connected to the NAND cell units in one memory block; a plurality of bit lines extending in the first direction, each bit line being connected to first ends of the NAND cell units in the memory blocks, and commonly connected across the plurality of first wells; a source line connected to second ends of the NAND cell units; and a well driver adapted to be capable of independently controlling potentials of the first wells.