Patent ID: 9396988
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, the method comprising: sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening therein on a substrate including a lower pattern; forming a trench in the interlayer insulating layer using the hard mask pattern, wherein the trench exposes the lower pattern; forming a liner layer including a first part extending along sidewalls and a bottom surface of the trench and a second part extending along a top surface of the hard mask pattern; forming a sacrificial pattern in the trench, wherein the sacrificial pattern exposes the second part of the liner layer; removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern as an etch mask; and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.