Patent ID: 9324721
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A pitch-halving integrated circuit (IC) process, comprising: forming, over a substrate, a plurality of parallel base line patterns each of which is connected with a hammerhead pattern at a first side or a second side of the plurality of base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner; trimming each base line pattern and each hammerhead pattern; forming, on sidewalls of each trimmed base line pattern and the corresponding trimmed hammerhead pattern as a spacer, a pair of derivative line patterns, a loop pattern around the trimmed hammerhead pattern, and a turning pattern at an end of the trimmed base line pattern without the corresponding trimmed hammerhead pattern; removing the trimmed base line patterns and the trimmed hammerhead patterns; and removing a portion of each loop pattern and at least a portion of each turning pattern to disconnect each pair of derivative line patterns, such that each remaining loop pattern includes two contact pad patterns.