Patent ID: 9530809
Filing Date: 2016-12-27
CPC Classification: H01L

Claim Text:
1. A layered structure comprising: a first electrode layer on an insulating substrate, the first electrode layer including a gate wire; a gate electrode connected to the gate wire; a capacitor wire; and a capacitor electrode connected to the capacitor wire; a first insulating film on the first electrode layer; a second electrode layer on the first insulating film, the second electrode layer including a source wire; a source electrode connected to the source wire; a drain electrode; and a pixel electrode connected to the drain electrode; a semiconductor located between the source electrode and the drain electrode, the gate electrode overlapping the semiconductor via the first insulating film, the capacitor electrode overlapping the pixel electrode via the first insulating film; a second insulating film on the second electrode layer and having an opening on the pixel electrode; a third electrode layer on the second insulating film, the third electrode layer comprising a plurality of reinforcement electrodes and including an upper pixel electrode connected to the pixel electrode via the opening, and a floating-gate thin film transistor, wherein the first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected, the third electrode layer relaying or reinforcing, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer, a common electrode around the thin film transistor array, the common electrode comprising a gate common electrode and a source common electrode; gate protective elements located between the gate wires and the gate common electrode; source protective elements located between the source wires and the source common electrode, the common electrode being directly connected to a ground potential or the ground potential via a resistor, wherein: at least one of the gate protective elements and the source protective elements comprises: the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, at least one of: