Patent ID: 9361238
Filing Date: 2016-06-07
CPC Classification: G06F

Claim Text:
1. A computer system comprising: a processor; and a memory unit coupled to said processor, wherein said memory unit comprises a memory addressing subsystem, said memory addressing subsystem comprising: a plurality of first type hash tables for addressing data, wherein said plurality of first type hash tables is collision-free and arranged in a hierarchy of priority order, wherein each first type hash table has associated therewith: a first table for tracking valid data therein; and a second table for tracking collision information; and a second type hash table having a priority below said plurality of first type hash tables, said second type hash table allowing collision therein, and said memory addressing subsystem operable wherein a newly presented data element traverses said hierarchy in said priority order and is stored in a highest priority first type hash table having an empty slot corresponding thereto, otherwise, said newly presented data element is stored in said second type hash table and, wherein further, upon a collision between said newly presented data element and a stored data element of a given first type hash table, both said newly presented data element and said stored data element are evicted from said given first type hash table and presented for storage to hash tables of lower priority than said given first type hash table.