Patent ID: 9484287
Filing Date: 2016-11-01
CPC Classification: G02F,H01L

Claim Text:
1. A semiconductor device comprising: (a) a semiconductor substrate of a substantially rectangular shape; (b) a semiconductor element formed on a main surface of the semiconductor substrate; (c) a multilayer wiring structure formed over the semiconductor element; (d) first pad electrodes and second pad electrodes formed in a same layer as an uppermost layer of the multilayer wiring structure; (e) dummy patterns being formed in the same layer as the uppermost layer of the multilayer wiring structure and being disposed at a different area from the first and second pad electrodes in a plan view; (f) a first insulating film being formed over the first and second pad electrodes and the dummy patterns and having first openings and second openings, the first openings being located at upper surfaces of the first pad electrodes respectively and the second openings being located at upper surfaces of the second pad electrodes respectively; (g) first bump electrodes and second bump electrodes being formed over the first insulating film and being electrically connected to the first pad electrodes via the first openings respectively; and (h) second bump electrodes being formed over the first insulating film and being electrically connected to the second pad electrodes via the second openings respectively, wherein the first bump electrodes are arranged along a first long side of the semiconductor substrate, wherein the second bump electrodes are arranged along the first long side of the semiconductor substrate and are disposed inwardly from the first bump electrodes in a first direction along a pair of short sides of the semiconductor substrate in plan view, wherein the dummy patterns are located between the first bump electrodes and the second bump electrodes in plan view, and wherein there are no wirings except the dummy patterns between the first pad electrodes and the second pad electrodes in plain view.