Patent ID: 9484320
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A semiconductor package comprising: a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs), wherein the TSVs are formed of conductive material that extend through the first IC die from an active surface of the die to a bottom surface of the die; a dielectric layer formed over the active surface of the first IC die; a first heat spreader formed over the dielectric layer; a first level of conductive lines coupled to the active surface of the first IC die, wherein the first level of conductive lines are arranged in a first plane substantially parallel to the active surface and extend to a first termination line outside a first edge of the IC die; a second level of conductive lines coupled to the TSVs at the bottom surface of the first IC die inside the perimeter of the die, wherein the second level of conductive lines are arranged in a second plane substantially parallel to the first plane and extend outside the perimeter of the die to a second termination line outside the first edge of the IC die, the second plane spaced apart from the first plane; a second heat spreader coupled to the bottom surface of the die, the second heat spreader conformal with and spaced from the first and second levels of conductive lines; and a molding compound encapsulating the first IC die and portions of the first and second levels of conductive lines, wherein the first and second termination lines extend outside the molding compound; and wherein the first and second levels of conductive lines at the first and second termination lines are configured to connect to a mounting surface, the semiconductor package to mount on the mounting surface so that the active surface and the bottom surface of the IC die are oriented perpendicular to the mounting surface.