Patent ID: 9360623
Filing Date: 2016-06-07
CPC Classification: G02B

Claim Text:
1. A method of fabricating a heterogeneous semiconductor wafer, the method comprising: depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate; bonding the first wafer to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer, and wherein the second wafer includes a metal layer that includes a thin contact metal stack on top of the patterned silicon layer, and wherein bonding includes annealing under pressure to form covalent bonds between the patterned silicon layer and the III-V type semiconductor epitaxial layer and interdiffusion between the thin contact metal stack and the III-V type semiconductor epitaxial layer; and removing the semiconductor substrate associated with the first wafer to expose the III-V type semiconductor epitaxial layer.