Patent ID: 9229874
Filing Date: 2016-01-05
CPC Classification: G06F

Claim Text:
1. A processor comprising: logic to generate one or more translation tables having a plurality of translation entries, each translation entry to include a pointer value and to store a portion of a full memory address usable within the processor to address data and instructions, wherein the translation tables comprise a first translation table and a second translation table, the first and second translation tables being located at different processor pipeline stages, and wherein the first translation table is used for converting from full memory addresses to compressed memory addresses, and the second translation table is used for converting from compressed memory addresses to full memory addresses; and address translation logic to use the translation tables to convert between the full address and a compressed version of the full address, the compressed version of the full address having the pointer value substituted for the portion of the full memory address, wherein a first portion of the processor is to perform operations using only the compressed version of the full address and a second portion of the processor is to perform operations using the full address when the full address is required.