Patent ID: 9436624
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. A circuitry for a computing system, comprising: a first load store unit (LSU); a second LSU; a memory arrangement; the first LSU being connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus, the first bus arrangement further comprising a first address bus connecting the first LSU and the memory arrangement; the second LSU being connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus; wherein the circuitry is arranged to carry out a multiple load instruction to cause the first LSU to simultaneously read data from the memory arrangement via the first read bus and the second read bus; and wherein the multiple load instruction causes the first LSU to read data from a first address of the memory arrangement propagated over the first address bus and to read data from a second address of the memory arrangement, the second address consecutive to the first address in the memory arrangement.