Patent ID: 9348349
Filing Date: 2016-05-24
CPC Classification: G01R,G05F

Claim Text:
1. An apparatus for detecting load on an input power, the apparatus comprising: a low dropout voltage regulator circuit configured to provide an output voltage to a load; a current mode comparator circuit connected to the low dropout voltage regulator circuit to monitor a low dropout voltage regulator circuit current driven by the output voltage of the low dropout voltage regulator circuit; wherein the current mode comparator circuit is configured to monitor the low dropout voltage regulator circuit current in a discrete time mixed analog/digital approach; wherein the low dropout voltage regulator circuit comprises a feedback loop transistor connected to pass the low dropout voltage regulator circuit current driven by the output voltage; and wherein the current mode comparator circuit comprises: a sensing transistor connected in parallel with the feedback loop transistor and configured to output a sensing current proportional to the low dropout voltage regulator circuit current; a reference current source configured to provide a reference current; a comparator circuit configured to perform a comparison between the sensing current and the reference current and to output a comparison signal based on the comparison; wherein the current mode comparator circuit comprises an n-bit digital to analog conversion circuit configured to control the reference current source to output a high reference current, wherein the comparator circuit is configured to output a digital flag signal in response to the sensing current exceeding the high reference current.