Patent ID: 9385023
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: providing a bulk semiconductor substrate of, from bottom to top, a silicon base layer having a p-type conductivity and a first dopant concentration, and a boron doped silicon layer having a second dopant concentration that is less than said first dopant concentration; forming a sacrificial trench isolation structure within said boron doped silicon layer to define a first boron doped silicon portion and a second boron doped silicon portion; forming a first porous silicon region of a first depth in said first boron doped portion and located beneath a remaining topmost portion of said first boron doped silicon portion, and a second porous silicon region of a second depth in said second boron doped portion and located beneath a remaining topmost portion of said second boron doped silicon portion, wherein said second depth is greater than said first depth; converting said first porous silicon region into a first buried oxide structure of said first depth and said second porous silicon region into a second buried oxide structure of said second depth; and patterning said remaining topmost portion of said first boron doped silicon portion to provide a first silicon fin of a first height on said first buried oxide structure, and said remaining topmost portion of said second boron doped silicon portion to provide a second silicon fin of a second height on said second buried oxide structure, wherein said second height is greater than said first height, yet said topmost surfaces of each first silicon fin and each second silicon fin are coplanar with each other.