Patent ID: 9312277
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. An array substrate for a display device, comprising: a substrate; first and second gate electrodes of impurity-doped polycrystalline silicon on the substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers of intrinsic polycrystalline silicon on the gate insulating layer, the first and second active layers corresponding to the first and second active layers, respectively; an interlayer insulating layer on the first and second active layers and including first to fourth active contact holes, the first and second active contact holes exposing side portions of the first active layer, the third and fourth active contact holes exposing side portions of the second active layer; first and second ohmic contact layers of impurity-doped amorphous silicon on the interlayer insulating layer, the first ohmic contact layer contacting the first active layer through the first and second active contact holes, the second ohmic contact layer contacting the second active layer through the third and fourth active contact hole; first source and drain electrodes on the first ohmic contact layer and second source and drain electrodes on the second ohmic contact layer; a data line on the interlayer insulating layer, the data line connected to the first source electrode; a first passivation layer on the first source and drain electrodes, the second source and drain electrodes and the data line; a gate line, a power line and a gate auxiliary pattern on the first passivation layer, the gate line connected to the first gate electrode and crossing the data line to define a pixel region; the gate auxiliary pattern electrically connected to the first drain electrode and the second gate electrode by a transparent gate connecting electrode; a second passivation layer on the gate line including an auxiliary contact hole exposing the gate auxiliary pattern; a power electrode connected to the power line and the second source electrode; and a pixel electrode on the second passivation layer, the pixel electrode connected to the second drain electrode; wherein the power electrode is formed on the interlayer insulating layer and extends from the second source electrode, and the power electrode overlaps the second gate electrode to constitute a first storage capacitor with the gate insulating layer and the interlayer interposed therebetween, and wherein the gate connecting electrode overlaps the power electrode to constitute a second storage capacitor with the first and second passivation layers interposed therebetween and the gate connecting electrode directly connected to the gate auxiliary pattern through the auxiliary contact hole.