Patent ID: 9425289
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming an initial fin structure in a semiconductor substrate; forming a layer of insulating material around said initial fin structure; performing a recess etching process to recess said initial fin structure and thereby define a recessed fin structure and a replacement fin cavity in said layer of insulating material above said recessed fin structure; forming at least first and second individual layers of epi semiconductor material in said replacement fin cavity, wherein each of said first and second layers have different concentrations of germanium; performing an anneal process on said first and second layers so as to form a substantially homogeneous SiGe replacement fin in said fin cavity; recessing said layer of insulating material so as to thereby expose at least an upper portion of said replacement fin; and forming a gate structure around at least a portion of said replacement fin exposed above said recessed layer of insulating material.