Patent ID: 9373565
Filing Date: 2016-06-21
CPC Classification: G11C,H01L

Claim Text:
1. A microelectronic package, comprising: a microelectronic element having memory storage array function, the microelectronic element having one or more columns of element contacts each column extending in a first direction along a face of the microelectronic element, such that an axial plane extending in a direction normal to the face of the microelectronic element intersects the face of the microelectronic element along a line extending in the first direction and centered relative to the one or more columns of element contacts; packaging structure including: a dielectric layer having a surface overlying the face of the microelectronic element and facing away from the face of the microelectronic element, the surface of the dielectric layer extending from a first edge thereof to a second edge thereof opposite from the first edge, the first and second edges extending in the first direction, wherein the surface of the dielectric layer has first and second peripheral regions adjacent to the first and second edges, respectively, and a central region separating the first and second peripheral regions and a plurality of terminals exposed at the surface of the dielectric layer, at least some of the terminals being electrically connected with the element contacts through traces extending along the dielectric layer and metallized vias extending from the traces and contacting the element contacts, the terminals disposed at positions within a plurality of parallel columns and being configured for connecting the microelectronic package to at least one component external to the microelectronic package, the terminals including first terminals disposed within at least one column in the central region and second terminals exposed at the surface of the dielectric layer in at least one of the peripheral regions, the first terminals being configured to carry all address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element, the second terminals configured to carry second information, the second information being other than the information carried by the first terminals, the second information including data signals, wherein the central region is not wider than three and one-half times a minimum pitch between any two adjacent columns of the terminals, and the axial plane intersects the central region.