Patent ID: 9502292
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: etching a shallow trench laterally surrounding a stack of a top semiconductor portion, a buried insulator portion, and an upper portion of a handle substrate in a semiconductor-on-insulator (SOI) substrate; depositing a stack of a dielectric metal oxide liner and a silicon nitride liner in said shallow trench; filling said shallow trench with a shallow trench fill portion; recessing said dielectric metal oxide liner to a depth below the horizontal plane of a bottom surface of said top semiconductor portion, wherein a divot laterally surrounding said top semiconductor portion is formed by said recessing; depositing a contact-level dielectric layer over said top semiconductor portion and said shallow trench fill portion; etching a contact via hole through said contact-level dielectric layer and a portion of said shallow trench fill portion employing at least one of said dielectric metal oxide liner and said silicon nitride liner as a stopping layer; and forming a contact via structure by depositing a conductive material within said contact via hole, wherein a portion of said contact via structure is formed directly on a vertical sidewall surface of said top semiconductor portion.