Patent ID: 9443844
Filing Date: 2016-09-13
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: a write bit line; a write word line intersecting with the write bit line; a read line; a source line intersecting with the read line; and a memory cell, wherein the memory cell comprises a write transistor, a read transistor, and a capacitor, wherein a gate, a drain, and a source of the write transistor are connected to the write word line, one electrode of the capacitor, and the source line, respectively, wherein a gate, a drain, and a source of the read transistor are connected to the drain of the write transistor, the read line, and the source line, respectively, wherein the other electrode of the capacitor is connected to the write bit line, wherein a potential corresponding to a piece of data to be stored in the memory cell is configured to be supplied to the write bit line, and wherein the potential of the write bit line is configured to be changed when the piece of data stored in the memory cell is rewritten.