Patent ID: 9472282
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A resistive memory device comprising: a memory cell array comprising a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other; a write circuit connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and to provide pulses to the selected memory cell; a voltage detector to detect a node voltage at a connection node between the selected first signal line and the write circuit; and a voltage generation circuit to generate a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and to change a voltage level of the second inhibit voltage based on the node voltage that is detected.