Patent ID: 9442848
Filing Date: 2016-09-13
CPC Classification: G06F

Claim Text:
1. A method for increased destaging efficiency by smoothing destaging tasks to reduce long input/output (I/O) read operations by a processor device in a computing environment, the method comprising: calculating a current number of the destaging tasks, the current number of destaging tasks being a number of destaging task control blocks (TCBs) active on a rank of a memory; calculating a desired number of destaging tasks, the desired number of destaging tasks being a number of TCBs needed for the rank based upon a non-volatile storage (NVS) occupancy for the rank; smoothing the destaging of the destaging tasks between the desired number of the destaging tasks and the current number of the destaging tasks by expediting the calculating of the current number of the destaging tasks and the desired number of the destaging tasks, according to either a duration of time or a variable recomputed destaging task number, for reaching the desired number of the destaging tasks by decrementing the current number of destaging tasks or incrementing the current number of destaging tasks; and smoothing according to the time interval when a delta value, which is the difference between the desired number of destaging tasks and the current number of destaging tasks, is less than a predetermined delta value;