Patent ID: 9324512
Filing Date: 2016-04-26
CPC Classification: H01H,H01L,H03K,H04B

Claim Text:
1. A single pole double throw switch, comprising: a first terminal, a second terminal and a third terminal; a first control terminal and a second control terminal; a first field-effect transistor having a drain connected to the first terminal, a source connected to a ground, and a gate; a first bias resistor connected between the gate of the first field-effect transistor and the first control terminal; a first inductor connected between the first terminal and the second terminal; a second field-effect transistor having a drain connected to the third terminal, a source connected to the ground, and a gate; a second bias resistor connected between the gate of the second field-effect transistor and the second control terminal; a second inductor connected between the second terminal and the third terminal; and a capacitor having one end connected to the second terminal and another end connected to the ground; wherein the first field-effect transistor and the second field-effect transistor have respective widths based on a target isolation of the single pole double throw switch; wherein each of the first and the second field-effect transistors has a switched-on state exhibiting an on-resistance and a switched-off state exhibiting an off-capacitance; wherein the single pole double throw switch is configured to form a π-impedance-matching network by the first inductor, the capacitor and the first field-effect transistor exhibiting the off-capacitance, or to form the π-impedance-matching network by the second inductor, the capacitor and the second field-effect transistor exhibiting the off-capacitance, wherein: the width of the first field-effect transistor is equal to the width of the second field-effect transistor is equal to ISO denotes the target isolation of the single pole double throw switch, Z r r