Patent ID: 9460778
Filing Date: 2016-10-04
CPC Classification: G11C

Claim Text:
1. A static random access memory comprising: a memory cell array comprising a plurality of memory cells; a control logic configured to generate a first write clock signal and a second write clock signal in response to a received clock signal, wherein each of the first and second write clock signals has a single pulse width during a cycle of the clock signal, the single pulse width being shorter than a pulse width of the clock signal; a row decoder connected to the plurality of memory cells through a plurality of word lines and configured to select a word line in response to the second write clock signal during a write operation; a column selector connected to the plurality of memory cells through a plurality of bit lines and a plurality of inverted bit lines and configured to select a bit line and an inverted bit line; a sense amplifier connected to the bit line and the inverted bit line selected by the column selector and configured to sense states of the selected bit line and the selected inverted bit line during a read operation; and a write driver connected to the bit line and the inverted bit line selected by the column selector and configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation.