Patent ID: 9343569
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a handle substrate including a doped Group IV semiconductor well; an insulator layer overlying said handle substrate; a doped semiconductor material portion overlying a first portion of said insulator layer that is located over said doped Group IV semiconductor well; a vertical stack including a lower active region and a channel region, said vertical stack extending at least through said first portion of said insulator layer and said doped semiconductor material portion and laterally surrounded by a gate dielectric contacting sidewalls of said first portion of said insulator layer and said doped semiconductor material portion, and wherein said lower active region and said channel region comprise at least one compound semiconductor material; and a field effect transistor overlying a second portion of said insulator layer, said field effect transistor comprising active regions composed of a same Group IV semiconductor material as said doped semiconductor material portion, wherein top surfaces of said active regions of said field effect transistor are coplanar with a top surface of said doped semiconductor material portion.