Patent ID: 9324735
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A manufacturing method of an array substrate, the array substrate including a plurality of pixel units, each of which includes: a thin film transistor (TFT) area provided with a thin film transistor including a gate, a gate insulation layer, a source, a drain and an active area; and a display area provided with a pixel electrode, wherein the manufacturing method of an array substrate includes steps of: forming a pattern including the gate on a substrate through a patterning process, and forming the gate insulation layer; forming patterns including the active area and an etching stop area provided on the active area through a patterning process, on the substrate subjected to the above step; forming a transparent conductive layer film, and forming patterns including the source and the drain from the transparent conductive layer film through a patterning process; and forming a pattern including the pixel electrode from the transparent conductive layer film through a patterning process, wherein the step of forming a transparent conductive layer film and forming patterns including the source and the drain from the transparent conductive layer film through a patterning process includes steps of: wherein, the source transition layer is used to electrically connect the source connection layer with the source, wherein the step of forming a pattern including the pixel electrode from the transparent conductive layer film through a patterning process includes steps of: