Patent ID: 9401220
Filing Date: 2016-07-26
CPC Classification: G09G,G11C

Claim Text:
1. A multi-phase gate driver disposed in a peripheral area of a display panel for generating a plurality of gate signals, the multi-phase gate driver comprising: a start/end signal generator circuit, configured to sequentially output N start signals according to a first control signal and N groups of clock signals and sequentially output N end signals according to a second control signal and the N groups of clock signals, wherein each one of the N start signals has a delay relative to the previous start signal, and each one of the N end signals has the delay relative to the previous end signal, each one of the N groups of clock signals comprises a respective first clock signal and a respective second clock signal, the first clock signal and its respective second clock signal are inverted to each other, each one of the N first clock signals has the delay relative to the first clock signal in the previous group; and X shift register modules, electrically coupled to the start/end signal generator circuit and each comprising N shift register units arranged in sequence from top to bottom, wherein the Mth of the N shift register units in the first of the X shift register modules is configured to output a respective gate signal according to the Mth of the N groups of clock signals, the Mth of the N start signals, and the gate signal outputted from the Mth of the N shift register units in the second of the X shift register modules, wherein M, N and X are positive integers and N is greater than 1.