Patent ID: 9444459
Filing Date: 2016-09-13
CPC Classification: H01L,H03K

Claim Text:
1. A logic circuit comprising: a first input terminal; a second input terminal; a first transistor comprising a first oxide semiconductor layer including a channel formation region; a second transistor comprising a second oxide semiconductor layer including a channel formation region, an output terminal; and a main logic circuit portion comprising a third transistor including a portion formed in a substrate including a semiconductor material, wherein one of a source and a drain of the first transistor is electrically connected to the first input terminal and the other of the source and the drain of the first transistor is electrically connected to the main logic circuit portion, wherein one of a source and a drain of the second transistor is electrically connected to the second input terminal and the other of the source and the drain of the second transistor is electrically connected to the main logic circuit portion, and wherein the main logic circuit portion is electrically connected to a first power supply potential line, a second power supply potential line, and the output terminal.