Patent ID: 9406814
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A non-volatile memory device comprising: an underlying layer having a top surface; a first stacked electrode provided above the underlying layer; a second stacked electrode juxtaposed with the first stacked electrode above the underlying layer; a first semiconductor layer extending through the first stacked electrode in a first direction perpendicular to the top surface of the underlying layer, the first semiconductor layer having a first top end and a first bottom end; a second semiconductor layer extending through the first stacked electrode in the first direction, the second semiconductor layer having a second top end and second bottom end; a third semiconductor layer extending through the first stacked electrode, the third semiconductor layer having a third top end and a third bottom end; a fourth semiconductor layer extending through the second stacked electrode in the first direction, the fourth semiconductor layer having a fourth top end and a fourth bottom end; a memory film provided between the first stacked electrode and the first semiconductor layer; a link part provided between the underlying layer and the first stacked electrode, and between the underlying layer and the second stacked electrode, the link part being electrically connected to the first bottom end of the first semiconductor layer, the second bottom end of the second semiconductor layer, the third bottom end of the third semiconductor layer, and the fourth bottom end of the fourth semiconductor layer; a first interconnection electrically connected to the first top end of the first semiconductor layer, the second top end of the second semiconductor layer, and the third top end of the third semiconductor layer; a second interconnection electrically connected to the fourth top end of the fourth semiconductor layer; and a conductive layer covering the link part.