Patent ID: 9502124
Filing Date: 2016-11-22
CPC Classification: G11C

Claim Text:
1. A nonvolatile memory device comprising: a memory cell array including memory cells stacked in a direction perpendicular to a substrate, and a word line connected to plural memory cells among the memory cells of the memory cell array; a voltage generator configured to sequentially provide a first setup voltage and a second setup voltage to the word line; and a control logic including a time control unit configured to determine a word line setup time for the second setup voltage for the word line based on a difference between a level of the first setup voltage and a level of the second setup voltage, the word line setup time for the second setup voltage being from a time the second setup voltage is applied to a time a sensing operation starts wherein the memory cell array comprises a channel hole for each of plural stacks of memory cells, and a plurality of word lines connected to respective memory cells of each stack of memory cells, each word line having a corresponding word line setup time defined at least in part by a diameter of the channel hole associated with the word line.