Patent ID: 9461162
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A semiconductor integrated circuit device comprising: first to third word lines buried in a semiconductor substrate and extending parallel to one another with a predetermined spacing along a first direction; first to third bit lines extending parallel to one another on the semiconductor substrate with a predetermined spacing along a second direction crossing the first direction, and formed in an upper region than a region that the first to third word lines are formed; a first storage node of a first memory cell formed over the semiconductor substrate of an inner space which is surrounded by the first word line, the second word line, the first bit line and the second bit line when viewed from top of the semiconductor substrate; a second storage node of a second memory cell formed over the semiconductor substrate of an inner space which is surrounded by the first word line, the second word line, the second bit line and the third bit line when viewed from top of the semiconductor substrate; a third storage node of a third memory cell formed over the semiconductor substrate of an inner space which is surrounded by the second word line, the third word line, the first bit line and the second bit line when viewed from top of the semiconductor substrate, first to third drain regions electrically connected with the first to third bit lines respectively, and formed in lower portions of the substrate under the first to third bit lines, respectively; and first to third source regions formed in upper portions of the substrate under the first to third storage nodes, respectively, wherein the first memory cell and the third memory cell share the second word line, wherein the first memory cell and the second memory cell share the second bit line.