Patent ID: 9329866
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. A method for changing execution latency for performance and power optimization of an instruction class adaptable pipeline processor, the method comprising: creating, by use of a computer, an application program for the instruction class adaptable pipeline processor, the application program containing class one instructions each executable with a first latency in a class one pipeline and class two instructions each executable with a second latency in a class two pipeline, wherein the first latency is shorter than the second latency; changing an encoding of an original class one instruction of the class one instructions to a second encoded class one instruction that specifies a function of the original class one instruction is to be executed with the second latency to minimize power use while still meeting performance requirements and to create a modified application program; and executing the modified application program on the instruction class adaptable pipeline processor, wherein the second encoded class one instruction is executed and the original class one instruction is not executed.