Patent ID: 9378317
Filing Date: 2016-06-28
CPC Classification: G01R,G06F,H01L

Claim Text:
1. A method for producing a semiconductor chip, the method comprising: arranging a plurality of semiconductor components in a semiconductor zone of the semiconductor chip, the plurality of semiconductor components comprising at least one electrical circuit; arranging at least one interconnect at a periphery of the semiconductor zone, wherein the at least one interconnect separates the plurality of semiconductor components from a crack stop located in a first dielectric layer of the semiconductor chip; arranging at least two transistors at the periphery of the semiconductor zone as at least two temperature sensors; electrically coupling a current source and the at least two transistors in series to the at least one interconnect; and creating a detection circuit configured to compare a voltage of the at least one interconnect with a predefined reference voltage, wherein the detection circuit is configured to detect a change in the voltage of the at least one interconnect, to identify a temperature, detected by the at least two temperature sensors, corresponding to the voltage of the at least one interconnect within a particular voltage range below the predefined reference voltage, and to identify a presence of damage to at least one portion of the semiconductor chip corresponding to the voltage of the at least one interconnect being above the predefined reference voltage.