Patent ID: 9455269
Filing Date: 2016-09-27
CPC Classification: H01L

Claim Text:
1. A semiconductor memory device, comprising: a memory cell array, the memory cell array including: a conductive layer stacked on a semiconductor substrate; an inter-layer insulating layer disposed on the conductive layer; a conductive line disposed on the inter-layer insulating layer; a first connecting line and a second connecting line that contact the semiconductor substrate and are electrically connected to the conductive line and that at least extend in a stacking direction of the conductive layer and the inter-layer insulating layer; and a columnar body that penetrates the conductive layer and the inter-layer insulating layer in the stacking direction between the first connecting line and the second connecting line and that includes a first semiconductor layer, the semiconductor substrate having: a first impurity region to which a first impurity is added at a place of contact with the first connecting line; and a second impurity region to which a second impurity different from the first impurity is added at a place of contact with the second connecting line.