Patent ID: 9355972
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A method of making a dielectric region to provide a high-Q passive resonator in a mixed-signal integrated circuit (IC), said method comprising: patterning and etching a hard mask to form a plurality of holes along <100> directions that overlie a bulk Si substrate of a (100) Si wafer; etching said bulk Si substrate through said plurality of holes, said etching forming a plurality of trenches with vertical sidewalls; wet etching said plurality of trenches, said wet etching providing a plurality of cavities with thin Si sidewalls between adjacent cavities and said wet etching removing undercut regions in said cavities; oxidizing the sidewalls of said plurality of cavities, including said thin Si sidewalls, said oxidizing forming Si oxide sidewalls in said cavities; filling said plurality of cavities with a Si oxide forming said dielectric region including a plurality of Si oxide filled cavities separated by said Si oxide sidewalls; depositing and planarizing a dielectric layer over said hard mask and said dielectric region; and forming said high-Q passive resonator in metallization layers associated with back-end-of-line (BEOL) processes in making of said mixed-signal IC, said metallization layers being over said dielectric region.