Patent ID: 9269447
Filing Date: 2016-02-23
CPC Classification: G11C

Claim Text:
1. A nonvolatile semiconductor memory device, comprising: a cell array including a source line, a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a plurality of cell strings electrically connected between the source line and the plurality of bit lines, each of the cell strings being configured from a plurality of memory cells connected in series to each be connected to one of the word lines; and a control unit that performs a data write/erase/read on the memory cells, the cell array being divided into a plurality of blocks including a target block, each of the blocks including first through N-th pages (where N is an integer of 2 or more), each of the pages being configured by a plurality of the memory cells connected to one of the word lines, the control unit executing the data write/read in a unit of the page, and executing the data erase in a unit of the block, and the control unit, in the data write, determining at least one of: a first requirement that the number of times of the data read on first through n a second requirement that the number of memory cells whose threshold voltage is higher than a reference voltage, of the plurality of memory cells of a reference page of n when the determined requirement is satisfied, writing additional data to the n