Patent ID: 9496021
Filing Date: 2016-11-15
CPC Classification: G06F,G11C

Claim Text:
1. In a volatile memory array having i anode lines, j cathode lines, and an array of vertical thyristor memory cells having a first electrode coupled to an anode line and a second electrode coupled to a cathode line, and in which N thyristor memory cells are connected to a selected anode line, a method of reducing current in the selected anode line to be accessed for an operation comprising: (a) dividing the N thyristor memory cells coupled to the selected anode line into M groups each of k thyristor memory cells where k is greater than 1; (b) for a first group of k thyristor memory cells upon at least one of which a desired operation is to be performed, applying a first voltage to each cathode line coupled to one of the k thyristor memory cells; (c) for all other of the N thyristor memory cells except the first group of k thyristor memory cells, applying a second voltage to each cathode line coupled to one of the all other N thyristor memory cells, where the second voltage is less than the first voltage; (d) performing the desired operation on at least one of the k thyristor memory cells; (e) selecting a second group of k thyristor memory cells from the M groups of thyristor memory cells; (f) for the second group of k thyristor memory cells upon at least one of which the desired operation is to be performed, applying the first voltage to each cathode line coupled to one of the k thyristor memory cells; (g) for all other of the N thyristor memory cells except the second group of k thyristor memory cells, applying the second voltage to each cathode line coupled to one of the all other N thyristor memory cells; and (h) performing the desired operation on at least one of the second group of k thyristor memory cells.