Patent ID: 9240346
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit device, comprising: forming a first hard mask layer over a substrate; forming a second hard mask layer over the first hard mask layer; forming a first photoresist layer over the first and second hard mask layers; exposing the first photoresist layer through a mandrel mask; developing the first photoresist layer to form a mask; patterning the second hard mask layer to form a second layer mask that defines locations at which conductive lines that will be formed in the substrate will end, wherein patterning comprises etching the second hard mask layer using the first photoresist layer as a mask and the first hard mask layer as an etch stop layer; performing a self-aligned double-patterning of the first hard mask layer to form a first layer mask, wherein the first layer mask defines the locations at which the conductive lines will be formed in the substrate, wherein the first layer mask remains intact where it is masked by the second layer mask, and wherein performing the self-aligned double-patterning comprises forming a mandrel over the patterned second hard mask layer using the mandrel mask and subsequently etching the first hard mask layer; forming trenches in the substrate by etching with the first layer mask providing a mask; and filling the trenches with conductive metal to form the conductive lines.