Patent ID: 9471743
Filing Date: 2016-10-18
CPC Classification: G06F,Y02P

Claim Text:
1. A method of predicting a process fail limit for a semiconductor manufacturing process, the method comprising: building test wafers, the building of the test wafers comprising varying a plurality of process parameters during forming of a test wafer feature on each test wafer; acquiring a set of measurements for the test wafer feature on each of the test wafers using a wafer measurement tool; determining, using one or more computing devices, a potential working process condition for each of the plurality of process parameters; determining, using one or more computing devices, a process sigma value for each of the plurality of process parameters; determining, using one or more computing devices, a measurement sigma value from the process sigma value for each of the plurality of process parameters; evaluating, using one or more computing devices, the set of measurements of the test wafer feature compared to an acceptable wafer feature dimension, where each measurement of the set of measurements is evaluated as a pass or a fail as compared to the acceptable wafer feature dimension and stored in a test wafer measurement database; determining, using one or more computing devices, whether one or more fails are evaluated as compared to the acceptable wafer feature dimension for the set of measurements of the test wafer feature for measurement sigma values below a desired target sigma value; and responsive to determining one or more fails are evaluated, producing, using one or more computing devices, a predicted process fail limit based, at least in part, on the evaluated one or more fails, the measurement sigma value, and the desired target sigma value for the semiconductor test wafer build.