Patent ID: 9515077
Filing Date: 2016-12-06
CPC Classification: G11C,H01L

Claim Text:
1. A Static Random Access Memory (SRAM) cell defined by first and second boundaries disposed opposite to each other, and third and fourth boundaries disposed opposite to each other and intersected by the first and second boundaries, the SRAM cell comprising: a first invertor including a first P-type pull-up transistor and a first N-type pull-down transistor; a second invertor including a second P-type pull-up transistor and a second N-type pull-down transistor and cross-coupled to the first invertor; and first and second pass-gate transistors connected to the cross-coupled first and second invertors, wherein: source regions of the first and second P-type pull-up transistors are formed by a main source active region extending continuously between the first and second boundaries, and source regions of the first and second pass-gate transistors and the first and second N-type pull-down transistors are formed by different source active regions spaced apart from each other.