Patent ID: 9344062
Filing Date: 2016-05-17
CPC Classification: H03K

Claim Text:
1. A semiconductor device comprising: a function block configured to perform power gating; a first transistor; a second transistor; a power source; a capacitor; and a control circuit, wherein one of a source and a drain of the first transistor is electrically connected to the function block and one of a source and a drain of the second transistor, wherein one electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor, wherein the other electrode of the capacitor is electrically connected to a wiring for supplying a fixed potential, wherein the power source is electrically connected to the other of the source and the drain of the first transistor, wherein the control circuit is electrically connected to a gate of the first transistor and a gate of the second transistor, and wherein the gate of the first transistor is not electrically connected to the gate of the second transistor.