Patent ID: 9367311
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A multi-core processor system comprising: a given core that includes: a detecting unit that detects migration of a thread under execution by a synchronization source core to a synchronization destination core in the multi-core processor, an identifying unit that refers to a table identifying a combination of a thread of a thread group and a register associated with the thread, and identifies a particular register corresponding to the thread for which migration was detected by the detecting unit, wherein the table does not specify a memory area other than a register, and a generating unit that generates synchronization control information identifying the synchronization destination core and the particular register identified by the identifying unit; and a synchronization controller that, communicably connected to the multi-core processor, acquires from the given core, the synchronization control information generated by the generating unit, reads in from the particular register of the synchronization source core, a value of the particular register obtainable from the synchronization control information, and writes to the particular register of the synchronization destination core, the value read in from the particular register of the synchronization source core.