Patent ID: 9378776
Filing Date: 2016-06-28
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; and a capacitor, wherein a gate of the first transistor is electrically connected to a first wiring, wherein one of a source and a drain of the first transistor is electrically connected to a second wiring, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to a third wiring, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein a gate of the third transistor is electrically connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring, wherein one electrode of the capacitor is electrically connected to the gate of the second transistor, wherein the other electrode of the capacitor is electrically connected to a sixth wiring, wherein the first wiring is capable of transmitting a first signal, wherein the second wiring is capable of transmitting a second signal, wherein the third wiring is capable of transmitting a first potential, wherein the fourth wiring is capable of transmitting a third signal, wherein the fifth wiring is capable of transmitting a second potential, wherein the sixth wiring is capable of transmitting a fourth signal, wherein the first signal is capable of turning on the first transistor so that a potential of the second signal is supplied to the gate of the second transistor, wherein the third signal is capable of turning on the third transistor so that the second potential is supplied to the one of the source and the drain of the third transistor, and wherein the fourth signal is capable of controlling an on/off state of the second transistor in accordance with the potential of the second signal supplied to the gate of the second transistor so that the first potential is supplied to the other of the source and the drain of the second transistor.