Patent ID: 9293223
Filing Date: 2016-03-22
CPC Classification: G09G,G11C

Claim Text:
1. A shift register unit comprising: a pull-up control module being connected to a first clock signal terminal, a first voltage signal terminal, a second voltage signal terminal and a pull-up control node, and configured to control a potential at the pull-up control node; a pull-up module being connected to the pull-up control node, the first voltage signal terminal and a signal output terminal of present stage and configured to pull up a signal outputted from the signal output terminal of present stage to a high potential when the pull-up module is controlled by a signal at the pull-up control node to be in a turn-on state and a signal at the first voltage signal terminal is at a high level; a pull-down control module being connected to a second clock signal terminal, a signal input terminal and a pull-down control node and configured to control a potential at the pull-down control node; a pull-down module being connected to the pull-down control node, the first clock signal terminal and the signal output terminal of present stage and configured to pull down the signal outputted from the signal output terminal of present stage to a low potential when the pull-down module is controlled by the signal at the pull-down control node to be in a turn-on state and a signal outputted from the first clock signal terminal is at a low level, wherein the pull-up control module comprises: a third transistor, whose gate and first electrode are connected to the second voltage signal terminal, and second electrode is connected to the pull-up control node; a fourth transistor, whose first electrode is connected to the pull-up control node, and second electrode is connected to the first voltage signal terminal; and a fifth transistor, whose gate is connected to the first clock signal terminal, first electrode is connected to the pull-down control node, and second electrode is connected to a gate of the fourth transistor.