Patent ID: 9460805
Filing Date: 2016-10-04
CPC Classification: G11C,H01L

Claim Text:
1. A memory device, comprising: a plurality of NAND strings comprising a selected NAND string and an unselected NAND string, wherein: a control circuit, the control circuit configured, for the unselected NAND string, to perform a pre-charge operation prior to application of a program voltage to the selected word line in a programming operation, wherein to perform the pre-charge operation, the control circuit is configured to concurrently apply a positive pre-charge voltage to the respective bit line of the unselected NAND string and a voltage to the first dummy memory cell, wherein a level of the voltage applied to the first dummy memory cell is a function of a distance between the selected word line and the first dummy memory cell such that the level is higher when the distance is greater.