Patent ID: 9401370
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A non-volatile memory device, comprising: a channel structure formed over a substrate and including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked along a vertical direction perpendicular to the substrate, wherein the channel structure extends along a first horizontal direction parallel to the substrate and has a first sidewall and a second sidewall; memory cells sharing each of the channel layers and arranged along the first horizontal direction to form a string; a first selection gate electrode and a second selection gate electrode that are disposed on the first sidewall and the second sidewall of the channel structure, respectively, and are conductive, wherein the first selection gate electrode and the second selection gate electrode are located at a same level in the vertical direction and located at a same end of the string in the first horizontal direction; and an insulation layer interposed between the first selection gate electrode and the channel structure, and between the second selection gate electrode and the channel structure, wherein a work function of the first selection gate electrode is different from a work function of the second selection gate electrode so that the work function of the first selection gate electrode and the work function of the second selection gate electrode are located at a same point along the channel structure with respect to a line normal to the sidewalls of the channel structure, and the first selection gate electrode, each of the channel layers and the insulation layer interposed therebetween form a first selection transistor, and the second selection gate electrode, each of the channel layers and the insulation layer interposed therebetween form a second selection transistor.