Patent ID: 9245083
Filing Date: 2016-01-26
CPC Classification: G06F,H01L

Claim Text:
1. A structure, comprising: a set of interconnect levels over a semiconductor substrate, each interconnect level of said set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer, one or more of said operational wires electrically connected to said semiconductor substrate; a dielectric barrier layer on an uppermost interconnect level of said set of interconnect levels and a bonding pad on said barrier layer, said bonding pad electrically connected to an operational wire of said one or more operational wires through an opening in said barrier layer; a passivation layer on said barrier layer and said bonding pad; a ball limiting metallurgy layer on said bonding pad through an opening in said passivation layer and a solder-bump on said ball limiting metallurgy layer; a stress reduction zone surrounding a perimeter of said bonding pad and extending into said set of interconnect levels; elongated fill wires in at least three of said interconnect levels in said stress reduction zone between said bonding pad and said semiconductor substrate, said elongated fill wires (i) not connected to any of said operational wires or (ii) connected only to a ground network; said elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of said set of interconnect levels; and wherein said set of interconnect levels intervene between said bonding pad and said semiconductor substrate.