Patent ID: 9466592
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A multi-chips in system level and wafer level package structure, comprising: a packaged substrate, the packaged substrate having a front surface and a back surface, a plurality of external connecting terminals on a four sides on the front surface of the packaged substrate, a plurality of chip arrangement regions on the packaged substrate and a through hole disposed in each plurality of chip arrangement regions, a plurality of connecting terminals is disposed on one side adjacent the plurality of through holes, wherein the plurality of connecting terminals is electrically connected with the plurality of external connecting terminals by a plurality of metal traces; a plurality of chips, each the plurality of chips having an active surface and a back surface, a plurality of pads on the active surface of each the plurality of chips and the location of the plurality of pads is corresponding to that of the plurality of through holes of the packaged substrate, and each the plurality of chips is arranged on each the plurality of chip arrangement regions and the active surface of each the plurality of chips is fixed on the back surface of the packaged substrate, such that the plurality of pads on the active surface of each the plurality of chips is exposed out of the plurality of through holes; a plurality of metal wires, the plurality of metal wires is provided for electrically connecting the plurality of connecting terminals and the plurality of pads on the active surface of the plurality of chips; and a packaged body, the packaged body is provided for filling the plurality of through holes on each the plurality of chip arrangement regions to encapsulate the plurality of connecting terminals, the plurality of pads on the active surface of each the plurality chips, and to locally encapsulate the front surface of the packaged substrate adjacent the plurality of through holes on each the plurality of chip arrangement region.