Patent ID: 9419570
Filing Date: 2016-08-16
CPC Classification: G09G,H01L,H03F,H03K

Claim Text:
1. A semiconductor device comprising: a first line, a second line, a third line, and a fourth line; a first transistor, a second transistor, and a third transistor each including a gate, a source and a drain; a first capacitor configured to store voltage depending on threshold voltage of the second transistor; and an element including an anode and a cathode, wherein the gate of the first transistor is electrically connected to the first line, wherein one of the source and the drain of the first transistor is electrically connected to the second line, wherein the other of the source and the drain of the first transistor is electrically connected to the second transistor, wherein the gate of the second transistor is electrically connected to one terminal of the first capacitor, wherein one of the source and the drain of the second transistor is electrically connected to the third line, wherein the other of the source and the drain of the second transistor is electrically connected to the other terminal of the first capacitor; wherein the gate of the third transistor is electrically connected to the fourth line, wherein one of the source and the drain of the third transistor is electrically connected to one of the anode and the cathode, wherein the one of the anode and the cathode is electrically connected to the other terminal of the first capacitor, wherein a first potential is capable of being supplied to the second line, wherein a second potential is capable of being supplied to the third line, and wherein the first potential is different form the second potential.