Patent ID: 9472290
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A method of operating a semiconductor device, comprising: performing a multi-plane erase operation on selected planes, the multi-plane erase operation including a plurality of erase loops, each of the selected planes including a plurality of memory blocks including a selected memory block, and each of the plurality of erase loops including an erase operation and an erase verifying operation; determining that the multi-plane erase operation fails; determining whether there is at least one passed plane among the selected planes in response to the determining that the multi-plane erase operation fails; storing information corresponding to an address of the at least one passed plane; and performing a soft program operation on the at least one passed plane in response to the information, wherein the failure of the multi-plane erase operation indicates that it is determined that at least one of the selected planes fails based on the erase verifying operation when the number of the erase loops reaches a maximum number.