Patent ID: 9336071
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. An apparatus for administering incomplete data communications messages in a parallel computer comprising a plurality of compute nodes, each compute node comprising a processor and a messaging accelerator, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: transmitting, by a source messaging accelerator to a destination messaging accelerator, a message comprising a plurality of packets, including processing a messaging descriptor describing the message and setting, in the message descriptor, a flag indicating the message has been sent, wherein the messaging descriptor includes an acknowledgement request descriptor and is stored in a list of messaging descriptors; transmitting, by the source messaging accelerator to the destination messaging accelerator responsive to processing the acknowledgement request descriptor corresponding to the message, a request for acknowledgment of receipt of the message comprising the plurality of packets; receiving, by the source messaging accelerator from the destination messaging accelerator, a negative acknowledgment (NACK) indicating that the message comprising the plurality of packets was not received at the destination messaging accelerator, wherein the destination messaging accelerator sends the NACK in response to determining that the plurality of packets was only partially received; and clearing, by the source messaging accelerator in the message descriptor, the flag indicating that message comprising the plurality of packets has been sent.