Patent ID: 9442510
Filing Date: 2016-09-13
CPC Classification: G06F,H03K

Claim Text:
1. A clock circuit comprising: a first transistor having a first terminal and a second terminal, the first terminal of the first transistor configured to receive a clock input signal, the second terminal of the first transistor coupled to a first node, and the first transistor configured to adjust a voltage of the first node to a first voltage level based on the clock input signal; a first inverter coupled to the first node, the first inverter configured to receive the voltage of the first node, and the first inverter being configured to output a clock output signal; and a second transistor having a first terminal and a second terminal, the first terminal of the second transistor configured to receive the clock input signal, the second terminal of the second transistor coupled to the first node and a second node, and the second transistor configured to adjust the voltage of the first node or a voltage of the second node to a second voltage level based on the clock input signal.