Patent ID: 9520300
Filing Date: 2016-12-13
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming an interlayer insulating layer on a substrate, the interlayer insulating layer comprising: a first portion being adjacent to the substrate and having a first pore density; a second portion formed on the first portion; and a third portion formed on the second portion and having a second pore density higher than the first pore density, and a pore density of the second portion gradually increasing toward the third portion; forming conductive patterns penetrating the third portion of the interlayer insulating layer; etching the third portion of the interlayer insulating layer to reduce a height of the interlayer insulating layer; and forming a capping insulation layer on the conductive patterns, wherein an air gap is formed between the conductive patterns.