Patent ID: 9229714
Filing Date: 2016-01-05
CPC Classification: G06F,G11C

Claim Text:
1. A memory control apparatus comprising: a pre-read processing section configured to read pre-read data from a data area to be written to before a write process in a predetermined data area of a memory cell array holding either a first value or a second value per bit; a conversion determination section configured such that upon selectively allowing said pre-read data to transition to either a first conversion candidate or a second conversion candidate of the write data to be written in said write process, said conversion determination section generates a determination result for selecting either said first conversion candidate or said second conversion candidate based on the larger of two values of which one is the number of bits transitioning from said first value to said second value upon transition of said pre-read data to said first conversion candidate and of which the other is the number of bits transitioning from said second value to said first value upon transition of said pre-read data to said first conversion candidate; and a conversion control section configured to select either said first conversion candidate or said second conversion candidate in accordance with said determination result while outputting selection information indicative of which of the two candidates has been selected.