Patent ID: 9329208
Filing Date: 2016-05-03
CPC Classification: G01R

Claim Text:
1. A method of measuring a negative voltage using a device including a first transistor and a second transistor, the first transistor being coupled to the second transistor and the negative voltage being supplied to a gate of the second transistor, the method comprising: setting a voltage of a source of the first transistor to a first supply voltage; when the voltage of the source of the first transistor is set to the first supply voltage and a current through the first transistor is equivalent to a current through the second transistor, comparing a first source-drain voltage of the first transistor to a second source-drain voltage of the second transistor; and when the voltage of the source of the first transistor is set to the first supply voltage and the first source-drain voltage of the first transistor is equivalent to the second source-drain voltage of the second transistor and the current through the first transistor is equivalent to the current through the second transistor, determining a magnitude of the negative voltage by determining a positive voltage of a node of the device.