Patent ID: 9455312
Filing Date: 2016-09-27
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit comprising the steps: forming a first layer of interconnect; depositing a first etch stop layer on said first layer of interconnect; depositing a first ILD layer on said first etch stop layer; depositing a capacitor bottom plate material over the first ILD layer; depositing a capacitor dielectric material over the capacitor bottom plate material; depositing a capacitor top plate material over the capacitor dielectric material; depositing a second etch stop layer over the capacitor top plate material; forming a capacitor top plate photoresist pattern and etching the second etch stop layer, the capacitor top plate material and the capacitor dielectric material using the capacitor top plate photoresist pattern; removing the capacitor top plate photoresist pattern; after removing the capacitor top plate photoresist pattern, depositing a third etch stop layer; forming a capacitor bottom plate photoresist pattern over the third etch stop layer and etching the third etch stop layer and the capacitor bottom plate material using the capacitor bottom plate photoresist pattern; depositing a second ILD layer; forming a via pattern on said second ILD layer with a first via over said first layer of interconnect, a second via over the capacitor bottom plate material, and a third via over the capacitor top plate material; using the via pattern, simultaneously extending the first via, second via, and third via by etching said second ILD layer with said plasma via etch until said first via reaches said first etch stop layer, wherein the second via extends through the second ILD to the third etch stop layer and the third via extends through the second ILD and the third etch stop layer to the second etch stop layer; and simultaneously etching said first etch stop layer at a bottom of the first via, said third etch stop layer at a bottom of the second via, and said second etch stop layer at a bottom of the third via with a plasma etch stop etch.