Patent ID: 9337869
Filing Date: 2016-05-10
CPC Classification: H03M

Claim Text:
1. A circuit for BCH encoding and syndrome computing, capable of processing p parallel computation, comprising: an encoding unit, for encoding one message having k bits as one BCH codeword having n bits after processing a first iterative operation, the first iterative operation being processed to receive p bits sequentially in each clock and output the BCH codeword after [n/p] clocks; a syndrome computing unit, for obtaining 2t syndromes each having m bits from one BCH codeword having n bits after processing a second iterative operation, the second iterative operation being processed to receive p bits sequentially in each clock and output the syndromes after [n/p] clocks; a plurality of multiplexers, each being used to receive a first intermediate computing result generated from the first iterative operation and a second intermediate computing result generated from the second iterative operation, wherein when the first iterative operation processes, the first intermediate computing result is outputted, and when the second iterative operation processes, the second intermediate computing result is outputted; and a plurality of registers, each being used to receive the first intermediate computing result or the second intermediate computing result from a corresponding multiplexer, or the second intermediate computing result from a syndrome computing unit, and outputting the first intermediate computing result to the encoding unit or the second intermediate computing result to the syndrome computing unit in a later clock after the first intermediate computing result or the second intermediate computing result is received, wherein k, n, p and t are positive integers, n is greater than k and m is the power of 2 over GF(2