Patent ID: 9425119
Filing Date: 2016-08-23
CPC Classification: B81B,G01L,H01L

Claim Text:
1. A method for fabricating a package structure, comprising the steps of: preparing a first wafer and a chip disposed on the first wafer, wherein the first wafer has opposite first and second surfaces and the first surface of the first wafer has a groove, a thin film closing an open end of the groove and a plurality of electrical contacts, and the chip has a third surface with a conductive layer, an opposite fourth surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the first surface of the first wafer in a manner that the seal ring surrounds the thin film of the first wafer and the electrical contacts are located outside the seal ring; electrically connecting the electrical contacts of the first wafer and the conductive layer of the chip through a plurality of first conductive wires; forming an encapsulant on the first surface of the first wafer for encapsulating the chip, the electrical contacts and the first conductive wires; removing a portion of the encapsulant and a portion of the first conductive wires from a top surface of the encapsulant so as to form a plurality of sub-conductive wires, wherein one ends of the sub-conductive wires are exposed from the encapsulant and the other ends of the sub-conductive wires are in electrical connection with the electrical contacts of the first wafer; and forming a through hole penetrating the first surface and the second surface of the first wafer and communicating with the concave portion of the chip.