Patent ID: 9398238
Filing Date: 2016-07-19
CPC Classification: H04N

Claim Text:
1. A semiconductor device, comprising: a pixel array portion in which unit pixels are disposed in a matrix of columns and rows and vertical signal lines are connected to the unit pixels configured to provide readout signals from the unit pixels; an analog to digital conversion portion including a comparing processing portion and a counting processing portion; the comparison processing portion configured to compare the unit pixels with a reference signal whose level is gradually changed, the counting processing portion configured to carry out a counting operation to convert an analog unit signal into digital data based on a comparison result in the comparison processing portion by using a counting clock for analog-to-digital conversion; the analog to digital conversion portion being configured to perform analog to digital conversion processing for acquiring digital data of the readout signals on the basis of output data of the counting processing portion; and an operating current supplying portion, including transistors, at least one of the transistors having a gate terminal, a first current terminal and a second current terminal, the first current terminal being connected to at least one of the vertical signal lines at a node between the pixel array portion and the AD conversion portion, the second current terminal being connected to a reference current source, and the gate terminal being connected to a control signal line, wherein power consumption is configured to be lower in a first operation mode than a second operation mode, where during the first operation mode only the readout signals from the unit pixels that are required are readout and during a second operation mode the readout signals from all of the unit pixels are readout.