Patent ID: 9300462
Filing Date: 2016-03-29
CPC Classification: H03F,H04B,H04J,H04L

Claim Text:
1. A signal processing circuit comprising: a synchronization reference generator configured to receive a trigger signal and capable in response to the trigger signal of adding an internal synchronization signal to a digital input signal to generate a digital composite RF signal; a first digital signal processor configured to receive the digital composite RF signal and generate a first digital signal; a first digital to analog converter configured to receive the first digital signal and generate a RF output signal; a coupling element configured to receive the RF output signal and generate a derived RF output signal; a second digital signal processor configured to receive the digital RF input signal and generate a second digital signal; a second digital to analog converter configured to receive the second digital signal and generate a reference signal; a subtraction block configured to receive the derived RF output signal and the reference signal, wherein the subtraction block is configured to generate an error signal; a detector block configured to receive the error signal and generate a digital error signal; and a digital processor unit configured to receive the digital RF input signal and the digital error signal, wherein the digital processor unit controls one or more of the first digital signal processor, the second digital signal processor, the first digital to analog converter, the second digital to analog converter, the subtraction block and the detector block.