Patent ID: 9508685
Filing Date: 2016-11-29
CPC Classification: H01L

Claim Text:
1. A method to fabricate a three-dimensionally integrated semiconductor device, the method comprising: depositing an amorphous/porous silicon layer on a first surface of a first wafer; positioning a first surface of a second wafer over the amorphous/porous silicon layer such that the first surface of the second wafer overlaps the first surface of the first wafer; bonding the first wafer and the second wafer with the amorphous/porous silicon layer between the first wafer and the second water; heat-treating the bonded first wafer and the second wafer effective to facilitate a reaction between a first portion of the amorphous/porous silicon layer and a first conductive coupler surface and also effective to facilitate a reaction between a second portion of the amorphous/porous silicon layer and a second conductive coupler surface to form silicide, removing the unreacted portions of the amorphous/porous silicon layer between the first wafer and the second wafer.