Patent ID: 9443773
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a vertical bipolar transistor in a CMOS process, comprising: forming a collector by: implanting an impurity of a first type into a substrate to form n-wells in the substrate and separated from one another at a predefined spacing; and connecting, after implanting the n-wells, the n-wells by laterally diffusing the impurity of the first type from each of said n-wells into a portion of the substrate between the n-wells; forming a halo implant using an impurity of a second type and a shallow implant using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over the laterally-diffused impurities of the collector, said halo implant vertically separating the shallow implant from the laterally-diffused impurities of the collector; forming, laterally spaced from the halo implant, a further implant using an impurity of the second type for providing a conductive connection through a MOSFET channel and to the halo implant, wherein the MOSFET channel is formed in one of the n-wells; and providing respective conductive connections to the further implant, the shallow implant and the collector allowing at least a portion of each of the shallow implant, the halo implant and the collector to be respectively operable as an emitter, base and collector of the vertical bipolar transistor.