Patent ID: 9391075
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. An integrated circuit, comprising: a first FET structure and a second FET structure, both of which being formed over a silicon substrate, and wherein the first FET structure comprises: and wherein the second FET structure comprises: a low resistance material layer comprising a low resistance tungsten material or a low resistance doped amorphous silicon material formed over and in contact with the second workfunction material layer, wherein the low resistance material layer fills an entirety of the area between the second portion of the second high-k material layer not filled by the second workfunction material layer; a second barrier material layer comprising the barrier material formed over and in contact with both of the second workfunction layer and over the low resistance material layer and between and along a mid-section of the second portion of the second high-k material layer, wherein the second barrier material layer does not completely fill the area between the mid-section of the second portion of the second high-k material formed along the sidewalls of the vertically-oriented dielectric material structures; and