Patent ID: 9510453
Filing Date: 2016-11-29
CPC Classification: H01L,H05K,Y10T

Claim Text:
1. A package carrier suitable for carrying at least a chip, the package carrier comprising: an insulating layer having a first surface and a second surface opposite to each other; a patterned circuit layer, embedded in the second surface of the insulating layer and having a bonding surface, wherein the second surface of the insulating layer and the bonding surface of the patterned circuit layer are coplanar, and the patterned circuit layer comprises at least one die pad; a plurality of conductive connection structures embedded in the insulating layer and connected to the patterned circuit layer; a plurality of pads disposed on the first surface of the insulating layer and respectively connected to the conductive connection structures; a solder resist layer disposed on the second surface of the insulating layer wherein a portion of the bonding surface of the patterned circuit layer is exposed by the solder resist layer; and a surface treatment layer disposed on the bonding surface of the patterned circuit layer, wherein a portion of the surface treatment layer is located between the chip and the die pad, a height difference is formed between a first top surface of the solder resist layer and a second top surface of the surface treatment layer so as to form a cavity between a sidewall of the solder resist layer and the second top surface of the surface treatment layer, and portions of the chip is embedded in the cavity formed by the solder resist layer and surface treatment layer, and a bottom surface of the chip is lower than the first top surface of the solder resist layer.