Patent ID: 9331174
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a semiconductor substrate; a transistor gate electrode at the surface of said semiconductor substrate; a gate dielectric on said surface of the semiconductor substrate beneath the transistor gate electrode, said gate dielectric having a thickness from about 0.5 to about 20 nanometers; an offset spacer abutting the transistor gate electrode at each end of the transistor gate; a recess in said surface at said each end; an epi layer of doped silicon germanium (SiGe) or silicon carbide (SiC), said epi layer epitaxially grown in, and filling, each said recess to said surface; a source/drain spacer on an end of said epi layer at said surface abutting said offset spacer at said each end; a source/drain extension under each said source/drain spacer, the portion of a respective said epi layer under said each source/drain spacer forming each said source/drain extension; and a source/drain diffusion region formed in said epi layer and said recess at said each source/drain extension, wherein the source/drain spacers above said each source/drain extension delimit said source/drain regions.