Patent ID: 9406569
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method of reducing leakage from a gate channel of a semiconductor device, comprising: forming first and second trenches through an active semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate, the first and second trenches defining the gate channel therebetween; forming at least one trench storage element in the SOI substrate and adjacent the gate channel, and forming at least one trench isolation element in the SOI substrate and in contact with the trench storage element depositing impurities in at least one leakage region within the active semiconductor layer of the gate channel; forming a diffusion barrier layer between the impurities and an upper surface of the gate channel, and annealing the diffusion barrier layer so as to prevent the impurities from diffusing therethrough such that a voltage threshold at the at least one leakage region is increased; and forming a gate directly over the gate channel containing the impurities and above the diffusion barrier layer such that the impurities are contained in the gate channel without extending beyond the gate channel.