Patent ID: 9437270
Filing Date: 2016-09-06
CPC Classification: G11C

Claim Text:
1. A nonvolatile memory apparatus comprising: a memory cell coupled to a bit line and a source line; a word line configured to select the memory cell; a first local switch block configured to provide at least one of a write voltage, a read voltage, and a source line voltage to the bit line in response to a first local switch select signal; a second local switch block configured to provide at least one of the write voltage and the source line voltage to the source line in response to a second local switch select signal; a first data write/read circuit configured to provide the write voltage, the read voltage, and the source line voltage to the first local switch block in response to a column address signal, a write signal, data, and a read signal; and a second data write/read circuit configured to provide the write voltage and the source line voltage to the second local switch block in response to the column address signal, the write signal, the data, and the read signal, wherein the first and second local switch select signals are enabled at logic high levels and the first and second local switch select signals are enabled at different voltage levels from each other.