Patent ID: 9337250
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands of the substrate; an insulation layer formed on the surface of the substrate, with a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer, wherein an entire region of the semiconductor chip projected onto the substrate covers only a portion of an outermost one of the passive devices, and the outermost one of the passive devices protrudes 0.1 to 1.5 mm from the entire region of the semiconductor chip projected onto the substrate, wherein the passive devices comprise a plurality of non-RF passive devices and at least one RF passive device; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; and an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip.