Patent ID: 9276596
Filing Date: 2016-03-01
CPC Classification: H03M

Claim Text:
1. An analog to digital converting apparatus, comprising: a first switching capacitor unit, having a plurality of first capacitors and a plurality of first switches respectively corresponding to the first capacitors, wherein the first switching capacitor unit couples each of the first capacitors to a first logic voltage, a second logic voltage, or a first input voltage to generate a first voltage through one of the corresponding first switches according to a first control signal; a second switching capacitor unit, having a plurality of second capacitors and a plurality of second switches respectively corresponding to the second capacitors, wherein the second switching capacitor unit couples each of the second capacitors to the first logic voltage, the second logic voltage, or a second input voltage to generate a second voltage through one of the corresponding second switches according to the first control signal; a circuit unit, generating the first control signal by comparing the first voltage and the second voltage; a first and second initialization switches, respectively serially connected between the first voltage and a common-mode endpoint and between the common-mode endpoint and the second voltage, and being turned on or off according to a second control signal; a third capacitor and a fourth capacitor, respectively receiving the first and second voltages and commonly coupled to the common-mode endpoint; and a logic buffer, choosing to output the first logic voltage or the second logic voltage to the common-mode endpoint according to the second control signal, wherein the second control signal indicates whether the analog to digital converting apparatus is in a sampling period or not.