Patent ID: 9431293
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A wiring structure for an integrated circuit device, comprising: a first metal line formed within an interlevel (ILD) dielectric layer; a second metal line formed in the ILD layer adjacent the first metal line; a plurality of metal cap regions formed over the first and second metal lines, the plurality of metal cap regions of the first metal line and the second metal line being at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and a conformal insulator layer formed over the metal cap regions and uncapped regions of the first metal line and the second metal line; wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.