Patent ID: 9369115
Filing Date: 2016-06-14
CPC Classification: G11C,H03K,Y10T

Claim Text:
1. A voltage doubler comprising: a first transistor connected between a first node and an input terminal configured to receive an input voltage; a second transistor connected between the input terminal and a second node; a third transistor connected between the first node and an output terminal configured to output an output voltage; a fourth transistor connected between the second node and the output terminal; a first capacitor connected between the first node and a first clock terminal configured to receive a first clock signal; a second capacitor connected between the second node and a second clock terminal configured to receive an inverted first clock signal; a first gate control unit configured to control the first and second transistors using the first clock signal and the inverted first clock signal; a second gate control unit configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal; and a load capacitor connected between the output terminal and a ground terminal.