Patent ID: 9461925
Filing Date: 2016-10-04
CPC Classification: H04L

Claim Text:
1. An apparatus, comprising: a memory; and a processor coupled to the memory, the processor configured to be coupled to a plurality of rate counters, each rate counter from the plurality of rate counters being associated with a different network device from a plurality of network devices associated with a level from a plurality of levels within a hierarchy of a network, the processor configured to begin execution of a first page of a first rate program, the first rate program including a linked list of a plurality of pages; the processor configured to send, during a first time period and in response to the execution, transmission credits to a first subset of rate counters from the plurality of rate counters based on execution of the first page of the first rate program, the processor configured to send, during a second time period after the first time period and prior to executing a second page of the linked list of the plurality of pages of the first rate program, transmission credits to a second subset of rate counters from the plurality of rate counters based on execution of a page of a second rate program and based on a priority of the second rate program being no lower than a priority of the first rate program, the second rate program including a linked list of a plurality of pages, the first subset of rate counters being mutually exclusive from the second subset of rate counters.