Patent ID: 9385185
Filing Date: 2016-07-05
CPC Classification: H01L,H03K

Claim Text:
1. A semiconductor device comprising: a transistor; a first guard ring of first conductivity type that forms a perimeter around the transistor and that is configured to receive a first bias; a second guard ring of second conductivity type opposite the first conductivity type, that forms a perimeter around the first guard ring and that is configured to receive the first bias; a third guard ring of the first conductivity type that forms a perimeter around the second guard ring and that is configured to receive a second bias that is different from the first bias; and a substrate, wherein a first depth of the first guard ring is deeper in the substrate than a second depth of the second guard ring in the substrate, wherein the first and second guard rings of the opposite first and second conductivity types, respectively, are electrically shorted together and to a bias terminal that is configured to provide the first bias to the first and second guard rings, and wherein the second guard ring is configured to block movement of charges from a drain electrode in the transistor such that the charges gather in the first guard ring.