Patent ID: 9245806
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming a gate stack layer including a high-k layer, a metal-containing layer on a semiconductor substrate having an NMOS region and a PMOS region; introducing arsenic to the gate stack layer in the NMOS region; introducing aluminum to the gate stack layer in the PMOS region; and etching the gate stack layer, where the arsenic and the aluminum are introduced, to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively, wherein the gate stack layer in the NMOS region includes a capping layer, wherein the capping layer has a lanthanum oxide and is located below the metal-containing layer and over the high-k layer, and wherein the gate stack layer in the PMOS region does not include the capping layer.