Patent ID: 9418997
Filing Date: 2016-08-16
CPC Classification: H01L,Y10S

Claim Text:
1. A semiconductor structure, comprising: a semiconductor substrate comprising an N well region having a first semiconductor fin protruding therefrom and a P well region having a second semiconductor fin protruding therefrom, the first semiconductor fin spaced apart from the second semiconductor fin, wherein the N well region is directly adjacent to the P well region in the semiconductor substrate: a trench isolation layer disposed on the semiconductor substrate between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer; a gate dielectric layer disposed on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins; a p type metal gate layer disposed over the gate dielectric layer over the first semiconductor fin but not over the second semiconductor fin, wherein the p type metal gate layer is further disposed on a portion of but not all of the trench isolation layer; and an n type metal gate layer disposed over the gate dielectric layer over the second semiconductor fin, wherein the n type metal gate layre is further disposed over the trench isolation layer and over the p type metal gate layer.