Patent ID: 9450598
Filing Date: 2016-09-20
CPC Classification: G01S,H04B

Claim Text:
1. A two-stage digital down-conversion system, comprising: A. an analog to digital converter (ADC) responsive to an applied analog signal, generating a digital output signal at a digital output, wherein the digital output is represented by a succession of digital samples, representing succession of samples of the input signal; B. a first-stage digital down-conversion (DDC) module generating first-stage quadrature digital components I1 and Q1, comprising: C. a first stage I/Q memory for storing first-stage quadrature data; D. a first stage I/Q processor module, performing first-stage amplitude envelope, phase and frequency detection E. a second stage DDC module, generating second-stage quadrature components I2/Q2, based on first stage I1/Q1 quadrature components, comprising: