Patent ID: 9245977
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A method of making a vertical double-diffusion MOS (VDMOS) transistor, the method comprising: a) etching an isolated oxide layer formed on a surface of an epitaxial structure to define an active region of said VDMOS transistor; b) injecting a first dopant into said active region, and diffusing said first dopant to form a doping region, wherein said doping region comprises a body region for said VDMOS transistor; c) after said body region is formed, forming a gate oxide layer on a surface of said active region; d) depositing polysilicon on said gate oxide layer, and etching said polysilicon to form a gate; e) injecting a second dopant at an end of said gate to form a source in said body region, wherein said first and second dopants have opposite types; f) forming a contact hole adjacent to said gate, and injecting a third dopant into said contact hole, wherein said first and third dopants have a same type; g) depositing and etching aluminum on a chip surface; and h) coating said aluminum and said chip surface with a passivation layer.