Patent ID: 9442733
Filing Date: 2016-09-13
CPC Classification: G06F

Claim Text:
1. An apparatus comprising: a first packed data operation mask register to store a first packed data operation mask which is to have a first plurality of packed data operation mask bits; a second packed data operation mask register to store a second packed data operation mask which is to have a second plurality of packed data operation mask bits; a decode unit to decode a packed data operation mask comparison instruction, the packed data operation mask comparison instruction to indicate the first packed data operation mask register and to indicate the second packed data operation mask register, wherein each packed data operation mask bit of the first plurality is to correspond to a packed data operation mask bit of the second plurality in a corresponding position; and an execution unit coupled with the first and second packed data operation mask registers and coupled with the decode unit, the execution unit, in response to the packed data operation mask comparison instruction, to: modify a first flag to a first value if a result of a bitwise operation on each packed data operation mask bit of the first packed data operation mask and each corresponding packed data operation mask bit of the second packed data operation mask is zero, or otherwise modify the first flag to a second different value; and modify a second flag to one of the first and second values.