Patent ID: 9484355
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate including a cell array region and a peripheral circuit region; a stack structure disposed on the cell array region, the stack structure including a plurality of electrodes and a plurality of insulating layers alternately stacked; a plurality of first peripheral gate structures disposed on a first region of the peripheral circuit region and extended in a first direction, wherein the plurality of first peripheral gate structures is spaced apart from each other at a first distance along a second direction crossing the first direction; a plurality of first residual spacers disposed in the first region, wherein at least two first residual spacers are interposed between two adjacent first peripheral gate structures; a plurality of second peripheral gate structures disposed on a second region of the peripheral circuit region, wherein the plurality of second peripheral gate structures is spaced apart from each other at a second distance along the second direction; a plurality of second residual spacers disposed in the second region, wherein one second residual spacer is interposed between two adjacent second peripheral gate structures; a first peripheral contact plug connected to the substrate and interposed between at least two first residual spacers; and a second peripheral contact plug connected to the substrate and penetrating one second residual spacer interposed between two adjacent second peripheral gate structures.