Patent ID: 9355054
Filing Date: 2016-05-31
CPC Classification: G06F,G11C,H04L

Claim Text:
1. A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link apparatus, comprising: a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link; a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link; a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link; and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link; wherein: the clock transmitting circuit and the data transmitting circuit are adapted to transmit the clock signal and the data signal in phase during a calibration mode; the clock transmitting circuit and the data transmitting circuit are adapted to transmit the clock signal and the data signal out of phase during a normal operation mode; the clock signal and the data signal are transmitted in a first direction on the first lane and the second lane, respectively, in the normal operation mode; the clock signal and the data signal are transmitted in a second direction on the first lane and the second lane, respectively, in the calibration mode; and the second direction is opposite of the first direction.