Patent ID: 9318158
Filing Date: 2016-04-19
CPC Classification: G11C

Claim Text:
1. A memory cell comprising: a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node; a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail; a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and a third power rail; a column decode and control circuit configured to apply a same voltage to the first and second power rails during a write operation while the internal node is at a different voltage than the same voltage; a second transistor coupled between the first current electrode of the first transistor and the first bitline, the second transistor having a first current electrode coupled to the first bitline, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode coupled to the read wordline; a third transistor having a first current electrode coupled to a second bitline, a control electrode coupled to a write wordline, and a second current electrode coupled to the internal node, wherein the first bitline and the second bitline are a same bitline.