Patent ID: 9525425
Filing Date: 2016-12-20
CPC Classification: H03H,H03L,H03M

Claim Text:
1. A sample rate converter for converting an input signal sampled at a first sample rate to an output signal sampled at an output sample rate different from the first sample rate, the sample rate converter comprising: a frequency synthesizer configured to produce a clock signal; a cross enable unit configured to accept the clock signal and the input signal and to generate a count disparity signal and a de-jittered signal sampled at substantially a mean of the first sample rate from the input signal and the clock signal; and a linear interpolation unit configured to generate the output signal at a sample rate of the clock signal from the de-jittered signal, the clock signal, and the count disparity signal, wherein the linear interpolation unit includes a first sigma delta loop, wherein the linear interpolation unit calculates a difference between successive samples of the de-jittered signal on each clock cycle of the de-jittered signal and inputs the difference to the first sigma delta loop, wherein the first sigma delta loop divides the difference by a predetermined value to obtain an integral part and a remainder part, and wherein the predetermined value is based on the output sample rate.