Patent ID: 9454051
Filing Date: 2016-09-27
CPC Classification: G02F,H01L

Claim Text:
1. A display panel, comprising: an array substrate; wherein the array substrate comprises data lines, scan lines, and a plurality of pixel units formed by crisscrossing the data lines and scan lines; wherein each of the pixel units comprises: a main pixel portion having a first thin film transistor, wherein a first insulation layer is disposed between a first grid electrode of the first thin film transistor and a first source electrode and a first drain electrode of the first thin film transistor; and the first source electrode is connected to the first drain electrode through a semiconductor layer; a sub-pixel portion having a second thin film transistor, wherein a second insulation layer is disposed between a second grid electrode of the second thin film transistor and a second source electrode and a second drain electrode of the second thin film transistor; and the second source electrode is connected to the second drain electrode through another semiconductor layer; wherein a second distance is larger than a first distance; a ratio of the second distance to the first distance is in the range of 1.25-2; the first distance is a thickness of the first insulation layer which is between the first grid electrode of the first thin film transistor and the semiconductor layer of the first thin film transistor; and the second distance is a thickness of the second insulation layer which is between the second grid electrode of the second thin film transistor and the semiconductor layer of the second thin film transistor.