Patent ID: 9396771
Filing Date: 2016-07-19
CPC Classification: G11C

Claim Text:
1. A memory device which has a burst length “b”, performs “k” core accesses per command, and receives a command, where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b”, the memory device comprising: a memory cell array comprising a plurality of bank groups; a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group; and a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signals output from the plurality of bank group control units, wherein data items in output data of the multiplexer have a same duration, wherein a time delay between an access to one of the bank groups and a next access to the same one of the bank groups is set to 4 clock cycles and a time delay between an access to the one of the bank groups and a next access to another of the bank groups is set to 2 clock cycles.