Patent ID: 9484807
Filing Date: 2016-11-01
CPC Classification: H02M,Y02B

Claim Text:
1. A switched capacitor voltage regulator circuit, including: (a) a pump capacitor having a first node and a second node; (b) at least one output capacitor; (c) a first switch coupled between an input voltage Vin and the first node of the pump capacitor; (d) a second switch coupled between a first auxiliary voltage source and the first node of the pump capacitor, wherein the first auxiliary voltage source is independent of Vin; (e) at least one third switch between the second node of the pump capacitor and at least one corresponding output capacitor; (f) a fourth switch coupled between a second auxiliary voltage source and the second node of the pump capacitor, wherein the second auxiliary voltage source is independent of Vin; and (g) a clock signal, electrically coupled to each of the first, second, third, and fourth switches, for generating a first clock phase and a second clock phase; wherein during the first clock phase, the first and third switches are open, and the second and fourth switches are closed, thereby charging the pump capacitor to a voltage ΔV equal approximately to the second auxiliary voltage minus the first auxiliary voltage; and wherein during a second clock phase, the first and third switches are closed, and the second and fourth switches are open, thereby coupling the input voltage Vin to the pump capacitor and coupling the pump capacitor to at least one output capacitor, thereby charging at least one output capacitor to an output voltage Vout approximately equal to Vin+ΔV.