Patent ID: 9331030
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A manufacturing method of an integrated antenna package, comprising: providing a first metal layer; disposing a chip on the first metal layer, wherein the chip includes a first contact pad and a second contact pad, wherein the first contact pad and the second contact pad faces the first metal layer, and the first contact pad and the second contact pad are electrically connected with the first metal layer; press laminating a multilayer board over the first metal layer and the chip, wherein the multilayer board comprises a filling layer and a second metal layer, and the second metal layer is disposed on the filling layer and electrically connected to the first metal layer and the chip is embedded within the filling layer; patterning the first metal layer; covering a multi-layered substrate to the patterned first metal layer, wherein one side of the multi-layered substrate away from the first patterned metal layer has a third metal layer; forming a through-hole penetrating the multi-layered substrate and terminating at the patterned first metal layer electrically connected to the first contact pad; forming a plated via structure in the through-hole and the plated via structure connects the third metal layer and the first contact pad; and patterning the second metal layer and the third metal layer to form a patterned second metal layer and a patterned third metal layer, wherein the patterned third metal layer includes an antenna pattern located beneath the chip, and the antenna pattern is electrically coupled to the chip through the plated via structure.