Patent ID: 9361201
Filing Date: 2016-06-07
CPC Classification: G06F,G11C

Claim Text:
1. A memory system comprising: a NAND-type flash memory comprising a plurality of blocks; and a memory controller configured to control the NAND-type flash memory, wherein the memory controller comprises: a monitoring module configured to acquire a time elapsed from a start of erase of data written in a first block before new data write in the first block is completed; and a determination module configured to determine whether a probability that an error occurs in the data write in the first block is high, based on whether the elapsed time has exceeded a reference time associated with holding of erase state, before completion of the data write in the first block, wherein the memory controller further comprises: an erase time management module configured to store, in a table, erase time information representing a relative time measured in accordance with the start of the data erase of the first block; a data movement controller configured to execute a data movement operation of moving first valid data from a plurality of blocks in the NAND-type flash memory in each of which comprises a first area where the first valid data is stored and a second area where first invalid data is stored to a third block that has undergone the data erase in the NAND-type flash memory, the first invalid data being data which is changed from second valid data and in which is invalidated by, in a state in which the second valid data is stored in the second area, writing update data for updating the second valid data in a fourth block that has undergone the data erase in the NAND-type flash memory; and a priority data movement management module configured to, in the data movement operation by the data movement controller, preferentially move valid data from the first block for which the data write has been ended halfway.