Patent ID: 9236888
Filing Date: 2016-01-12
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A storage device comprising: a semiconductor memory including one or more word lines and one or more memory cells, and configured to store a first code word and a second code word, the memory cells being capable of respectively storing a plurality of bits, and a plurality of the memory cells being connected to one word line being capable of storing a plurality of pages; and a controller configured to read out the first code word from one page among the plurality of pages of the semiconductor memory, and the second code word written in a page other than the page corresponding to the first code word among the plurality of pages, wherein the controller performs error correction processing using the first and the second code word read out from the semiconductor memory, re-reads the first code word when the first code word has not been able to be corrected, and the second code word has been able to be corrected, by the error correction processing, and determines each bit value of the first code word using a read-out result by the re-reading, and a bit value of each bit of the second code word after error correction.