Patent ID: 9361961
Filing Date: 2016-06-07
CPC Classification: G11C

Claim Text:
1. A memory device comprising: a plurality of memory banks; a row control signal input unit suitable for receiving a plurality of row control signals, wherein the row control signals include one or more row control signals and one or more first address signals; a column control signal input unit suitable for receiving a plurality of column control signals, wherein the column control signals include one or more column control signals and one or more second address signals; a row control unit suitable for selecting a first memory bank among the plurality of memory banks and a row in response to the row control signals, and controlling a row operation for the selected row; and a column control unit suitable for selecting the first memory bank or another memory bank among the plurality of memory banks and a column in response to the column control signals, and controlling a column operation for the selected column, wherein the row control signal input unit sequentially receives the row control signals through a plurality of row input pads, and the column control signal input unit sequentially receives the column control signals through a plurality of column input pads, and wherein one or more row input pads among the plurality of row input pads receives the row control signals and the first address signals, and one or more column input pads among the plurality of column input pads receives the column control signals and the second address signals.