Patent ID: 9436543
Filing Date: 2016-09-06
CPC Classification: B60R,G06F

Claim Text:
1. An electronic device comprising a clock unit and a processing unit connected to said clock unit, said clock unit arranged to generate an output clock signal, said processing unit arranged to be clocked by said output clock signal, said clock unit having: a normal mode in which said output clock signal has a low amount of jitter and a normal clock rate to enable normal use of said electronic device and a failure analysis mode in which said output clock signal has a high amount of jitter or a reduced clock rate, or a high amount of jitter combined with a reduced clock rate, to impede said normal use; wherein said clock unit is protected against unauthorized re-activation of said normal mode, and said output clock signal has a shortest possible high time and a shortest possible low time which are not shorter in said analysis mode than in said normal mode.