Patent ID: 9472415
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a semiconductor structure including a source-drain region in a substrate and adjacent to a gate structure and a nitride layer on the source-drain region, wherein the gate structure includes a gate, a gate cap on a top surface of the gate, and a gate spacer on a sidewall surface of the gate and a sidewall surface of the gate cap; forming a dielectric layer on the nitride layer and on the gate structure; forming a contact trench in the dielectric layer by iteratively etching until the nitride layer is exposed, the contact trench exposing the gate cap and the gate spacer, each iterative etching step comprising: forming a nitride trench in the nitride layer by iteratively etching until the source-drain region is exposed, each iterative etching step comprising: