Patent ID: 9372665
Filing Date: 2016-06-21
CPC Classification: G06F

Claim Text:
1. A method for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising: generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function implemented via corresponding AND gates to produce na times nb single bit products; selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na−1 multiplied with the second operand bits 0 to nb−2 implemented via corresponding XOR gates; selectively inverting the single bit products of the signed first operand bits 0 to na−2 multiplied with the signed second operand bit nb−1, implemented via corresponding XOR gates; adding the single bit products in accordance with their respective order for producing an intermediate product after both the steps of selectively inverting; and adding a ‘1’ bit value at bit positions nb−1, na−1 and na+nb−1 for receiving a final product.