Patent ID: 9274960
Filing Date: 2016-03-01
CPC Classification: G06F,Y02D

Claim Text:
1. A computer system comprising: multiple processor cores; a main memory; at least one local cache memory associated with and operatively coupled to each core for storing cache lines accessible only by the associated core, each of the cache lines being classified as either a shared cache line or a private cache line; and a global cache memory, the global cache memory being operatively coupled to the local cache memories and main memory and accessible by the cores, the global cache memory being capable of storing a plurality of cache lines, and wherein when a core writes a cache line, the core performs a write-back to the associated local cache memory if the cache line is a private cache line and a write-through to the global cache memory if the cache line is a shared cache line, wherein at least one of the shared cache lines are in a valid state, an invalid state, or a transient dirty state, and wherein a shared cache line in a local cache memory transitions to the transient dirty state from the valid state or the invalid state when the cache line is written by the associated core, and wherein a shared cache line in the transient dirty state transitions to the valid state with a self-initiated write-through to the global cache memory.