Patent ID: 9240223
Filing Date: 2016-01-19
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a first internal power line configured to provide a driving voltage comprising a power supply voltage and a ground voltage, the first internal power line comprising a first signal line configured to provide the power supply voltage and a second signal line configured to provide the ground voltage; a second internal power line configured to provide a gate voltage comprising a gate power supply voltage and a gate ground voltage, the second internal power line comprising a third signal line configured to provide the gate power supply voltage and a fourth signal line configured to provide the gate ground voltage; a plurality of driving signal generators configured to generate a plurality of driving signals based on the gate voltage; and a plurality of load drivers configured to drive a plurality of loads based on the driving voltage and the driving signals, wherein the first signal line is connected to a first node of an external power line, and the third signal line is connected to a second node of the external power line, the second node being different from the first node, and wherein a cross-sectional area of the first internal power line is greater than a cross-sectional area of the second internal power line and a resistance of the first internal power line is less than a resistance of the second internal power line.