Patent ID: 9269729
Filing Date: 2016-02-23
CPC Classification: G02F,H01L

Claim Text:
1. A method for manufacturing a thin film transistor array panel, comprising: disposing a thin film transistor including a drain electrode on a substrate; disposing a passivation layer on the thin film transistor and the substrate; depositing a transparent organic material on the passivation layer and patterning the transparent organic material to form a partition including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode; forming a color filter in a region defined by the partition through an Inkjet printing method; depositing an organic capping layer covering the partition and the color filter; removing a portion of the organic capping layer aligned with the drain electrode; removing a contact portion of the partition and a portion of the passivation layer by a dry etch method to form a contact hole which exposes the drain electrode; and electrically connecting a pixel electrode to the drain electrode through the contact hole.