Patent ID: 9356013
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type disposed adjacent to the first semiconductor region; a third semiconductor region and a fourth semiconductor region of the second conductivity type disposed over or at least partially within the first semiconductor region, a fifth semiconductor region of the first conductivity type disposed between the third and fourth semiconductor regions, and a first gate disposed over the fifth semiconductor region; wherein the fifth semiconductor region is of the same type as the first semiconductor region and the fifth semiconductor region comprises a dopant concentration smaller than the first semiconductor region; a sixth semiconductor region and a seventh semiconductor region of the first conductivity type disposed over or at least partially within the second semiconductor region, an eighth semiconductor region of the second conductivity type disposed between the sixth and seventh semiconductor regions, and a second gate disposed over the eighth semiconductor region; wherein the eighth semiconductor region is of the same type as the second semiconductor region and the eighth semiconductor region comprises a dopant concentration smaller than the second semiconductor region; wherein the third semiconductor region is coupled to a first region of the first gate, and the seventh semiconductor region is coupled to a second region of the first gate; and wherein the fourth semiconductor region is coupled to a first region of the second gate and the sixth semiconductor region is coupled to a second region of the second gate.