Patent ID: 9368509
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a three-dimensional memory structure, comprising: forming a stack of alternating layers comprising first material layers and second material layers over a substrate; forming a temporary material layer over the stack; forming a memory opening through the temporary material layer and the stack; forming a memory film and a semiconductor channel in the memory opening; forming a first backside recess by removing the temporary material layer and a portion of the memory film that adjoins the temporary material layer, wherein a portion of a sidewall of the semiconductor channel is physically exposed to the first backside recess; introducing electrical dopants through the physically exposed portion of the sidewall of the semiconductor channel and into a portion of the semiconductor channel, which is converted into a drain region forming a trench through the temporary material layer and the stack; removing a material of second material layers to form second backside recesses; and simultaneously filling the first and second backside recesses with a combination of a dielectric liner and a conductive material; the first backside recess is formed prior to formation of the second backside recesses; the dielectric liner is formed on a sidewall of the drain region at a level of the temporary material layer, and on a sidewall of the memory film at each level of the second material layer; and the dielectric liner is formed on a top surface of a remaining portion of the memory film, and on a bottom surface of another remaining portion of the memory film.