Patent ID: 9411701
Filing Date: 2016-08-09
CPC Classification: G01R,G06F

Claim Text:
1. An apparatus, comprising: a system-on-chip having at least one analog block, an input/output interface, and a processing unit; a data test block coupled to the at least one analog block through the input/output interface; and a link test block coupled to the at least one analog block, wherein the link test block comprises a test interface; wherein the processing unit is coupled to the input/output interface to control access to the at least one analog block; wherein the processing unit is coupled to the data test block and configured to execute test code having at least one test pattern; wherein the data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern; and wherein the link test block is separately controllable via the test interface to adjust operating parameters of the at least one analog block during the execution of the test code.