Patent ID: 9473126
Filing Date: 2016-10-18
CPC Classification: H03K

Claim Text:
1. A latch, comprising: a first logic unit coupled between a power supply and a ground wire, wherein the first logic unit comprises a first control terminal, a first input terminal and a first output terminal; a second logic unit having a structure symmetrical to that of the first logic unit, wherein the second logic unit comprises a second control terminal, a second input terminal and a second output terminal; and a feedforward control unit adapted for cutting off a current path in the first logic unit or the second logic unit based on signals inputted into the first input terminal and the second input terminal, wherein the first logic unit comprises a first transistor, a third transistor and a fifth transistor, and the second logic unit comprises a second transistor, a fourth transistor and a sixth transistor, wherein a source of the first transistor is coupled with the ground wire, a gate of the first transistor is coupled with the first control terminal, a drain of the first transistor is coupled with a drain of the third transistor, a drain of the fifth transistor, a gate of the fourth transistor and the first output terminal; wherein a source of the second transistor is coupled with the ground wire, a gate of the second transistor is coupled with the second control terminal, a drain of the second transistor is coupled with a drain of the fourth transistor, a drain of the sixth transistor, a gate of the third transistor and the second output terminal; and wherein the third transistor and the fifth transistor are connected in parallel, the fourth transistor and the sixth transistor are connected in parallel, and sources of the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are coupled with the power supply.