Patent ID: 9294328
Filing Date: 2016-03-22
CPC Classification: H03M,H04L

Claim Text:
1. An apparatus, comprising: a plurality of in-phase multiplying cells that receive an in-phase local oscillator signal and a plurality of in-phase bits, each in-phase multiplying cell producing an output signal based on a received one of the plurality of in-phase bits, wherein each in-phase bit has a significance from most significant to least significant and a binary-weighted number of in-phase multiplying cells are connected to each in-phase bit, the binary-weighted number matching the significance of the in-phase bit; a plurality of quadrature multiplying cells that receive a quadrature local oscillator signal and a plurality of quadrature bits, each quadrature multiplying cell producing an output signal based on the received one of the plurality of quadrature bits, wherein each quadrature bit has a significance from most significant to least significant and a binary-weighted number of quadrature multiplying cells are connected to each quadrature bit, the binary-weighted number matching the significance of the quadrature bit; a first output line connected to a first set of the plurality of in-phase multiplying cells and a first set of the plurality of quadrature multiplying cells, the first output line propagating a first output signal produced from output signals of the first set of the plurality of in-phase multiplying cells and the first set of the plurality of quadrature multiplying cells; and a second output line connected to a second set of the plurality of in-phase multiplying cells and a second set of the plurality of quadrature multiplying cells, the second output line propagating a second output signal produced from output signals of the second set of the plurality of in-phase multiplying cells and the second set of the plurality of quadrature multiplying cells.