Patent ID: 9298640
Filing Date: 2016-03-29
CPC Classification: G06F

Claim Text:
1. A processor comprising: a first register to reference a set of page tables, the set of page tables to provide a mapping of guest virtual addresses to guest physical addresses; a second register to reference an active set of extended page tables, wherein the active set of extended page tables is one of: address translation logic to access the set of page tables and the set of extended page tables to translate a guest virtual address to a guest physical address and to translate the guest physical address to a host physical address in response to a memory access request including the guest virtual address; a translation look-aside buffer (TLB) to cache a plurality TLB entries, including guest physical address to host physical address translations; and execution logic, in response to a TLB invalidate instruction, to invalidate TLB entries storing the guest physical address to host physical address translations independent of their association with corresponding guest physical addresses and independent of their association with the first or second virtual machine.