Patent ID: 9311050
Filing Date: 2016-04-12
CPC Classification: G06F

Claim Text:
1. A mixed radix converter configured to convert a mixed radix number to a fixed radix number: a first shift register configured to store a plurality of mixed radix digits and to output each of the plurality of mixed radix digit operands in a last in first out sequence; a second shift register configured to store a plurality of digit radix and to output each of the plurality of digit radix in a last in first out sequence; and a plurality of digit processing units configured to perform one or more arithmetic operations on a plurality of mixed radix operands and to generate a fixed radix output, each digit processing unit comprising: wherein the plurality of digit processing units are connected in an ordered sequence such that, except for the last digit processing unit in the ordered sequence, the adder of one digit processing unit is in communication with the additive operand register of a subsequent digit processing unit to transmit the carry value from one digit processing unit to the next; and wherein a fixed radix representation of the mixed radix number comprises the sums stored in the binary digit accumulators of the plurality of digit processing units store.