Patent ID: 9412700
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. An integrated circuit comprising: a substrate comprising: a first gate structure over a top surface of the substrate, wherein the first gate structure is between the source feature and the drain feature; a second gate structure over the top surface of the substrate, wherein the second gate structure is adjacent to the first gate structure and the source feature; a pair of first spacers on each sidewall of the first gate structure; a pair of second spacers on each sidewall of the second gate structure; an insulating layer over at least the first gate structure, the insulating layer being embedded between the pair of first spacers on each sidewall of the first gate structure; a first conductive feature over the source feature or the drain feature, wherein a top surface of the first conductive feature is coplanar with a top surface of the insulating layer; a second conductive feature over the substrate; and a third conductive feature, wherein the third conductive feature is over the first conductive feature or the second conductive feature.