Patent ID: 9418745
Filing Date: 2016-08-16
CPC Classification: G11C

Claim Text:
1. A method of operating a multi-time programmable memory cell, said multi-time programmable memory cell having a series connection of a first transistor and a second transistor, said method comprising: writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells by changing a threshold voltage state of one of said first and said second transistor relative to the other of said first and said second transistor to create a different state in a selected cell; rebalancing, using said write circuit, the threshold voltage state associated with one or more said first transistor or second transistor by changing the threshold voltage state of one of said first or said second transistor to set equal both threshold voltage states at said select memory cell, and erasing, at each said rebalanced select memory cell, said written initial bit value.