Patent ID: 9514986
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A device comprising: a semiconductor substrate; a first dielectric layer over a major surface of the semiconductor substrate; a gate electrode formed in the first dielectric layer; a through-substrate via (TSV) structure extending through the first dielectric layer and into the semiconductor substrate at a first depth, wherein the TSV structure comprises a conductive layer at a center of the TSV structure, a diffusion barrier layer surrounding and contacting the conductive layer and an isolation layer surrounding the diffusion barrier layer; and a capping layer comprising cobalt formed on top surfaces of the conductive layer and the diffusion barrier layer of the TSV structure, wherein an end of the capping layer is substantially aligned with an interface between the diffusion barrier layer and the isolation layer and not aligned with an interface between the isolation layer and the semiconductor substrate, and wherein the capping layer extends from below a top surface of the isolation layer to above the top surface of the isolation layer, wherein the top surface of the isolation layer is substantially parallel to the major surface of the semiconductor substrate.