Patent ID: 9299619
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device, the method comprising: preparing a semiconductor substrate that includes a PMOS region for forming a PMOS structure and includes an NMOS region for forming an NMOS structure; forming an interlayer dielectric layer on the semiconductor substrate; forming a first gate trench in the interlayer dielectric layer and on the PMOS region; sequentially forming a first high-k dielectric layer and a first high-k cap layer that cover a bottom and sides of the first gate trench; forming a second gate trench in the interlayer dielectric layer and on the NMOS region; sequentially forming a second high-k dielectric layer and a second high-k cap layer that cover a bottom and sides of the second gate trench; removing a portion of the first high-k dielectric layer and a portion of the first high-k cap layer, wherein the portion of the first high-k dielectric layer and the portion of the first high-k cap layer are positioned inside the first gate trench and overlap a side of the first gate trench, and wherein the side of the first gate trench is not parallel to the top surface of the semiconductor substrate; and removing a portion of the second high-k dielectric layer and a portion of the second high-k cap layer, wherein the portion of the second high-k dielectric layer and the portion of the second high-k cap layer are positioned inside the second gate trench and overlap a side of the second gate trench, and wherein the side of the second gate trench is not parallel to the to surface of the semiconductor substrate.