Patent ID: 9305480
Filing Date: 2016-04-05
CPC Classification: G09G

Claim Text:
1. A display having a data driving integrated circuit, comprising: N number of output channels where N is an integer including a first to Nth output channel; first and second data output channel groups having data output channels which supply pixel data to a corresponding number of data lines in accordance with a desired resolution of the display, wherein a number of channels of the first data output channel group equals a number of channels of the second data output channel group; a dummy output channel group provided at a middle portion between the first and second data output channel groups and having dummy output channels wherein the dummy output channels are not supplied with pixel data; a shift register part including a sequence of N shift registers for shifting a source start pulse, wherein the Nth shift register outputs a carry signal to a carry bit output terminal of a next data driving integrated circuit; and a channel selector setting the data output channels and the dummy output channels in advance based on the desired resolution of the display by applying a channel selection signal to the data driving integrated circuit; and a second selector receiving inputs from the channel selector and at least one of first to Mth (where M is an integer less than N) shift registers and controlling an output timing of the carry signal from the Nth shift register to the carry bit output terminal by using a multi-bit control signal including at least two integer values, wherein the channel selector for selecting a number of dummy output channels and the number of the first and second data output channels, wherein the first data output channel group, the dummy output channel group and the second data output channel group are consecutively arranged to form the N number of output channels of the data driving integrated circuit, wherein the first data output channel group has a plurality of first data output channels being consecutively arranged, the dummy output channel group has a plurality of dummy output channels being consecutively arranged, and the second data output channel group has a plurality of second data output channels being consecutively arranged.