Patent ID: 9235666
Filing Date: 2016-01-12
CPC Classification: G06F

Claim Text:
1. A simulation device for verifying operation of a semiconductor circuit comprising an ESD (Electro Static Discharge) protection element, comprising: a first parameter file creating unit configured to create a parameter file for an equivalent circuit of the ESD protection element; a second parameter file creating unit configured to create a parameter file for an internal circuit in the semiconductor circuit except for the ESD protection element; a parameter file storage configured to store the parameter files created by the first and second parameter file creating units; a parameter file selector configured to select one parameter file from the parameter files stored in the parameter file storage, depending on whether or not operation of the ESD protection element should be verified; a netlist creating unit configured to create a netlist of the semiconductor circuit utilizing the parameter file selected by the parameter file selector; and a simulation executing unit configured to verify the operation of the semiconductor circuit based on the netlist, wherein the equivalent circuit of the ESD protection element for which the first parameter file creating unit creates the parameter file comprises: first and second impedance elements configured to be connected in series between first and second reference voltage terminals; and a third impedance element, a rectifier element, and a transistor configured to be connected in series between the first and second reference voltage terminals, the transistor comprising a control terminal connected to a connection path between the first impedance element and the second impedance element, and the rectifier element being connected so that current flows from the first impedance element to the transistor through the third impedance element in a breakdown state, wherein the first parameter file creating unit creates a parameter file for a detailed model based on the equivalent circuit of the ESD protection element when verifying the operation of the ESD protection element, and creates a parameter file for a simplified model of the ESD protection element when verifying the operation of the internal circuit in the semiconductor circuit except for the ESD protection element, and the second parameter file creating unit creates a parameter file for a simplified model of the internal circuit when verifying the operation of the ESD protection element, and creates a parameter file for a detailed model of the internal circuit when verifying the operation of the internal circuit.