Patent ID: 9331086
Filing Date: 2016-05-03
CPC Classification: G11C,H01L,H03K,H03M

Claim Text:
1. Integrated circuit, comprising: at least one first group each having at least one analog circuit; at least one second group each having at least one electronically settable semi-permanent switching circuit coupled to the at least one analog circuit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell; wherein each many-times-programmable cell comprises at least one MOS transistor connected in series with one of the analog circuits and having a source and drain in parallel with a source and drain of at least another MOS transistor in another one of the many-times-programmable cells, and having a floating gate with a tunnel oxide and a first capacitor coupled to the floating gate; and wherein the capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor; wherein the at least one analog circuit comprises at least one of a capacitor, an inductor, and a time delay unit, and wherein the at least on electronically settable semi-permanent switching circuit includes a plurality of switching circuits that are grouped in bits, where the nth bit contains 2n many-times-programmable cells, where n is a positive integer.