Patent ID: 9472642
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device structure, comprising: providing source/drain regions within a semiconductor substrate adjacent a gate structure formed over said semiconductor substrate, said gate structure having a gate electrode structure, a first sidewall spacer and a second sidewall spacer, said first sidewall spacer covering sidewall surfaces of said gate electrode structure and said second sidewall spacer being formed on said first sidewall spacer, wherein said first sidewall spacer has an L-shape with a vertical leg and a horizontal leg; removing said second sidewall spacer so as to expose said first sidewall spacer; forming a third sidewall spacer on a portion of said first sidewall spacer such that said first sidewall spacer is partially exposed and said third sidewall spacer has a surface extending from said vertical leg to said source/drain regions; and forming silicide regions in the presence of said third sidewall spacer in said source/drain regions.