Patent ID: 9466613
Filing Date: 2016-10-11
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: first and second selection lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; first vertically-stacked memory cell strings coupled to the first selection line; second vertically-stacked memory cell strings coupled to the second selection line; a first sub-interconnection coupling one of the first vertically-stacked memory cell strings to one of the second vertically-stacked memory cell strings; a second sub-interconnection that is adjacent first sub-interconnection in the first direction; and bit lines extending in the second direction and coupled to respective ones of the first and second sub-interconnections, wherein the first sub-interconnection and the second sub-interconnection comprise respective first and second protrusions that protrude in the first direction, and wherein a length of the first sub-interconnection in the second direction is different from a length of the second sub-interconnection in the second direction.