Patent ID: 9431133
Filing Date: 2016-08-30
CPC Classification: G01R,G06F,G11C

Claim Text:
1. A method of testing a device, comprising the steps: selectively mounting a device under test (DUT) comprising an integrated circuit (IC) and a first DUT interface structure to a circuit board comprising an aperture and a second DUT interface structure adjacent to said aperture configured to selectively couple with said first DUT interface structure in manner as to orient a first side of said DUT to be exposed or subject to direct exposure from a radiation source; aligning said circuit board with said radiation source by mounting said circuit board to a mounting structure and adjusting a height and angle of the mounting structure; applying a voltage to the circuit board and DUT via a power source wherein said voltage is selected using a voltage select system coupled to a plurality of power modules on the circuit board which are powered by the power source; loading a test program into an IC on said circuit board by pressing a button in a programmable read only memory (PROM) system coupled to said circuit board to load said test program from a PROM memory in said PROM system onto said IC; providing said radiation source configured to emit radiation; positioning said DUT such that a second side of said DUT having said IC is subject to direct exposure from said radiation source via an aperture in said circuit board; operating said radiation source to direct the radiation through said aperture and into said DUT; selecting a test procedure comprising a plurality of test sequences configured to operate said IC to execute a plurality of functions on the IC via a user input on a graphical user interface (GUI) on a computer coupled to said IC via an interface connector on said circuit board; initiating the test procedure via another user input into said GUI that causes the computer to send an initialization signal and test program execution signal from said computer to said IC through said interface connector on said circuit board; operating the DUT based on said test procedure and said test program; polling sensors on the circuit board to gather environmental data; checking for errors and bad data on the DUT by comparing expected results with actual results from said test procedure; displaying an error list, summary of errors, and environmental data in a display window on said GUI; writing test data onto a dynamic random access memory (DRAM) memory device housed within a dual in-line memory module (DIMM) receptacle on said circuit board; sending a stop signal to said IC via said GUI generated by computer and said interface connector.