Patent ID: 9373636
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor construction, comprising: forming a stack comprising alternating control gate material and intervening dielectric material; forming a plurality of first trenches within the stack and extending along a first direction; recessing the control gate material along interior walls of the first trenches to form a plurality of cavities along the interior walls, the cavities being bounded on top and bottom by the intervening dielectric material, and on one side by the control gate material; forming memory cell stacks within the cavities, the memory cell stacks comprising cell dielectric material shaped as containers and having open ends pointing away from the sides of the cavities bounded by the control gate material; the memory cell stacks also comprising charge-storage material within the containers; after forming the memory cell stacks, forming channel material panels within the first trenches; the channel material panels extending along the first direction of the first trenches; forming a plurality of second trenches within the stack and extending along the first direction; forming first dielectric material panels within the second trenches; forming form a plurality of third trenches within the stack and channel material panels, and extending along a second direction substantially orthogonal to the first direction; and forming a plurality of second dielectric material panels within the third trenches.