Patent ID: 9240452
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A structure, comprising: a deep trench having sidewalls and a bottom in a DRAM array having a first critical dimension; a deep trench having sidewalls and a bottom in a moat region having a second critical dimension, larger than the first critical dimension; a dielectric node lining at least a portion of the sidewalls and an entire a bottom of the deep trench in the DRAM array and at least a portion of the sidewalls and an entire a bottom of the deep trench in the moat region; a metal filling the first critical dimension of the deep trench in the DRAM array, formed over the dielectric node; a metal lining over the dielectric node in the deep trench in the moat region, wherein the metal lining has a dimension smaller than that of the metal filling the first critical dimension of the deep trench in the DRAM array; and a Si material formed over the metal in the deep trench in the moat region, wherein the metal in the DRAM array is lower than the metal lining in the moat region due to RIE lag.