Patent ID: 9362900
Filing Date: 2016-06-07
CPC Classification: H03K

Claim Text:
1. A switching unit for the arithmetic linking of at least two input signals supplied to the switching unit, comprising: a switching matrix to which the at least two input signals are supplied, wherein the switching matrix applies at least one summation operation to at least two input signals, applies at least one multiplication operation to at least one input signal of the at least two input signals, or connects the at least one input signal of the at least two input signals directly through to a first output, wherein the switching matrix includes several current switches, wherein a current switch includes a first input, a second input, a third input, a first output, and a second output, wherein the current switch includes a first transistor and a second transistor, wherein the first and second transistors are connected at their emitter terminals or source terminals to one another and to the first input of the current switch, wherein a base terminal or a gate terminal of the first transistor is connected to the second input of the current switch, wherein a base terminal or a gate terminal of the second transistor is connected to the third input of the current switch, wherein a control voltage is applied to the second and third inputs of the current switch, wherein a collector terminal or a drain terminal of the first transistor is connected to the first output of the current switch, and wherein a collector terminal or a drain terminal of the second transistor is connected to the second output of the current switch.