Patent ID: 9331008
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate upon which semiconductor elements are formed; a lower layer wiring pattern which includes a multilayer wiring structure including a plurality of wiring layers and an interlayer film, in the multilayer wiring structure, the plurality of wiring layers being laminated via the interlayer film, an uppermost wiring layer of the plurality of wiring layers including a first wiring and a second wiring, the first wiring and the second wiring disposed separately so as to be flush with each other and the first wiring is fixed at a different potential from that of the second wiring; an uppermost interlayer film disposed on the lower layer wiring pattern; a titanium nitride layer disposed on the uppermost interlayer film to be flat, the titanium nitride layer covering the first wiring and the second wiring, the titanium nitride layer having a thickness of 800 Å or more; a pad metal disposed on the titanium nitride layer, the second wiring being insulated from the pad metal; and vias formed so as to penetrate through the uppermost interlayer film to connect a portion of the titanium nitride layer with the first wiring at a region facing the pad metal in a vertical direction, the first wiring being electrically connected to the pad metal through the vias, wherein the vias are arranged at regular intervals in a first direction and a second direction, the pad metal includes a wire joining region to which a bonding wire is joined, and in a plan view, the vias are arranged in only a part of an entire region directly beneath the wire joining region.