Patent ID: 9230982
Filing Date: 2016-01-05
CPC Classification: G01R,G11C,H01L

Claim Text:
1. A memory device, comprising: a stacked three-dimensional memory structure comprising alternating conductive layers and dielectric layers, the conductive layers comprising a select gate layer, the select gate layer comprises parallel select gate lines and a remaining portion of the select gate layer, the remaining portion of the select gate layer extends transversely to the parallel select gate lines and is separated from the parallel select gate lines by an end trench at one end of the parallel select gate lines, the parallel select gate lines are separated from one another by side trenches, the end trench is connected to the side trenches, an oxide is provided in the side trenches, a protective structure is provided in the end trench, and a breakdown voltage of the protective structure is higher than a breakdown voltage of the oxide in the side trenches.