Patent ID: 9312143
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method comprising: providing a semiconductor substrate; forming a hard-mask layer on top of the substrate; forming a first resist-mask on top of a first portion of the hard-mask layer etching a top portion of the hard-mask layer in areas not covered by the first resist-mask to create a recessed portion of the hard-mask layer; applying the first resist-mask in forming a first type of wells in a first region of the substrate; forming a second resist-mask on top of a second portion of the hard-mask layer wherein a first portion of the recessed portion of the hard-mask layer is covered by the second resist-mask; etching a second portion of the recessed portion of the hard-mask layer that is not covered by the second resist-mask until the substrate is exposed; applying the second resist-mask in forming a second type of wells in a second region of the substrate; etching at least the exposed portion of the substrate to create deep trenches that separate the first type of wells from the second types of wells; and filling the deep trenches with insulating materials.