Patent ID: 9420683
Filing Date: 2016-08-16
CPC Classification: H01L,H05K

Claim Text:
1. A substrate embedding a passive element, comprising: a first insulating layer in which a passive element having an external electrode is embedded; a second insulating layer formed on an upper surface of the first insulating layer; a third insulating layer formed on a lower surface of the first insulating layer; a first conductor pattern layer disposed on a lower surface of the third insulating layer; a second conductor pattern layer disposed on an upper surface of the second insulating layer; a third conductive pattern layer formed on the lower surface of the first insulating layer; a fourth conductive pattern layer formed on the upper surface of the first insulating layer; a first via electrically connecting between a lower surface of the external electrode and the first conductor pattern layer; a second via electrically connecting between an upper surface of the external electrode and the second conductor pattern layer; a third via penetrating the third insulating layer and electrically connecting between the third conductive pattern layer and the first conductive pattern layer; a fourth via penetrating the first insulating layer and electrically connecting between the third conductive pattern layer and the fourth conductive pattern layer; and a fifth via penetrating the second insulating layer and electrical connecting between the fourth conductive pattern layer and the second conductive pattern layer, wherein the first via and the third via are both in contact with a conductive pattern of the first conductive pattern layer, wherein the third via and the fourth via are both in contact with a conductive pattern of the third conductive pattern layer, and wherein the fourth via and the fifth via are both in contact with a conductive pattern of the fourth conductive pattern layer.