Patent ID: 9299498
Filing Date: 2016-03-29
CPC Classification: H01G,H05K,Y10T

Claim Text:
1. A multi-layer ceramic capacitor device, comprising: a ceramic chip having a top side, a bottom side, a front side, a back side, a left end, and a right end, said bottom side defining a reference plane; a first plurality of electrically conductive layers embedded within the ceramic chip that form a first capacitor, each of said first plurality of electrically conductive layers extending transversely within the ceramic chip parallel to the reference plane; a second plurality of electrically conductive layers embedded within the ceramic chip that form a second capacitor, each of said second plurality of electrically conductive layers extending transversely within the ceramic chip parallel to the reference plane; a plurality of electrically conductive pads on the top side of the ceramic chip, each of the plurality of electrically conductive pads having a flat surface that is parallel to and at a distance away from the top side, and being otherwise configured to function as a wire-bondable capacitor terminal; and a plurality of vias in the ceramic chip, each of the plurality of vias connecting a respective one of the plurality of electrically conductive pads to a respective one of the first and second capacitors; whereby the multi-layer ceramic capacitor device enables electrical connection of the first and second capacitors to a printed circuit board by wire bonding to the plurality of electrically conductive pads on the top side instead of requiring solder connections to terminals on the left and right ends.