Patent ID: 9502431
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A nonvolatile semiconductor memory device comprising: a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction, where n is a natural number; an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction; a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges; and an area provided in the oxide semiconductor layer, being in contact with at least one of the first to (n+1)-th insulating layers, having a composition ratio of oxygen lower than a composition ratio of oxygen in the oxide semiconductor layer.