Patent ID: 9379699
Filing Date: 2016-06-28
CPC Classification: H03K

Claim Text:
1. A driver for a power transistor switch, comprising: a first p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to an output-drive power supply V a first n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to a ground potential relative to the V a second p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first p-channel FET; a second n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first n-channel FET; a current-limiting and cross-delaying circuit including a first node and a second node, further comprising at least one resistor, and wherein the first node is coupled to the drain terminal of the second p-channel FET, and wherein the second node is coupled to the drain terminal of the second n-channel FET, to reduce current flowing from the first node to the second node thereby limiting shoot-through current when both the second p-channel FET and the second n-channel FET are momentarily turned on during a switching transition, and delaying turning on the first p-channel FET when the first n-channel FET is being turned off, and delaying turning on the first n-channel FET when the first p-channel FET is being turned off; and an input-buffer and level-shifter circuit, being powered by both a logic-voltage-level power supply V