Patent ID: 9460926
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A power integrated circuit, comprising: a semiconductor layer of a first conductivity type and being lightly doped; a junction field effect transistor (JFET) device formed in a first portion of the semiconductor layer and being formed in a first deep well of a second conductivity type, the JFET device comprising a gate region formed using a first body region of the first conductivity type, source and drain regions of the second conductivity type formed on opposite sides of the gate region, the first body region, the source and drain regions of the JFET device being formed on a first surface of the semiconductor layer, a channel of the JFET device being formed in an area of the first deep well between the source region and the drain region outside of the gate region; a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a second portion of the semiconductor layer and being formed in a second deep well of the second conductivity type, the LDMOS transistor comprising a second body region of the first conductivity type formed in the second deep well, a gate electrode, a source region, and a drain drift region in electrical contact with a drain region, the source region, the drain drift region and the drain region being of the second conductivity type, the second body region, the source region the drain drift region, and the drain region being formed on the first surface of the semiconductor layer, a channel of the LDMOS transistor being formed in the second body region between the source region and the drain drift region, wherein the second body region is formed to optimize a threshold voltage and a breakdown voltage of the LDMOS transistor and the first and second body regions have the same doping concentration and the same doping depth; a first deep diffusion region formed in the first deep well under the first body region and in electrical contact with the first body region, the first deep diffusion region together with the first body region establishing a pinch off voltage of the JFET device; and a second deep diffusion region formed in the second deep well under the second body region and in electrical contact with the second body region, the second deep diffusion region forming a reduced surface field (RESURF) structure in the LDMOS transistor.