Patent ID: 9450590
Filing Date: 2016-09-20
CPC Classification: G06F,H03K,H03L,Y02D

Claim Text:
1. A method for reconfiguring clock generation circuitry in a clock distribution network of a synchronous digital system, the method comprising: generating a first clock signal using the clock generation circuitry; selecting the first clock signal as a primary clock for the synchronous digital system, wherein the synchronous digital system is comprised on a chip; detecting a signal indicating possible tampering with the synchronous digital system; selecting a second clock signal as the primary clock in response to the detecting, wherein the second clock signal is generated by an on-chip oscillator that is independent of external clock signals, wherein the selecting the second clock signal comprises causing the second clock signal to replace the first clock signal as the primary clock without causing clock-induced errors in the synchronous digital system; reconfiguring the clock generation circuitry during the time that the second clock signal is acting as the primary clock; and selecting the first clock signal as the primary clock for the synchronous digital system after the clock generation circuitry has stabilized, wherein the selecting the first clock signal comprises causing the first clock signal to replace the second clock signal as the primary clock without causing clock-induced errors in the synchronous digital system.