Patent ID: 9349649
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a plurality of semiconductor fins extending upward from a topmost surface of an insulator layer; a gate structure straddling a first portion of each semiconductor fin of said plurality semiconductor fins; a dielectric spacer located on a sidewall of each side of said gate structure and straddling a second portion of each semiconductor fin of said plurality semiconductor fins; epitaxial semiconductor material portions having a non-planar bottommost surface and a non-planar topmost surface located between and merging exposed semiconductor fin portions of an adjacent pair of semiconductor fins of said plurality of semiconductor fins; and a metal semiconductor alloy located on said non-planar bottommost surface and said non-planar topmost surface of said epitaxial semiconductor material portions, wherein a gap is present beneath said epitaxial semiconductor material portions and said topmost surface of said insulator layer.