Patent ID: 9419599
Filing Date: 2016-08-16
CPC Classification: H03K

Claim Text:
1. A semiconductor integrated circuit comprising: a first generation unit configured to generate, in response to an output clock signal of a clock source, a fixed frequency division clock signal having a fixed frequency; a fixed frequency division state monitoring unit configured to monitor a frequency division state of the fixed frequency division clock signal; a second generation unit configured to generate, in response to the output clock signal of the clock source, a variable frequency division clock signal having a variable frequency; and a variable frequency division state monitoring unit configured to monitor a frequency division state of the variable frequency division clock signal, wherein in a case where the frequency of the variable frequency division clock signal is returned from a frequency obtained by reducing a normal frequency to the normal frequency, when the variable frequency division state monitoring unit determines that the variable frequency division clock signal becomes a high state in a next cycle, output of the variable frequency division clock signal having the frequency returned to the normal frequency is stopped, and when the fixed frequency division state monitoring unit determines, after the output is stopped, that the fixed frequency division clock signal becomes a high state in a next cycle, the output of the variable frequency division clock signal having the frequency returned to the normal frequency is resumed.