Patent ID: 9330732
Filing Date: 2016-05-03
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a first bit line extending in a first direction; a first source line including a first portion that is adjacent to the first bit line and extends in the first direction, a second portion that is adjacent to the first portion and extends in the first direction, and a third portion that connects one end of the first portion and one end of the second portion; a first word line that extends in a second direction crossing with the first direction and is crossing with the first bit line and the first source line; a first memory cell formed from a variable resistive element and a select transistor having a gate electrically connected to the first word line, the first memory cell having one terminal electrically connected to the first bit line and the other terminal electrically connected to the first portion of the first source line; a first sense amplifier arranged on the other end side of the first portion and the second portion of the first source line; and a first current sink arranged between the first sense amplifier and the first memory cell, wherein in a read operation, one end of the first bit line is electrically connected to a first input terminal of the first sense amplifier, and the other end of the second portion of the first source line is electrically connected to the first current sink.