Patent ID: 9257367
Filing Date: 2016-02-09
CPC Classification: G03F,G06F,G16Z,H01L

Claim Text:
1. A method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, comprising: estimating, by a processor, shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask, wherein the shape of the wiring formed based on one of a plurality of edges of the pattern is estimated; and modifying, by a processor, shape of the edge if the estimated shape of the wiring does not satisfy a requirement, wherein the shape of the one edge is modified, the estimating and the modifying are repeated until the wiring with the estimated shape satisfies the requirement, the repeating is performed in order of arrangement of the edges for all the edges included in the initial layout; and further comprising producing the mask layout of the exposure mask based on the modified shapes of all of the edges after the repeating.