Patent ID: 9465744
Filing Date: 2016-10-11
CPC Classification: G06F

Claim Text:
1. A method of data prefetching for a multi-core chip, comprising: determining memory utilization of the multi-core chip; in response to the memory utilization of the multi-core chip exceeding a first level and a historical prefetching accuracy not exceeding a second level, modifying data prefetching for the multi-core chip from a first data prefetching arrangement to a second data prefetching arrangement to reduce unused prefetched cache lines; and in response to the memory utilization of the multi-core chip not exceeding the first level, maintaining the first data prefetching arrangement, wherein the first and second data prefetching arrangements are different, and wherein in response to the memory utilization being below the first level a prefetcher refrains from delaying implementation of a prefetch ramp and in response to the memory utilization being above the first level and the historical prefetching accuracy being below the second level the prefetcher delays implementation of the prefetch ramp until one or more cache lines of a candidate stream are confirmed.