Patent ID: 9268885
Filing Date: 2016-02-23
CPC Classification: G06F

Claim Text:
1. A method, comprising: assuming variation among process targets for a plurality of integrated circuit (IC) fabrication process sources of variation; deriving relationships between each process source variance of the IC fabrication process and a device metric variance by operation of a computer program executed by a computer, the device metric variance being a variance in an IC performance characteristic; generating a predicted device metric variation by at least multiplying each process source variation by the corresponding relationships between its process source variance and the device metric variance; and designing at least a portion of an integrated circuit with the predicted device metric variation; wherein. generating the predicted device metric variation includes calculating a root sum square of process source variations and the relationships between the corresponding process source variance and the device metric variance; designing the at least a portion of the integrated circuit includes selecting process source variations having a greatest effect on the predicted device metric variation and creating a transistor performance model from at least the device metric; and fabricating the at least a portion of the integrated circuit with the predicted device metric variation.