Patent ID: 9355710
Filing Date: 2016-05-31
CPC Classification: G11C

Claim Text:
1. A hybrid write-assist memory system, comprising: an array voltage supply; a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply; a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation, wherein the voltage reduction of the separable cell supply voltage is provided through a charge sharing connection with an upper metal capacitance and an upper metal coupling capacitance during an initial portion of the write operation; and a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation.