Patent ID: 9485199
Filing Date: 2016-11-01
CPC Classification: H04L

Claim Text:
1. A device, comprising: a plurality of inputs for receiving a corresponding first plurality of channels carrying a plurality of data flows, each of the first plurality of channels carried on a physical lane of a first set of physical lanes; a data flow identifier module configured to identify data flow identifiers contained within the plurality of data flows; and a bit de-multiplexer configured to de-multiplex bits from the first plurality of channels into a second plurality of channels that have a lower bit rate as compared to the first plurality of channels, wherein an ordering of bits that are de-multiplexed into the second plurality of channels is based on an identity of the data flow identifiers identified by the data flow identifier module, the bit de-multiplexer also configured to output each of the second plurality of channels onto an assigned physical lane of a second set of physical lanes corresponding to a physical lane of a set of input physical lanes of a multiplexer in accordance with a stored channel assignment definition that maps data flow identifiers to physical lanes, the stored channel assignment definition ensuring that a channel having a particular data flow identifier is always output on the same physical lane that is pre-assigned to the particular data flow identifier based on the input physical lanes of the multiplexers; wherein the data flow identifier information is fed back from the data flow identifier module to the bit de-multiplexer.