Patent ID: 9524983
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A vertical memory device, comprising: a substrate; gate lines stacked on top of each other on the substrate, the gate lines being spaced apart from each other in a vertical direction with respect to a top surface of the substrate, the gate lines including step portions that extend in a parallel direction with respect to the top surface of the substrate, the gate lines including first gate lines and second gate lines, wherein the first gate lines ate either on top of the second gate lines or the first gate lines are alternately stacked with the second gate lines; channels extending through the gate lines in the vertical direction; contacts on the step portions of the gate lines, the contacts including first contacts connected to the first gate lines and second contacts connected to the second gate lines; and contact spacers formed along sidewalls of the first contacts, the contact spacers not being formed along sidewalls of the second contacts.