Patent ID: 9276563
Filing Date: 2016-03-01
CPC Classification: H03K

Claim Text:
1. A clock driver for an integrated circuit, comprising a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements, an input of the plurality of delay elements for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal for the integrated circuit, and an output of the plurality delay elements connected to a positive pulse driving branch and a negative pulse driving branch formed from the logic circuitry; and a pulse generator having pulse generation logic circuitry and transistors forming a positive pulse generator portion that is connected to an output of the positive pulse driving branch of the multi-stage delay cell and a negative pulse generator portion that is connected to an output of the negative pulse driving branch of the multi-stage delay cell, wherein the pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.