Patent ID: 9531406
Filing Date: 2016-12-27
CPC Classification: H03M

Claim Text:
1. A computer implemented method for decoding a sequence of bits written on a memory following a binary asymmetric channel, the sequence of bits being encoded by a low-density parity check (LDPC) code, whereby each bit of the sequence of bits has corresponding parity checks defined by the LDPC code, the method comprising: providing a set of bit states including a first bit state and a second bit state and a set of conditions, each bit state corresponding to a logical value for the bit and each condition corresponding to an evaluation of the LDPC code, wherein, when a condition is met, a bit state is changed, the set of conditions including a first condition to change the bit state from the first bit state to the second bit state and a second condition to change the bit state from the second bit state to the first bit state, wherein the first condition and the second condition are different, such that they provide a different result for the same input, using a computer processor, reading a value of each bit of the sequence of bits and associating each bit to a respective state of the set of bit states according to the value as read, for a target bit of the sequence of bits, evaluating the condition of the target bit, using the computer processor, wherein: determining that the condition is met, using the computer processor, the condition being met being based on satisfying a number of the parity checks, changing the state of the target bit as a result of the condition being met, using the computer processor, and setting the value of the target bit according to the state thereof, using the computer processor.