Patent ID: 9379130
Filing Date: 2016-06-28
CPC Classification: G11C,H01L

Claim Text:
1. A nonvolatile semiconductor memory device, comprising: a foundation layer; a stacked body provided on the foundation layer, the stacked body including a plurality of first electrode layers stacked alternately with a plurality of first insulating layers; a selection gate stacked body provided on the stacked body, the selection gate stacked body including a plurality of selection gate electrode layers stacked alternately with a plurality of second insulating layers in a stacking direction of the stacked body; a semiconductor member provided inside the stacked body and inside the selection gate stacked body to extend in the stacking direction; a memory film provided between the semiconductor member and one of the plurality of first electrode layers; a gate insulator film provided between the channel body film and one of the plurality of selection gate electrode layers, the gate insulator film including a charge storage film; and a controller capable of controlling to apply a potential to each of the plurality of selection gate electrode layers, a plurality of selection transistors being provided on the stacked body, one of the plurality of selection transistors including the gate insulator film, the semiconductor member, and one of the plurality of selection gate electrode layers, the stacked body having a plurality of memory cells, one of the memory cells including the semiconductor member, the memory film, and one of the plurality of first electrode layers, the plurality of memory cells being unselected by the plurality of selection transistors at programming.