Patent ID: 9245792
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A method for forming an interconnect structure in an integrated circuit (IC) comprising: forming a via dielectric layer on a surface of a substrate, wherein the via dielectric layer is a single low-k dielectric material; forming an etch stop layer directly atop the via dielectric layer; patterning the etch stop layer to form openings through the etch stop layer of a first width; forming a trench dielectric layer over the patterned etch stop layer, wherein the forming the trench dielectric layer further comprises: planarizing the first layer using a sacrificial layer different from the first oxide material, wherein the sacrificial layer is completely removed during the planarizing the first layer; forming trench openings in the trench dielectric layer overlying the openings in etch stop layer; forming via openings of a second width in the via dielectric layer through respective ones of the trench openings of the trench dielectric layer and through respective ones of the openings of the etch stop layer, the second width being smaller than the first width, the forming via openings beginning after the patterning the etch stop layer has been completed, wherein respective portions of each one of the via openings closest to the etch stop layer are laterally separated from the etch stop layer, wherein the via openings are centered with the openings; and forming a conductive material within the via openings and in physical connection with a conductive region within the substrate.