Patent ID: 9367318
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A method for managing thread execution in a process, the method comprising: fetching a first multiple of instructions using multiple fetch queues equal to the first multiple, each instruction a first bit size, from an instruction cache in a processor designed to handle a second multiple of threads of a second bit size, where the first multiple is greater than the second multiple and the second bit size is greater than the first bit size; decoding the first multiple of instructions received from the fetch queues; dividing the first multiple of instructions received from the fetch queues into a first group of a second multiple of instructions of the first bit size and a second group of a second multiple of instructions of the first bit size; and processing the instructions in the first group in an upper integer processing pathway and processing the instructions in the second group in a lower integer processing pathway, wherein the upper integer pathway uses an upper X bits of a 2X bit integer pathway of the processor to process the first group of the second multiple of instructions, and the lower integer pathway uses a lower integer X bits of the 2X bits of the integer pathway of the processor to process the second group of the second multiple of instructions, wherein the upper and lower pathways are mapped such that the upper and lower pathways operate simultaneously and process information independently.