Patent ID: 9502344
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A wafer level packaging of semiconductor devices comprising: a semiconductor device with a top face and a bottom face and one or more metal pads with each metal pad located on either the top face or the bottom face and; a top cover wafer affixed to the top face of the semiconductor device and; a bottom cover wafer affixed to the bottom face of the semiconductor device; wherein the top cover wafer and the bottom cover wafers have one or more vias extending from an external face of the respective cover wafer to an internal face of said cover wafer, wherein each of the one or more vias is associated with one of the one or more metal pads; and wherein an electroplated metal layer extends from the external face of each of the respective cover wafers through the via to the metal pad associated with the via.