Patent ID: 9323468
Filing Date: 2016-04-26
CPC Classification: G06F

Claim Text:
1. A computer system comprising: a storage apparatus; and a server configured to transmit an I/O (Input/Output) request to the storage apparatus, wherein the storage apparatus comprises multiple ports communicable with the server, multiple processor cores and multiple LUs (Logical Units), wherein, for each port, a port responsible core, which is a processor core to accept an I/O request received by the port, is specified, wherein, for each LU, an LU responsible core, which is a processor core responsible for I/O, is specified, wherein the storage apparatus is configured to judge whether or not it is necessary to change the LU responsible core, and if a result of the judgment is positive, perform a responsible core changing process, which is a process for changing the LU responsible core, at a first time interval, wherein the server comprises one or more communication interface devices, a storage device, and a control device coupled therewith, wherein the storage device is configured to store path information which includes, for each path, information about the path from the communication interface device to an LU and LU responsible core information which includes, for each LU, identification information about an LU responsible core, wherein the path information includes, for each path, identification information about a port responsible core responsible for a port through which the path passes, wherein the control device is configured to, by transmitting a responsible core notification request, which is a request for identification information about LU responsible cores responsible for the LUs, acquire the identification information about the LU responsible cores from the storage apparatus at a second time interval, and include the identification information into the LU responsible core information, wherein the control device is configured to, when transmitting an I/O request: (A) select a non-cross call path, which is such a path that the LU responsible core and the port responsible core are the same processor core, from among multiple paths to an I/O destination LU, which is an LU specified by the transmission target I/O request, on the basis of the path information and the LU responsible core information; and (B) transmit the transmission target I/O request via the path selected at the step (A).