Patent ID: 9472259
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a plurality of normal memory mats, one or more of which includes a redundancy word line; a dummy memory mat that performs an operation with an edge memory mat as a pair during an active operation, wherein the edge memory mat is one among the plurality of normal memory mats disposed at an edge; and a refresh control section that controls refresh operations for the plurality of normal memory mats and the dummy memory mat, and restricting activation of the redundancy word line during a refresh operation for the edge memory mat, wherein the refresh control section comprises: a refresh address generation unit that generates a refresh address during the refresh operations for the plurality of normal memory mats and the dummy memory mat; an activation control unit that generates an activation control signal in response to the refresh address corresponding to the edge memory mat; and a refresh driving unit that selectively activates the plurality of normal memory mats in response to the refresh address and restricts activation of the plurality of normal memory mats in response to the activation control signal.