Patent ID: 9378785
Filing Date: 2016-06-28
CPC Classification: G11C

Claim Text:
1. A resistive random-access memory device, comprising: a memory array, comprising a plurality of memory cells, wherein each memory cell comprises at least one non-volatile memory unit; a read circuit, coupled to one of a select bit-line and a select word-line, wherein the select bit-line and the select word-line are electrically connected to a selected memory cell among the memory cells, and the read circuit reads data stored in the selected memory cell and generates a first control signal according to a resistance state of the selected memory cell; a write-back circuit, performing a write-back operation on the selected memory cell according to a write-back control signal and a write-back voltage, so as to change the resistance state of the selected memory cell from a low resistance state to a high resistance state, and generating a second control signal according to the resistance state of the selected memory cell; and a write-back logic circuit, coupled to the read circuit and the write-back circuit and generating the write-back control signal according to the first control signal and the second control signal, wherein the write-back control signal is set to a value to cause the write-back circuit to perform the write-back operation when both the first control signal and the second control signal indicate the low resistance state of the selected memory cell, wherein the write-back logic circuit comprises: wherein the high and low resistance states respectively correspond to a high and low logic level of the selected memory cell.