Patent ID: 9337872
Filing Date: 2016-05-10
CPC Classification: G06F,H03M

Claim Text:
1. An integrated-circuit memory component comprising: a data storage array; a command/address interface to receive command/address information via a variable number of external signaling links in accordance with a command/address interface width indicated by a width configuration value, the command/address information specifying a storage location within the data storage array and a memory access operation to be executed with respect to the storage location; an error information interface to receive error-checking information via one or more error information links external to the integrated-circuit memory component; and error circuitry to detect errors within the command/address information using the error-checking information according to (i) a first error detection scheme if the width configuration value indicates a first command/address interface width in which the command/address information is to be received via a first number of external signaling links, and (ii) a second error detection scheme if the width configuration value indicates a second command/address interface width in which the command/address information is to be received via a second number of external signaling links, wherein the first and second error detection schemes are different from one another and the first and second numbers of external signaling links are different from one another.