Patent ID: 9268618
Filing Date: 2016-02-23
CPC Classification: G06F,Y02D

Claim Text:
1. A communication device for a multiprocessor computer system comprising: a chip having a network integrated therein with a plurality of network routers, wherein communication on said network takes place in a packet-based manner, wherein said chip is a non-transitory storage hardware medium configured so that a time response is adjusted so that background data traffic is given priority over data traffic with defined bandwidth requirements by regulating a bandwidth of said communication medium so that sufficient bandwidth is remaining for said data traffic with defined bandwidth requirements, and wherein each of the plurality of network routers supports: a first traffic class that includes guaranteed minimum bandwidth with upwardly restricted latency; a second traffic class that includes no guarantees but the shortest possible latency; and a third traffic class that includes guaranteed maximum latency with upwardly restricted bandwidth.