Patent ID: 9438410
Filing Date: 2016-09-06
CPC Classification: H03K,H04L

Claim Text:
1. A semiconductor apparatus comprising: a transmission block configured to convert an input signal into two or more synchronization signals, some bits of which have longer data valid windows than the other bits, and output the two or more synchronization signals; and a reception block configured to generate the output signal by capturing bits having longer data valid windows between the two or more synchronization signals, wherein the transmission block alternately outputs the some bits and the other bits in series, wherein the transmission block is configured to convert the input signal into a rising synchronization signal and a falling synchronization signal, and output the rising synchronization signal, a first bit of which has a longer data valid window than a second bit, and the falling synchronization signal, a second bit of which has a longer data valid window than a first bit, and the reception block is configured to output the rising synchronization signal as an output signal by capturing the first bit, and output the falling synchronization signal as the output signal by capturing the second bit.