Patent ID: 9411678
Filing Date: 2016-08-09
CPC Classification: G06F

Claim Text:
1. A method of operation in an integrated circuit (IC) memory device, the method to monitor the validity of error information associated with first data, the method comprising: storing the first data in a first group of storage locations in the memory device; storing the error information associated with the stored data in a second group of storage locations in the memory device; evaluating the validity of the error information based on a state of an error enable bit, the state based on whether a most recent access to the first group of storage locations involved a partial access; identifying a faulty storage location based on the error information; storing an address corresponding to the faulty storage location; and repairing the faulty storage location for subsequent accesses by augmenting data stored in the faulty storage location with error correction bits from a repair group of storage cells.