Patent ID: 9425239
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A memory on a semiconductor substrate, comprising: a data line, a selection line, a reference line, a memory cell that includes a variable impedance element and a select transistor having a control gate electrically coupled to the selection line, a first conduction terminal electrically coupled to the variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, wherein: the select transistor comprises a deep first doped region buried in the substrate, the first conduction terminal is a second doped region on a surface of the substrate and electrically coupled to the variable impedance element, the control gate is an embedded vertical gate produced in a trench formed in the substrate, and the select transistor includes a channel region opposite a first face of the trench and extending between the first doped region and the second doped region.