Patent ID: 9378986
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A chip package, comprising: a substrate having a plating layer formed on a surface thereof and including a cavity formed concavely in an inner direction; a chip wherein an electrode portion or a metal portion is formed on a bottom of the chip; an insulating portion configured to electrically isolate a first conductive portion of the substrate from a second conductive portion of the substrate and wherein the plating layer includes one plated surface of the cavity on the first conductive portion of the substrate and another plated surface of the cavity on the second conductive portion of the substrate electrically isolated from the one plated surface; a bump formed on the one plated surface of the cavity; and a solder for bonding the chip and the bump by being melted, and sealing a space between the chip and the substrate formed by bonding the chip and the bump, and a wire configured to electrically connect the chip and the another plated surface of the cavity on the second conductive portion of the substrate.