Patent ID: 9343573
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A method of fabricating a transistor with a non-uniform stress layer, comprising: providing a semiconductor substrate having a first transistor region; forming at least a transistor comprising a gate structure within the first transistor region; performing a low temperature deposition process to form a first tensile stress layer on the transistor, wherein a temperature of the low temperature deposition process is lower than 300 degrees Celsius (° C.), wherein the first tensile stress layer comprises a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition point between the curved portion and the extension portion, and wherein the first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition point and a thinnest thickness of the first tensile stress layer is defined by the transition point and an external corner of the gate structure and the semiconductor substrate; after performing the low temperature deposition process, performing a high temperature annealing process, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process; and forming a second tensile stress layer on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.