Patent ID: 9478666
Filing Date: 2016-10-25
CPC Classification: G02F,H01L

Claim Text:
1. An apparatus comprising: a gate electrode, a source electrode, and a drain electrode configured as a co-planar structure for a thin film transistor; an oxide semiconductor layer, under said co-planar structure, configured to serve as a channel between said source and drain electrodes; and a single layer of oxidizable material, on said oxide semiconductor layer and under said co-planar structure, configured such that a first end region exhibits conductive properties and is in electrical contact with said source electrode, a second end region exhibits conductive properties and is in electrical contact with said drain electrode, and a central region between said first and second end regions exhibits insulation properties as a result of oxidation thereof to reduce electrical resistance between the channel of said oxide semiconductor layer and said source and drain electrodes compared to a co-planar TFT without said single layer of oxidizable material.