Patent ID: 9496254
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A device, comprising: a semiconductor substrate; a first intermediate conductive layer comprising a silicon nitride layer, the first intermediate conductive layer further comprising a first capacitor plate on a shallow trench isolation (STI) region in the semiconductor substrate and a first set of local conductive interconnects to source and drain regions of the device, the first capacitor plate partially formed in the silicon nitride layer; an insulator layer on a surface of the first capacitor plate facing away from the STI region; a second intermediate conductive layer, comprising a second capacitor plate on a surface of the insulator layer and arranged along an entire length of the surface of the insulator layer, and supported by the first plate of the capacitor; a first interconnect coupled to the first capacitor plate; and a second interconnect coupled to the second capacitor plate.