Patent ID: 9490784
Filing Date: 2016-11-08
CPC Classification: H03B,H03K

Claim Text:
1. An apparatus for quadrupling a clock frequency, comprising: a voltage-controlled oscillator (VCO) configured to output a sinusoidal signal according to a first clock frequency; a first buffer configured to generate, based on the sinusoidal signal, a first digital signal having a 25% duty cycle; a second buffer configured to generate, based on the sinusoidal signal, a second digital signal having a 25% duty cycle; a combining module configured to combine the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle, the combined digital signal having a second clock frequency that is double the first clock frequency; a frequency doubling module configured to double the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency; and a feedback module configured to couple to the output signal to generate a feedback output, wherein at least one of the first buffer and the second buffer operates based on the feedback output.