Patent ID: 9530469
Filing Date: 2016-12-27
CPC Classification: G11C

Claim Text:
1. A method of manufacturing an integrated circuit system comprising: providing an integrated circuit die; forming a non-volatile memory cell in the integrated circuit die and a bit line for reading a data condition state of the non-volatile memory cell; and forming a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected at a first end to the bit line and at a second end to a voltage limiter, wherein the semiconductor switch is for reducing voltage excursions on the bit line, wherein the voltage clamp limits voltages on the bit line to a predetermined threshold level when the non-volatile memory cell is in a high resistive state, wherein the semiconductor switch enables the voltage clamp only during memory read operations and disables the voltage clamp during memory write operations, and wherein forming the voltage limiter of the voltage clamp includes: forming a semiconductor current sink having a first end connected to the semiconductor switch and having a second end connected to ground, wherein the semiconductor switch is between the bit line and the semiconductor current sink, and forming an operational amplifier, wherein an output of the operational amplifier is connected to a gate of a transistor provided as part of the semiconductor current sink.