Patent ID: 9337746
Filing Date: 2016-05-10
CPC Classification: H02M

Claim Text:
1. A multilevel inverter, the multilevel inverter comprising: a modularized phase-shift transformer including a plurality of modules to provide a phase shifted voltage by receiving a 3-phase input voltage; a plurality of first group unit power cells configured to provide a first output voltage of predetermined phase by performing a predetermined inverting operation by receiving a signal corresponding to each phase of a first phase voltage from any one module in the plurality of modules; a plurality of second group unit power cells configured to provide a second output voltage of predetermined phase by performing a predetermined inverting operation through receipt of a signal corresponding to each phase of a second phase voltage from any one module in the plurality of modules; a plurality of third group unit power cells configured to provide a third output voltage of predetermined phase by performing a predetermined inverting operation by receiving a signal corresponding to each phase of a third phase voltage from any one module in the plurality of modules; wherein one of the first group unit power cells, one of the second group unit power cells and one of the third group unit power cells are paired to provide an output voltage of same phase, wherein each of the first to third group unit power cells comprise first to third unit power cells, and wherein the unit power cells comprise comprises a rectifier configured to provide a first rectifying voltage rectified by receiving a first phase of the first phase voltage, a smoothing unit configured to provide voltages of mutually different levels to mutually different first to third nodes by receiving the first rectifying voltage rectified by the rectifier, and an inverter unit formed with a plurality of switches for transmitting voltages of three levels provided by the smoothing unit, wherein the inverter unit comprises a first switch unit interposed between the first node and a first output terminal, second switch units interposed between the second node and the first output terminal, a third switch unit interposed between the third node and the first output terminal, a fourth switch unit interposed between the first node and a second output terminal, fifth switch units interposed between the second node and the second output terminal and a sixth switch unit interposed between the third node and the second output terminal.