Patent ID: 9430242
Filing Date: 2016-08-30
CPC Classification: G06F,G06T,Y02D

Claim Text:
1. A computer-implemented method for throttling an instruction issue rate of a processor, the method comprising: receiving a plurality of instructions to be issued to one or more execution units within the processor; dispatching a subset of instructions included in the plurality of instructions to the one or more execution units within a first number of clock cycles during a current scheduling period, wherein the instruction issue rate during the current scheduling period is defined by a number of clock cycles for which at least one instruction is dispatched, and wherein the instruction issue rate during the current scheduling period is less than or equal to a throttling rate for the current scheduling period; updating a moving average based on the instruction issue rate during the current scheduling period; and updating a throttling rate for a next scheduling period based on the moving average.