Patent ID: 9305841
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a trench over a layer disposed on a semiconductor substrate filling the trench with a first material, thereby forming a filled trench over the layer; forming a feature of a second material over the filled trench, wherein the feature is disposed over the filled trench and extends along two opposing sidewalls of the filled trench to a top surface of the layer; planarizing the feature to expose a top surface of the filled trench, wherein the planarizing provides a first portion of the feature adjacent a first sidewall of the two opposing sidewalls of the filled trench and a second portion of the feature adjacent a second sidewall of the two opposing sidewalls of the filled trench; and using the first and second portions of the feature to define a dimension of an interconnect feature disposed over the semiconductor substrate.