Patent ID: 9257501
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate that is divided into at least an element region and a peripheral region that surrounds the element region, the semiconductor substrate including (i) a first conductive type body region that is formed in the element region and is arranged in an area facing an upper surface of the semiconductor substrate; (ii) a second conductive type drift region that is formed in the element region and contacts a lower surface of the first conductive type body region; (iii) a gate electrode that is formed in the element region, and that is arranged in a gate trench that passes through the first conductive type body region and extends to the second conductive type drift region, and that faces the first conductive type body region; (iv) an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; (v) a first conductive type floating region that is formed in the element region, and that surrounds a bottom portion of the gate trench, and that is surrounded by the second conductive type drift region; (vi) a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region, the first voltage-resistance retaining structure has a first termination trench that extends in a thickness direction of the semiconductor substrate from a front surface of the semiconductor substrate; (vii) a second voltage-resistance retaining structure formed in the peripheral region, the second voltage-resistance retaining structure surrounds the gate electrode, the second voltage-resistance retaining structure is surrounded by the first voltage-resistance retaining structure, the second voltage-resistance retaining structure has a second termination trench that extends in the thickness direction of the semiconductor substrate from the front surface of the semiconductor substrate; and (viii) a gate pad that is formed in the peripheral region, and the gate pad is electrically connected to the gate electrode in a position on an element region-side of the first voltage-resistance retaining structure, on a front surface side of the semiconductor substrate, the gate pad is only surrounded by the first voltage-resistance retaining structure from among the first voltage-resistance retaining structure and the second voltage-resistance retaining structure.