Patent ID: 9396780
Filing Date: 2016-07-19
CPC Classification: G11C

Claim Text:
1. A decoder circuit comprising: a first driver circuit having an input coupled to receive a first pre-decode signal and an output, the first driver circuit including a stack of transistors wherein a first current electrode of a first transistor in the stack is coupled to receive a second pre-decode signal and a first current electrode of a second transistor in the stack is coupled to a first supply terminal; a second driver circuit having an input coupled to receive a third pre-decode signal and an output, the second driver circuit including a stack of transistors wherein a first current electrode of a third transistor in the stack is coupled to receive the second pre-decode signal and a first current electrode of a fourth transistor in the stack is coupled to the first supply terminal; and a fifth transistor having a first current electrode coupled to the output of the first driver circuit, a second current electrode coupled to the output of the second driver circuit, and a control electrode coupled to a fourth pre-decode signal.