Patent ID: 9262079
Filing Date: 2016-02-16
CPC Classification: G06F

Claim Text:
1. A data processing method of a data storage device including cache memory and a plurality of nonvolatile memory devices coupled to the cache memory through a plurality of channels respectively, the method comprising: receiving a write command, a logical block address (LBA) value and a sector count value from an external device; receiving data corresponding to the write command from the external device; storing the received data into the cache memory, wherein the stored data includes at least one body portion and another portion; and transferring the at least one body portion from the cache memory to the plurality of nonvolatile memory devices through the plurality of channels, wherein each channel corresponds to a distinct set of the plurality of nonvolatile memory devices, each set comprising at least one of the plurality of nonvolatile memory devices, and wherein the body portion is determined to be present in the received data based on an offset and a ratio of the sector count value to a super page size of the data storage device, wherein the offset is based on the LBA value and the super page size.