Patent ID: 9305665
Filing Date: 2016-04-05
CPC Classification: G06F,G11C

Claim Text:
1. A memory system comprising: a nonvolatile first memory including a plurality of blocks as a unit of data erasing; a second memory that is randomly accessible; and a controller that performs data transfer between a host device and the first memory via the second memory, wherein the first memory stores therein a first address translation table for managing lookup information that associates a logical address specified by the host device with a physical address in the first memory, and a second address translation table for managing reverse lookup information that associates the physical address in the first memory with the logical address, wherein the controller is configured to, when loading of the reverse lookup information from the first memory to the second memory has failed, determine whether data at a first physical address is valid or invalid by using the lookup information loaded from the first memory to the second memory.