Patent ID: 9378968
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A method for planarizing a semiconductor device, comprising steps of: providing a substrate with a first dielectric layer covering at least one electrode structure formed thereon; performing a chemical-mechanical polishing (CMP) process on said first dielectric layer until said at least one electrode structure is exposed, wherein a plurality of voids and scratches are produced by the CMP process on a surface of said first dielectric layer; depositing a second dielectric layer so as to cover said at least one electrode structure and fill-in the plurality of voids and scratches produced by the CMP process on the surface of said first dielectric layer; and performing an etching-back process on said second dielectric layer until said at least one electrode structure is exposed, wherein said second dielectric layer is substantially removed, but with only a portion of said second dielectric layer being remained to form a remaining second dielectric layer with the surface of said first dielectric layer with the plurality of voids and scratches thereon being only filled with the second dielectric layer, which thereby together forming a planar surface.