Patent ID: 9419630
Filing Date: 2016-08-16
CPC Classification: H03K,H03L

Claim Text:
1. A clock dithering circuit comprising: an input clock signal on an input clock signal lead; a control unit having a clock input coupled with the input clock signal lead, an enable signal output, a coarse select signal output, and a fine select signal output; an ICG (integrated clock gating) cell having a clock input coupled with the input clock signal, an enable input coupled with the enable output, and a gated clock signal output, the ICG providing a gated clock signal in phase with the input clock signal during one state of the enable signal and providing no gated clock signal in another state of the enable signal; a coarse dither unit having a gated clock signal input coupled to the gated clock signal output, a coarse select signal input coupled to the coarse select signal output, and a coarse clock signal output, the coarse dither unit providing a coarse clock signal with a phase shift of either 0 degrees or 180 degrees with respect to the input clock signal in response to coarse select signals of one or another state on the coarse signal input; and a fine dither unit having a coarse clock signal input coupled to the coarse signal output, a fine select signal input coupled to the fine select signal output, and a fine clock signal output, the fine dither unit providing a fine clock signal with a phase shift of less than that of the coarse dither unit with respect to the input clock signal in response to fine select signals of different states on the fine signal input.