Patent ID: 9240772
Filing Date: 2016-01-19
CPC Classification: H03K,H03L

Claim Text:
1. A low power frequency synthesiser circuit, comprising: a digital controlled oscillator configured to generate an output signal having a frequency controlled by an input digital control word; a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word and the output signal; and a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal; wherein the feedback loop comprises a first feedback loop configured to provide a first part of the digital control word for coarse control of the frequency of the output signal of the digital controlled oscillator and a second feedback loop configured to provide a second part of the digital control word for fine control of the frequency of the output signal of the digital controlled oscillator; and wherein the first feedback loop includes the second feedback loop includes a second subtractor configured and arranged to generate the second part of the digital control word based on a difference between the number of clock cycles indicated by the counter and a second part of the frequency control word.