Patent ID: 9455198
Filing Date: 2016-09-27
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a first patterned masking layer comprised of a plurality of first features above a semiconductor substrate; forming a second patterned masking layer above said first patterned masking layer, said second patterned masking layer having an opening that exposes at least one, but not all, of said first features of said first patterned masking layer; performing at least one first etching process through said second patterned masking layer to remove said exposed at least one first feature and to form an initial isolation trench in said semiconductor substrate, said at least one first etching process defining a modified first patterned mask layer; removing said second patterned mask layer from above said modified first patterned mask layer; and after forming said initial isolation trench, performing at least one second etching process through said modified first patterned mask layer to thereby define a plurality of fin-formation trenches in said semiconductor substrate and to extend a depth of said initial isolation trench so as to define a final isolation trench having a final depth that is greater than a depth of said fin-formation trenches, said fin-formation trenches defining a plurality of fins.