Patent ID: 9324617
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a plurality of silicon fin structures in a bulk silicon substrate, said silicon fin structures being separated by a trench; forming a sacrificial SiGe material in said trench between said silicon fin structures; forming a layer of silicon above an upper surface of said silicon fin structures and above an upper surface of said sacrificial SiGe material, said layer of silicon having a lower surface and an upper surface; performing at least one etching process so as to cut said silicon fin structures and said sacrificial SiGe material, thereby exposing cut end surfaces of said sacrificial SiGe material; performing at least one etching process to selectively remove said sacrificial SiGe material relative to at least said silicon fin structures and said layer of silicon, said removal of said sacrificial SiGe material defining a cavity between said silicon fin structures, said lower surface of said layer of silicon and said bulk silicon substrate; forming a non-sacrificial SiGe material on said upper and lower surfaces of said layer of silicon and on said bulk substrate, said non-sacrificial SiGe material filing a portion, but not all, of said cavity; forming a layer of insulating material in any remaining portion of said cavity not filled by said non-sacrificial SiGe material; and forming a layer of strained channel semiconductor material above said non-sacrificial SiGe material positioned above said upper surface of said layer of silicon.