Patent ID: 9325307
Filing Date: 2016-04-26
CPC Classification: H03K

Claim Text:
1. A semiconductor device comprising: first and second output terminals coupled to one end side and another end side of an inductive or capacitive load, respectively; a first MOS transistor coupled between a first voltage and the first output terminal; a second MOS transistor coupled between a second voltage and the first output terminal; a third MOS transistor coupled between the first voltage and the second output terminal; a fourth MOS transistor coupled between the second voltage and the second output terminal; and a drive circuit driving the first to fourth MOS transistors for controlling the inductive or capacitive load, wherein the drive circuit drives the first to fourth MOS transistors while providing a dead-off period so that one of the first and second MOS transistors or one of the third and fourth MOS transistors is are brought into a non-conductive state, and the semiconductor device further comprises first and second bypass transistors which are provided corresponding to the first and second output terminals, respectively, the first bypass transistor is configured to provide bypassing of a forward current of a parasitic diode of a PN-junction formed in the one of the first and second MOS transistors brought into the non-conductive state in the dead-off period, and the second bypass transistor is configured to provide bypassing of a forward current of a parasitic diode of a PN-junction formed in the one of the third and fourth MOS transistors brought into the non-conductive state in the dead-off period, and the semiconductor device further comprises at least one inverter including a fifth MOS transistor and a sixth MOS transistor coupled between the first voltage and the second voltage, a parasitic transistor being formed to have a gate coupled to the second voltage, a collector coupled to a connection between the fifth MOS transistor and the sixth MOS transistor, and an emitter coupled to one of the first and second output terminals, and one of the corresponding first and second bypass transistor is configured to provide bypassing of a current from the parasitic transistor flowing toward the one of the first and second output terminals.