Patent ID: 9471125
Filing Date: 2016-10-18
CPC Classification: G06F,Y02D

Claim Text:
1. A processing device, comprising: a microprocessor comprising a control unit and a datapath unit, said control unit directing said datapath unit; said control unit comprising: a control store having therein a microprogram which comprises fully decoded microinstructions; a look behind control store register cache comprising a plurality of registers configured to receive and store data from a predetermined number of previously accessed memory locations in said control store and a clock transition isolating gate which provides clock enable signals for power reduction, the plurality of registers including latches or flip flops; and a controller for controlling access to data stored in said look behind control store register cache and said control store, wherein the look behind control store register cache is written and stores a copy of a microinstruction accessed from the control store, wherein the look behind control store register cache is accessed when a requested microinstruction is present within the look behind control store register cache and access to the control store is avoided.