Patent ID: 9479162
Filing Date: 2016-10-25
CPC Classification: B06B,H03K

Claim Text:
1. A receive switch comprising: a first terminal; a second terminal; a first field effect transistor (FET) including a first drain electrically connected to the first terminal, a first gate electrically connected to a gate node, and a first source electrically connected to a source node; a second FET including a second drain electrically connected to the second terminal, a second source electrically connected to the source node, and a second gate electrically connected to the gate node; a first threshold detection and control circuit configured to detect a voltage of the first terminal and to turn off at least one of the first FET or the second FET when the voltage of the first terminal is greater than a first threshold voltage; a second threshold detection and control circuit configured to detect the voltage of the first terminal and to turn off at least one of the first FET or the second FET when the voltage of the first terminal is less than a second threshold voltage; and a gate bias circuit configured to turn on the first and second FETs when neither the first threshold detection and control circuit nor the second threshold detection and control circuit is active to turn off the first or second FETs.