Patent ID: 9275709
Filing Date: 2016-03-01
CPC Classification: G11C

Claim Text:
1. An electronic apparatus comprising: a CPU configured to execute a program; a non-volatile memory storing in advance the program to be executed by said CPU and used as a main memory region for said CPU; and a reset unit configured to control reset of said CPU, and output, when said electronic apparatus enters a predetermined state, a predetermined signal to said non-volatile memory, wherein said non-volatile memory includes a plurality of memory regions including a first memory region storing the program in advance and a second memory region accessed by said CPU to execute the program, a transfer unit configured to transfer the program from said first memory region to said second memory region in response to the predetermined signal from said reset unit, and a controller configured to, upon completion of transfer of the program by said transfer unit, control to disable access from the outside of said non-volatile memory to said first memory region and enable access from the outside of said non-volatile memory to said second memory region, and upon completion of transfer of the program by said transfer unit, said reset unit outputs a reset-release signal to said CPU.