Patent ID: 9286997
Filing Date: 2016-03-15
CPC Classification: G11C

Claim Text:
1. A read only memory (ROM) array, comprising: a first field effect transistor (FET) in a first column of FETs, the first FET having a first source/drain (S/D) terminal coupled to a first S/D node, a second S/D terminal coupled to a second S/D node, and a gate terminal coupled to a signal source; a second FET in a second column of FETs, the second FET having a third S/D terminal coupled to a third S/D node and a fourth S/D terminal coupled to a fourth S/D node; a first plurality of bit lines, each one of which is coupleable to the first S/D node; a second plurality of bit lines, each one of which is coupleable to the second S/D node or the third S/D node; and a third plurality of bit lines, each one of which is coupleable to the fourth S/D node.