Patent ID: 9472654
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method for fabricating a fin MOSFET with substantially reduced parasitic capacitance and resistance, comprising: patterning a fin structure on a substrate, the substrate including a first semiconductor layer; patterning a dummy gate structure covering a first portion of the fin structure; growing an epitaxy layer covering the substrate and a second portion of the fin structure, the second portion of the fin structure not being covered with the dummy gate structure and the second portion of the fin structure being doped to be integrated with the epitaxy layer, wherein a source and drain region is formed in the epitaxy layer; depositing an oxide layer covering the epitaxy layer, a topmost surface of the oxide layer being planarized to be level with a topmost surface of the dummy gate structure; removing the dummy gate structure to form a gate trench structure; undercutting the epitaxy layer under the oxide layer along sidewalls of the gate trench structure to form an undercut structure; forming a metal gate high-k structure by filling the undercut structure and a remaining portion of the gate trench structure with a high-k dielectric material and a metal gate material, a first portion of the metal gate high-k structure that fills the remaining portion of the gate trench structure being removed to form a nitride structure in the remaining portion of the gate trench structure; removing the oxide layer to expose the metal gate high-k structure and the epitaxy layer; removing a second portion of the metal gate high-k structure, the second portion of the metal gate high-k structure being not directly under the nitride structure; forming an oxide spacer structure by depositing an oxide material into a void formed by removal of the second portion of the metal gate high-k structure; and forming a metal contact structure for the source and drain region.