Patent ID: 9348558
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. A processor, comprising: a multiplier configured to multiply two operands; an arithmetic logic unit configured to sum two operands; and sequencing logic that controls operation of the multiplier and the arithmetic logic unit during instruction execution; wherein the sequencing logic is configured to, as part of execution of a multiply and accumulate instruction: add, in the arithmetic logic unit, a product value generated by the multiplier to a previous output of the arithmetic logic unit; wherein the arithmetic logic unit includes a carry register configured to: store a carry flag generated by addition in the arithmetic logic unit, and provide the stored carry flag to the arithmetic logic unit for summation during execution of a double precision multiply and accumulate instruction; wherein the multiplier is a carry save array multiplier comprising an array of cascaded partial product generators, configured to: generate a first output value as a product of two operands presented at inputs of the multiplier; and generate a second output value as a sum of two operands presented at inputs of the multiplier.