Patent ID: 9446305
Filing Date: 2016-09-20
CPC Classification: A63F,H04H,H04L,H04N

Claim Text:
1. A computer implemented method for efficiently processing a video stream with a processor pipeline having a plurality of pipeline stages, comprising: identifying a bottleneck stage within the processor pipeline, the bottleneck stage having a first clock and processing frames of the video stream; receiving a feedback signal from the bottleneck stage at one or more upstream stages, at least one of the upstream stages having a second clock, the feedback signal including information as to time required by the bottleneck stage to operate on data and information as to time the data spent queued; and responsively adjusting the speed at which the one or more upstream stages are processing frames of the video stream to approximate the speed at which the bottleneck stage is processing the frames of the video stream, wherein the speed is adjusted, at least in part, by modifying a frequency of the second clock.