Patent ID: 9280625
Filing Date: 2016-03-08
CPC Classification: G06F

Claim Text:
1. In an electronic design automation (EDA) tool in a computer, a method for incrementally propagating slack margins in a circuit design while optimizing the circuit design by processing gates in the circuit design in a reverse-levelized order, the method comprising: after the EDA tool in the computer replaces a first gate with an alternative gate, the EDA tool in the computer marking outputs of source drivers that drive inputs of the alternative gate as out-of-date; in response to the EDA tool in the computer determining that an output of a source driver is marked out-of-date, the EDA tool in the computer performing at least the following operations: (1) computing a new arrival time at the output of the source driver, (2) propagating the new arrival time to inputs of gates that are driven by the output of the source driver, and (3) removing an out-of-date mark from the output of the source driver; in response to the EDA tool in the computer determining that an input of a second gate is marked out-of-date or that a slack margin was not computed for an output of the second gate, the EDA tool in the computer performing at least the following operations: (1) propagating arrival times from the input to the output of the second gate, and (2) marking the output of the second gate as having an out-of-date slack margin; and in response to the EDA tool in the computer determining that an output of a third gate is marked as having an out-of-date slack margin, the EDA tool in the computer performing at least the following operations: (1) computing new slack margins for the output of the third gate based on the old arrival time, new arrival time, and old slack margin at the output of the third gate, and (2) computing new slack margins for each input of the third gate based on a new margin at the output of the third gate and an arrival time from each input of the third gate to the output of the third gate.