Patent ID: 9349829
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a transistor device, the method comprising: forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure, the 2DEGs forming current channels of the transistor device; forming a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels; forming a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels; forming a plurality of spaced apart gate structures extending into the semiconductor heterostructure and comprising an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material; spacing the gate structures apart from one another in a direction perpendicular to a current flow direction of the transistor device so that current flows around and between the gate structures through regions of the semiconductor heterostructure disposed between adjacent ones of the gate structures via the 2DEG current channels when the transistor device is biased in an on-state; and configuring the gate structures to deplete the 2DEG current channels from sides of the gate structures in regions of the semiconductor heterostructure disposed between adjacent ones of the gate structures.