Patent ID: 9454631
Filing Date: 2016-09-27
CPC Classification: G06F,H01L

Claim Text:
1. A method for generating shapes for a design layout, said method comprising: providing a design layout including a conductive line level, an underlying conductive line level, and a via design level, said conductive line level including conductive-line-level design shapes that represent conductive line structures in a conductive line level in a target interconnect structure, said underlying conductive line level including underlying-conductive-line-level design shapes that represent underlying conductive line structures in an underlying conductive line level located underneath said conductive line level in said target interconnect structure, and said via design level including via-level design shapes that represent via structures that vertically interconnect said conductive line structures and said underlying conductive line structures, wherein said conductive-line-level design shapes include a plurality of decomposed design shapes having different colors, wherein each color corresponds to a different lithographic mask; and modifying, for a conductive-line-level design shape that overlaps with said via-level design shapes, decomposed design shapes corresponding to said conductive-line-level design shape such that each via overlap region in which said conductive-line-level design shape overlaps with said via-level design shapes is transformed into a stitch region in which two decomposed design shapes overlap by running an automated program on a computer configured to run said automated program.