Patent ID: 9312358
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a p-type substrate having an N-well formed from a portion of the p-type substrate via ion diffusion, wherein another portion of the p-type substrate blocked from ion diffusion forms an anode region and an interface between the N-well and the anode extends vertically from a top surface of the substrate to a bottom surface of the substrate; a cavity formed to a selected depth in the anode region and adjacent the N-well; a p-type doped region including p-type doped material deposited in the cavity of the anode adjacent the N-well, wherein the interface between the N-well and the anode provides a boundary of the p-type doped region and a p-n junction of the p-type doped region extends into the N-well and into the anode; and a gate stack formed on the N-well, the gate stack including a spacer, wherein an outer sidewall of the spacer is substantially aligned with the vertical interface between the N-well and the anode.