Patent ID: 9331089
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming a semiconductor substrate including a single first active area defined by a first isolation layer, wherein a gate insulating layer and a first conductive layer are stacked over the single first active area; forming a dielectric layer over the first conductive layer; forming a plurality of first contact holes passing through the dielectric layer; forming a second conductive layer on the dielectric layer to fill the plurality of first contact holes; forming a gate pattern by etching the second conductive layer, the dielectric layer, and the first conductive layer; forming an interlayer insulating layer over the single gate pattern; and forming a plurality of first contact plugs in the single first active area, wherein the plurality of first contact plugs are to be connected to the second conductive layer, and the plurality of first contact plugs are offset from the plurality of first contact holes to overlap the dielectric layer, and wherein the plurality of first contact plugs and the plurality of first contact holes overlap with the single first active area, and the plurality of first contact plugs are connected to the single gate pattern, including the first conductive layer and the second conductive layer, over the single first active area.