Patent ID: 9418749
Filing Date: 2016-08-16
CPC Classification: G11C

Claim Text:
1. A method of operating a nonvolatile memory device, the nonvolatile memory device comprising a plurality of cell strings including a first cell string, a second cell string, a third cell string and a fourth cell string, each of the plurality of cell strings comprising a plurality of serially-connected memory cells stacked on or above a substrate in a direction perpendicular to the substrate, the first cell string including a first ground selection transistor (GST) and a first string selection transistor (SST), the second cell string including a second GST and a second SST, the third cell string including a third GST and a third SST, the fourth cell string including a fourth GST and a fourth SST, the first through fourth cell strings being connected to a first bit-line, the method comprising: during a first interval, performing a preset operation, the preset operation including applying a plurality of first voltages simultaneously to a first string selection line (SSL), a second SSL, a third SSL, a fourth SSL, a first ground selection line (GSL) and a second GSL, to turn-on the first through fourth SSTs and the first through fourth GSTs, the first through fourth SSLs being connected to the first through fourth SSTs respectively, the first GSL being connected to the first GST and the second GST, the second GSL being connected to the third GST and the fourth GST; and during a second interval following the first interval, performing a read operation including: applying a plurality of second voltages to each of the first SSL and the first GSL to turn-on the first SST and the first GST; applying a plurality of third voltages to each of the second through fourth SSLs and the second GSL to turn-off the second through fourth SSTs, the third GST and the fourth GST; applying a selected read voltage to a selected wordline connected to the first through fourth cell strings; applying unselected read voltages to unselected wordlines connected to the first through fourth cell strings, each of the unselected read voltages being higher than the selected read voltage; and applying a pre-charge voltage higher than a ground voltage to the first bit-line, wherein the applying the plurality of second voltages and the applying the plurality of third voltages are simultaneously performed during the second interval.