Patent ID: 9397162
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.