Patent ID: 9465578
Filing Date: 2016-10-11
CPC Classification: G06F

Claim Text:
1. A method, comprising: receiving, by a dual-mode floating-point arithmetic circuit, an operating mode for a multiplication operation, wherein the operating mode is one of a 32-bit floating-point multiply-accumulate mode and a dual 16-bit floating-point mode dot-product mode, wherein power consumption of the dual-mode floating-point arithmetic circuit is reduced by: determining, by dual-mode booth encoder circuits within a dual-mode multiplier array circuit, based on the operating mode, nine recoding terms for a mantissa of at least one floating-point input operand; computing, by the dual-mode multiplier array circuit that is configurable to generate partial products for either one 32-bit floating-point result or for two 16-bit floating-point results, the partial products based on the nine recoding terms; and processing the partial products to generate an output based on the operating mode.