Patent ID: 9496240
Filing Date: 2016-11-15
CPC Classification: B23K,H01L

Claim Text:
1. A method of forming a wire loop in connection with a semiconductor package, the method comprising the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm on a computer and the package data provided in step (1), for forming the desired wire loop, wherein the deriving of the looping parameters includes using loop model data stored in the wire bonding machine in connection with the algorithm to more closely approximate the looping parameters related to the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).