Patent ID: 9252052
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a shallow trench laterally surrounding a stack of a top semiconductor portion, a buried insulator portion, and an upper portion of a handle substrate and located in a semiconductor-on-insulator (SOI) substrate; a stack of a dielectric metal oxide liner and a silicon nitride liner located at a bottom of said shallow trench; a shallow trench fill portion located within said shallow trench and vertically contacting said stack of said dielectric metal oxide liner and said silicon nitride liner; a contact-level dielectric layer located over said top semiconductor portion and said shallow trench fill portion; and a contact via structure extending through said contact-level dielectric layer and into a portion of said shallow trench and in contact with a vertical sidewall of said shallow trench fill portion and one of said dielectric metal oxide liner and said silicon nitride liner, wherein a portion of said contact via structure is located below a topmost surface of said top semiconductor portion.