Patent ID: 9515880
Filing Date: 2016-12-06
CPC Classification: G06F,H04J,H04L

Claim Text:
1. An integrated circuit, comprising: clock generation circuitry that supplies at least first and second clock signals, wherein the first clock signal is a global clock signal, and wherein the second clock signal is a local clock signal; reconfigurable circuitry with configurations corresponding to at least first and second modes, wherein the reconfigurable circuitry is coupled to a first type of client network in the first mode, and wherein the reconfigurable circuitry is coupled to a second type of client network that is different than the first type of client network in the second mode; and a clock selection circuit that routes the first clock signal to the reconfigurable circuitry when the reconfigurable circuitry is configured to operate in the first mode and that routes the second clock signal to the reconfigurable circuitry when the reconfigurable circuitry is configured to operate in the second mode.