Patent ID: 9336163
Filing Date: 2016-05-10
CPC Classification: G01R,G06F,G06T,G09G,G11C

Claim Text:
1. A memory control apparatus for issuing a command to control a memory including a plurality of banks, comprising: a command control unit configured to, based on a transfer request which is input, issue a command for a bank corresponding to the transfer request, said command control unit comprising: at least one processor functioning as: a transfer request storage unit configured to store the transfer request for each bank; a transfer request comparison unit configured to compare a column address of a transfer request stored at a first location of said transfer request storage unit with column addresses of a plurality of subsequent transfer requests; a command determination unit configured to determine based on a comparison result of said transfer request comparison unit whether to issue a command with precharge or a command without precharge for the transfer request stored at the first location of said transfer request storage unit, wherein, when the column addresses of the plurality of subsequent transfer requests are different from the column address of the transfer request stored at the first location of said transfer request storage unit, said command determination unit determines to issue a command without precharge in a case where the transfer request stored at the first location of said transfer request storage unit is a transfer for which burst termination is possible, and said command determination unit determines to issue a command with precharge in a case where the transfer request stored at the first location of said transfer request storage unit is a transfer for which burst termination is prohibited; and a command issuance unit configured to issue the command determined by said command determination unit.