Patent ID: 9525340
Filing Date: 2016-12-20
CPC Classification: H02M,H03K

Claim Text:
1. A boost capacitor circuit, comprising a first nMOS transistor and a voltage doubler circuit, the first nMOS transistor having a gate for providing a boosted voltage, the voltage doubler circuit comprising: a first pMOS transistor, having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter, having an input terminal for receiving a first signal; a second pMOS transistor, having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor, having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node, wherein a source and a drain of the first nMOS transistor are coupled to each other and further to the second node for receiving a second signal from the second node.