Patent ID: 9270994
Filing Date: 2016-02-23
CPC Classification: H04N

Claim Text:
1. A video decoder, comprising: an interface configured to receive a bit stream in tile order within a video frame that was encoded into rectangular tiles; and processing circuitry configured to decode the video frame while respecting dependency breaks at tile boundaries, wherein the rectangular tiles including an integer number of two-dimensional blocks of pixels, a tile shape of each of the rectangular tiles being defined by N×M two-dimensional blocks of pixels, respective values of N and M need not be identical for each of the rectangular tiles, and information regarding tile shape being conveyed from an encoder to the decoder, the decoder configured to determine the values of N and M for each tile from the information, the rectangular tiles having dependency breaks therebetween; wherein the processing circuitry is configured to process a maximum number of horizontal tiles and a maximum number of vertical tiles independent of a resolution of video frames, wherein the resolution of the video frames is determined by a width of the video frames and a height of the video frames.