Patent ID: 9356099
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a quantum well structure disposed above a substrate, said quantum well structure having an upper barrier layer above a quantum well layer; a trench, through said upper barrier layer disposed in said quantum well structure, and above said quantum well layer, said trench having sidewalls and a bottom; source/drain metal regions disposed on the quantum well structure and on either side of said trench; a gate electrode disposed in said trench; a gate dielectric layer on the bottom of said trench and between said gate electrode and said quantum well structure; and a dielectric material on the sidewalls of said trench and extending to the bottom of said trench, wherein said dielectric material is between said gate electrode and said source/drain metal regions, and between the sidewalls of said trench and said gate dielectric layer.