Patent ID: 9275724
Filing Date: 2016-03-01
CPC Classification: G11C

Claim Text:
1. A method, comprising: selecting a memory cell included in a memory cell array in which data is to be stored, wherein the memory cell array is connected with a logic gate array, and the memory cells of the memory cell array are individually coupled with a corresponding logic gate of the logic gate array by a separate word line output; communicating a write row output signal to the logic gate array, the write row output signal being communicated from a write address row decoder to the logic gate array, wherein the write address row decoder has a plurality of write row outputs coupled with the logic gate array; and communicating a write column output signal to the logic gate array, the write column output signal being communicated from a write address column decoder to the logic gate array, wherein the write address column decoder has a plurality of write column outputs coupled with the logic gate array.