Patent ID: 9280291
Filing Date: 2016-03-08
CPC Classification: G01R,G06F,G11C

Claim Text:
1. A method of fetching digital data and writing the digital data into one single memory of one single logic analyzer, comprising the steps of: A. designating a first region and a second region in the one single memory of the one single analyzer; B. setting a first triggering condition and a second triggering condition; C. fetching digital data and writing the digital data into the memory, wherein the digital data have first test data and second test data; the first test data have an identification, which satisfies the first triggering condition, and the second test data have an identification too, which satisfies the second triggering condition; D. finding the first test data and the second test data in the digital data, and then writing the first test data into the first region, and writing the second test data into the second region, wherein the digital data are restricted from being written into the first region once the first test data are found and written into the first region, and the digital data are restricted from being written into the second region once the second test data are found and written into the second region; and E. recording a first time point which indicates when the first test data are written into the first region, and recording a second time point which indicates when the second test data are written into the second region, wherein the first time point and the second time point are obtained by calculating a sum of products of an occurring cycle of a number of specific data and occurring counts of those specific data.