Patent ID: 9235423
Filing Date: 2016-01-12
CPC Classification: G06F

Claim Text:
1. An availability analysis device having a processor and memory, comprising: a state transition storage unit realized by the memory and configured to store definitions of a plurality of state transitions corresponding to configurations of a system, each of the definitions of the plurality of state transitions including a transition source state, a transition destination state and a transition probability; an additional state transition storage unit realized by the memory and configured to store definitions of a plurality of additional state transitions that are used when operating the system and that are different from the plurality of state transitions, each of the definitions of the plurality of additional state transitions including a transition source state, a transition destination state and a transition probability; an operation registration unit realized by the processor executing a program stored in the memory and configured to receive the definitions of the additional state transitions and register the definitions in the additional state transition storage unit; an availability analyzing unit realized by the processor executing the program stored in the memory and configured to analyze an availability indicating a ratio of time where the system is in operation, based on the definitions of the state transitions stored in the state transition storage unit and the definitions of the additional state transitions stored in the additional state transition storage unit; an operation analysis unit realized by the processor executing the program stored in the memory and configured to analyze a number of occurrences of each pair of the transition source state and the transition destination state in the definitions of the plurality of additional state transitions stored in the additional state transition storage unit; and an operation analysis result output unit realized by the processor executing the program stored in the memory and configured to output analysis results obtained by the operation analysis unit.