Patent ID: 9368600
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: forming a plurality of trenches in a semiconductor substrate, on opposite sides of a gate electrode of a P-type metal-oxide-semiconductor (PMOS) disposed on the semiconductor substrate; forming an embedded silicon germanium layer inside the trenches; doping the embedded silicon germanium layer with boron (B) having a first dopant concentration; then forming an undoped silicon layer directly on the embedded silicon germanium layer; then doping the undoped silicon layer with boron (B) having a second dopant concentration; and then lightly doping the undoped silicon layer with germanium (Ge), and an atomic percentage of the germanium (Ge) in the undoped silicon layer is from about 1% to about 10%. wherein the first dopant concentration is greater than the second dopant concentration, wherein an atomic percentage of germanium (Ge) in the embedded silicon germanium layer ranges from about 30% to about 50%, and wherein an atomic percentage of germanium (Ge) in the embedded silicon germanium layer is greater than the atomic percentage of germanium (Ge) in the undoped silicon layer.