Patent ID: 9412624
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method of manufacture of an integrated circuit packaging system comprising: providing a prepared carrier having a conductive carrier coating; depositing a first trace layer on the conductive carrier coating; forming a first via layer on the first trace layer, the first via layer having vertical sidewalk; forming an encapsulation on the first trace layer and the first via layer; planarizing the encapsulation for exposing a top surface of the first trace layer; forming a second trace layer over the first trace layer and on the encapsulation, the second trace layer connected to the first trace layer; removing the prepared carrier while leaving the conductive carrier coating on the first trace layer; removing all of the conductive carrier coating, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of the conductive carrier coating; applying a protective layer on the first trace layer and the second trace layer; and connecting an integrated circuit die to the first trace layer.