Patent ID: 9349468
Filing Date: 2016-05-24
CPC Classification: G11C

Claim Text:
1. A sense amplifier circuit for a memory circuit, comprising: a latch circuit; an intermediate circuit having an internal node connectable to one or more bit lines of an array of memory cells and connectable to the latch circuit; bit line selection circuitry connected to the internal node, whereby the internal node can selectively be connected to the one or more bit lines; an operational amplifier having a first input connected to receive a reference voltage and a second input connected to receive feedback from an output of the operational amplifier; and a first switch whereby the internal node is connectable to the output of the operational amplifier, wherein during a pre-charge phase of a sensing operation the first switch is turned on to set the internal node to a level of the operational amplifier's output, and wherein, during the pre-charge phase, the reference voltage is initially set to a first value and subsequently set to a second value, where the second value corresponds to a pre-charge level for the internal node and the first value is lower than the second.