Patent ID: 9424327
Filing Date: 2016-08-23
CPC Classification: G06F

Claim Text:
1. An apparatus, comprising: an execution unit to execute a first instruction and a second instruction, said execution unit including the following: input register space to store a first data structure to be replicated when executing said first instruction and to store a second data structure to be replicated when executing said second instruction, said first and second data structures both being packed data structures, data values of said first packed data structure being twice as large as data values of said second packed data structure; replication logic circuitry to replicate said first data structure when executing said first instruction to create a first replication data structure, and, to replicate said second data structure when executing said second instruction to create a second replication data structure; and masking logic circuitry to mask said first replication data structure at a first granularity and mask said second replication data structure at a second granularity, said second granularity being twice as fine as said first granularity.