Patent ID: 9466351
Filing Date: 2016-10-11
CPC Classification: G11C

Claim Text:
1. A method of refreshing a memory device comprising a plurality of volatile memory cells and a nonvolatile memory storing at least a first address, the first address corresponding to a first group of the plurality of volatile memory cells, the method comprising: in response to each of a series of refresh commands, refreshing a corresponding group of volatile memory cells corresponding to each refresh command; and in response to a first refresh command of the series of refresh commands and in response to accessing the first address stored in the nonvolatile memory, refreshing the first group of volatile memory cells, wherein the first refresh command corresponds to a second group of volatile memory cells other than the first group of volatile memory cells, the second group of volatile memory cells having a second row address, the second group of volatile memory cells being refreshed in response to the first refresh command, and wherein refreshing the first group of memory cells is performed in response to comparing only part of the second row address that does not include at least one bit of the second row address with corresponding address bits of the first address to determine if the first address matches the part of the second row address.