Patent ID: 9484110
Filing Date: 2016-11-01
CPC Classification: G11C

Claim Text:
1. A mask-programmed ROM (MROM) comprising: a column line pair including a bit line and a complement bit line; a plurality of memory cells, wherein each memory cell includes a pair of transistors comprising a first transistor coupled to the bit line and a second transistor coupled to the complement bit line, and wherein for each pair of transistors, one of the first and second transistors is a low threshold voltage (low Vt) transistor and a remaining one of the first and second transistors is a high threshold voltage (high Vt) transistor; a sense amplifier configured to sense a voltage difference between the bit line and the complement bit line; a choke device coupled between ground and a source of each of the first and second transistors, wherein the choke device is configured to reduce a gate-to-source voltage for the each of the first and second transistors to inhibit leakage current; a first PMOS transistor having its gate coupled to the complement bit line and a drain coupled to the bit line; and a second PMOS transistor having its gate coupled to the bit line and a drain coupled to the complement bit line.