Patent ID: 9419590
Filing Date: 2016-08-16
CPC Classification: H03K

Claim Text:
1. A toggle latch-based flip-flop circuit, comprising: a first logic gate; an input terminal of a toggle latch that is directly coupled to a first input terminal of the first logic gate; an output terminal of the toggle latch is coupled to the first input terminal of the first logic gate; a latch that is coupled to an output terminal of the first logic gate and to a clock; and a second logic gate including: wherein: the first logic gate further includes a data input terminal that is configured to receive a data input signal; the first logic gate is an exclusive-OR (XOR) gate; the first input terminal of the XOR gate is inverted; the data input terminal of the XOR gate is non-inverted; in response to the data input signal being a logical 0 and a data output signal on the output terminal of the toggle latch being a logical 0, the toggle latch is configured to toggle the output signal; in response to the data input signal being a logical 0 and the data output signal on the output terminal of the toggle latch being a logical 1, the toggle latch is configured to hold the output signal; in response to the data input signal being a logical 1 and the data output signal on the output terminal of the toggle latch being a logical 0, the toggle latch is configured to hold the output signal; and in response to the data input signal being a logical 1 and the data output signal on the output terminal of the toggle latch being a logical 1, the toggle latch is configured to toggle the output signal.