Patent ID: 9269660
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A three-dimensional stacked IC device comprising: a stack of at least first, second, third and fourth contact levels at an interconnect region; each contact level comprising a conductive layer and an insulation layer; at least first, second, third and fourth electrical conductors passing through corresponding portions of the stack of contact levels; the first, second, third and fourth electrical conductors in electrical contact with the first, second, third and fourth conductive layers, respectively; and a dielectric sidewall spacer circumferentially surrounding the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers, wherein the stack is formed at least in part through a set of masks for creating interconnect contact regions aligned with and exposing landing areas at the contact levels, the set of masks comprising: a set of N masks for creating a plurality of levels of interconnect contact regions at the stack of the contact levels, N being an integer equal to at least 2, and to etch contact openings to reach to up to 2 a first mask to etch one contact level for effectively half of the contact openings; and a second mask to etch two contact levels for effectively half of the contact openings, and wherein the set of masks further comprises a common mask for removing at least a portion of any upper layer overlying the interconnect region to expose the first contact level, the locations of the first, second, third and fourth electrical conductors being determined by the common mask.