Patent ID: 9355959
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A microelectronic structure comprising: (a) a first semiconductor chip having a body with oppositely-facing front and rear surfaces, first contacts exposed at the front surface, a cavity extending into the body from the rear surface, the cavity having a rearwardly-facing cavity floor surface, the first semiconductor chip having first via conductors extending into the first chip from the cavity floor surface, and (b) a second semiconductor chip disposed within the cavity, the second semiconductor chip having a top surface facing toward the cavity floor surface of the first chip, active circuit elements disposed in an active layer near the top surface, and a bottom surface facing in the same direction as the rear surface of the first chip, the second semiconductor chip having top contacts exposed at the top surface and electrically connected to at least some of the first via conductors, the second semiconductor chip having bottom contacts exposed at the bottom surface; a dielectric encapsulant layer disposed within the cavity and physically bonding the second semiconductor chip to the first semiconductor chip; wherein the bottom surface of the first chip comprises semiconductor material whose bottom surface is planar and is co-planar with a bottom surface of the dielectric encapsulant layer and with all of the bottom surface of the second chip except for the bottom contacts which protrude out of the bottom surface of the second chip.