Patent ID: 9377509
Filing Date: 2016-06-28
CPC Classification: G01R

Claim Text:
1. A test architecture within an integrated circuit comprising: A. a plurality of core wrappers each having a serial input, a serial output, and control inputs, the control inputs including a clock input, a shift input, a capture input, an update input, a reset input, an enable input, and a core select input; B. input circuitry having a serial input, a plurality of serial outputs, each selectively coupled to the serial input, and control inputs, each serial output being connected to the serial input of a core wrapper; C. output circuitry having a plurality of serial inputs, a serial output, and a control input, each serial input being connected to the serial output of a core wrapper and each serial input being selectively coupled to the serial output; and D. a link instruction register having a serial input, a serial output, control inputs, and control outputs,