Patent ID: 9419217
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a memory structure, comprising: forming a plurality of vertically-stacked horizontal line layers, each horizontal line layer including a plurality of electrically conductive horizontal lines; interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines such that the electrically conductive vertical lines extend through the horizontal line layers in between rows of electrically conductive horizontal lines except along edges of the horizontal line layers; forming a resistive memory film at and between the electrically conductive vertical lines and the electrically conductive horizontal lines to create a memory array of two-terminal memory elements; each electrically conductive vertical line disposed to serve as a shared bit line for accessing memory elements facing left with respect to a centerline of the electrically conductive vertical line and also as a shared bit line for accessing memory elements facing right with respect to the centerline of the electrically conductive vertical line; each electrically conductive horizontal line disposed to serve as a shared word line for the memory elements formed between the electrically conductive horizontal line and each electrically conductive vertical line that the electrically conductive horizontal line crosses, including at each such crossing, the left facing memory cell and the right facing memory cell, whereby the electrically conductive horizontal line accesses two rows of memory cells; fabricating a first set of global bit lines in front end of line (FEOL) circuitry below said memory array, wherein each one of the first set of global bit lines is electrically connected to a first subset of alternate ones of the electrically conductive vertical lines; fabricating a second set of global bit lines in back end of line (BEOL) circuitry above the memory array, wherein each one of the second set of global bit lines is electrically connected to a second subset of alternate ones of the electrically conductive vertical lines, wherein the first and second subsets are mutually exclusive; and fabricating: