Patent ID: 9437627
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a thin film transistor, comprising following steps: providing a substrate; forming a semiconductor layer on the substrate; forming a photoresist pattern having an uneven top surface on the semiconductor layer, wherein the photoresist pattern comprises a middle portion and two peripheral portions, the middle portion is disposed between the peripheral portions, and a thickness of the middle portion is greater than a thickness of each of the peripheral portions; performing an etching process with using the photoresist pattern as an etching mask on the semiconductor layer to remove the semiconductor layer uncovered by the photoresist pattern to form a patterned semiconductor layer; performing a photoresist ashing process to remove the peripheral portions to form a channel defining photoresist pattern and expose two portions of the patterned semiconductor layer; performing a conductivity-enhancing treatment with using the channel defining photoresist pattern as a mask on the two portions of the patterned semiconductor to form a semiconductor portion and two conductor portions in the patterned semiconductor layer, wherein the semiconductor portion is disposed between the conductor portions, and the semiconductor portion is covered with the channel defining photoresist pattern for being a channel; removing the channel defining photoresist pattern; wherein the step of forming the photoresist pattern comprises: performing a lithography process with using a binary mask, to form a photoresist material pattern on the semiconductor layer, wherein the photoresist material pattern comprises a flat top surface; and performing a baking process on the photoresist material pattern to form the photoresist pattern, wherein a processing temperature of the baking process is ranged from 70° C. to 150° C.