Patent ID: 9478580
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A method of manufacture of a photosensor array integrated circuit adapted to backside illumination comprising: forming N-channel MOS (NMOS) transistors in a first side of a device wafer; forming at least one heavily P-doped edge contact doped region, the heavily P-doped edge contact region formed in the first side of the device wafer; performing at least one metallization sequence comprising providing a structural layer, and thinning a second side of the device wafer; opening at least one substrate-stripped zone by removing silicon of the device wafer and exposing the at least one heavily P-doped edge-contact doped region to the substrate-stripped zone, the substrate-stripped zone associated with a bondpad; depositing backside metal on the second side of the device wafer with sidewall metal at edges of the substrate-stripped zone, the sidewall metal contacting the at least one heavily P-doped edge-contact doped region; and defining openings in the backside metal for windows over photosensors and isolation gaps between backside metal and other metal of the integrated circuit.