Patent ID: 9229053
Filing Date: 2016-01-05
CPC Classification: G01R,G06F

Claim Text:
1. A method for debugging a finite state machine (FSM) that sequences System-On-Chips (SOCs) through low power states including a lowest power state, comprising: implementing an on-chip debug logic circuit; connecting the debug logic circuit to a power gate-able voltage source of a system on chip (SoC); operating the finite state machine connected to an Always On voltage source to sequence the SoC through the low power states by moving from a low power state to a next low power state and generating respective output signals corresponding to the low power states; masking the respective output signals to generate respective masked output signals; applying the respective masked output signals to circuit elements of the SoC to prevent the debug logic circuit from transitioning into the low power states; applying the respective masked output signals to circuit elements of the debug logic circuit to prevent the debug logic circuit from entering into a reset state; and debugging the finite state machine in the lowest power state by the debug logic circuit.