Patent ID: 9362309
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor structure comprising: forming a first set of fins on a {110} wafer, each fin of the first set of fins having a top surface and two sidewalls, wherein each fin of the first set of fins is oriented with its top oriented parallel to a {110} plane and its sidewalls parallel to a {100} plane, and forming a second set of fins on the {110} wafer, each fin of the second set of fins having two sidewalls, wherein each fin of the second set of fins is oriented with its top oriented parallel to a {110} plane and its sidewalls not oriented to a {100} plane; merging the first set of fins, while preserving the second set of fins as unmerged fins, wherein the merging comprises forming an epitaxial semiconductor region on the first set of fins and an epitaxial semiconductor region on the second set of fins; and wherein forming the epitaxial semiconductor region on the first set of fins comprises growing the epitaxial semiconductor region laterally therefrom at a first growth rate, and forming the epitaxial semiconductor region on the second set of fins comprises growing the epitaxial semiconductor region laterally therefrom at a second growth rate, wherein the first growth rate is faster than the second growth rate.