Patent ID: 9368624
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method for fabricating a transistor with reduced junction leakage current, comprising: forming a layered stack, the layered stack including at least a doped screening layer and an undoped channel layer over the doped screening layer; forming a gate over the undoped channel layer, the gate having an effective gate length; forming a source region on one side of the gate and a drain region on another side of the gate; wherein a depth of the doped screening layer is set a preselected distance below the gate such that the distance is a fraction of the effective gate length of the transistor, a thickness of the doped screening layer is preselected such that a bottom of the doped screening layer is above a bottom of the source region and a bottom of the drain region, the doped screen layer extends laterally to and contacts both the source region and the drain region, and further comprising: