Patent ID: 9311137
Filing Date: 2016-04-12
CPC Classification: G06F

Claim Text:
1. A method implemented by a data processing system, for executing a set of instructions while receiving interrupts, the method comprising: executing a set of instructions; receiving an interrupt; responsive to determining that the interrupt fails to have an implementation time frame, suspending processing of the interrupt for a predetermined time period; responsive to completing the set of instructions within the predetermined time period, processing the interrupt; responsive to determining that the interrupt has an implementation time frame, determining whether a delay mode is active; responsive to the delay mode being active, delaying processing of the interrupt, thereby forming a delayed interrupt, and setting keeper logic in order to maintain a state for the delayed interrupt; starting a delay counter that incremented on every processor cycle; on every clock cycle: responsive to the delay mode failing to be active, processing the delayed interrupt and aborting the set of instructions.