Patent ID: 9397674
Filing Date: 2016-07-19
CPC Classification: H03L,H04L

Claim Text:
1. A clock and data recovery device comprising: a phase detector coupled to an input node for producing phase error samples at an output; a quantizer, coupled to the output of the phase detector and responsive to a high threshold value and a low threshold value different from the high threshold value, for producing tri-valued quantized phase error samples at an output; a loop filter coupled to the output of the quantizer; a jitter frequency detector having an output and an input, the input coupled to the output of the quantizer; a multiplexer, disposed between the loop filter and the output of the quantizer and having a control input coupled to the output of the jitter frequency detector, configured to selectively couple either the phase error samples or the quantized phase error samples to the loop filter in response to the jitter frequency detector.