Patent ID: 9461154
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A trench gate MOS semiconductor device, comprising: a first-conductivity-type semiconductor substrate; a second-conductivity-type floating region that is provided in a surface layer of one main surface of the first-conductivity-type semiconductor substrate and that will be a drift layer; a plurality of trenches that reach a predetermined depth from the one main surface of the first-conductivity-type semiconductor substrate and that are arranged in a parallel pattern; a second-conductivity-type base region that is formed in a surface layer of a portion of the first-conductivity-type semiconductor substrate, which is interposed between the plurality of trenches arranged in a parallel pattern, and that is separated from the second-conductivity-type floating region by one trench of the plurality of trenches; a first-conductivity-type emitter region that is formed in a surface layer of the second-conductivity-type base region so as to come into contact with said one trench; an emitter electrode that comes into contact with the second-conductivity-type base region and the first-conductivity-type emitter region, and that covers the second-conductivity-type floating region; an interlayer insulating film interposed between the emitter electrode and the second-conductivity-type floating region; and a first conductive polysilicon electrode and a second conductive polysilicon electrode that are formed in said one trench along respective side surfaces thereof so as to be separated from each other by an insulating film that surrounds a cavity, the insulating film and cavity being interposed there between, wherein the entire cavity is interposed between the first conductive polysilicon electrode and the second conductive polysilicon electrode, and wherein the first conductive polysilicon electrode and the second conductive polysilicon electrode are connected to different electrodes.