Patent ID: 9437435
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method for forming an LTPS TFT having a dual-gate structure, comprising: forming a plurality of patterned a-Si layers disposed on a substrate; forming a barrier layer on the plurality of patterned a-Si layers; forming a first patterned poly-Si layer and a second patterned poly-Si layer on the barrier layer; coating a first photoresist layer on a top surface of the second patterned poly-Si layer and surrounding the second patterned poly-Si layer; forming an N-type channel by doping the first patterned poly-Si layer; removing the first photoresist layer from the second patterned poly-Si layer; forming a gate insulation layer on both of the second patterned poly-Si layer and the first patterned poly-Si layer where the N-type channel is formed; forming a second photoresist layer on the gate insulation layer, and doping the second patterned poly-Si layer to form a P removing the second photoresist layer from the gate insulation layer, and coating a third photoresist layer on the gate insulation layer; removing a part of the third photoresist layer, a part of the gate insulation layer, and a part of the barrier layer by performing exposing and developing processes, for forming a plurality of openings; N forming a plurality of patterned GE layers on the gate insulation layer; N forming an ILD on the plurality of patterned GE layers and the gate insulation layer; forming a plurality of via holes penetrating the ILD and the gate insulation layer; and forming a plurality of patterned source/drain electrodes through the plurality of via holes, the plurality of patterned source/drain electrodes connected to the P