Patent ID: 9257373
Filing Date: 2016-02-09
CPC Classification: H01L,H05K

Claim Text:
1. An electronic component device comprising: a coreless wiring board including: a wiring formation region including a chip mounting region, and the wiring formation region in which a plurality of wiring layers are stacked while sandwiching insulating layers, wherein an outermost insulating layer of the insulating layers is disposed at a top surface of the coreless wiring board, outermost wiring layer of the wiring layers are buried in the outermost insulating layer, a top surface of the outermost wiring layer is exposed at a surface of the outermost insulating layer, and a side surface and a back surface of the outermost wiring layer are covered by the outermost insulating layer; an outer periphery region which is arranged to surround the wiring formation region; a plurality of reinforcing patterns stacked on the outer periphery region, and formed in the same layer as each of the wiring layers, wherein an outermost reinforcing pattern of the reinforcing patterns is buried in the outermost insulating layer, a top surface of the outermost reinforcing pattern is exposed at the surface of the outermost insulting layer, and a side surface and a back surface of the outermost reinforcing pattern are covered by the outermost insulating layer, wherein each layer in the reinforcing patterns includes a pattern in which a plurality of land patterns are arranged, or a mesh pattern, and a pattern part of one layer in the reinforcing patterns is overlapped with a non-forming region of another layer in the reinforcing patterns thereby, the reinforcing patterns exist without a gap in the outer periphery region when the wiring board is viewed in planar perspective; and an electronic component connected to the outermost wiring layer in the chip mounting region of the wiring board.