Patent ID: 9368193
Filing Date: 2016-06-14
CPC Classification: G11C

Claim Text:
1. A memory cell having a front side and a back side, said memory cell comprising: a semiconductor substrate; a PMOS transistor disposed on said front side; a P well disposed on said front side, said P well forming at least one P well-to-substrate PN-junction; an NMOS transistor located in said P well; a ground terminal disposed on said front side and electrically connected to said P well; and a power supply terminal disposed on said front side and electrically connected to the source of said PMOS transistor, said power supply terminal having a voltage equal to a margin-free constant data retention voltage (DRV); wherein said memory cell is optically refreshed by a refreshing photocurrent in response to light generated by a light source; wherein said at least one P well-to-substrate PN-junction generates a parasitic photocurrent that flows into said at least one ground terminal and wherein said PMOS transistor is located in an N well located in a deep P well, said deep P well forming a PN-junction with said substrate such that said deep P well-to-substrate PN junction generates said memory cell refreshing photocurrent in response to light generated by said light source.