Patent ID: 9508423
Filing Date: 2016-11-29
CPC Classification: G11C

Claim Text:
1. A method, executed by a memory controller, of reading data stored by memory cells of a nonvolatile memory device addressed by a selected word line, the method comprising: reading a flag bit value stored by a first memory cell addressed by the selected word line; identifying the selected word line as least-significant bit (LSB) programmed when the flag bit has a first value and identifying the selected word line as most-significant bit (MSB) programmed when the flag bit has a second value differing from the first value; applying a first read voltage to the selected word line to identify, as the number of failed-read cells, the number of memory cells addressed by the selected word line storing a voltage exceeding the first read voltage; and applying a second read voltage to the selected word line to perform a read operation of the memory cells addressed by the selected word line, wherein: the second read voltage exceeds a third read voltage by a first amount when the identified number of failed-read cells exceeds a first threshold number and the selected word line is identified as LSB programmed, the third read voltage has a level for distinguishing, for each of the memory cells, an erase state from a program state adjacent to the erase state, and the selected word line is LSB programmed when all memory cells addressed by the selected word line are programmed to store no more than one bit of data and the selected word line is MSB programmed when a memory cell addressed by the selected word line, other than the first memory cell, is programmed to store more than one bit of data.