Patent ID: 9425194
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. An integrated circuit product, comprising: a first transistor positioned in and above a first active region of a semiconducting substrate, wherein said first transistor comprises a first gate material stack and has a first gate length, said first gate material stack comprising a first gate dielectric layer having a first thickness positioned above said first active region and at least one layer of metal positioned above said first gate dielectric layer, wherein said first gate dielectric layer comprises a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on said layer of said first high-k insulating material; and a second transistor positioned in and above a second active region of said semiconducting substrate, wherein said second transistor comprises a second gate material stack and has a second gate length, said second gate material stack comprising a second gate dielectric layer having a second thickness positioned above said second active region and at least one layer of metal positioned above said second gate dielectric layer, wherein said second gate dielectric layer comprises a layer of said second high-k insulating material, said second gate length being less than said first gate length and said second thickness being less than said first thickness.