Patent ID: 9466715
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A metal-oxide-semiconductor (MOS) transistor in a semiconductor substrate, comprising: a well region of a first conductivity type extending into the semiconductor substrate; a source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type in opposite sides of the well region, wherein the well region has a first portion laterally adjacent to the drain region, a second portion laterally adjacent to the source region and a third portion laterally between the first portion and the second portion; a first gate dielectric layer over and overlapped with the first portion of the well region; a second gate dielectric layer over and overlapped with the first portion and the third portion of the well region, and over the first gate dielectric layer, and in contact with a side surface of the first gate dielectric layer, wherein the side surface of the first gate dielectric layer is adjacent to the drain region; a third gate dielectric layer over and overlapped with the first portion, the second portion and the third portion of the well region, and over the first gate dielectric layer and the second gate dielectric layer, and in contact with a side surface of the second gate dielectric layer, wherein the side surface of the second gate dielectric layer is adjacent to the drain region; and a gate electrode over the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer.