Patent ID: 9455714
Filing Date: 2016-09-27
CPC Classification: H03K

Claim Text:
1. A configurable logic element for a programmable integrated circuit (IC), comprising: a first lookup-table (LUT) including a first logic gate, first sum logic, and first carry logic, where first, second, and third inputs of the first carry logic are respectively coupled to a first input of the first logic gate, a first input of the first sum logic, and an output of the first logic gate, and where a second input of the first sum logic coupled to the output of the first logic gate; a first cascade multiplexer having an output coupled to the first input of the sum logic; a second cascade multiplexer having an input coupled to an output of the first carry logic; and a second LUT including a second logic gate and second sum logic, where first and second inputs of the second sum logic are respectively coupled to an output of the second logic gate and an output of the second cascade multiplexer.