Patent ID: 9337820
Filing Date: 2016-05-10
CPC Classification: H03K

Claim Text:
1. A duty cycle adjustment apparatus of an integrated circuit (IC), comprising: a duty cycle adjustment determination module configured to determine an adjustment to a duty cycle of a clock signal; a clock delay module configured to receive the clock signal, to delay the clock signal through a first delay stage module and a second delay stage module based on the duty cycle adjustment determined by the duty cycle adjustment determination module, and to output the delayed clock signal, the first delay stage module comprising a first plurality of delay paths, the second delay stage module comprising a second plurality of delay paths, the second plurality of delay paths having a greater delay difference between each of the corresponding delay paths than the first plurality of delay paths; and a duty cycle adjustment module configured to receive the clock signal and the delayed clock signal, to adjust the duty cycle of the clock signal based on the delayed clock signal, and to output a duty cycle adjusted clock signal.