Patent ID: 9509258
Filing Date: 2016-11-29
CPC Classification: H03F

Claim Text:
1. A signal amplifier comprising: a first common gate-type amplifying unit connected to a source voltage terminal, configured to divide an input signal into two signals, configured to amplify the two divided signals, respectively, and configured to provide a first signal and a second signal, wherein the first common gate-type amplifying unit includes: a second common gate-type amplifying unit connected between the first common gate-type amplifying unit and a ground, configured to divide the input signal into two signals, configured to amplify the two divided signals, respectively, and configured to provide a third signal and a fourth signal, wherein the first NMOS transistor and the first PMOS transistor are connected to each other in series between the source voltage terminal and the second common gate-type amplifying unit, to form a single current path; a signal summing unit configured to sum the first signal and the second signal from the first common gate-type amplifying unit and the third signal and the fourth signal from the second common gate-type amplifying unit; and an impedance matching unit configured to impedance-match a signal summed by the signal summing unit, wherein the first common gate-type amplifying unit and the second common gate-type amplifying unit form a single current path between the source voltage terminal and a ground terminal.