Patent ID: 9305921
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, wherein a height of the second insulator is greater than a height of the second gate pattern wherein the height of the second insulator is greater than a height of the first insulator, and wherein the first gate pattern includes a first high-k gate insulation film, the first high-k gate insulation film being formed on the sidewalls and a bottom surface of the first gate pattern, and the second gate pattern includes a second high-k gate insulation film, the second high-k gate insulation film being formed on the sidewalls and a bottom surface of the second gate pattern.