Patent ID: 9444324
Filing Date: 2016-09-13
CPC Classification: H02M,Y02B

Claim Text:
1. A synchronous DC-DC converter comprising: a clock signal generator which generates a first clock signal; a gate driving part which is connected to the clock signal generator and outputs a first delay clock signal and a second delay clock signal with respect to the first clock signal generated by the clock signal generator; a switching part which is connected to the gate driving part and includes a first switching element and a second switching element which are complementarily switched according to each of the first delay clock signal and the second delay clock signal; and a controller which is connected to the switching part and configured to detect a dead time error by using a voltage difference between terminals of the switching part and generate, based the detected dead time error, a control signal which is usable by the gate driving part in order to control a dead time between the first switching element and the second switching element; a dead time error detector detecting the dead time error; a dead time error accumulator accumulating the detected dead time error; and a control signal generator generating the control signal in accordance with an output signal of the dead time error accumulator, wherein the first delay clock signal and the second delay clock signal are applied to a gate of the first switching element and a gate of the second switching element respectively, wherein a drain of the first switching element and a drain of the second switching element are connected to each other at a coupling node, wherein the dead time error detector detects a voltage difference between the drain and a source of the first switching element and transmits current caused by the voltage difference to the dead time error accumulator during the dead time, wherein the dead time error detector corn arises a current mirror including a first transistor and a second transistor whose control terminals are connected to each other and whose one ends are connected to the drain and the source of the first switching element respectively, wherein a switch for transmitting the current to the dead time error accumulator only during the dead time is connected between the dead time error accumulator and the other end of the first transistor, and wherein a reference current source is connected between a ground terminal and the other end of the second transistor.