Patent ID: 9449677
Filing Date: 2016-09-20
CPC Classification: G11C,H01L

Claim Text:
1. A method of operating a semiconductor memory device comprising a semiconductor substrate including first and second spaced apart source/drain regions defining a channel region therebetween, a control gate structure on the channel region, and a memory storage capacitor electrically coupled to the second source/drain region, the method comprising: applying a write/read-enable voltage to the control gate structure across the channel region to allow electrical current flow through the channel region between the first and second source/drain regions; while applying the write/read-enable voltage, applying a write signal through the first source/drain region, the channel region, and the second source/drain region to the memory storage capacitor to charge/discharge the memory storage capacitor thereby writing a memory value to the memory storage capacitor; and after applying the write signal, applying different first and second stand-by voltages to different portions of the control gate structure adjacent the channel region to maintain the memory value of the memory storage capacitor.