Patent ID: 9508716
Filing Date: 2016-11-29
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region; patterning the insulating material to expose a first portion of the N-FET region and a second portion of the P-FET region; forming an oxide layer over the first portion of the N-FET region and the second portion of the P-FET region; altering the oxide layer on the second portion of the P-FET region and not altering the oxide layer on the first portion of the N-FET region; forming a metal layer over the first portion of the N-FET region and the second portion of the P-FET region; annealing the workpiece so that the metal layer reacts with a material on the second portion of the P-FET region to form a metal compound but does not react with the first portion of the N-FET region; and forming a conductive layer over the first portion of the N-FET region and the second portion of the P-FET region, the metal layer being interposed between the oxide layer and the conductive layer over the first portion of the N-FET region.