Patent ID: 9263144
Filing Date: 2016-02-16
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a first sub-array including a plurality of first memory cells stacked above a semiconductor substrate; a second sub-array including a plurality of second memory cells stacked above the semiconductor substrate; a first bit line electrically connected to a first group of the first memory cells; a second bit line electrically connected to a first group of the second memory cells; a bit line connection unit configured to connect the first bit line and the second bit line; a first sense amplifier configured to receive a first voltage from either of the first bit line or the second bit line in a read operation, and transfer a second voltage to either of the first bit line or the second bit line in a write operation; a first source line electrically connected to the first memory cells; a second source line electrically connected to the second memory cells; and a source line driver configured to apply voltages to the first source line and the second source line, wherein the first sense amplifier is electrically connected to the first bit line on the condition that the first bit line is disconnected from the second bit line in either the read operation of the first memory cells or the write operation of the first memory cells, the bit line connection unit electrically connects the first bit line to the second bit line in either the read operation of the second memory cells or the write operation of the second memory cells, and the source line driver applies an erase voltage to the first source line and does not apply the erase voltage to the second source line in an erase operation of the first memory cells.