Patent ID: 9281270
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A method for making contact with a semiconductor, wherein the semiconductor ( 10 , 10 ′, 10 ″) is surface-connected to at least one first contact partner ( 20 , 20 ′, 20 ″, 60 ″) on at least one first surface by providing a first solder layer ( 30 , 32 ′, 34 ′, 36 ′, 30 ″, 80 ″) that has a predetermined thickness (LD), characterized in that a solder-resistant layer of polyimide ( 14 , 14 ′, 14 ″, 18 ′) is provided as a restricting means on the semiconductor ( 10 , 10 ′, 10 ″) and said solder-resistant polyimide layer determines at least one of the dimensions and the shape of at least one solder area ( 12 , 12 ′, 12 ″) of the semiconductor ( 10 , 10 ′, 10 ″) and prevents the semiconductor ( 10 , 10 ′, 10 ″) from floating and displacing laterally during the soldering process, and in that a lateral spacing (A) between at least one contact surface ( 20 . 2 , 22 . 2 ′, 24 . 2 ′, 26 . 2 ′, 20 . 2 ″) of the at least one first contact partner ( 20 , 20 ′, 20 ″, 60 ″) and a border of the solder-resistant polyimide layer ( 14 , 14 ′, 14 ″, 18 ′) is selected in dependence upon the thickness (LD) of the first solder layer ( 30 , 32 ′, 34 ′, 36 ′, 30 ″, 80 ″).