Patent ID: 9330772
Filing Date: 2016-05-03
CPC Classification: G11C

Claim Text:
1. A non-volatile semiconductor memory device comprising a memory cell array including a plurality of memory cells, the plurality of memory cells including a first memory cell and a second memory cell; a plurality of word-lines including a first word-line; and a control circuit, the memory cell array comprising, a semiconductor substrate, a first semiconductor layer extending in a direction perpendicular to the semiconductor substrate, and functioning as a body of the first memory cell, a charge accumulation layer, and a first conductive layer provided to sandwich the charge accumulation layer with the first semiconductor layer, and functioning as a gate of the first memory cell and a first word-line; the control circuit being configured to perform a write operation when the non-volatile semiconductor memory device receives a first instruction for executing the write operation, suspend the write operation when the non-volatile semiconductor memory device receives a suspend command during the write operation, resume the write operation when the non-volatile semiconductor memory device receives a resume command after the non-volatile semiconductor memory device suspends, and output a first signal and a second signal to a controller when the non-volatile semiconductor memory device receives a status command after the non-volatile semiconductor memory device suspends and before the non-volatile semiconductor memory device resumes, the first signal and the second signal indicating whether the write operation is completed or not and that the write operation is suspended.