Patent ID: 9397114
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A method of fabricating a three-dimensional semiconductor, comprising: forming a stack structure on a substrate, the stack structure including a plurality of insulating layers and a plurality of sacrificial layers, the insulating layers alternating with the sacrificial layers; forming at least one first trench and a plurality of second trenches, the first and second trenches separating the stack structure into a plurality of mold structures, the at least one first trench between the second trenches; forming first vertical insulating separators in the first and second trenches; forming semiconductor patterns penetrating the mold structure, the semiconductor patterns being spaced apart from the first and second trenches; removing the first vertical insulating separator from the second trench to expose the sacrificial layers; removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separators; and forming conductive patterns in the recess regions.