Patent ID: 9391017
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A semiconductor integrated circuit comprising: one or more power supply strap wires arranged in a first routing layer and extending in a first direction; one or more auxiliary power supply strap wires arranged in a second routing layer below the first routing layer and extending in the first direction; intermediate power supply wires arranged in a third routing layer between the first and second routing layers, each of the intermediate power supply wires electrically connecting one of the power supply strap wires to one of the auxiliary power supply strap wires through at least a via plug arranged between the first and third routing layers and at least a via plug arranged between the second and third routing layers; power supply rails arranged in a fourth routing layer below the second routing layer, extending in a second direction perpendicular to the first direction, and electrically connected to the auxiliary power supply strap wires; and upper power supply strap wires arranged in a fifth routing layer above the first routing layer, extending in the second direction, and electrically connected to the power supply strap wires, wherein an interval in the first direction between the intermediate power supply wires is larger than an interval in the first direction between the power supply rails, and is smaller than an interval in the first direction between the upper power supply strap wires.