Patent ID: 9530759
Filing Date: 2016-12-27
CPC Classification: H01L

Claim Text:
1. A device comprising: a first integrated circuit die including a transistor formed at a top surface of the first integrated circuit die and a conductive through via extending from the top surface to a bottom surface of the first integrated circuit die; a metallization layer over the top surface of the first integrated circuit die; contact pads disposed over the metallization layer; a protection layer disposed over the contact pads; a first redistribution layer (RDL) disposed over the protection layer and extending to the contact pads through openings in the protection layer; first connectors disposed over/on the first RDL; a molding compound over the first RDL and around the first connectors; a second RDL disposed on the bottom surface of the first integrated circuit die and electrically connected to the conductive through via; and a second integrated circuit die mounted to the bottom surface of the first integrated circuit die and electrically connected to the second RDL.