Patent ID: 9385202
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. An insulated gate semiconductor device structure comprising: a region of semiconductor material having a major surface and a first conductivity type; a first trench extending from the major surface; a second trench extending from the major surface and spaced apart from the first trench; a first dielectric layer formed along lower surfaces of both the first and second trenches and at least a portion of a first upper surface of both the first and second trenches; a second dielectric layer formed along at least a portion of a second upper surface of both the first and second trenches but not along the first upper surfaces of both the first and second trenches, wherein the second dielectric layer is thinner than the first dielectric layer; a first conductive electrode formed within the first trench along the first and second dielectric layers; and a second conductive electrode formed within the second trench along the first and second dielectric layers, wherein the first and second conductive electrodes and the second dielectric layer are configured to control a channel region within the region of semiconductor material.