Patent ID: 9443716
Filing Date: 2016-09-13
CPC Classification: C23C,H01L

Claim Text:
1. A semiconductor device processing method comprising: providing a substrate having a photoresist features thereon, each of the features having a top, sidewalls and a width; depositing up to 10 layers of an initial spacer film using a first process condition to decrease the width of the photoresist features; depositing additional spacer film on the initial spacer film using a second process condition to form a an integrated spacer film having a total thickness less than about 50 nm; etching the integrated spacer film from the top of the photoresist features leaving the integrated spacer film on the sidewalls of the photoresist features; removing the photoresist features to leave the integrated spacer film and expose portions of the substrate previously occupied by the photoresist features; and etching the exposed portions of the substrate to form adjacent pairs of substrate features.