Patent ID: 9312182
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method of forming conductive structures for a transistor device formed above an active region of a semiconducting substrate surrounded by an isolation region, the method comprising: forming a gate structure that is positioned above said active region and said isolation region; forming a gate cap layer above said gate structure, said gate cap layer having substantially a same initial thickness profile above the entire gate structure; performing at least one recess etching process on a first portion of said gate cap layer positioned above said isolation region while masking a second portion of said gate cap layer positioned above said active region so as to thereby define a modified gate cap layer comprising a modified first portion having a modified thickness profile positioned above said isolation region and said second portion having said initial thickness profile positioned above said active region, said modified thickness profile having a reduced-thickness portion relative to said initial thickness profile; forming a gate contact opening that extends through said reduced-thickness portion of said modified gate cap layer and exposes said gate structure; and forming a gate contact in said gate contact opening.