Patent ID: 9461165
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A semiconductor device having a surrounding gate transistor (SGT), the semiconductor device comprising: a semiconductor pillar formed on a substrate; a first impurity region formed in a lower part of the semiconductor pillar and containing a donor or acceptor impurity; a second impurity region formed in a top portion of the semiconductor pillar, the second impurity region being disposed above the first impurity region, containing a donor or acceptor impurity, and having the same conductivity type as the first impurity region; a first insulating layer surrounding an outer periphery of the semiconductor pillar between the first impurity region and the second impurity region; a first conductor layer surrounding an outer periphery of the first insulating layer; an electrically conductive or nonconductive first material layer surrounding an outer periphery of the first conductor layer; a second insulating layer which is disposed at a position higher than the first conductor layer and is in contact with an upper end surface of the first material layer; a third insulating layer covering the substrate and the semiconductor pillar; a contact hole formed in the third insulating layer, surrounding the top portion of the semiconductor pillar, and having a bottom portion that is in contact with a surface layer portion of the second insulating layer, in which an outer periphery of the bottom portion is located inside an outer periphery of the first material layer in plan view; and a second conductor layer that is, in the contact hole, in contact with the surface layer portion of the second insulating layer and in contact with a side face of the top portion of the semiconductor pillar in which the second impurity region is formed, wherein an SGT is formed in which one of the first impurity region and the second impurity region functions as a source and the other functions as a drain, a part of the semiconductor pillar between the first impurity region and the second impurity region functions as a channel, the first insulating layer functions as a gate insulating layer, the first conductor layer functions as a gate conductor layer, and the second conductor layer is electrically connected to the second impurity region located in the top portion of the semiconductor pillar.