Patent ID: 9502447
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. An array substrate comprising a base substrate, a gate line, a data line and a thin film transistor arranged in an array on the base substrate, a pixel electrode and a passivation layer, the thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode, wherein the pixel electrode and the active layer, the drain electrode are disposed in a same layer and formed integrally, the thin film transistor is a top-gate type thin film transistor, the array substrate comprises: the active layer, the drain electrode and the pixel electrode on the base substrate; a first insulating layer on the active layer, the drain electrode and the pixel electrode; the gate line and the gate on the first insulating layer; a second insulating layer on the gate line and the gate electrode; the data line and the source electrode on the second insulating layer; and the passivation layer on the data line and the source electrode, wherein the first insulating layer and the second insulating layer are provided therein with a via hole corresponding to the active layer, and the source electrode of the thin film transistor is connected with the active layer through the via hole; the source electrode is disposed in a layer different from the pixel electrode, the active layer and the drain electrode.