Patent ID: 9437705
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a spacer for an electronic memory, the electronic memory comprising: a substrate which extends along a reference plane; a first gate structure deposited on the substrate, the first gate structure having at least one lateral flank; a stack comprising a plurality of layers whereof at least one of said layers is able to store electric charges, said stack covering at least the at least one lateral flank of the first gate structure and a portion of the substrate; said method comprising: depositing a spacer material layer at least on an area covered by the stack; ion beam machining the spacer material layer, said ion beam machining being carried out with controlled stopping, so as to preserve a residual portion of the thickness of the spacer material layer covering the stack; plasma etching the residual portion of the thickness of the spacer material layer, and following the plasma etching, second plasma etching the stack which is not covered by the spacer material after the plasma etching, said second plasma etching being carried out selectively relative to the spacer material.