Patent ID: 9443582
Filing Date: 2016-09-13
CPC Classification: G11C

Claim Text:
1. A method for testing a nonvolatile memory device, the method comprising: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device; determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level; determining a number of first fail bits generated in the first resistance dispersion based on the lower test bias level and a number of second fail bits generated in the second resistance dispersion based on the upper test bias level; determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits; and trimming the reference bias level to the selected reference bias level, wherein the lower test bias level is spaced apart by a first margin from the reference bias level, the upper test bias level is spaced apart by a second margin from the reference bias level, and the first margin and the second margin are different from each other.