Patent ID: 9466696
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A device comprising: a first semiconductor fin and a second semiconductor fin parallel to each other; a gate dielectric on sidewalls of the first semiconductor fin and the second semiconductor fin; a gate electrode over the gate dielectric, with the gate dielectric and the gate electrode comprised in a Fin Field-Effect Transistor (FinFET); and isolation regions comprising: a source/drain region comprising a lower portion lower than the second top surfaces, wherein the first semiconductor fin has a first width, and the lower portion of the source/drain region has a second width equal to the first width, with both the first width and the second width measured at a same level as the second top surfaces, and wherein both the first width and the second width are measured in a same direction perpendicular to a source-to-drain direction of the FinFET.