Patent ID: 9349430
Filing Date: 2016-05-24
CPC Classification: G11C

Claim Text:
1. A memory device, comprising: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation in the memory blocks; and a refresh control block suitable for controlling a 1 st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed, and when a target refresh operation is performed, controls a word line corresponding to the target address to be refreshed.