Patent ID: 9368166
Filing Date: 2016-06-14
CPC Classification: G11C

Claim Text:
1. A nonvolatile memory device, comprising: a cell array including a plurality of cell strings extending on a substrate in a vertical direction, memory cells in each of the cell strings being controlled by a plurality of word lines and a plurality of bit lines; a page buffer connected to the plurality of bit lines and configured to store sensing data of the cell array in a sensing operation; a voltage generator configured to apply a bias voltage to at least one of the plurality of word lines and the plurality of bit lines prior to the sensing operation and to enable execution of the sensing operation; an input/output buffer configured to output the sensing data to an external device before completion of a recovery operation, in which the bias voltage applied to the at least one of the plurality of word lines and plurality of bit lines for the sensing operation is discharged; and a control logic configured to set a status of the nonvolatile memory device to a ready state before the recovery operation of the cell array from the applied bias voltage of the sensing operation is completed, wherein: the control logic is configured to provide the page buffer with a dump signal such that the sensing data is dumped from the page buffer to the input/output buffer, and the control logic comprises a status generator configured to set the status to the ready state in response to the dump signal.