Patent ID: 9448581
Filing Date: 2016-09-20
CPC Classification: G06F,H03K

Claim Text:
1. A timer unit having a first output mode and a second output mode, the timer unit comprising: a first register that stores a first value; a second register that stores a second value; a third register that stores a third value; a first counter that generates a first count signal based on the first value; a second counter that generates a second count signal based on the second value; a third counter that generates a third count signal based on the third value; and an output circuit that outputs a first output signal and a second output signal, wherein, when the timer unit is set in the first output mode, the output circuit outputs the first output signal having a pulse width determined by the first count signal and the second count signal, and outputs the second output signal having a pulse width determined by the first count signal and the third count signal, and wherein, when the timer unit is set in the second output mode, the output circuit outputs the first output signal having a pulse width determined by the first count signal, the second count signal, and the third count signal.