Patent ID: 9401806
Filing Date: 2016-07-26
CPC Classification: H03M,H04L

Claim Text:
1. A data security method by a transmission end using double layer coding in a wireless communication system, the method comprising: acquiring a first bit sequence including data associated with a security key and a second bit sequence including data associated with a payload as input; setting a transmission rate of the first bit sequence less than channel capacity of an intended receiver in order to prevent an instantaneous bit error from being generated in a first block in the intended receiver with respect to the first bit sequence; setting the transmission rate of the first bit sequence greater than channel capacity of an unintended receiver in order to generate at least one instantaneous bit error in a second block in the unintended receiver with respect to the first bit sequence; setting a transmission rate of the second bit sequence less than the channel capacity of the intended receiver in order to prevent the instantaneous bit error from being generated in the first block in the intended receiver with respect to the second bit sequence; setting the transmission rate of the second bit sequence greater than the channel capacity of the unintended receiver in order to generate at least one instantaneous bit error in the second block in the unintended receiver with respect to the second bit sequence; and if at least one instantaneous bit error is generated in the second block in the unintended receiver, setting an average bit error probability of the at least one instantaneous bit error in the second block to 0.5 using a Substitution-Permutation Network (SPN), wherein the first bit sequence is used to decode the second bit sequence, the average bit error probability is calculated by repeatedly performing a step of passing an input bit including at least one instantaneous bit error in the second block through an S-box (substitution-box) and a P-box (permutation-box) included in the SPN preset times, the S-box sets an error probability of an output bit of the S-box to 0.5 by amplifying an error of an input bit including at least one instantaneous bit error in the second block, and the P-box interleaves the output bit of the S-box.