Patent ID: 9391505
Filing Date: 2016-07-12
CPC Classification: H02M,Y02B,Y02P

Claim Text:
1. A power factor correction (PFC) circuit, comprising: a) a rectifier bridge and a PFC converter coupled to an input capacitor; b) a harmonic wave compensation circuit configured to shift a phase of a DC input voltage provided from said rectifier bridge, wherein said harmonic wave compensation circuit comprises a phase of about −45° when a corner frequency is about 50 Hz; c) a PFC control circuit configured to control said PFC converter, wherein said PFC control circuit comprises a voltage sampling circuit coupled to said harmonic wave compensation circuit, and configured to generate a first sampling voltage, and wherein said harmonic wave compensation circuit is configured to control a phase of said first sampling voltage to lag a phase of said DC input voltage by about 45°; d) said PFC control circuit comprising a current sampling circuit configured to sample an output current of said PFC converter, and to generate a second sampling voltage, and an error signal amplifier circuit configured to generate an error voltage signal from said first and second sampling voltages, and a reference voltage that represents an average value of said output current; and e) said PFC control circuit comprising a driving signal generation circuit configured to generate a driving signal coupled to a power switch of said PFC converter based on a comparison of said error voltage signal and a ramp signal.