Patent ID: 9515148
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a plurality of transistor gates comprising one or more inner gates and a plurality of outer gates, the plurality of transistor gates formed at least directly upon a buried-dielectric layer of a semiconductor substrate, the semiconductor substrate comprising a plurality of outer active areas and one or more inner active areas, wherein the plurality of outer active areas are of opposite polarity relative to at least one inner active area; an isolator formed directly upon the one or more inner gates associated with the one or more inner active areas, the isolator comprising a protective barrier portion formed directly upon a dielectric layer formed at least directly upon the one or more inner gates; and a monolithic contact bar electrically connecting the plurality of outer active areas, the monolithic contact bar formed directly upon the protective barrier portion, wherein the isolator electrically insulates the monolithic contact bar from the one or more inner gates.