Patent ID: 9460018
Filing Date: 2016-10-04
CPC Classification: G06F

Claim Text:
1. A method of operation of a processor comprising an instruction cache that comprises extended cache lines where each extended cache line comprises a main cache line portion and an extra data portion, comprising: caching a page-crossing instruction in a single extended cache line of the instruction cache, where a first part of the page-crossing instruction resides in a first page of memory and is cached in the main cache line portion of the extended cache line and a second part of the page-crossing instruction resides in a second page of memory and is cached in the extra data portion of the extended cache line; caching one or more memory page attributes for the main cache line portion of the extended cache line in association with the extended cache line, wherein the one or more memory page attributes for the main cache line portion of the extended cache line comprise one or more execution permissions for the first page of memory, each comprising a plurality of execution permission bits representing whether execution is permitted for a corresponding plurality of processing modes; caching one or more memory page attributes for the extra data portion of the extended cache line in association with the extended cache line, wherein the one or more memory page attributes for the extra data portion of the extended cache line comprise one or more execution permissions for the second page of memory, each comprising a plurality of execution permission bits representing whether execution is permitted for a corresponding plurality of processing modes; fetching the page-crossing instruction from the extended cache line; and detecting that the page-crossing instruction is prohibited from executing based on the one or more memory page attributes for the extra data portion of the extended cache line.