Patent ID: 9519377
Filing Date: 2016-12-13
CPC Classification: G06F,G09G,G11C

Claim Text:
1. A gate driving circuit, comprising a plurality of shift register units connected in cascade, wherein, the gate driving circuit further comprises: at least two delay shift modules, each delay shift module being located between adjacent shift register units, and at least one cascaded shift register unit being further provided between the delay shift modules; and a switch control module respectively connected with the delay shift modules, the switch control module being used for controlling different delay shift modules to be connected between the adjacent shift register units between adjacent frames, and enabling transmission of a gate line drive signal to skip other delay shift modules not connected therein within each frame; the delay shift module being used for suspending a clock signal connected with the delay shift module for a predetermined time when connected between the adjacent shift register units, storing the gate line drive signal from a shift register unit at an adjacent previous stage within the predetermined time for which the clock signal is suspended, and transmitting the gate line drive signal to a shift register unit at an adjacent next stage after the clock signal is restored.