Patent ID: 9281047
Filing Date: 2016-03-08
CPC Classification: G11C

Claim Text:
1. A dynamic random access memory (DRAM) device, comprising: a plurality memory banks each having a plurality of wordlines, each of the plurality of wordlines being connected to a plurality of data store cells that are refreshable in a self-refresh mode; a first storage for storing first bits, each of the first bits corresponding to a respective one of the plurality of memory banks, to indicate whether or not the respective memory bank is to be refreshed in the self-refresh mode, and one or more memory banks of the plurality of memory banks being indicated, by the first bits, to be refreshed in the self-refresh mode; and a second storage for storing second bits, the second bits indicating which subblocks of the one or more memory banks are to be refreshed in the self-refresh mode, and wherein, in the self-refresh mode, the DRAM device performs a self-refresh operation only for the subblocks of the one or more memory banks to be refreshed.