Patent ID: 9286964
Filing Date: 2016-03-15
CPC Classification: G06F,G11C

Claim Text:
1. A memory device comprising: a first bank including a first row and a second row physically adjacent to the first row; a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank; detect logic to configure the memory device in response to an indication that repeated access to the first row exceeds a threshold; row hammer response logic of the memory device, in response to the indication and prior to receipt of an expected targeted refresh command from an associated memory controller, to restrict access to the first bank for access other than a targeted refresh, to prepare for receipt of the targeted refresh command; and access logic to service a memory access command from the memory controller prior to receipt of the targeted refresh command, including the access logic to access the second bank in response to the memory access command, the access logic further to perform the targeted refresh of the second row in response to the targeted refresh command received by the memory device from the memory controller after the memory access command.