Patent ID: 9361954
Filing Date: 2016-06-07
CPC Classification: G11C

Claim Text:
1. A memory device, comprising: a plurality of word lines; an address counting unit configured to generate a counting address; a period control unit configured to store the counting address and enable a frequency control signal when a self refresh mode is enabled, and disable the frequency control signal when the counting address becomes a stored address; a self refresh control unit configured to periodically enable a self refresh signal during the self refresh mode; and a refresh control unit configured to refresh a word line selected by the counting address within a first period in response to a periodic refresh command during an auto refresh mode, refresh a word line selected by the counting address within a second period that is longer than the first period during the self refresh mode, but refresh a word line selected by the counting address within a third period which is shorter than the second period during an enabled section of the frequency control signal.