Patent ID: 9484276
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A semiconductor mounting device, comprising: a first substrate comprising a plurality of insulation layers, a plurality of conductor layers formed on the insulation layers, and a plurality of via conductors connecting the conductor layers; a second substrate comprising a plurality of insulation layers and a plurality of conductor layers formed on the insulation layers of the second substrate; a plurality of first bumps connecting the first substrate and the second substrate and formed on an outermost conductor layer of the first substrate formed on an outermost insulation layer of the first substrate; a plurality of second bumps positioned to mount a semiconductor element to the second substrate and formed on an outermost conductor layer of the second substrate formed on an outermost insulation layer of the second substrate; a solder resist layer formed on the outermost conductor layer and the outermost insulation layer of the first substrate such that the solder resist layer has a plurality of opening portions forming a plurality of exposed portions of the outermost conductor layer of the first substrate; and a plurality of metal layers formed on the exposed portions of the outermost conductor layer of the first substrate, respectively, wherein the second substrate has a thickness which is greater than a thickness of the first substrate.