Patent ID: 9268720
Filing Date: 2016-02-23
CPC Classification: G06F

Claim Text:
1. A method for load balancing in a multiple channel Dynamic Random Access Memory (DRAM) system, the method comprising: interleaving memory data across two or more memory channels; controlling access to the two or more memory channels with memory controllers; coupling bus masters to the memory controllers via an interconnect system; transmitting memory requests from the bus masters to the memory controllers; detecting congestion in a first memory channel in response to a memory request to a first memory controller by tracking a number of memory requests which are denied by the first memory controller, and determining that congestion exists in the first memory channel if a predetermined threshold number of denials of the memory requests by the first memory controller is reached; generating a congestion signal for the first memory channel; transmitting the congestion signal to the bus masters; and rerouting the memory request to a second memory controller in response to the congestion signal, wherein the rerouting comprises remapping a memory address association for the memory request from a first physical address in the first memory channel to a second physical address in a second memory channel coupled to the second memory controller, wherein a second congestion signal for the second memory channel is not asserted.