Patent ID: 9318219
Filing Date: 2016-04-19
CPC Classification: G09G,G11C

Claim Text:
1. A shift register unit, comprising: a first capacitor, a first transistor, a pull-up module, a first pull-down module and a second pull-down module, wherein the first transistor has a first electrode configured to receive a clock signal, a gate connected with one terminal of the first capacitor, the pull-up module and the first pull-down module, and a second electrode connected with the other terminal of the first capacitor; the pull-up module is configured to output a first level signal to the gate of the first transistor when the clock signal is at a second level and a pull-up selection signal is at a first level; and to not output the first level signal to the gate of the first transistor when the clock signal is at the first level and the pull-up selection signal is at the second level, wherein the pull-up selection signal is a signal output from a shift register unit one-stage previous to the shift register unit; the first pull-down module is configured to control the gate of the first transistor to be connected to a second level signal input terminal when the clock signal is at the first level and a first pull-down selection signal is at the first level, wherein the first pull-down selection signal is a signal output from a shift register unit two-stage subsequent to the shift register unit; the first transistor is configured to output the received clock signal from the second electrode of the first transistor when a signal at the gate of the first transistor is at the first level; and to not output the received clock signal from the second electrode of the first transistor when the signal at the gate of the first transistor is at the second level; and the second pull-down module is connected with the gate and the second electrode of the first transistor and is configured to control the gate and the second electrode of the first transistor to be connected with the second level signal input terminal when the signal at the gate of the first transistor is at the second level, the clock signal is at the first level and a clock blocking signal is at the second level; to control the gate and the second electrode of the first transistor to be disconnected from the second level signal input terminal when the signal at the gate of the first transistor is at the second level, the clock signal is at the second level and a clock blocking signal is at the first level; and to control the gate and the second electrode of the first transistor to be disconnected from the second level signal input terminal when the signal at the gate of the first transistor is at the first level.