Patent ID: 9355061
Filing Date: 2016-05-31
CPC Classification: G06F

Claim Text:
1. A data processing apparatus comprising: a vector register store configured to store vector operands; processing circuitry configured to perform operations on vector operands retrieved from said vector register store; control circuitry configured to control the processing circuitry to perform the operations required by one or more instructions, said one or more instructions including a vector scan instruction specifying a vector operand comprising N vector elements and defining a scan operation to be performed on a sequence of vector elements within the vector operand; the control circuitry being responsive to the vector scan instruction to partition the N vector elements of the specified vector operand into P groups of adjacent vector elements, where P is between 2 and N/2, and to control the processing circuitry to perform a partitioned scan operation yielding the same result as the defined scan operation, the processing circuitry being configured to perform the partitioned scan operation by performing separate scan operations on those vector elements of the sequence contained within each group to produce intermediate results for each group, and to perform a computation operation to combine the intermediate results into a final result vector operand containing a sequence of result vector elements.