Patent ID: 9425150
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A method comprising: providing a bonded structure having a first semiconductor chip having a first substrate bonded to a second semiconductor chip having a second substrate, the first substrate having one or more first dielectric layers thereon and a first pad in the one or more first dielectric layers, the second substrate having one or more second dielectric layers thereon and a second pad in the one or more second dielectric layers, the first substrate being bonded to the second substrate such that the first dielectric layers face the second dielectric layers, wherein the first semiconductor chip is a first technology node chip and the second semiconductor chip is a second technology node chip, the first technology node chip being a different technology node than the second technology node chip; forming a first opening extending through the first substrate; forming a second opening extending from the first opening to the first pad; forming a third opening extending from the first pad to the second pad; and simultaneously forming a first multi-via interconnect structure and a redistribution layer with a conductive material, wherein the first multi-via interconnect structure is formed in the first opening, the second opening, and the third opening, wherein the redistribution layer provides an external electrical connection to the first multi-via interconnect structure.