Patent ID: 9269767
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate of a first conductive type having first and second sides arranged along a first direction, and third and fourth sides arranged along a second direction which is perpendicular to the first direction; a drift region of the first conductive type formed on the semiconductor substrate; a cell region arranged in the drift region; a plurality of power MOSFETs formed in the cell region; a first peripheral region arranged in the drift region and arranged between the cell region and the first side; a second peripheral region arranged in the drift region and arranged between the cell region and the second side; a third peripheral region arranged in the drift region and arranged between the cell region and the third side; and a fourth peripheral region arranged in the drift region and arranged between the cell region and the fourth side, wherein the first peripheral region has a plurality of first columns of the second conductive type opposite to the first conductive type which are formed in the drift region and which extend along the first direction, wherein the second peripheral region has a plurality of second columns of the second conductive type which are formed in the drift region and which extend along the first direction, wherein the third peripheral region has a plurality of third columns of the second conductive type which are formed in the drift region and which extend along the second direction, wherein the fourth peripheral region has a plurality of fourth columns of the second conductive type which are formed in the drift region and which extend along the second direction, wherein the cell region has a plurality of fifth columns of the second conductive type which are formed in the drift region and which extend along the first direction, wherein a resurf region of the second conductive type is formed in the drift region and is arranged at upper portions of the first, second, third and fourth columns, wherein a plurality of gate electrodes of the power MOSFETs are formed over the drift region of the cell region, wherein a plurality of well regions of the second conductive type are formed in the drift region of the cell region, are arranged at upper portions of the fifth columns and have higher impurity concentration than the resurf region, wherein a plurality of source regions of the power MOSFETs of the first conductive type are formed in the well regions, wherein, in the first direction, the cell region, the first peripheral region and the second peripheral region are arranged between the third peripheral region and the fourth peripheral region, wherein the third column and the fourth column extend along the second direction in order to abut the cell region, the first peripheral region and the second peripheral region in the first direction, wherein a plurality of impurity regions of the second conductive type having higher impurity concentration than the resurf region are formed in the first, second, third and fourth peripheral regions in order to contact with the resurf region and each of the first, second, third and fourth columns, wherein the impurity region formed in the first peripheral region extends along the first column, wherein the impurity region formed in the second peripheral region extends along the second column, wherein the impurity region formed in the third peripheral region extends along the third column, and wherein the impurity region formed in the fourth peripheral region extends along the fourth column.