Patent ID: 9524879
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: forming a transistor including first and second source/drain regions and a bit line connected to the first source/drain region of the transistor on a substrate; forming an interlayer insulating layer covering the transistor and the bit line; forming first and second contact holes exposing the second source/drain region of the transistor on both side surfaces of the bit line so as to penetrate the interlayer insulating layer; forming a sacrificial layer on the interlayer insulating layer and filling the first and second contact holes; forming a first trench separating the sacrificial layer filling the first contact hole and the sacrificial layer filling the second contact hole from each other by removing at least a part of the sacrificial layer; forming a spacer filling the first trench; forming a second trench on the first contact hole, and overlapping a part of the first contact hole and a part of the interlayer insulating layer on a side surface of the first contact hole, by removal of a first portion of a remainder of the sacrificial layer; forming a third trench on the second contact hole, and overlapping a part of the second contact hole and a part of the interlayer insulating layer on a side surface of the second contact hole, by removal of a second portion of the remainder of the sacrificial layer; forming a contact plug pattern filling the first and second contact holes; and forming a metal pattern filling the second and third trenches.