Patent ID: 9263342
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method of semiconductor fabrication, comprising: providing a substrate having a semiconductor fin; forming a gate structure over the semiconductor fin; forming a recess in the semiconductor fin adjacent the gate structure, wherein the recess is defined by a first sidewall, an opposing second sidewall and a bottom surface extending from the first sidewall to the opposing second sidewall, and wherein each of the first sidewall, the opposing second sidewall, and the bottom surface are interfaces with the semiconductor fin; altering the first sidewall of the recess and the opposing second sidewall of the recess by forming a dielectric offset liner layer on the first and opposing second sidewalls of the recess; and growing a first epitaxial region in the recess, wherein the first epitaxial region interfaces a first surface and an opposing second surface of the dielectric offset liner layer and wherein the first epitaxial region is a strained epitaxial region, and wherein the first epitaxial region extends to a first height and the dielectric offset liner layer extends to a second height, the second height being greater than the first height such that an angle defined by an intersection between a top surface of the first epitaxial region and the first surface of the dielectric offset liner layer is less than 90 degrees; and after the growing of the first epitaxial region, removing the dielectric offset liner layer including the first surface and the opposing second surface of the dielectric offset liner layer; and growing a second epitaxial region on and over the first epitaxial region after removing the dielectric offset liner layer.