Patent ID: 9472257
Filing Date: 2016-10-18
CPC Classification: G06F,G11C,H01L

Claim Text:
1. An apparatus, comprising: a hybrid cache architecture having: wherein the magnetoresistive random-access memory bit cell array is uniform such that a number of magnetoresistive random-access memory bit cells in each column of the first plurality of magnetoresistive random-access memory bit cells is same as a number of magnetoresistive random-access memory bit cells in each column of the second plurality of magnetoresistive random-access memory bit cells, wherein the differential sense amplifier is configured to output a single data bit by sensing currents from at least two magnetoresistive random-access bit cells, wherein the single-ended sense amplifier is configured to output a single data bit by sensing a current from a single magnetoresistive random-access bit cell, wherein at least one magnetoresistive random-access memory bit cell in the first plurality of magnetoresistive random-access memory bit cells is coupled to the single-ended sense amplifier, and wherein at least two magnetoresistive random-access memory bit cells in the second plurality of magnetoresistive random-access memory bit cells are coupled to the differential sense amplifier.