Patent ID: 9520341
Filing Date: 2016-12-13
CPC Classification: H01L

Claim Text:
1. A semiconductor package comprising: a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain; a sync transistor disposed on said leadframe and including a bottom surface having a sync drain and a top surface having a sync source and a sync gate; a first conductive clip electrically coupling said control drain to a first pad of said leadframe, said control source being electrically coupled to said sync drain by a common region of said leadframe; said control gate electrically coupled to a second pad of said leadframe; a driver integrated circuit (IC) disposed on a third pad of said leadframe, said third pad isolated from said common region; a second conductive clip electrically coupling said sync source to a fourth pad of said lead frame, wherein said first pad and said fourth pad are disposed along a common peripheral edge of said leadframe such that said control transistor and said sync transistor are not situated between said first pad and said fourth pad.