Patent ID: 9390975
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit comprising a tunnel transistor, the method comprising: forming an auxiliary layer over a substrate; forming at least one auxiliary region by patterning the auxiliary layer and removing material of the auxiliary layer; forming a first spacer element in a region in which material of the auxiliary layer has been removed; doping a first connection region having a first doping type of a transistor, the first spacer element and the auxiliary region serving as a mask; covering the first connection region with a covering material; removing material of the auxiliary region; forming a second spacer element in a region in which material of the auxiliary region has been removed; doping a second connection region having a second doping type of the transistor, the first doping being opposite the second doping type, the second spacer element and the covering material serving as a mask; and forming an extension region in only one of the first connection region or the second connection region but not the other one of the first connection region or the second connection region.