Patent ID: 9490810
Filing Date: 2016-11-08
CPC Classification: H03F,H03K

Claim Text:
1. An integrated circuit comprising: a first input terminal configured to receive a first input signal generated with reference to an external ground reference that is external to the integrated circuit, the first input signal comprising a first noise component; a second input terminal configured to receive a second input signal generated with reference to the external ground reference, the second input signal comprising a second noise component; a differential circuit in communication with the first input terminal and the second input terminal, the differential circuit configured to: a ground pin directly connected to the external ground reference and unshared with one or more other ground pins of the integrated circuit, the ground pin sharing a same ground reference voltage as the external ground reference and the one or more other ground pins used for generation of a chip ground reference different than the external ground reference; and a reference circuit configured to: