Patent ID: 9396796
Filing Date: 2016-07-19
CPC Classification: G11C

Claim Text:
1. A memory system comprising: a non-volatile memory; and a controller configured to control an operation of the non-volatile memory, wherein the non-volatile memory comprises: a memory cell array comprising a target page; a first page buffer configured to store first data read from the target page, which is selected according to a first read command output from the controller, using a first read voltage level changed according to a first read voltage level change command output from the controller; a second page buffer configured to store second data read from the target page, which is selected according to a second read command output from the controller, using a second read voltage level changed according to a second read voltage level change command output from the controller; and a third page buffer configured to generate data which is the same as bit-wise logical operation data with respect to the first data and second data by changing third data stored therein using at least part of the first data transmitted from the first page buffer and at least part of the second data transmitted from the second page buffer according to a command output from the controller.