Patent ID: 9508274
Filing Date: 2016-11-29
CPC Classification: G09G,H01L

Claim Text:
1. A thin film transistor substrate, comprising: a plurality of pixels disposed in a display area of the thin film transistor substrate, the plurality of pixels being connected to a plurality of gate lines and a plurality of data lines; a plurality of gate pad parts connected to first ends of the plurality of gate lines; a plurality of first test transistors, each of the plurality of first test transistors being connected to a second end of a corresponding gate line of the plurality of gate lines; a plurality of data pad parts connected to first ends of the plurality of data lines; and a plurality of second test transistors, each of the plurality of second test transistors being connected to a second end of a corresponding data line of the plurality of data lines, wherein the plurality of gate pad parts, the plurality of data pad parts, the plurality of first test transistors, and the plurality of second test transistors are disposed in a non-display area of the thin film transistor substrate, and wherein the plurality of first test transistors is configured to be switched to receive a first inspection signal and the plurality of second test transistors is configured to be switched to receive a second inspection signal.