Patent ID: 9416004
Filing Date: 2016-08-16
CPC Classification: B81B,B81C,H01L

Claim Text:
1. A semiconductor fabrication method, comprising: providing a semiconductor substrate comprising a first electrode layer therein, wherein the first electrode layer has a top surface coplanar with a top surface of the semiconductor substrate; forming a sacrificial layer on the semiconductor substrate and the first electrode layer; forming a first mask layer on the sacrificial layer, wherein the first mask layer is made of a conductive material; etching the first mask layer and the sacrificial layer, by a first etching process, using a patterned layer as an etch mask to etch the first mask layer until a surface of the sacrificial layer is exposed, and a second etching process following the first etching process, using the first mask layer as an etch mask to etch the sacrificial layer, until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer; performing a cleaning process to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings; and forming conductive plugs in the openings after the cleaning process.