Patent ID: 9489989
Filing Date: 2016-11-08
CPC Classification: G11C

Claim Text:
1. A voltage regulator comprising: an amplifier configured to output a control signal based on a comparison between a reference voltage and an output voltage; an output end electrically coupled to a first memory array, the output end being configured to provide the output voltage to the first memory array; a feedback loop coupling the output end to the amplifier, the output voltage being provided to the amplifier by way of the feedback loop; an output stage electrically coupled between the amplifier and the output end, the output stage comprising at least one transistor having a bulk and a drain; and at least one back-bias circuit electrically coupled with the bulk of the at least one transistor, the at least one back-bias circuit being configured to provide a bulk voltage such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of the first memory array, wherein the first memory array is coupled to a second memory array by a word line, the second memory array is coupled to a corresponding voltage regulator through a corresponding output end of the corresponding voltage regulator, the voltage regulator is directly electrically coupled with the corresponding voltage regulator, a contention current flows between the voltage regulator and the corresponding voltage regulator, and the back-bias circuit is configured to reduce the contention current during the standby mode by way of the reverse biasing.