Patent ID: 9344113
Filing Date: 2016-05-17
CPC Classification: G06F,H03M

Claim Text:
1. A data compression architecture, comprising: means for receiving input data characters; means for receiving a data flush enable input signal, wherein said data flush input signal is asserted in response to said means for receiving input data characters beginning to receive said input data characters from a new source; means for storing a plurality of previously received data characters, wherein the plurality of previously received data characters are cleared within a clock cycle in response to the data flush enable input signal; means for comparing each received input data character with said plurality of stored data characters; means for detecting a match in response to determining that a sequence of two or more of the received input data characters is equal to a sequence of the stored data characters; means for determining that a match criterion is met; and means for supplying a match output in response to said detecting a match and in response to said determining that a match criterion is met.