Patent ID: 9431437
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a display panel comprising: sequentially stacking a first metal layer, a first insulating layer, an amorphous silicon layer, an n+ amorphous silicon layer, and a first photoresist layer, on a substrate comprising a transistor area and a line area; patterning the first photoresist layer using a first mask comprising a halftone pattern in the transistor area and the line area, to form a first photoresist pattern; substantially simultaneously removing portions of the stack of the amorphous silicon layer, the n+ amorphous silicon layer, the first insulating layer and the first metal layers, by exposing the portions through the first photoresist pattern, to form an active layer and a gate insulating layer each defining a protruding portion thereof which extends further than the gate electrode and the gate line and to form a gate electrode extended from a gate line; removing the protruding portion of the active layer and the gate insulating layer, to form respective edges of the gate electrode and the gate line protruding further than edges of the active layer and the gate insulating layer on the gate electrode and the gate line; forming a planarization organic layer comprising an organic material, on the active layer and the substrate, after the active layer is formed; removing the planarization organic layer overlapping the active layer, to form a planarization layer; forming a second metal layer on the planarization layer and the active layer; patterning the second metal layer using a second mask to form a source electrode, a drain electrode and a data line; forming a protective layer on the planarization layer to cover the source electrode, the drain electrode and the data line; patterning the protective layer using at least a third mask, a contact hole being formed through the protective layer to expose the drain electrode; forming a transparent electrode layer on the protective layer; and patterning the transparent electrode layer using a fourth mask to form a pixel electrode electrically connected to the drain electrode through the contact hole.