Patent ID: 9401376
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A thin film transistor, comprising: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer, the semiconductor layer comprising a source region, a drain region and a channel region; a first gate insulating layer configured to cover the semiconductor layer, the first gate insulating layer comprising a first width; a second gate insulating layer foot formed on the first gate insulating layer, the second gate insulating layer foot being made by different material with the first gate insulating layer and comprising a second width, the width of the second gate insulating layer foot being smaller than the width of the first gate insulating layer; and a gate electrode formed on the second gate insulating layer foot; wherein a part of the first gate insulating layer on the semiconductor layer has a flat upper surface, and wherein the semiconductor layer further comprises two second lightly doped drain regions respectively adjacent to the source region and the drain region and two first lightly doped drain regions respectively adjacent to the two second lightly doped drain regions, and the second lightly doped drain regions have a doping concentration lower than that of the first lightly doped drain regions.