Patent ID: 9411752
Filing Date: 2016-08-09
CPC Classification: G06F,H03H,H03M

Claim Text:
1. A conversion device comprising: an A/D conversion unit that sequentially converts an analog value into a digital value for each A/D conversion period and outputs the digital value; an input-data storage unit that arranges a plurality of digital values that are outputted most lately in order of delay amount and stores therein the digital values so that each of the digital values is positioned at a fixed address according to a delay amount; a filter-characteristic storage unit that stores therein setting information for specifying a filter characteristic; a coefficient-data storage unit that stores therein a filter coefficient; a receiving unit that receives an execution request; a coefficient-data computation unit that, when the receiving unit receives the execution request, reads setting information out from the filter-characteristic storage unit to calculate an order and filter coefficients number of which is equal to the order based on the read setting information, arranges the calculated filter coefficients in order of delay amount, respectively and stores the filter coefficients in the coefficient-data storage unit so that each of the filter coefficients is positioned at a fixed address according to the corresponding delay amount; and a digital-filter computation unit that performs for each A/D conversion period an operation of reading digital values number of which is equal to the calculated order from the input-data storage unit and filter coefficients the number of which is equal to the calculated order from the coefficient-data storage unit based on addresses where the values and coefficients are stored for each delay amount, respectively, performing a filter computation based on the read values for each delay amount, and outputting a computation result thereof.