Patent ID: 9524899
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a semiconductor device comprising: forming element isolation regions demarcating element regions in a semiconductor substrate; introducing a first impurity of a first conductivity type into a first region of the semiconductor substrate to form a first well of the first conductivity type and introducing the first impurity into a second region of the semiconductor substrate to form a second well of the first conductivity type; introducing a second impurity of a second conductivity type, which is a conductivity type opposite to the first conductivity type, into a third region of the semiconductor substrate to form a third well of the second conductivity type and introducing the second impurity into a fourth region of the semiconductor substrate between the first well and the second well to form a first separation well of the second conductivity type; introducing a third impurity of the second conductivity type into the fourth region without introducing the third impurity into the third region; and forming an embedded well of the second conductivity type, which partially overlaps with the first well, the second well and the first separation well, by introducing the second impurity of the second conductivity type under the first well, the second well and the first separation well.