Patent ID: 9240460
Filing Date: 2016-01-19
CPC Classification: H01J,H01L

Claim Text:
1. A method of forming a semiconductor device, the method comprising: forming a gate structure on a fin active region that is on a substrate; forming preliminary trenches by anisotropically etching the fin active region; forming etching selection regions in portions of the fin active region that are exposed by the preliminary trenches, wherein the etching selection regions comprise a first impurity concentration that is higher than a second impurity concentration in the fin active region, and wherein forming the etching selection regions comprises forming a horizontal width of portions of the etching selection regions defining sidewalls of the preliminary trenches that is greater than a vertical thickness of portions of the etching selection regions that are perpendicular to the horizontal width; forming trenches in the fin active region adjacent opposing sides of the gate structure, by removing the etching selection regions; and forming a stressor in the trenches.