Patent ID: 9530474
Filing Date: 2016-12-27
CPC Classification: G11C

Claim Text:
1. A semiconductor integrated circuit comprising: a memory control apparatus configured to receive a data signal, a command signal, and an address signal from outside and control the data signal to be inputted or outputted; and a semiconductor memory apparatus configured to receive the data signal, the command signal, and the address signal from the memory control apparatus, shift the command signal and the address signal to have a predetermined margin in synchronization with the same clock, generate a plurality of control signals using the shifted command signal and address signal, and input the data signal to a corresponding bank of a plurality of banks according to control of the generated control signals, wherein the semiconductor memory apparatus includes: a command address signal shifter configured to shift the command signal and the address signal to have the predetermined margin between the command signal and the address signal, and to output a plurality of shifting signals; a data enable signal generator configured to generate a data enable signal having a predetermined margin, using the plurality of shifting signals; a latch signal generator configured to generate a latch signal for latching data signals inputted to a first bank group and a second bank group, respectively, using the plurality of shifting signals; and an align signal generator configured to generate an align signal for aligning the data signals inputted to the first and second bank groups, using the plurality of shifting signals.