Patent ID: 9437423
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method for fabricating an inter dielectric layer in a semiconductor device, comprising: forming a bit line stack over a semiconductor substrate, the bit line stack comprising a barrier metal pattern, a conductive pattern, and a hard mask pattern, the hard mask pattern having two sides, wherein the barrier metal pattern, the conductive pattern and the hard mask pattern are sequentially stacked; forming a bit line spacer on both sides of the bit line stack to expose a top surface of the hard mask pattern, the bit line spacer covers entirely both sides of the bit line stack; supplying a high density plasma (HDP) deposition source to the bit line stack to form a primary liner HDP oxide layer on the bit line spacer while maintaining a bottom bias of an HDP chamber at less than 500 W during formation of the primary liner HDP oxide layer, wherein the primary liner HDP oxide layer covers both sides of the bit line spacer and a top surface of the hard mask pattern; etching the primary liner HDP oxide layer to a predetermined thickness to form a secondary liner HDP oxide layer, wherein the secondary liner HDP entirely covers both sides of the bit line spacer while exposing the top surface of the hard mask pattern; filling an area defined by adjacent bit line stacks where the secondary liner HDP oxide layer is formed with a flowable spin on dielectric (SOD) layer such that the SOD layer contacts the secondary liner HDP oxide layer; and, curing the flowable SOD layer to form an oxide layer.