Patent ID: 9246112
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor structure, the method comprising: depositing a first dielectric material on a substrate; forming a first opening in the first dielectric material; forming a bottom gate comprising filling the first opening in the first dielectric material with a first conductive material; depositing a second dielectric material on the first dielectric material and the first conductive material; forming a trench in the second dielectric material down to the first conductive material, wherein a sidewall of the trench contacts a top surface of the first conductive material; depositing a second conductive material on the sidewall of the trench to form an electrical connection between the first conductive material and the second conductive material; depositing a third dielectric material in the trench and on the second conductive material; removing an excess portion of the third dielectric material and an excess portion of the second conductive material not in the trench; depositing a gate dielectric layer on the second conductive material, the second dielectric material and the third dielectric material; forming a channel layer on the gate dielectric layer; and depositing a third conductive material on the channel layer and portions of the gate dielectric layer to form a source terminal and a drain terminal.