Patent ID: 9337043
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method for forming a metal gate transistor, comprising: providing a substrate having a top surface and a back surface; forming a dummy gate on the top surface of the substrate; forming a first interlayer dielectric layer on the top surface of substrate; planarizing the first interlayer dielectric layer to expose the dummy gate; removing the dummy gate to form a trench; forming a metal gate stack to cover the first interlayer dielectric layer and to fill the trench; planarizing the metal gate stack to remove a portion of the metal gate stack from the first interlayer dielectric layer to form a metal gate electrode in the trench and to leave a remaining edge portion of the metal gate stack over an annular region of the substrate; and performing an edge cleaning process on the top surface of the substrate to remove the remaining edge portion of the metal gate stack from the annular region of the substrate, wherein the performing of the edge cleaning process includes: