Patent ID: 9419014
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. An integrated circuit comprising: a plurality of N wells on a P substrate; a plurality of tap columns located across the plurality of N wells on the P substrate; a plurality of standard cells between the plurality of tap columns; a plurality of tap cells disposed consecutively in the plurality of tap columns; each tap cell comprising a first tap active and a second tap active, wherein the first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell, and wherein, the first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column; and two end tap cells, one located at a top end of the tap column and the other at a bottom end of the tap column, wherein the end tap cells are wider than the tap cells to accommodate logic blocks disposed adjacent to the plurality of tap columns and to meet the minimum area design rule associated with the integrated circuit.