Patent ID: 9349785
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, the method comprising: providing a semiconductor substrate with a plurality of first portions, a first resist region and a second resist region, wherein the first resist region is disposed between two adjacent first portions, and the second resist region is disposed between another two adjacent first portions; forming a plurality of trench isolations in the first portions of the semiconductor substrate respectively; forming a first sacrificial layer on the first resist region and a second sacrificial layer on the second resist region; implanting doping ions into the first resist region and the second resist region of the semiconductor substrate, wherein a doping type of the first resist regions is the same as a doping type of the second resist regions; removing the second sacrificial layer from the second resist region to expose the second resist region with the first resist region still covered by the first sacrificial layer; and annealing the semiconductor substrate to homogenize the doping ions in the first resist region and the second resist region, and to diffuse a portion of the doping ions out of the second resist region, thereby having the second resist region with a remaining doping concentration, wherein a resistance of the second resist region is greater than that of the first resist region.