Patent ID: 9449651
Filing Date: 2016-09-20
CPC Classification: G06F,G11C

Claim Text:
1. A co-processing and input/output (CPIO) module with a load-reduction dual in-line memory module (LRDIMM) interface, the CPIO module comprising: a CPIO device; a CPIO variable timing control circuit; and a load-reduction dual in-line memory module (LRDIMM) interface configured to interface with a memory bus, the LRDIMM interface comprising data buffers to bridge data between the CPIO variable timing control circuit and the memory bus, wherein the CPIO variable timing control circuit is operatively coupled between the LRDIMM interface and the CPIO device, and is configured to provide variable timing control to signaling between the CPIO variable timing control circuit and the LRDIMM interface to at least partially offset latency between the memory bus and the CPIO variable timing control circuit so that the CPIO module is timing compatible with a registered dual in-line memory module (RDIMM).