Patent ID: 9368578
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method, comprising: obtaining a structure comprised of a first layer of a first semiconductor material, a layer of insulating material positioned on and in contact with an upper surface of said first layer, at least one strain relief buffer layer positioned above an upper surface of said layer of insulating material, a second layer of a second semiconductor material positioned on and in contact with said at least one strain relief buffer layer, wherein an upper surface of said at least one strain relief buffer layer contacts a lower surface of said second layer; forming a patterned masking layer above said second layer; performing at least one etching process to form an opening in said second layer to thereby expose a portion of said strain relief buffer layer at a bottom of said opening, said opening having sidewalls; forming an insulating sidewall spacer on said sidewalls of said opening; after forming said sidewall spacer, forming a third semiconductor material in said opening on said exposed portion of said strain relief buffer layer so as to overfill said opening with said third semiconductor material, wherein said first, second and third semiconductor materials are different semiconductor materials; after forming said third semiconductor material, performing at least one chemical mechanical planarization process to remove said patterned masking layer and thereby produce a substantially planar surface that includes planarized and substantially coplanar upper surfaces of said second layer, said third semiconductor material and said sidewall spacer; forming a first transistor device in and above said second layer, wherein forming said first transistor device comprises forming a gate insulation layer for said first transistor device on and in contact with said planarized upper surface of said second layer; and forming a second transistor device in and above said third semiconductor material, wherein said second transistor device is a type that is opposite said first transistor device and wherein forming said second transistor device comprises forming a gate insulation layer for said second transistor device on and in contact with said planarized upper surface of said third semiconductor material.