Patent ID: 9449880
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A method of semiconductor device fabrication, comprising: forming a plurality of first spacers over a substrate, wherein each first spacer of the plurality of first spacers has a first spacer width; depositing a second spacer of a plurality of second spacers on sidewalls of each first spacer of the plurality of first spacers, wherein each second spacer of the plurality of second spacers has a second spacer width; forming a third spacer of a plurality of third spacers on each opposing sidewall of each second spacer of the plurality of second spacers, wherein each third spacer of the plurality of third spacers has a third spacer width; and performing a first etch process on the substrate to form fin regions within the substrate, wherein the plurality of third spacers mask portions of the substrate during the first etch process, and wherein a fin region width is substantially equal to about the third spacer width.