Patent ID: 9342122
Filing Date: 2016-05-17
CPC Classification: G06F,Y02D

Claim Text:
1. A processor comprising: a first domain having a first compute engine; a second domain having a second compute engine, the first and second compute engines asymmetrical, each of the first and second domains to operate at an independent voltage and frequency; a first domain counter and a second domain counter, wherein one of the first and second domain counters is to be updated based on whether a frequency of the first domain is substantially around a target frequency for the first domain; a first logic to update a power bias value stored in a configuration register, the power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a measure of a busyness of the second domain, the power bias value corresponding to a portion of a power budget for the processor to be allocated to one of the first and second domains, wherein the first logic is to dynamically update the power bias value based at least in part on one of the first domain counter and the second domain counter; and a second logic to dynamically allocate at least a portion of the power budget between the first and second domains based at least in part on the power bias value.