Patent ID: 9349437
Filing Date: 2016-05-24
CPC Classification: G11C

Claim Text:
1. A memory cell having integrated read and write assist functionality, the memory cell comprising: a storage element for storing a logical state of the memory cell, the storage element comprising a pair of cross-coupled inverters configured as a latch; a first switching circuit configured to selectively couple a first internal storage node of the storage element with a first bit line as a function of a first plurality of control signals; a second switching circuit configured to selectively couple a second internal storage node of the storage element with a second bit line as a function of a second plurality of control signals; wherein during a read operation of the memory cell, at least one of the first and second switching circuits is configured to increase a switching threshold of at least one inverter of the pair of inverters in the storage element, and during a write operation of the memory cell, at least a given one of the first and second switching circuits is configured such that ground bounce associated with the given one of the first and second switching circuits assists in writing a logical state of the memory cell, wherein the ground bounce occurs as a result of a bit line discharging and potentially flipping a logic state of the one of the first and second internal storage nodes.