Patent ID: 9502418
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a first gate stack and a second gate stack; forming a spacer material over the first gate stack and the second gate stack; forming source and drain regions abutting the spacer material of the first gate stack; creating a space between the source and drain regions and the spacer material of the first gate stack by a thinning process of the spacer material; forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over the spacer material on sidewalls of the first gate stack and the second gate stack and within the space formed between the spacer material and source and drain regions of the first gate stack, wherein a portion of the spacer material formed over the second gate stack is not covered by the liner material; and forming source and drain regions directly abutting sidewalls of the liner material of the second gate stack and the portion of the spacer material formed over the second gate stack which is not covered by the liner material.