Patent ID: 9515019
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate having a main surface which has an edge; a plurality of output circuits disposed in a row along the edge on the main surface; each of the plurality of output circuits including a first MISFET and a second MISFET, wherein a shortest distance between the first MISFET and the edge of the main surface is smaller than that between the second MISFET and the edge of the main surface; a first bonding pad disposed over the main surface, the first bonding pad being overlapped with the first MISFET in a first output circuit of the plurality of output circuits in plan view; a first wiring disposed under the first bonding pad; a first conductor plug disposed between the first bonding pad and the first wiring, the first conductor plug connecting the first bonding pad and the first wiring, the first bonding pad and the first wiring being electrically connected to one of source and drain terminals of the first MISFETs and one of source and drain terminals of the second MISFETs in the first output circuit; a second bonding pad disposed over the main surface, the second bonding pad being overlapped with the second MISFET in a second output circuit of the plurality of output circuits in plan view, the first output circuit and the second output circuit being disposed side by side; a second wiring disposed under the second bonding pad, and a second conductor plug disposed between the second bonding pad and the second wiring, the second conductor plug connecting the second bonding pad and the second wiring, the second bonding pad and the second wiring being electrically connected to one of source and drain terminals of the first MISFETs and one of source and drain terminals of the second MISFETs in the second output circuit; a first power supply wiring extending along the edge of the main surface, and disposed across at least the first MISFET of the first output circuit and the first MISFET of the second output circuit; and a second power supply wiring extending along the edge of the main surface, and disposed across at least the second MISFET of the first output circuit and the second MISFET of the second output circuit, wherein a shortest distance between the first bonding pad and the edge of the main surface is smaller than that between the second bonding pad and the edge of the main surface, wherein the first conductor plug is located between the first MISFET and the second MISFET in the first output circuit in plan view, and wherein the second conductor plug is located between the first MISFET and the second MISFET in the second output circuit in plan view, and wherein the first power supply wiring is electrically connected to one of the first and the second bonding pad through a corresponding one of the first and the second wiring.