Patent ID: 9431823
Filing Date: 2016-08-30
CPC Classification: H01L,H02H

Claim Text:
1. An ESD protection circuit comprising: an overvoltage detection circuit that detects application of an overvoltage under ESD events to a power supply node and outputs a detection signal, wherein the overvoltage under ESD events is higher than a power supply voltage under normal operation; a clamp circuit that, in response to the detection signal, connects the power supply node to a ground node to clamp a voltage of the power supply node, when the application of the overvoltage to the power supply node is detected; a voltage regulation circuit that drops the voltage of the power supply node to generate a regulated voltage, wherein, at the regulated voltage, the overvoltage detection circuit is not activated when the power supply voltage under normal operation is supplied to the power supply node at Power-On, and wherein the overvoltage detection circuit is activated when the overvoltage under ESD events is applied to the power supply node, the regulated voltage being supplied as a supply voltage for the overvoltage detection circuit; and a voltage compensation circuit that compensates for a voltage of the detection signal which is dropped since the overvoltage detection circuit operates on the regulated voltage, so that the voltage of the detection signal becomes equal to the overvoltage, when the overvoltage is applied to the power supply node.