Patent ID: 9281825
Filing Date: 2016-03-08
CPC Classification: H03L

Claim Text:
1. An integrated circuit for frequency synthesis, said integrated circuit comprising: a gapper configured to generate a first gapped signal based on an input signal, said gapper comprising a gapping unit configured to generate said first gapped signal that comprises an equivalent of Q pulses responsive to P pulses of said input signal in accordance with a plurality of gapping control signals, wherein P is greater than or equal to Q; a frequency divider coupled with said gapper and configured to receive said first gapped signal and generate a second gapped signal; and a phase locked loop (PLL) configured to receive said second gapped signal and generate an output signal, wherein, if a frequency ratio of said input signal to said output signal is less than 1, said gapper is configured to incorporate a factor that is greater than 1 from said frequency divider, wherein said gapper comprises a multi-modulus divider configured to divide said input signal with a sequence of divide ratios, wherein an average of said divide ratios is approximately equal to P/Q, and wherein said sequence of divide ratio are converted from said plurality of gapping control signals.