Patent ID: 9318604
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a plurality of first gate electrodes buried in a semiconductor substrate including an active region and a device isolation film; a plurality of junction regions, each of the plurality of junction regions disposed in a portion of the active region between two adjacent first gate electrodes, the plurality of junction regions including storage node junction regions and a bit line junction region disposed between the storage node junction regions; a plurality of storage node contact plugs disposed over and coupled to the storage node junction regions, respectively; a plurality of storage nodes coupled to and disposed over the plurality of storage node contact plugs, respectively; and a second gate electrode disposed over a sidewall of a corresponding one of the plurality of storage node contact plugs, wherein a vertical transistor includes the second gate electrode and the corresponding one of the plurality of storage node contact plugs and stores charges leaked from a corresponding one of the plurality of storage nodes.