Patent ID: 9305847
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: forming a substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type, wherein the first conductivity type and the second conductivity type are complementary; forming an inner-layer dielectric layer on the substrate, wherein the inner-layer dielectric layer comprises a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor; forming a work function metal layer on the inner-layer dielectric layer; coating an anti-reflective layer on the work function metal layer to fill the first gate trench, the second gate trench and the third gate trench; etching portions of the anti-reflective layer that are respectively filled in the first gate trench, the second gate trench and the third gate trench to expose portions of the work function metal layer and to leave a first capping portion and a second capping portion of the anti-reflective layer with different levels respectively in the first gate trench and the third gate trench; and removing the exposed portions of the work function metal layer to form a U-shaped work function metal layer in the third gate trench.