Patent ID: 9449904
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate having a main surface and a back surface opposite each other; a MISFET formed in the semiconductor substrate and having a gate, a source region, and a drain region, the gate being comprising a first conductor; a gate electrode arranged over the main surface of the semiconductor substrate and coupled to the gate, the gate electrode comprising a second conductor having a resistivity lower than the first conductor, and the gate electrode having a gate finger portion; a source electrode arranged over the main surface of the semiconductor substrate and coupled to the source region, the source electrode comprising the second conductor, the gate electrode and the source electrode being formed in a same conductive layer, the source electrode having a plurality of regions, and the gate finger portion of the gate electrode being located between two adjacent regions of the plurality of regions of the source electrode; a protection film arranged over the gate electrode and the source electrode, the protection film having a gate opening for exposing a part of the gate electrode and a plurality of source openings for exposing parts of the source electrode; a drain electrode arranged over the back surface of the semiconductor substrate and coupled to the drain region of the MISFET; a single gate bump electrode arranged over the gate electrode and coupled to the gate electrode through the gate opening; a plurality of source bump electrodes each respectively arranged over each of the respective plurality of regions of the source electrode and coupled to the source electrode through the source openings; a gate lead coupled to the gate bump electrode; a source lead coupled to the plurality of source bump electrodes; a drain lead coupled to the drain electrode; and a resin body sealing the semiconductor substrate.