Patent ID: 9406559
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method for forming a semiconductor structure, comprising: forming a gate structure over a substrate; forming source and drain regions adjacent to the gate structure in the substrate; forming a first inter-layer dielectric layer surrounding the gate structure over the source and drain regions over the substrate; forming a second inter-layer dielectric layer over the gate structure and the first inter-layer dielectric layer; forming a contact modulation structure over a portion of the second inter-layer dielectric layer over the gate structure; forming a first contact trench through the second inter-layer dielectric layer and the first inter-layer dielectric layer over the source and drain regions and forming a second contact trench through the second inter-layer dielectric layer and the contact modulation structure over the gate structure by performing a same etching process using a same etchant; forming a first contact in the first contact trench and a second contact in the second contact trench, wherein the first inter-layer dielectric layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate during the same etching process.