Patent ID: 9251070
Filing Date: 2016-02-02
CPC Classification: G06F

Claim Text:
1. A multi-level cache structure comprising: a first cache structure; a second cache structure, the second cache structure being hierarchically above the first cache; and the second cache comprising a tag array comprising a plurality of tag entries corresponding to respective addresses of data within a system memory; a selector array associated with the tag array; and a data array configured to store a subset of the data, wherein the tag array has an N-way associativity and the data array has M ways, where N and M are integers, with N being a larger integer than M; wherein the selector array comprises a plurality of bits that indicate, for each corresponding tag entry, whether or not data corresponding to the tag entry is present in the data array, and, when the data corresponding to the tag entry is present in the data array, a position of the data corresponding to the tag entry in the data array.