Patent ID: 9401364
Filing Date: 2016-07-26
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: an output terminal; a first terminal; a second terminal; a first circuit; and a second circuit, wherein the first circuit comprises a first transistor, a second transistor, and an inverter, wherein the second circuit comprises a third transistor, a fourth transistor, a third circuit, and a fourth circuit, wherein the third circuit comprises a first node, wherein the fourth circuit comprises a second node, wherein an input terminal of the inverter is electrically connected to the second terminal, wherein an output terminal of the inverter is electrically connected to the output terminal, wherein the first transistor and the second transistor are electrically connected in parallel between the second terminal and a wiring supplied with a first potential, wherein a gate of the first transistor is electrically connected to the output terminal of the inverter, wherein the third circuit is configured to make the first node in an electrically floating state, wherein the fourth circuit is configured to make the second node in an electrically floating state, wherein the third transistor and the fourth transistor are electrically connected in series between the first terminal and the second terminal, wherein the first node is electrically connected to the gate of the third transistor, and wherein the second node is electrically connected to a gate of the fourth transistor.