Patent ID: 9362222
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A semiconductor device structure, comprising: a metal-insulator-metal (MIM) capacitor formed on a substrate, wherein the MIM capacitor comprises a capacitor top metal (CTM) layer, an insulating layer and a capacitor bottom metal (CBM) layer; an inductor formed on the MIM capacitor; a via formed between the MIM capacitor and the inductor, wherein the via is formed in a plurality of dielectric layers, and the dielectric layers comprise an etch stop layer; a second etch stop layer formed above a top of the MIM capacitor, wherein a bottom of the via is level with a bottom of the second etch stop layer; a second via formed between the inductor and the CBM layer and in contact with the CBM layer; and a third etch stop layer formed above the CBM layer, wherein a bottom of the second via is level with a bottom of the third etch stop layer, and the bottom of the second via is in contact with the CBM layer.