Patent ID: 9455024
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising first and second storages that enable writing and reading of data, the first storage comprising: a first decoding line, a first word line, a first bit line, a second decoding line, a second word line, a second bit line; a first decoder including an output part that outputs a signal to the first decoding line; a first control circuit including an output part that outputs a signal to the first word line based on a first decoding signal supplied to the first decoding line; a first amplifier including an output part that outputs a signal to the first bit line; a second decoder that outputs a signal to the second decoding line; a second control circuit that outputs a second control signal to the second word line based on the signal supplied to the second decoding line; a first memory cell that stores, in response to a first control signal supplied to the first word line, data based on a first data signal supplied to the first bit line and outputs a second data signal based on the stored data to the second bit line in response to the second control signal; and a second amplifier that senses the signal of the second bit line and outputs a first output data signal based on the sensed signal, the second storage comprising: a third decoding line, a third word line, a third bit line, a fourth decoding line, a fourth word line, a fourth bit line; a third control circuit including an output part that outputs a signal to the third word line based on a third decoding signal supplied to the third decoding line; a fourth decoder that outputs a signal to the fourth decoding line; a fourth control circuit that outputs a fourth control signal to the fourth word line based on a signal supplied to the fourth decoding line; a second memory cell that stores, in response to a third control signal supplied to the third word line, data based on a third data signal supplied to the third bit line and outputs a fourth data signal based on the stored data to the fourth bit line in response to the fourth control signal; and a third amplifier that senses the signal of the fourth bit line and outputs a second output data signal based on the sensed signal, the first decoding line and the third decoding line being electrically connected to each other, the first bit line and the third bit line being electrically connected to each other.