Patent ID: 9304166
Filing Date: 2016-04-05
CPC Classification: G01R,H01L

Claim Text:
1. A system for testing semiconductor chips comprising: a plurality of semiconductor chips disposed in a wafer, each of the plurality of semiconductor chips having a first set of ports, a second set of ports, at least one test output port, at least one internal core logic, wherein at least one port of the first set of ports is for receiving test data; at least one connection disposed in a kerf region of the wafer between at least one port of the second set of ports of a first semiconductor chip and at least one port of the first set of ports of at least one second semiconductor chip in the plurality of semiconductor chips; wherein test data sent from a tester exclusively to the at least one port of the first set of ports of the first semiconductor chip is passed through an internal path of the first semiconductor chip and to the at least one port of the first set of ports of the at least one second semiconductor chip via the at least one connection, wherein the internal core logic enables the internal path of the first semiconductor chip to connect the at least one port of the first set of ports for receiving test data to the at least one port of the second set of ports of the first semiconductor chip; wherein the at least one test output port of each of the plurality of semiconductor chips is individually connected to the tester, wherein the tester is external to the wafer.