Patent ID: 9484389
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a three-dimensional resistive memory array, the method comprising the steps of: a) providing a substrate; b) forming a stack of layers arranged on top of each other on a front surface of the substrate, wherein the stack of layers comprises a repetitive sequence, each sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer, wherein the gate insulating layer is arranged between the semiconductor layer and the conductive layer; c) forming a plurality of parallel trenches through the stack of layers, the trenches being alternating of a first type and a second type and extending along and to the front surface of the substrate; d) removing at least a portion of the conductive layer in each sequence of the stack of layers from inner side walls of the first type and the second type of trenches such that recesses are formed in each sequence of the stack of layers; e) filling the trenches of the first type and the second type, and the recesses with a first type of dielectric material; f) removing the first type of dielectric material formed in the first type of trenches thereby exposing the side walls of the trenches of the first type thereby leaving the recesses filled; g) forming a metal oxide layer on the exposed inner side walls of the trenches of the first type, wherein the metal oxide layer is partly filling the first type of trenches, and wherein the metal oxide layer comprises a binary oxide from a transition metal; h) forming a first type of conductive material in a remaining portion of the trenches of the first type; i) removing the first type of dielectric material formed in the second type of trenches; j) forming a second type of conductive material in the trenches of the second type; k) forming in each trench of the first type a plurality of separated holes extending through the stack of layers, and exposing the metal oxide layer formed on the inner side walls of the trenches of the first type; l) forming in each trench of the second type a plurality of separated holes extending through the stack of layers; and m) filling the plurality of separated holes formed in the trenches of the first type and the second type with a second type of dielectric material.