Patent ID: 9349656
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of forming a complementary metal-oxide-semiconductor (CMOS) device, the method comprising: forming a first layer on an extension layer of a wafer, wherein the extension layer includes a first region associated with a p-type transistor and a second region associated with an n-type transistor, wherein the first region includes a first channel region between a first well implants region and a second well implants region, and wherein the second region includes a second channel region between a third well implants region and a fourth well implants region; forming a gate on the first region, wherein the gate is in contact with the extension layer and in contact with a first expansion region and a second expansion region that include a portion of the first layer, wherein the first expansion region provides a first conducting path between a first source and the first well implants region, and wherein the second expansion region provides a second conducting path between a first drain and the second well implants region; forming a second gate on the second region, wherein the second gate is in contact with the extension layer and in contact with a third expansion region and a fourth expansion region formed on a portion of the second region; and wherein the first expansion region, the second expansion region, the third expansion region, and the fourth expansion region comprise undoped semiconducting material.