Patent ID: 9424935
Filing Date: 2016-08-23
CPC Classification: G11C

Claim Text:
1. A semiconductor device, comprising: a memory string including a source selection transistor, first dummy memory cells, memory cells, second dummy memory cells and a drain selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a source selection line, first dummy word lines, word lines, second dummy word lines and a drain selection line, wherein the first dummy memory cells are coupled between the source selection transistor and the memory cells, and the second dummy memory cells are coupled between the drain selection transistor and the memory cells; and an operation circuit configured for performing a program operation on the memory string, wherein the operation circuit, after performing an operation programming the first and second dummy memory cells, is configured for sequentially performing a first operation programming memory cells adjacent to the drain selection transistor, a second operation programming memory cells adjacent to the source selection transistor, and a third operation programming remaining memory cells.