Patent ID: 9401305
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A method of forming air gaps in an integrated circuit comprising: forming a plurality of parallel lines of dielectric of equal height on a first layer of dielectric; the plurality of parallel lines defining first regions where no conductive material is to be located, a distance between adjacent lines in the first regions being smaller than a predetermined distance; the plurality of parallel lines defining second regions where conductive material is to be located, a distance between adjacent lines in the second regions being larger than the predetermined distance; subsequently, depositing a second layer that caps air gaps between lines in the first regions that are less than the predetermined distance apart and that deposits the second layer on the first layer of dielectric in the second regions where adjacent lines are more than the predetermined distance apart; subsequently removing the second layer in the second regions to expose the surface of the first layer; subsequently depositing barrier metal and conductive material across the first and second regions; and subsequently planarizing to expose the second layer in the first regions and to form individual lines of conductive material in the second regions.