Patent ID: 9274880
Filing Date: 2016-03-01
CPC Classification: H04L

Claim Text:
1. Circuitry for reducing errors in a data signal received over a high-speed serial link, wherein the data signal includes multiple groups of bits, and wherein each group of bits includes data bits and parity bits, the circuitry comprising: an interface circuit that receives the data signal over the high-speed serial link; an error generating circuit that receives at least a first group of bits of the multiple groups of bits and that generates an error signal based at least in part on a value of at least one additional bit in the first group of bits that is selected between an odd parity bit and an even parity bit; and an error correction circuit that receives the data signal from the interface circuit and that uses the parity bits to locate and correct only single-bit errors in the data bits of each group of bits in the data signal.