Patent ID: 9245624
Filing Date: 2016-01-26
CPC Classification: G11C

Claim Text:
1. A memory device comprising: an SRAM-type elementary memory cell having first and second inverter coupled to one another crosswise; a first non-volatile memory unit having a first non-volatile elementary memory cell with a first floating-gate transistor, the first floating-gate transistor having a second non-volatile memory unit having a second non-volatile elementary memory cell with a second floating-gate transistor, the second floating-gate transistor having a controllable interconnection stage with a first portion coupled between the second conduction electrode of the first floating-gate transistor and an output of the first inverter and a second portion coupled between the second conduction electrode of the second floating-gate transistor and an output of the second inverter; and a control circuit configured to cause the first and second floating-gate transistors to turn off when a data item stored in the SRAM-type elementary memory cell is differentially programmed into the first and second non-volatile memory units.