Patent ID: 9438206
Filing Date: 2016-09-06
CPC Classification: H03K

Claim Text:
1. A storage circuit comprising: a first logic circuit; a second logic circuit; a first transistor; a second transistor; a third transistor; a fourth transistor; a first capacitor; a second capacitor; a first node; a second node; and a third node, wherein the first capacitor is connected to the first node, wherein an input terminal of the second logic circuit is connected to the second node, wherein the first transistor is configured to control connection between an output terminal of the first logic circuit and the first node, wherein a first clock signal is input to a gate of the first transistor, wherein the second transistor is configured to control connection between the first node and the second node, wherein a second clock signal is input to a gate of the second transistor, wherein the second capacitor is connected to the third node, wherein the third transistor is configured to control connection between the input terminal of the second logic circuit and the third node, wherein the fourth transistor is configured to control connection between the first node and the third node, wherein phases of the first clock signal and the second clock signal are inverted from each other, and wherein a channel formation region of each of the first transistor, the second transistor, the third transistor and the fourth transistor includes an oxide semiconductor.