Patent ID: 9418988
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A four transistor circuit layout for an integrated circuit substrate, comprising: an isolation region in the integrated circuit substrate that defines an active region, the active region extending along first and second different directions; a common source region of the four transistors that extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region; four drain regions, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region; and four gate electrodes, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions, a respective gate electrode including a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction, wherein the active region is recessed between the first extending portions of the gate electrodes of a first pair of the four transistors and between the first extending portions of the gate electrodes of a second pair of the four transistors, so that the isolation region protrudes between the first extending portions of the gate electrodes of the first pair of the four transistors and between the first extending portions of the gate electrodes of the second pair of the four transistors.