Patent ID: 9298872
Filing Date: 2016-03-29
CPC Classification: G06F,H01L

Claim Text:
1. A method of optimizing timing for a critical path of an integrated circuit design comprising: receiving a description of the critical path including a path timing constraint for the critical path, the critical path having a plurality of nodes, by executing first instructions in a computer system; identifying selected gates corresponding to certain nodes of the critical path, by executing second instructions in the computer system; assigning internal timing constraints to the selected gates using the path timing constraint, by executing third instructions in the computer system; translating the internal timing constraints into physical locations respectively associated with the selected gates, by executing fourth instructions in the computer system; applying placement constraints to the selected gates based on the physical locations, by executing fifth instructions in the computer system; and performing a timing-driven placement optimization of the critical path subject to the placement constraints, by executing sixth instructions in the computer system.