Patent ID: 9378814
Filing Date: 2016-06-28
CPC Classification: G11C

Claim Text:
1. A system, comprising: a plurality of memory cells, the plurality of memory cells includes a first memory cell and a second memory cell; and one or more managing circuits in communication with the plurality of memory cells, the one or more managing circuits configured to cause a first sense amplifier to be coupled to a first bit line, the first bit line is connected to the first memory cell, the first sense amplifier includes a first precharge circuit, the first precharge circuit includes a first transistor, the first transistor includes a first gate and a first source node, the first source node is connected to the first bit line, the one or more managing circuits configured to cause the first bit line to be precharged to a read voltage using the first precharge circuit, the first precharge circuit configured to set the first gate to a first bias voltage based on feedback from the first bit line, the one or more managing circuits configured to cause a second sense amplifier to be coupled to a second bit line, the second bit line is connected to the second memory cell, the second sense amplifier includes a second precharge circuit, the second precharge circuit includes a second transistor, the second transistor includes a second gate and a second source node, the second source node is connected to the second bit line, the one or more managing circuits configured to cause the second bit line to be precharged to the read voltage using the second precharge circuit, the second precharge circuit configured to set the second gate to a second bias voltage based on feedback from the second bit line, the second bias voltage is different from the first bias voltage, the one or more managing circuits configured to cause the first memory cell to be sensed using the first sense amplifier and the second memory cell to be sensed using the second sense amplifier.