Patent ID: 9331648
Filing Date: 2016-05-03
CPC Classification: H03F

Claim Text:
1. An amplifier circuit for improved slew rate comprises a common mode rejection stage; a primary gain stage; an output stage; said primary gain stage comprising a circuit for enhancing a first output impedance; a reduced compensation capacitor being needed to obtain a frequency pole, wherein said frequency pole is the same to an ordinary amplifier's frequency pole; said compensation capacitor being added to only one side of a differential op-amp circuit; an output voltage being taken from the same side where said phase compensation capacitor is added; said primary gain stage adopting a cascade configuration; said cascade configuration preventing a systematic offset; said cascade configuration regulating a common mode input range of said amplifier circuit; said common mode rejection stage being before said primary gain stage; said common mode rejection stage rejecting a common mode signal; the differential op-amp circuit comprising resistors r said cascade configuration comprising transistors M said primary gain stage comprising a common source circuit; said common mode rejection stage comprising transistors M the resistors r