Patent ID: 9337809
Filing Date: 2016-05-10
CPC Classification: H03K

Claim Text:
1. An information processing device comprising a plurality of semiconductor integrated circuits, each of the plurality of semiconductor integrated circuits includes: an identification information storage for storing identification information of the semiconductor integrated circuit; an intermediate clock generator for generating an intermediate clock having a frequency higher than that of a reference clock using the reference clock input to the semiconductor integrated circuit from the outside of the semiconductor integrated circuit; an operating clock generator for generating an operating clock having a frequency higher than that of the reference clock and lower than that of the intermediate clock in synchronization with a timing allotted according to the identification information stored in the identification information storage, using the intermediate clock; a signal terminal fixed at a predetermined logic level; and an identification information setter for causing the identification information storage to store a signal input to the signal terminal as the identification information when the plurality of semiconductor integrated circuits are reset, the plurality of semiconductor integrated circuits being distinguished from each other according to the identification information; wherein the operating clock generators provided in the plurality of semiconductor integrated circuits generate the operating clocks at timings different from each other.