Patent ID: 9401711
Filing Date: 2016-07-26
CPC Classification: H03K

Claim Text:
1. A circuit of an output stage of a push-pull driver having dynamic biasing, the circuit comprising: a first stacked configuration of p-type field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, wherein the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a first switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET; and a first transmission gate connected to a second supply voltage, wherein the first transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a first voltage breakdown condition associated with the first stacked configuration of PFETs, and wherein the third PFET is bias controlled via the switching of the output of the first switchable voltage bias generator circuit.