Patent ID: 9229792
Filing Date: 2016-01-05
CPC Classification: G06F,H04L,H04N,H04W

Claim Text:
1. An apparatus comprising: a hardware memory device configured to store a message queue storing at least i) a first message having a first weight indicating a first transmission priority assigned by a first device that produced the first message and ii) a second message having a second weight indicating a second transmission priority assigned by the first device, or a second device, that produced the second message, wherein the hardware memory device is configured to store the first message and the second message in the message queue in a first order in which the first message and the second message are received; and a message scheduler having a plurality of slots, the message scheduler separate from the hardware memory device and configured to obtain the first weight and the second weight, wherein the first weight is different from the second weight, use the first weight and the second weight, store information corresponding to the first message in a first slot among the plurality of slots and store information corresponding to the second message in a second slot among the plurality of slots such that an order of the first slot and the second slot in the plurality of slots indicates a second order to retrieve the first message and the second message from the message queue, and determine whether a first pending bit for the first message has not been set, determine whether a second pending bit for the second message has not been set, when the message scheduler determines that the first pending bit has not been set and determines that the second pending bit has not been set, retrieve the first message and the second message from the message queue according to the second order indicated by the order of the first slot and the second slot in the plurality of slots of the message scheduler separate from the hardware memory device.