Patent ID: 9437276
Filing Date: 2016-09-06
CPC Classification: G06F,G06Q,G11C

Claim Text:
1. A method of operating a memory controller that controls the operation of a memory device, the memory device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the method comprising: the memory controller transmitting a refresh command, along with a plurality of bits, to the command interface of the memory device, wherein responsive to the refresh command, during a first time interval, the memory device performs a refresh operation to refresh data stored in at least one bank of the plurality of memory banks, the plurality of bits to identify at least one bank as a first bank of the plurality of banks to be refreshed in a sequence; and transmitting an operation code from the memory controller to the memory device, the operation code specifying a calibration operation of the command interface; wherein, after receiving the operation code, the memory device is to perform the calibration operation of the command interface of the memory device while performing the refresh operation to the at least one bank identified by the plurality of bits.