Patent ID: 9502573
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A pixel structure disposed on a substrate, comprising: an active device disposed on the substrate comprising a gate, a semiconductor channel layer, a source and a drain, wherein the source and the drain are disposed above the gate and separated by a gap such that the gate has at least one portion that is not overlapped with the source and the drain, and the semiconductor channel layer is at least disposed in the gap between the source and the drain; a gate insulation layer disposed between the gate and the semiconductor channel layer, wherein the source and the drain are disposed between the gate insulation layer and the semiconductor channel layer; a dielectric insulation layer disposed on the substrate and covering the semiconductor channel layer, wherein a dielectric index of the dielectric insulation layer is greater than a dielectric index of the gate insulation layer; a capacitance electrode disposed on the dielectric insulation layer and the capacitance electrode overlapping with the drain such that the capacitance electrode, the drain and the dielectric insulation layer sandwiched between the capacitance electrode and the drain constitute a storage capacitor structure, wherein the capacitance electrode is not overlapping with the gate and the source; a protection layer disposed on the dielectric insulation layer, wherein the capacitance electrode located between the protection layer and the dielectric insulation layer; and a pixel electrode disposed on the protection layer and connected to the drain of the active device.