Patent ID: 9431083
Filing Date: 2016-08-30
CPC Classification: G11C

Claim Text:
1. A nonvolatile memory device comprising: first and second true cells storing data; first and second complementary cells storing complementary data of the data; bit lines respectively connected to first ends of the first and second true cells; complementary bit lines respectively connected to first ends of the first and second complementary cells; a first sub word line connected to second ends of the first true cells; a second sub word line connected to second ends of the second true cells; a first complementary sub word line connected to second ends of the first complementary cells; a second complementary sub word line connected to second ends of the second complementary cells; and a first transistor configured to connect the first sub word line to a first source line in response to a first on voltage applied to a first word line; a first complementary transistor configured to connect the first complementary sub word line to a first complementary source line in response to the first on voltage; a second transistor configured to connect the second sub word line to the first source line in response to a second on voltage applied to a second word line; and a second complementary transistor configured to connect the second complementary sub word line to the first complementary source line in response to the second on voltage.