Patent ID: 9262177
Filing Date: 2016-02-16
CPC Classification: G06F

Claim Text:
1. A computer system for initializing a plurality of processors of a multi-processor system, the computer system comprising the steps of: a memory containing external initialization code; a plurality of processors, wherein each of the plurality of processors store local initialization code, and wherein the plurality of processors and the memory are interconnected such that a designated processor of the plurality of processors is capable of receiving external initialization code from the memory, and a remainder of the plurality of processors are capable of receiving external initialization code from the designated processor but are not capable of receiving external initialization code from the memory; and control logic operable to: execute, at each respective processor of the plurality of processors, at least a portion of local initialization code stored on the respective processor; receive, external initialization code stored in external memory through a designated pin on a designated processor out of the plurality of processors, wherein only through the designated pin of the designated processor is external initialization code capable of being received and the remainder of the plurality of processors do not include the designated pin for receiving external initialization code stored in external memory; and determine, by the designated processor, to send at least a portion of the external initialization code to a processor of the remainder of the plurality of processors.