Patent ID: 9330971
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method for fabricating an integrated circuit comprising: etching an ILD layer of dielectric material overlying a semiconductor substrate that comprises a device region to form first contact vias that expose active areas of the device region; etching the ILD layer to form second contact vias that correspondingly expose a gate that is disposed in the device region adjacent to the active areas and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region, wherein the patterned resistive metal-containing layer is spaced apart and separated from the gate by at least a portion of the dielectric material; and filling the first contact vias and the second contact vias with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively, wherein, prior to filling, the active areas, the gate, and the patterned resistive metal-containing layer are concurrently exposed by the first and second contact vias, and wherein filling comprises filling the first and second contact vias with the electrically-conductive material to simultaneously cover exposed portions of the active areas, the gate, and the patterned resistive metal-containing layer.