Patent ID: 9477805
Filing Date: 2016-10-25
CPC Classification: G06F

Claim Text:
1. A method comprising: identifying, by a computing system, matched register pairs, each having one register in a first circuit design and one register in a second circuit design; determining, by the computing system in a combinational equivalence check mode, a portion of combinational logic, corresponding to a first matched register pair, in the first circuit design is not equivalent to a portion of combinational logic, corresponding to the first matched register pair, in the second circuit design; switching the computing system from the combinational equivalence check mode to a sequential equivalence check mode; sequentially expanding, by the computing system in the sequential equivalence check mode, the portions of the combinational logic in the first circuit design and the second circuit design by coupling the portions of the combinational logic corresponding to the first matched register pair to combinational logic corresponding to a second matched register pair; and determining, by the computing system, whether the expanded portion of the combinational logic in the first circuit design is equivalent to the expanded portion of the combinational logic in the second circuit design.