Patent ID: 9406682
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a plurality of first semiconductor fins in a first device region of a substrate and a plurality of second semiconductor fins in a second device region of the substrate, wherein the plurality of first semiconductor fins are separated from each other by a first spacing and the plurality of second semiconductor fins are separated from each other by a second spacing that is greater than the first spacing; forming sacrificial spacers on sidewalls of the plurality of first semiconductor fins and the plurality of second semiconductor fins, wherein the sacrificial spacers fill spaces between the plurality of first semiconductor fins, but only partially fill spaces between the plurality of second semiconductor fins and between an outermost first semiconductor fin of the plurality of first semiconductor fins and an adjacent outermost second semiconductor fin of the plurality of second semiconductor fins, leaving gaps between the plurality of second semiconductor fins and between the outermost first semiconductor fin and the adjacent outermost second semiconductor fin; forming dielectric barrier layer portions on the substrate, the dielectric barrier layer filling the gaps between the sacrificial spacers; removing the sacrificial spacers selective to the dielectric barrier layer portions; forming a gate structure over a channel portion of each of the plurality of first semiconductor fins and the plurality of second semiconductor fins; and forming source/drain regions on portions of the plurality of first semiconductor fins and the plurality of second semiconductor fins that are not covered by the gate structure, wherein the source/drain regions merge the plurality of first semiconductor fins but not the plurality of second semiconductor fins.