Patent ID: 9429618
Filing Date: 2016-08-30
CPC Classification: G01R,H03K

Claim Text:
1. A semiconductor integrated circuit device comprising: an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor; a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor; a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor, a first output terminal unit withdrawn from a connection node of the PMOS transistor and the NMOS transistor; a second output terminal unit electrically coupled to a source of the PMOS transistor; and a loop forming unit configured to electrically couple the second output terminal unit and a source of the NMOS transistor, wherein the first and second output terminals and the loop forming unit are configured to measure a current value of a first current path flowing through the PMOS transistor and a current value of a second current path flowing through the NMOS transistor.