Patent ID: 9383841
Filing Date: 2016-07-05
CPC Classification: G06F,G09G,G11C

Claim Text:
1. A shift register circuit comprising: a pull up control circuit configured to provide a pull up control signal; a first pull up circuit configured to provide a sensor driving signal in response to the pull up control signal and a second clock signal; a second pull up circuit configured to provide a gate driving signal in response to a first clock signal, the pull up control signal and the second clock signal; a first pull down control circuit configured to output a first pull down control signal; a first pull down circuit configured to pull down the pull up control signal, the sensor driving signal and the gate driving signal in response to the first pull down control signal; and a main pull down circuit configured to pull down the pull up control signal and the gate driving signal; a second pull down control circuit configured to output a second pull down control signal; and a second pull down circuit configured to pull down the pull up control signal, the sensor driving signal and the gate driving signal in response to the second pull down control signal; wherein a high level of the first clock signal and a high level of the second clock signal have a overlapped ratio there between, and a pulse width of the sensor driving signal and a pulse width of the gate driving signal have a ratio there between.