Patent ID: 9336898
Filing Date: 2016-05-10
CPC Classification: G09G,G11C

Claim Text:
1. A shift register unit comprising: a pull-up control module for receiving an input signal and outputting a pull-up control signal to a pull-up node; a pull-up module for providing a signal input from a first clock signal input terminal to a first output terminal according to the pull-up control signal at the pull-up node; a reset module for providing a first power supply voltage to the pull-up node and the first output terminal according to a reset signal; a denoise module for holding a signal output from the first output terminal when the signal output from the first output terminal has a level higher than a first preset threshold and outputting the held signal output from the first output terminal from a second output terminal when a signal input from a denoise control signal input terminal has a level higher than a second preset threshold; wherein the denoise module comprises a seventh transistor and a second capacitor, the seventh transistor has a control terminal and a first terminal connected together to the first output terminal, and a second terminal connected to a first terminal of the second capacitor; and a second terminal of the second capacitor is connected to the first power supply voltage.