Patent ID: 9355963
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a base having a first side and a second side opposite the first side; a first redistribution layer on the first side of the base, the first redistribution layer configured to couple the base with an external device; a first die attached to the second side of the base with an active side of the first die facing away from the base; a second die attached to the second side of the base adjacent the first die with an active side of the second die facing away from the base; an interposer attached to the active side of the first die and the active side of the second die; an encapsulation layer encapsulating the second side of the base, the first die, the second die, and the interposer; a first plurality of vias coupled to the first die; a second plurality of vias coupled to the second die, the first plurality of vias and the second plurality of vias extending partially through the encapsulation layer; and a third plurality of vias extending through the encapsulation layer and the base.