Patent ID: 9514937
Filing Date: 2016-12-06
CPC Classification: B82Y,H01L

Claim Text:
1. A method of forming a non-planar semiconductor device comprising: forming at least one semiconductor nanowire suspended above an insulator layer of a semiconductor-on-insulator substrate, wherein an end segment of said at least one semiconductor nanowire is attached to a first semiconductor-on-insulator pad region and another end segment of said at least one semiconductor nanowire is attached to a second semiconductor-on-insulator pad region, said first and second semiconductor-on-insulator pad regions are both located atop said insulator layer; forming at least one semiconductor nanowire into at least one suspended and tapered semiconductor nanowire comprising a first semiconductor nanowire portion having a first width, a second semiconductor nanowire portion having a second width and a third semiconductor nanowire portion having a third width, wherein said third semiconductor nanowire portion is located between the first and second semiconductor nanowire portions, and said first width is less than the third width, and wherein said third width is less than the second width; forming a gate on a portion of said third semiconductor nanowire portion of said at least one semiconductor nanowire, wherein said first semiconductor nanowire portion is located on a first side of the gate and said second semiconductor nanowire portion is located on a second side of the gate that is opposite to said first side; forming a source region on said first side of the gate and forming a drain region on the second side of the gate; and forming a polysilicon line on a surface of said gate and having a bottommost surface directly contacting a surface of said insulator layer.