Patent ID: 9520876
Filing Date: 2016-12-13
CPC Classification: G06F,H01L,H03K

Claim Text:
1. A semiconductor comprising: a front end of line portion that includes a first logical processing unit (LPU) and a second LPU, the first LPU designed to perform a first operation and the second LPU designed to perform a second operation following the first operation; a back end of line (BEOL) portion that includes a plurality of wiring levels, and further includes a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels, the power gate and the clock gate are further electrically connected to the first LPU by an enable wire, the power gate and the clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU; and a signal wire is electrically connected to the first LPU, and is also electrically connected to the latch.