Patent ID: 9450184
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A multilayer-stacked resistive random access memory device comprising: first and second electrode layers; a resistive oxide layer which is electrically coupled to said first and second electrode layers, which exhibits resistive switching characteristics, and which includes a first metal oxide containing a first metal selected from the group consisting of W, Ti, Zr, Sn, Ta, Ni, Ag, Co, Hf, Ru, Mo, Cr, Fe, Al, and combinations thereof; a sulfide layer contacting said resistive oxide layer, disposed between said resistive oxide layer and said first electrode layer, and including a metal sulfide that contains a second metal that is the same as said first metal, and a conductive oxide layer disposed between said resistive oxide layer and said second electrode layer; wherein said sulfide layer cooperates with said resistive oxide layer to form a p-n junction therebetween.