Patent ID: 9369317
Filing Date: 2016-06-14
CPC Classification: H03M,H04B,H04L

Claim Text:
1. Circuitry for converting a multi-level signal into at least one binary signal, the multi-level signal having a period T and comprising n signal levels, n being equal to or greater than 3, comprising: comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n−1) different reference values, and having N sets of (n−1) output terminals for outputting N sets of (n−1) output signals, each set of (n−1) output signals indicating whether the value of the multi-level signal is below or above the (n−1) reference values, wherein N is greater than or equal to 2; N sets of (n−1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, each set of the N sets being arranged for sampling-and-holding at moments in time that are shifted in time with respect to another set of the N sets, wherein each output terminal of a set of the N sets of (n−1) output terminals is connected to the input of a sample-and-hold circuit of a corresponding set of the N sets of (n−1) sample-and-hold circuits; and logical circuitry connected to the outputs of the N sets of (n−1) sample-and-hold circuits for generating at least one binary signal having a period N*T, using the signals on the outputs of the N sets of (n−1) sample-and-hold circuits.