Patent ID: 9368505
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A mask read-only memory, comprising a plurality of storage units arranged in an array, wherein the mask read-only memory comprises two kinds of storage units with different structures, the two kinds of storage units with different structures are a first MOS transistor and a second MOS transistor, a source and a drain of the first MOS transistor have the same type, a source and a drain of the second MOS transistor have inverse types, wherein the first MOS transistor and the second transistor are both provided with control gates of their own each formed directly on a gate oxide dielectric, the first MOS transistor and the second MOS transistor are both provided with lightly doped drain regions located between the drain and its control gate and between the source and its control gate, wherein sidewalls of the control gate are formed on the respective lightly doped regions, outer edges of the sidewalls coincide with inners edge of the source and drain, respectively, of each of the first MOS transistor and the second MOS transistor, and the mask read-only memory is unrewritable and inerasable.