Patent ID: 9484106
Filing Date: 2016-11-01
CPC Classification: G11C

Claim Text:
1. A nonvolatile semiconductor memory comprising: a plurality of memory cells arranged in a matrix form; word lines connected to said plurality of memory cells; bit lines crossing said word lines and connected to said plurality of memory cells, respectively, such that a current is simultaneously supplied from a power supply line via said bit lines to said memory cells to write data to said memory cells; charge amount measurement sections for measuring amounts of charge stored in the corresponding ones of said memory cells, respectively; first current routes each being connected between said power supply line and a predetermined terminal being in a predetermined potential; second current routes each connecting said power supply line to the corresponding ones of said bit lines; and a control circuit, connected to said charge amount measurement sections, for adjusting an amount of current supplied from said power supply line to each of said first current routes and said second current routes depending on a measured value of the amount of charge measured by said charge amount measurement section associated with the memory cell concerned; wherein each of said first current routes includes a switch element connected to said power supply line, and a current amount adjustment element connected between the switch element and said predetermined terminal.