Patent ID: 9444470
Filing Date: 2016-09-13
CPC Classification: H03L

Claim Text:
1. A double phase-locked loop, comprising: a first narrowband phase-locked loop including a first loop filter configured to reduce phase noise in a first input clock; a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source, said second input clock having a frequency with a fractional offset relative a frequency of said first input clock of not more than 200 ppm; said first phase-locked loop having a bandwidth at least an order of magnitude less than said second phase-locked loop; a controlled oscillator driven by a local oscillator responsive to a control input to generate an output with a frequency and phase, said second loop filter providing said control input so that at start-up said controlled oscillator locks to said second input clock; and a coupler coupling an output of said first loop filter to said second phase-locked loop, said first-phase locked loop being operable when said second phase locked loop is locked to said second input clock to modify said control input with the output of said first loop filter so that said controlled oscillator gradually becomes locked to said first input clock in both frequency and phase.