Patent ID: 9436464
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. An instruction-issuance controlling device included in a multithread processor, the device comprising: a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state; a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution; and an instruction-issuance controlling unit configured to control the multithread processor so that simultaneously issuable instructions are issued from the selected thread, wherein the resource management unit is configured to, for each of the threads in execution, (i) manage the number of stalled cycles which indicates the number of remaining cycles for the stalled state to determine whether or not the number of the stalled cycles is one or more, and (ii) determine that the thread is not in the stalled state and update the stall information if the number of the stalled cycles is 0.