Patent ID: 9349691
Filing Date: 2016-05-24
CPC Classification: C23F,H01L

Claim Text:
1. A method of fabricating a semiconductor interconnect structure, the method comprising: providing a semiconductor structure including a first dielectric layer having a first electrically conductive structure embedded therein, a second dielectric layer located above the first dielectric layer, the second dielectric layer and the first dielectric layer having a segment of a dielectric capping layer and a segment of a metal capping layer located therebetween such that the segment of the dielectric capping layer is horizontally planar with the segment of the metal capping layer, the segment of metal capping layer covers and abuts at least a portion of a top surface of the first electrically conductive structure; forming an opening in the second dielectric layer and the metal capping layer, thereby exposing at least a portion of the first electrically conductive structure and a portion of the dielectric capping layer; and forming a second electrically conductive structure in the opening, such that a first bottom portion of the second electrically conductive structure is located over a portion of the dielectric capping layer, and such that a second bottom portion of the second electrically conductive structure is in electrical contact with the portion of the first electrically conductive structure.