Patent ID: 9437701
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. An integrated circuit device, comprising: a semiconductor substrate having a substrate surface; a well of a first conductivity type extending from the substrate surface; a source of a second conductivity type, which is different from the first conductivity type, formed within the well and extending from the substrate surface; a drain of the second conductivity type formed within the well and extending from the substrate surface; a channel formed within the well, the channel extending along the substrate surface and electrically separating the source and the drain; a conductive gate extending across the substrate surface and along the channel between the source and the drain and comprising (i) a first gate region of the second conductivity type, wherein the first gate region comprises a second dopant of the second conductivity type, (ii) a second gate region of the second conductivity type, wherein the second gate region comprises the second dopant of the second conductivity type, and (iii) a third gate region of the first conductivity type, wherein the third gate region extends between the first gate region and the second gate region, wherein the third gate region comprises a first dopant of the first conductivity type, and further wherein a concentration of the first dopant within the third gate region is at least 110% of a concentration of the second dopant within the first gate region and within the second gate region; a gate dielectric extending between and electrically isolating the conductive gate and the substrate surface; and a silicide region in electrical communication with the first gate region, the second gate region, and the third gate region.