Patent ID: 9368168
Filing Date: 2016-06-14
CPC Classification: G11C

Claim Text:
1. A nonvolatile memory device comprising: a nonvolatile memory cell array including a plurality of nonvolatile memory cells; and a peripheral circuit configured to receive an address through input/output pins during an address input cycle, to read data from the nonvolatile memory cell array based on the address, and to output the data read from the nonvolatile memory cell array through the input/output pins during a data output cycle, wherein the peripheral circuit is configured to select one of a first alignment type and a second alignment type, the peripheral circuit is configured to receive a first signal toggling between a high level and a low level, and to output a second signal toggling between a high level and a low level during the data output cycles, the peripheral circuit is configured to receive the address in synchronization with one of a rising edge and a falling edge of the first signal regardless of whether the first alignment type is selected or the second alignment type is selected, and the peripheral circuit is configured to output the data in synchronization with both a rising edge and a falling edge of the second signal during the data output cycle when the first alignment type is selected.