Patent ID: 9241420
Filing Date: 2016-01-19
CPC Classification: G11C,H01L,H05K

Claim Text:
1. A microelectronic package, comprising: a package substrate having first and second oppositely facing surfaces, a plurality of first terminals at the second surface of the package substrate and configured for connection with a component external to the package, the plurality of first terminals configured to carry address information; and first and second microelectronic elements each having a first face confronting the first surface of the substrate, each microelectronic element including a memory storage array, and each microelectronic element having address inputs for receipt of address information specifying locations within the memory storage array of the respective microelectronic element, the package substrate further having a plurality of address lines electrically connected with the plurality of first terminals and configured to carry address information to a first connection region on the substrate, the first connection region having a first delay from the plurality of first terminals, the address lines being configured to carry the address information beyond the first connection region at least to a second connection region on the substrate having a second delay from the plurality of first terminals, wherein the address inputs of the first microelectronic element are coupled with each of the plurality of address lines at the first connection region, and the address inputs of the second microelectronic element are coupled with each of the plurality of address lines at the second connection region, wherein the second delay is greater than the first delay; and an encapsulant material overlying second faces of the first and second microelectronic elements that face away from the package substrate.