Patent ID: 9362951
Filing Date: 2016-06-07
CPC Classification: G06F,H03M

Claim Text:
1. A decoding method for low density parity code, and for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of first memory cells, and the decoding method comprises: reading a data bit of each of the first memory cells; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of the low density parity code, obtaining reliability message of each of the data bits according to the checks, and deciding an index of an error bit from the data bits according to the reliability messages, wherein the index of the error bit comprises at least one of a first index of a first error bit and a second index of a second error bit, wherein the first error bit corresponding to the first index is different from the second error bit corresponding to the second index in an arrangement of the data bits; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding, and correcting the data bit according to the index of the error bit, wherein the first index is used to correct the first error bit, and the second index is used to correct the second error bit.