Patent ID: 9258506
Filing Date: 2016-02-09
CPC Classification: H03K,H03M,H04N

Claim Text:
1. A counter circuit comprising: a first counter which is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval; and a second counter which is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval, wherein N and M are natural numbers, N is greater than M, and M is greater than or equal to 3.