Patent ID: 9431458
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: forming a first electrode layer, a selection device layer and a variable resistance layer sequentially on a substrate; selectively etching the variable resistance layer to form preliminary variable resistance layer patterns each extending longitudinally in a first direction; forming a first protective layer along sides of the preliminary variable resistance layer patterns, and a top surface of the selection device layer; etching portions of the first protective layer, the selection device layer and the first electrode layer situated between the preliminary variable resistance layer patterns to form first protective layer patterns, preliminary selection device patterns and first electrodes; forming a second electrode layer on the preliminary variable resistance layer patterns; selectively etching the second electrode layer and the preliminary variable resistance layer patterns to form second electrodes and variable resistance layer patterns, the second electrodes each extending longitudinally in a second direction that crosses the first direction; forming a second protective layer along side surfaces of the second electrodes, sides the variable resistance layer patterns, and sides of the preliminary selection device patterns; and etching portions of the second protective layer and the preliminary selection device patterns situated between the variable resistance layer patterns to form second protective layer patterns and selection device patterns.