Patent ID: 9444497
Filing Date: 2016-09-13
CPC Classification: G06F,H03K,H03M,Y02D

Claim Text:
1. An integrated circuit comprising: at least one monitored path comprising a plurality of circuit elements operating on a clock signal, wherein a last circuit element of said plurality of circuit elements comprises a first flip flop; a second flip flop either: (a) operating on an early clock signal that is phase shifted from said clock signal, or (b) coupled via a delay to said at least one monitored path, wherein said second flip flop is coupled to said at least one monitored path at a point prior to said last circuit element; a transition detection module coupled to said at least one monitored path for detecting when an output from said first flip flop toggles; an error prediction module coupled to said second flip flop to predict a potential error on said at least one monitored path; and a controller coupled to said transition detection module and said error prediction module, wherein said controller is configured to adaptively scale a voltage or a frequency of said integrated circuit based on an output of the transition detection module and an output of the error prediction module, to prevent the potential error from occurring on said at least one monitored path.