Patent ID: 9508434
Filing Date: 2016-11-29
CPC Classification: G11C

Claim Text:
1. A non-volatile memory comprising a plurality of elementary cells arranged in rows and in columns, each cell comprising: a first access transistor coupling first and second nodes of the cell; a second access transistor coupling the first node to a third node of the cell, wherein the first and second transistors are MOS transistors of opposite conductivity types, or wherein the first and second transistors have different dimensions or wherein the first and second transistors are MOS transistors of opposite conductivity types and have different dimensions; and a single programmable-resistance storage element connected to the first node, this storage element coupling the first node to a fourth node of the cell, wherein, in each row, the cells have their fourth nodes connected by a first row-connection conductive track, and the gates of their first transistors connected by a second row-connection conductive track, and wherein, in each column, the cells have their second nodes connected by a first column-connection conductive track and their third nodes connected by a second column-connection conductive track, the memory further comprising a control circuit connected to the cells via the first and second row-connection conductive tracks and the first and second column-connection conductive tracks, this circuit being configured for: during a phase of programming a cell to a first state, applying a voltage of a first biasing across the storage element of the cell via the fourth and second nodes and the first transistor of the cell, the second transistor of the cell being maintained off; and during a phase of programming the cell to a second state, applying a voltage having an opposite biasing across the storage element of the cell via the fourth and third nodes and the second transistor of the cell, the first transistor of the cell being maintained off.