Patent ID: 9281311
Filing Date: 2016-03-08
CPC Classification: G11C,H01L

Claim Text:
1. An integrated circuit, comprising: a plurality of bit lines of a memory cell array disposed in a first metal layer and extending in a first direction; a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction; and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, wherein the write-assist circuit comprises at least two serially coupled inverters, a capacitor having a first node coupled to an output of the at least two serially coupled inverters and a second node coupled to the driving source node, and a metal oxide semiconductor transistor having a source coupled to the driving source node and a drain coupled to at least one of the plurality of bit lines, wherein the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the at least one of the plurality of bit lines.