Patent ID: 9472529
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. An electronic circuit, comprising: a first chip including first electronics and a first connector including a plurality of self-alignment features and conductive pads; a second chip including second electronics and a second connector including a plurality of self-alignment features and conductive pads; and a third chip including a third connector and a fourth connector, the third connector including a plurality of self-alignment features and conductive pads, the fourth connector including a plurality of self-alignment features and conductive pads, the conductive pads of the third connector and the conductive pads of the fourth connector being electrically connected, wherein the first chip and the second chip are electrically connected to one another through the third chip with the conductive pads of the first connector electrically connected to the conductive pads of the third connector and with the conductive pads of the second connector electrically connected to the conductive pads of the fourth connector, and wherein the first chip and the second chip are horizontally aligned in a coplanar manner with the self-alignment features of the first connector aligned with the self-alignment features of the third connector and with the self-alignment features of the second connector aligned with the self-alignment features of the fourth connector.