Patent ID: 9377825
Filing Date: 2016-06-28
CPC Classification: G06F,G11C,H01L

Claim Text:
1. A semiconductor device comprising: a wiring board having a main surface, a rear surface opposite to the main surface, a long side, a short side intersecting the long side, a plurality of first terminals arrayed along the long side on the main surface, a plurality of second terminals arrayed along the short side on the main surface, and external connecting terminals formed on the rear surface; a memory chip mounted over the main surface of the wiring board, the memory chip having a first main surface, a first side, a second side intersecting the first side, and a plurality of first electrodes arrayed along the second side on the first main surface, the first electrodes being connected with the second terminals of the wiring board via a plurality of first wires; and a controller chip mounted over the first main surface of the memory chip, the controller chip being operable to control the memory chip and having a second main surface and a plurality of second electrodes arrayed on the second main surface, the second electrodes being connected with the first terminals of the wiring board via a plurality of second wires, wherein the long side of the wiring board includes a first portion and a second portion, and the first terminals are arrayed between the first side of the memory chip and the first portion of the long side of the wiring board in a plan view, wherein a distance between the first portion of the long side of the wiring board and the first side of memory chip is greater than a distance between the second portion of the long side of the wiring board and the first side of the memory chip in a first direction perpendicular to the first side of the memory chip, and wherein the second terminals are arranged on a first area of the main surface of the wiring board between the second side of memory chip and the short side of the wiring board.