Patent ID: 9437530
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A combined packaged power semiconductor device, comprising: a high-side (HS) MOSFET and a low-side (LS) MOSFET, each of said HS and LS MOSFETs comprising a bottom drain, a top gate and a top source; a lead frame comprising a die paddle and a plurality of pins separated and electrically insulated from said die paddle, wherein said LS MOSFET is flipped and stacked on said die paddle forming an electrical connection between said LS source and a top surface of said die paddle, as such said LS source is electrically connected to an exposed bottom surface of said die paddle; a first metal interconnection plate stacked on said drain of said flipped LS MOSFET, wherein said HS MOSFET directly stacked or flipped first and then stacked on said first metal interconnection plate, forming an electrical connection between said HS drain or flipped HS source and said LS drain through said first metal interconnection plate; a second metal interconnection plate stacked and electrically connected to said source of said HS MOSFET or said drain of said flipped HS MOSFET; and an integrated circuit (IC) controller stacked on said die paddle, said IC controller comprising a plurality of electrodes, wherein electrical connections between said plurality of pins, said plurality of electrodes on said IC controller and electrodes of said HS and said flipped LS MOSFETs are formed; wherein a bottom surface of said IC controller is stacked on and electrically insulated from said die paddle, and wherein said flipped LS MOSFET stacks and covers a portion of a top surface of said IC controller, forming electrical connection between a subset of said plurality of electrodes on said IC controller and said gate and a first portion of said source of said flipped LS MOSFET.