Patent ID: 9484100
Filing Date: 2016-11-01
CPC Classification: G11C,H01L

Claim Text:
1. A method of operating a memory device, the method comprising: biasing a data line to a first potential, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells; biasing a source to a second potential substantially the same as the first potential, where the source is coupled to a second end of the first string and to a second end of the second string of memory cells; deactivating a select gate coupled between the first end of the second string of memory cells and the data line; and performing a programming operation on a selected memory cell of the first string of memory cells concurrently with biasing the data line to the first potential and the source to the second potential and while the select gate is deactivated.