Patent ID: 9515022
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate including a memory cell region and a peripheral circuit region; a buried word line formed in the substrate in the memory cell region; a bit line structure formed in the memory cell region and including a first plug and a bit line, wherein the first plug is electrically coupled to a first impurity region in the memory cell region, wherein the bit line is provided over the first plug; a planar gate structure formed over the substrate in the peripheral circuit region; a gate air spacer including a first air gap and positioned over a sidewall of the planar gate structure; a second plug electrically coupled to a second impurity region in the memory cell region and including a first portion and a second portion, wherein the first portion is provided over a sidewall of the first plug, wherein the second portion extends from the first portion and is provided over a sidewall of the bit line; and a bit line air spacer including a second air gap and positioned between the bit line structure and the second plug.