Patent ID: 9368629
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. An integrated circuit comprising: a first source/drain region having a first conductivity type; a second source/drain region having a second conductivity type, the first conductivity type being different than the second conductivity type; a channel region interposed between the first source/drain region and the second source/drain region, the channel region having the second conductivity type, the second source/drain region having a higher dopant concentration of the second conductivity type than the channel region; a gate dielectric over the channel region, the gate dielectric having a first edge closest to the first source/drain region and a second edge closest to the second source/drain region, wherein the first edge is laterally offset from an interface between the channel region and the first source/drain region in a plan view; and a gate electrode over the gate dielectric, wherein the gate electrode and the second source/drain region are connected to a first node.