Patent ID: 9489478
Filing Date: 2016-11-08
CPC Classification: G06F

Claim Text:
1. A computer-implemented method for simplifying modes of a circuit design, the method using a computer processor to execute steps including: receiving, by the computer processor, a description of a mode of a circuit, the description comprising a netlist and timing constraints associated with the netlist, the netlist comprising timing nodes connected by timing paths, and the timing constraints comprising one or more clocks and corresponding timing exceptions associated with one or more timing paths; identifying, by the computer processor, a set of timing nodes of the circuit, each timing node in the identified set of timing nodes associated with timing paths reaching the timing node; selecting, by the computer processor, critical clock pairs, the selecting comprising, for each timing node in the identified set of timing nodes: modifying, by the computer processor, the description of the mode by eliminating one or more clocks that do not occur in the selected critical clock pairs; and performing a timing analysis of the circuit using the modified description of the mode.