Patent ID: 9331714
Filing Date: 2016-05-03
CPC Classification: H03M,H04L

Claim Text:
1. A receiver for a multi-lane data link, the receiver comprising: a plurality of physical media attachment circuits for de-serializing data from a plurality of serial lanes of the multi-lane data link, each physical media attachment circuit outputting the data at a first bus width; a plurality of gearbox circuits, each gearbox circuit receiving the data at the first bus width and outputting the data at a second bus width, wherein the first bus width is different from the second bus width; and a forward error correction (FEC) decoder for receiving and decoding the data at a third bus width, wherein the third bus width in bits is a product of the second bus width in bits and a number of the serial lanes of the multi-lane data link, and wherein the data is encoded with an FEC code having a block length, wherein the third bus width in bits is an exact multiple of a number of bits per symbol in the data, and wherein the block length in bits is an exact multiple of the third bus width.