Patent ID: 9270266
Filing Date: 2016-02-23
CPC Classification: H02M,H03K

Claim Text:
1. A high voltage switching circuit, comprising: a low voltage driving circuit having first and second capacitors; an isolated high voltage driving circuit operably coupled to the low voltage driving circuit; the isolated high voltage driving circuit having an isolated charge pump circuit and a transistor driving circuit; the isolated charge pump circuit having first, second, and third diodes, a capacitor, and a first resistor; the first diode being coupled to and between first and second electrical nodes, the second diode being coupled to and between the second electrical node and a third electrical node, the capacitor and the first resistor of the isolated charge pump circuit being electrically coupled in parallel to one another and further coupled to and between the third electrical node and a fourth electrical node; the third diode being coupled to and between the fourth electrical node and the first electrical node; the first capacitor of the low voltage driving circuit being electrically coupled to the second electrical node of the isolated charge pump circuit, and the second capacitor of the low voltage driving circuit being electrically coupled to the first electrical node of the isolated charge pump circuit; the first capacitor being adapted to receive a first pulse width modulated voltage signal, the second capacitor being adapted to receive a second pulse width modulated voltage signal which is 180 degrees out of phase with the first pulse width modulated voltage signal; the third and fourth electrical nodes of the isolated charge pump circuit being electrically coupled to the transistor driving circuit, the transistor driving circuit being further coupled to a resistive load, the transistor driving circuit being adapted to increase an output voltage of the resistive load to a desired output voltage level over a time interval in response to first and second voltage signals being applied to the third and fourth electrical nodes, respectively, when the first and second capacitors are receiving the first and second pulse width modulated voltage signals, respectively, over the time interval.