Patent ID: 9363137
Filing Date: 2016-06-07
CPC Classification: G06F,H04L

Claim Text:
1. A redundant routing system for a processor array, comprising: multiple switches for routing packets between multiple core circuits of the processor array, wherein the multiple switches are organized into multiple blocks, each switch corresponds to at least one core circuit of the multiple core circuits, and each block includes at least one redundant switch for recovering a failed switch and at least one redundant core circuit for recovering a failed core circuit; and multiple data paths interconnecting the multiple switches, wherein the multiple data paths include at least one redundant data path interconnecting a pair of non-adjacent switches in a same block to bypass a component failure in the same block, and the multiple data paths further include at least one diagonal data path interconnecting a pair of diagonally adjacent switches in different blocks to propagate packets between the different blocks; wherein each bypassed component failure is recovered using at least one of a redundant switch and a redundant core circuit included in at least one of the multiple blocks.