Patent ID: 9300285
Filing Date: 2016-03-29
CPC Classification: H01L,H03K

Claim Text:
1. A gate driver circuit, comprising: a driving signal generating unit configured to generate first and second control signals based on a data signal and a fault state signal and control gate detection; a driving inverter configured to operate in response to the first and second control signals to generate a gate signal and provide the gate signal to a power switch element; and a soft turn-off/gate detecting unit configured to operate in response to the second control signal, perform a soft turn-off in the case of a fault, and detect the gate signal to provide a detected signal; wherein the first control signal has a level into which the data signal is inverted when the fault state signal is at the low level and has a level into which the fault state signal is inverted regardless of a level of the data signal when the fault state signal is at the high level, wherein the second control signal has a same level as the first control signal when the fault state signal is at the low level and has a level of the fault state signal regardless of the level of the first control signal when the fault state signal is at the high level.