Patent ID: 9236131
Filing Date: 2016-01-12
CPC Classification: G11C,H01L

Claim Text:
1. A method for controlling a memory device, comprising: applying a voltage to a remaining portion of a select gate layer in a stacked three-dimensional memory structure, the stacked three-dimensional memory structure comprising alternating conductive layers and dielectric layers, the select gate layer is one of the conductive layers and comprises parallel select gate lines, the remaining portion of the select gate layer extends transversely to the parallel select gate lines and is separated from the parallel select gate lines by an end trench at one end the of parallel select gate lines, the parallel select gate lines are separated from one another by side trenches, the end trench is connected to the side trenches, an oxide is provided in the end trench and an oxide is provided in the side trenches; detecting a short circuit path in the oxide in the end trench during the applying the voltage; determining a voltage level for counteracting the short circuit path; and biasing the remaining portion of the select gate layer during an operation in the stacked three-dimensional memory structure using the voltage level for counteracting the short circuit path.