Patent ID: 9391172
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A method of forming a transistor, the method comprising: forming a fin portion protruding upward from a substrate; forming a device isolation pattern on the substrate to cover a sidewall of the fin portion; forming a trench in the device isolation pattern, the trench exposing a top surface and sidewalls of a channel region of the fin portion; and recessing the channel region to form a first recessed channel region of which a top surface is lower than top surfaces of source/drain regions at both sides of the fin portion; and injecting a Group-IV element into the first recessed channel region of the fin portion to form a second recessed channel region, wherein a volume of the second recessed channel region of the fin portion is larger than a volume of the first recessed channel region, wherein a top surface of the second recessed channel region of the fin portion is lower than top surfaces of source/drain regions of the fin portion.