Patent ID: 9331196
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a first conductive type epitaxial layer, disposed on a second conductive type substrate; a high voltage second conductive type well, disposed within the first conductive type epitaxial layer; a first conductive type buried layer, disposed within the first conductive type epitaxial layer and below the high voltage second conductive type well; a source region, disposed within the high voltage second conductive type well; a linear graded high voltage first conductive type well, disposed within the first conductive type epitaxial layer, wherein the linear graded high voltage first conductive type well is a doped region having a lateral linear doping profile that has a doping concentration gradually increases from a location nearest the first conductive type buried layer to a location farther from the first conductive type buried layer, and a length of the first conductive type buried layer is smaller than a length of the high voltage second conductive type well, wherein one side of the first conductive type buried layer is pulled back with a pull-back length, such that the first conductive type buried layer is spaced away from the linear graded high voltage first conductive type well for the pull-back length; a drain region, disposed within the linear graded high voltage first conductive type well; and a gate structure, disposed above the first conductive type epitaxial layer and disposed between the source region and the drain region.