Patent ID: 9472542
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A DRAM array layout, comprising: wordlines extending along a first direction; bitlines extending along a second direction that crosses the first direction; cell active material structures at intersections of the wordlines and bitlines, the cell active material structures being substantially parallelograms having a first side coupled to a bitline and a second side coupled to a charge storage device; the second side being on an opposite side of a wordline passing through an individual cell active material structure relative to the first side; each cell active material structure having a connection to a bitline which is not shared with any other cell active material structures; wherein the wordline passing through the individual cell active material structure is a primary wordline relative to the individual cell active material structure; wherein the second side of the individual cell active material structure comprises a region proximate a wordline adjacent the primary wordline; and each of the substantial parallelograms of the cell active material structures having four corners; two of said four corners being overlapped by the primary wordlines passing through the cell active material structures and being sharp corners; third corners of each of the substantial parallelograms of the cell active material structures being on the second sides of the cell active material structures and being rounded relative to said two of the four corners of each of the substantial parallelograms of the cell active material structures.