Patent ID: 9318482
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a well on a substrate; a first impurity region on the well, connected to an input/output pad; a second impurity region on the well, spaced apart from the first impurity region, and connected to a ground (Vss); a third impurity region on the well, spaced apart from the first impurity region, and connected to the ground (Vss); an isolation layer between the first impurity region and the second impurity region; and a high-resistance region between the first impurity region and the isolation layer, configured to directly contact the first impurity region and the well, and having a resistance higher than that of the first impurity region, wherein the well and the third impurity region include first conductive type impurities, and the first impurity region and the second impurity region include second conductive type impurities different from the first conductive type impurities, and wherein the high-resistance region comprises the second conductive type impurities.