Patent ID: 9250831
Filing Date: 2016-02-02
CPC Classification: G06F,Y02D

Claim Text:
1. A massively parallel and memory centric computing system, the system comprising: a plurality of processing units operably coupled to each other through one or more communication channels, each of the plurality of processing units having an ISMn (Isolated Shared Memory network) interface device, each of the plurality of ISMn interface devices being coupled to an ISMe (Isolated Shared Memory endpoint) devices connected to each of the processing units; a plurality of DRAM or Flash memories configured in a disaggregated architecture; one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture; and a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.