Patent ID: 9484105
Filing Date: 2016-11-01
CPC Classification: G11C,H01L

Claim Text:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string being commonly connected to a wiring, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor; a word line connected to both a gate of the first memory cell and a gate of the second memory cell; a first line connected to a gate of the first transistor; a second line connected to a gate of the second transistor; and a control circuit configured to perform an erase operation on a condition that a first voltage is applied to the wiring, a second voltage is applied to the first line, and a third voltage is applied to the second line in a first period, and a fourth voltage is applied to the wiring, a fifth voltage is applied to the first line, and a sixth voltage is applied to the second line in a second period after the first period, and a seventh voltage is applied to the word line in the first and the second period, the first voltage being higher than the seventh voltage and lower than the fourth voltage, the second voltage being higher than the seventh voltage and lower than the fifth voltage, the third voltage being higher than the seventh and lower than sixth voltage, the fifth voltage being lower than the fourth voltage, the fourth voltage being substantially same as the sixth voltage.