Patent ID: 9305646
Filing Date: 2016-04-05
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device, comprising a memory cell and a control circuit, the memory cell including: a first electrode; a first resistance varying layer formed on the first electrode; a second resistance varying layer formed on the first resistance varying layer and having a resistance value which is smaller than that of the first resistance varying layer; a third resistance varying layer formed on the second resistance varying layer and having a resistance value which is larger than that of the second resistance varying layer; and a second electrode formed on the third resistance varying layer, and the control circuit applying to the memory cell a first voltage pulse, and then applying to the memory cell a second voltage pulse that has a polarity which is identical to that of the first voltage pulse and that has a rise time which is shorter than that of the first voltage pulse, thereby performing write of data to the memory cell.