Patent ID: 9502521
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method of forming a gate stack on a semiconductor substrate having a channel, the method comprising: depositing a tunnel layer over the channel, wherein the tunnel layer comprises at least one silicon nitride compound having a chemical formula of Si depositing a charge trapping layer comprising a compound including silicon and nitrogen on top of the tunnel layer, the charge trapping layer comprising at least a first trapping sub-layer and a second trapping sub-layer, the first trapping sub-layer adjacent to the tunnel layer, the first trapping sub-layer having a first composition engineered to provide a low charge trap density to increase retention of information, the first composition comprising a nitrogen-rich silicon nitride compound and oxygen, the first composition having about the same as or more nitrogen on an atomic percentage basis than is present in stoichiometric silicon nitride, the silicon nitride compound present in the range of about 50% to less than 100% on an atomic percentage basis and oxygen present in the range of greater than 0% to about 50% on an atomic percentage basis, the second trapping sub-layer comprising a silicon-rich silicon nitride compound containing more silicon on an atomic percentage basis than is present in stoichiometric silicon nitride; forming an interface region on the charge trapping layer, the interface region comprising a discrete layer with a compound including silicon, nitrogen and a charge blocking component selected from the group consisting of Al, Mg, Sr, Ba, Ti, Ta, Zr, Hf, Y, La and combinations thereof; depositing a charge blocking layer on top of the interface region, the charge blocking layer containing an oxide of the charge blocking component included in the interface region; and placing a control gate on top of the charge blocking layer.