Patent ID: 9437261
Filing Date: 2016-09-06
CPC Classification: G06F,G11C

Claim Text:
1. A memory controller comprising: a first variable delay circuit that delays a data strobe signal received from a memory; a second variable delay circuit that delays a data signal which is received from the memory and is synchronous with the data strobe signal; a first data signal latch circuit that latches a delay data signal, which is delayed by the second variable delay circuit, in response to an internal clock; a phase comparator that generates a first variable delay setting value corresponding to a first delay amount of the first variable delay circuit such that a phase difference between the data strobe signal and the internal clock is reduced, and sets the first variable delay setting value to the first variable delay circuit; and an adder that adds to the first variable delay setting value an offset value such that a setup margin and a hold margin of the first data signal latch circuit are corrected, to generate a second variable delay setting value corresponding to a second delay amount of the second variable delay circuit, and sets the second variable delay setting value to the second variable delay circuit.