Patent ID: 9293211
Filing Date: 2016-03-22
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: a memory cell; a page buffer including a first and a second switching devices coupled in common to a sensing node coupled to the memory cell through a bit line and a first and a second sensing latch units coupled to the sensing node, respectively, through the first and second switching devices; and a control logic suitable for transferring a first and a second sensing signals, respectively, to the first and second switching devices when a threshold voltage of the memory cell is reflected on the sensing node through the bit line during a verification operation, the first and second sensing signals having different voltage levels, wherein each of the first and second switching devices is turned on or off according to a voltage of the sensing node and a voltage of a corresponding sensing signal such that the voltage of the sensing node is transferred to the first and second sensing latch units through the first and second switching devices as data bits.