Patent ID: 9519479
Filing Date: 2016-12-13
CPC Classification: G06F

Claim Text:
1. A method of vector lane predication for a processor, comprising the steps of: fetching predicated vector instructions from a memory; decoding the predicated vector instructions; determining if a mask value of the predicated vector instructions is available and, if the mask value of the predicated vector instructions is not available, predicting the mask value of the predicated vector instructions; dispatching the predicated vector instructions to only masked vector lanes; and dispatching non-conflicting instructions to only unmasked vector lanes at a same time as the predicated vector instructions are dispatched to the masked vector lanes, wherein decrementing a safeguard counter each time it is determined that the mask value of the predicated vector instructions that is predicted is incorrect, wherein the safeguard counter is set at a dynamic maximum tolerance level that includes a maximum bound of incorrect predictions that will be tolerated by taking into account a performance improvement of the processor device by the correct prediction of the mask value and also taking into account a performance penalty of the processor device by the incorrect prediction of the mask value; and reverting to a baseline process when the safeguard counter reaches zero which dispatches a same predicated vector instruction to all lanes until the mask value is known.