Patent ID: 9330018
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. A method for managing address translations in a multi-processor computer system, the method comprising: in response to detecting a hit in a translation lookaside buffer of a processor unit for a virtual address corresponding to an instruction, determining whether an entry corresponding to the hit will be purged from the translation lookaside buffer based, at least in part, on an indication of a change to a page table, updating a first register in response to the indication of a change to the page table; copying content of the first register to a second register in response to the update to the first register determining whether the instruction entered an instruction pipeline of the processor unit after the processor unit received the indication of the change to the page table allowing the hit in the translation lookaside buffer in response to determining that the instruction entered the pipeline before the processor unit received the indication of the change to the page table; suppressing the hit in the translation lookaside buffer, by forming new translation lookaside buffer entries in response to determining that the instruction entered the pipeline after the processor unit received the indication of the change to the page table, wherein the new translation lookaside buffer entries are formed without purging the translation lookaside buffer, blocking access to the page table for address translation of the virtual address for the instruction into a physical address after suppressing the hit and in response to determining that the entry will be purged based, at least in part, on indication of the change to the page table, and allowing access to the page table for address translation of the virtual address for the instruction into a physical address after suppressing the hit and in response to determining that the entry will not be purged based, at least in part, on the indication of the change to the page table.