Patent ID: 9378019
Filing Date: 2016-06-28
CPC Classification: G06F

Claim Text:
1. A microprocessor having an instruction set architecture that defines a conditional load instruction, the microprocessor comprising: a register file; an instruction translator, that translates the conditional load instruction into at least two microinstructions, wherein the conditional load instruction specifies a destination register and source registers of the register file; and an out-of-order execution pipeline, comprising a plurality of execution units that execute the microinstructions; wherein to execute a first of the microinstructions, one of the execution units receives source operands from the source registers of the register file, and in response generates a first result using the source operands; wherein to execute a second of the microinstructions, one of the execution units receives a previous value of the destination register and the first result, and in response reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not; wherein the previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.