Patent ID: 9405622
Filing Date: 2016-08-02
CPC Classification: G06F,G11C

Claim Text:
1. An apparatus, comprising: an error correction encoder configured to add error correction data to a received digit pattern; a shaping encoder coupled to the error correction encoder and configured to encode the received digit pattern and to encode the added error correction data in accordance with a mapping of digit patterns to shaping digit patterns; wherein the mapping of digit patterns to shaping digit patterns obeys a shaping constraint that limits, to an uppermost quantity, a quantity of consecutive digits of the shaping digit patterns allowed to have a particular digit value; wherein each one of the digit patterns corresponding to the mapping comprises fewer digits than a particular shaping digit pattern to which the respective digit pattern is mapped; and wherein the shaping encoder is configured to encode the received digit pattern and encode the added error correction data in accordance with the mapping of digit patterns to shaping digit patterns only when the received digit pattern is to be programmed to a group of memory cells as a lower page of data.