Patent ID: 9275704
Filing Date: 2016-03-01
CPC Classification: G06F,G11C

Claim Text:
1. An asynchronous FIFO (first-in-first-out) circuit comprising: a data memory coupled to a write data path and a read data path, the data memory configured to receive a write clock and a read clock; a FIFO write pointer counter configured to receive a write enable signal and the write clock, the FIFO write pointer counter configured to provide a FIFO write pointer signal to the data memory, a FIFO read pointer counter configured to receive a read enable signal and the read clock, the FIFO read pointer counter configured to provide a FIFO read pointer signal to the data memory; and a control circuit configured to receive the write enable signal, the read enable signal, the FIFO write pointer signal, the FIFO read pointer signal, the write clock and the read clock, the control circuit configured to generate a memory full signal when the data memory is full and a memory empty signal when the data memory is empty.