Patent ID: 9449662
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A semiconductor memory apparatus comprising: a command decoder configured to decode an external command and output the decoded command as an internal command; a command transmitter configured to determine a delay time in response to a voltage level of an external voltage being applied to the semiconductor memory apparatus, delay the internal command by the determined delay time, and output the delayed internal command as a delayed command; and a data storage area configured to receive the delayed command, and perform an operation according to the delayed command, wherein the command transmitter comprises: a delay control unit configured to generate a plurality of delay control signals in response to the voltage level of the external voltage; and a variable delay unit configured to determine a delay time in response to the plurality of delay control signals, delay the internal command by the determined delay time, and output the delayed internal command as the delayed command, wherein the delay control unit comprises: a divided voltage generation unit configured to generate a plurality of divided voltages by dividing the external voltage; a comparison signal generation unit configured to generate a plurality of comparison signals by comparing the plurality of divided voltages to a voltage level of a reference voltage, respectively; and a decoding unit configured to enable one of the plurality of delay control signals in response to the plurality of comparison signals.