Patent ID: 9419095
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a dummy gate in a gate-last process, comprising: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon, α-Si, on the gate oxide layer; depositing an oxide-nitride-oxide, ONO, structured hard mask on the bottom-layer α-Si; depositing top-layer α-Si on the ONO structured hard mask; depositing a hard mask layer on the top-layer α-Si; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines; etching the hard mask layer by using the trimmed photoresist lines as a mask for the hard mask layer, and removing the photoresist lines; etching the top-layer α-Si by using the hard mask layer as a mask for the top-layer α-Si; etching the ONO structured hard mask by using the hard mask layer and the top-layer α-Si as a mask for the ONO structured hard mask, and removing the hard mask layer before etching the bottom-layer α-Si; and etching the bottom-layer α-Si by using the top-layer α-Si and the ONO structured hard mask as a mask for the bottom-layer α-Si, and removing the top-layer α-Si.