Patent ID: 9411739
Filing Date: 2016-08-09
CPC Classification: G06F

Claim Text:
1. An apparatus comprising: logic to assign a transactional memory (TM) region indicator to each instruction of a transaction; execution logic to execute each instruction of the transaction; a copy-on-write (COW) buffer to maintain a mapping from checkpointed architectural registers to physical registers, wherein the COW buffer to maintain a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions using pointers, a first pointer to identify a position in the COW buffer of the last committed instruction, a retirement pointer to identify a boundary between a youngest TM region and a currently retiring instruction position; a data cache to store data associated with executed instructions, wherein each entry of the data cache has a read-bit per TM region indicator to mark memory state of speculative reads wherein a read-bit for a TM region is set when data is speculatively read from that cache line during that transaction and a write-bit to indicate when the cache line has speculatively written data.