Patent ID: 9405161
Filing Date: 2016-08-02
CPC Classification: G02F,G09G

Claim Text:
1. A liquid crystal (LC) array substrate, comprising a plurality of pixel regions, each pixel region comprises a main region, a sub-region, and an adjustment thin film transistor (TFT), the adjustment TFT is configured to adjust a ratio of voltage of the main region and the sub-region to achieve a LCS design; wherein, the main region comprises a first TFT and a main region array common electrode lead wire, the sub-region comprises a second TFT and a sub-region array common electrode lead wire, and the main region array common electrode lead wire and the sub-region array common electrode lead wire are electrically isolated; a gate of the first TFT is connected to a first scan line, a source of the first TFT is connected to a data line, a drain of the first TFT is connected to one pixel electrode and is coupled to the main region array common electrode lead wire; a gate of the second TFT is connected to the first scan line, a source of the second TFT is connected to the data line, a drain of the second TFT is connected to one pixel electrode and is coupled to the sub-region array common electrode lead wire; a source of the adjustment TFT is coupled to the drain of the first TFT, a drain of the adjustment TFT is electrically connected to the drain of the second TFT, a gate of the adjustment TFT is connected to a second scan line: the main region array common electrode lead wire of all pixel regions of the LC array substrate are connected to a main region conductive pad, the sub-region array common electrode lead wire of all pixel regions of the LC array substrate are connected to a sub-region conductive pad, wherein a sharing capacitor is connected between the pixel electrode of the drain of the first TFT and the source of the adjustment TFT, a coupling capacitor is connected between the main region array common electrode lead wire of the main region and the source of the adjustment TFT, the sharing capacitor and the coupling capacitor are arranged in parallel to each other.