Patent ID: 9502425
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate; a device isolation layer on the substrate; a fin-type active pattern defined by the device isolation layer, the fin-type active pattern extending lengthwise in a first direction, the fin-type active pattern having a first edge portion, a center portion, and a second edge portion opposite the first edge portion, wherein the first edge portion, center portion, and second edge portion are arranged sequentially in the first direction, and the fin-type active pattern having a top surface higher than a top surface of the device isolation layer; a first conductive line on the first edge portion of the fin-type active pattern and on the device isolation layer adjacent to the first edge portion of the fin-type active pattern; and an insulating thin layer between the fin-type active pattern and the first conductive line, wherein the first conductive line forms a gate electrode of an anti-fuse to which a write voltage is applied, and wherein the first conductive line covers at least a first point corner portion of the fin-type active pattern.