Patent ID: 9515662
Filing Date: 2016-12-06
CPC Classification: H03K

Claim Text:
1. A level shifter comprising: a first and a second transistor coupled to a first power supply voltage terminal supplied with a second power supply voltage in parallel, the first transistor including a first gate connected to a drain of the second transistor and a first gate insulating film, and the second transistor including a second gate connected to a drain of the first transistor and a second gate insulating film; a third and a fourth transistor coupled to a reference voltage terminal in parallel, the third transistor including a third gate supplied with a first control signal and a third gate insulating film, and the fourth transistor including a fourth gate supplied with a second control signal and a fourth gate insulating film; a first and a second depression transistor, the first depression transistor being coupled between the first and the third transistor and including a fifth gate supplied with a third control signal and a fifth gate insulating film, the second depression transistor being coupled between the second and the fourth transistor and including a sixth gate supplied with a fourth control signal and a sixth gate insulating film; and a timing control unit placed between a second power supply voltage terminal supplied with a second power supply voltage lower than the first power supply voltage and the reference voltage terminal, that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non-inverted signal of the input signal, wherein the third and the fourth gate insulating film is thinner than the first, the second, the fifth and the sixth gate insulating film.