Patent ID: 9514258
Filing Date: 2016-12-06
CPC Classification: G06F

Claim Text:
1. A computer-implemented method for generating a memory structural model of a memory instance, the method comprising: receiving memory layout information of the memory instance; receiving configuration information of the memory instance, the configuration information not including address scrambling information; determining physical bit patterns for the memory structural model based at least on a number of row and a number of column of the memory instance as described in the configuration information; programming each of the physical bit patterns into a memory layout of the memory instance as defined by the memory layout information by applying each of the physical bit patterns to the memory layout; performing simulation of operation of the memory instance applied with the physical bit patterns; extracting a logical bit pattern corresponding to each of the physical bit patterns based on the simulation; at a computing device, analyzing each of the physical bit patterns and the extracted logical bit pattern and generating address scrambling information of the memory instance based on said analysis; generating strap information based on parameters in the configuration information and the memory layout information, wherein the strap information indicates locations and sizes of vertical and horizontal straps in the memory instance; and generating the memory structural model by combining the strap information and the address scrambling information.