Patent ID: 9407574
Filing Date: 2016-08-02
CPC Classification: G06F,H04L,H04Q

Claim Text:
1. A signal processing apparatus comprising bidirectional high speed ports connected via an integrated high speed serial switch fabric and serializer/de-serializer circuits to an internal processing logic, wherein said high speed serial switch fabric is adapted to switch a serial reception signal received by a high speed port to at least one other high speed port of said apparatus in addition to connections with a parallel domain of said high speed ports, and wherein each bidirectional high speed port comprises at least one internal loopback signal path provided to loop a signal received by its reception port directly back to its transmission port in response to an internal control signal repurposed for use as a low latency functional path, wherein the reception port of each bidirectional high speed port comprises a clock and data recovery circuit receiving the serial reception signal and supplying the respective serializer/de-serializer circuit of said bidirectional high speed port with a recovered clock signal and with a recovered serial reception signal, wherein each bidirectional high speed port comprises a pre-CDR loopback signal path and a post-CDR loopback signal path either of which can be repurposed as a low latency functional path.