Patent ID: 9507952
Filing Date: 2016-11-29
CPC Classification: G06F

Claim Text:
1. A processor comprising: a plurality of cores; a first interconnect to couple a first core of the plurality of cores to an interface; a protocol engine to format information from the first core into one or more packets; a link controller to communicate the one or more packets to at least a second processor of a plurality of second processors; and a logic to perform a secure enter instruction for a platform including a first plurality of processors including the processor and the plurality of second processors, the processor corresponding to an initiating logical processor and the second processor corresponding to a responding logical processor, wherein the logic is to send a message responsive to the secure enter instruction to the plurality of second processors, receive an acknowledgement of the message from the plurality of second processors, after receipt of the acknowledgement compute a hash of an authenticated code module to be launched on the first plurality of processors, authenticate the authenticated code module, store the hash of the authenticated code module in a trusted platform module of the platform, and thereafter execute the authenticated code module.