Patent ID: 9479113
Filing Date: 2016-10-25
CPC Classification: G06F,H03B,H03C,H04B

Claim Text:
1. A clock signal generating circuit, comprising: a first oscillator configured to have a trimming function of arbitrarily adjusting an oscillation frequency of a first clock signal generated by the first oscillator depending on trimming data; a trimming data modulation part configured to dynamically change a reference trimming data for adjusting the oscillation frequency of the first clock signal to generate modulation trimming data, and output the modulation trimming data, as the trimming data, to the first oscillator, a second oscillator configured to generate a second clock signal having a fixed oscillation frequency; and a counter configured to count the number of pulses of the second clock signal to output a counter value, wherein the trimming data modulation part is further configured to switch a data value of the modulation trimming data at a frequency change timing based on the counter value; and wherein the second oscillator is further configured to have a trimming function for arbitrarily adjusting an oscillation frequency of the second clock signal generated by the second oscillator itself, depending on the reference trimming data.