Patent ID: 9484441
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method for fabricating a transistor, comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate to cover the substrate and the gate electrode; forming a patterned channel layer and a hard-mask layer on the gate insulating layer, wherein the patterned channel layer and the hard-mask layer are disposed above the gate electrode, and the hard-mask layer is located on the patterned channel layer; and forming a source and a drain on the gate insulating layer by a wet etchant and removing part of the hard-mask layer that is not covered by the source and the drain by the wet etchant until the patterned channel layer is exposed, so as to form a plurality of patterned hard-mask layers, wherein a material of the patterned hard-mask layer is the same as a material of the source and the drain.