Patent ID: 9312253
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device comprising: providing a first chip having a first terminals; providing a second chip having second terminals; providing a third chip having third terminals; providing a first silicon interposer having first through silicon vias TSVs; providing a second silicon interposer having second TSVs; arraying the first TSVs in a first, a second, and a third set, wherein the first set is located in a first interposer region and matching the first terminals, the second set is located in a second interposer region and matching the second terminals, and the third set is located in a third interposer region between the first and second regions and matching the TSVs of the second interposer and the third terminals; aligning the first chip with the first set TSVs, the second chip with the second set TSVs, and the second interposer with the third set TSVs; giving the first silicon interposer a characteristic of a three-dimensional (3D) interposer by stacking the second silicon interposer on top of the first silicon interposer; and using a solder of a first melting temperature.