Patent ID: 9425051
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A fabrication method of a field effect transistor successively comprising: providing a substrate provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface, depositing a continuous silicon-germanium layer on the first semiconducting area and on the first masking pattern, in non-selective manner, the continuous silicon-germanium layer completely covering the first semiconducting area and the first masking pattern, so as to form an interface between the continuous silicon-germanium layer and the first semiconducting area, applying a diffusion annealing configured to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area, depositing an electrically insulating layer so as to cover the masking pattern and source and drain areas, wherein the masking pattern is a gate stack of the field effect transistor or is used to define a shape of a gate stack in the electrically insulating layer so as to form said gate stack which is self-aligned with the source and drain areas and to form germanium-enriched source and drain areas when diffusion annealing is performed.