Patent ID: 9502496
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: providing a main drain region which is a first conduction type and is formed on a first main surface of a semiconductor substrate of the first conduction type; providing a vertical trench MOS gate-type semiconductor element portion including a base region that is a second conduction type and is selectively formed on a second main surface of the semiconductor substrate, a main source region that is the first conduction type and is selectively formed on a surface of the base region, a trench that extends from a surface of the base region to the semiconductor substrate through the base region and the main source region, and a trench MOS gate that includes a gate electrode provided in the trench with a first insulating film, which is an insulating film, interposed therebetween; providing a semiconductor element portion for control that is adjacent to the vertical trench MOS gate-type semiconductor element portion, with an element isolation region including a second insulating film which is formed on the second main surface of the semiconductor substrate and is thicker than the first insulating film interposed therebetween, includes a well diffusion region which is the second conduction type and forms a pn junction with the semiconductor substrate on the second main surface of the semiconductor substrate, a gate electrode for control which is formed on a surface of the well diffusion region with a third insulating film which is thinner than the second insulating film interposed therebetween, and a control drain region of the first conduction type and a control source region of the first conduction type which are provided on the surface of the well diffusion region with the control gate electrode interposed between, and controls the vertical trench MOS gate-type semiconductor element portion; providing a junction edge termination region that includes the second insulating film provided on the second main surface of the semiconductor substrate and surrounds the vertical trench MOS gate-type semiconductor element portion or both the vertical trench MOS gate-type semiconductor element portion and the semiconductor element portion for control, wherein the junction edge termination region includes the second insulating film, a sustain region which is the second conduction type and comes into contact with the trench at an outer circumferential end of the vertical trench MOS gate-type semiconductor element portion, and a first region which is the second conduction type and is provided so as to come into contact with an outside of the sustain region, the first region has a junction depth greater than that of the base region and has low impurity concentration, the sustain region has a junction depth less than that of the first region and has high impurity concentration, the well diffusion region has a junction depth greater than those of the base region and the sustain region and has low impurity concentration, and an avalanche breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench MOS gate-type semiconductor element portion; and forming the first region and the well diffusion region included in the semiconductor device at a same time.