Patent ID: 9324631
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a metallization system positioned above a substrate, said metallization system comprising a plurality of metallization layers, at least some of said metallization layers comprising a low-k dielectric material; a copper-containing contact pad positioned in a last metallization layer of said metallization system, wherein an upper surface of said copper-containing contact pad is substantially co-planar with an upper surface of said last metallization layer; a passivation layer positioned above said last metallization layer, said passivation layer covering a portion of said upper surface of said copper-containing contact pad; a stress buffer layer positioned above said passivation layer, said stress buffer layer comprising a copper-containing buffer region having a contact portion that is embedded in said passivation layer and connects to said copper-containing contact pad; a lead-free contact element positioned on a portion of said copper-containing buffer region, wherein a portion of said lead free contact element is embedded in said copper-containing buffer region and a lateral width of said buffer region is greater than a lateral width of said lead-free contact element; and a package substrate connected to said metallization system via said lead-free contact element.