Patent ID: 9412504
Filing Date: 2016-08-09
CPC Classification: G11C,H01C,H01L

Claim Text:
1. An electrically adjustable memory effect resistor comprising: a stack comprising: a means for controlling the electrical voltage between the first layer of superconductive material and the third layer of conductive material, generating an electric field allowing the polarization direction of the ferroelectric second material to be modified when the electrical control voltage is higher than a threshold voltage value; the stack further comprises a fourth layer comprising at least one electrically insulating fourth material, the fourth layer being placed between the second layer of ferroelectric material and the third layer of conductive material, the thickness of the electrically insulating fourth layer varying in a direction parallel to the axis x and/or the fourth layer comprises a succession of materials of different dielectric constants in a direction parallel to the axis, so as to cause a variation in the electric field applied between the first layer and the third layer, the adjustable resistor being configured to operate over an interval of temperatures in which the difference between the electrical resistance of the over-doped state and the under-doped state of the first material is nonzero.