Patent ID: 9330220
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. A method, comprising: creating, using a processor, partitions for a plurality of clocks of a circuit design for an integrated circuit; wherein the integrated circuit comprises clock regions organized in a grid and wherein a selected partition comprises a plurality of the clock regions including a congested clock region comprising a number of assigned clocks exceeding a capacity of the congested clock region; legalizing the selected partition using the processor by resizing the selected partition to exclude the congested clock region and relocating a clock source and clock loads of the clock source of the selected partition out of the congested clock region and into the resized partition; selecting roots for implementing clock trees of the clocks within the partitions; and routing the plurality of clocks by assigning clock distribution tracks to the plurality of clocks according to the roots.