Patent ID: 9298420
Filing Date: 2016-03-29
CPC Classification: G06F

Claim Text:
1. A method in a circuit for identifying one or more bit positions of instances of a selected bit value in an input bit string, the method comprising: a plurality of adders computing, in parallel, sums of bits in each of the P input substrings of an N-bit input bit string; for each of the P input substrings for which the sum differs from a threshold sum, detecting, by a plurality of zero position detectors, one or more bit positions of the selected bit value; generating, utilizing correction logic, adjustment indications indicative of a number of detected instances of the selected bit value; and based on the detected bit positions and the adjustment indications, outputting, by a plurality of output substring adjusters, one or more output vectors identifying a bit position of at least an Mth instance of the selected bit value in the input bit string.