Patent ID: 9489879
Filing Date: 2016-11-08
CPC Classification: G09G,G11C

Claim Text:
1. A display device comprising: a plurality of pixels including a pixel transistor respectively, a plurality of scanning signal lines supplying a scanning signal to the plurality of pixels respectively, a driving circuit sequentially applying the scanning signal to the plurality of scanning lines, and four clock signal lines including a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, wherein the scanning signal has an active potential which is able to turn on a pixel transistor and the non-active potential which is able to turn off the pixel transistor, wherein the plurality of scanning signal lines are arranged in order of a first scanning signal line, a second scanning signal line and a third scanning signal line, wherein the driving circuit comprises a first output circuit configured to output the active potential to the first scanning signal line, wherein four clock signal lines become the active potential in order of the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line, wherein a period of the active potential of four clock signal lines are not overlapped each other, wherein the first output circuit comprises a first output transistor, the first output transistor has a gate, a source and a drain, the gate of the first output transistor is connected to a first node, one of the source and the drain of the first output transistor is connected to the first scanning signal line for outputting the active potential to the first scanning signal line and the other of the source and the drain is connected to the second clock signal line, and when the first node is the active potential, the first output transistor outputs the second clock signal to the first scanning signal line; wherein the first output circuit further comprises a first reset transistor, the first reset transistor provides the non-active potential to the gate of the first output transistor when the fourth clock signal becomes the active potential, wherein the first reset transistor has a gate which directly connects to the fourth clock signal line; and wherein the first output circuit further comprises a second output transistor, the second output transistor has a gate, a source and a drain, the gate of the second output transistor is connected to the fourth clock signal line, one of the source and the drain of the second output transistor is connected to the first scanning signal line for outputting the non-active potential to the first scanning signal line and the other of the source and the drain is connected to a non-active potential line, and when the fourth clock signal becomes the active potential, the second output transistor outputs the non-active potential to the first scanning signal line.