Patent ID: 9362170
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a semiconductor material portion including a doped semiconductor region on a substrate; forming a conductive material portion above said semiconductor material portion; forming at least one dielectric material layer over said semiconductor material portion; forming a first contact via structure through said at least one dielectric material layer, said first contact via structure being electrically shorted to said doped semiconductor region; forming a cavity overlying said conductive material portion through said at least one dielectric material layer, wherein an outer sidewall of said first contact via structure is physically exposed within said cavity after formation of said cavity; forming a dielectric spacer on sidewalls of said cavity, wherein said dielectric spacer is formed by: depositing a dielectric liner on a bottom surface and sidewalls of said cavity and on a top surface of said at least one dielectric material layer; and anisotropically etching said dielectric liner, wherein a remaining portion of said dielectric liner is said dielectric spacer; and forming a second contact via structure in said cavity and directly on said conductive material portion.