Patent ID: 9424126
Filing Date: 2016-08-23
CPC Classification: G06F

Claim Text:
1. A memory controller that controls a non-volatile memory, the memory controller comprising: an encoder configured to sequentially receive data, and to sequentially calculate parity based on the data, a buffer configured to store the parity calculated by the encoder, the parity stored in the buffer including at least one of completed parity calculated based on the data having predetermined size and intermediate parity calculated based on the data having a size less than the predetermined size; a write processing unit configured to write the data output from the encoder and the completed parity read from the buffer to a non-volatile memory; a decoder configured to perform a decoding process based on the data and the completed parity read from the non-volatile memory; and a controller configured to control the decoder to perform decoding based on the data read from the non-volatile memory and the intermediate parity stored in the buffer when receiving a read request directing to the data for which the intermediate parity in the buffer being generated.