Patent ID: 9305945
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A TFT array substrate, comprising: a plurality of gate lines and a plurality of data lines formed on a substrate, wherein the gate lines and the data lines intersect with each other to define a plurality of pixel units, and each of the pixel units comprises a TFT and a pixel electrode, and wherein the TFT comprises: a gate electrode formed on the substrate; a gate insulating layer and a passivation layer formed in this order on the substrate and covering the gate electrode; a drain electrode formed on the passivation layer; a first ohmic contact layer pattern formed on the drain electrode; a semiconductor layer formed on both of the first ohmic contact layer pattern and the passivation layer; a second ohmic contact layer pattern formed on the semiconductor layer and separated from the drain electrode and the first ohmic contact layer pattern; and a source electrode formed on the second ohmic contact layer pattern.