Patent ID: 9472286
Filing Date: 2016-10-18
CPC Classification: G11C,H01L

Claim Text:
1. A memory device, comprising: a plurality of stacks of conductive strips alternating with insulating strips, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips; a plurality of vertical structures arranged orthogonally to the plurality of stacks; memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of vertical structures; a stack of linking elements separated by insulating layers, and connected to conductive strips in respective intermediate planes in the plurality of intermediate planes; a plurality of pairs of interlayer connectors extending from a connector surface, wherein each pair of interlayer connectors includes first and second interlayer connectors connected to a single linking element in the stack of linking elements; and decoding circuitry coupled to the plurality of intermediate planes, and configured to address a respective conductive strip connected to the single linking element via the first and second interlayer connectors in the pair of interlayer connectors.