Patent ID: 9465730
Filing Date: 2016-10-11
CPC Classification: G06F

Claim Text:
1. A flash memory device, comprising: a flash memory including a data region that stores data; and a memory controller that forms a plurality of blocks, including a first block and a second block, in the data region of the flash memory, wherein the memory controller writes to the first block an updated value of the data and a first block management value indicating whether the first block is in a used state, when the first block is in an unused state, the memory controller writes the updated value of the data and the first block management value to the first block, sequentially recognizes updated values of the data, and writes an updated value of the updated values to the first block when each of the updated values is recognized, when the first block becomes full, the memory controller copies the updated value, which is written at the end of the updated values written to the first block, from the first block to the second block and writes a second block management value to the second block, the memory controller sets and writes a plurality of different block management values, including the first and second block management values, respectively, to the plurality of blocks based on a predetermined rule, and the memory controller compares the plurality of block management values to read the updated value of the data as a true updated value from the second block, wherein the predetermined rule sets the plurality of block management values, respectively, as different values that sequentially increase or decrease, and the memory controller determines, when more than one of the plurality of blocks is in the used state, that the updated value of the block storing the largest or smallest one of the block management values is a true updated value.