Patent ID: 9392684
Filing Date: 2016-07-12
CPC Classification: H01L,H05K,Y10T

Claim Text:
1. A wiring substrate comprising: a core substrate including an upper surface and a lower surface located at an opposite side of the upper surface; a plurality of first wiring patterns and a plurality of first insulative layers alternately stacked on the upper surface of the core substrate; a plurality of second wiring patterns and a plurality of second insulative layers alternately stacked on the lower surface of the core substrate, wherein the number of second insulative layers stacked on the lower surface is less than the number of first insulative layers stacked on the upper surface; an insulative film that covers a surface of an outermost one of the second insulative layers stacked on the lower surface and exposes a surface of an outermost one of the second wiring patterns stacked on the lower surface, wherein the insulative film is entirely arranged in one or more spaces between i) portions of the outermost one of the second wiring patterns and ii) portions of the outermost one of the second wiring patterns and ends of the outermost one of the second insulative layers; a first solder resist that covers a surface of an outermost one of the first insulative layers and a surface of an outermost one of the first wiring patterns; and a second solder resist that covers a surface of the insulative film and the surface of the outermost one of second wiring patterns.