Patent ID: 9449666
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A memory circuit, comprising: a plurality of word line drivers coupled to a plurality of word lines, word line drivers in the plurality including a CMOS driver, the CMOS driver having an input and an output coupled to a word line of the plurality of word lines; and control circuitry having at least a first mode to discharge a particular word line of the plurality of word lines via at least a first transistor type of the CMOS driver; the control circuitry having at least a second mode to discharge the particular word line of the plurality of word lines via at least a second transistor type of the CMOS driver, the second transistor type different from the first transistor type, wherein in the second mode the control circuitry applies a negative voltage to the input of the CMOS driver.