Patent ID: 9484890
Filing Date: 2016-11-01
CPC Classification: G01C

Claim Text:
1. A quadrature compensation circuit to reduce quadrature error, the circuit comprising: a front-end circuit coupled to receive a first signal that comprises a quadrature error component, the front-end circuit outputs an analog signal; a first demodulator coupled to the front-end circuit, the first demodulator demodulates the analog signal and is configured to output a first demodulated signal related to the quadrature error component; a low pass filter coupled to the first demodulator, the low pass filter is coupled to filter out a harmonic signal from the first demodulated signal to generate a DC signal that is representative of an amplitude of the quadrature error; a modulator coupled to receive the DC signal, the modulator is configured to output a modulated DC signal; and a DAC coupled to the modulator, the DAC generates a calibration quadrature signal.