Patent ID: 9405567
Filing Date: 2016-08-02
CPC Classification: G06F

Claim Text:
1. A method comprising: creating a first working set of shadow page table hierarchies for a first processor of a plurality of processors, wherein the first working set of shadow page table hierarchies uses a first hardware translation lookaside buffer in the first processor to store virtual to physical address translations; creating a second working set of shadow page table hierarchies for a second processor of the plurality of processors; keeping a record of modified guest page tables, and for each modified guest page table, an indication of which of the plurality of processors have a hardware translation lookaside buffer containing a writable reference to the modified guest page table; synchronizing each modified guest page table with a corresponding shadow page table in the first working set; flushing the first hardware translation lookaside buffer; and updating the record of modified guest page tables to indicate that the first hardware translation lookaside buffer contains no writable references to modified guest page tables.