Patent ID: 9478471
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A device comprising: a common node disposed in a first wafer; a test node disposed in the first wafer and having a plurality of test pads exposed at a first surface of the first wafer, the test node further having a plurality of test node lines separated by a first spacing and extending to a second surface of the first wafer and each connected to a respective one of the plurality of test pads; and a comb disposed in a second wafer and having a plurality of comb lines having a second spacing different from the first spacing, each of the comb lines having a first surface exposed at a first side of the second wafer, the comb lines configured to provide an indication of an alignment of the first wafer with the second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.