Patent ID: 9424948
Filing Date: 2016-08-23
CPC Classification: G11C

Claim Text:
1. An array of eFuses that utilize two field effect transistors, the array of eFuses comprising: a plurality of rows of data cells, at least one row of the plurality of rows having a plurality of programmable data cells and a plurality of indicator data cells, wherein a selected logical state of the plurality of indicator data cells indicates that the plurality of data cells has been programmed; a wordline coupled to the plurality of programmable data cells and to the plurality of indicator data cells of the at least one row of data cells; a first plurality of bitlines coupled to the plurality of programmable data cells of the at least one row of data cells; a second plurality of bitlines coupled to the plurality of indicator data cells of the at least one row of data cells; a plurality of sense amplifiers coupled to the first and second plurality of bitlines, wherein each bitline of the first and second plurality of bitlines is coupled to a sense amplifier of the plurality of sense amplifiers; one or more logic gates coupled to outputs of the respective sense amplifiers coupled to the second plurality of bitlines, the one or more logic gates configured to determine if the plurality of indicator data cells are in the selected logical state; and a plurality of mask logic gates coupled to respective sense amplifiers coupled to the first plurality of bitlines and to one or more outputs of the one or more logic gates, the plurality of mask logic gates configured to mask outputs of the plurality of programmable data cells when the indicator data cells are not in the selected logical state.