Patent ID: 9484307
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a first die comprising a first pad and a first passivation layer; a second die comprising a second pad and a second passivation layer, wherein the first die has a first sidewall and the second die has a second sidewall; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer comprises: a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of the dielectric layer; wherein a first roughness of the first surface of the encapsulant is greater than a second roughness of the third surface of the dielectric layer.