Patent ID: 9244732
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. A method for scheduling a plurality of resource consumers executing on a computer system having at least one processor core, a last-level cache (LLC) proximate to the at least one processor core, and a main memory, the method comprising: at each descheduling event of one resource consumer of the plurality of resources consumers following an execution interval that represents a period of time during which the one resource consumer is executed on one of the at least one processor core between scheduling events, estimating time during the execution interval that was spent repopulating cache line misses evicted from the LLC by the other resources as the lesser of the execution interval or a product of a number of misses during the execution interval caused by cache lines being evicted from the LLC by the other resource consumers, an estimated amount of time to repopulate one evicted cache line, and the execution interval, and determining an effective central processing unit (CPU) time as an estimated portion of the execution interval that excludes the estimated time; and compensating the one resource consumer for contention of microarchitectural resources by prioritizing scheduling of the one resource consumer based in part on the effective CPU time for the one resource consumer and executing the resource consumers on the at least one processor core in accordance with the scheduling.