Patent ID: 9362188
Filing Date: 2016-06-07
CPC Classification: G01R,H01L

Claim Text:
1. An integrated circuit die comprising: (a) a substrate of semiconductor material having a top surface, a bottom surface, and a first opening through the substrate between the top surface and the bottom surface; (b) a first through silicon via having a first conductive body in the opening, having a first top contact point coupled to the first body at the top surface, and having a first bottom contact point coupled to the first body at the bottom surface; and (c) a first scan cell having a first serial input, a first serial output, first control inputs, a first voltage reference input, a first response input coupled to one of the first contact points, and a first stimulus output coupled to the other one of the first contact points, the first scan cell including comparator circuitry having an input coupled to the first voltage reference input, an input coupled to the first response input, and an output coupled to the first serial output.