Patent ID: 9405882
Filing Date: 2016-08-02
CPC Classification: G06F

Claim Text:
1. A computer implemented static timing analysis method for input/output modes of an integrated circuit design, comprising: loading the integrated circuit design into a memory of a computing device, wherein the integrated circuit design is described in a hardware description language; receiving an active set of input ports and an active set of output ports; defining an active zone of the integrated circuit design, the active zone comprising logic and interconnect between the active set of input ports, the active set of output ports and a selected level of sequential logic elements upstream from the active set of input ports and downstream from the active set of output ports, and which excludes functional logic between the selected level of sequential logic elements upstream from the input port and downstream from the output port; generating a description of the active zone using the hardware description language; and running a static timing analysis on the logic of the active zone; and performing timing signoff.