Patent ID: 9361231
Filing Date: 2016-06-07
CPC Classification: G06F

Claim Text:
1. A computer-implemented method for implicit input-output send on cache operations of a central processing unit, the computer-implemented method comprising the steps of: an aggregation queue of a central processing unit, storing, by one or more processors, input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit; a memory management unit of the central processing unit, interpreting address space descriptors, by the one or more processors, for implicit input-output transmittal of the input-output data of the aggregation queue; a cache traffic monitor of the central processing unit, transmitting, by the one or more processors, the input-output data in an implicit input-output transmittal range between the cache traffic monitor and the aggregation queue, wherein the cache traffic monitor transmits cache protocol of the central processing unit to the memory management unit; and the cache traffic monitor, synchronizing, by the one or more processors, implicit input-output transmittal of input-output data to initiate implicit input-output operations of the central processing unit.