Patent ID: 9330229
Filing Date: 2016-05-03
CPC Classification: G03F

Claim Text:
1. An optical proximity correction verification method comprising: loading a layout data to be verified from a first memory segment to a processor; loading a reference layout data from a second memory segment to the processor; the processor performing a first stage Boolean operation on the layout data to be verified to generate a first verified data; the processor performing a layout versus layout verification on the first verified data by using a user-defined verification tool of optical proximity correction data in a database to generate a second verified data according to the reference layout data; the processor performing a second stage Boolean operation on the second verified data to generate a third verified data if the layout versus layout verification is successfully performed; and the processor performing a Boolean check on the third verified data to generate a fourth verified data by using the reference layout data; wherein the optical proximity correction verification method provides high flexibility of design with low detection error by using the first stage Boolean operation, the layout versus layout verification, the second stage Boolean operation, and the Boolean check.