Patent ID: 9373393
Filing Date: 2016-06-21
CPC Classification: G11C

Claim Text:
1. A method in a resistive memory device, the resistive memory device including a two-dimensional array of resistive memory cells, each memory cell being accessed by a word line, a bit line and a source line, the method comprising: selecting a memory cell for read operation; generating a sense signal indicative of a programmed resistance value of the selected memory cell; comparing the sense signal to a first reference signal to generate a first read signal having a first logical state; comparing the sense signal to a second reference signal to generate a second read signal having a second logical state, the first reference signal having a first sense margin and the second reference signal having a second sense margin, the second sense margin being a reduced sense margin as compared to the first sense margin for the first logical state of the first read signal; in response to the first read signal and the second read signal having different logical states, writing the logical state of the first read signal to the selected memory cell; and providing the first read signal as the output signal of the read operation.