Patent ID: 9405308
Filing Date: 2016-08-02
CPC Classification: G05F,H03K

Claim Text:
1. A power management circuit, comprising: a main reference voltage circuit operative to generate a main reference voltage; a plurality of regulator voltage reference circuits, each receiving the main reference voltage and an enable signal, and each operative to output a signal having a predetermined voltage in response to the enable signal; wherein each regulator voltage reference circuit comprises: a voltage setting circuit operative to generate the predetermined voltage from the main reference voltage; a first current limiting transistor in series with the voltage setting circuit and operative to interrupt an operating current to the voltage setting circuit in response to the enable signal; a second current limiting transistor proportionate in size to the first current limiting transistor; and a switching network connecting the first and second current limiting transistors; and a control circuit operative to: control the switching network to enable and couple the first and second current limiting transistors as a current mirror configuration so as to limit the operating current supplied to the voltage setting circuit and to decrease a slew rate of the predetermined voltage, for an initial duration when the regulator voltage reference circuit is enabled; and disable the current mirror configuration after the initial duration.