Patent ID: 9251118
Filing Date: 2016-02-02
CPC Classification: G06F,H04L

Claim Text:
1. A method of scheduling a plurality of computation processes including all-to-all communications (A2A) among a plurality of processor nodes constituting a network of processor nodes having a torus or a mesh form based on n (n>2) dimensions on an n-dimensional space, the method comprising the steps of: selecting, by a processor node, a first plurality of processor nodes from the plurality of processor nodes, the first plurality of processor nodes forming a longest axis corresponding to a dimension of said network of processor nodes as a first subgroup; providing a first processing comprising an all-to-all longest communications (A2A-L) only among the first plurality of processor nodes included in the first subgroup; selecting, by the processor node, a second plurality of processor nodes from the plurality of processor nodes, the second plurality of processor nodes including all remaining axes other than the longest axis as a second subgroup; providing a second processing comprising an all-to-all plane communications (A2A-P) only among the second plurality of processor nodes included in the second subgroup; and scheduling, using a plurality of threads in the processor node, the plurality of computation processes for pipelined parallel processing at the processor node in a first time interval and subsequent time intervals such that in a second time interval immediately following the first time interval and in said subsequent time intervals the first all-to-all longest communications processing (A2A-L) overlaps with the second all-to-all plane communications processing (A2A-P) across the plurality of threads in the processor node and such that a single thread of the processor node is only able to perform said first all-to-all longest communications processing (A2A-L) in the first time interval and said subsequent time intervals, and the completion of said first all-to-all longest communications processing (A2A-L) in the first subgroup occurs before proceeding to a next computation process at said single thread, wherein said next computation process at said single thread includes said all-to-all plane communications processing (A2A-P) in the second subgroup, and said scheduling including scheduling the plurality of computation processes for said pipelined parallel processing in such a way as to enable the first all-to-all longest communications processing (A2A-L) all at a first thread of the processor node and a Fast Fourier Transformation (FFT) computation process or a matrix transpose computation process at a second thread of the processor node to be processed in parallel.