Patent ID: 9372950
Filing Date: 2016-06-21
CPC Classification: G06F

Claim Text:
1. A circuit layout method, comprises: displaying a system interface by a display apparatus; receiving a user request in response to an input from an input device; selecting a stack up data table, corresponding to the user request, from a stack up database by a processor, wherein the stack up data table comprises a header, a stack up field and an impedance requirement field, the stack up field comprises a stack up design, and the impedance requirement field comprises a line width data corresponding to the stack up design; generating a design rule of a computer aided design (CAD) according to the stack up data table by the processor, wherein the design rule comprises the stack up design and the line width data; and comparing a circuit board design with the design rule to determine whether the circuit board design complies with the design rule by the processor.