Patent ID: 9344108
Filing Date: 2016-05-17
CPC Classification: H03F,H03M

Claim Text:
1. An apparatus comprising: a delta-sigma modulator; a parallel-serial converter connected to the delta-sigma modulator; and a switching amplifier connected to the parallel-serial converter; wherein the parallel-serial converter comprises, in series, a parallel-to-serial converter and a subsequent swap element, wherein a multi-bit output y wherein a serial output signal y wherein the swap element generates an output signal y wherein the swap element, based on a last bit value 0 or 1 of a preceding word in the output signal y wherein the delta-sigma modulator is configured to perform the functions of receiving an input signal having a frequency range above 25 kHz, oversampling the input signal at an oversampling ratio that lies between 7 and 15, and maintaining a high signal-to-noise ratio such that 1-0 and 0-1 transitions at word boundaries are substantially eliminated.