Patent ID: 9503065
Filing Date: 2016-11-22
CPC Classification: G06F,H03K

Claim Text:
1. Circuitry comprising: a first sampling circuit configured to operate based on a first clock signal, to receive data, and to sample the data, the first clock signal being calibrated to compensate for a first timing error in a rising edge of the data; a second sampling circuit configured to operate based on a second clock signal, to receive the data, and to sample the data, the second clock signal being calibrated to compensate for a second timing error in a falling edge of the data; and a third sampling circuit to receive the data and a third clock signal, to sample the data based on the third clock signal to produce sampled data, and to control an output of the circuitry based on the sampled data to be either an output of the first sampling circuit or an output of the second sampling circuit.