Patent ID: 9240414
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate having a field area that defines active areas; gate trenches in the substrate and extending in a first direction; a buried gate in a respective gate trench; a gate capping fence in a respective gate trench over a respective buried gate, the gate capping fence protruding from top surfaces of the active areas and extending in the first direction; a bit line trench in a respective gate capping fence, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction; an insulator structure on inner walls of a respective bit line trench; a bit line and a bit line capping pattern stacked on the insulator structure in a respective bit line trench; contact pads self-aligned with the gate capping fences and on the substrate between adjacent bit lines; and a lower electrode of a capacitor on a respective contact pad.