Patent ID: 9329963
Filing Date: 2016-05-03
CPC Classification: G01R,G06F

Claim Text:
1. An integrated circuit (IC) comprising: a plurality of hardware sectors, each hardware sector associated with a debug observability circuit that is served by a debug data bus of a debug circuit, wherein the plurality of hardware sectors includes one or more steady state sectors residing in an always on power domain that remains on whenever the debug circuit is operable, and the debug observability circuits associated with the steady state sectors are directly coupled to the debug data bus; the plurality of hardware sectors including a controlled sector, the controlled sector residing in a dynamically-controlled power domain that may be turned off while the power domain of another sector remains on; and a selectively switchable data bus component configured to couple the debug observability circuit associated with the controlled sector to the debug data bus when the power to the controlled sector is on and to switch to bypass the debug observability circuit associated with the controlled sector when the power to the controlled sector is not on.