Patent ID: 9286223
Filing Date: 2016-03-15
CPC Classification: G06F,Y02D

Claim Text:
1. A processor, comprising: a processing unit; a cache memory; a central request queue operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit; and a processor request queue operable to store the demand load request, wherein the central request queue is operable to merge the prefetch load request and the demand load request to generate the promoted load request in the central request queue and is operable to delete the demand load request from the processor request queue in response to generating the promoted load request.