Patent ID: 9355262
Filing Date: 2016-05-31
CPC Classification: G06F

Claim Text:
1. A processor comprising: instruction hardware to receive a first instruction and a second instruction, wherein the first instruction is to extend access permissions for a page in a secure enclave and the second instruction is to be called, by an application from within the secure enclave, an operating system outside the secure enclave to invoke the second instruction to restrict access permissions for the page; execution hardware to execute the first instruction and the second instruction, wherein execution of the first instruction and the second instruction includes changing at least one of a read, write, and execute access permission in an enclave page cache map entry without setting a modified bit in the enclave page cache map entry, wherein execution of the second instruction includes storing an enclave epoch value in the enclave page cache map entry, and wherein the page is immediately accessible from inside the secure enclave according to the changed access permissions; and a translation lookaside buffer, wherein the operating system is to track enclave threads with translation lookaside buffer entries made stale by the changed access permissions and send interprocessor interrupts to trigger enclave thread exits and a translation lookaside buffer shootdown.