Patent ID: 9472277
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A non-volatile memory device comprising: a first memory cell region including first wirings extending in a first direction, second wirings extending in a second direction crossing the first direction, the second wirings being adjacent to the first wirings in a third direction crossing the first direction and the second direction, and first memory cells being provided at first crossing portions, the first wirings and the second wirings crossing at the first crossing portions, one of the first memory cells electrically connecting to one of the first wirings and one of the second wirings at one of the first crossing portions, and including a first resistive layer; a second memory cell region positioned beside the first memory cell region in a direction crossing the third direction, the second memory cell region including third wirings extending in the first direction, fourth wirings extending in the second direction, the third wirings being adjacent to the fourth wirings in the third direction, and second memory cells being provided at second crossing portions, the third wirings and the fourth wirings crossing at the second crossing portions, one of the second memory cells electrically connecting to one of the third wirings and one of the fourth wirings at one of the second crossing portions, and including a second resistive layer; and a control circuit configured to independently control each of the first memory cell region and the second memory cell region by selecting one of the first wirings and one of the second wirings or selecting one of the third wirings and one of the fourth wirings, a number of the second memory cells provided at the second crossing portions being smaller than a number of the first memory cells provided at the first crossing portions, and the second memory cell region having a smaller area than the first memory cell region.