Patent ID: 9344093
Filing Date: 2016-05-17
CPC Classification: H03K

Claim Text:
1. A counter, configured to output a count value having N bits, wherein N is a positive integer, the counter comprising: a state determination unit, receiving a current count value to calculate a next count value of the counter, wherein the next count value has a high bit count part and a low bit count part; a value analyzing unit, receiving and outputting a reset counter value, comparing the reset counter value and a delay cycle value to output a value comparing signal; and a count comparing unit, receiving a clock signal, determining to use a first comparator or a second comparator based on the value comparing signal, and outputting a reset counter signal to the state determination unit to reset the next count value based on a comparison result and the clock signal, wherein a bit number of the first comparator is smaller than a bit number of the second comparator.