Patent ID: 9331059
Filing Date: 2016-05-03
CPC Classification: G01R,H01L

Claim Text:
1. A chip for a chip package, the chip comprising: a substrate, an integrated circuit over the substrate, the integrated circuit comprising a test circuit and an operation circuit, the test circuit comprising one or more first driver stages each having a first driver performance and the operation circuit comprising one or more second driver stages each having a second driver performance which is different to the first driver performance, first contacts electrically coupled with the one or more first driver stages, and second contacts electrically coupled with the one or more second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode; wherein the first contacts are arranged in a plurality of groups, wherein all first contacts of one group are electrically coupled with each other by a pin that at least partially overlaps all first contacts in the group with the same first driver stage.