Patent ID: 9337837
Filing Date: 2016-05-10
CPC Classification: H03K

Claim Text:
1. A circuit authentication system comprising: a plurality of physical unclonable function (PUF) elements including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, wherein the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements; a measurement unit configured to measure at least one differential of states between said first subset of PUF elements and said second subset of PUF elements, said at least one differential of states forming a basis of at least part of a bit sequence of an authentication signature for said circuit; and a multiplexer configured to combine said states, wherein said measurement unit comprises at least one quantizer configured to assess whether each of the differentials of states is a one or a zero in said bit sequence, and wherein the multiplexer, the at least one quantizer, and at least some of the PUF elements are each connected to a same regulated voltage.