Patent ID: 9343450
Filing Date: 2016-05-17
CPC Classification: G02B,H01L

Claim Text:
1. A method for aligning components of a plurality of optical transceiver modules using a silicon interposer wafer as a platform for assembling a plurality of separate transceiver modules, wherein the silicon interposer wafer comprises a silicon planar surface defining an optical reference plane and a plurality of conductive vias formed through the silicon interposer wafer to provide electrical connections to other components, the method comprising: forming a dielectric layer over the silicon planar surface of the silicon interposer wafer, wherein the dielectric layer is configured to support the placement and interconnection of electrical integrated circuit components associated with the plurality of separate transceiver modules, the dielectric layer further including electrical conductive paths for providing electrical connection between the supported electrical integrated circuit components and selected ones of the conductive vias of the underlying silicon interposer wafer; patterning and etching the dielectric layer to create a plurality of openings, thereby exposing the silicon planar surface of the silicon interposer wafer at each opening, wherein the plurality of openings are of predetermined sizes and are disposed in predetermined locations, such that placement of the optical components into corresponding openings of the plurality of openings aligns at least two of the optical components and establishes optical signal paths between the aligned optical components along the optical reference plane; and assembling the plurality of separate transceiver modules on the silicon interposer wafer.