Patent ID: 9461129
Filing Date: 2016-10-04
CPC Classification: G11C,H01L

Claim Text:
1. A memory cell, comprising: a selection gate extending vertically in a trench made in a semiconductor substrate a first gate dielectric layer insulating the selection gate from the substrate; a vertical channel region extending in the substrate along the first gate dielectric layer; a horizontal floating gate extending above the substrate; a second gate dielectric layer insulating the horizontal floating gate from the substrate; a horizontal control gate extending above the floating gate; and an embedded layer forming a collective source plane in electrical contact with the vertical channel region, the collective source plane being configured to collect programming currents for programming the memory cell and other memory cells formed in the substrate, wherein the selection gate covers a lateral face of the floating gate, the floating gate being separated from the selection gate only by the first gate dielectric layer and being separated from the vertical channel region by the second gate dielectric layer.