Patent ID: 9378987
Filing Date: 2016-06-28
CPC Classification: H01L,H05K

Claim Text:
1. A semiconductor package comprising: a lower package comprising a lower semiconductor chip on a lower package substrate; an upper package comprising an upper package substrate on the lower package and on the lower semiconductor chip opposite the lower package substrate; interconnection terminals electrically connecting the lower package substrate with the upper package substrate; and a lower molding film molding the lower semiconductor chip between the lower package substrate and the upper package substrate, wherein the lower package substrate comprises a chip region between the lower semiconductor chip and the lower package substrate, an interconnection region outside of and enclosing a portion of the chip region, and a mold injection region defined by the chip region and the interconnection region, and the interconnection terminals are on the lower package substrate of the interconnection region but not on the lower package substrate of the mold injection region, wherein an interval between the interconnection terminals in one direction is smaller than a width of the mold injection region in the one direction.