Patent ID: 9305915
Filing Date: 2016-04-05
CPC Classification: H01L,H03K

Claim Text:
1. An electrostatic discharge (ESD) protection circuit, comprising: a first NMOS transistor coupled to a power line; a second NMOS transistor coupled between the first transistor and a ground; a detection unit, providing a detection signal when an ESD event occurs at the power line; and a trigger unit, turning on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors, wherein the trigger unit further comprises: a first PMOS transistor coupled between the power line and a gate of the second NMOS transistor, having a gate coupled to the cathode of the diode for receiving the detection signal; a fourth resistor coupled between the gate of the second NMOS transistor and the ground; and a second PMOS transistor coupled between the gates of the first and second NMOS transistors, having a gate coupled to the cathode of the diode for receiving the detection signal.