Patent ID: 9466348
Filing Date: 2016-10-11
CPC Classification: G06F,G11C,Y02D

Claim Text:
1. An apparatus comprising: a first memory unit including a first array of memory cells and control logic, the first memory unit configured to receive command information and chip select information; and a second memory unit including a second array of memory cells, the second memory unit coupled to the first memory unit, the first memory unit configured to access data stored in the first array of memory cells responsive to the command information when the chip select information designates the first memory unit, and further configured to cause the second memory unit to access data stored in the second array of memory cells responsive to the command information when the chip select information designates the second memory unit, wherein the control logic is configured to detect a deselect condition wherein the chip select information does not designate either of the first and second memory units.