Patent ID: 9437304
Filing Date: 2016-09-06
CPC Classification: G11C,H01L

Claim Text:
1. A memory device, comprising: a memory array; and control logic; wherein the control logic is configured to decrease a difference of a voltage applied to a first select gate of the memory array minus a voltage applied to a source of the memory array coupled to the first select gate while the first select gate is off; wherein the control logic is configured to decrease a difference of a voltage applied to a second select gate of the memory array minus a voltage applied to a data line coupled to the second select gate while the second select gate is off; and wherein the control logic is configured to increase a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell, not targeted for programming, in a string of memory cells of the memory array coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and after or substantially concurrently with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.