Patent ID: 9404969
Filing Date: 2016-08-02
CPC Classification: G01R,G06F

Claim Text:
1. A method of testing an integrated circuit having a plurality of logic gates fabricated thereon to determine whether defects are present, wherein the integrated circuit to be tested comprises a plurality of core instances, with each of the plurality of core instances comprising a plurality logic gates, and a plurality of scan chains, the method comprising: for the plurality of core instances, receiving a plurality of test stimulus values for the plurality of scan chains; receiving an expected response signature; broadcasting the expected response signature and mask values to a plurality of identical core instances; loading the expected response signature and the mask values into the plurality of identical core instances; loading the plurality of test stimulus values into the plurality of core instances in parallel to produce a test response output for the plurality of core instances; capturing the test response output for the plurality of core instances into the plurality of scan chains of a corresponding one of the plurality of core instances; generating a test response signature from the plurality of test response outputs stored in the plurality of scan chains; comparing the test response signature against the expected response signature; generating a plurality of pass/fail bits for the plurality of core instances structured to correspond each pass/fail bit of the plurality of pass/fail bits to a core instance of the plurality of core instances, wherein the plurality of pass/fail bits contain information about whether the test response signature matches the expected response signature; and unloading the pass/fail bits from a pin of the integrated circuit.