Patent ID: 9530724
Filing Date: 2016-12-27
CPC Classification: H01L

Claim Text:
1. A power quad flat no-lead (PQFN) semiconductor package comprising: a leadframe comprising a plurality of die pads; a driver integrated circuit (IC) coupled to a top surface of a first die pad of said leadframe; a plurality of vertical conduction power transistors including a first group of vertical conduction power transistors coupled to a top surface of a common die pad of said leadframe and a second group of vertical conduction power transistors individually coupled to respective top surfaces of separate die pads of said leadframe; a top surface electrode of one of said first group of vertical conduction power transistors being electrically connected to a first plating, and a bottom surface electrode of one of said second group of vertical conduction power transistors being electrically connected to a second plating, said first plating being electrically coupled to said second plating; wherein said common die pad has an exposed surface on a bottom surface of said PQFN semiconductor package that corresponds to an outline of said first plating; and wherein a die pad of said separate die pads of said leadframe has an exposed surface on said bottom surface of said PQFN semiconductor package that corresponds to an outline of said second plating.