Patent ID: 9449129
Filing Date: 2016-09-20
CPC Classification: G06F

Claim Text:
1. A method of accelerating sparse matrix operations in full accuracy simulation of a circuit, comprising: determining repetitive blocks of the circuit and associating each of the repetitive blocks with one of a plurality of block types in which each block type identifies blocks having identical block structures; determining a set of node or branch values of a current block of the repetitive blocks of the circuit; determining whether the set of node or branch values of the current block is within a predetermined error range of a stored set of node or branch values of a stored block solution previously computed for another block of the same block type, in which the predetermined error range comprises a linear approximation range; when the set of node or branch values of the current block is outside the predetermined error range of a stored set of node or branch values of any stored block solution, performing a full computation evaluation for determining a solution for the current block and storing the solution; and when the set of node or branch values of the current block is not identical to but is within the predetermined error range of a stored set of node or branch values of a stored block solution of the same block type, performing a reduced computation evaluation using the stored set of node or branch values of the stored block solution to determine a solution for the current block, wherein said reduced computation evaluation comprises: