Patent ID: 9378843
Filing Date: 2016-06-28
CPC Classification: G05F,G11C,H03L,H03M,H04B

Claim Text:
1. An integrated circuit (IC), comprising: first sample-and-hold circuitry to sample an input signal based on a data clock signal, and to output a first sampled voltage for at least a first holding period; a first set of adjustable comparators, wherein each adjustable comparator in the first set of adjustable comparators has a respective reference voltage that is adjustable, and wherein each adjustable comparator in the first set of adjustable comparators outputs a result signal based on comparing the first sampled voltage with the respective reference voltage of the adjustable comparator in the first set of adjustable comparators; second sample-and-hold circuitry to sample the input signal based on an edge-detection clock signal, and to output a second sampled voltage for at least a second holding period; a second set of adjustable comparators, wherein each adjustable comparator in the second set of adjustable comparators has a respective reference voltage that is adjustable, and wherein each adjustable comparator in the second set of adjustable comparators outputs a result signal based on comparing the second sampled voltage with the respective reference voltage of the adjustable comparator in the second set of adjustable comparators; and control-logic circuitry to (1) predict a first voltage range of a future edge sample of the input signal, (2) set reference voltages for the second set of adjustable comparators based on the predicted first voltage range, (3) predict a second voltage range of a future data sample of the input signal, and (4) set reference voltages for the first set of adjustable comparators based on the predicted second voltage range.