Patent ID: 9293366
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A device comprising: a substrate; a plurality of dielectric layers over the substrate; a plurality of metallization layers formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers lower than the top level of the plurality of metallization layers comprises a metal pad; an interlayer dielectric (ILD) disposed over the substrate and under the plurality of metallization layers, the bottommost surface of the metal pad above the topmost surface of the ILD; a through-substrate via (TSV) extending from the top level of the plurality of the dielectric layers to a bottom surface of the substrate; a deep conductive via extending from the top level of the plurality of dielectric layers and landing on the metal pad, wherein the deep conductive via is a structure different from the metal pad; a metal line over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via; a passivation layer over the metal line; and a metal bump over the passivation layer, the metal bump disposed outside a lateral extent of the metal line.