Patent ID: 9304967
Filing Date: 2016-04-05
CPC Classification: G06F,Y02D

Claim Text:
1. A non-transitory computer-readable storage medium comprising a compiler for a reconfigurable processor that comprises a coarse-grained array (CGA) mode utilizing a CGA module comprising a first plurality of functional units and a very long instruction word (VLIW) mode utilizing a VLIW module comprising a second plurality of functional units, the compiler being configured to; detect a loop entry node that stores context for switching to a VLIW mode; in response to detecting the loop entry, insert a CGA power-on instruction into a node preceding the detected CGA entry node, to cause the reconfigurable processor to supply power to the CGA module; determine if the node prior to the detected loop entry node is a branch node; in response to determining the node prior to the detected CGA entry node is a branch node, insert a CGA power-off instruction into a node on any branch of the branch node that is not connected to the detected loop entry node; detect a loop exit decision node, and in response to detecting the loop exit decision node, insert a VLIW power-on instruction in a node next to a detected loop exit decision node and prior to a loop exit node to cause the reconfigurable processor to supply power to the VLIW module, wherein the loop exit decision node determines whether to terminate iterative execution of a loop in a data dependency graph of a program to be run in the reconfigurable processor.