Patent ID: 9275907
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: multiple fins above a semiconductor substrate, a gate adjacent to the center portion of each of the fins; a gate sidewall spacer adjacent to the gate, the end portion of each of the fins extending laterally beyond the gate and the gate sidewall spacer; an epitaxial doped layer covering the end portion of each of the fins and filling any space between adjacent end portions of adjacent fins, the epitaxial doped layer comprising a second semiconductor material that is different from the first semiconductor material; and a nitride layer immediately adjacent to a top surface and sidewalls of the epitaxial doped layer and further abutting the gate sidewall spacer, the nitride layer being physically separated from the gate by the gate sidewall spacer and not extending over the gate sidewall spacer and the gate, the end portion of each of the fins having the different crystal lattice, the epitaxial doped layer, and the nitride layer comprising a strained source and drain region that induces stress in the channel region, the stress enhancing carrier mobility within the channel region.