Patent ID: 9515094
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first memory cell, a second memory cell, and a third memory cell, each of the first memory cell, the second memory cell, and the third memory cell comprising: a first wiring; a second wiring; a third wiring; and a fourth wiring, wherein, in each of the first memory cell, the second memory cell, and the third memory cell, a first terminal of the first transistor is electrically connected to a gate of the second transistor, wherein, in each of the first memory cell, the second memory cell, and the third memory cell, a first terminal of the second transistor is electrically connected to a gate of the third transistor, wherein, in each of the first memory cell and the second memory cell, a gate of the first transistor is electrically connected the first wiring, wherein, in the third memory cell, a gate of the first transistor is electrically connected the second wiring, wherein, in each of the first memory cell and the third memory cell, a first terminal of the third transistor is electrically connected to the third wiring, wherein, in the second memory cell, a first terminal of the third transistor is electrically connected to the fourth wiring, wherein an off-state current of the first transistor is lower than an off-state current of the third transistor, and wherein a leakage current of the second transistor is lower than a leakage current of the third transistor.