Patent ID: 9443941
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a transistor device, comprising: providing a compound semiconductor body having first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body; forming a source in contact with the two-dimensional charge carrier gas; forming a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas; forming a first passivation layer having a first surface in contact with the first surface of the compound semiconductor body and a second surface facing away from the first surface; forming a second passivation layer in contact with the first passivation layer, the second passivation layer having a different etch selectivity than the first passivation layer; forming an etched opening in the second passivation layer, the etched opening extending through the second passivation layer and stopping at the second surface; forming a further etched opening in the first passivation layer beneath the etched opening, the further etched opening extending from the second surface towards the compound semiconductor body; forming a gate in the etched opening and in the further etched opening; and forming a field plate spaced apart from the gate in the second passivation layer and disposed on the first passivation layer, wherein forming the etched opening and forming the further etched opening comprises two different etching processes, and wherein forming the gate and the field plate comprises: