Patent ID: 9258010
Filing Date: 2016-02-09
CPC Classification: H03M

Claim Text:
1. A method comprising: receiving an input binary word, wherein the binary word includes a plurality of most significant bits and a plurality of least significant bits; decoding the input binary word to an intermediate signal, wherein the intermediate signal includes a bit width equal to or greater than a bit width of the binary word; setting a plurality of output switches according to the intermediate signal, wherein the plurality of output switches includes a pair of switches for each state of the plurality of most significant bits and a pair of switches for each state of the plurality of least significant bits; setting a plurality of current source switches according to the intermediate signal, wherein the plurality of current source switches includes a pair of switches for each state of the plurality of most significant bits; and providing an analog output signal that represents the input binary word, wherein the analog output signal is controlled by the plurality of output switches and the plurality of current source switches.