Patent ID: 9384523
Filing Date: 2016-07-05
CPC Classification: G06F,G06T

Claim Text:
1. A computer-implemented method, the method comprising: receiving, by a first process, a set of input events associated with user input; separating input dependent commands associated with the set of input events into a set of input update commands for writing a set of data into a shared graphics processing unit (GPU) texture and a set of rendering commands that reference data in the shared GPU texture; writing, by the first process, the set of input update commands into a first low-latency first-in-first-out (FIFO) graphics pipeline; writing, by the first process, the rendering commands into a first high-latency FIFO graphics pipeline, the first low-latency FIFO graphics pipeline having a lower latency metric in comparison with a latency metric of the first high-latency FIFO graphics pipeline; dispatching, by the first process, the set of input update commands from the first low-latency FIFO graphics pipeline to a second process; receiving, by the second process, the set of input update commands from the first low-latency FIFO graphics pipeline; and writing, by the second process via a second low-latency FIFO graphics pipeline, the set of data into the shared GPU texture.