Patent ID: 9362383
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method to fabricate a plurality of field effect transistors (FETs) each having a source region, a drain region, and a gate that overlies a channel region disposed between the source region and the drain region, the method comprising: forming a plurality of spaced apart mandrels on a top surface of a substrate; forming spacers on sidewalls of the mandrels, the spacers each having an inner sidewall disposed on a sidewall of a mandrel and an outer sidewall; forming first recesses through the top surface of the substrate, each recess extending from an outer sidewall of a first spacer to an outer sidewall of an adjacent spacer; filling the first recesses with source material and covering the source material with first dielectric material; removing the mandrels and forming, where the mandrels are removed, second recesses through the top surface of the substrate; filling the second recesses with drain material and covering the drain material with second dielectric material; removing the spacers to form a plurality of openings to expose a portion of the top surface of the substrate, each opening having sidewalls defined by first and second dielectric material; forming in each opening a gate structure on the sidewalls of the first and second dielectric material and on an exposed portion of the top surface of the substrate; removing the first and second dielectric material; and depositing, where the first and the second dielectric material is removed, source and drain contacts to the source material and the drain material, respectively.