Patent ID: 9256430
Filing Date: 2016-02-09
CPC Classification: G06F

Claim Text:
1. A method to select a design from at least two different designs of a processor with at least two execution pipes and at least two registers, the method comprising: obtaining the at least two different designs of the processor, wherein the at least two different designs each specify a respective specific processor instruction set architecture having a fixed hardware and instruction set thereof, and wherein the at least two different designs comprise data for processor instruction latency and execution pipes; obtaining a plurality of code streams, each code stream of the plurality of code streams comprising processor instructions and corresponding register selections, and each code stream of the plurality of code streams comprising compiled code compiled for a corresponding different design of the at least two different designs of the processor; generating, by a processor, an optimized code stream for each design of the at least two different designs, the generating being performed for each design based on the fixed hardware and instruction set of the design, wherein the generating an optimized code stream for a design of the at least two different designs comprises reordering the compiled code of the code stream corresponding to that design such that an optimum value for at least one design parameter is achieved without affecting operation results of the obtained code stream corresponding to that design, wherein the generating the optimized code stream for each design of the at least two different designs provides a plurality of optimum values for the at least one design parameter, and wherein the generating uses register renaming; and selecting a design, from the at least two different designs, for which the best optimum value of the plurality of optimum values for the at least one design parameter is achieved.