Patent ID: 9306591
Filing Date: 2016-04-05
CPC Classification: H03M

Claim Text:
1. A computer-implemented method, comprising: applying a predetermined input signal to a last pipeline stage of a pipeline analog-to-digital converter (ADC), the pipeline ADC comprising a plurality of pipeline stages; adjusting one or more settings of the last pipeline stage; estimating one or more correction parameters of the last pipeline stage; calculating a correction coefficient for the last pipeline stage based at least in part upon the estimated one or more correction parameters of the last pipeline stage; estimating one or more correction parameters of each of remaining pipeline stage(s) in the pipeline ADC; calculating a correction coefficient of each of the remaining pipeline stage(s) based at least upon the estimated one or more correction parameters of the corresponding pipeline stage; and correcting an output signal of the pipeline ADC by applying the correction coefficient of each of the plurality of pipeline stages to the corresponding pipeline stage.