Patent ID: 9477587
Filing Date: 2016-10-25
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A system for partitioning a non-volatile memory device comprising: a memory array of multi-level memory cells; a first addressable range of memory blocks of the memory array, the first addressable range of memory blocks configured as single level memory cells, and further configured to store at least one type of data, wherein the at least one type of data comprises software code and a first error correcting code; a second addressable range of memory blocks of the memory array, the second addressable range of memory blocks configured to store at least another type of data wherein the at least another type of data comprises user data and a second error correcting code, wherein the first and second error correcting codes are different, and wherein the first error correcting code is based on error correcting coding that codes data with a higher reliability level than error correcting coding on which the second error correcting code is based; and a third addressable range of memory blocks of the memory array, the third addressable range of memory blocks configured as single level memory cells and further configured to store attribute data of the first, second, and third addressable ranges of memory blocks, wherein updating the attribute data causes a region of the first or second addressable range of memory blocks to be converted to the second or first addressable range of memory blocks, respectively, and wherein the third addressable range is located at a fixed location in the non-volatile memory device, which is identified at a time of testing the non-volatile memory device, and wherein the attribute data is updated to track all converted memory blocks of the first and second addressable ranges without the use of physical markers located in the individual blocks of the first and second addressable ranges.