Patent ID: 9472399
Filing Date: 2016-10-18
CPC Classification: B82Y,H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming a three-dimensional germanium-containing semiconductor structure on a semiconductor release layer disposed above a semiconductor substrate, the semiconductor release layer comprising a semiconductor material different from the three-dimensional germanium-containing semiconductor structure; insulating the three-dimensional germanium-containing semiconductor structure from the semiconductor substrate by forming one or more isolation pedestals directly under the semiconductor release layer; and, subsequently, removing a portion of the semiconductor release layer; forming a gate electrode stack at least partially surrounding a channel region of the three-dimensional germanium-containing semiconductor structure; and forming a pair of conducting contacts, one contact at least partially surrounding a source region of the three-dimensional germanium-containing semiconductor structure, and the other contact at least partially surrounding a drain region of the three-dimensional germanium-containing semiconductor structure, wherein removing the portion of the semiconductor release layer comprises removing a portion between the source and drain regions and the semiconductor substrate, and wherein the one contact surrounds the source region and the other contact surrounds the drain region.