Patent ID: 9448284
Filing Date: 2016-09-20
CPC Classification: G01R

Claim Text:
1. A circuit comprising: an input converter configured to receive N scan inputs and configured to generate M pseudo scan inputs, where M and N are integers; a scan compression architecture coupled to the input converter and configured to generate P pseudo scan outputs in response to the M pseudo scan inputs; and an output converter coupled to the scan compression architecture and configured to generate Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers, and the input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency, and a ratio of the first frequency and the second frequency is equal to a ratio of M and N and to a ratio of P and Q.