Patent ID: 9269636
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A process of forming an integrated circuit, comprising the steps: forming a high quality gate dielectric on a substrate at a temperature of at least 850° C.; depositing a sacrificial gate dielectric on the high quality gate dielectric; forming a first polysilicon replacement gate transistor with a first polysilicon replacement gate on the sacrificial gate dielectric; removing by etching the first polysilicon replacement gate to form a first replacement gate transistor trench; removing the sacrificial gate dielectric from a bottom of the first replacement gate trench using an etch with high selectivity to the high quality gate dielectric; depositing a high-k dielectric into the first replacement gate transistor trench wherein the high-k dielectric covers the high quality gate dielectric in the bottom and wherein the high-k dielectric covers vertical sidewalls of the first replacement gate trench; depositing metal gate material on the high-k dielectric; polishing the integrated circuit to remove overfill of the metal gate material and the high-k dielectric from the flat surface of the replacement gate dielectric; forming a second polysilcon replacement gate transistor with a second polysilcon replacement gate wherein the first polysilcon replacement gate transistor is a low voltage transistor and wherein the second polysilicon replacement gate transistor is a high voltage transistor; during the step of removing by etching the first polysilicon replacement gate to form the first replacement gate transistor trench, removing by etching the second polysilicon replacement gate to form a second replacement gate transistor trench; forming a high voltage transistor photo resist pattern wherein the high voltage transistor photo resist pattern covers the second replacement gate trench and does not cover the first replacement gate trench; removing the sacrificial gate dielectric from a bottom of the first replacement gate trench by etching; and removing the high voltage transistor photo resist pattern prior to the step of depositing the high-k dielectric.