Patent ID: 9342294
Filing Date: 2016-05-17
CPC Classification: G06F

Claim Text:
1. A method of patching executable instructions or data in a read-only memory accessible by a processor including a hardware interrupt interface and input bus, comprising the steps of: providing a CAM device storing a vector of addresses of cells that must be patched in the read-only memory, comparing the addresses of executable instructions or data in the read-only memory with the elements of the vector stored in the CAM device, if the address requested by the processor matches with one of the elements in the vector of addresses to be patched, presenting to the processor a substitution executable instruction or data to replace an executable instruction or data already provided to the processor input bus when addressed by the processor in the read-only memory with a patched executable instruction or data stored in a patch memory; the CAM device including a MRAM-TCAM device comprising a plurality of MRAM memory cells, each MRAM memory cell comprising at least one magnetic tunnel junction, and interrupting the processor by applying an interrupt signal to the interrupted interface if the address requested by the processor matches with one of the elements of the vector, so as to prevent the reading of the executable instruction of data provided on the processor input bus by the read-only memory, and removing the interrupt signal from the interrupt interface after application of the patched executable instruction or data to the processor input bus to cause the processor to read the patched executable instruction or data.