Patent ID: 9281318
Filing Date: 2016-03-08
CPC Classification: G11C,H01L

Claim Text:
1. An integrated circuit comprising: a substrate; a pillar of semiconductor material electrically coupled to the conductive source layer; two or more stacked memory cells comprising channels that are formed in the pillar, wherein a segment of the pillar of semiconductor material extends beyond the two or more stacked memory cells; and a field effect transistor (FET) formed proximate to the two or more stacked memory cells, and having a channel that is formed in said pillar, wherein the FET comprises an exposed portion of the segment of the pillar extending beyond the two more stacked memory cells the pillar having a first cross-sectional area where the channel of the FET is formed, and a second cross-sectional area where the channels of the two or more stacked memory cells are formed.