Patent ID: 9412428
Filing Date: 2016-08-09
CPC Classification: G11C

Claim Text:
1. A memory controller, comprising: a first circuit to send a first timing reference signal to a memory device; a second circuit to send a second timing reference signal to the memory device, the second timing reference signal to have a quadrature phase relationship with respect to the first timing reference signal, the memory device to send a plurality of calibration bit patterns synchronously with respect to the first timing reference signal and the second timing reference signal; a receiver circuit to sample the plurality of calibration bit patterns over a range of receive timings, the sampling of the plurality of calibration bit patterns over the range of receive timings resolving a plurality of timing indicators associated with when transitions between bits of the plurality of calibration bit patterns are received; and, a timing adjustment circuit to adjust, based on the plurality of timing indicators, a duty cycle of the first timing reference, a duty cycle of the second timing reference, and a quadrature phase adjustment between the first timing reference and the second timing reference.