Patent ID: 9331172
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device, comprising: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer, wherein the ONO structure comprises a first oxide layer, a nitride layer, and a second oxide layer from the first oxide layer up to the second oxide layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the uppermost layer of the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on a top surface of the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at a top surface of the dummy gate oxide layer to form a dummy gate structure, wherein the dummy gate material layer comprises amorphous silicon with a thickness of 900-1200 Å, and the dummy gate oxide layer comprises silicon dioxide with a thickness of about 20-40 Å.