Patent ID: 9490206
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A method for fabricating an electrical device, the method comprising: forming a fin structure on a substrate, wherein the fin structure comprises a first section comprising a first width and a first height, and a second section comprising a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height, wherein forming the fin structure comprises: forming a first partial fin core structure and a second partial fin core structure of a crystalline semiconductor material on the substrate, the first and second partial fin core structures being separated by a gap; and growing an epitaxial semiconductor layer of the crystalline semiconductor material selectively on the first and second partial fin core structures, wherein the epitaxial semiconductor layer bridges the gap and forms an electrically conductive link of the crystalline semiconductor material between the first and second partial fin core structures.