Patent ID: 9496243
Filing Date: 2016-11-15
CPC Classification: G11C,H01L

Claim Text:
1. A microelectronic assembly, comprising: a circuit panel having first and second opposed surfaces and first and second panel contacts at the first and second surfaces, respectively; and a first microelectronic package having a plurality of terminals mounted to the first panel contacts, a second microelectronic package having a plurality of terminals mounted to the second panel contacts, each of the first and second microelectronic packages including: a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon; a microelectronic element having memory storage array function, the microelectronic element having a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face, the plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component external to the package, the plurality of terminals electrically coupled with the substrate contacts and including first terminals disposed at locations within first and second sets, each set of first terminals distributed at at least eight different positions within a column of at least one column extending in a first direction, the first terminals of each of the first and second sets being configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element, wherein the signal assignments of the first terminals in the first set are symmetric about an axis extending in the first direction with the signal assignments of the first terminals in the second set, the terminals further including first and second groups of second terminals, each of the first and second groups of second terminals having at least eight data terminals disposed on first and second opposite sides of the axis, respectively, wherein each group of the second terminals being distributed at at least four different positions within a row of at least one row extending in a second direction transverse to the first direction, and each of the data terminals of the first and second groups is configured to carry a data signal for read and write access to locations of a memory storage array within the microelectronic element, and each data terminal of the first group has modulo-X symmetry about the axis with each data terminals of the second group, wherein X is a whole number greater than 2.