Patent ID: 9291672
Filing Date: 2016-03-22
CPC Classification: G01R

Claim Text:
1. A debug apparatus for debugging a chip under test with a plurality of pins, wherein a program is stored in the chip under test, and the debug apparatus comprising: a processor, controlling the chip under test via an emulator, and obtaining electric signals from at least one of the plurality of pins of the chip under test via the emulator when the chip under test is controlled by the processor to perform the program, wherein the processor is configured to provide graphical data, which includes a chip object representing a first image corresponding to an exterior of the chip under test, and a plurality of pin objects, wherein each of the pin objects represents a second image corresponding to the individual pin of the chip under test, to indicate pin states of the chip under test according to the electric signals, wherein the first image and the second images are displayed in a display unit via a graphical pin interface, wherein relative positions of the first image and the second images are identical to relative positions of the chip under test and the pins of the chip under test.