Patent ID: 9406599
Filing Date: 2016-08-02
CPC Classification: H01L,H05K

Claim Text:
1. A wiring substrate comprising: an insulating layer including upper and lower surfaces; a wiring layer including upper, lower, and side surfaces and being in a position that is recessed relative to the upper surface of the insulating layer; a via wiring formed in the insulating layer and connected to the lower surface of the wiring layer; and a solder resist layer formed on the upper surface of the insulating layer; wherein the via wiring includes a first part contacting the lower surface of the wiring layer and a second part exposed from the lower surface of the insulating layer, the first part having an area smaller than an area of the second part, wherein the wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface, wherein the solder resist layer includes an upper surface and an opening that exposes the pad and a part of the upper surface of the insulating layer, wherein the solder resist layer buries a step part formed by the upper surface of the insulating layer and the upper surface of the wiring pattern, wherein the pad includes wherein the upper surface of the pad body and the upper surface of the wiring pattern are on the same plane, and wherein the upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer.