Patent ID: 9324822
Filing Date: 2016-04-26
CPC Classification: G01R,H01L

Claim Text:
1. A method for forming a transistor, comprising: forming a source region on a substrate, comprising forming a first n+dopant region on a p-type substrate and forming a first contact region above said first n+dopant region; forming a drain region on said substrate adjacent said active gate region, comprising forming a second n+dopant region on said p-type substrate and forming a second contact region above said second n+dopant region; forming an active gate region on said substrate adjacent said source region, comprising forming a first gate oxide region above said p-type substrate between said first and second n+dopant regions and forming a first polysilicon conductor region above said first gate oxide region; and forming a first inactive gate region on said substrate in parallel to said active gate region, comprising forming a second gate oxide region above said p-type substrate adjacent said first n+dopant region, forming a second polysilicon conductor region above second first gate oxide region, and electrically coupling said second polysilicon conductor region to said first polysilicon conductor region, wherein said source region, said drain region, said active gate region, and said first inactive gate region comprise said transistor, and wherein said first inactive gate region is capable of dissipating at least a portion of a charge.