Patent ID: 9230049
Filing Date: 2016-01-05
CPC Classification: G06F

Claim Text:
1. A computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to design a power grid for an integrated circuit, the designing comprising: forming a plurality of half pitch tiles that do not have a via violation, wherein each half pitch tile has a different orientation; generating a plurality of types of sub tile cell arrays from each of the half pitch tiles, wherein at least one of the sub tile cell arrays has an asymmetric vertical and horizontal dimension; forming a plurality of quarter pitch tiles that do not have a via violation, wherein each quarter pitch tile has a different orientation; generating a plurality of types of deep sub tile cell arrays from each of the quarter pitch tiles, wherein at least one of the deep sub tile cell arrays has the asymmetric vertical and horizontal dimension; covering a plurality of adjacent individual sub tile cell areas of the power grid with one or more of the types of sub tile cell arrays; and covering a plurality of adjacent individual deep sub tile cell areas of the power grid with one or more of the types of deep sub tile cell arrays; wherein the covering the plurality of adjacent individual sub tile cell areas and the covering the plurality of adjacent individual deep sub tile cell areas determine a via placement layout for the power grid and generate an integrated circuit design that comprises the via placement layout and that is adapted to be used to manufacture a corresponding integrated circuit.