Patent ID: 9312189
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method for fabricating an integrated circuit, the method comprising: providing a semiconductor substrate with first gates overlying second conductive type regions in the semiconductor substrate and second gates overlying first conductive type regions in the semiconductor substrate; performing a first ion implantation to form halo implant regions in the semiconductor substrate adjacent selected second gates; after performing the first ion implantation, performing a second ion implantation to form halo implant regions in the semiconductor substrate adjacent selected first gates; after performing the second ion implantation, performing a third ion implantation to form extension implant regions in the semiconductor substrate adjacent the selected first gates; and after performing the third ion implantation, performing a fourth ion implantation to form extension implant regions in the semiconductor substrate adjacent the selected second gates.