Patent ID: 9525422
Filing Date: 2016-12-20
CPC Classification: G11C,H03K

Claim Text:
1. A reconfigurable semiconductor integrated circuit comprising: a plurality of memories connected in parallel; a logic circuit whose logic is defined according to data output of one of the memories; a signal output unit including a plurality of output terminals corresponding to the respective memories, each output terminal outputting either a selection signal for enabling the data output or a non-selection signal for disabling the data output to the logic circuit, the signal output unit being configured to output the selection signal in a cyclic manner over the output terminals so that one of the output terminals outputs the selection signal and the others output the non-selection signal; and a switching unit configured to set a route between a first output terminal of the output terminals and a second output terminal of the output terminals either to an open state or a closed state, the route bypassing at least a single output terminal.