Patent ID: 9483271
Filing Date: 2016-11-01
CPC Classification: G06F

Claim Text:
1. A method for predicting a branch target T in a microprocessor, the method which is performed by a processor device comprises the steps of: maintaining a compressed count cache table (CTABLE) of branch targets indexed using a function combining a branch address and a branch history vector for each of the branch targets, wherein entries in the CTABLE contain only low-order bits of each of the branch targets in combination with one or more index bits I; obtaining a given one of the entries from the CTABLE related to a given one of the branch targets; determining from the index bits I in the given entry whether A) high-order bits of the given branch target are equal to the branch address, or B) the high-order bits of the given branch target are contained in an auxiliary cache table (HTABLE); and when A applies: predicting the branch target T using only the low-order bits of the given branch target, or when B applies: accessing the high-order bits of the given branch target via the HTABLE and predicting the branch target T using one or more of the low-order bits of the given branch target and the high-order bits of the given branch target.