Patent ID: 9389925
Filing Date: 2016-07-12
CPC Classification: G06F,Y02D

Claim Text:
1. In a computer system having one or more processors operatively coupled to one or more memory devices, a method for achieving low grace-period latencies in an energy efficient environment in which processors with Read-Copy Update (RCU) callbacks are allowed to enter low power states, comprising: periodically generating RCU callbacks as part of shared data element update Operations, said callbacks representing requests for deferred destruction of shared data elements following an RCU grace period; maintaining said RCU callbacks on a per-processor basis: for each of said one or more processors that maintains RCU callbacks, assigning different RCU grace period numbers to different groups of said processor's RCU callbacks; periodically starting new RCU grace periods and ending old RCU grace periods; and as said old RCU grace periods end, invoking said groups of RCU callbacks having corresponding assigned RCU grace period numbers.