Patent ID: 9418716
Filing Date: 2016-08-16
CPC Classification: G11C

Claim Text:
1. A circuit, comprising: a first delay circuit configured to delay a memory clock by a simulated row decoding period to produce a first output signal, the first delay circuit including a logic-power-domain portion configured to delay a memory clock signal to provide a delayed signal, the first delay circuit further including a first level-shifter configured to level shift the delayed signal according to a memory power supply voltage to produce the first output signal; a second delay circuit configured to delay the memory clock signal by a simulated column decoding period to produce a second output signal, the second delay circuit including a second level-shifter configured to level shift the memory clock signal into a memory-power-domain dummy write clock, the second delay circuit further including a memory-power-domain portion configured to delay the dummy write clock into the second output signal; and a logic circuit configured to process the first output signal and the second output signal to assert a logic output signal responsive to a completion of both the simulated row decoding period and the simulated column decoding period.