Patent ID: 9324405
Filing Date: 2016-04-26
CPC Classification: G11C

Claim Text:
1. A ferroelectric memory comprising: a plurality of ferroelectric memory cells, each ferroelectric memory cell comprising a ferroelectric capacitor characterized by a maximum charge that can be stored in said ferroelectric capacitor; a write line; a read line; a plurality of ferroelectric memory cell select buses, one of said ferroelectric memory cell select buses corresponding to each of said ferroelectric memory cells, wherein each of said ferroelectric memory cells comprises first and second gates for connecting said ferroelectric memory cells to said read line and said write line, respectively, in response to signals on said ferroelectric memory cell select bus corresponding to that ferroelectric memory cell; a write circuit that causes a charge to be stored in said ferroelectric capacitor of said ferroelectric memory cell currently connected to said write line, said charge having a value determined by a data value input to said write circuit, said charge being independent of said maximum charge of said ferroelectric capacitor; and a read circuit that measures said charge stored in said ferroelectric capacitor of said ferroelectric memory cell currently connected to said read line to generate an output value, said output value corresponding to a data value currently stored in said ferroelectric capacitor.