Patent ID: 9390766
Filing Date: 2016-07-12
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: a wiring substrate having an upper surface, a plurality of control chip electrodes formed over the upper surface, a plurality of memory chip electrodes formed over the upper surface, a lower surface opposite the upper surface, a plurality of external terminal electrodes formed over the lower surface, a plurality of vias formed between the upper surface and the lower surface, and a plurality of via wirings formed inside of the vias, respectively, and electrically connecting the control chip electrodes and the memory chip electrodes with the external terminal electrodes, respectively; a control chip having a reference potential generation circuit, a chip front surface, a plurality of electrode pads formed over the chip front surface, a chip rear surface on the opposite side of the chip front surface, and mounted over the upper surface of the wiring substrate; a plurality of conductive members electrically connecting the electrode pads of the control chip with the control chip electrodes, respectively; and a plurality of external terminals connected to the external terminal electrodes of the wiring substrate, respectively, wherein the electrode pads have a first reference potential pad electrically connected to the reference potential generation circuit, wherein the control chip electrodes have a first reference potential electrode electrically connected to the first reference potential pad of the control chip, wherein the memory chip electrodes have a second reference potential electrode electrically connected to a second reference potential pad of a memory chip, wherein a reference potential terminal electrode of the external terminal electrodes, which is electrically connected to a bypass capacitor, is electrically connected to the first reference potential electrode and the second reference potential electrode through a reference potential wiring of wirings formed in the wiring substrate and a reference potential via wiring of the via wirings, respectively, and wherein the reference potential via wiring is connected only at a connecting part of the reference potential wiring where a distance on the reference potential wiring from the connecting part to the second reference potential electrode is shorter than a distance on the reference potential wiring from the connecting part to the first reference potential electrode.