Patent ID: 9385213
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, the method comprising: forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor; forming a first drain region and a first source region for the first type transistor in the first diffusion area; forming a second drain region and a second source region for the second type transistor in the second diffusion area; forming a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction; and forming a first metallic layer, a second metallic layer, and a third metallic layer, wherein the first metallic layer is electrically coupled with the first source region, the second metallic layer is electrically coupled with the first drain region and the second drain region, the third metallic layer is electrically coupled with the second source region, the first metallic layer and the first diffusion area are overlapped by a first distance in the routing direction, the second metallic layer and the first diffusion area are overlapped by a second distance in the routing direction, the first distance is larger than the second distance, the third metallic layer and the second diffusion area are overlapped by a third distance in the routing direction, the second metallic layer and the second diffusion area are overlapped by a fourth distance in the routing direction, and the third distance is larger than the fourth distance.