Patent ID: 9478558
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A method of fabricating a memory device, comprising: forming a stack including an alternating plurality of material layers and insulator layers over a substrate; forming a memory opening extending through the stack; forming a first blocking dielectric layer in the memory opening and over the stack; forming a continuous material layer over the first blocking dielectric layer; forming a spacer by anisotropically etching the continuous material layer, wherein a top surface of a horizontal portion of the first blocking dielectric layer is physically exposed within an opening in the spacer; etching the horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the spacer, whereby a top semiconductor surface of the substrate is physically exposed at a bottom of the memory opening; forming a memory material layer comprising a charge trapping material or patterned conductive material portions over the top semiconductor surface of the substrate and over a sidewall of the spacer within the memory opening after the continuous material layer is patterned into the spacer; and forming a tunneling dielectric layer and a semiconductor channel over the memory material layer.