Patent ID: 9236476
Filing Date: 2016-01-12
CPC Classification: G11C,H01L

Claim Text:
1. An apparatus comprising: a semiconductor substrate; a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes: wherein the first and second channel layers define a two-channel region of the fin structure that corresponds to a first portion of the first channel layer over which the second channel layer is disposed above the first channel layer, and a one-channel region of the fin structure that corresponds to a second portion of the first channel layer over which the second channel layer is not disposed above the first channel layer, a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for the first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for the second transistor.