Patent ID: 9287857
Filing Date: 2016-03-15
CPC Classification: H03K

Claim Text:
1. A semiconductor device comprising: a first inverter; a first switch coupled between an input terminal of the first inverter and a data input terminal; first and second p-channel MOS field-effect transistors coupled in series between a power supply voltage node and an input terminal of the first inverter; first and second n-channel MOS field-effect transistors coupled in series between the input terminal of the first inverter and a reference potential node; a first capacitance element coupled to an interconnection node of the first and second n-channel MOS field-effect transistors; and a second switch coupled in series to the first capacitance element, wherein the first capacitance element and the second switch are coupled in series between the interconnection node of the first and second n-channel MOS field-effect transistors and an output terminal of the first inverter, wherein gates of the first p-channel MOS field-effect transistor and the second n-channel MOS field-effect transistor are coupled to the output terminal of the first inverter, wherein gates of the second p-channel MOS field-effect transistor and the first n-channel MOS field-effect transistor are coupled to nodes of clock signals which are inverted to each other, wherein the second p-channel MOS field-effect transistor and the first n-channel MOS field-effect transistor are turned off when the first switch is turned on, wherein the second p-channel MOS field-effect transistor and the first n-channel MOS field-effect transistor are turned on when the first switch is turned off, wherein the second switch is turned off when the first switch is turned on, and wherein the second switch is turned on when the first switch is turned off.