Patent ID: 9417818
Filing Date: 2016-08-16
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor memory comprising: a plurality of memory blocks which each includes a group of memory cells arranged at positions where a group of word lines and a group of bit lines intersect and connected to a common source line; each memory cell, of the group of memory cells, including a gate directly connected to a word line of the group of word lines, a drain directly connected to a bit line of the group of bit lines and a source directly connected to the common source line; the plurality of memory blocks sharing the group of word lines; each common source line, of the plurality of memory blocks, being separated from one another; and a circuit which supplies first voltage at program operation time to a first common source line of a first memory block, of the plurality of memory blocks, including a memory cell to be programmed; and which supplies second voltage different from the first voltage at the program operation time to a second common source line of a second memory block, of the plurality of memory blocks, not including the memory cell to be programmed, wherein: each memory cell is a p-channel transistor; and at the program operation time the circuit supplies the second voltage to the second common source line of the second memory block, of the plurality of memory blocks, not including the memory cell to be programmed, the second voltage being increased by capacitance coupling between a well in which the second memory block is formed and a source junction of a memory cell in the second memory block.