Patent ID: 9494618
Filing Date: 2016-11-15
CPC Classification: G01R,H01L

Claim Text:
1. An apparatus for testing and packaging semiconductor dies, comprising: a package having a wafer side positionable to face toward a device under test, and an inquiry side facing away from the wafer side, wherein the package is suitable for packaging the device under test to create a tested packaged die; a plurality of wafer side nanospike pads carried by the package at the wafer side of the package; and a plurality of nanospikes carried by the nanospike pads of the package, wherein individual nanospike pads each carry multiple nanospikes, wherein individual nanospikes project directly from the nanospike pads, wherein the nanospikes form an intermetallic bond with solderballs of the device under test, wherein intermetallic bonds are formed by melting and resolidifying to form a tested packaged die that successfully passed a test using signals and power from a tester, and wherein the intermetallic bonds comprise nanospike material diffused into contact structures of the tested packaged die.