Patent ID: 9391025
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: first and second adjacent semiconductor dies; a silicon bridge structure electrically coupling the first and second semiconductor dies, and comprising a plurality of layers of conductive traces disposed above a substrate, a first pair of ground traces disposed in a first of the plurality of layers of conductive traces, a signal trace disposed in a second of the plurality of layers of conductive traces, below the first layer, and a second pair of ground traces disposed in a third of the plurality of layers of conductive traces, below the first layer; a plurality of package routing layers, wherein the silicon bridge structure is disposed in one of the package routing layers, the first and second die are disposed on the plurality of package routing layers, and the first die is electrically coupled to an uppermost metallization layer of the plurality of package routing layers by a plurality of conductive contacts; one or more discrete metal planes disposed at the uppermost metallization layer, each metal plane located, from a plan view perspective, at a corner of a perimeter of the first die; and microstrip routing disposed at the uppermost metallization layer, from the plan view perspective, outside of the perimeter of the first die.