Patent ID: 9343566
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate that includes a channel region; a gate insulating film formed on the channel region of the semiconductor substrate; a gate electrode formed on the gate insulating film; a source region of a first conductivity type formed in the semiconductor substrate; a drain region of the first conductivity type formed in the semiconductor substrate; a drift region of the first conductivity type formed between the channel region and the drain region, the drift region having an impurity concentration lower than an impurity concentration of the drain region; a first semiconductor region of a second conductivity type opposite to the first conductivity type that encloses the source region, the drift region and the drain region, and includes the channel region in a plan view; a first shield wiring formed above the semiconductor substrate and electrically connected to the first semiconductor region; and a second shield wiring formed above the first shield wiring and electrically connected to the first shield wiring, wherein the source region includes a first portion that is not covered by the gate electrode in a plan view; the first portion is enclosed by the first shield wiring together with the gate electrode in a plan view, and the drift region is enclosed by an inner edge of the second shield wiring in a plan view, the inner edge being located above the first shield wiring.