Patent ID: 9424889
Filing Date: 2016-08-23
CPC Classification: G11C,H01L

Claim Text:
1. A static random access memory (SRAM) cell in a chip, comprising: a storage circuit having a first data node, a second data node, a supply voltage node, and a first reference voltage node; a write port circuit coupled with the first data node and having a first write word line node and a first write bit line node; a first read port circuit coupled with the first data node and having a first read word line node, a first read bit line node, and a second reference voltage node; a second read port circuit coupled with the second data node and having a second read word line node, a second read bit line node, and a third reference voltage node; a plurality of first conductive lines extending along a first direction in a first metal layer of the chip, the plurality of first conductive lines comprising: a plurality of second conductive lines extending along a second direction in a second metal layer of the chip and over the first metal layer, the plurality of second conductive lines comprising: a plurality of third conductive lines extending along the first direction in a third metal layer of the chip and over the second metal layer; and a plurality of fourth conductive lines extending along the second direction in a fourth metal layer of the chip and over the third metal layer, the plurality of fourth conductive lines comprising: