Patent ID: 9478312
Filing Date: 2016-10-25
CPC Classification: G06F,G11C,Y02D

Claim Text:
1. An address circuit comprising: a first barrel shifter configured to shift high order bits and low order bits of an address in a rightward direction by a number of bits; a second barrel shifter configured to shift the low order bits of the address in a leftward direction by the number of bits after the first barrel shifter shifts the high order bits and the low order bits; a third barrel shifter configured to shift the high order bits and the low order bits of the address in the leftward direction by the number of bits after the second barrel shifter shifts the low order bits; an arithmetic logic unit (ALU) to modify a value of the address after the third barrel shifter shifts the high order bits and the low order bits; a fourth barrel shifter configured to shift the high order bits and the low order bits of an address in the rightward direction by a number of bits after the ALU increments the value of the address; a fifth barrel shifter configured to shift the low order bits of the address in the rightward direction by the number of bits after the fourth barrel shifter shifts the high order bits and the low order bits; and a sixth barrel shifter configured to shift the high order bits and the low order bits of the address in the leftward direction by the number of bits after the fifth barrel shifter shifts the low order bits.