Patent ID: 9372766
Filing Date: 2016-06-21
CPC Classification: G06F

Claim Text:
1. A computer-implemented method comprising: generating a library function for execution on each parallel-processing node of a plurality of parallel-processing nodes executing a simulation controlled by a simulator, the library function a computational and communication load balanced for the plurality of parallel-processing nodes and instrumented to collect timing statistics from each particular parallel-processing node and to transmit the collected timing statistics to a software agent; receiving timing statistics from each of the plurality of parallel-processing nodes; determining, using the received timing statistics collectively, that a faulty parallel-processing node exists, wherein the determination compares the received timing statistics for each particular parallel-processing node against an average timing value calculated for the plurality of parallel-processing nodes against a predetermined threshold; signaling the simulator to checkpoint and stop the simulation executing on the parallel processing nodes; and removing the faulty parallel-processing node from parallel processing nodes available to execute the simulation.