Patent ID: 9285399
Filing Date: 2016-03-15
CPC Classification: G01R,H02M

Claim Text:
1. A method of estimating cycle average current for an output phase of a switching regulator during pulse width modulation (PWM) cycles of the switching regulator, each PWM cycle having an on-portion and an off-portion, the method comprising: measuring a low-side transistor current of the output phase during the off-portion for each PWM cycle; estimating a pulse width for the on-portion for the present PWM cycle; estimating a cycle average current for the present PWM cycle based on the low-side transistor current measured during the off-portion for the immediately preceding PWM cycle and the pulse width estimate for the on-portion for the present PWM cycle; comparing the cycle average current estimated for each PWM cycle to a measured phase current for the same PWM cycle upon completion of that PWM cycle to generate a prediction error; incorporating the cycle average current estimate into a response of the switching regulator; and compensating for the prediction error so that a steady-state response of the switching regulator is unaffected by the prediction error.