Patent ID: 9467161
Filing Date: 2016-10-11
CPC Classification: H03M

Claim Text:
1. A low-power, high-speed successive approximation register (SAR) analog-to-digital converter (ADC) comprising: a bootstrapping unit configured to receive inputs of first and second analog signals; a double-bit output SAR analog-to-digital conversion unit configured to output a two-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit; and a single-bit output SAR analog-to-digital conversion unit configured to output a one-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit; wherein the bootstrapping unit includes first to third bootstrapping switch pairs, wherein the first and second bootstrapping switch pairs apply the first and second analog signals to the double-bit output SAR analog-to-digital conversion unit, and wherein the third bootstrapping switch pair applies the first and second analog signals to the single-bit output SAR analog-to-digital conversion unit.