Patent ID: 9348620
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. A system comprising: a processor programmed to initiate executable operations comprising: invoking a first operation for a concurrent linked queue of an interpretive program using a Just-In-Time (JIT) compiler of a virtual machine, wherein the first operation does not use hardware transactional memory; determining whether a data processing system executing the virtual machine supports hardware transactional memory; responsive to determining that the data processing system does support hardware transactional memory, detecting, within the first operation, a call to a second operation that is configured, in byte code, to return an indication of a failed hardware transaction; and responsive to detecting the second operation, generating a machine code implementation of the first operation that includes a machine code implementation of the second operation, wherein the machine code implementation of the second operation is an implementation of the first operation that does use hardware transactional memory in lieu of machine code for the byte code of the second operation that returns an indication of the failed hardware transaction.