Patent ID: 9374049
Filing Date: 2016-06-21
CPC Classification: H03F

Claim Text:
1. A differential amplifier comprising: an operational amplifier (OP AMP) having an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal; a first feedback capacitor connected to the non-inverting input terminal and the inverting output terminal of the OP AMP; a second feedback capacitor connected to the inverting input terminal and the non-inverting output terminal of the OP AMP; a first transistor having four terminals and connected to the non-inverting input terminal and the inverting output terminal of the OP AMP, wherein the four terminals include a source terminal, a drain terminal, a gate terminal and a bulk terminal; and a second transistor having four terminals and connected to the inverting input terminal and the non-inverting output terminal of the OP AMP, wherein the four terminals include a source terminal, a drain terminal, a gate terminal and a bulk terminal, wherein one of the source and drain terminals of the first transistor and a gate terminal thereof are connected to the inverting output terminal of the OP AMP, and the other one of the source and drain terminals and the bulk terminal are connected to the non-inverting input terminal of the OP AMP, and one of the source and drain terminals of the second transistor and a gate terminal thereof are connected to the non-inverting output terminal of the OP AMP, and the other one of the source and drain terminals and a bulk terminal are connected to the inverting input terminal of the OP AMP; wherein the first and second transistors are PMOS transistors, the source and drain terminals of the first and second transistors are respectively connected to a pair of P regions that are formed by injecting a p-type dopant into an N-type semiconductor substrate, the first and second transistors are formed with channels between the pair of P regions and include gate terminals that protrude above the channels, and the first and second transistors include bulk regions on the N-type semiconductor substrate that are connected to the bulk terminals.