Patent ID: 9337334
Filing Date: 2016-05-10
CPC Classification: H01L,H03K

Claim Text:
1. A semiconductor structure comprising: a semiconductor nanowire located on a substrate and including a channel region; an upper dielectric material portion located on a top surface of said channel region; a lower dielectric material portion located underneath a bottom surface of said channel region; a gate dielectric contacting said channel region, said upper dielectric material portion, and said lower dielectric material portion; and a ferromagnetic gate structure located on said gate dielectric, wherein said semiconductor nanowire further includes: a source region contacting a sidewall of said channel region; and a drain region contacting another sidewall of said channel region, and wherein said channel region has a doping of a first conductivity type at a first dopant concentration, said source region has a doping of a second conductivity type at a second dopant concentration that is greater than said first dopant concentration, and said drain region includes dopants at a third concentration that is greater than said first concentration, wherein said second conductivity type is the opposite of said first conductivity type.