Patent ID: 9502563
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate including a first region having a memory area and a second region having a logic area, the substrate extending in a horizontal direction of extension; a first active region defined in the memory area of the first region; a plurality of first gate electrodes on the first active region; a first inner spacer on a side surface of the first gate electrode; a first trench in the first active region between the first gate electrodes; a first strain-inducing pattern including a first intermediate edge extended laterally to the first gate electrode in the first trench; a second active region defined in the logic area of the second region; a plurality of second gate electrodes on the second active region; a second inner spacer on a side surface of the second gate electrode; a second trench in the second active region between the second gate electrodes; and a second strain-inducing pattern including a second intermediate edge extended laterally to the second gate electrode in the second trench; wherein the first intermediate edge is disposed below and between a side surface of the first gate electrode and an outer surface of the first inner spacer, wherein the second intermediate edge is disposed below and between a side surface of the second gate electrode and an outer surface of the second inner spacer; and further comprising: