Patent ID: 9411926
Filing Date: 2016-08-09
CPC Classification: G06F,Y02P

Claim Text:
1. A method of generating, based on a first netlist of an integrated circuit, a second netlist, the method comprising: generating layout geometry parameters for at least a portion of the first netlist of the integrated circuit, wherein the portion of the first netlist of the integrated circuit comprises a first device; generating a third netlist based on the first netlist and the layout geometry parameters; decomposing a description in the third netlist for modeling the first device into a description in a fourth netlist for modeling a plurality of secondary devices; and generating the second netlist based on the fourth netlist; wherein at least one of the above operations is performed by a computer; and at least one of the following configurations exists: the first device includes (a) a first gate electrode having a first length; or (b) a first oxide diffusion (OD) region having a first width; when the first device includes the first gate electrode having the first length: when the first device includes the first OD region having the first width: