Patent ID: 9379081
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A semiconductor device package, comprising: a first substrate with a die receiving opening and a first wiring circuit on a top surface of said substrate and a second wiring circuit on a bottom surface of said substrate, wherein a first contact conductive bump is formed on said first wiring circuit; a die with at least one bump structure on at least one of bonding pads formed on a bottom surface of said die, wherein said bump structure of said die is electrically connected to said first contact conductive bump of said first wiring circuit of said first substrate; a first adhesive layer on said bottom surface of said first substrate and said die, and filled into the gap between said die and said first substrate for adhering said die and said first substrate; and a second substrate with a die opening window and a third wiring circuit on a top surface of said second substrate and a fourth wiring circuit on a bottom surface of said second substrate, wherein a second contact conductive bump is formed on said fourth wiring circuit; and wherein said second contact conductive bump of said second substrate is electrically connected to said first contact conductive bump of said first wiring circuit of said first substrate; a second adhesive layer formed under said second substrate except said die opening window for adhering said die and said second substrate.