Patent ID: 9312360
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A structure comprising: a pedestal of an insulating material present over at least one layer of a semiconductor material that includes a punch through barrier layer and a semiconductor substrate, wherein the punch-through layer is present between the pedestal of the insulating material and the semiconductor substrate; at least one fin structure in contact with the pedestal of the insulating material; source and drain region structures on opposing sides of the at least one fin structure, at least one of the source and drain region structures comprising at least two epitaxial material layers, wherein a first epitaxial material layer of the at least two epitaxial layers is in contact with the punch through barrier layer of the at least one layer of semiconductor material, and a second epitaxial material layer of the at least two epitaxial layers is in contact with the at least one fin structure, the first epitaxial material layer being separated from the at least one fin structure by the second epitaxial material layer; and a gate structure present on the at least one fin structure.