Patent ID: 9412450
Filing Date: 2016-08-09
CPC Classification: G11C

Claim Text:
1. An operating method of a nonvolatile memory which includes a plurality of cell strings in a memory block, wherein the plurality of cell strings are arranged on a substrate in rows and columns and each of the cell strings includes a plurality of memory cells stacked in a direction perpendicular to the substrate, a ground selection transistor provided between the memory cells and the substrate, and a string selection transistor provided between the memory cells and a bit line, wherein two or more of the plurality of cells strings in the memory block are connected in common to the bit line, the operating method comprising: adjusting a threshold voltage of at least one first memory cell adjacent to the substrate in each cell string to be higher than a threshold voltage distribution of an erase state; reading a second memory cell located above the at least one first memory cell in each cell string; checking threshold voltages of first memory cells in the plurality of cell strings; and if the threshold voltages of the first memory cells in the plurality of cell strings are determined to have decreased, re-adjusting the threshold voltages of the first memory cells in the plurality of cell strings to be higher than those in the threshold voltage distribution corresponding to the erase state, wherein the at least one first memory cell in each cell string is a dummy memory cell.