Patent ID: 9501995
Filing Date: 2016-11-22
CPC Classification: G02F,G09G

Claim Text:
1. A liquid crystal display (LCD) comprising: an LCD panel comprising a plurality of pixels arranged in rows, pixels in each row arranged alternatively between odd and even pixels of the plurality of pixels; a timing controller having a plurality of switch enable lines and configured to enable data line switches; a source driving circuit configured to convert image data into data voltages and to control the plurality of pixels using the data voltages, the plurality of pixels being coupled to the source driving circuit by having each of the plurality of pixels coupled to a second data line of a plurality of second data lines, the data line switches coupling the plurality of second data lines to a first data line of a plurality of first data lines, the plurality of first data lines being coupled to the source driving circuit, several odd pixels of a row of pixels of the plurality of pixels being coupled to one first data line of the plurality of first data lines and several even pixels of the row of pixels being coupled to another one first data line of the plurality of first data lines; and a gate driving circuit configured to enable the plurality of pixels, the plurality of pixels receiving enable signals from a plurality of gate lines coupled to the gate driving circuit, the odd pixels of a first row of pixels being coupled to a first gate line of the plurality of gate lines, and the even pixels of the first row of pixels being coupled to a second gate line of the plurality of gate line, wherein a first enable signal of the enable signals for the first gate line partially overlaps a second enable signal of the enable signals for the second gate line so that a duration between a falling edge of the first enable signal for the first gate line and a raising edge of the second enable signal for the second gate line is substantially equal to a sum of durations of switch enable signals being applied to switch enable lines, of the plurality of switch enable lines, configured to enable the data line switches coupling to only the even pixels connected to the second gate line.