Patent ID: 9396951
Filing Date: 2016-07-19
CPC Classification: C23C,H01J,H01L

Claim Text:
1. A transistor device having a gate dielectric, a gate electrode, a source region and a drain region, wherein the gate dielectric is formed by a process comprising the steps of: forming a dielectric layer on a substrate in a first process chamber of a processing system, the first process chamber having a first pumping element configured to evacuate gas from the first process chamber; introducing nitrogen atoms in the dielectric layer using a plasma process in a second process chamber of the processing system, the second process chamber having a second pumping element configured to evacuate gas from the second process chamber; performing a thermal process in a third process chamber; transferring the substrate between the first process chamber, the second process chamber, and the third process chamber through a transfer chamber of the processing system, wherein the transfer chamber is connected to the first process chamber via a first vacuum lock door and connected the second process chamber via a second vacuum lock door, the transfer chamber having a gas distribution system and a third, distinct pumping element that maintain a pressure of about 3 Torr in the transfer chamber and actively purge the transfer chamber by flowing N introducing the substrate to the processing system through a load lock distinct from said transfer chamber to allow introduction and removal of the substrate from the processing system.