Patent ID: 9257185
Filing Date: 2016-02-09
CPC Classification: G11C

Claim Text:
1. A nonvolatile memory device comprising: a first memory cell configured to store a first data pattern; a second memory cell configured to be programmed using a program voltage; a first word line connected to the first memory cell; a second word line connected to the second memory cell, the first word line being adjacent to the second word line; and a coupling program control unit, the coupling program control unit being configured to perform a verification operation for verifying whether the first memory cell is programmed with the first data pattern, the verification operation providing to the first memory cell a verification voltage corresponding to the first data pattern, the coupling program control unit being configured to shift a threshold voltage of the first memory cell by programming the second memory cell using the program voltage at a time when the first memory cell is not being programmed using the program voltage, the coupling program control unit being configured to end programming the second memory cell when the verification operation on the first memory cell indicates a pass, wherein during a first program period, the coupling program control unit is configured to apply a first level of the program voltage to the second word line and then apply the verification voltage to not the second word line, but the first word line, the coupling program control unit is configured to apply a second level of the program voltage higher than the first level of the program voltage when the verification operation of the first memory cell following the first program period indicates a fail and apply the verification voltage to the first word line after applying the second level program voltage to the second word line.