Patent ID: 9311971
Filing Date: 2016-04-12
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; power circuitry that provides power to the device upon power up, the power circuitry comprising a first power up circuit that outputs a first power up signal and a second power up circuit that outputs a second power-up signal, wherein the second power up circuit includes a latching circuit; an output buffer that outputs data from the memory cells or an output buffer pad sourced data selectively by a first control signal, wherein the output buffer includes level shifting circuitry; and a DQ pull-up level shift circuit including a first transistor coupled to a power supply voltage and configured, during a power up mode when other circuitry within the pull-up level shift circuit powered by the first power up circuit has not been powered, to initialize a first cross coupled output of a cross-coupled pair of transistors too high to avoid an initial high signal on a second cross couple output, providing a signal to turn off and provide a pull up signal at an output.