Patent ID: 9438414
Filing Date: 2016-09-06
CPC Classification: H04L

Claim Text:
1. A hardware computational engine, comprising: a working memory configured to receive a first input message and a second input message; a plurality of switches coupled with the working memory and configured to transmit to the working memory the first input message, a first portion of the second input message, and a second portion of the second input message independently from the first portion; a context memory coupled with the working memory, wherein the context memory is configured to simultaneously store a first context corresponding to the first input message and a second context corresponding to the second input message; and a set of hardware computational elements coupled with the working memory and coupled with the context memory, wherein the set of hardware computational elements is configured to finish calculations for generating a first output digest based on the first input message and the first context after starting calculations for generating a second output digest based the second input message and the second context and before finishing the calculations for generating the second output digest.