Patent ID: 9281362
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate having a cell array region and a peripheral circuit region, the substrate including a plurality of first active regions defined by a first trench isolation region in the substrate in the cell array region, the plurality of first active regions each being aligned to extend longitudinally in a first direction in the cell array region, the plurality of first active regions being repeatedly disposed at first pitches in the first direction in the cell array region, the substrate including a second active region defined by a second trench isolation region in the substrate in the peripheral circuit region, the substrate including at least one deep trench isolation region defined by a portion of the second trench isolation region that is recessed in the substrate in the peripheral circuit region to a level lower than a level of other points of a bottom surface of the second trench isolation region in the substrate in the peripheral circuit region, the level of the at least one deep trench isolation region being recessed in the substrate lower than a bottom of an adjacent sidewall of the second active region, the at least one deep trench isolation region including at least one point in the substrate in the peripheral circuit region that is spaced apart in the first direction from a corresponding one of the plurality of first active regions, and the at least one deep trench isolation region including two deep trench isolation regions that are spaced apart from each other by the first pitch in the first direction.