Patent ID: 9256438
Filing Date: 2016-02-09
CPC Classification: G06F

Claim Text:
1. A processor comprising: a pipeline including front end pipeline portion, an execution pipe, and a back end pipeline portion; an architectural register file (ARF) having a size such that reading a location in the ARF requires more than a single processor cycle; a working register file (WRF) wherein a lifetime of an entry in said WRF may continue after an originating instruction that generated said entry is retired; wherein the front end pipeline portion comprises an issue stage configured to issue instructions to said execution pipe, and a pre-issue stage configured to read early an ARF location to obtain a first value of an operand for a particular instruction that issues in the issue stage so that said operand is available upon issue of the particular instruction by the issue stage; wherein said processor is configured to monitor said ARF location after said read early to determine whether said ARF location is written to after said read early and before said particular instruction is issued by said issue stage; wherein, if said ARF location is not written to after said read early and before said particular instruction is issued by said issue stage, the issue stage is configured to issue said particular instruction for operation on said first value of said operand; wherein, if said ARF location is written to after said read early and before said particular instruction is issued by said issue stage, the processor is configured to,