Patent ID: 9383759
Filing Date: 2016-07-05
CPC Classification: G05F

Claim Text:
1. A system for calibrating a reference voltage signal in an integrated circuit, comprising: a digital-to-analog converter (DAC) that receives first and second sets of digital control words and generates corresponding first and second sets of control voltage signals during first and second calibration cycles, respectively; a voltage monitoring circuit, comprising: a digital controller, connected to the voltage monitoring circuit and the DAC, that receives the first and second monitor voltage signals and generates the first and second sets of digital control words in the first and second calibration cycles, respectively, such that a first reference voltage digital control word of the first set of digital control words corresponds to the first reference voltage signal at the end of the first calibration cycle and a second reference voltage digital control word corresponds to the second reference voltage signal at the end of the second calibration cycle, generates a voltage margin word that corresponds to a difference between the first and second reference voltage digital control words at the end of the first and second calibration cycles, generates a voltage trimming signal based on a comparison between the voltage margin word and at least one of predetermined maximum and minimum reference voltage words and calibrates the second reference voltage signal based on the voltage trimming signal.