Patent ID: 9244846
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. A method of data processing, comprising: in a data processing system implementing memory transactions and a weak consistency memory model for a distributed shared memory system, concurrently executing on a plurality of processor cores one or more transactional memory instructions within a pending memory transaction and one or more non-transactional memory instructions including a non-transactional store instruction, wherein the plurality of processor cores includes at least three processor cores; committing the pending memory transaction to the distributed shared memory system of the data processing system only in response to both: all accesses to the distributed shared memory system caused by constituent memory instructions of the pending memory transaction completing atomically without a conflict with any memory access of any other thread; and enforcement of causality of the non-transactional store instruction with respect to the pending memory transaction by ensuring visibility to all of the plurality of processor cores of a value stored to the distributed shared memory system by the non-transactional store instruction and read by a transactional load instruction within the pending memory transaction.