Patent ID: 9391178
Filing Date: 2016-07-12
CPC Classification: G11C,H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising the steps of: defining, in a main surface of a semiconductor substrate, first through third element formation regions using isolation insulating films; forming a first gate electrode over a surface of the first element formation region; forming a second gate electrode between one of side walls of the first gate electrode and the surface of the first element formation region with an insulating film holding charges being disposed therebetween; forming an offset spacer over a side wall of the second gate electrode; after forming the offset spacer, forming a third gate electrode over a surface of the second element formation region and forming a fourth gate electrode over a surface of the third element formation region; implanting a predetermined impurity into a first area of the first element formation region which is located on a side on which the second gate electrode of the first and second gate electrodes is disposed to form an impurity region of a predetermined conductivity type; and removing the offset spacer.