Patent ID: 9311437
Filing Date: 2016-04-12
CPC Classification: G06F

Claim Text:
1. A method for processing data in a transaction through a virtual bus structure model after inclusion of the virtual bus structure model in one or more system designs including one or more programmable processors, the virtual bus structure model in the system designs located between a sender of data and a receiver of data, wherein the sender of data is configured to write data through the transaction and the receiver of data is configured to read data through the transaction, the method comprising: determining a number of data beats to commit to supply from a sender of data to a receiver of data; marking a data channel as busy; indicating a simulated time at which the first of the committed data beats will be available from the sender of data; signaling the receiver of data that the number of data beats is available; determining a number of data payloads needed to transfer the number of data beats; determining the point in simulated time at which the last of the data beats will be accepted by the receiver of data; and signaling the sender of data the acceptance of a data payload by the receiver of data, wherein the sender of data sends the data within the committed data beats ahead of simulation time to a receiver of data without compromising cycle accuracy of the data.