Patent ID: 9304569
Filing Date: 2016-04-05
CPC Classification: G06F,Y02D

Claim Text:
1. A method for changing performance states of a processor, comprising: receiving a desired end performance state for a processor, wherein the desired end performance state is associated with an end state minimum voltage; determining a plurality of intermediate performance states for the processor, wherein the plurality of intermediate performance states include performance states for the processor that are between a current performance state of the processor and the desired end performance state, and wherein each of the plurality of intermediate performance states are associated with respective intermediate state minimum voltages; initiating a voltage reduction of a provided voltage to the processor to provide the end state minimum voltage; determining that the provided voltage has reached each respective intermediate state minimum voltage plus an offset voltage using a sub-step timer that provides a first slew time that is required for the provided voltage to reach each respective intermediate state minimum voltage plus the offset voltage; changing the performance state of the processor to each intermediate performance state of the plurality of intermediate performance states in response to determining that the provided voltage has reached each respective intermediate state minimum voltage plus the offset voltage such that the voltage reduction through the plurality of intermediate performance states is continuous; determining that the provided voltage has reached the end state minimum voltage plus an offset voltage using the sub-step timer that provides a second slew time that is required for the provided voltage to reach the end state minimum voltage plus the offset voltage; and changing the performance state of the processor to the end performance state in response to determining that the provided voltage has reached the end state minimum voltage plus the offset voltage such that the voltage reduction from one of the plurality of intermediate performance states to the end performance state is continuous.