Patent ID: 9362420
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A transistor structure for electrostatic discharge (ESD) protection, comprising: a substrate; a single doped well disposed in the substrate, wherein the single doped well comprises a first conductive type dopant; a first doped region disposed in the substrate and encompassed by the single doped well, wherein the first doped region is floating and comprises the first conductive type dopant and a plurality of sub first doped regions; a single second doped region disposed in the substrate and encompassed by the single doped well, wherein the single second doped region comprises a second conductive type dopant, each of the sub first doped regions is surrounded by the single second doped region and the single doped well from topview and a gap is disposed between the single second doped region and each of the sub first doped regions; and a third doped region disposed in the substrate and encompassed by the single doped well, wherein the third doped region comprises the second conductive type dopant.