Patent ID: 9529596
Filing Date: 2016-12-27
CPC Classification: G06F

Claim Text:
1. An apparatus comprising: an out-of-order instruction fetch unit to retrieve a plurality of dependent instructions for execution from a multi-strand representation of a sequential program listing; a plurality of registers to store data; an instruction scheduling unit to schedule the execution of the plurality of dependent instructions based at least in part on an operand synchronization bit encoded within each of the plurality of dependent instructions for each operand, wherein the instruction scheduling unit is to include a scoreboard implemented via a hardware table, the scoreboard is to contain a status of each of the plurality of registers and is to indicate operand readiness for each of the plurality of dependent instructions via an availability bit and a busy bit per register, wherein when the availability bit for a register is set, it is to indicate that the register has been written to and is available for reading, and wherein when the busy bit for the register is set, it is to indicate that an instruction that has been issued by the instruction scheduling unit is updating and not written a value in the register, and wherein a synchronization bit for a source operand of an instruction when set is to indicate that both the availability bit and the busy bit for that source operand are to be cleared after reading that source operand value, a synchronization bit for a destination operand of an instruction is to indicate that the instruction with the destination operand is to not be issued until both the availability bit and the busy bit for that destination operand are cleared; and a plurality of execution units to execute at least a subset of the plurality of dependent instructions in parallel.