Patent ID: 9312033
Filing Date: 2016-04-12
CPC Classification: G11C

Claim Text:
1. A NOR-type flash memory device comprising: a memory array comprising at least one memory sector, wherein the at least one memory sector comprises a first sector bit line and a second sector bit line, wherein the memory array comprises a plurality of flash memory cells disposed on a matrix structure comprising a plurality of cell bit lines and a plurality of word lines arranged sequentially, and wherein the cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order; a row selection circuit configured to be driven to select a word line in the plurality of word lines corresponding to a row address; a column selection circuit configured to be driven to select a cell bit line in the plurality of cell bit lines corresponding to a column address; and a program driver circuit configured to be driven to provide a program voltage to the selected cell bit line, wherein the memory array comprises: the at least one memory sector comprises: the first connection switches are all turned on during the programming of a flash memory cell connected to any one of the second cell bit lines, and the second connection switches are all turned on during the programming of a flash memory cell connected to any one of the first cell bit lines.