Patent ID: 9312362
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) comprising: forming a well region of a first conductivity type in a substrate; forming a silicon oxide layer over at least a portion of the well region; forming a poly gate over the silicon oxide, the poly gate extend defining a first region in the well; forming a source region of a second conductivity type and a drain region of the second conductivity type, the source region being formed in a second portion of the well region and having a shallow portion thereof that is adjacent to the first region, the drain region being formed in a third portion of the well region and having a shallow portion thereof that is adjacent the first region and separate from the second region; forming spacers on the silicon oxide at the sides of the poly gate and over at least a portion of the shallow region of the source and the shallow region of the drain; processing the drain region and the source region not covered by the spacers to establish a desired level of high conductivity; forming a first interlayer dielectric over at least the first region, the second region and the third region; polishing the interlayer dielectric to expose a top surface of the poly gate; sacrificing the poly gate to form a cavity between the spacers; clearing the part of the silicon oxide within the cavity; etching selectively a recess into the well within the cavity, the recess having a bottom surface that is deeper than the depth of the shallow source region and the shallow drain region; forming an undoped channel epitaxial layer in the recess, the undoped channel epitaxial layer having a thickness that reduces statistical variations of threshold voltage (σV forming a high-K dielectric stack over the undoped channel epitaxial layer; and forming a metal gate layer over the high-K dielectric layer; the forming of the undoped channel epitaxial layer, the forming the high-K dielectric stack and the forming the metal gate layer all using processes that do not exceed 900° C.