Patent ID: 9472407
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A field effect transistor (FET) device, comprising: a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region; a gate stack arranged over the channel region of the fin, the gate stack comprising a gate a dielectric layer; a hardmask layer disposed on the top surface of the fin, over the channel region, the hardmask layer in contact with the gate stack; and sidewall spacers adjacent sidewalls of the gate stack, wherein bottom surfaces of the sidewall spacers are separated from a top surface of the fin; wherein a gap between bottom surfaces of the sidewall spacers and the top surface of the fin is filled by the dielectric layer of the gate stack, and the dielectric layer of the gate stack extends as a continuous liner that lines inner sidewalls of the sidewall spacers, fills the gap between the bottom surfaces of the sidewall spacers and the top surface of the fin, and forms a bottom layer that directly contacts the fin, and wherein the hardmask layer comprises first and second portions that also fill the gap between a bottom surface of the gate stack contacts and the top surface of the fin.