Patent ID: 9390981
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a first dielectric layer comprising a first section and a second section, said first section being over a first gate structure on a first semiconductor body of a first transistor and said second section being over a second gate structure on a second semiconductor body of a second transistor; forming a mask on said second section of said first dielectric layer; etching said first section of said first dielectric layer to form a first gate sidewall spacer on said first gate structure and to expose first source/drain regions of said first semiconductor body; forming first raised source/drain regions on said first source/drain regions such that said first gate sidewall spacer is between said first raised source/drain regions and said first gate structure; removing said mask; forming a second dielectric layer on said first gate structure, said first gate sidewall spacer and said first semiconductor body, said second dielectric layer further extending over said second section of said first dielectric layer; forming a third dielectric layer on said second dielectric layer; forming an additional mask on said third dielectric layer above said first gate structure, said first gate sidewall spacer and said first raised source/drain regions; etching said third dielectric layer and said second dielectric layer to expose said second section of said first dielectric layer; etching said second section of said first dielectric layer to form a second gate sidewall spacer on said second gate structure and to expose second source/drain regions of said second semiconductor body; and, forming second raised source/drain regions on said second source/drain regions such that said second gate sidewall spacer is between said second raised source/drain regions and said second gate structure.