Patent ID: 9397042
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A chip package comprising: a chip stack comprising at least one chip, the at least one chip comprising at least one switching component; and a thermal power plane comprising at least two substantially parallel dielectric layers patterned within substrate and having conductive connectors patterned therein, the at least two dielectric layers electrically connected by vias, wherein said vias are substantially perpendicular to the at least two dielectric layers, wherein one or more vias are stacked to reach from a top of the substrate to a bottom of the substrate and adapted for dissipating heat, wherein each of the vias electrically connects to a connector patterned within a dielectric layer of the at least two dielectric layers at a via connection, and wherein an inductor used in supplying power to the at least one chip is formed from the vias and from connectors electrically connecting via connections on each of the at least two dielectric layers.