Patent ID: 9304691
Filing Date: 2016-04-05
CPC Classification: G06F

Claim Text:
1. A memory system comprising: a memory controller; a first memory chip having a first I/O terminal; a second memory chip having a second I/O terminal; and a signal line connecting the first I/O terminal and the second I/O terminal commonly to the memory controller, the signal line being used to transmit data between the first memory chip and the memory controller and between the second memory chip and the memory controller, and to transmit a command from the memory controller to the first memory chip and the second memory chip; wherein the memory controller outputs a first read command to the first memory chip and then outputs a second read command to the second memory chip, outputs a first data transfer command to the first memory chip after receiving read completion notification associated with the first read command from the first memory chip, outputs a third read command to the first memory chip after receiving all data associated with the first read command from the first memory chip in response to the first data transfer command, and then outputs a second data transfer command to the second memory chip to receive data associated with the second read command from the second memory chip.