Patent ID: 9437595
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A structure, comprising a PFET having a source and a drain formed in a silicon layer of silicon-on-insulator substrate which comprises the silicon layer on a buried oxide layer; a first NFET having a source and a drain formed in the silicon layer of the silicon-on-insulator substrate; a second NFET having a source and a drain formed in the silicon layer of the silicon-on-insulator substrate; a barrier trench structure lined with gate dielectric material and filled with gate polysilicon material which also forms the first NFET, the second NFET and the PFET, the barrier trench structure extending from a top surface of the silicon layer to the buried oxide layer, and physically isolates the source of the first NFET from the drain of the second NFET; a strap material extending on a surface of the barrier trench structure on a same level of the first NFET and the second NFET and spanning the barrier trench structure to electrically connect the source of the first NFET to the drain of the second NFET; and a shallow trench isolation structure in the silicon layer which electrically isolates the PFET and the first NFET, wherein the gate dielectric material and gate polysilicon material form a gate electrode material of the first NFET and the second NFET.