Patent ID: 9349651
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor wafer, the semiconductor wafer comprising at least a first circuit region and a first scribe lane adjacent the first circuit region; and separating the first circuit region from the wafer to provide the semiconductor device, including providing a separation along the first scribe lane, wherein, the first circuit region comprises: wherein the first scribe lane region comprises: wherein the first gate structure and the second gate structure are formed from the same material layers, a height of a bottom surface of the second gate structure of the first scribe lane region is lower than a height of a bottom surface of the first gate structure of the first circuit region, which is disposed on the top surfaces of the first and second fin shaped active regions, and the second gate structure is directly formed on the second portion of the device insulating layer in the first scribe lane region.