Patent ID: 9502413
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate including an NMOSFET region and a PMOSFET region; a first gate structure and first spacers on sidewalls of the first gate structure in the NMOSFET region; a second gate structure and second spacers on sidewalis of the second gate structure in the PMOSFET region; a silicon pattern on a side of the first gate structure in the NMOSTET region, wherein the silicon pattern includes a first protruded portion having a top surface that is higher than a bottom surface of the first gate structure and a first facet, and wherein the first facet is slanted at a first predetermined angle with respect to an upper surface of the semiconductor substrate and forms a first concave portion with one of the first spacers; a silicon germanium pattern on a side of the second gate structure in the PMOSFET region, wherein the silicon germanium pattern includes a second protruded portion having a top surface that is higher than a bottom surface of the second gate structure, a second facet that is higher than the bottom surface of the second gate structure and a third facet that is opposite the second facet, and wherein the second facet is slanted at a second predetermined angle with respect to the upper surface of the semiconductor substrate and foi HIS a second concave portion with one of the second spacers; a blocking insulating layer extending along the top surface, the second facet and the third facet of the second protruded portion of the silicon germanium pattern and the second spacers, wherein a portion of the blocking insulating layer that extends along the one of the second spacers and the second facet of the second protruded portion of the silicon germanium pattern defines a recess in the second concave portion; a first insulating wing pattern in the first concave portion; a second insulating wing pattern in the recess; and an insulating interlayer on the first insulating wing pattern and the second insulating wing pattern, wherein the blocking insulating layer exposes the NMOSFET region, and wherein the insulatino interlayer directly contacts the blocking insulating layer and the silicon pattern and covers the first and second gate structures.