Patent ID: 9514420
Filing Date: 2016-12-06
CPC Classification: G06F,G06N,G11C

Claim Text:
1. A memory controller comprising: differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair, the differential data strobe signal pair comprised of a first signal and a second signal; single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair; circuitry to generate a gating signal for gating the first data strobe signal, the circuitry receiving a gate strobe signal indicative of an active data strobe window and generating the gating signal based on the second data strobe signal and the gate strobe signal, the gating signal indicative of an adjusted version of the active data strobe window; and training circuitry to calibrate the active data strobe window of the gate strobe signal based on the second data strobe signal.