Patent ID: 9396959
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device comprising: forming a first metal layer partially above a substrate; etching the first metal layer and the substrate using a first mask to form first wiring layers and a trench in the substrate; forming a first interlayer insulating film between and on the first wiring layers and planarizing the first interlayer insulating film so that the trench is filled and a top surface of the first interlayer insulating film is above the first wiring layers; forming a second metal layer partially above the first interlayer insulating film, and forming silicon oxynitride on the second metal layer; etching the silicon oxynitride and the second metal layer using a second mask to form second wiring layers partially above the first interlayer insulating film, and stop layers on the second wiring layers; forming a cover film between and on the first layers, so that a top surface of the cover film above a region between stop layers is higher than top surfaces of the stop layers, wherein the first cover film comprises silicon dioxide; and forming an embedded layer between the second wiring layers and stop layers, by polishing the cover film to the stop layers using chemical mechanical polishing (CMP).