Patent ID: 9300329
Filing Date: 2016-03-29
CPC Classification: H03M

Claim Text:
1. A system, comprising: a second error correction decoder configured to perform decoding associated with a second error correction code; a first error correction decoder configured to perform decoding associated with a first error correction code; an intersegment interleaver configured to perform intersegment interleaving on Ns first-corrected and second-corrected segments of data, Ns first-corrected and second-corrected first sets of parity information, and Ns first-corrected and second-corrected second sets of parity information to obtain intersegment interleaved data, wherein: a third error correction decoder configured to perform decoding associated with a third error correction code on the intersegment interleaved data and interleaved parity information to obtain at least third-corrected interleaved data; and an intersegment de-interleaver configured to perform de-interleaving on the third-corrected interleaved data.