Patent ID: 9455276
Filing Date: 2016-09-27
CPC Classification: G02F,H01L

Claim Text:
1. A thin film transistor array panel, comprising: a substrate; a drain electrode of a thin film transistor, on the substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connecting member on the second passivation layer and electrically separated from each other, wherein a first contact hole and a second contact hole are defined in the first and second passivation layers, the pixel electrode and the drain electrode are connected to each other through the second contact hole, the connecting member and the common electrode contact each other at the first contact hole defined in the first and second passivation layers, the common voltage line and the connecting member contact each other at the first contact hole at which the connecting member and the common electrode contact, and the connecting member contacts a side surface and an upper surface of the common electrode at an edge of the common electrode.