Patent ID: 9438247
Filing Date: 2016-09-06
CPC Classification: H03K

Claim Text:
1. An apparatus for simplification of input signal configured to input, to an MPU (Micro Processing Unit), an output of an input circuit at a PLC high speed counter module by converting the input to a single signal, the apparatus comprising: a first detector configured to output a single pulse in response to a rising edge or a falling edge by detecting the rising edge or the falling edge of a reference signal, which is a reference of adding or deducting calculation in response to an operation mode of the high speed counter module; a second detector configured to detect, from an output of the first detector, a pulse of rising edge or falling edge configured to perform an actual adding or deducting calculation in response to an operation mode of the high speed counter module; and a switching unit configured to output an output of the second detector using the adding or deducting calculation.