Patent ID: 9269418
Filing Date: 2016-02-23
CPC Classification: G06F,G11C

Claim Text:
1. An apparatus comprising: a dynamic random-access memory (DRAM) for storing data; refresh control circuitry configured to control said DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of said DRAM; and a refresh address sequence generator configured to generate a refresh address sequence of addresses identifying the order in which memory locations of said DRAM are refreshed during said refresh cycle; wherein said refresh address sequence generator is configured to generate said refresh address sequence with the addresses of at least a portion of said memory locations in a random order which varies from refresh cycle to refresh cycle; wherein said refresh address sequence generator has a normal mode in which said refresh address sequence is generated with said addresses of said at least a portion of said memory in a sequential order, and a random mode in which said refresh address sequence is generated with said addresses of said at least a portion of said memory locations in said random order; and wherein said refresh address sequence generator is configured to operate in said normal mode when processing circuitry configured to perform data processing is operating in a normal mode and to operate in said random mode when said processing circuitry is operating in a power saving mode; or wherein said refresh control circuitry is configured to detect accesses to said DRAM by said processing circuitry and said refresh address sequence generator is configured to operate in said normal mode when a detected volume of accesses is greater than a predetermined threshold and to operate in said random mode when said detected volume of accesses is less than said predetermined threshold.