Patent ID: 9251888
Filing Date: 2016-02-02
CPC Classification: G11C,H01L

Claim Text:
1. A Static Random Access Memory (SRAM) cell comprising: a first pull-up transistor and a second pull-up transistor; a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor; a first pass-gate transistor and a second pass-gate transistor, wherein each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors comprises a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate as a second source/drain region over the channel; a first isolated active region, wherein the first isolated active region acts as both the bottom plate of the first pull-down transistor and the bottom plate of the first pass-gate transistor; and a second isolated active region, wherein the second isolated active region acts as both the bottom plate of the second pull-down transistor and the bottom plate of the second pass-gate transistor.