Patent ID: 9436848
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. A method comprising: receiving a feature name for an integrated circuit comprising a security manager core and an additional component, wherein a feature provided by the additional component is associated with the feature name; receiving a specified number of bits associated with the feature name; mapping, by a processing device, the feature name to a feature address space of the security manager core based at least in part on the specified number of bits; and generating a hardware description logic (HDL) module for an extractor that is to connect to a feature bus comprising a plurality of feature bits of the feature address space based on the mapping, wherein the extractor is further to group a subset of the plurality of feature bits that are associated with a related feature into a sub-feature bus, and wherein the HDL module is usable to configure the security manager core for delivery of a payload associated with the feature name to the additional component.