Patent ID: 9471422
Filing Date: 2016-10-18
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A method for adaptive error correction in a memory system, the method comprising: reading data from a memory array of a non-volatile memory device in the memory system; checking, by error correcting logic, the data for at least one error condition stored in the memory array; based on determining that the at least one error condition exists, asserting a write-back indicator, by the error correcting logic, to request correction of the at least one error condition; based on determining that the at least one error condition does not exist, continuing accesses of the memory array without asserting the write-back indicator; saving write data into a write retry buffer based on receiving a write command for the non-volatile memory device; executing a write of the write data to store the write data in the memory array; and performing the reading of the data from the memory array as a write verify operation, wherein correction of the at least one error condition is performed as a write retry operation.