Patent ID: 9319060
Filing Date: 2016-04-19
CPC Classification: H03M

Claim Text:
1. An n-bit digital to analog converter comprising: a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream corresponding to bit values of the input bit stream at a time; a first delay circuit coupled to the receiving circuit to receive the first bit signal stream, the delay circuit configured to generate a second bit signal stream representing a version of the first bit signal stream delayed by a first period of time; a first current generation circuit coupled to the receiving circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current to a first output responsive to receiving the first bit signal stream, the first current corresponding to the first bit signal stream; and a second current generation circuit coupled to the delay circuit to receive the second bit signal stream, the second current generation circuit configured to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.