Patent ID: 9343185
Filing Date: 2016-05-17
CPC Classification: G06F,G11C

Claim Text:
1. An integrated circuit structure, comprising: a memory under repair having variable size blocks of failed memory addresses; a Ternary Content Addressable Memory (TCAM) comprising cells storing data values comprising ranges of addresses, said ranges of addresses corresponding to virtual addresses that, in combination with an offset value, point away from failed memory addresses in said memory under repair; a reduction circuit operatively connected to said TCAM, said reduction circuit producing a single output for each programmed range of said ranges of said addresses, based on a virtual address input to said TCAM; a priority encoder operatively connected to said reduction circuit, said priority encoder selecting a first programmed range from said reduction circuit; a random-access memory (RAM) operatively connected to said priority encoder, said RAM comprising cells storing data values comprising said offset value for each range of said ranges of said addresses; and an adder having two inputs, a first input being operatively connected to said RAM and a second input being operatively connected to a virtual address line,