Patent ID: 9237649
Filing Date: 2016-01-12
CPC Classification: H05K

Claim Text:
1. A wiring board comprising: a lower wiring conductor; an upper insulating layer laminated on the lower wiring conductor and having a via hole where a bottom surface is the lower wiring conductor; and a via conductor connected to the lower wiring conductor and filling the via hole, wherein the upper insulating layer includes at least a first resin layer laminated on the lower wiring conductor and a second resin layer laminated on the first resin layer, wherein the first resin layer has a Young's modulus of 5 to 10 GPa, and a thermal expansion coefficient of 0 to 40 ppm/° C. (30 to 150° C.), and contains 51 to 80 vol. % of an inorganic insulating filler, and the second resin layer has a Young's modulus of 0.5 to 4 GPa, the via hole has an annular groove formed by recessing an inner wall of the via hole over a whole circumference of the inner wall in a boundary between the first resin layer and the second resin layer, and the via conductor filling the via hole also fills the groove while invading in the groove.