Patent ID: 9335373
Filing Date: 2016-05-10
CPC Classification: G01R,G06F,G11C

Claim Text:
1. An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a differential point-to-point channel, the integrated circuit comprising: an inbound redrive circuit to receive and redrive signals on an inbound path of the differential point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the differential point-to-point channel; an outbound redrive circuit to receive and redrive signals on an outbound path of the differential point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the differential point-to-point channel; a deskew circuit to deskew data received from the two or more bit-lanes of the outbound path, wherein the deskew circuit is separate from the outbound redrive circuit; and a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive the deskewed data from the deskew circuit.