Patent ID: 9527727
Filing Date: 2016-12-27
CPC Classification: B81C,H01L

Claim Text:
1. A semiconductor package comprising: an ASIC die including a first surface and a first contact pad on the first surface; a cap including conductive and insulative layers, second and third surfaces, and second and third contact pads on the second surface; a MEMS die including fourth and fifth surfaces, the fourth surface of the MEMS die being coupled to the third surface of the cap, the fifth surface of the MEMS die being coupled to the first surface of the ASIC die; a first conductive wire having a first end coupled to the first contact pad of the ASIC die and a second end coupled to the second contact pad of the cap; a conductive bump coupled to the third contact pad of the cap; and molding compound over the first surface of the ASIC die, the first conductive wire, the cap, and the MEMS die, a portion of the conductive bump extending from a surface of the molding compound.