Patent ID: 9367461
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. Apparatus for processing data comprising: a plurality of memory access request sources configured to generate memory access requests and each having a cache memory configured to store one or more blocks of data values corresponding to respective blocks of memory addresses within a memory address space of a main memory; a coherency controller configured to receive from a store requester, that is one of said plurality of memory access request sources, a store request seeking: (i) to retrieve from said main memory to a cache memory of said store requester a target block of data from a target block of memory addresses within said memory address space, and (ii) to store one or more new data values within said target block of data retrieved to said cache memory of said store requester, and to provide to said store requester an exclusive right to access data values of said target block of data, wherein: said coherency controller is configured to provide of said exclusive right to said store requester before said target block of data is retrieved from said main memory to said cache memory of said store requester; and said store requester is enabled by said exclusive right to perform a further processing operation having an ordering constraint specifying that said further processing operation follows said storing of said one or more data values to said target block of data without waiting for said one or more data values to be stored to said target block of data.