Patent ID: 9501041
Filing Date: 2016-11-22
CPC Classification: G04F,H03K

Claim Text:
1. A duty cycle error detection device, comprising: a first digital code generator configured to generate a high digital code and a low digital code, which correspond to a length of a high level period of a clock signal and a length of a low level period of the clock signal, respectively, to determine a longer period and a shorter period between the high level period of the clock signal and the low level period of the clock signal based on the high digital code and the low digital code, to generate a sign signal representing the longer period of the clock signal, and to output one of the high digital code and the low digital code, which corresponds to the shorter period of the clock signal, as a first digital code; a clock delay circuit configured to generate a delay clock signal by delaying the clock signal for a time corresponding to the first digital code; and a second digital code generator configured to generate a duty error digital code, which corresponds to a length from a start of the longer period of the delay clock signal to an end of the longer period of the clock signal, based on a logic level of the sign signal.