Patent ID: 9349825
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method for producing a graphene transistor based on self-aligning technology comprising: forming a graphene layer on a substrate; depositing a metal layer on the graphene layer; covering a desired region on the metal layer with a first photoresist pattern; using the first photoresist pattern as a mask to remove a first exposed portion of the metal; using the first photoresist pattern as a mask to etch away an exposed portion of the graphene layer prior to removing the first photoresist; forming metal electrodes of a source electrode and drain electrode, wherein the source electrode and drain electrode are connected with a remaining portion of the metal layer corresponding to an active region; forming a gate mask pattern from a second photoresist to expose a second portion of the metal layer between the source electrode and the drain electrode; using the gate mask pattern of the second photoresist as a mask to remove the second portion of the exposed metal thereby exposing a portion of the graphene layer; forming a gate dielectric seed layer on the exposed portion of the graphene layer by using the gate pattern of the second photoresist as a mask; forming a gate dielectric on the gate dielectric seed layer; forming a gate electrode on the gate dielectric and then removing the photoresist.