Patent ID: 9397218
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a gate layer comprising (i) a first section and (ii) a second section, wherein the gate layer is non-linear such that the first section of the gate layer is offset with respect to the second section of the gate layer, and wherein the first section of the gate layer and the second section of the gate layer form a continuous section of the gate layer; and a first contact, a second contact, a third contact, and a fourth contact, wherein the first section of the gate layer is at (i) a first distance from the first contact and (ii) a second distance from the second contact, wherein the first distance is different from the second distance, wherein the second section of the gate layer is substantially at a third distance from each of the third contact and the fourth contact, wherein at least a part of the first section of the gate layer is included in a first transistor, wherein at least a part of the second section of the gate layer is included in a second transistor, and wherein the second transistor is different from and adjacent to the first transistor.