Patent ID: 9529590
Filing Date: 2016-12-27
CPC Classification: G06F

Claim Text:
1. A node processor for performing sparse matrix operations, comprising: memory configured to store one or more non-zero matrix elements of a first sparse matrix, one or more non-zero matrix elements of a second sparse matrix, and one or more matrix elements of a sparse results matrix mapped to the node processor; a matrix communications module adapted to communicate with other node processors, the matrix communications module exchanging, with the other node processors, non-zero matrix elements of one or more of the first sparse matrix, second sparse matrix, and sparse results matrix; and an arithmetic logic unit generating, in accordance with a matrix operation being performed, partial results based on the non-zero matrix elements of the first sparse matrix and on the non-zero matrix elements of the second sparse matrix stored in the memory, the arithmetic logic unit further generating a final value for each of the matrix elements of the sparse results matrix mapped to the node processor based on the partial results generated by the arithmetic logic unit and on partial results received from the other node processors.