Patent ID: 9246010
Filing Date: 2016-01-26
CPC Classification: G02F,H01L

Claim Text:
1. A thin film transistor substrate, comprising: a base substrate; and a plurality of thin film transistors provided on the base substrate; a protective insulating film provided so as to cover the thin film transistors; and a plurality of pixel electrodes provided on the protective insulating film so as to correspond to the thin film transistors, respectively, wherein each of the thin film transistors includes a gate electrode, a gate insulating film provided so as to cover the gate electrode, a semiconductor layer made of an oxide semiconductor and provided on the gate insulating film so as to overlap the gate electrode, and a source electrode and a drain electrode which are provided on the gate insulating film so as to be separated from each other on the semiconductor layer and so that a portion of the source electrode and a portion of the drain electrode are connected to the semiconductor layer, a channel region is provided in a portion of the semiconductor layer which is located between the source electrode and the drain electrode, a ratio of oxygen to all metal elements of a first portion of the semiconductor layer located at a lower surface of the semiconductor layer which is arranged directly on the gate insulating film is S a ratio of oxygen to all metal elements of second portions of the semiconductor layer located at an upper surface of the semiconductor layer at connection regions with the source and drain electrodes is S a ratio of oxygen to all metal elements of a third portion located at the upper surface portion of the semiconductor layer between the second portions is S the first portion is located between the second portions and the gate insulating film in a vertical direction at positions overlapping with the source and drain electrodes when seen from a top plan view, and the first portion is located between the third portion and the gate insulating film in the vertical direction at a position overlapping with the channel region in the top plan view.