Patent ID: 9236475
Filing Date: 2016-01-12
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate; a plurality of gate structures disposed on a top surface of the substrate, and including a first gate structure, a second gate structure and a third gate structure; an isolation layer disposed in the substrate; a first epitaxial layer disposed in the substrate, and disposed between the first gate structure and the second gate structure; a second epitaxial layer disposed in the substrate, and disposed between the second gate structure and the third gate structure; and a third epitaxial layer disposed in the substrate, and disposed between the third gate structure and the isolation layer, wherein each of the first epitaxial layer and the second epitaxial layer includes a v-shaped lower portion, wherein the third epitaxial layer includes an upper surface that is inclined with respect to the top surface of the substrate, wherein the upper surface of the third epitaxial layer is substantially flat, and wherein the upper surface of the third epitaxial layer contacts the third gate structure and the isolation layer.