Patent ID: 9310436
Filing Date: 2016-04-12
CPC Classification: G01R,G06F,H04L

Claim Text:
1. A system comprising on one integrated circuit: a seed memory coupled to provide a seed to a vector generator, the vector generator configured to generate a serial test vector according to the seed; at least one scan chain configured to apply data to, and observe data output of, logic of a first functional unit; a signature generator configured to generate a signature from observed data from the scan chain; a signature comparator configured to compare the signature to an expected signature in a signature memory; a state memorizer; a test register having at least a unit-idle flag settable by a processor of a system remainder and a unit-under-test flag settable by a test control unit, the test register accessible by the processor of the system remainder, and the test control unit being configured to operate a test sequence upon the first functional unit based on the unit-idle flag being set in the test register, the test sequence including setting the unit-under-test flag, using the state memorizer to save a state of the first functional unit, use the vector generator and signature generator with the scan chain to test the logic of the first functional unit, and then using the state memorizer to restore the state of the first functional unit, and then clearing the unit-under-test flag.