Patent ID: 9337252
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method for making a semiconductor device comprising: forming a first inter-level dielectric (ILD) layer above a semiconductor substrate; forming a first trench in the first ILD layer; filling the first trench with electrically conductive material; removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove; forming a filler dielectric material in the recess to define a second trench; filling the second trench with electrically conductive material to define an upper conductive member; forming a second ILD layer over the first ILD layer and upper conductive member; forming a first pair of vias through the second ILD layer, and underlying filler dielectric material to opposing lateral ends of the lower conductive member to define a first resistor therewith; and forming a second pair of vias through the second ILD layer to opposing lateral ends of the upper conductive member to define a second resistor therewith.