Patent ID: 9411912
Filing Date: 2016-08-09
CPC Classification: G06F

Claim Text:
1. A clock tree planner for an integrated circuit design, the clock tree planner comprising: a queue to: a power analyzer to analyze non-switching power and switching energy of clock subtrees to determine how to conserve power in the balanced clock tree network; a static timing analyzer to analyze clock subtrees to determine clock signal timing delay from one or more clocked elements at a lowest level of clock tree hierarchy in the clock subtrees to a clock signal input terminal of the clock subtrees; and an optimizer coupled to the queue, the power analyzer and the static timing analyzer, the optimizer to generate a hierarchical model using the balanced clock tree network, the non-switching power and switching energy, and the clock signal timing delay, and the optimizer to optimize subtree merger and clock signal paths of the balanced clock tree network in response to the non-switching power, the switching energy, and the clock signal timing delay of the clock subtrees, using the hierarchical model.