Patent ID: 9294419
Filing Date: 2016-03-22
CPC Classification: H04L

Claim Text:
1. A router chip comprising: a plurality of input-output (IO) interfaces, disposed proximate to a periphery of the router chip; each IO interface comprising an IO input and an IO output; a first plurality of interconnect paths, configured in a first two-dimensional (2D) mesh comprising a plurality of rows and columns, each interconnect path operatively coupled at opposing ends to an IO input and an IO output for a pair of IO interfaces disposed on opposite sides of the router chip, wherein a given row or column of the 2D mesh includes a pair of interconnect paths configured to transfer data in opposite directions; a first plurality of router nodes, each disposed at a respective row and column intersection, wherein each router node is configured to route data along a path either in the same direction via which the data arrived at the node or turn the data to be routed along a path in a direction perpendicular to the direction via which the data arrived at the node; and a plurality of additional interconnect paths operatively coupled between nodes along the periphery of the first 2D mesh.