Patent ID: 9396362
Filing Date: 2016-07-19
CPC Classification: G01C,G06G,H03D,H03F,H03G

Claim Text:
1. An analog multiplier circuit, comprising: a multiplier core comprising at least one differential transistor pair including a pair of emitter-coupled bipolar transistors, in which a coupled emitter point of the at least one differential transistor pair is set as a first input terminal, two bases of the differential transistor pair are set as a pair of second input terminals, and two collectors of the differential transistor pair are set as a pair of output terminals; a linearizer circuit comprising a linearizing transistor pair including a pair of bipolar transistors whose emitters are respectively connected to the second input terminal pair, in which each base and each collector of the linearizing transistor pair are each connected to a predetermined power source; and a correction current generating circuit for adding a correction current proportional to a current gain of each of the bipolar transistors of the at least one differential transistor pair to a signal applied to the second input terminal pair, the current gain being defined by a ratio of a collector current to an emitter current.