Patent ID: 9299719
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A method of forming a CMOS structure, the method comprising: providing a silicon-on-insulator substrate having a first substrate surface in a first region and a second substrate surface in a second region, wherein the first substrate surface and the second substrate surface are isolated by a shallow trench isolation; forming a first gate stack on the first substrate surface and a second gate stack on the second substrate surface; forming a first insulating layer on all exposed surfaces in the first and second regions; forming a second insulating layer on the first insulating layer in the first and second regions; etching the first insulating layer and the second insulating layer only in the second region to form a first set and a second set of insulating spacers on sidewalls of the second gate stack; forming raised epitaxial source and drain layers only on the second substrate surface; forming a hard mask layer on all exposed surfaces in the first and second regions, such that the hard mask layer covers unetched portions of the first insulating layer in the first region, and covers the first set and the second set of insulating spacers on sidewalls of the second gate stack, and the raised epitaxial source and drain layers on the second substrate; removing the hard mask layer only in the first region to expose the unetched first insulating layer; etching the unetched first insulating layer and the unetched second insulating layer in order to form a first set and a second set of insulating spacers on sidewalls of the first gate stack and expose the first substrate surface; forming raised epitaxial source and drain layers only on the first substrate surface, the epitaxial source and drain layers on the first substrate surface having an opposite polarity type with respect to the epitaxial source and drain layers on the second substrate surface; removing the hard mask layer in the second region, leaving the first set and the second set of insulating spacers on the sidewalls of the first and second gate stacks; forming a third insulator layer over the raised epitaxial source and drain layers in both the first and second region, on the first and second gate stacks and on the first set and second set of insulating spacers; etching to remove portions of the third insulator layer to form a third set of insulating spacers adjacent to the first set and the second set of insulating spacers on the sidewalls of the first gate stack and the sidewalls of the second gate stack; with the first set and the second set of insulating spacers still remaining on the sidewalls of the first and second gate stacks, forming silicide contacts on the source and drain layers in both the first and second regions and on the first and second gate stacks.