Patent ID: 9378533
Filing Date: 2016-06-28
CPC Classification: G06F,G06T

Claim Text:
1. A single processor including a plurality of cores, comprising: an upper core allocated with a main thread; and a plurality of lower cores, each of the plurality of the lower cores being allocated with at least one worker thread, wherein the single processor does not include a general purpose graphic processing unit (GPGPU), the upper core and the plurality of lower cores do not include a graphic processing unit (GPU), the single processor loads a GPU simulation code from a random access memory (RAM) or a nonvolatile memory device through a system bus, the upper core transmits address information of the GPU simulation code associated with allocated simulation operations to the lower cores, based on the GPU simulation code, each worker thread requests the GPU simulation code associated with the address information from the RAM, based on the received address information, the plurality of the lower cores perform simulation operations on operation units of a virtual graphic processing unit (GPU), in the respective at least one worker thread, to generate simulation data, and the upper core allocates the simulation operations on the operation units of the virtual GPU to the plurality of the worker threads and generates synchronization data based on the generated simulation data.