Patent ID: 9501261
Filing Date: 2016-11-22
CPC Classification: G06F,H03M

Claim Text:
1. A binary array system, comprising: a binary counter configured to output a plurality of bit values through a plurality of bit outputs, each of the plurality of bit values being output through a corresponding one of the plurality of bit outputs; a binary array having a plurality of binary array elements, each of the plurality of binary array elements coupled to a corresponding one of the plurality of bit outputs and configured to provide a unit value based on one of the plurality of bit values output through the corresponding one of the plurality of bit outputs; and a controller coupled to the binary counter and configured to set the plurality of bit values such that a transition of only a least significant bit of the plurality of bit values, of the binary counter, from a first state to a second state effectuates, via the binary array, an incremental change in a total unit value provided by the binary array, wherein a first binary array element coupled to the least significant bit of the binary counter and a second binary array element coupled to the next to least significant bit of the binary counter have the same unit value.