Patent ID: 9251916
Filing Date: 2016-02-02
CPC Classification: G01R,G06F,G11C

Claim Text:
1. A memory storage system comprising: a first on-chip controller connected to a first test circuit, the first on-chip controller comprising at least one channel control block, the first on-chip controller configured to operate in a first clock domain; a second on-chip controller connected to a second test circuit, the second on-chip controller comprising at least one channel control block, the second on-chip controller configured to operate in a second clock domain; and control circuitry connected to the first on-chip controller and the second on-chip controller, wherein: the at least one channel control block of the first on-chip controller is configured to receive a first shift clock signal; the at least one channel control block of the second on-chip controller is configured to receive a second shift clock signal; the first on-chip controller is configured to produce a first clock signal based on a signal received from the control circuitry and the first shift clock signal; the second on-chip controller is configured to produce a second clock signal based on a signal received from the control circuitry and the second shift clock signal; and the first clock signal and second clock signal are substantially similar.