Patent ID: 9311090
Filing Date: 2016-04-12
CPC Classification: G06F

Claim Text:
1. A circuit arrangement, comprising: a processing unit; a first register disposed in the processing unit; an execution unit disposed in the processing unit and configured to receive a predication enable signal that indicates whether to predicate an instruction and selectively predicate instructions based at least in part on the predication enable signal; predication logic disposed in the processing unit and configured to receive a first register address corresponding to the first register included in the instruction, determine a second register address based at least in part on a value stored at the first register address of the first register, and communicate the predication enable signal based at least in part on a value stored at the second register address; and instruction decoding logic configured to decode an instruction including a first register address, determine whether the instruction is of a type that supports predication, and communicate the first register address and a predication valid signal indicating whether the instruction is of a type that supports prediction to the predication logic, wherein the predication logic is configured to receive a first register address corresponding to the first register included in a decoded instruction, determine a second register address based on a value stored at the first register address of the first register, and communicate the predication enable signal based at least in part on a value stored at the second register address responsive to receiving the predication valid signal indicating that the instruction is of the type that supports predication.