Patent ID: 9349155
Filing Date: 2016-05-24
CPC Classification: G06T

Claim Text:
1. A computing apparatus comprising: a memory configured to comprise an address space defined as a multidimensional space comprising two axes; a memory allocator implemented by a processor and configured to allocate the address space, as one-dimensional (1D) arrays thereof, to two-dimensional (2D) array data by allocating row data of the 2D data along a first axis and allocating column data of the 2D data along a second axis, wherein the memory allocator allocates the address space using 2D vector addresses corresponding to sequential pieces of data arranged in accordance with the 1D arrays; and a memory accessor implemented by a processor and configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis, wherein the memory accessor is configured to access the memory in accordance with a size of each of the 1D arrays, in which the memory accessor pops data from or pushes data onto the memory in a direction of the row by increasing or decreasing a value of the second pointer by a degree of the size of each of the 1D arrays while a value of the first pointer remains unchanged, and pops data from or pushes data onto the memory in a direction of the column by increasing or decreasing the value of the first pointer by a degree of the size of each of the 1D arrays while the value of the second pointer remains unchanged.