Patent ID: 9454438
Filing Date: 2016-09-27
CPC Classification: G06F

Claim Text:
1. A recovery circuit for a basic input-output system (BIOS) of a computer, the recovery circuit comprising: a storage unit comprising a chip selection pin, an output pin, an input pin, and a clock pin; a platform controller hub (PCH), wherein the PCH is a chip configured to exchange information with peripherals in a manner that serial peripheral interface buses are connected to the storage unit; wherein the SPI buses comprise a chip select signal bus coupled to the chip selection pin of the storage unit, an input data bus coupled to the output pin of the storage unit, an output data bus coupled to the input pin of the storage unit, and a serial clock bus coupled to the clock pin of the storage unit; and a processor comprising a serial input pin, a serial output pin, a first pin, a second pin, a third pin, a first clock pin, and a second clock pin, and a power pin; wherein the power pin is coupled to a standby power supply, the first clock pin is coupled to the clock pin of the storage unit, the second clock pin is coupled to ground, the second pin is coupled to a cathode of a diode, an anode of the diode is coupled to the chip selection pin of the storage unit, the third pin is coupled to the chip selection pin of the storage unit, the serial input pin is coupled to the input pin of the storage unit, the serial output pin is coupled to the output pin of the storage unit, and the first pin is coupled to the serial output pin; wherein if an effective chip select signal is received by the chip selection pin of the storage unit via the second pin of the processor when the first pin of the processor does not receive any signals, data in the processor is transmitted to the PCH to make the computer boot up, and the data in the processor is transmitted to the storage unit to erase and update data in the storage unit.