Patent ID: 9240424
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a thin film transistor array substrate, comprising: forming an active layer thin film and a conductive layer thin film on a substrate; depositing a source/drain electrode layer thin film on the conductive layer thin film, treating the conductive layer thin film and the source/drain electrode layer thin film using a gray tone or half tone masking process, to form at least two data lines, a pixel electrode and source/drain electrodes of a thin film transistor, and the source electrode of the thin film transistor being connected with one of the data lines; after depositing an insulating layer thin film covering the active layer thin film, the source/drain electrodes, the data lines and the pixel electrode, forming a through hole in the insulating layer thin film, forming a gate insulating layer, and forming an active layer of the thin film transistor, and the through hole being provided at a selected position in the area corresponding to each of the data lines; and forming a gate electrode of the thin film transistor and at least two gate scanning lines crossing with the data lines on the insulating layer, and the gate electrode of the thin film transistor being connected with one of the gate scanning lines, wherein, forming the through hole in the insulating layer thin film, forming the gate insulating layer of the thin film transistor and forming the active layer of the thin film transistor comprises: coating photoresist on the deposited insulating layer thin film, after exposing and developing the photoresist, etching the insulating layer thin film and the active layer thin film, to obtain the through hole and the gate insulating layer and the active layer of the thin film transistor; wherein, the active layer of the thin film transistor is located within an area whose boundaries are defined by the gate scanning lines and the data lines and is distributed within the whole area.