Patent ID: 9368631
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A thin film transistor, comprising: a gate electrode on a substrate, wherein the gate electrode includes a gate area with respect to the substrate; a channel layer overlapping the gate electrode, wherein the channel layer includes a channel area with respect to the substrate; a gate dielectric layer disposed between the gate electrode and the channel layer; a source electrode and a drain electrode electrically connected to two parts of the channel layer; and a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the passivation layer has a planar surface; a via hole through the passivation layer to expose a part of the drain electrode; and a conductive pattern on the planar surface of the passivation layer to serve as a pixel electrode, wherein the conductive pattern contacts the drain electrode through the via hole, wherein the channel layer comprises an oxide semiconductor, and wherein the channel area falls within the gate area.