Patent ID: 9529045
Filing Date: 2016-12-27
CPC Classification: G01R,G06F,H04L

Claim Text:
1. An integrated circuit comprising: (a) a first test clock lead, a second test clock lead, a test mode select lead, a test data in lead, and a test data out lead; (b) a first test access port having a clock input connected to the second test clock lead and being free of the first test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the second test access port having class T0-T2 capabilities and including topology selection logic; and (c) a second test access port having a clock input connected to the second test clock lead and being free of the first test clock lead, having a mode input connected to the test mode select lead, being free of the test data in lead and the test data out lead, the second test access port having class T4 capabilities and including topology selection logic.