Patent ID: 9425288
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device for manufacturing a FinFET device, comprising: providing a semiconductor substrate, on which a plurality of semiconductor fins arranged in parallel are formed; depositing a gate insulation layer and a gate material, defining a gate pattern, forming a plurality of parallel gates which intersect the semiconductor fins, and defining the channel region of the FinFET; forming a spacer located on side surfaces of the gates and the semiconductor fins; depositing a polycrystalline silicon layer, and then planarizing the polycrystalline silicon layer to expose the top of the gates; monocrystalizing the polycrystalline silicon layer to form a single crystal silicon layer; forming an isolation structure which cuts off the semiconductor fins; forming a metal silicide by reacting of the single crystal silicon layer located on top of the semiconductor fins with a metal, wherein the formed metal silicide is a source/drain region contact; and cutting the gates arranged in parallel in accordance with the predetermined region to form a gate isolation trench, thereby obtaining the desired FinFET.