Patent ID: 9390809
Filing Date: 2016-07-12
CPC Classification: G11C

Claim Text:
1. A method, comprising: defining a first voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a second voltage configuration, different from the first voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block, wherein the second voltage configuration comprises a higher programming-verification threshold than the programming-verification threshold used in the first voltage configuration; if no WL-WL short-circuit is found in the memory block, performing a data storage operation, which comprises programming a selected WL in the memory block, by applying the first voltage configuration; and if a WL-WL short-circuit is found in the memory block, performing the data storage operation in the memory block by applying the second voltage configuration.