Patent ID: 9299781
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A device, comprising: an active region defined in a semiconductor substrate; a layer of material positioned above said substrate; a plurality of laterally spaced-apart source/drain trenches formed in said layer of material above said active region; a conductive source/drain contact structure formed within each of said source/drain trenches; a gate trench formed partially in said layer of material between said spaced-apart source/drain trenches formed in said layer of material and partially within another layer of material surrounding an outer perimeter of said layer of material, wherein portions of said layer of material remain positioned between said source/drain trenches and said gate trench; a gate structure positioned within said gate trench; and a gate cap layer positioned above said gate structure, wherein an entirety of sidewalls of said gate cap layer directly contacts sidewalls of said gate trench.