Patent ID: 9467177
Filing Date: 2016-10-11
CPC Classification: H03M,H04L

Claim Text:
1. An error correction system, comprising: a memory storing executable components; and a processor, communicatively coupled to the memory, that facilitates execution of executable components, the executable components comprising: a concatenation component configured for stacking a plurality of forward error correction bits on top of each other in a matrix arrangement with a plurality of binary code, wherein a symbol size of the forward error correction bits is smaller than a sample size of the binary code; an encoding component configured for generating an encoded bit for each product of a forward error correction bit of the plurality of forward error correction bits and a code of the plurality of binary code; a forward error correction decoder that is configured for generating decoded bits by decoding the encoded bits using a hexacode, wherein a portion of the encoded bits are not successfully decoded; and a multilevel decoding leech lattice that is configured for receiving the decoded bits and the encoded bits from the forward error correction decoder, wherein the multilevel decoding leech lattice and the forward error correction decoder iteratively decode the encoded bits until all the encoded bits are decoded.