Patent ID: 9361825
Filing Date: 2016-06-07
CPC Classification: G09G

Claim Text:
1. A method of detecting a data bit depth comprising: receiving, at an interface receiving terminal configured to receive display data in two or more data bit depth modes without a separate option pin indicating the data bit depth, a clock data recovery (CDR) training pattern signal from an interface transmitting terminal; outputting clocks from a CDR circuit of the interface receiving terminal using the CDR training pattern signal; receiving, at the interface receiving terminal, an alignment training pattern signal subsequent to the CDR training pattern signal from the interface transmitting terminal, the alignment training pattern signal including a number of bits of pixel data and alignment data, the alignment data indicative of a start time for the interface receiving terminal to receive display data that is received subsequent to the alignment training pattern signal; separating a data enable signal from the alignment training pattern signal in the interface receiving terminal, the data enable signal indicating input timing of one line of pixel data for display on a display device; determining, at the interface receiving terminal without the separate option pin indicating the data bit depth, the data bit depth of the subsequently received display data by counting the number of bits of the pixel data accumulated in one of a high period and a low period of the data enable signal included in the alignment training pattern signal; and receiving, at the interface receiving terminal, the display data based on the alignment data, the display data received subsequent the alignment training pattern signal and displayed on the display device.