Patent ID: 9324866
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A semiconductor structure, comprising: an isolation feature formed in a semiconductor substrate; a first fin and a third fin, adjacent to the first fin, extending in a first direction on the semiconductor substrate and a second fin and a fourth fin, adjacent to the second fin, extending in the first direction on the semiconductor substrate and being collinear with the first fin and third fin respectively, wherein the isolation feature interposes the first fin and the second fin, and the isolation feature interposes the first fin and the third fin, such that a first contiguous region of insulating material is disposed between the first fin and the third fin, and a second contiguous region of insulating material is disposed between the first fin and the second fin; a first active region in the first fin and a second active region in the second fin, wherein the first and second active regions extend in a first direction and are separated from each other by the second contiguous region of insulating material of the isolation feature; a dummy gate disposed on the second contiguous region of insulating material of the isolation feature and extending over end regions of at least the first fin and the third fin; a first functional gate disposed on the first active region and configured to form a first field effect transistor; a second functional gate disposed on the second active region and configured to form a second field effect transistor; a first epitaxy source/drain feature formed in a trench in the first active region of the first fin and interposing the first functional gate and the dummy gate in the first direction, wherein a bottom edge of the first epitaxy feature is below a top surface of the isolation feature and wherein a sidewall of the trench nearest the dummy gate is defined by a semiconductor material of the first fin, wherein the first epitaxy source/drain feature is separated from the second contiguous region of insulating material of the isolation feature by a portion of the semiconductor material of the first fin the portion having a length in the first direction that is defined by a distance the dummy gate extends over the end region of the first fin.