Patent ID: 9264070
Filing Date: 2016-02-16
CPC Classification: G06F,H03M

Claim Text:
1. A memory controller for controlling a nonvolatile memory, comprising: a memory interface that has multiple channels and carries out writing into the nonvolatile memory through each of the channels; a data buffer; an ECC (error correcting code) encoder for applying an error correction encoding processing on write data to be written into the nonvolatile memory, thereby generating ECC data; a channel allocation part for allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory; a write data reception processing part that stores the write data in the data buffer and outputs the write data to the ECC encoder; a channel scheduler for transferring the write data and the ECC data to the channels of the memory interface as allocated by the channel allocation part, wherein subsequent write data are transferred to each of the channels which has finished carrying out writing of the write data allocated to the channel into the nonvolatile memory without waiting for writing of the corresponding ECC data to finish, such that a period during which the write data is transferred overlaps a period during which error correction encoding processing is applied on the write data; and a write command issuing part that (1) specifies a unit size of write data transferred to the memory interface, (2) receives a channel allocation result from the channel allocation part, and (3) issues a write command to instruct the channel scheduler to write the write data, upon determining that processing of write data equal in size to the unit size of the write data has completed, wherein the unit size of the write data is smaller than a unit size of error correction data, the error correction data including both the ECC data and the write data corresponding to the ECC data.