Patent ID: 9379124
Filing Date: 2016-06-28
CPC Classification: G11C,H01L

Claim Text:
1. A method of making a monolithic three dimensional NAND string comprising a semiconductor channel and a plurality of control gate electrodes, the method comprising: forming a stack of alternating first material layers and second material layers over a substrate, wherein the first material comprises an electrically insulating material and the second material is different from the first material; etching the stack to form a front side opening in the stack; selectively forming a plurality of discrete charge storage regions using atomic layer deposition, wherein the plurality of discrete charge storage regions comprises at least one of a metal or an electrically conductive metal oxide, and wherein the step of selectively forming the plurality of discrete charge storage regions using atomic layer deposition comprises selectively forming the plurality of discrete charge storage regions using atomic layer deposition on exposed portions of the second material layers in the front side opening but not on exposed portions of the first material layers in the front side opening; forming a tunnel dielectric over the discrete charge storage regions in the front side opening; forming the semiconductor channel layer over the tunnel dielectric in the front side opening; etching the stack to form a back side opening in the stack; removing at least a portion of the second material layers through the back side opening to form back side recesses between the first material layers; forming a blocking dielectric in the back side recesses through the back side opening; and forming the plurality of control gate electrodes over the blocking dielectric in the back side recesses through the back side openings; wherein: