Patent ID: 9423906
Filing Date: 2016-08-23
CPC Classification: G06F

Claim Text:
1. A drive system adaptable to a matrix scanning device, comprising: a plurality of first drive circuits disposed on a first periphery along a first direction of a substrate with each said first drive circuit being electrically coupled to at least one column wire of the matrix scanning device; a plurality of second drive circuits disposed on a second periphery along a second direction of the substrate with each said second drive circuit being electrically coupled to at least one row wire of the matrix scanning device; a master controller configured to control the first drive circuits and the second drive circuits; and a bus electrically coupled to the master controller, the first drive circuits and the second drive circuits, wherein at least one bus wire of the bus is configured as either an analog channel in an analog mode or a digital channel in a digital mode and the master controller outputs an analog/digital switching signal used to switch between the analog mode and the digital mode; wherein each of the plurality of first drive circuits comprises: a register controller electrically coupled to the bus; a matrix multiplexer electrically coupled to at least one said column wire and controllably communicated to one bus wire of the bus under control of the respective first drive circuits register controller and the analog/digital switching signal; and an analog or digital multiplexer configured to regulate signal transferred on the bus under control of the respective first drive circuits register controller and the analog/digital switching signal; and wherein each of the plurality of second drive circuits comprises: a matrix multiplexer electrically coupled to at least one said row wire and controllably communicated to one bus wire of the bus under control of the respective second drive circuits register controller and the analog/digital switching signal; and an analog or digital multiplexer configured to regulate signal transferred on the bus under control of the respective second drive circuits register controller and the analog/digital switching signal, wherein the plurality of first drive circuits and the plurality of second drive circuits each comprises a logic circuit configured to generate a control signal under control of the respective first drive circuits register controller and the analog/digital switching signal, and respective second drive circuits register controller and the analog/digital switching signal, correspondingly, wherein each analog or digital multiplexer comprises a switch which is closed by the control signal after the associated first or second drive circuit has been set, such that a predefined signal passes through the analog or digital multiplexer, and wherein the master controller comprises a feedback signal node configured to receive the predefined signal from a first drive circuit through which the predefined signal passes last in the plurality of first drive circuits or a second drive circuit through which the predefined signal passes last in the plurality of second drive circuits.