Patent ID: 9306039
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method of forming a memory device, comprising: providing a substrate of semiconductor material of a first conductivity type; forming first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, wherein the channel region has first and second portions; forming a stressor region of embedded silicon carbide in the substrate directly under the second portion of the channel region, wherein no stressor region of embedded silicon carbide is formed directly under the first portion of the channel region; forming a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and the first portion of the channel region; and forming a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from the second portion of the channel region and over the stressor region.