Patent ID: 9293593
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A structure comprising: a substrate comprising a silicon film, having a thickness of 10 nm-40 nm, bonded or formed directly on an insulator layer; a stress layer having a bottom surface directly on a top surface of the silicon film; isolation regions surrounding the stress layer and having bottom surfaces directly on a top surface of the insulator layer; a stressed Si layer in a trench formed in the stress layer, wherein the stressed Si layer is an active channel region of a device and the stressed Si layer has a lattice constant different than the stress layer; and a gate structure formed in the active channel region formed from the stressed Si layer, the gate structure comprising a dielectric material formed on the stressed Si layer and a gate body, wherein a top surface of the stressed Si layer is coplanar with a top surface of the stress layer; wherein an entirety of the stress layer is a compressive stress material consisting essentially of SiGe deposited directly on the top surface of the silicon film; wherein the isolation regions have top surfaces coplanar with the top surface of the stress layer; and wherein an entirety of the stressed Si layer exhibits a compressive strain, a portion of which results from being in the trench formed in the stress layer, wherein the stressed Si layer extends completely through the stress layer and is in direct contact with a bottom surface of the dielectric material and in direct contact with the top surface of the silicon film.