Patent ID: 9496879
Filing Date: 2016-11-15
CPC Classification: H03L,H04L

Claim Text:
1. A method of data communications, comprising: configuring a clock recovery circuit to provide a first clock signal that includes pulses corresponding to symbols transmitted on a 3-wire, 3-phase interface, wherein symbols are transmitted on the 3-wire, 3-phase interface at a first frequency; adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more than half the first frequency, wherein the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols; configuring a clock generation circuit to provide a second clock signal, wherein the second clock signal includes pulses for each of the other symbols in the integer number of symbols; and capturing symbols from the 3-wire, 3-phase interface using the first clock signal and the second clock signal, wherein the loop delay corresponds to a pulse generation cycle used to generate a pulse in response to a first-detected transition in signaling state of the 3-wire, 3-phase interface, and wherein detection of other transitions in signaling state of the 3-wire, 3-phase interface is suppressed during the pulse generation cycle.