Patent ID: 9305785
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a semiconductor substrate; a plurality of semiconductor fins disposed on the semiconductor substrate; a shallow trench isolation between fins of the plurality of fins; a first gate disposed on the semiconductor substrate adjacent to at least one fin of the plurality of fins; a second gate disposed over a non-active area of the substrate; a first insulator layer disposed between the first gate and the second gate, and in direct physical contact with the non-active area of the substrate; a metal layer disposed on, and in contact with, the at least one fin of the plurality of fins; a second insulator layer disposed over the first insulator layer and metal contact layer; a first contact via disposed in the second insulator layer and making contact with the contact metal layer; and a second contact via disposed in the second insulator layer and the first insulator layer, and making contact with the second gate.