Patent ID: 9373400
Filing Date: 2016-06-21
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device comprising: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, the plurality of gate electrodes being separated from one another and being disposed along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from an impurity-doped second region of the substrate, an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes, wherein the semiconductor region, plurality of gate electrode, and gate dielectric layer define a memory cell string extending vertically from the first region of the substrate; and the insulating region is between the memory cell string and the substrate contact electrode.