Patent ID: 9515163
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A method of forming a FinFET transistor above an active region defined in a semiconductor substrate, comprising: forming a plurality of fins in said semiconductor substrate; forming a sacrificial gate structure above said plurality of fins, said sacrificial gate structure extending in a gate width direction oriented perpendicular with respect to an axial length direction of said plurality of fins; forming a sidewall spacer adjacent said sacrificial gate structure; performing an epitaxial deposition fin-merger process to form a plurality of merged-fin regions from portions of said plurality of fins that define a plurality of source/drain regions for said transistor; removing said sacrificial gate structure to define a gate recess; forming a conductive replacement gate structure in said gate recess; forming a dielectric cap layer above said conductive replacement gate structure in said gate recess; after forming said replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of said plurality of source/drain regions; forming a first sacrificial layer of material above said source/drain regions; performing at least one etching process to define a patterned first sacrificial layer of material that comprises features that correspond to said at least one source/drain contact structure and to remove at least portions of said dielectric gate cap layer and at least a portion of said sidewall spacer so as to thereby expose a portion of said conductive replacement gate structure; forming a layer of insulating material around said patterned first sacrificial layer of material and in contact with said exposed portion of said replacement gate structure; with said replacement gate structure in position, removing remaining portions of said first sacrificial layer of material so as to defined a plurality of source/drain contact opening in said layer of insulating material exposing portions of said metal silicide layer; and forming at least one source/drain contact structure for each of said plurality of source/drain regions in said plurality of source/drain contact openings, wherein said at least one source/drain contact structure is formed such that it is conductively coupled to a portion of said metal silicide layer and a dimension of said at least one source/drain contact structure in said gate width direction is less than a dimension of said source/drain region in said gate width direction.