Patent ID: 9230802
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A method of fabricating field effect transistors (FETs), the method comprising: recessing a semiconductor material to form a cavity therein adjacent to a channel region of a transistor, the recessing defining a first channel interface surface and a second channel interface surface within the cavity; providing a protective liner over the second channel interface surface within the cavity, with the first channel interface surface being exposed within the cavity; processing the first channel interface surface to facilitate forming a first channel junction of the transistor at the first channel interface surface within the cavity; and removing the protective liner from over the second channel interface surface, and processing the second channel interface surface to form a second channel junction of the transistor at the second channel interface surface within the cavity, wherein the first channel junction of the transistor and the second channel junction of the transistor comprise one or more different channel junction characteristics.