Patent ID: 9406529
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method for forming a finFET comprising: forming a finFET structure, wherein the finFET structure comprises a silicon germanium fin having a source/drain region and a channel region, an epitaxial layer located on the source/drain region of the silicon germanium fin, a dummy gate located above the channel region of the silicon germanium fin, and a spacer located between the dummy gate and the epitaxial layer and above the source/drain region of the fin; removing the dummy gate; performing thermal condensation on an exterior portion of the silicon germanium fin in the channel region, wherein thermal condensation forms a silicon oxide layer on the exterior portion of the silicon germanium fin in the channel region and an enriched germanium fin on an interior portion of the silicon germanium fin in the channel region, and wherein a concentration of germanium in the enriched germanium fin is higher than the concentration of germanium in the silicon germanium fin in the source drain region; and removing the silicon oxide layer from the exterior portion of the silicon germanium fin.