Patent ID: 9471329
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. An apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: determining, by a socket configuration module, a number of central processing units (“CPUs”) of a computing system to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with computing devices that are off-chip from the number of CPUs and that are coupled to one or more of the number of CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with the computing devices that are off-chip from the number of CPUs and a predetermined performance policy, a target CPU of the number of CPUs to utilize as a boot CPU.