Patent ID: 9344200
Filing Date: 2016-05-17
CPC Classification: G02B,H01L,H01S,H04B

Claim Text:
1. An electrical device comprising: a first semiconductor device positioned on a first portion of a semiconductor on insulator (SOI) substrate; a second semiconductor device positioned on a third portion of the SOI substrate; and an optical interconnect positioned on a second portion of the semiconductor substrate that is positioned between the first and third portions of the semiconductor substrate, the optical interconnect is present on at least one interlevel dielectric layer that is present over at least one of the first and second semiconductor devices, the optical interconnect including a III-V light emission device, a dielectric waveguide and III-V light detection device, wherein at least one material layer of at least one of the III-V light emission device and the III-V light detection device is an epitaxial material that is in direct contact with abuse semiconductor substrate of the SOI substrate through a via extending through the least one interlevel dielectric layer and a buried dielectric layer of the SOI substrate.