Patent ID: 9530520
Filing Date: 2016-12-27
CPC Classification: G09G,G11C

Claim Text:
1. An shift register unit, comprising an input module, a charging module, a reset module, a first switch module and a second switch module, wherein a output terminal of the input module is connected to an Ith gate line through the first switch module and connected to a (i+3)th gate line through the second switch module, a control terminal of the first switch module is connected to a first clock signal line and a control terminal of the second switch module is connected to a second clock signal line, and a phase difference between clock signals output from the first clock signal line and the second clock signal line is half of a cycle; a (i−1)th gate line and a (i+2)th gate line are connected to an input terminal of the input module through the charging module; a (i+1)th gate line and a (i+4)th gate line are connected to the input terminal and the output terminal of the input module through the reset module; and i is a natural number and i>2; wherein the first switch module is a first switch transistor and the control terminal of the first switch module is gate of the first switch transistor; the second switch module is a second switch transistor and the control terminal of the second switch module is gate of the second switch transistor; wherein the input module comprises a capacitor and an output switch transistor, two terminals of the capacitor are connected to gate and drain of the output switch transistor, respectively, and source of the output switch transistor is connected to a high level signal line; the gate of the output switch transistor is the input terminal of the input module and the drain of the output switch transistor is the output terminal of the input module.