Patent ID: 9488855
Filing Date: 2016-11-08
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: a gate line, a transparent pixel electrode, a first data line and a first transparent common electrode, wherein the first transparent common electrode is disposed over the transparent pixel electrode and used to generate an electric field between the first transparent common electrode and the transparent pixel electrode; the array substrate further comprises: a second data line, a second transparent common electrode and an insulating layer disposed between the second data line and the second transparent common electrode and having a via hole, wherein the second data line and the insulating layer are disposed in a non-aperture region of the array substrate; wherein the transparent pixel electrode has an extension, the second data line is physically connected to the extension and physically and electrically connected to the second transparent common electrode through the via hole in the insulating layer, and the second data line overlays a portion of the extension, wherein the extension of the transparent pixel electrode is a protrusion toward the gate line, and the extension and the gate line are disposed with an interval therebetween, and wherein the first data line and the second data line are disposed in a same layer, the second data line is overlapped with the gate line, the extension of the transparent pixel electrode, and the interval between the gate line and the extension of the transparent pixel electrode.