Patent ID: 9460813
Filing Date: 2016-10-04
CPC Classification: G06F,G11C

Claim Text:
1. A memory system comprising: a first transmitting port connectable to a first host apparatus; and a controller that is configured to transmit a transmission signal to the first host apparatus through the first transmitting port, that includes a first output interface and a second output interface, that outputs a first signal from the first output interface to the first transmitting port, and that outputs a second signal from the second output interface to the first transmitting port, the first signal being selected from a plurality of first signals, the plurality of first signals including high impedance, the second signal being selected from a plurality of second signals, the plurality of second signals not including high impedance; and a signal line including a first signal line, a second signal line and a third signal line, the first signal line being connected to the first transmitting port, the second signal line being diverged from the first signal line, the second signal line being connected to the first output interface through a first resistor, the third signal line being diverged from the first signal line, the third signal line being connected to the second output interface through a second resistor, the second resistor having a greater resistance value than the first resistor.