Patent ID: 9251902
Filing Date: 2016-02-02
CPC Classification: G11C

Claim Text:
1. A semiconductor storage device comprising: a plurality of memory cells; a plurality of word lines connected to the memory cells; a plurality of bit lines connected to the memory cells; and a sense amplifier unit connected to the bit lines, wherein a data write operation comprises a first write loop and a second write loop, the first write loop including a first program operation and a first verify operation, the second write loop including a second program operation and a second verify operation, and a maximum value of a consumed current in the first verify operation is substantially equal to a maximum value of the consumed current in the second verify operation, and the consumed current in the first verify operation is substantially same as the consumed current in the second verify operation if data input in the data write operation is all equal to first data corresponding to an erasure state, wherein the maximum value of the consumed current appears between a first point in which a voltage of the bit lines starts rising and a second point in which a strobe signal starts rising.