Patent ID: 9530721
Filing Date: 2016-12-27
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first semiconductor chip having a main surface and a back surface opposite the main surface; a second semiconductor chip having a main surface and a back surface opposite the main surface; a plurality of leads; a plurality of wires; and a sealing body sealing the first and second semiconductor chips, part of each of the plurality of leads, and the plurality of wires, wherein a first pad, a second pad, and a first wiring electrically connected to the first and second pads are formed on the main surface of the first semiconductor chip, a third pad is formed on the main surface of the second semiconductor chip, the third pad of the second semiconductor chip is electrically connected to the first pad of the first semiconductor chip via a first wire among the plurality of wires, the second pad of the first semiconductor chip is electrically connected to a first lead among the plurality of leads via a second wire among the plurality of wires, in a plan view, a distance between an end portion of the first lead and a side of the first semiconductor chip facing the end portion of the first lead is smaller than a distance between the end portion of the first lead and a side of the second semiconductor chip facing the end portion of the first lead, and the first pad, the second pad, and the first wiring are not connected to any circuit formed in the first semiconductor chip, wherein the first wiring is formed along an outer periphery of the first semiconductor chip, wherein the first wiring includes a third wiring and a fourth wiring formed on a layer below the third wiring, wherein the third wiring has a substantially uniform thickness and width throughout, and the fourth wiring has a substantially uniform thickness and width throughout, wherein, in a direction perpendicular to the main surface of the first semiconductor chip, the third wiring is larger in thickness than the fourth wiring, and in a direction parallel to the main surface of the first semiconductor chip, the fourth wiring is larger in width than the third wiring, and wherein the third wiring is formed on the same layer where the first pad or second pad is formed.