Patent ID: 9324717
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, comprising the steps: providing a substrate comprising silicon, said substrate having a first region of a first conductivity type in an area for a first polarity finFET and having a second region of a second, opposite, conductivity type in an area for a second, opposite, polarity finFET; forming a dielectric layer 50 nanometers to 100 nanometers thick over said substrate; forming a first trench in said dielectric layer down to said substrate in said area for said first polarity finFET; forming a first silicon-germanium buffer 1 nanometer to 5 nanometers thick on said substrate in said first trench; forming a first polarity fin of said first polarity finFET on said first silicon-germanium buffer, so that said first polarity fin extends above a top surface of said dielectric layer; forming an epitaxial blocking layer over said dielectric layer so as to cover said first polarity fin; forming a second trench in said epitaxial blocking layer and said dielectric layer down to said substrate in said area for said second polarity finFET; forming a second silicon-germanium buffer 1 nanometer to 5 nanometers thick on said substrate in said second trench; forming a second polarity fin of said second polarity finFET on said second silicon-germanium buffer, so that said second polarity fin extends above a top surface of said dielectric layer; forming a cap layer of dielectric material over said epitaxial blocking layer so as to cover said second polarity fin; removing said cap layer and said epitaxial blocking layer by a chemical mechanical polish (CMP) process so as to planarize said first polarity fin and said second polarity fin down to said dielectric layer; and recessing said dielectric layer so that said first polarity fin and said second polarity fin extend at least 10 nanometers above said dielectric layer.