Patent ID: 9390220
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. A method comprising: within a processor: determining a respective initial delay for each clock to out path in a bus including a plurality of clock to out paths for a programmable logic device; forming pairs of each clock to out path in the plurality of clock to out paths; for each pair of clock to out paths, determining a delay difference between the initial delay across a first clock to out path in that pair and the initial delay across a remaining second clock to out path in the pair; determining, for each clock to out path of the pair, a maximum delay difference between the initial delay and a corresponding clock out delay as well as a minimum delay difference between the initial delay and the corresponding clock out delay; for each clock to out path, determining a first difference between the minimum delay difference for the first clock to out path in the pair and the maximum delay difference for the second clock to out path in the pair and determining a second difference between the maximum delay difference for the first clock to out path in the pair and the minimum delay difference for the second clock to out path in the pair; determining an individual delay offset range to be added to the initial delay for each of the clock to out paths using the maximum and minimum delay differences, the first differences, and the second differences; and placing and routing the clock to out paths for the programmable logic device.