Patent ID: 9513917
Filing Date: 2016-12-06
CPC Classification: G06F

Claim Text:
1. An apparatus comprising: an instruction converter to convert each occurrence of an instruction of a first instruction set that has a first instruction format into one or more corresponding instructions of a second different instruction set, wherein the first instruction format includes a first plurality of templates that each include a plurality of fields including a base operation field, a data element width (W) field, a vector length field, a write mask control field, and a write mask field, wherein the first instruction format supports through different values in the base operation field specification of a plurality of different vector operations, wherein each of the plurality of vector operations requires an operation to be independently performed on each of a plurality of different data element positions of at least one source vector operand to generate at least one destination vector operand, wherein the first instruction format supports through different values in the data element width field specification of a 32 bit and a 64 bit data element width, wherein the first plurality of templates support through different values in the vector length field specification of a plurality of different vector lengths, wherein the first instruction format supports through different values in the write mask field specification of different write masks, wherein the first instruction format supports through different values in the write mask control field selection between merging write mask and zeroing write mask, wherein only one of the different values is placed in each of the base operation field, the data element width field, the write mask control field, and the write mask field on each said occurrence of the instruction in the first instruction format in instruction streams, the instruction converter to convert the occurrences of the instructions that have the first instruction format that includes the first plurality of templates as follows: a processor coupled with the instruction converter, the processor to decode and execute the one or more instructions converted from each occurrence of the instruction of the first instruction set that has the first instruction format.