Patent ID: 9391018
Filing Date: 2016-07-12
CPC Classification: H01L,H01P,H05K

Claim Text:
1. A method of fabricating transmission line circuitry for coupling a first and second input/output (I/O) channel of an integrated circuit (IC) disposed on a chip to an off-chip connection point, the method comprising: forming a first conductive trace defining a routing path for the first I/O channel in a first metallization level disposed over a substrate; forming a second conductive trace defining a routing path for the second I/O channel in the first metallization level wherein the first I/O channel is separate and electrically isolated from the second I/O channel; forming a first dielectric material disposed between the first and second conductive traces; forming a ground plane in a second metallization level disposed over the substrate and above or below the first metallization level; and forming a second dielectric material disposed between the ground plane and the first and second conductive traces, wherein the second dielectric material has a different dielectric constant than that of the first dielectric material.