Patent ID: 9397017
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor package, comprising: providing an electrically insulative layer having a first surface opposing a second surface; plating a first copper layer onto the second surface of the electrically insulative layer; patterning the first copper layer; forming traces in the first copper layer by etching through exposed portions of the first copper layer; plating a second copper layer onto the traces in the first copper layer; patterning the second copper layer; forming traces in the second copper layer that correspond with the traces in the first copper layer by etching through exposed portions of the second copper layer; bonding at least one semiconductor device with at least one of the traces in the second copper layer; encapsulating the at least one semiconductor device with a mold compound; and bonding at least one package electrical connector with one of the first copper layer and the second copper layer; wherein a width of the traces of the second copper layer are thinner than a width of the traces of the first copper layer by an offset distance.