Patent ID: 9305509
Filing Date: 2016-04-05
CPC Classification: G09G,G11C

Claim Text:
1. A shift register unit comprising: an inputting module connected with a first signal input terminal, a second signal input terminal, a first voltage terminal, a second voltage terminal and a first outputting module, and configured to control a scan direction of the shift register unit according to a signal inputted from the first signal input terminal, a signal inputted from the second signal input terminal, a voltage inputted from the first voltage terminal and a voltage inputted from the second voltage terminal; the first outputting module connected with a first clock signal terminal, a first node and a first signal output terminal, and configured to control a potential of a signal outputted from the first signal output terminal according to a signal outputted from the inputting module and a first clock signal inputted from the first clock signal terminal, the first node being a connection node of the first outputting module and a second outputting module; and the second outputting module connected with the first node, a second clock signal terminal and a second signal output terminal, and configured to control a potential of a signal outputted from the second signal output terminal according to a signal at the first node and a second clock signal inputted from the second clock signal terminal.