Patent ID: 9325315
Filing Date: 2016-04-26
CPC Classification: H03K

Claim Text:
1. A NAND gate circuit, comprising at least two input transistors, a gate electrode of each input transistor being connected to an input signal, a first electrode of a first input transistor being connected to a NAND gate output end, a second electrode of a last input transistor being connected to a first level, and apart from the last input transistor, a second electrode of each input transistor being connected to a first electrode of a next input transistor, wherein the NAND gate circuit further comprises at least two pull-up modules and at least two input control transistors, a gate electrode of each input control transistor is connected to the input signal, a first electrode thereof is connected to a control end of the corresponding pull-up module, and a second electrode thereof is connected to the first level, the first electrode of the first input transistor is connected to a second level output end via the pull-up module, the input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor corresponding to the input control transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level, and the at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection between the second level output end and the NAND gate output end when none of the input signals is at the second level, wherein the pull-up module comprises a first pull-up transistor, a second pull-up transistor and a storage capacitor, a gate electrode of the second pull-up transistor is the control end of the pull-up module, a gate electrode of the first pull-up transistor is connected to the second level output end a first electrode of the first pull-up transistor is connected to the gate electrode of the first pull-up transistor, and a second electrode of the first pull-up transistor is connected to the gate electrode of the second pull-up transistor, a first electrode of the second transistor is connected to the second level output end, and a second electrode thereof is connected to the NAND gate output end, and the storage capacitor is connected between the gate electrode and the second electrode of the second pull-up transistor.