Patent ID: 9385860
Filing Date: 2016-07-05
CPC Classification: H03L,H04B,H04L

Claim Text:
1. A fractional PLL circuit comprising: a phase comparator that detects a phase difference between an input clock signal as a reference and a feedback signal, and outputs a control voltage according to the phase difference; a voltage-controlled oscillation unit that generates and outputs an output-clock signal having a frequency according to the control voltage; a phase-selection unit that equally divides a period of the output-clock signal into a predetermined number of phases, selects one of the phases, and generates a phase-shift clock signal having a rising edge in the selected phase; a frequency-divider unit that divides a frequency of the phase-shift clock signal, and outputs the frequency-divided phase-shift clock signal to the phase comparator as the feedback signal; and a phase-control unit that determines the phase to be selected by the phase-selection unit for changing a duration of a period of the phase-shift clock signal from a duration of the period of the output-clock signal by a predetermined phase-shift amount, the phase-control unit that controls the phase-selection unit to select the determined phase, wherein the phase-control unit receives the frequency-divided phase-shift clock signal and operates according to the frequency-divided phase-shift clock signal.