Patent ID: 9403672
Filing Date: 2016-08-02
CPC Classification: B81B,B81C,H01L

Claim Text:
1. A method of manufacturing a chip package, comprising: forming at least a bump on a lower surface of an interposer; forming a first insulation layer to cover the lower surface and the bump; forming at least a trench extending from the lower surface towards an upper surface of the interposer; forming a polymer supporting adhesive layer surrounding the bump; coupling the interposer and a semiconductor chip by the polymer supporting adhesive layer, the semiconductor chip having at least a sensing component and a conductive pad electrically connected to the sensing component, wherein the bump is connected to the conductive pad; forming a via extending from the upper surface towards the lower surface, the via going through the bump to expose the conductive pad, wherein a width of the via is smaller than a width of the bump; forming a second insulation layer covering the upper surface and a wall of the via; forming a redistribution layer on the second insulation layer and in the via to electrically connect to the conductive pad; etching the interposer to expose the upper surface; and forming a packaging layer covering the redistribution layer, the packaging layer having a second opening to expose the trench.