Patent ID: 9506977
Filing Date: 2016-11-29
CPC Classification: G01R,G05B,H01L

Claim Text:
1. A method for applying stress conditions to a chip device comprising an integrated circuit during accelerated stress testing, the method comprising: partitioning the integrated circuit into a first region having a first functional element; partitioning the integrated circuit into a second region having a second functional element; applying a first stress condition to the first functional element until the first functional element is no longer operational; applying a second stress condition to the second functional element until the second functional element is no longer operational; measuring a first time period between starting the application of the first stress condition and when the first functional element is no longer operational; measuring a second time period between starting the application of the second stress condition and when the second functional element is no longer operational; and deriving an acceleration model parameter based on the first stress condition and the corresponding first time period and the second stress condition and the corresponding second time period.