Patent ID: 9293218
Filing Date: 2016-03-22
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a first One Time Programmable (OTP) cell array and a second OTP cell array each including a plurality of bit lines connected to a plurality of OTP cells, each bit line extending in a first direction; a converging circuit connected to at least a first bit line of the first OTP cell array and at least a first bit line of the second OTP cell array, and the converging circuit configured to select at least one bit line between the first bit lines of the first and second OTP cell arrays; and a sense amplifier circuit configured to amplify at least one signal of the selected bit line, wherein the first OTP cell array includes a first word line connected to a plurality of OTP cells, the first word line extending in a second direction perpendicular to the first direction, wherein the second OTP cell array includes a second word line connected to a plurality of OTP cells, the second word line extending in the second direction, and wherein the first word line and the second word line are configured to be activated in response to the same row address.