Patent ID: 9385151
Filing Date: 2016-07-05
CPC Classification: H01L,Y02E

Claim Text:
1. A semiconductor wafer including a plurality of device forming regions and having first and second principal surfaces opposed to each other, said semiconductor wafer comprising: an impurity-doped layer of a first conductivity type formed in each of the device forming regions; an impurity-doped layer of a second conductivity type formed in each of the device forming regions; and an electrode formed corresponding to each said impurity-doped layer, on the first principal surface side of the semiconductor wafer, wherein a trench extending in a direction of thickness of the semiconductor wafer from the first principal surface is formed by etching, at a position of a boundary between adjacent device forming regions out of the plurality of device forming regions, so as to expose side faces of the device forming regions, and wherein an insulating film is formed on the exposed side faces of the device forming regions.