Patent ID: 9319050
Filing Date: 2016-04-19
CPC Classification: H03L

Claim Text:
1. An apparatus for generating phase aligned clock signals comprising: a first signal generator configured to generate a reference clock signal responsive to a system clock signal; a second signal generator configured to generate a first clock signal responsive to the system clock signal and a control signal; and a phase alignment circuit configured to sample the first clock signal on the reference clock signal and sample the reference clock signal on the first clock signal to determine a relative phase between the first clock signal and the reference clock signal, to generate a phase signal indicative of whether a phase of the first clock signal lags, leads or is aligned with a phase of the reference clock signal responsive to said determination, and to generate the control signal responsive to the phase signal, the control signal setting a phase shift direction for the first clock signal, said second signal generator is further configured to shift the phase of the generated first clock signal responsive to the control signal to align the phases of the first clock signal and the reference clock signal, wherein the first and second signal generators comprise phase-locked loops.