Patent ID: 9514058
Filing Date: 2016-12-06
CPC Classification: G06F,Y02D

Claim Text:
1. A method of address translation comprising the steps of: storing only a single address translation entry in a current page translation register, said signal address translation entry consisting of a first predetermined number of address bits in a first address domain and a corresponding second predetermined number of address bits in a second address domain; receiving a first address of a memory access in a said first address domain; determining if said first address corresponds to the single address translation entry stored in the current page translation register by detecting if a first predetermined most significant bits of said first address matches said first predetermined number of address bits in said first address domain of said single address translation entry; and if said first address corresponds to the single address translation entry stored in the current page translation register, translating said first address into a second address in a second address domain corresponding to said single address translation entry stored in a current page translation register by substituting said second predetermined number of address bits in said second address domain of the single address translation entry for said first predetermined most significant bits of said first address.