Patent ID: 9412851
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack directly above the patterned multi-layered dielectric film, wherein an edge located at a sidewall of the patterned multi-layered dielectric film is exposed from the patterned stack, wherein the patterned stack comprises an electrically conductive layer; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; performing an ion implantation process by using the cover layer as a mask so as to form a doped region; and completely removing the cover layer after performing the ion implantation process.