Patent ID: 9263375
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method of packaging a semiconductor die (SD), comprising: (a) placing a first component on an adhesive substrate, the first component comprising the SD mounted to a first element that is selected from a group consisting of a first flange and a printed circuit board (PCB), the first element providing electrical conductivity; (b) placing a second flange on the adhesive substrate adjacent to but spaced apart from the first component; (c) electrically interconnecting the SD and the second flange with an electrical interconnect selected from a group consisting of a wire bond and both of at least one conductive layer and at least one dielectric layer; (d) prior to electrically interconnecting the SD and the second flange, housing at least portions of the first component and the second flange by encapsulation with an encapsulation material to form an assembly surrounding the first component and the second flange; and (e) housing the first component and the second flange and the electrical interconnect, wherein a surface of the first element that is farthest from the SD and a flange surface of the second flange are coplanar.