Patent ID: 9406623
Filing Date: 2016-08-02
CPC Classification: H01L,H03K

Claim Text:
1. A system comprising: an array of memory cells coupled to local access lines; and a plurality of string driver circuits, each string driver circuit comprising a transistor comprising a drain terminal coupled to one of the local access lines and a source terminal, the transistor further comprising a drain field plate coupled to the drain terminal and extending from the drain terminal substantially parallel with a drain diffusion region and disposed between the drain diffusion region and a plurality of global access lines to shield the drain diffusion region in a semiconductor material, the transistor further comprising a source field plate coupled to the source terminal and extending from the source terminal substantially parallel with a source diffusion region and disposed between the source diffusion region and the plurality of global access lines, the source field plate separated from the drain field plate by a gate terminal head coupled to a gate electrode of the transistor.