Patent ID: 9385134
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate comprising a memory cell region and a connection region; a plurality of first line groups, each of the plurality of first line groups comprising four first conductive lines extending on the substrate from the memory cell region in a first direction; a plurality of second line groups, each of the plurality of second line groups comprising four second conductive lines extending from the four first conductive lines in a second direction other than the first direction; a plurality of pad groups, each of the plurality of pad groups comprising four pads provided on the substrate and electrically connected to the four second conductive lines; a plurality of dummy lines extend from the plurality of pad groups; and a trim region that electrically opens the plurality of dummy lines, wherein a first line and a second line adjacent to each other in the four second conductive lines form a first line pair, and a third line and a fourth line adjacent to each other in the four second conductive lines form a second line pair, wherein a first extension region is disposed between the first and second line pairs, and each of the first and second line pairs comprises a second extension region.