Patent ID: 9450888
Filing Date: 2016-09-20
CPC Classification: H04L

Claim Text:
1. A method comprising: determining, in an input port register of a node of a system on a chip (SoC), whether incoming information received in the input port register is a valid incoming packet; after determining receipt of the valid incoming packet, determining whether the packet received in the node is destined for a core coupled to the node and if so, providing the packet to an egress queue of the node to enable the packet to be provided to the core; if the received packet is destined for the core, determining whether one or more packets are present in an ingress queue of the node and if so and the one or more packets queue match a global schedule, providing a selected one of the one or more packets from the ingress queue to a first output port or a second output port of the node according to the global schedule, the global schedule independent of traffic flow; and if the received packet is not destined for the core, providing the received packet to the first output port or the second output port according to the global schedule.