Patent ID: 9472582
Filing Date: 2016-10-18
CPC Classification: G02F,H01L

Claim Text:
1. A thin film transistor array panel, comprising: an insulation substrate; a gate line and a data line on the insulation substrate; a first passivation layer on the gate line and the data line; an organic layer on the first passivation layer; a first electrode on the organic layer; a second electrode connected to a thin film transistor via a contact hole defined in the organic layer; and a second passivation layer between the first electrode and the second electrode which is connected to the thin film transistor via the contact hole defined in the organic layer, wherein an edge of the organic layer is exposed by the first electrode at the contact hole via which the second electrode is connected to the thin film transistor, the second passivation layer is extended to define a first portion thereof at the exposed edge of the organic layer, the first portion of the second passivation layer disposed between the second electrode and the organic layer, and the first portion of the second passivation layer extends to be disposed inside the contact hole via which the second electrode is connected to the thin film transistor.