Patent ID: 9372230
Filing Date: 2016-06-21
CPC Classification: G01R

Claim Text:
1. A substrate comprising: a test data in lead; a test clock lead; a test reset lead; a test mode select lead; a command input lead; a command control lead; a match lead; an address input lead; an address command lead; state machine circuitry having a test data input coupled with the test data in lead, a test clock input coupled with the test clock lead, a test reset input coupled with the test reset lead, an enable input, a reset input, a command output coupled with the command input lead, a command control output coupled with the command input lead, a match input coupled with the match lead, an address output coupled with the address input lead, and an address control output coupled with the address control lead; and TAP state monitor circuitry having a test mode select input coupled with the test mode select lead, a test clock input coupled with the test clock lead, a test reset input coupled with the test reset lead, an enable output coupled with the enable input, and a reset output coupled with the reset input.