Patent ID: 9489136
Filing Date: 2016-11-08
CPC Classification: G06F

Claim Text:
1. A method, comprising: identifying a data access request at a first logic component of a first computing device, wherein the data access request involves a second logic component; storing request information associated with the data access request in a first predefined memory space of a memory module connected via a memory channel bus to the first logic component and to the second logic component, wherein the first predefined memory space is known to the second logic component; generating, by the first logic component, a request-ready interrupt signal through one or more redundant pins of the memory channel bus, wherein the redundant pins are pins that are not specified by an industry standard memory channel specification to carry data to or from the memory module; receiving, by the first logic component, a request fulfillment interrupt signal on the one or more redundant pins of the memory channel bus; and completing, by the first logic component, the data access request in response to receiving the request fulfillment interrupt signal.