Patent ID: 9390016
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. A computing device, comprising: a communications substrate; a processor chip coupled to the communications substrate, the processor chip comprising a cache controller; and a cache chip coupled to the communications substrate, wherein the cache chip comprises two or more cache banks, and wherein the processor chip and the cache chip are separate, distinct semiconductor chips; and a silicon photonic waveguide which forms an optical channel that routes an optical signal from an optical transmitter in the cache controller directly to an optical receiver in a first cache bank in the cache chip, wherein the optical channel provides an end-to-end optical link between a structure in the processor chip and the first cache bank, thereby allowing each cache bank on the cache chip to be accessed with uniform latency, wherein separate bi-directional optical channels route optical signals from the cache controller to each cache bank of the cache chip; wherein separate, distinct silicon photonic waveguides route optical signals to each cache bank in the cache chip; wherein the silicon photonic waveguides are arranged in a separate layer from the cache circuitry; wherein the optical channel comprises a first silicon photonic waveguide in the processor chip, a second silicon photonic waveguide in the communications substrate, and a third silicon photonic waveguide in the cache chip; where the first silicon photonic waveguide routes the optical signal to the second silicon photonic waveguide via a first inter-layer coupler; and wherein the optical signal is routed from the second silicon photonic waveguide to a third silicon photonic waveguide via a second inter-layer coupler.