Patent ID: 9449984
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A completed three dimensional memory device, comprising: a substrate; a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate; at least one charge storage region located adjacent to semiconductor channel; and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; wherein each of the plurality of control gate electrodes comprises: wherein surfaces of the semiconductor material portion are in contact with the metal silicide portion and the at least one charge storage region, wherein each vertically neighboring pair of control gate electrodes is spaced by a respective air gap that extends parallel to the major surface of the substrate and is in physical contact with substantially horizontal surfaces of an overlying metal silicide portion and an underlying metal silicide portion wherein a vertically extending volume extending through the plurality of control gate electrodes is adjoined to the air gaps which comprise a plurality of laterally extending volumes located between each vertically neighboring pair of control gate electrodes to provide a contiguous air gap comprising a single undivided space.