Patent ID: 9379109
Filing Date: 2016-06-28
CPC Classification: G11C,H01L

Claim Text:
1. An integrated circuit device having improved radiation immunity, comprising: an n-type die from an n-type wafer having a first surface and a second surface; a p-type epitaxial layer formed on the first surface of the n-type die, the p-type epitaxial layer having first elements storing charge and a p-tap, wherein the p-tap is coupled to a contact configured to receive a ground voltage or a negative voltage; an n-well formed in the p-type epitaxial layer, the n-well having second elements storing charge and an n-type region; and a deep n-well contact coupled to the first surface of the n-type die; wherein the deep n-well contact is coupled to a first positive voltage contact configured to receive a positive voltage; wherein the n-type region of the n-well is coupled to a second positive voltage contact configured to receive a positive voltage; and wherein the n-well and the p-type epitaxial layer form a first p-n junction to attract excess minority carriers in the p-type epitaxial layer, and the n-type die and the p-type epitaxial layer form a second p-n junction to attract excess minority carriers in the p-type epitaxial layer.