Patent ID: 9524980
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A memory device including a plurality of memory cells, comprising: first and second stacks of conductive strips separated by a trench, the conductive strips in the first and second stacks having sidewalls on first and second sides, respectively, of the trench; data storage structures on the sidewalls of the conductive strips; a vertical channel structure having a first semiconductor film disposed vertically in contact with the data storage structures on the first side of the trench, and a second semiconductor film disposed vertically in contact with the data storage structures on the second side of the trench, and electrically connected between the first stack and the second stack to the first semiconductor film; the memory cells in the plurality of memory cells having channels in the first and second semiconductor films and gates in the conductive strips in the first and second stacks; and a patterned conductor layer or layers over the first stack and the second stack, a first interlayer connector connecting a first conductor in the patterned conductor layer or layers to a top surface of the first semiconductor film, and a second interlayer connector connecting a second conductor in the patterned conductor layer or layers to a top surface of the second semiconductor film; wherein an upper strip in the first stack is configured as a gate of a first switch having a channel in the first semiconductor film, and an upper strip in the second stack is configured as a gate of a second switch having a channel in the second semiconductor film.