Patent ID: 9467163
Filing Date: 2016-10-11
CPC Classification: H03M

Claim Text:
1. A delta-sigma modulator, comprising: a first amplifying/integrating circuit comprising: an amplifying/integrating circuit is cascaded in series after the first amplifying/integrating circuit to amplify the first integrated signal by an expected gain to output a respective amplified signal and afterwards integrate the respective amplified signal with a respective integrator to output a respective integrated signal, wherein the amplifying/integrating circuit comprising N stages of amplifying/integrating circuit(s) pair cascaded in series after the first amplifying/integrating circuit, where N is an integer equal to or larger than 1; and a quantizer configured to compare a magnitude of an expected reference signal with a magnitude of a sum of respective signals from each of: the analog input signal, the amplified first output integrated signal of the first amplifying/integrating circuit and the respective amplified output integrated signal from each of the N stages of the cascaded amplifying/integrating circuit(s) pair, to output a digital value as a compared result, wherein, of the first amplifying/integrating circuit and the N stages of the cascaded amplifying/integrating circuit(s) pair, amplifying/integrating circuits which are cascaded in series comprise a delay integrating circuit after a first stage amplifier and a non-delay integrating circuit after a subsequent stage amplifier, respectively.