Patent ID: 9396113
Filing Date: 2016-07-19
CPC Classification: G06F

Claim Text:
1. A processor comprising: a streaming unit configured to load one or more input data streams, wherein the streaming unit includes an internal network having a plurality of queues configured to store streams of data and a plurality of operations circuits configured to perform operations on the streams of data, wherein the streaming unit is programmable to operatively couple two or more of the plurality of operations circuits together via one or more of the plurality of queues, and wherein the plurality of queues includes a plurality of input queues each associated with a corresponding unique one of the plurality of operations circuit and a plurality of output queues each associated with a corresponding unique one of the plurality of operations circuits; wherein the streaming unit is configured to: concurrently load two or more streams from a memory coupled to the processor into corresponding selected ones of the plurality of queues; and concurrently store two or more streams from corresponding selected ones of the plurality of queues to memory.