Patent ID: 9450087
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device that has a source region, a channel region, and a drain region disposed in order from a surface of the semiconductor device in a thickness direction of a semiconductor substrate, the method comprising: a step of forming a gate trench in the semiconductor substrate so that the gate trench penetrates regions where the source region and the channel region are to be formed, respectively, and reaches the drain region; a step of forming a gate insulating film on a side wall of the gate trench, wherein the gate insulating film is formed so as to have a first extended portion that covers the surface of the semiconductor substrate outside of the gate trench; a step of forming a polysilicon gate by embedding polysilicon in the gate trench so that at least a portion of the gate insulating film facing the region of the semiconductor substrate where the channel region is to be formed is covered with the polysilicon gate and so that all of the polysilicon gate is placed under a surface of the semiconductor substrate; a step of forming a second extended portion of the gate insulating film that covers a top surface of the polysilicon gate embedded in the gate trench such that the second extended portion is to be integral with the first extended portion of the gate insulating film and a portion of the gate insulating film on the side wall of the gate trench; a step of forming the channel region in the semiconductor substrate; a step of forming the source region in the semiconductor substrate so as to be placed closer to the surface of the substrate than the channel region; a step of forming an interlayer insulating film on the first and second extended portions of the gate insulating film; a contact groove formation step of forming a source contact groove that penetrates the source region and reaches the channel region in a region different from the gate trench and simultaneously forming a gate contact groove in the polysilicon gate so as to reach a depth of the channel region wherein the source contact groove is formed so as to penetrate the interlayer insulating film and the first extended portion of the gate insulating film, and the gate contact groove is formed so as to penetrate the interlayer insulating film, the second extended portion of the gate insulating film, and the top surface of the polysilicon gate; a step of embedding a source metal in the source contact groove; and a step of embedding a gate metal contiguous to the polysilicon gate in the gate contact groove.