Patent ID: 9443944
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A method comprising: obtaining a wafer with at least one source, at least one drain, and at least one gate; forming a first contact region over at least a portion of the at least one source and at least a portion of an isolation region adjacent to the at least one source; forming a second contact region over at least a portion of the at least one drain and at least a portion of an isolation region adjacent to the at least one drain; forming at least one first small contact over the first contact region, wherein the at least one first small contact is positioned on the first contact region over the isolation region and offset from the at least one source; and forming at least one second small contact over the second contact region wherein the at least one second small contact is positioned on the second contact region over the isolation region and offset from the at least one drain.