Patent ID: 9379697
Filing Date: 2016-06-28
CPC Classification: G09G,G11C,H03K

Claim Text:
1. A gate driver circuit having a plurality of shift registers, each of the shift registers configured for receiving at least one clock signal and a start signal and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on a display panel, the shift register comprising: a control unit having at least one clock input terminal, a first voltage input terminal, a second voltage input terminal, and at least one first output terminal; and a first output unit having a first pull-down TFT electrically connected to one of the first output terminals and a gate-driving terminal configured for providing the gate signal; wherein one of the clock signals at the clock input terminal is provided to the first output unit; wherein a first control signal's period at the first output terminal is longer than the clock signal's period at the clock input terminal and shorter than the period of a frame; and wherein the control unit further comprises a second output terminal and a second output unit having a second pull-down TFT electrically connected to the second output terminal and the gate-driving terminal; the other one of the clock signal at the clock input terminal is provided to the second output unit, and a second control signal's period at the second output terminal is longer than the clock signal's period selected at the clock input terminal and shorter than the period of a frame.