Patent ID: 9490024
Filing Date: 2016-11-08
CPC Classification: G06F,G11C

Claim Text:
1. A solid state storage device, comprising: a non-volatile memory having a memory array composed of plural cells; and a controlling circuit connected with the non-volatile memory, and performing a hard decoding process and a soft decoding process on the non-volatile memory, wherein after the hard decoding process fails, the controlling circuit obtains a first histogram parameter and a second histogram parameter generated in the hard decoding process according to a first sensing voltage, a second sensing voltage and a third sensing voltage, wherein the first histogram parameter is the number of cells between the first sensing voltage and second sensing voltage and the second histogram parameter is the number of cells between the first sensing voltage and the third sensing voltage, wherein before the soft decoding process is performed, a voltage shift amount is obtained according to the first histogram parameter, the second histogram parameter and a voltage shift function relating to the first histogram parameter and the second histogram parameter, and the first sensing voltage, the second sensing voltage and the third sensing voltage are updated according to the voltage shift amount, wherein the non-volatile memory generates a soft data in the soft decoding process according to the updated first sensing voltage, the updated second sensing voltage and the updated third sensing voltage.