Patent ID: 9471529
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. An embedded storage device adapted for use with a computer device, the embedded storage device comprising: a microprocessor for providing a clock signal and creating data transmission link to the computer device; a master storage unit having: a master clock pin coupled to the microprocessor and adapted to receiving the clock signal; at least a master data pin coupled to the microprocessor and adapted to transmitting data; and a master control pin for receiving a command signal from the microprocessor; a slave storage unit having: a slave clock pin coupled to the microprocessor; and at least a slave data pin coupled to the microprocessor and adapted to transmitting data; and a relay bus coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, wherein, as soon as the microprocessor generates and sends the command signal to the master storage unit, the master storage unit determines whether the command signal is for use in controlling and accessing the master storage unit or the slave storage unit, sends the command signal to the slave storage unit by the relay bus, and sends a response signal to the microprocessor by the master control pin.