Patent ID: 9478566
Filing Date: 2016-10-25
CPC Classification: G02F,G09G,H01L

Claim Text:
1. An array substrate, comprising a plurality of pixel units arranged in form of matrix, each pixel unit comprising: a first thin film transistor (TFT), a second TFT, a first pixel electrode and a second pixel electrode; wherein a drain electrode of the first TFT is electrically coupled to the first pixel electrode; a drain electrode of the second TFT is electrically coupled to the second pixel electrode; and the first pixel electrode is electrically insulated from the second pixel electrode, so that when an electric potential difference exists between the first pixel electrode and the second pixel electrode, an electric field is generated between the first pixel electrode and the second pixel electrode; wherein the second pixel electrode is a whole layer coated electrode; the first pixel electrode is a strip-shaped electrode; and the first pixel electrode is arranged on the second pixel electrode having an insulation layer sandwiched therebetween; the second pixel electrode directly extends from the drain electrode of the second TFT.