Patent ID: 9362938
Filing Date: 2016-06-07
CPC Classification: H03M

Claim Text:
1. A method of measuring capacitance error in a successive approximation register (SAR) analog to digital converter (ADC), said ADC including a register and a digital to analog converter (DAC), the method comprising: connecting a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage; connecting a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage; connecting the first capacitance between a first node and the third reference voltage; connecting the first set of one or more capacitances between the first node and the second reference voltage; and measuring a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances; the first reference voltage being a common mode voltage, the second reference voltage being one of a predetermined reference voltage and ground, and the third reference voltage being the other of the predetermined reference voltage and ground.