Patent ID: 9281805
Filing Date: 2016-03-08
CPC Classification: H03K,H03L,H04L

Claim Text:
1. A clock control circuit comprising: a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks; a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks; wherein the second buffer includes a first operation mode that buffers and outputs the second pair of input clocks, and a second operation mode that outputs a high level and a low level of the fixed level.