Patent ID: 9490275
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A method for a thin film transistor array panel, comprising: forming a gate line including a gate electrode, on a substrate; forming an insulating material layer on the substrate and on the gate line; forming a first gate insulating layer from the insulating material layer, comprising: forming a second gate insulating layer on the first gate insulating layer; forming a semiconductor layer on the second gate insulating layer; forming a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; forming a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and forming a pixel electrode connected with the drain electrode, on the passivation layer, wherein the first and second gate insulating layers are between the gate line and the semiconductor layer, the first gate insulating layer has a tensile stress, and the second gate insulating layer has a compressive stress.