Patent ID: 9425102
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a first shallow trench isolation (STI) region and a second STI region in a semiconductor substrate, the first STI region being in a first device region, and the second STI region being in a second device region; forming a first mask covering the second device region; recessing the first STI region to a first depth, a portion of the semiconductor substrate extending from the recessed first STI region forming a first semiconductor fin, the first depth being from a top surface of the first semiconductor fin to a top surface of the recessed first STI region; removing the first mask; forming a second mask covering the first device region; and recessing the second STI region to a second depth different from the first depth, a portion of the semiconductor substrate extending from the recessed second STI region forming a second semiconductor fin, the second depth being from a top surface of the second semiconductor fin to a top surface of the recessed second STI region, a portion of the semiconductor substrate being between the first semiconductor fin and the second semiconductor fin, top surfaces of the first semiconductor fin, the second semiconductor fin, and the portion of the semiconductor substrate being level with each other.