Patent ID: 9473156
Filing Date: 2016-10-18
CPC Classification: G06F,H03L

Claim Text:
1. A phase locked loop with optimum spur reduction of spurious frequency components and fast settling time comprising: a phase detector receiving a reference phase signal and a submultiple phase signal and generating a phase difference signal as difference of the reference signal and the submultiple phase signal wherein the phase difference signal contains high frequency spurious frequencies in a steady state mode of operation; a loop filter in communication with the phase detector to receive the phase difference signal and configured for filtering the spurious frequency components to required criteria and configured for generating the fast settling time for the phase difference signal to generate a frequency control signal with settling criterion to meet allowable offset of a phase locked loop output frequency; an adjustable frequency source in communication with the loop filter to receive frequency control signal and generate an output phase signal; and a feedback divider in communication with the adjustable frequency source to the receive the output phase signal, divide an output phase signal frequency by a factor to generate the submultiple phase signal; wherein the loop filter is based on a closed loop transfer function of the phase locked loop such that the transfer function has a filter prototype configured for meeting the fast settling time; and wherein the transfer function is determined by a gain of the phase detector, a gain of the loop filter, a tuning gain of the adjustable frequency source, criteria for the spurious frequency components, and a maximum frequency step; wherein the closed loop transfer function of the phase locked loop is determined by the equation: