Patent ID: 9435841
Filing Date: 2016-09-06
CPC Classification: G01R,H01L,H02H,H05K

Claim Text:
1. A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system, the method comprising: applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit; applying an ESD simulated signal to one other input of the integrated circuit; conducting the applied ESD simulated signal along a first current path to a first ground; conducting a low-current signal associated with the at least one device along a second current path to a second ground; and maintaining the DC bias voltage between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal; wherein applying the direct current (DC) bias voltage comprises: connecting to the input of the at least one device a first connection having a center conductor and an outer conductor, the center conductor of the first connection delivering the DC bias voltage to the input of the at least one device; and connecting to the second ground a second connection having a center conductor and an outer conductor, the center conductor of the second connection electrically coupling the outer conductor of the first connection to the second ground, and the outer conductor of the second connection connected to the first ground.