Patent ID: 9281030
Filing Date: 2016-03-08
CPC Classification: G11C

Claim Text:
1. A memory device, comprising: a plurality of memory bitcells arranged in columns and rows, each column of the bitcells connected by a pair of bitlines; a write assist circuit connected to at least one pair of the bitlines and configured to inject negative charge to a bitline of the pair of the bitlines to place the bitline in a negative voltage level in a write operation; a column decoder configured to generate a column select signal indicating a column of the bitcells for the write operation, delay of the column select signal changing at a first rate responsive to change in a supply voltage level of the memory device; and a trigger signal generator configured to generate a trigger signal to set time for injecting negative charge into the bitline to place the bitline in the negative voltage level, delay of the trigger signal changing at a second rate higher than the first rate responsive to change in the supply voltage level.