Patent ID: 9236391
Filing Date: 2016-01-12
CPC Classification: H01L

Claim Text:
1. A device comprising: a first gate on a substrate, the first gate having an upper surface; an interpoly isolation layer or charge storage layer on side surfaces of the first gate and extending above the upper surface of the first gate; a second gate adjacent to the interpoly isolation layer or charge storage layer on a first side of the first gate, the second gate having a spacer shape and having an uppermost point of the second gate below the upper surface of the first gate; spacers formed on exposed vertical surfaces of the first and second gates and the interpoly isolation layer; a salicide formed on exposed non-vertical surfaces of the first and second gates and the substrate; and wherein the first gate is one of a select gate and a control gate, and the second gate is the other of a select gate and a control gate, wherein an uppermost point of the interpoly isolation layer or charge storage layer on the first side is higher than an uppermost point of the second side opposite to the first side and an uppermost point of the first gate is lower than the uppermost point of the interpoly isolation layer or charge storage layer on the second side.