Patent ID: 9305635
Filing Date: 2016-04-05
CPC Classification: G11C

Claim Text:
1. A semiconductor memory, comprising: a plurality of sub banks, each sub bank comprising a row of a plurality of memory bit cells, each memory cell coupled to a corresponding local bit line of a plurality of local bit lines, each local bit line coupled to a respective global bit line of a plurality of global bit lines for reading/writing data from/to the plurality of memory bit cells of each sub bank; a plurality of switch elements for each of the sub banks, wherein each switch element couples a local bit line to a corresponding global bit line for data transmission between the local bit line and the global bit line; a plurality of bank selection signal lines, each bank selection signal line coupled to a plurality of switch elements in a corresponding one of the plurality of sub banks, wherein each bank selection signal line is configured to carry a bank selection signal to select one of the plurality of the sub banks for data transmission between the local bit lines coupled to the selected sub bank and the plurality of global bit lines.