Patent ID: 9312383
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device, comprising: patterning a semiconductor structure from an active semiconductor layer of a substrate, the patterned semiconductor structure comprising a planar semiconductor slab, and first and second semiconductor fins vertically extending from the planar semiconductor slab; forming a first insulating spacer to cover the planar semiconductor slab; forming a first gate structure around a lower portion of the first semiconductor fin and a second gate structure around a lower portion of the second semiconductor fin; forming a second insulating spacer which covers a least a portion of the first and second gate structures surrounding the first and second semiconductor fins, and which fills a space between the first and second gate structures; forming first and second source/drain structures on exposed portions of the first and second semiconductor fins extending from the second insulating spacer; forming a third source/drain structure on an exposed portion of the planar semiconductor slab adjacent the first and second insulating spacers; forming a pre-metal dielectric layer over the substrate; and forming first and second conductive via contacts in the pre-metal dielectric layer, wherein the first conductive via contact is formed self-aligned to the first and second source/drain structures, and wherein the second conductive via contact is formed self-aligned to the third source/drain structure.