Patent ID: 9252097
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A semiconductor memory device comprising: a plurality of first wiring lines extending in a first direction; a plurality of second wiring lines extending in a second direction crossing the first direction; a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in crossing portions of the first and second wiring lines; a first dummy-wiring-line region formed in a peripheral area around the memory cell array, the first dummy-wiring-line region comprising a first dummy wiring line and a second dummy wiring line, the first dummy wiring line being formed in the same layer as the first wiring lines and disconnected from the first wiring lines, and the second dummy wiring line being formed in the same layer as the second wiring lines and disconnected from the second wiring lines; a contact formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions; and a plurality of second dummy-wiring-line regions formed in a periphery of the contact, each second dummy-wiring-line region comprising a third dummy wiring line and a fourth dummy wiring line, the third dummy wiring line being formed in the same layer as the first wiring lines and the first dummy wiring line and disconnected from the first wiring lines, disconnected from the first dummy wiring line, and disconnected from other third dummy wiring lines of different second dummy-wiring-line regions, the fourth dummy wiring line being formed in the same layer as the second wiring lines and the second dummy wiring line and disconnected from the second wiring lines, disconnected from the second dummy wiring line, and disconnected from other fourth dummy wiring lines of different second dummy-wiring-line regions, and the second dummy-wiring-line regions are formed surrounding the periphery of the contact; the third dummy wiring lines of different second dummy-wiring-line regions and the fourth dummy wiring lines of different second dummy-wiring-line regions are formed surrounding the periphery of the same respective contact.