Patent ID: 9343306
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A method of fabricating a thin film transistor array substrate, comprising: providing a substrate, the substrate comprising a display region, a gate driver region, and a source driver region; forming an amorphous silicon layer on the substrate; using a laser beam to irradiate the amorphous silicon layer to form a poly-silicon layer, wherein the poly-silicon layer comprises a plurality of main grain boundaries and a plurality of sub grain boundaries, and grain sizes of the poly-silicon layer disposed in the display region and the gate driver region are different from grain sizes of the poly-silicon layer disposed in the source driver region; patterning the poly-silicon layer to form a plurality of poly-silicon islands, wherein the poly-silicon islands disposed in the display region and the gate driver region constitute a plurality of first poly-silicon islands, and the poly-silicon islands disposed in the source driver region constitute a plurality of second poly-silicon islands; defining a source region, a drain region, and a channel region disposed between the source region and the drain region in each of the first poly-silicon islands and each of the second poly-silicon islands, wherein the main grain boundary of each of the first poly-silicon islands is only disposed within the source region and/or the drain region of each of the first poly-silicon islands; and forming a plurality of gates on the substrate to correspond to the channel regions.