Patent ID: 9305853
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device package assembly, comprising: a substrate comprising one or more layers of polymer material with one or more conductive traces in the layers of polymer material; a reinforcement layer at least partially covering a top surface of the substrate, the reinforcement layer being in direct contact with the substrate, wherein the reinforcement layer comprises one or more terminals coupled to the substrate and exposed at a top surface of the reinforcement layer, and wherein the reinforcement layer comprises an opening formed in the reinforcement layer subsequent to the substrate being formed on the reinforcement layer, the opening exposing at least part of the top surface of the substrate; and a die coupled to a terminal pad pattern on the top surface of the substrate, wherein the die is positioned in the opening in the reinforcement layer; wherein the terminal pad pattern on the top surface of the substrate is defined by the conductive traces in a layer of the polymer material at the top surface of the substrate, wherein the conductive traces at the top surface are exposed in the opening in the reinforcement layer when the opening in the reinforcement layer is formed.