Patent ID: 9362275
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate comprising an active region having a first side and a second side opposite to the first side; a first shallow trench isolation (STI) adjoining the first side of the active region; a second STI adjoining the second side of the active region; a first oxide layer over the active region; a first gate electrode over the first oxide layer wherein the width of the first gate electrode is substantially in the range from 38 nm to 40.5 nm; a first dummy gate electrode over the first STI, wherein a width of the first dummy gate electrode is greater than a width of the first gate electrode; and a second dummy gate electrode over the second STI, wherein a width of the second dummy gate electrode is greater than the width of the first gate electrode.