Patent ID: 9324731
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method for fabricating a memory device, comprising: forming a multi-layer stack on a substrate; patterning the multi-layer stack to form a plurality of trenches extending along a first direction, so as to define a plurality of ridge-shaped stacks each of which comprises at least one conductive strip; forming a memory layer and a channel layer in sequence on bottoms and sidewalls of the trenches; forming a sacrifice layer to fulfill the trenches; removing portions of the sacrifice layer, the memory layer and the channel layer formed in the trenches to form a plurality of openings and exposing a portion of the substrate therefrom, wherein the process for forming the plurality of openings comprises: forming a patterned hard mask layer on the ridge-shaped stacks and the sacrifice layer; wherein the patterned hard mask layer has a plurality of patterned opening used to expose portions of the sacrifice layer and the channel; and performing an etching process to remove portions of the memory layer, the channel layer and the sacrifice layer that are not covered by the patterned hard mask layer; removing the remaining sacrifice layer to form a plurality of air gaps in the trenches; performing a deposition process to form an silicon oxide layer covering the openings and the patterned hard mask layer; and patterning portions of the memory layer and the channel layer disposed on the ridge-shaped stacks to form an interconnection interconnecting two adjacent trenches through two of the openings formed in the two adjacent trenches.