Patent ID: 9356024
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate including a transistor element formed in the element region, the transistor element including a transistor buried impurity layer formed within the active layer and being spaced apart from a surface of the active layer; and a substrate contact including wherein the transistor element includes a CMOS transistor having first and second transistors, wherein the first transistor includes a CMOS buried layer as the transistor buried impurity layer, and the first transistor has the same conductivity type as the first conductivity type of the active layer, the second transistor includes a CMOS isolation layer as the transistor buried impurity layer, and the second transistor has an opposite conductivity type to the first conductivity type of the active layer, and the contact buried impurity layer is formed as the same layer as at least one of the CMOS buried layer and the CMOS isolation layer.