Patent ID: 9461148
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: providing a fin formed to protrude from a substrate and a plurality of gate electrodes formed on the fin to intersect the fin, the gate electrodes comprising gate spacers on sidewalls thereof; forming first recesses in the fin on at least one side of the respective gate electrodes; forming an oxide layer in the first recesses; expanding the first recesses into second recesses by removing the oxide layer and partially exposing respective bottom surfaces of the gate spacers; forming source/drain regions in the second recesses by epitaxial growth, wherein the gate electrodes comprise dummy gate electrodes; removing the dummy gate electrodes after forming the source/drain regions in the second recesses; and forming a metal layer on the fin after removing the dummy gate electrodes.