Patent ID: 9298672
Filing Date: 2016-03-29
CPC Classification: G06F,H01L,Y02D

Claim Text:
1. A method for operating a computer processor comprising a first processor chip having a first processor, and a second processor chip having a second processor, wherein the first and second processor chips are connected in a stacked configuration with the first and second processors vertically aligned and connected through vertical connections between the first and second processor chips, wherein the first and second processors have an identical layout of corresponding subsystem regions, the method comprising: generating, by a control system, different sets of configuration parameters to operate the computer processor in different operating modes; generating, by a control system, a first control signal to selectively input a first set of the configuration parameters to the first and second processors; utilizing, by the first and second processors, the first set of the configuration parameters to configure the first and second processors to operate in a first mode of operation, wherein the first and second processors are configured to operate as a single processor by combining subsystem regions of the first and second processors having faster operating speeds and by turning off subsystem regions of the first and second processors having slower operating speeds; generating, by the control system, a second control signal to selectively input a second set of the configuration parameters to the first and second processors; and utilizing, by the first and second processors, the second set of the configuration parameters to configure the first and second processors to operate in a second mode of operation wherein both the first and second processors operate independently without aggregating or sharing resources of the first and second processors.