Patent ID: 9443907
Filing Date: 2016-09-13
CPC Classification: G11C,H01L

Claim Text:
1. A method for forming a non-volatile storage system, the method comprising: forming a three dimensional memory array of memory cells above a substrate; forming a plurality of word lines coupled to a subset of the memory cells; forming a plurality of global bit lines; forming a plurality of vertically oriented bit lines coupled to the memory cells, wherein the vertically oriented bit lines are oriented vertically with respect to the substrate; and forming a plurality of vertically oriented thin film transistor (TFT) select devices, wherein the vertically oriented TFT select devices are oriented vertically with respect to the substrate; wherein forming each of the vertically oriented TFT select devices comprises: forming a plurality of select lines, wherein each of the select lines is coupled to the gates of a group of the plurality of vertically oriented TFT select devices; and forming a plurality of select line drivers associated with the plurality of select lines, each of the select line drivers configured to apply a signal to its associated select line to cause a given vertically oriented TFT select device to connect or disconnect its associated vertically oriented bit line to or from its associated global bit line.