Patent ID: 9515066
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising an insulated gate bipolar transistor arrangement, the insulated gate bipolar transistor arrangement comprising a carrier confinement reduction region laterally arranged between a cell region and a sensitive region, wherein the insulated gate bipolar transistor arrangement comprises a plurality of insulated gate bipolar transistor structures distributed over the cell region and a plurality of insulated gate bipolar transistor structures distributed over the carrier confinement reduction region, wherein the insulated gate bipolar transistor arrangement is configured so that the cell region comprises a first average density of free charge carriers, the carrier confinement reduction region comprises a second average density of free charge carriers and the sensitive region comprises a third average density of free charge carriers in an on-state of the insulated gate bipolar transistor arrangement, wherein the first average density of free charge carriers is larger than the second average density of free charge carriers and the second average density of free charge carriers is larger than the third average density of free charge carriers.