Patent ID: 9330025
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. A memory control apparatus configured to issue a plurality of memory commands in a memory access unit based on a transfer instruction, the memory control apparatus comprising: a reception unit configured to receive a transfer instruction; a plurality of output units configured to each hold at least one transfer instruction and an output status based on the transfer instruction, and, based on the transfer instruction, each output a plurality of memory access requests in a memory access unit; and a command generation unit configured to, based on the plurality of memory access requests, issue a memory command to a memory device, wherein the command generation unit is configured to issue a second memory command that is received by the reception unit after a first transfer instruction and is based on a memory access request related to a second transfer instruction held by a second output unit so as to allow the second memory command to cut in on a plurality of memory commands based on a plurality of memory access requests related to the first transfer instruction held by a first output unit, wherein the first output unit comprises a plurality of status buffers and is configured to, in a case where the memory access request for the second transfer instruction having a high priority is completed, based on a processing status held by a status buffer corresponding to the first transfer instruction having a low priority, resume to output a memory access requirement based on the first transfer instruction, and wherein the plurality of status buffers is provided only for the first transfer instruction having the low priority.