Patent ID: 9396691
Filing Date: 2016-07-19
CPC Classification: G09G,H03K

Claim Text:
1. A method for compensating resistance of signal lines of gate driving circuits, comprising: providing a TFT substrate having a GOA area arranged thereon, the GOA area comprises a plurality of GOA units, each of the GOA units comprises a plurality of GOA modules electrically connecting to one pull-line; providing a control system board electrically connecting to the GOA modules via the pull-lines; adjusting the resistance between the control system board and the GOA modules such that the clock signals provided from the control system board to the GOA modules within the same GOA unit is the same, wherein resistors corresponding to the pull-lines are arranged on the control system board to adjust the resistance between the control system board and the GOA modules such that the RC delay of the clock signals provided from the control system board to the GOA modules within the same GOA unit is the same; and wherein the GOA modules comprise a first GOA module, a second GOA module, a third GOA module, and a fourth GOA module arranged in sequence, the pull-lines comprises a first pull-line, a second pull-line, a third pull-line, and a fourth pull-line electrically connecting to the first GOA module, the second GOA module, the third GOA module, and the fourth GOA module respectively, a length of the first pull-line, the second pull-line, the third pull-line, and the fourth pull-line increases in sequence, the control system board further comprises a first resistor, a second resistor, and a third resistor respectively corresponding to the first pull-line, the second pull-line, and the third pull-line, a resistance of the first pull-line, the second pull-line, the third pull-line, and the fourth pull-line are respectively R