Patent ID: 9330742
Filing Date: 2016-05-03
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a plurality of data output circuits that output data; an address training driver that generates a plurality of address training data and a control signal; a plurality of data lines that transfer the address training data to the data output circuits; and a self-correction circuit that corrects a delay time of the address training data reaching the data output circuits from the address training driver through the plurality of data lines, and that corrects skew of the data outputted from the data output circuits, wherein the self-correction circuit comprises: a Resistor-Capacitor (RC) delay detection block that obtains RC delay information on each node of the plurality of data lines corresponding to the data output circuits, wherein the RC delay detection block comprises: a first signal line including a plurality of output nodes, each outputting a delay value proportional to RC delay of each node of the plurality of data lines, that receives the control signal; and a second signal line including a plurality of output nodes, each outputting a delay value inversely proportional to the RC delay of each node of the plurality of data lines, that receives a signal at a final output node of the first signal line.