Patent ID: 9479171
Filing Date: 2016-10-25
CPC Classification: H03K

Claim Text:
1. An integrated circuit voltage level shifter comprising: a first set of pull-up transistors adapted to selectively pull an output voltage towards a high voltage source level based on an input; a second set of pull-down transistors adapted to selectively pull the output voltage towards a lower voltage source level based on said input; and a third set of transistors to limit current flow through said second set of pull-down transistors and to mitigate snapback of said second set of pull-down transistors using a bias gate voltage wherein said input is substantially limited between said high voltage source level and a medium voltage and said output voltage is substantially limited between said high voltage source level and said lower voltage source level and further wherein said high voltage source level is selected from the range of: 0V to 10V and said medium voltage source is 0V and said lower voltage source is selected from the range of minus 10V and 0V, wherein said high voltage source level is higher or equal to said medium voltage source and said medium voltage source is higher or equal to said lower voltage source level excluding when all of said voltage sources are 0V.