Patent ID: 9281378
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A method comprising: forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate; forming a dummy gate strip layer over the hard mask strip layer; patterning the hard mask strip layer and the dummy gate strip layer using a same etching mask to form a hard mask strip and a dummy gate strip, respectively; recessing second portions of the isolation regions un-covered by the dummy gate strip; forming a gate spacer on a sidewall of the dummy gate strip, wherein an edge of the gate spacer is in physical contact with an edge of the isolation regions, wherein the gate spacer extends below a top surface of the semiconductor strip; removing the dummy gate strip; removing the hard mask strip; and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip, wherein a portion of the semiconductor strip between and contacting the recessed first portions of the isolation regions forms a semiconductor fin.