Patent ID: 9406257
Filing Date: 2016-08-02
CPC Classification: G09G

Claim Text:
1. A display device, comprising: a plurality of pixel units that are arrayed on a substrate in a matrix, and each having a drive transistor, an output switch, a retention capacitor, a pixel switch, a light emitting element, and a pixel circuit that supplies a drive current to the light emitting element; a plurality of first scanning lines, a plurality of second scanning lines, and a plurality of third scanning lines, which are plural kinds of scanning lines arranged along rows in which the pixel units are arrayed; a plurality of video signal lines that are arranged along columns in which the pixel units are arrayed; a plurality of reset lines that are arranged along the rows; a high-potential voltage power supply line, and a low-potential voltage power supply line; a scanning line drive circuit that includes a plurality of reset switches, sequentially supplies a control signal to the plural kinds of scanning lines, and line-sequentially scans the pixel units line by line; and a signal line drive circuit that supplies a gradation voltage signal corresponding to the video signal to the video signal lines according to the line-sequentially scanning operation, wherein the drive transistor is connected in series with the light emitting element between the low-potential voltage power supply line and the high-potential voltage power supply line, a first terminal of the drive transistor is connected to the light emitting element, and a second terminal of the drive transistor is connected to the corresponding reset line, wherein a first terminal of the output switch is connected to a high-potential voltage power supply, a second terminal of the output switch is connected to the second terminal of the drive transistor, and a control terminal of the output switch is connected to the corresponding first scanning line, wherein the retention capacitor is connected between the first terminal of the drive transistor and a control terminal of the drive transistor, wherein a first terminal of the pixel switch is connected to the corresponding video signal line, a second terminal of the pixel switch is connected to the control terminal of the drive transistor, and a control terminal of the pixel switch is connected to the corresponding second scanning line, and the pixel switch captures the gradation voltage signal from the corresponding video signal line, and retains the gradation voltage signal in the retention capacitor, wherein the output switch is shared by four of the pixel units adjacent to each other in a row direction and a column direction, wherein the respective reset switches are disposed for every reset line, a first terminal of each of the reset switches is connected to a reset power supply, a second terminal of the reset switch is connected to the corresponding reset line, and a control terminal of the reset switch is connected to the corresponding third scanning line, and wherein the signal line drive circuit applies an initialization voltage to the control terminal of the drive transistor from the corresponding video signal line, applies a reset potential to the first terminal of the drive transistor from the corresponding reset line to initialize the drive transistor, and the initialization voltage is set to a lower value as a voltage value of the gradation voltage signal written after offset cancellation for offset-canceling a threshold value of the drive transistor is higher.