Patent ID: 9397786
Filing Date: 2016-07-19
CPC Classification: H04L

Claim Text:
1. A system comprising: a plurality of first forward error correction (FEC) code encoders, each of said first FEC code encoders being configured to encode an associated input signal using a first FEC code and provide an associated first FEC code encoded output; an interleaver coupled to at least one of said plurality of first FEC code encoders and configured to provide an interleaved output comprising at least a portion of said associated first FEC code encoded output of said at least one of said plurality of first FEC code encoders; a second FEC code encoder coupled to said interleaver and configured to encode said interleaved output with a second FEC code and provide a second FEC code encoded output; a modulator coupled to said second FEC code encoder and configured to modulate an optical signal in response to said second FEC code encoded output to provide a modulated output signal; a second FEC decoder configured to receive a signal representative of said modulated output signal and decode said signal using said second FEC code to provide a second FEC code decoded output signal; an de-interleaver coupled to said second FEC decoder and configured to provide a plurality of de-interleaved outputs in response to said second FEC code decoded output signal; a plurality of first FEC code decoders, each of said first FEC code decoders being configured to receive an associated one of said de-interleaved outputs and provide an associated first FEC code decoded output signal; a multiplexer configured to receive each of said first FEC code decoded output signals and multiplex said first FEC code decoded output signals into a serial output data stream; and an interleaver configured to interleave said output data stream to provide feedback to the second FEC decoder.