Patent ID: 9281024
Filing Date: 2016-03-08
CPC Classification: G11C

Claim Text:
1. A write block read apparatus for a memory device, the apparatus comprising: a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation, wherein the address conflict occurs when a group of most significant bits of the static write address bits equals a group of most significant bits of the static read address bits, wherein: an output of the static write address decoder is coupled to a dynamic AND gate of the dynamic read address decoder; the dynamic read address decoder comprises first and second level read predecode circuitry, the first level read predecode circuitry receiving each of the static write address bits as inputs thereto, and the second level read predecode circuitry including the dynamic AND gate; and the static write address decoder receives the group of most significant bits of the static write address bits as inputs thereto.