Patent ID: 9397772
Filing Date: 2016-07-19
CPC Classification: H04H,H04L

Claim Text:
1. An apparatus for receiving a digital data stream comprising: a demodulator that receives the digital data stream and demodulates the digital data stream, the digital data stream comprising alternating groups of information blocks and groups of parity blocks, each block comprising a plurality of packets, each packet comprising 187 bytes, each group of information blocks being followed by a group of parity blocks, each group of parity blocks being followed by a group of information blocks, each group of information blocks including a plurality of information blocks and each group of parity blocks including a plurality of parity blocks, wherein each parity block contains only parity packets; an equalizer, that compensates for distortions in the digital data stream to generate a compensated digital data stream; a delay buffer, that generates a first stream of digital data representing the compensated digital data stream and a second stream of digital data representing the compensated digital data stream delayed for a delay period; a forward error correction block, that receives and processes the first and second streams of digital data from the delay buffer, and outputs an error corrected stream of digital data, wherein a first information block in the group of information blocks and a corresponding first parity block in the group of parity blocks together form a potential codeword for an error correction serial concatenated packet block code and the delay buffer and forward error correction block align said first information block in the first stream of digital data with said corresponding first parity block in the second stream of digital data for decoding in a packet block decoder; and a transport block, that receives and processes the error corrected stream from the forward error correction block for display.