Patent ID: 9318420
Filing Date: 2016-04-19
CPC Classification: G11C,H01L

Claim Text:
1. A stack package comprising: a first semiconductor chip stacked on a package substrate; and a second semiconductor chip stacked on a side of the first semiconductor chip opposite to the package substrate, wherein the first semiconductor chip is between the package substrate and the second semiconductor chip, wherein the first semiconductor chip includes first data I/O pads for transmitting data I/O signals, a first flag pad, disposed on a semiconductor substrate of the first semiconductor chip, for receiving a flag signal, and a first buffer for controlling a switching operation between the first data I/O pads and an internal circuit of the first semiconductor chip, wherein the second semiconductor chip includes second data I/O pads for transmitting the data I/O signals, a second flag pad, disposed on a semiconductor substrate of the second semiconductor chip, for receiving the flag signal, and a second buffer for controlling a switching operation between the second data I/O pads and an internal circuit of the second semiconductor chip, wherein the first data I/O pads are electrically connected to respective ones of the second data I/O pads through first wires, and the first flag pad is electrically connected to the second flag pad through a second wire, wherein the package substrate includes a pad, the pad directly electrically connected to the first flag pad through the second wire, and wherein the first flag pad is directly electrically connected to the second flag pad through the second wire.