Patent ID: 9384813
Filing Date: 2016-07-05
CPC Classification: G06F,G11C,H03K

Claim Text:
1. A semiconductor device comprising: a first output node, and k first circuits, where k is an integer of two or more, wherein each of the k first circuits includes a first transistor, a second transistor, a capacitor, and a first memory circuit including a second output node, wherein k first signals are configured to be input to the different k first circuits, respectively, wherein, in each of the k first circuits: one of terminals of the capacitor is electrically connected to the first output node, the other of the terminals of the capacitor is electrically connected to a third output node, the first transistor is configured to control conduction between the first output node and the second output node, and the second transistor is configured to control supply of one of the k first signals to a gate of the first transistor.