Patent ID: 9529745
Filing Date: 2016-12-27
CPC Classification: G06F

Claim Text:
1. A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit, wherein each of the data sources is capable of providing a data stream, wherein the memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer, wherein each of the thus maintained buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer and a data accumulation rate of the respective buffer, wherein the memory control unit is arranged to allocate and de-allocate memory regions to and from each of said buffers in dependence of the data accumulation rate of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers, and wherein the buffer characteristics of each buffer include a hypothetical fill time T and wherein the memory control unit is arranged to associate, with each of the buffers, an allocation threshold T_ALLOC and to allocate a memory region in the memory unit to the respective buffer in response to detecting that the hypothetical fill time T is less than the allocation threshold T_ALLOC.