Patent ID: 9343186
Filing Date: 2016-05-17
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor storage device comprising: a cell array; a redundant array provided logically separated from the cell array, the redundant array comprising a column area replaceable with a defective column in the cell array; a cache memory comprising a storing area of data read from or written in the cell array by one access, the cache memory allowing interleave access to a plurality of divided areas to which the area is logically divided; a defective column storage to store a column address of a defective column in the cell array; a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage; and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area that corresponds to the defective column, at the generation timing of the clock accessing the divided page buffer area, to generate a clock accessing the redundant array that has stored data of the defective column.