Patent ID: 9305930
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a pair of semiconductor fins located on a substrate; a tunneling gate dielectric located on proximal sidewalls of said pair of semiconductor fins; a floating gate electrode located between said pair of semiconductor fins and contacting said tunneling gate dielectric, wherein said floating gate electrode fills an entire space between said pair of semiconductor fins; a control gate dielectric contacting distal sidewalls of said pair of semiconductor fins and a top surface of said floating gate electrode; a control gate electrode overlying said control gate dielectric; a back gate dielectric located in said substrate and contacting bottom surfaces of said pair of semiconductor fins; and a back gate electrode located in said substrate and underlying said back gate dielectric, wherein said tunneling gate dielectric is in contact with portions of a top surface and sidewalls of said back gate dielectric and a top surface of said back gate electrode.