Patent ID: 9257390
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate; an insulating film formed above the semiconductor substrate; and a multilayered wiring formed in a prescribed area within the insulating film, wherein the multilayered wiring comprises a dual damascene wiring positioned on at least one layer of said multilayered wiring, wherein the dual damascene wiring comprises an alloy including copper as a principal component, and wherein a concentration of at least one metallic element contained as an added component of the alloy is 10% or more higher in a via connected to a wiring of the dual damascene wiring having a width that exceeds by five or more times a diameter of the via than that in another via connected to another wiring of the dual damascene wiring of a smallest width in a same upper wiring layer of said multilayered wiring.