Patent ID: 9448338
Filing Date: 2016-09-20
CPC Classification: G02B,Y10T

Claim Text:
1. A method of aligning upper and lower wafers, the lower wafer having a plurality of first optical elements each respectively opposing one of a plurality of second optical elements of the upper wafer, and the lower wafer having a plurality of first alignment features each respectively opposing one of a plurality of second alignment features of the upper wafer, the method comprising: positioning a spacer wafer, the spacer wafer having a plurality of alignment apertures each respectively corresponding one of the plurality of first alignment features, on the lower wafer such that the plurality of alignment apertures align with the plurality of first alignment features; inserting, after the step of positioning, one of a plurality of alignment elements within the each of the alignment apertures; arranging the upper wafer on the spacer wafer such that the upper and lower wafers passively align via the plurality of alignment elements; wherein the first alignment features, and the respective first and second alignment features cooperate to passively align the upper wafer to the lower wafer in at least four degrees of freedom, the four degrees of freedom including: X- and Y-coordinates defining centering of each one of the plurality of first optical elements to a respective one of the plurality of second optical elements, a Z-coordinate defining spacing between the lower wafer and the upper wafer, and rotation of the lower wafer with respect to the upper wafer.