Patent ID: 9348403
Filing Date: 2016-05-24
CPC Classification: G06F,H03L

Claim Text:
1. A microcontroller having a normal operation mode and a low-power operation mode, the microcontroller comprising: a phase locked loop (PLL) circuit that receives a clock signal and generates a first clock in response to the clock signal in a normal-oscillation mode, and that generates a second clock independently from the clock signal in a self-oscillation mode; and a central processing unit (CPU) that operates with the first clock or the second clock in the normal operation mode, and that stops its operation in the low-power operation mode, wherein when the microcontroller returns to the normal operation mode from the low-power operation mode after the microcontroller switches to the low-power operation mode from the normal operation mode, an operation mode of the PLL circuit is determined by the operation mode of the PLL circuit before the switching.