Patent ID: 9311438
Filing Date: 2016-04-12
CPC Classification: G06F,H03K

Claim Text:
1. An integrated circuit (IC) comprising: logic cells; flip-flop cells connected with the logic cells in a combination in a functional mode of operation, and connected together in series in a scan test mode of operation by a scan control signal for shifting scan test data into the IC; and a signal delay cell provided by at least one of the flip-flop cells, wherein the signal delay cell has a first multiplexer having a first data input node, a scan data input node and a first output node, a second multiplexer having a second data input node, a second input node connected to the first output node, and a second output node, and a flip-flop module having a data input connected to the second output node, a clock input node and a flip-flop output node, and wherein the propagation of a scan data input signal applied to the scan data input node in the scan test mode of operation is delayed, and the hold margin of the flip-flop module for the scan data input signal is increased by transit through the first multiplexer, and wherein the first data input node is connected with the combination of cells to receive functional data input signals in the functional mode of operation, and at least a second one of the flip-flop cells has a functional data input node connected to the first output node to receive functional data signals whose propagation is delayed, wherein the hold margin of the second flip-flop cell is increased by transit through the first multiplexer.