Patent ID: 9478565
Filing Date: 2016-10-25
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising a first region and a second region adjoining the first region, a plurality of signal lines being provided in the first region, and a plurality of lead wires connected with the plurality of signal lines being provided in the second region, wherein the array substrate comprises at least one conductive member, each conductive member is connected in parallel with one lead wire, and an overall resistance of the conductive member and the lead wire connected in parallel with the conductive member is smaller than a resistance of the lead wire connected in parallel with the conductive member, transparent electrodes are provided in the first region, each conductive member comprises a transparent conductive member made of the same material as the transparent electrode and provided in the same layer as the transparent electrode, an insulation layer is provided between a layer comprising the transparent electrode and the transparent conductive member and a layer comprising the lead wires, and each transparent conductive member is connected with the lead wire through at least one via penetrating through the insulation layer, so that the transparent conductive member is connected in parallel with the lead wire.