Patent ID: 9490315
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A method of fabricating a power semiconductor device comprising an active area and a cutoff ring located at a periphery of the active area, wherein the method comprises: forming at least one trench by etching the cutoff ring; implanting ions into the trench to form an implant area located below the trench; and performing thermal oxidation on the power semiconductor device to form a silicon dioxide dielectric layer covering the trench and a surface of the active area; wherein the power semiconductor device further comprises a scribe line located at a periphery of the cutoff ring; forming at least one trench by etching the cutoff ring comprises: coating a photoresist on surfaces of the scribe line, a divider area and the active area and a surface of the cutoff ring; exposing and developing the photoresist to expose a part of the surface of the cutoff ring; and forming the trench in the exposed part of the cutoff ring by using a dry etching which is one of a reactive ion etching and an inductive coupling plasmas etching; and after the ions are implanted into the trench to form the implant area located below the trench, the method further comprises: removing the photoresist.