Patent ID: 9478562
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A manufacturing method of an array substrate, comprising: sequentially forming an active material layer, a gate insulating layer and a metal thin film on a base substrate, and patterning the active material layer, the gate insulating layer and the metal thin film by a first patterning process, so as to form a pattern including an active layer and a pattern including a gate electrode, a source electrode, a drain electrode, a gate line and a data line, with a part of the gate insulating layer being exposed at a periphery of the gate electrode, the gate line or the data line being disconnected at an intersection of the gate line and the data line; forming a passivation layer on the base substrate, and patterning the passivation layer by a second patterning process, so as to form a source contact hole, by which a part of the source electrode and a part of the active layer are exposed, a drain contact hole, by which a part of the drain electrode and a part of the active layer are exposed, and a bridge-structure contact hole, by which a part of disconnected gate line or data line is exposed; forming a transparent conductive thin film on the base substrate, and removing the transparent conductive thin film partially, so that a source contact section for electrically connecting the source electrode and the active layer is formed in the source contact hole, a drain contact section for electrically connecting the drain electrode and the active layer is formed in the drain contact hole, a pixel electrode electrically connected to the drain contact section is formed on the passivation layer above the drain electrode, and an bridge structure for electric connection of the disconnected gate line or data line is formed within the bridge-structure contact hole and over the passivation layer.