Patent ID: 9256261
Filing Date: 2016-02-09
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor device comprising an identification information generation circuit including a power supply control circuit having a first input node to which a first control signal is applied, a first power supply voltage output node and a second power supply voltage output node, and a memory array having a bit line pair, a word line, a memory cell connected to said bit line pair and said word line, a first cell power line connected to said memory cell, and a second cell power line connected to said memory cell, said first cell power line and said second cell power line being connected to said first power supply voltage output node and said second power supply voltage output node, respectively, said memory cell having a first conductivity type MOS transistor and a second conductivity type MOS transistor, said power supply control circuit being configured to output a first supply voltage and a second supply voltage to said first power supply voltage output node and said second power supply voltage output node, respectively, when said first control signal is in a first state, and output an intermediate voltage to said first power supply voltage output node and said second power supply voltage output node when said first control signal is in a second state.