Patent ID: 9263582
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: an active region positioned above a substrate; a field effect transistor positioned in and above said active region; a contact structure connecting to said active region, said contract structure defining a direction of current flow through a channel region of said field effect transistor; a buried insulating layer positioned between said substrate and said active region, said buried insulating layer comprising a piezoelectric material layer that is in direct contact with and mechanically coupled to said active region; an isolation structure laterally defining said active region and said buried insulating layer, wherein said buried insulating layer is coextensive with said active region; a first contact connecting to a first contact portion on an upper surface of said piezoelectric material layer; and a second contact connecting to a second contact portion on said upper surface of said piezoelectric material layer, wherein said first and second contact portions of said piezoelectric material layer are positioned so as to define an electric field direction in said piezoelectric material layer that is aligned to said direction of current flow through said channel region of said field effect transistor.