Patent ID: 9331091
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method of forming a 3D NAND memory, comprising: (a) forming a multi-layer slab on top of a semiconductor substrate with layers corresponding to structures of an array of vertically aligned NAND strings, the layers including memory layers initially constituted from a sacrificial material; (b) forming an array of vertical shafts in rows and columns through openings across a top surface of the multi-layer slab, wherein the rows of vertical shafts are interleaved by ledges, each row of vertical shafts provides access for forming memory cells at the memory layers under an adjacent ledge, and wherein the array of vertical shafts is partitioned into first and second subarrays of either odd or even shafts; (c) selecting the vertical shafts of the first subarray while masking those of the second subarrays; (d) forming grottoes by isotropically recessing the sacrificial material of the memory layers though the selected vertical shafts, each grotto having walls intruding about halfway into a respective adjacent ledge; (e) depositing a layer of word line material in each grotto to form a socket component of a word line; (f) depositing a layer of insulating material to line the socket component of a word line; (g) filling the socket component with a floating gate material to form an embedded floating gate; (h) forming other structures of the NAND strings and a plurality of vertical bit lines through the selected vertical shafts; and (i) selecting the vertical shafts of the second subarray while masking those of the first subarray and repeating (d)-(h), and wherein said isotropically recessing in (d) has the wall of each grotto contiguous with adjacent one in the same memory layer formed through the vertical shafts of the first subarray to form a continuous word line with socket components in a row.