Patent ID: 9425091
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A method for forming a semiconductor structure, comprising: forming a first etch stop layer (ESL); forming an oxide region above the first ESL; forming a low-k (LK) dielectric region above the oxide region; forming a first metal line through at least one of the first ESL, the oxide region, or the LK dielectric region; forming a second metal line through at least one of the first ESL, the oxide region, or the LK dielectric region; forming a second ESL over at least one of the first metal line, the second metal line, or the LK dielectric region; removing at least a portion of the second ESL at least one of: forming a gap by removing at least one of: forming an ESL seal region over at least one of the second ESL, the first metal line, the second metal line, or the gap.