Patent ID: 9343524
Filing Date: 2016-05-17
CPC Classification: G06F,H01L

Claim Text:
1. A semiconductor device comprising, a substrate having at least one dielectric layer disposed on the substrate surface; a first dielectric etchstop layer and a second dielectric etchstop layer disposed on the dielectric layer, wherein the second dielectric etchstop layer is disposed directly on the first dielectric etchstop layer; and a well formed through the first and second dielectric etchstop layers and in the at least one dielectric layer, wherein the well comprises inwardly tapered sidewalls and a bottom, and a first layer of conducting material is disposed on the inwardly tapered sidewalls and bottom of the well, an insulating layer disposed on the first layer of conducting material, and a second layer of conducting material disposed on the insulating layer.