Patent ID: 9257644
Filing Date: 2016-02-09
CPC Classification: G11C,H01L

Claim Text:
1. A method of manufacturing a variable resistance memory device, the method comprising: forming a common source line on a semiconductor substrate; forming selection switches on the common source region; forming, over the selection switches, an insulating structure on the semiconductor substrate by alternately stacking a plurality of first interlayer insulating layers, having a first etch selectivity, and a plurality of second interlayer insulating layers, having a second etch selectivity that is different than the first etch selectivity; forming through-holes in the insulating structure to expose the string selection switches; forming space portions by removing portions of the plurality of first interlayer insulating layers exposed through the through-holes; forming a cell drain region in each of the space portions; forming, in each through-hole, a channel layer along surfaces defining each through-hole; selectively removing the plurality of second insulating layers to form a plurality of openings; forming a gate insulating layer in each opening of the plurality of openings; forming a cell gate electrode in each opening, of the plurality of openings, so that each cell gate electrode is surrounded by a gate insulating layer; forming a variable resistance layer on a surface of the channel layer; forming an insulating layer in the through-holes; and forming a bit line to be electrically connected to the channel layer and the variable resistance layer.