Patent ID: 9275754
Filing Date: 2016-03-01
CPC Classification: G09G,G11C

Claim Text:
1. A shift register, comprising: a plurality of odd latch units and a plurality of even latch units connected in series, the plurality of odd latch units each configured to output a first control signal in response to a first clock signal, the plurality of even latch units each configured to output a second control signal in response to a second clock signal, the first clock signal being inverted from the second clock signal and being delayed by a half period with respect to the second clock signal, the first control signal and the second control signal being sequentially and alternately outputted; a plurality of odd sampling units and a plurality of even sampling units, the plurality of odd sampling units connected to the respective odd latch units and the plurality of even sampling units connected to the respective even latch units, the plurality of odd sampling units configured to output a first sampling signal in response to the first control signal and a low level of the second clock signal, the plurality of even sampling units configured to output a second sampling signal in response to the second control signal and a high level of the second clock signal, the first sampling signal and the second sampling signal being sequentially and alternately outputted; and a plurality of storing cells respectively connected to the sampling units and configured to: