Patent ID: 9281258
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A chip scale package (CSP), comprising: a die; a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead, the first surface of the first lead forming a first plane and a second surface of the first lead forming a fifth plane, a thickness of the first lead present between the first plane and the fifth plane; a second lead mechanically coupled to a second surface of the die at a first surface of the second lead, the first surface of the second lead forming a second plane and a second surface of the second lead forming a fourth plane, a thickness of the second lead present between the second plane and the fourth plane; and a mold compound at least partially encapsulating the die, where the die, first lead, second lead, and mold compound form a chip scale package (CSP); wherein the first plane of the first lead and the second plane of the second lead are oriented substantially perpendicularly to a third plane formed by a motherboard when the CSP is coupled to the motherboard at the thickness of the first lead and the thickness of the second lead.