Patent ID: 9479866
Filing Date: 2016-10-25
CPC Classification: H04R

Claim Text:
1. A system comprising a plurality of microphone stages arranged in a daisy chained array, each microphone stage in the plurality of microphone stages arranged in the daisy chained array comprising: an analog to digital converter (ADC) having an input for receiving a microphone signal and outputting a digital code; a decimation unit having an input for receiving the digital code and for decimating the digital code, producing a decimated digital code, and for outputting the decimated digital code; a receiver for receiving a first serial data stream including a cumulative sum of decimated digital codes outputted by decimation units of prior microphone stages in the daisy chained array; a delay unit configured to delay sound from a particular direction represented as the decimated digital code outputted by the decimation unit to time-align with the cumulative sum of the decimated digital codes outputted by the decimation units of the prior microphone stages in the daisy chained array to produce a delayed decimated digital code; an adder that adds the delayed decimated digital code outputted from the delay unit to the received cumulative sum of the decimated digital codes for producing and outputting an updated cumulative sum that is formed from adding the decimated digital code and the received cumulative sum; a transmitter for transmitting a second serial data stream including the updated cumulative sum outputted by the adder to a next microphone stage of the plurality of the microphone stages in the daisy chained array; and wherein the delay unit comprises: wherein the second serial data stream transmitted between the microphone stages includes configuration data specifying a delay in a number of clock cycles that each delay unit is to implement, and wherein each of the microphone signal and the cumulative sum represents at least one audio signal.