Patent ID: 9385042
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising a complementary metal-oxide semiconductor (CMOS) circuit formed on a (551) plane of silicon, wherein the CMOS circuit includes an n-type transistor and a p-type transistor, each of the n-type transistor and the p-type transistor includes a diffusion region and a silicide layer, said silicide layer of each of the n-type transistor and the p-type transistor (i) being in contact with the diffusion region and (ii) consisting of silicon and a metal material, a thickness of the silicide layer, which is in contact with the diffusion region of the n-type transistor, is not less than 2 nm and is not more than 8.5 nm, and a thickness of the silicide layer, which is in contact with the diffusion region of the p-type transistor, is thicker than the thickness of the silicide layer of the n-type transistor.