Patent ID: 9317366
Filing Date: 2016-04-19
CPC Classification: G06F

Claim Text:
1. A computing system, the system comprising: a buffer integrated circuit device comprising: a substrate member comprising a silicon bearing material; an output driver formed on the substrate member, the output driver having at least a command bus and an address bus, the command bus and the address bus being configured to a plurality of memory devices; a protocol and parity checking block (“Block”), the protocol and parity checking block comprising a protocol circuit formed on the silicon bearing material and a parity circuit configured with the protocol circuit; a table configured in the block, the table being programmable with a plurality of timing parameters, the plurality of timing parameters being at least one or two of tCL, tRCD, tRP, tWR, tAL, tRFC, tRRD, tCCD, tRAS, or tCWL; a memory state block, the memory state block coupled to the table; and a command history table, the command history table coupled to the table, and configured with the memory state block to process protocol information for all commands that pass through the Block; and a host memory controller in communication with the buffer integrated circuit device.