Patent ID: 9319080
Filing Date: 2016-04-19
CPC Classification: H04L

Claim Text:
1. A detection enhanced adjustable bandwidth signal detection circuit apparatus, comprising: an analog-to-digital converter into which an analog signal is input, wherein said analog-to-digital converter digitizes said analog signal; a parser for parsing said digitized signal into sequential vectors of element length N; a weighting window for weighting said parsed vectors; a Fourier transformer for transforming and squaring said weighted vectors; a logarithmic compressor for compressing the amplitude of said Fourier transformed vectors; a vector processor for signal processing said Fourier transformed vectors; and a digital-to-analog converter having as an input said signal processed vectors and having as an output voltage signals, wherein said voltage signals further comprise video and control signals for inputs to a graphical display means, wherein said vector processor further comprises: