Patent ID: 9520189
Filing Date: 2016-12-13
CPC Classification: G11C

Claim Text:
1. A computer-implemented method for performing a voltage-based measurement of a resistive memory cell having a plurality of programmable cell states, the method comprising: providing, via a processor, a prebiased voltage at a connecting node coupled to the resistive memory cell; coupling, via the processor, a resistor circuit in parallel to the resistive memory cell such that the resistor is configured to reduce an effective resistance at the connecting node of the prebiasing circuit; prebiasing a bitline capacitance of the resistive memory cell by the prebiasing circuit; settling, via the processor, a sensing circuit to a target voltage by connecting the sensing circuit to one of a plurality of settling circuits, wherein the one of the plurality of settling circuits is selected based on a temperature reading of the resistive memory cell; sensing a voltage of the resistive memory cell; and outputting a resultant value based on the sensed voltage.