Patent ID: 9496361
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a semiconductor structure, comprising: forming a plurality of gate trenches in a first dielectric layer on a semiconductor substrate, wherein a sidewall spacer layer is formed on the semiconductor substrate and on at least two sides of each gate trench; forming a plurality of first metal gates on the semiconductor substrate, wherein each of the first metal gates comprises an upper part and a lower part connected to the upper part, the lower part is formed in one of the gate trenches, and the upper part covers at least a part of the sidewall spacer layer in a vertical direction, wherein the upper part and the lower part of the first metal gate are formed by an identical process together; and forming a source/drain contact between two adjacent gate trenches, wherein the first dielectric layer is formed between the gate trenches, and the step of forming the source/drain contact comprises: