Patent ID: 9397210
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A memory array, comprising: first and second memory cells over a semiconductor; an isolation region extending into the semiconductor, comprising: a second dielectric passing over the upper surface of the second thickness of the first dielectric and the dielectric liner so that a first portion of the second dielectric extends beyond the first side of the dielectric liner and over the charge storage structure of the first memory cell and a second portion of the second dielectric extends beyond the second side of the dielectric liner and over the charge storage structure of the second memory cell; and a conductor over the second dielectric; wherein the second dielectric is between the conductor and the second thickness of the first dielectric and between the conductor and the dielectric liner and separates the conductor from the second thickness of the first dielectric and the dielectric liner.