Patent ID: 9460038
Filing Date: 2016-10-04
CPC Classification: G06F

Claim Text:
1. A microprocessor, comprising: a plurality of physical pins for coupling the microprocessor to a bidirectional processor bus coupled to a chipset, the processor bus comprising data and address lines; a die having a plurality of processing cores, each core having a bus interface coupling respective inputs and outputs of the core to corresponding bidirectional lines of the processor bus; and a bypass bus on the die that enables at least first and second complementary cores of the die to bypass the processor bus in order to communicate directly with each other, the bypass bus providing bus lines corresponding to all of the data and address lines of the processor bus; wherein the bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-driven signals from the processor bus; wherein when the first core drives values on the processor bus to the chipset, the bus interface of the second core causes the second core to observe the values driven by the first core directly from the bypass bus rather than from the processor bus; and wherein when the second core drives values on the processor bus to the chipset, the bus interface of the first core causes the first core to observe the values driven by the second core directly from the bypass bus rather than from the processor bus.