Patent ID: 9344267
Filing Date: 2016-05-17
CPC Classification: H04L

Claim Text:
1. A data receiver, comprising: a serial-data processing circuit, configured to receive a serial data, generate an operation clock according to the serial data, and dynamically modulate a frequency of the operation clock until the frequency of the operation clock is locked in a correct frequency, the serial-data processing circuit being further configured to restore the serial data back to a parallel data according to the operation clock, and perform a data latch operation on the parallel data according to the operation clock thereby restoring the parallel data back to a required data, the serial-data processing circuit being further configured to determine whether the frequency of the operation clock is correct or not and accordingly generate a first determination result, and determine, according to a reset control signal, whether to re-generate the operation clock or not according to the serial data; a null-frequency detecting circuit, electrically coupled to the serial-data processing circuit and configured to receive the operation clock, determine whether the received operation clock is locked or null, and accordingly output a second determination result; a data checking circuit, electrically coupled to the serial-data processing circuit and configured to be either enabled or disabled according to the first determination result, the enabled data checking circuit being configured to obtain a checking data contained in the required data according to the operation clock, determine whether the checking data is correct or not, and accordingly output a third determination result; a state control circuit, electrically coupled to the serial-data processing circuit and configured to output a frequency-locked indication signal and change a state of the frequency-locked indication signal according to the first, second and third determination results; and a timeout detecting circuit, electrically coupled to an output terminal of the status control circuit and configured to determine whether the state of the frequency-locked indication signal is not converted into a predetermined state in a predetermined time or not and generate the reset control signal when the state of the frequency-locked indication signal is not converted into the predetermined state in the predetermined time.