Patent ID: 9276007
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a memory device, the method comprising: performing a shallow trench isolation process on a semiconductor material to form a plurality of active regions over the semiconductor material, the plurality of active regions having a plurality of sharp corners; forming a plurality of isolation regions separating the plurality of active regions, the plurality of sharp corners of the plurality of active regions being exposed during the forming of the plurality of isolation regions; rounding the plurality of sharp corners; filling the plurality of isolation regions with an insulator material; forming a plurality of charge trapping structures over the plurality of active regions, wherein the plurality of charge trapping structures are self-aligned, are separated from each other, and wherein each charge trapping structure corresponds specifically to a different active region of the plurality of active regions; and forming a first layer of semiconductor or conductive material over the charge trapping structure.