Patent ID: 9323665
Filing Date: 2016-04-26
CPC Classification: G06F

Claim Text:
1. A circuit for generating a start sequence, comprising a series of operations that are performed by a computing unit in a switch-on process, the circuit comprising: an at least partially programmable memory for storing a coded sequence; a control unit, which is designed to read the coded start sequence and decode it into a decoded start sequence and to generate at least one target register address on the basis of the coded start sequence; and an addressable memory, which has a set of registers with register addresses, and into which the decoded start sequence can be written at the target register address by means of the control unit, one of the register addresses being defined by the target register address, wherein at least one of the register addresses of the addressable memory is linked to a voltage supply circuit of the computing unit, and wherein at least one of the register addresses of the addressable memory is linked to an input/output interface of the computing unit.