Patent ID: 9337215
Filing Date: 2016-05-10
CPC Classification: G02F,H01L

Claim Text:
1. A method for fabricating an active matrix substrate, the method comprising: forming, on a pixel region of the active matrix substrate, a gate line forming portions of a plurality of semiconductor elements, and forming a plurality of wiring layers on a frame region of the active matrix substrate surrounding the pixel region, the wiring layers being made of a same material as the gate line and extending in parallel; forming a gate insulating layer on the frame region and the pixel region to cover the wiring layers and the gate line; forming a semiconductor material layer on a surface of the gate insulating layer on the frame region and the pixel region; forming a first resist covering a portion of the semiconductor material layer over the pixel region, and second resists individually covering portions of the gate insulating layer between adjacent pairs of the wiring layers; and etching portions of the semiconductor material layer exposed from the first and second resists by dry etching to form semiconductor layers forming portions of the semiconductor elements; wherein in the forming of the second resists, only portions of each of the adjacent pairs of the wiring layers are covered by each of the second resists with remaining portions of the adjacent pairs remaining uncovered by the second resists.