Patent ID: 9236869
Filing Date: 2016-01-12
CPC Classification: G06F,H03K,H03L

Claim Text:
1. A semiconductor device comprising: a first sampling circuit for outputting a data value and an edge value corresponding to odd-numbered data of data contained in an input signal, using multiphase sampling clocks including a plurality of sampling clocks having different phases by 90 degrees; and a second sampling circuit for outputting a data value and an edge value corresponding to even-numbered data of data contained in the input signal, using the multiphase sampling clocks, wherein one piece of data is sampled in one sampling period, and two sampling periods are included in one cycle of the sampling clock, the first sampling circuit and the second sampling circuit each comprising: a first data sampling circuit which adds a negative offset to a signal level of the input signal, samples the input signal, and outputs a first data value; a second data sampling circuit which adds a positive offset to the signal level of the input signal, samples the input signal, and outputs a second data value; a selector for selecting and outputting the first data value or the second data value as the data value, based on a data value sampled in a last sampling period; a shift register for shifting and outputting the data value outputted by the selector to a subsequent register in order; a first edge sampling circuit which adds a first offset to the signal level of the input signal and outputs a first edge value indicating a value of an edge part of the input signal; and a second edge sampling circuit which adds a second offset to the signal level of the input signal and outputs a second edge value indicating a value of an edge part of the input signal, wherein at least one of the first offset and the second offset in one sampling circuit is determined based on a data value acquired from a location other than between the selector and the shift register in the other sampling circuit.