Patent ID: 9263282
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method of fabricating semiconductor patterns, comprising steps as follows: providing a substrate, wherein the substrate comprises a silicon layer formed thereon and a protection layer formed atop the silicon layer; forming a dummy structure on the protection layer, forming a spacer layer on a sidewall of the dummy structure with a semiconductor material; removing the dummy structure; forming at least a first semiconductor pattern and at least a second semiconductor pattern with the spacer layer on the protection layer, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern; forming a barrier pattern over a surface of the first semiconductor pattern, and exposing the second semiconductor pattern; forming a sacrificial structure layer by reacting a surface portion of the second semiconductor pattern; and removing the barrier pattern and the sacrificial structure layer to obtain the line width of the second semiconductor pattern configured to be less than the line width of the first semiconductor pattern.