Patent ID: 9459309
Filing Date: 2016-10-04
CPC Classification: G01R

Claim Text:
1. A test device for testing a semiconductor device including a through silicon via (TSV), the test device comprising: a ring oscillator including a plurality of inverters; a counter counting a clock signal output from the ring oscillator; a switch selectively connecting an output node of an inverter of the plurality of inverters with the TSV; and a controller controlling the switch to disconnect the node and the TSV for a first time period and to connect the node and the TSV for a second time period, wherein the controller tests the TSV by comparing a first counter value of the counter for the first time period to a second counter value of the counter for the second time period, and the controller determines that the TSV has passed a test when a difference between the first counter value and the second counter value is greater than a threshold value.