Patent ID: 9484349
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A static random access memory, comprising at least one static random access memory cell, wherein a gate layout of the static random access memory cell comprises: a first strip doped region, a second strip doped region, a third strip doped region, and a fourth strip doped region, disposed in a substrate in order and separated from each other; a recessed gate line, intersecting the first strip doped region, the second strip doped region, the third strip doped region, and the fourth strip doped region, wherein the first strip doped region, the second strip doped region, the third strip doped region, and the fourth strip doped region are disconnected at intersections with the recessed gate line; a first gate line, intersecting the first strip doped region and the second strip doped region, wherein the first strip doped region and the second strip doped region are disconnected at intersections with the first gate line; and a second gate line, intersecting the third strip doped region and the fourth strip doped region, wherein the third strip doped region and the fourth strip doped region are disconnected at intersections with the second gate line.