Patent ID: 9301395
Filing Date: 2016-03-29
CPC Classification: H01G,H01L,H05K,Y02P,Y10T

Claim Text:
1. A surface mounted layout to reduce voltage noise on a printed circuit board, comprising: a first co-layout of multilayer ceramic capacitors mounted on a first corner of a rectangular footprint of a bottom side of the printed circuit board; a second co-layout of multilayer ceramic capacitors mounted on a second corner of the rectangular footprint of the bottom side of the printed circuit board diagonal to the first corner; and a first solid electrolytic polymer capacitor and a second solid electrolytic polymer capacitor mounted on the remaining corners, respectively, of the rectangular footprint of the bottom side of the printed circuit board, wherein the rectangular footprint of the printed circuit board is a footprint of a high-speed processing unit mounted on the printed circuit board, and wherein the high-speed processing unit is mounted on a top side of the printed circuit board opposite the bottom side comprising the first co-layout of multilayer ceramic capacitors and the second co-layout of multilayer ceramic capacitors, and wherein a set of leads of at least one of the first co-layout of multilayer ceramic capacitors, the first solid electrolytic polymer capacitor, the second co-layout of multilayer ceramic capacitors, and the second solid electrolytic polymer capacitor is coupled to at least one of a voltage supply pin and a ground pin of a voltage supply of the high-speed processing unit through a via.