Patent ID: 9293432
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A chip package structure, comprising: a semiconductor substrate; a metal pad inside the semiconductor substrate; an insulating layer on the semiconductor substrate, the insulating layer having an opening exposing a first surface of the metal pad; a sub-ball metal electrode on the first surface of the metal pad, wherein the sub-ball metal electrode partially covers the first surface; a solder ball encompassing the sub-ball metal electrode, wherein the solder ball comprises a first portion extending from the bottom part of the sub-ball metal electrode along directions substantially in parallel with the first surface, such that the first portion of the solder ball covers at least a part of the first surface which is not covered by the sub-ball metal electrode; and a covering layer disposed between the solder ball and the sub-ball metal electrode, and between the solder ball and the first surface of the metal pad, wherein the covering layer is a stacked structure comprising an anti-diffusion layer and a wetting layer, wherein the anti-diffusion layer is disposed on the surface of the sub-ball metal electrode and has a first apron structure, and the wetting layer is disposed on a surface of the anti-diffusion layer and has a second apron structure.