Patent ID: 9466590
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method of assembling a multi-chip system, comprising: providing a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the major surfaces; providing a bottom chip stack element comprising a bottom substrate having two major surfaces, bottom solder pads arrayed along a plane of one of the major surfaces, conduits connected to one or more of the bottom solder pads, and a reservoir pad connected to each of the conduits; plating a first solder material on the bottom solder pads; plating a second solder material on the reservoir pads; aligning the top chip stack element and the bottom chip stack element to bring one or the top solder pads into proximity with the solder material; raising the temperature to melt both of the first solder material and the second solder material; connecting the solder material to the top solder pads to form a connected assembly; and cooling the connected assembly to re-solidify both of the first solder material and the second solder material, wherein the second solder material has a higher melting temperature than the first solder material.