Patent ID: 9477386
Filing Date: 2016-10-25
CPC Classification: G06F,H03K,H03M

Claim Text:
1. A method for processing a signal, the method comprising: configuring a programmable hardware element of a device to comprise a plurality N of processing portions, wherein the number N of processing portions is based on a processing rate of the programmable hardware element and an effective sampling rate K; receiving, at the device, an input signal; sampling, by an analog to digital converter (ADC) of the device, the input signal, wherein said sampling is performed in an interleaved fashion on a per sample basis at the effective sampling rate K and wherein said sampling produces a plurality N of parallel data streams, wherein the effective rate K is greater than the processing rate of the programmable hardware element, wherein each of the N data streams has a rate K/N, wherein the rate K/N is not greater than the processing rate of the programmable hardware element; each of the N processing portions processing a respective one of the N parallel data streams in parallel, wherein said processing produces a plurality of intermediate data streams; and combining the plurality of intermediate data streams to produce output data.