Patent ID: 9368308
Filing Date: 2016-06-14
CPC Classification: H01H,Y10T

Claim Text:
1. A fuse in chip design, comprising: a substrate having a top surface and a first edge, opposite second edge, first side edge and opposite second side edge; an intermediate layer having a thermal conductivity lower than that of the substrate, the intermediate layer being disposed on and in direct contact with the substrate and sized and positioned so as to leave exposed portions of the top surface of the substrate between the intermediate layer and the edges of the substrate, the intermediate layer comprising at least one of an inorganic glass paste or an inorganic material; an adhesive layer covering and in direct contact with the intermediate layer and the exposed portions of the top surface of the substrate, wherein the adhesive layer reaches to the edges of the substrate; a fusible metallic conductor fabricated using thin-film technology covering and in direct contact with at least a portion of the adhesive layer and extending between the first edge of the substrate and the second edge of the substrate; a cover layer coated over at least a central region of the fusible metallic conductor and in contact with at least a portion of the adhesive layer; a first contact plated on top of at least a portion of the fusible metallic conductor adjacent the cover layer and the first edge of the substrate; and a second contact plated on top of at least a portion of the fusible metallic conductor adjacent the cover layer and the second edge of the substrate.