Patent ID: 9406787
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate having a first conductivity type; a first insulating layer formed over a main surface of the semiconductor substrate; a trench formed in the first insulating layer; a first semiconductor layer formed over the semiconductor substrate exposed at a bottom portion of the trench in the trench; a pair of gate electrodes formed on both sides of the first semiconductor layer in the trench such that the first semiconductor layer is interposed therebetween; gate insulating films interposed between the first semiconductor layer and the pair of gate electrodes in the trench; a second insulating layer formed over the first insulating layer so as to cover the first semiconductor layer and the pair of gate electrodes; a first contact hole formed over the first semiconductor layer to extend through the second insulating layer and reach the first semiconductor layer; a first electrode portion formed in the first contact hole; a first semiconductor region formed on a back surface side of the semiconductor substrate opposite to a side thereof where the first insulating layer is formed and having a second conductivity type opposite to the first conductivity type; and a back-side electrode formed over the back surface of the semiconductor substrate and electrically coupled to the first semiconductor region, wherein, under the pair of gate electrodes, parts of the first insulating layer are present, wherein side surfaces of the pair of gate electrodes opposite to side surfaces thereof facing the first semiconductor layer via the gate insulating films are adjacent to the first insulating layer, wherein, in an upper portion of the first semiconductor layer, a second semiconductor region having the second conductivity type and a third semiconductor region having the first conductivity type and located over the second semiconductor region are formed, wherein a portion of the first semiconductor layer which is located under the second semiconductor region has the first conductivity type, and wherein the first electrode portion is electrically coupled to the second and third semiconductor regions.