Patent ID: 9354893
Filing Date: 2016-05-31
CPC Classification: G06F

Claim Text:
1. An information processing device comprising: a first cache that stores a first instruction code comprising a plurality of specific instruction codes; a second cache that stores data to be processed; first and second arithmetic unit group circuits configured to execute operations on the data by a plurality of arithmetic units configured to operate in parallel; a first arithmetic-control circuit configured to read the first instruction code, and to generate one or more operation instructions for the first arithmetic unit group circuit based on the first instruction code; and a second arithmetic-control circuit configured to include a fixed instruction register fixed in length that stores a second instruction code, comprising one or more specific instruction codes, specified by the first arithmetic unit group circuit, and to generate one or more operation instructions for the second arithmetic unit group circuit based on the second instruction code, wherein the first instruction code at least includes first and second specific instruction codes, when the one or more operation instructions generated by the first arithmetic-control circuit include a first operation instruction on a basis of the first specific instruction code, the first arithmetic unit group circuit is configured to set the second instruction code to the fixed instruction register in accordance with the first operation instruction, and when the one or more operation instructions generated by the first arithmetic-control circuit include a second operation instruction on a basis of the second specific instruction code, the first arithmetic unit group circuit is configured to provide data to be processed by the second arithmetic unit group circuit to the second arithmetic unit group circuit, and the second arithmetic unit group circuit repeatedly executes operations on a basis of the one or more operation instructions generated based on the second instruction code by the second arithmetic-control circuit, wherein the first arithmetic unit group circuit and the second arithmetic unit group circuit have an identical but separate configuration of the plurality of arithmetic units, such that the first arithmetic unit group circuit and the second arithmetic unit group circuit have identical arithmetic units interconnected in the same manner.