Patent ID: 9361152
Filing Date: 2016-06-07
CPC Classification: G06F

Claim Text:
1. An apparatus, comprising: a processor element; an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, execute the hardware transaction in a first hardware phase when a retry counter value is less than a retry threshold value for the first hardware phase, and to execute the hardware transaction in a second hardware phase when the retry counter value is greater than or equal to the retry threshold value for the first hardware phase but less than a retry threshold value for the second hardware phase; a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution; and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes.