Patent ID: 9425177
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: preparing a semiconductor wafer which is partitioned into a plurality of first semiconductor chips, the plurality of first semiconductor chips including a first group of first semiconductor chips and a second group of defective semiconductor chips; positioning a plurality of second semiconductor chips over corresponding ones of the first semiconductor chips of the first group, but not over the defective semiconductor chips such that individual ones of the second semiconductor chips are separated from one another by individual voids over each of the defective semiconductor chips; disposing a sealer on a face of each of the defective semiconductor chips and such that the sealer fills the individual voids over each of the defective semiconductor chips; and grinding a face of the semiconductor wafer after the voids over each of the defective semiconductor chips are filled with the sealer, thereby reducing a variation in load applied to the semiconductor wafer during grinding.