Patent ID: 9299308
Filing Date: 2016-03-29
CPC Classification: G09G,G11C

Claim Text:
1. A shift register circuit comprising: a plurality of cascaded stages including a first start-stage and M stages (M is natural number equal to or greater than 2); a start signal line electrically connected with the first start-stage; a plurality of output signal lines electrically connected with M stages respectively for applying a conducting potential which makes a pixel transistor electrically connecting with the output signal line conductive; a first clock signal line electrically connected with the plurality of cascaded stages and applying a first clock signal; a second clock signal line electrically connected with the plurality of cascaded stages and applying a second clock signal, a third clock signal line electrically connected with the plurality of cascaded stages and applying a third clock signal, wherein the first clock, the second clock and the third clock become the conducting potential in order, wherein M stages and the first start-stage include an output transistor, a first node and a first node setting transistor, wherein the output transistor of M stages has a first electrode which is electrically connected with the output signal line, a second electrode which is electrically connected with the first clock signal line or the third clock signal line, and a gate electrode which is electrically connected with the first node, wherein the first node setting transistor of M stages has a first electrode which is electrically connected with the first node, a second electrode and gate electrode which are electrically connected with the first electrode of the output transistor of a previous stage, wherein the output transistor of the first start-stage has a first electrode which is electrically connected with the second electrode of the first node setting transistor of a first stage of M stages, a second electrode which is electrically connected with the third clock signal line, a gate electrode which is electrically connected with the first node of the first start-stage, and wherein the first node setting transistor of the first start-stage has a first electrode which is electrically connected with the first node of the first start-stage, a second electrode which is electrically connected with the second clock signal line, a gate electrode which is electrically connected with the start signal line.