Patent ID: 9311981
Filing Date: 2016-04-12
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array including nonvolatile memory cells respectively arranged at intersections between word lines and bit lines, each nonvolatile memory cell having a variable resistance element; a conductor line array, corresponding to the memory cell array, and including an array of conductive lines, different than the word lines and bit lines, and establishing current paths and configured to generate a compensation magnetic field with respect to the nonvolatile memory cells of the memory cell array; a current driver configured to supply current to the conductive lines; a magnetic field sensor configured to sense an applied external magnetic field and in response generate external magnetic field information; and a compensation magnetic field controller configured to generate compensation magnetic field information in response to the external magnetic field information, and to control the current driver in accordance with the compensation magnetic field information to supply current to the array of conductive lines to generate the compensation magnetic field to compensate for an influence of the applied external magnetic field upon memory cells in the memory cell array.