Patent ID: 9401217
Filing Date: 2016-07-26
CPC Classification: G11C

Claim Text:
1. A non-volatile memory device comprising: an array of memory cells, wherein each memory cell of the array includes a first supply voltage terminal and a second supply voltage terminal; a plurality of word lines, wherein each memory cell of the array is coupled to a word line of the plurality of word lines; a plurality of voltage supply lines, each voltage supply line of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array, wherein each subset of the plurality of subsets includes a plurality of memory cells; a voltage switch operable to supply a respective one or more of a plurality of aged voltages to each of the plurality of subsets of memory cells in the memory array on respective ones of the plurality of voltage supply lines during at least one of program verify and erase verify operations, wherein the respective one of the aged voltages supplied to a first of the plurality of subsets of memory cells is different than the respective one of the aged voltages supplied to a second of the plurality of subsets of memory cells; and a plurality of differential age values that correspond to numbers of the memory cells that do not pass erase verify, wherein each of the plurality of differential age values corresponds to a different number of the memory cells that do not pass erase verify.