Patent ID: 9425189
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: an SOI substrate comprising an active semiconductor layer disposed on a buried insulating material layer, which is in turn disposed on a base semiconductor material; first and second laterally spaced apart gate structures formed above said active semiconductor layer, each having a gate insulation structure contacting said active semiconductor layer; a first source/drain region positioned adjacent a first side of said first gate structure; a second source/drain region positioned adjacent a first side of said second gate structure; a common source/drain region positioned in said active semiconductor layer between said laterally spaced apart first and second gate structures; a first contact element contacting said first source/drain region; a second contact element contacting said second source/drain region, and a third contact element contacting said common source/drain region, wherein said third contact element further extends through said common source/drain region and said buried insulating material layer and into electrical contact with said base semiconductor material.