Patent ID: 9337190
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A device, comprising: a first active transistor and a second active transistor, wherein the first and second active transistors each have a metal gate with a first type of work function, wherein the metal gate with the first type of work function includes a first material having the first type of work function and a second material disposed over the first material, the second material having a second type of work function; a third active transistor and a fourth active transistor, wherein the third and fourth active transistors each have a metal gate with the second type of work function, wherein the metal gate of the third active transistor is substantially collinear with the metal gate of the first active transistor and the metal gate of the fourth active transistor is substantially collinear with the metal gate of the second active transistor; an isolation gate structure, wherein the isolation gate structure has a first linear uninterrupted sidewall and an opposing second linear uninterrupted sidewall, and wherein the isolation gate structure includes: a first portion of the isolation gate structure interposing the first and second active transistors, wherein the first portion of the isolation gate structure has a metal gate with the second type of work function, wherein the metal gate of the first portion of the isolation gate structure has a layer of the second material disposed directly on a gate dielectric layer, wherein the first portion of the isolation gate structure defines a first portion of the first linear uninterrupted sidewall and a first portion of the opposing second linear uninterrupted sidewall; and a second portion of the isolation gate structure interposing the third and fourth active transistors, wherein the second portion of the isolation gate structure has a metal gate with the first type of work function, wherein the second portion of the isolation gate structure defines a second portion of the first linear uninterrupted sidewall and a second portion of the opposing second linear uninterrupted sidewall and a first active region underlying the first and second active transistors and the first portion of the isolation gate structure; a second active region underlying the third and fourth active transistors and the second portion of the isolation structure; and an isolation region interposing the first and second active regions, wherein a third portion of the isolation gate structure overlies the isolation region, and wherein the third portion of the isolation gate structure defines a third portion of the first linear uninterrupted sidewall and a third portion of the opposing second linear uninterrupted sidewall, the third portions of the sidewalls connecting the first and second portions of the sidewalls.