Patent ID: 9435862
Filing Date: 2016-09-06
CPC Classification: G01R

Claim Text:
1. An integrated circuit, IC, device comprising at least one self-test component arranged to execute self-testing within at least one self-test structure during a self-test execution phase of the IC device, and at least one clock control component arranged to provide at least one clock signal to the at least one self-test component at least during the self-test execution phase of the IC device; wherein the at least one clock control component is further arranged to: receive at least one indication of at least one power dissipation parameter for at least a part of the IC device; and modulate the at least one clock signal provided to the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the IC device, wherein the at least one indication of at least one power dissipation parameter comprises at least one static power dissipation parameter value, and the at least one static power dissipation parameter value is/are configured within at least one register accessible by the at least one clock control component.