Patent ID: 9442797
Filing Date: 2016-09-13
CPC Classification: G06F,G11C

Claim Text:
1. A memory system comprising: a memory device configured to read out normal data from memory cells, and read out sampling data including N units of sampling data from the memory cells by use of a plurality of read voltages, the N units of sampling data being output N times with one unit of sampling data per time, N being a natural number greater than 1; and a controller configured to generate probabilistic information, and update the probabilistic information based on the sampling data input from the memory device, and configured to perform an error correction operation, to correct errors in the normal data, by use of the updated probabilistic information, wherein the controller repeatedly updates the probabilistic information whenever at least one unit of the sampling data is input to the controller, and the controller performs the error correction operation after the N units of sampling data are input from the memory device.