Patent ID: 9502083
Filing Date: 2016-11-22
CPC Classification: G11C,H03K

Claim Text:
1. A device comprising: first and second power terminals; an output terminal; a plurality of first output transistors each including a first gate and first and second nodes, the first node of each of the first output transistors being coupled to the first power terminal and the second node of each of the first output transistors being coupled to the output terminal; a plurality of second output transistors each including a second gate and third and fourth nodes, the third node of each of the second output transistors being coupled to the output terminal and the fourth node of each of the second output transistors being coupled to the second power terminal; a control circuit producing a set of first control signals and a set of second control signals, the first control signals being supplied respectively to the first gates of the first output transistors to render selected one or ones of the first output transistors conductive or to render each of the first output transistors non-conductive, and the second control signals being supplied respectively to the second gates of the second output transistors to render selected one or ones of the second output transistors conductive or to render each of the second output transistors non-conductive; and