Patent ID: 9229862
Filing Date: 2016-01-05
CPC Classification: G06F

Claim Text:
1. A method comprising: including a memory management unit in a processor unit operably coupled to at least one processor; storing in a cache table entries for a number of physical addresses and a number of virtual addresses wherein each of the number of virtual addresses is mapped to only one of a number of corresponding physical addresses residing in a number of different memory devices and the number of different memory devices are of a number of types, wherein each of the number of types is different and each of the number of types has a number of different characteristics, and wherein each entry in the cache table comprises data including a virtual address and a corresponding physical address, a start address, an end address, a memory type, a memory read speed and a memory write speed; identifying, by a hypervisor, a number of memory devices, a number of types of memory devices, and for each of the number of types of memory devices determines the number of different characteristics; and responsive to obtaining a new address, identifying an addressing variant associated with the new address, wherein the addressing variant is one of a virtual address and a physical address, and wherein responsive to the addressing variant is the virtual address, selecting a first process and responsive to the addressing variant is the physical address, selecting a second process.