Patent ID: 9286970
Filing Date: 2016-03-15
CPC Classification: G11C

Claim Text:
1. A memory, comprising: a word line; a bit line and a complementary bit line; a memory cell having a data node coupled to the bit line and a complementary data node coupled to the complementary bit line, wherein the word line controls access to the memory cell; and a circuit coupled to the bit line and the complementary bit line, wherein the circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving, wherein the first timing and the second timing are synchronized by control signals and further wherein the circuit comprises a first PMOS transistor coupled between a high voltage node and the bit line, a second PMOS transistor coupled between the high voltage node and the complementary bit line, a first NMOS transistor coupled between a low voltage node and the bit line, a second NMOS transistor coupled between the low voltage node and the complementary bit line, and wherein the circuit is configured to turn on the first PMOS transistor and the second PMOS transistor for pre-charging.