Patent ID: 9318377
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising a dual damascene metal interconnect structure, the dual damascene metal interconnect structure comprising: a terminal; a first layer overlying the terminal and comprising via openings in a field of a first dielectric, and excluding air gaps, wherein metal vias fill the via openings; a first metal cap layer arranged in a lowermost portion of a via opening, the first metal cap layer having a lower portion making contact with the terminal and having an upper portion making contact with a metal via filling the via opening; and a second layer overlying the first layer and comprising metal bodies filling trenches in a field of a second dielectric, wherein the second dielectric includes air gaps that substantially reduce an effective dielectric constant of the second dielectric; wherein the first and second dielectrics directly abut one another; a second metal cap layer arranged over and abutting the metal bodies filling the trenches and having a metal composition which differs from that of the metal bodies and which differs from that of the first metal cap layer, wherein a lower surface of the second metal cap layer is at a height corresponding to the second dielectric and an upper surface of the second metal cap layer is co-planar with an upper surface of the second dielectric.