Patent ID: 9306547
Filing Date: 2016-04-05
CPC Classification: H03K

Claim Text:
1. A method for adjusting a duty cycle, comprising: generating a duty cycle signal having a voltage representing a duty cycle of a clock signal; generating, using a reference voltage generator, in response to a reference control signal, a reference voltage from voltage sources applied to the reference voltage generator; and comparing, using the comparator, the reference voltage and the duty cycle signal; adjusting, using a clock evaluation control circuit, the reference voltage generated by the adjustable reference voltage generator to match the duty cycle signal to produce a first matched value; inverting supply voltage sources input to the reference voltage generator in response to an applied reference polarity signal; adjusting, using the clock evaluation control circuit, while the supply voltage sources are inverted, the reference voltage to match the duty cycle signal to produce a second matched value; and swapping comparator inputs into the comparator in response to an applied comparator polarity signal; and while the comparator inputs are swapped: