Patent ID: 9499395
Filing Date: 2016-11-22
CPC Classification: B06B,B81B,B81C,G01N,H01L,H04R

Claim Text:
1. An apparatus, comprising: a semiconductor wafer having a complementary metal oxide semiconductor (CMOS) integrated circuit; a conductive membrane bonded with the semiconductor wafer to form a bonded structure such that a sealed cavity exists between a bonding surface of the semiconductor wafer and a first side of the conductive membrane, the conductive membrane having a second side distal from the bonding surface of the semiconductor wafer; and a conductive standoff on the first side of the conductive membrane proximate the bonding surface of the semiconductor wafer such that a surface of the conductive standoff forms an interface between the first side of the conductive membrane and the bonding surface, wherein the conductive standoff connects the conductive membrane to the CMOS integrated circuit, and wherein the bonded structure lacks an electrode that is on the second side of the conductive membrane and that overlies the cavity.