Patent ID: 9431507
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A device, comprising: a gate structure positioned above an upper surface of a semiconductor substrate, said gate structure comprising a high-k gate insulation layer (k value of 10 or greater) and a gate electrode comprised of at least one layer of metal; a lower sidewall spacer positioned adjacent opposite sides of at least a portion of said gate electrode, said lower sidewall spacers having an upper surface that is positioned above said upper surface of said substrate; a gate cap layer positioned above at least said gate electrode; a layer of insulating material positioned above said surface of said substrate and around said gate structure; and a plurality of sidewall spacers positioned laterally between said layer of insulating material and a portion of said gate structure and vertically between said upper surface of said lower sidewall spacer and a bottom surface of said gate cap layer, wherein said plurality of sidewall spacers comprise a low-k spacer comprised of an insulating material having a dielectric constant equal to or less than 3.9.