Patent ID: 9281320
Filing Date: 2016-03-08
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: a gate line disposed on a substrate; a data line crossing the gate line; a transistor electrically connected to the gate line and the data line; a pixel electrode electrically connected to the transistor; a first common electrode insulated from the pixel electrode and disposed between the pixel electrode and the substrate; a second common electrode adjacent to the first common electrode; and a connecting portion electrically connecting the first and second common electrodes to each other, wherein: the data line is disposed between the first and second common electrodes; the connecting portion overlaps with a portion of the data line, and is formed from a same layer as the first and second common electrodes such that the connecting portion consists of the same material as the first common electrode and the second common electrode; and the pixel electrode has at least two slits, and the first common electrode forms a continuous plane between the at least two slits, wherein the connecting portion comprises a first connecting portion connecting a first end of the first common electrode to a first end of the second common electrode, and a second connecting portion connecting a second end of the first common electrode to a second end of the second common electrode, and wherein the first connecting portion is spaced apart from the second connecting portion in a direction substantially parallel with the data line thereby forming an opening overlapping with a portion of the data line.