Patent ID: 9455318
Filing Date: 2016-09-27
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: providing a substrate; forming a well region on the substrate; forming at least one first gate structure on the well region, wherein the first gate structure includes a gate insulating layer and a first gate electrode formed on the gate insulating layer, wherein the first gate electrode is formed having a first enclosed pattern on a surface of the well region; wherein an area inside the first enclosed pattern is defined as a first region, and an area outside the first enclosed pattern is defined as a second region; performing ion implantation on the first region such that the first region has a first conductivity type, performing ion implantation on the second region such that the second region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different, forming a second gate structure on the well region, wherein the second gate structure is spaced apart from the first gate structure, wherein the second gate structure includes the gate insulating layer and a second gate electrode formed on the gate insulating layer, wherein the second gate electrode is formed having a second enclosed pattern on the surface of the well region, and the second enclosed pattern is surrounded by the first region, wherein an area inside the second enclosed pattern is defined as a third region; and performing ion implantation on the third region such that the third region has the second conductivity type.