Patent ID: 9349837
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a semiconductor fin over top surfaces of insulation regions; forming a gate stack on a top surface and sidewalls of a middle portion of the semiconductor fin, wherein the insulation regions comprise first portions overlapped by the gate stack, and second portions misaligned from the gate stack; etching an end portion of the semiconductor fin to form a recess, wherein the recess is located between the second portions of the insulation regions; performing an epitaxy to grow a source/drain region from the recess; after the epitaxy, performing a first recessing to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing; and after the first recessing, forming a dielectric mask layer on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack.