Patent ID: 9419620
Filing Date: 2016-08-16
CPC Classification: H03K,H04N

Claim Text:
1. A device, comprising: a video compression processor communicatively coupled to a direct memory access engine; and an array of programmable objects comprising functional core circuitry configured to execute an application process and party line communication circuitry communicatively coupling the array of programmable objects to the video compression processor and to a memory, the array of programmable objects configured to initiate sending of search window pixel data from the memory to the video compression processor via the party line communication circuitry in response to initiation of an integer search operation of the application process and to initiate sending of the search window pixel data from the memory to the video compression processor via the direct memory access engine in response to initiation of a interpolation operation of the application process, wherein the party line communication circuitry is configured to route the search window pixel data via multiple channels through one or more of the programmable objects at a higher transfer rate relative to the direct memory access engine, the party line communication circuitry transferring at least a portion of the search window pixel data via the multiple channels during a single clock cycle, and wherein the direct memory access engine is configured to route the search widow pixel data via two multi-bit periphery buses that bypass the array of programmable objects, a first of the two multi-bit periphery buses supporting data flow in a first direction and a second of the two multi-bit periphery buses supporting data flow in a second direction.