Patent ID: 9269609
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A device comprising: a semiconductor substrate; a first Metal-Oxide-Semiconductor (MOS) device at a top surface of the semiconductor substrate; a second MOS device at the top surface of the semiconductor substrate; a first trench extending into the semiconductor substrate from the top surface of the semiconductor substrate, the first trench including a first portion, a second portion, and a third portion, wherein: an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate and extending into the first trench, wherein a first air gap is sealed in the first trench by the ILD layer, wherein at least a portion of the first air gap is disposed in the first trench below the top surface of the semiconductor substrate, wherein the semiconductor substrate along a first semiconductor sidewall of the first trench contacts the first air gap, and wherein the first air gap is contiguous through the first portion of the first trench, the second portion of the first trench, and the third portion of the first trench; and a contact plug through the ILD and connected to at least one of the first MOS device and the second MOS device.