Patent ID: 9472665
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A MOS transistor in a semiconductor substrate, the MOS transistor comprising: a source region of a first conductivity type and a drain region of the first conductivity type in the semiconductor substrate; a channel region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate between the source region and the drain region; an isolation region adjacent to the drain region; a drift region of the first conductivity type laterally adjacent to the channel region and beneath the isolation region and the drain region; a gate dielectric layer over the channel region and extending over the drift region; a gate electrode over the gate dielectric layer having a first portion and a second portion, wherein the first portion of the first conductivity type has a uniform or substantially uniform dopant concentration and is over the channel region and further extends over a portion of the drift region and a portion of the isolation region, the second portion is un-doped and over the isolation region, an interface between the first portion and the second portion is directly overlying the isolation region, and the first portion has a width less than a width of the second portion; and a field plate contacting an upper surface of the gate electrode, wherein the field plate comprises polycide.