Patent ID: 9508868
Filing Date: 2016-11-29
CPC Classification: G11C,H01L

Claim Text:
1. A paired non-volatile memory bitcell comprising: a first active region in a substrate, the first active region comprising a first and second source and a first and second drain; a second active region separated from the first active region by a nonconductive region, the second active region comprising one plate of each of a first and second capacitor; a third active region separated from the first and second active regions by a second nonconductive region, the third active region comprising one plate of each of a first and second band to band tunneling (BTBT) capacitor; a first floating gate located above the second active region and forming another plate of the first capacitor, above the third active region forming another plate of the first BTBT capacitor, and above the first active region between the first source and the first drain; and a second floating gate located above the second active region and forming another plate of the second capacitor, above the third active region forming another plate of the second BTBT capacitor, and above the first active region between the second source and the second drain; wherein the first and second sources of the first active region each comprise at least one of a source-drain extension implant and a lightly doped drain (LDD) implant, and wherein the first and second sources each comprise a halo implant and the first and second drains do not comprise a halo implant.