Patent ID: 9478736
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A memory array device comprising: memory cells; a plurality of memory cell pillars, each memory cell pillar including: a plurality of gate conductors configured along a first axis in parallel, wherein each FET of the memory cells is adjacent to two gate conductors; a gate oxide continuously extending along an array column of the memory array device and in contact with the straight sides of the memory cell pillar for each of the memory cells; a dielectric row filler layer extending along sides of the memory cell pillars and in contact with the FET channel and the memory element of each memory cell pillar; and a plurality of bit lines configured along a second axis in parallel, wherein each bit line is electrically coupled to a plurality of memory elements of the memory cells along the second axis, the second axis being perpendicular to the first axis.