Patent ID: 9420209
Filing Date: 2016-08-16
CPC Classification: H01L,H04N

Claim Text:
1. A pixel array generating system, comprising: a layout file storage medium configured to store a plurality of layouts for a pixel array of an image sensor; a layout generator configured to select a layout from among the plurality of layouts and generate a final layout by one of reading the selected layout from the layout file storage medium and generating a new layout based on the selected layout; and a semiconductor processing apparatus configured to manufacture the pixel array of the image sensor based on the generated final layout, wherein the plurality of layouts includes a layout of a first unit pixel that includes a layout of a plurality of first transistors and a shallow trench isolation (STI), the STI being formed between a first p-well region and a first deep trench isolation (DTI) area, the first p-well region being below a gate of a first drive transistor from among the plurality of first transistors, wherein the plurality of layouts includes a layout of a second unit pixel that includes a layout of a plurality of second transistors and a second DTI area, the second DTI area being formed adjacent to a second p-well region, the second p-well region being below a gate of a second drive transistor from among the plurality of second transistors, and wherein the layout generator is further configured to generate one of the layout of the first unit pixel and the layout of the second unit pixel as the final layout based on desired performance characteristics of the image sensor.