Patent ID: 9240242
Filing Date: 2016-01-19
CPC Classification: G11C

Claim Text:
1. A method for operating a low-cost electrically erasable programmable read only memory array, wherein said low-cost electrically erasable programmable read only memory (EEPROM) array comprises a plurality of parallel bit lines; a plurality of parallel word lines; a plurality of parallel common source lines; and a plurality of sub-memory arrays, and wherein said bit lines are divided into a plurality of bit line groups including a first bit line group, and wherein said word lines are vertical to said bit lines and include a first word line and a second word line, and wherein said common source lines are parallel to said word lines and include a first common source line, and wherein each said sub-memory array is connected with one said bit line group, two said word lines and one said common source line, and wherein each said sub-memory array includes a first memory cell and a second memory cell, and wherein said first memory cell is connected with said first bit line group, said first common source line and said first word line, and wherein said second memory cell is connected with said first bit line group, said first common source line and said second word line, and wherein said first memory cell and said second memory cell are symmetrically arranged at two sides of said first common source line, and wherein each of said first memory cell and said second memory cell has an N-type field-effect transistor (FET) built in a P-type substrate or a P-type well, and wherein each of said first memory cell and said second memory cell is an operation memory cell, and wherein in operating all said operation memory cells, said method is characterized in that a substrate voltage V that a bit voltage V that in writing, following conditions must be satisfied: that in erasing, following conditions must be satisfied: