Patent ID: 9406366
Filing Date: 2016-08-02
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: a memory cell; a reference cell; a first current source configured to cause a first current to flow through the memory cell; a second current source configured to cause a second current having an amount thereof being variable to flow through the reference cell; a sense amplifier configured to compare a voltage responsive to a voltage drop across the memory cell with a voltage responsive to a voltage drop across the reference cell; and a current-amount setting circuit configured to determine the amount of the second current, wherein the current-amount setting circuit determines the amount of the second current such that the voltage drop across the reference cell is set equal to a midpoint between the voltage drop across the memory cell having a data value of “0” stored therein and the voltage drop across the memory cell having a data value of “1” stored therein, and wherein the second current source includes a plurality of MOS transistors connected in parallel to each other and each series-connected to the reference cell, wherein the amount of the second current is determined in response to a number of one or more MOS transistors that are placed in a conductive state among the plurality of MOS transistors.