Patent ID: 9459866
Filing Date: 2016-10-04
CPC Classification: G06F,H03M

Claim Text:
1. A method of performing an instruction in a computer processor, comprising: fetching the instruction that includes a source operand and a destination operand, wherein the source operand specifies a single source vector register that includes a plurality of source data elements including one or more runs of identical data elements, wherein the destination operand identifies a destination vector register and wherein each of the one or more runs of identical values that are to be compressed in the destination vector register as a value and run length pair; decoding the fetched instruction; and executing the decoded instruction causing, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value wherein one or more runs of one or more source data elements equal to a compression value are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.