Patent ID: 9391196
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A high-voltage metal-oxide-semiconductor (HV MOS) transistor device, comprising: a semiconductor substrate; a gate structure disposed on the semiconductor substrate, wherein the semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure; a first isolation structure disposed in the first region of the semiconductor substrate; a first sub-gate structure disposed on the semiconductor substrate, wherein the first sub-gate structure is separated from the gate structure, and the first sub-gate structure is disposed on the first isolation structure in the first region of the semiconductor substrate; and a drain region disposed in the first region of the semiconductor substrate, wherein the drain region is electrically connected to the first sub-gate structure via a first contact structure disposed on the drain region and the first sub-gate structure, and at least a part of the first isolation structure is disposed between the drain region and the first sub-gate structure.