Patent ID: 9245629
Filing Date: 2016-01-26
CPC Classification: G11C,H01L

Claim Text:
1. A method of operating a re-programmable non-volatile memory system, comprising: utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having x, y and z-directions and which comprises: a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate; a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction, wherein said plurality of first conductive lines is partitioned into a first set of first conductive lines acting as local bit lines and into a second set of first conductive lines; a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of first conductive lines in the individual planes, wherein said plurality of second conductive lines act as word lines and the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes; a plurality of non-volatile re-programmable memory elements individually connected between the first set of first conductive lines and second conductive lines adjacent the crossings thereof at a first set of the plurality of locations; a plurality of connectors individually connected between the second set of first conductive lines and second conductive lines adjacent the crossings thereof at a second set of the plurality of locations; a plurality of third conductive lines partitioned into first and second groups of third conductive lines; and a first group of select devices arranged to switch a selected row of first conductive lines in the x-direction to the first set of third conductive lines; and a second group of select devices arranged to switch a selected set of the plurality of second conductive lines to respective second set of third conductive lines; and wherein the select devices each has a source terminal and a drain terminal that are aligned with the two-dimensional array of first conductive lines in the x-y plane; and wherein the source and drain terminals of each select device are aligned diagonally in the x-y plane; selecting one or more of the plurality of memory elements by applying select control signals to the first and second groups of select devices in order to connect selected row of the first set of first conductive lines to individual ones of the first set of third conductive lines and to connect selected second conductive lines, via the second set of first conductive lines, to individual ones of the second set of third conductive lines; and causing the selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying either a first or a second electrical stimulus through the individual ones of the first and second sets of third conductive lines between which the selected one or more of the plurality of memory elements are operably connected.