Patent ID: 9461031
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A transient voltage suppressing (TVS) array comprising: a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate to separate a plurality of semiconductor regions insulated by the isolation trenches and a body region having a second conductivity type in an upper part of said epitaxial layer with the body region extends laterally over an entire length of the semiconductor regions between two of the isolation trenches; a plurality of doped regions of said first conductivity type in each of the semiconductor regions including a top doped region of the first conductivity type disposed under a top surface of the substrate encompassed in the body region and extends laterally over substantially an entire length of the first semiconductor region to constitute a bipolar transistor comprising vertically stacked PN junctions disposed between two of the isolation trenches for triggering the bipol transistor by a Zener diode comprising a bottom vertically stacked PN junction between the body region and the epitaxial layer for carrying a transient current for suppressing a transient voltage; and a top metal layer in contact with the doped region of the first conductivity type disposed on top of the bipolar transistor constituting a cathode electrode and a bottom metal layer disposed on a bottom surface of the semiconductor substrate constituting an anode electrode.