Patent ID: 9383418
Filing Date: 2016-07-05
CPC Classification: G01R,H01L

Claim Text:
1. A method of forming an Integrated Dual Axis Fluxgate Sensor, comprising: providing a processed semiconductor wafer that has been chemical mechanical polished (CMP'd) and has an etch stop first SiN layer deposited on the surface; depositing and defining a first TetraEthyl OrthoSilicate (TEOS) layer to define a form for a bottom layer of a coil; depositing a Ti/Cu seed layer on the first TEOS layer, wherein a first copper conductor layer is then electroplated on the top surface of the seed layer; chemical mechanical planarization (CMP) polishing the top surface of the wafer to remove the excess copper not filling the form, known as a damascene process; depositing a second SiN layer and then a second TEOS layer, in sequence, on the top surface of the first TEOS layer and the top surface of the copper bottom layer of the coil; depositing a third SiN layer on the top surface of the second TEOS layer and finally a titanium layer on the top surface of the third SiN layer; depositing a laminated magnetic core structure selected from a group of a first magnetic lamination method or a second magnetic lamination method; depositing and patterning photoresist and then etching the magnetic core structure of alternating layers of NiFe and AIN dielectric layers stopping on the titanium layer and then etching the titanium layer exposed by the magnetic core etch; depositing a third TEOS layer the top surface of the magnetic core stack structure and the top surface of the third SiN layer, wherein the third TEOS layer is configure to included a plurality of openings terminating on the bottom layer of the coil; electroplating a second layer of copper to form copper vias through the openings in the third TEOS layer, wherein the copper vias couple with the bottom layer of the coil; CMP polishing the top surface of the wafer to remove the excess copper not filling the openings in the third TEOS layer, known as a damascene process; depositing and defining a fourth TEOS layer to define a form for a top layer of the coil; electroplating a third copper layer over the fourth TEOS layer, CMP polishing the top surface of the wafer to remove the excess copper not filling the openings in the fourth TEOS layer, known as a damascene process, wherein the third copper layer connects to the vias thereby coupling the top layer of the coil to the bottom layer of the coil; and depositing passivation layers touching the top surface of the fourth TEOS layer and the top surface of the top layer of coil, wherein openings are included in the passivation layers to contact the top copper layer.