Patent ID: 9391639
Filing Date: 2016-07-12
CPC Classification: H03M

Claim Text:
1. An apparatus, comprising: a high throughput LDPC decoder configured to process no less than a first number of codeword bits in a single time unit, where the first number is equal to the product of n and y, further where n and y are natural numbers; a low throughput LDPC decoder configured to process no more than a second number of codeword bits in the single time unit, where the second number is equal to y, such that the low throughput LDPC decoder processes 1/n as many codeword bits in the single time unit as compared to the high throughput LDPC decoder; first logic configured to enable decoding of codeword bits by either the high throughput LDPC decoder or the low throughput LDPC decoder based on selection criteria.