Patent ID: 9306054
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming a plurality of first gate electrode structures on a substrate; forming a first recess in the substrate, wherein the first recess is formed between two adjacent first gate electrode structures of the plurality of first gate electrode structure; forming a diffusion prevention layer, comprising a first material, on the first recess of the substrate, wherein the diffusion prevention layer is conformally formed on a bottom surface and sidewall surfaces of the first recess of the substrate; forming a first pre-silicide layer, comprising a second material different from the first material, on the diffusion prevention layer; forming a metal layer on the first pre-silicide layer; and forming a first silicide layer by performing an annealing process on the substrate, wherein metal atoms of the metal layer are diffused to the first pre-silicide layer in the annealing process and the diffusion prevention layer prevents the metal atoms from diffusing to the substrate, and the first silicide layer comprises a monocrystalline layer, and wherein the annealing process comprises a first annealing process and a second annealing process, wherein the first annealing is performed at a first temperature and the second annealing is performed at a second temperature higher than the first temperature.