Patent ID: 9436432
Filing Date: 2016-09-06
CPC Classification: G06F,G11C

Claim Text:
1. A first-in first-out (FIFO) memory providing multi-port functionality, the FIFO memory comprising: a plurality of single-port memory structures, each single port memory structure having a plurality of addresses to read and write data thereto; an indexing block configured to store, for each data write operation, a unique memory identifier corresponding to a single-port memory structure in which the data write operation is performed; and an access controller configured to control operations in the single-port memory structures based on contents of the indexing block, wherein the access controller is configured to perform a plurality of write operations to the plurality of single-port memory structures in a single clock cycle, and wherein the access controller is further configured to continue at least one write operation of the plurality of write operations in the single clock cycle to a write address of a different single port memory structure of the plurality of single-port memory structures during the single clock cycle whenever there is a read and write operation request at a same time on one of the plurality of single-port memory structures.