Patent ID: 9357632
Filing Date: 2016-05-31
CPC Classification: H05K

Claim Text:
1. An apparatus for reducing interference between clock signals, the apparatus comprising: a circuit board; a first set of clock vias that transmit a first clock signal and are coupled to the circuit board; a second set of clock vias that transmit a second clock signal that cycles at a frequency that is different from a frequency of the first clock signal, wherein the second set of clock vias are coupled to the circuit board in a linear pattern adjacent to the first set of clock vias; at least one ground via coupled to the circuit board in line with the second set of clock vias, wherein a total number of ground vias coupled to the circuit board is less than a total number of clock vias coupled to the circuit board; wherein each ground via coupled to the circuit board, including the at least one ground via, is positioned outside any region of the circuit board located between the first and second sets of clock vias.