Patent ID: 9501308
Filing Date: 2016-11-22
CPC Classification: G06F

Claim Text:
1. A method for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system, said computer system including a processor; and a hypervisor managing functions associated with the hardware I/O adapter; said method comprising: providing the I/O adapter with a coherent accelerator including an interface services layer providing Partitionable Endpoint (PE) functions and multiple accelerator function units (AFUs); enabling each AFU to operate independently of the other AFUs to perform a computing task; enabling each AFU to access system memory bound to an application and to make one or more copies of said system memory bound to the application within the AFU; enabling each AFU to maintain synchronization between AFU memory-cache and processor memory-cache; providing a Peripheral Component Interconnect Express (PCIE) host bridge (PHB) for coherent accelerator PE (Partitionable Endpoint) support, said PCIE host bridge (PHB) interconnecting said AFU and a processor and memory; and providing an adapter PE, AFU PE and isolation facilities included in said PCIE host bridge (PHB).