Patent ID: 9252123
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a multi-chip package, the method comprising: providing a package substrate including a plurality of substrate pads disposed on an upper surface of the package substrate, the substrate pads including at least a ground pad and at least a signal pad; stacking a first semiconductor chip on the package substrate, the first semiconductor chip including at least a first bonding pad disposed on an upper surface of the first semiconductor chip; stacking at least a second semiconductor chip on the first semiconductor chip such that the first bonding pad remains exposed, the second semiconductor chip including at least a second bonding pad disposed on an upper surface of the second semiconductor chip; forming a first stud bump on an upper surface of the first bonding pad; forming a first conductive wire to extend from a first ground pad of the plurality of substrate pads to an upper surface of the first stud bump; forming a first nail head bonding bump on the first stud bump and first conductive wire; and after the first semiconductor chip has been electrically connected to the first ground pad: forming a second stud bump on an upper surface of the second bonding pad; forming a second conductive wire extending from an upper surface of the first nail head bonding bump to the second stud bump; and testing an electrical connectivity of the first semiconductor chip, wherein the step of testing is perform after forming the first conductive wire and before forming the second stud bump.