Patent ID: 9490364
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A transistor comprising: a silicon layer disposed directly on a monocrystalline substrate, the silicon layer having a first lattice constant; a silicon channel region disposed in said silicon layer; a gate dielectric layer over the silicon channel region, wherein the gate dielectric layer includes an oxide and a nitride and is formed to a thickness of between 5 Angstroms and 30 Angstroms; a gate electrode on the gate dielectric layer; a pair of spacers on opposing sides of the gate electrode; and source and drain regions on opposite sides of the silicon channel region and above a portion of said silicon layer, the source and drain regions each having a first portion comprising a boron doped portion of said silicon layer and a second portion above the first portion, the second portion comprising a boron doped epitaxial silicon germanium layer having a second lattice constant that is different than the first lattice constant of the silicon layer, wherein: