Patent ID: 9389637
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. A communication circuit comprising: a data node to convey a series of data symbols; a reference voltage node to convey a reference voltage; a timing-reference node to convey an intermittent timing-reference signal concomitant and synchronized with the data symbols; an amplifier coupled to the timing-reference node and the reference voltage node to perform a comparison between the intermittent timing-reference signal and the reference voltage, and to provide a recovered timing-reference signal responsive to the comparison; a sampler coupled to the data node and the amplifier, the sampler to sample the data symbols timed to the recovered timing-reference signal; and an offset control circuit to offset the comparison during a time in which the intermittent timing-reference signal is absent, the offset control circuit including a selectable impedance between the reference voltage node and a DC voltage node, wherein the offset control circuit selects the selectable impedance to offset the reference voltage.