Patent ID: 9287880
Filing Date: 2016-03-15
CPC Classification: H03K,H03L

Claim Text:
1. A circuit, comprising: an input to receive an input clock signal; an output to output an output clock signal, wherein at least a portion of the circuit is clocked by the output clock signal; an amplifier to generate an adjusted input clock signal based on the input clock signal, wherein a gain of the amplifier is changed based on power mode information associated with the portion of the circuit that is clocked by the output clock signal; and a variable injection-strength injection-locked oscillator (ILO), wherein the variable injection-strength ILO generates the output clock signal based on the adjusted input clock signal, and wherein the output clock signal pauses synchronously with respect to the input clock signal when the gain of the amplifier is sufficiently high and the input clock signal pauses.