Patent ID: 9331585
Filing Date: 2016-05-03
CPC Classification: H02M,Y02B

Claim Text:
1. A power control apparatus with dynamical adjustment of driving capability for converting an input power with an input voltage into an output power with an output voltage supplied to an external load, comprising: a switch transistor being an N type switching element comprising an N-channel Metal-Oxide Semiconductor (NMOS) or an NPN bipolar transistor: a pulsed width modulation (PWM) driving controller connected to the switch transistor, performing a adjustment operation and generating a PWM driving signal for controlling the switch transistor to turn on; an output diode; an output capacitor parallel connected to the output diode; a transformer comprising a first side coil and a second side coil, wherein the first side coil is connected to the input power and further connected to the switch transistor in series, the switch transistor controls the current of the first side coil, the second side coil is connected to the output diode to supply the output power to the load; and an isolation element connected to one end of the load so as to convert the output power into a feedback signal transferred back to the PWM driving controller, wherein the adjustment operation performed by the PWM driving controller comprising steps of; during a first rising period, increasing a driving voltage of the PWM driving signal from zero voltage to a first voltage for beginning to turn on the switch transistor such that a drain-source voltage (Vds) of the switch transistor is lowered; during a second rising period, increasing the driving voltage from the first voltage to a second voltage or more than the second voltage which is larger than the first voltage, for beginning to turn on the switch transistor such that a drain-source voltage (Vds) of the switch transistor is lowered; sustaining the driving voltage for a preset period; lowering the driving voltage from the second voltage or more than the second voltage to the first voltage during a first falling period; and lowering the driving voltage from the first voltage to zero voltage during a second falling period, wherein the first voltage is about Miller plateau for the switch transistor, the Miller plateau is referred to a specific constant gate-source voltage (Vgs) lasting for a period of time when the switch transistor shifts from a turn-off state to a turn-on state or from the turn-on state to the turn-off state, the first rising period is prolonged as much as possible to minimize electromagnetic interference, and the second rising period, the first falling period and the second falling period are shortened as much as possible to reduce switching loss.