Patent ID: 9431096
Filing Date: 2016-08-30
CPC Classification: G11C

Claim Text:
1. A memory device having a plurality of banks, each bank comprising a plurality of memory cells, each of which being interconnected via a local write bit-line and a complementary local write bit-line to a respective local write bit-line buffer circuit, wherein said local write bit-line buffer circuit is connected via a global write bit-line and a complementary global write bit-line to a negative bias write assist circuit, the memory device also comprising: an address decoder separately connected to each of said respective local write bit-line buffer circuits by a plurality of respective local write enable signal lines, said address decoder comprising a generating unit for enabling exactly one local write enable signal for a respective one of said local write bit-line buffer circuits when a write address vector specifies a write operation to one of memory cells in a corresponding one of said banks, wherein said local write bit-line buffer circuit is adapted for generating local write data on said local write bit-line and said complementary local write bit-line in response to receiving global write data on said global write bit-line and said complementary global write bit-line when its local write enable signal is enabled.