Patent ID: 9229720
Filing Date: 2016-01-05
CPC Classification: G06F

Claim Text:
1. A test apparatus to perform circuit marginality validation test in an integrated circuit, comprising: a front end unit to bind a micro-operation of a first micro-operation flow generated by a decoder that is dispatchable on more than one of a plurality of ports, to one of the plurality of ports using alias bits of the micro-operation to over-load the micro-operation to specify the one of the plurality of ports and to create a second micro-operation flow from the first micro-operation flow by inserting a floating point data exchange micro-operation in the first micro-operation flow, an out-of-order cluster coupled to the front end unit, wherein the out-of-order cluster is to receive the second micro-operation flow and to dispatch the micro-operation of the second micro-operation flow on the one of the plurality of ports specified by the alias bits, and an execution cluster coupled to the out-of-order cluster, wherein the execution cluster is to generate fault information of the circuit marginality validation test while the integrated circuit is in a localized functional test mode in response to executing the micro-operation of the second micro-operation flow, wherein the front end unit further comprises a decode queue that includes a first port binding and bubble logic to bind the micro-operation to the one of the plurality of ports based on the alias bits including an address alias bit and a data alias bit of the micro-operation to encode an identifier of the one of the plurality of ports, wherein the front end unit further comprises a localized functional test logic to generate a localized functional test mode signal to enable the integrated circuit to be placed in the localized functional test mode.