Patent ID: 9236054
Filing Date: 2016-01-12
CPC Classification: G10L

Claim Text:
1. An apparatus comprising: a decoder to decode first and second sets of data blocks; a processor to process the first and second sets of decoded data blocks; a storage area to store the first and second sets of processed data blocks; and a controller to control a rate at which data blocks are to be decoded by the decoder to reduce a time gap between outputting adjacent ones of the data blocks from the first and second sets in the storage area, wherein the controller is to generate a first interrupt signal between decoding of the first and second sets of data blocks, and to generate a second interrupt signal during decoding of the second set of data blocks, wherein the second interrupt signal is to be applied at a time to reduce the time gap between outputting adjacent ones of the data blocks from the first and second sets in the storage area.