Patent ID: 9419145
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: an insulating layer; a first oxide layer on and in direct contact with the insulating layer; a second oxide layer over the first oxide layer; an oxide semiconductor layer sandwiched by the first and the second oxide layers and in direct contact with each of the first and the second oxide layers; a first and a second electrodes on and in direct contact with the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode over the gate insulating layer; wherein the insulating layer includes a projecting portion, wherein a top surface of the projecting portion is positioned inside an outline of the oxide semiconductor layer when seen in a plan view, wherein the gate electrode and the gate insulating layer overlap with a region of the oxide semiconductor layer between the first electrode and the second electrode when seen in the plan view, wherein each of the oxide semiconductor layer, and the first and the second oxide layers comprises indium, gallium, and zinc, wherein, in the first oxide layer and the second oxide layer, proportions of gallium and zinc are higher than proportions of indium, and wherein the oxide semiconductor layer has a higher proportion of indium than the first oxide layer and the second oxide layer.