Patent ID: 9331065
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor region of a first conductivity type; a trench extending from a first major surface of the semiconductor region; a first dielectric layer at least along lower sidewall surfaces of the trench, but not along upper sidewall surfaces of the trench; a first conductive layer disposed on at least a portion of upper sidewall surfaces of the trench; a second conductive layer disposed in the trench overlying at least portions of the first dielectric layer; a gate dielectric layer overlying the first major surface; a third conductive layer overlying the gate dielectric layer; a first doped region of a second conductivity type adjacent the trench and spaced apart from the major surface, wherein: the first conductive layer is configured as a first electrode of a Schottky diode structure, and wherein at least a portion of the semiconductor region adjacent the first conductive layer is configured as a second electrode of the Schottky diode structure; the semiconductor region, the gate dielectric layer, and the third conductive layer are configured as a first MOS structure; and the first doped region and the semiconductor region are configured as a first diode structure; and a second doped region of the second conductivity type disposed in the semiconductor region adjoining corner regions defined by the first major surface and the upper sidewall surfaces, wherein the second doped region and the semiconductor region are configured as a second diode structure.