Patent ID: 9312853
Filing Date: 2016-04-12
CPC Classification: H03K,H04B

Claim Text:
1. A high-frequency semiconductor switch circuit comprising: one common input/output terminal, two or more separate input/output terminals, and two or more control terminals corresponding to the separate input/output terminals; two or more path switching FET blocks, one block being provided between the common input/output terminal and each of the two or more separate input/output terminals; one or more shunt FET blocks, one block being provided between the ground and each of at least one of the two or more separate input/output terminals; a direct-current blocking capacitor provided at both ends of each of the two or more path switching FET blocks; a direct-current blocking capacitor provided at both ends of each of the one or more shunt FET blocks; and a source bias resistor provided for each of the two or more path switching FET blocks and for each of the one or more shunt FET blocks, wherein a control voltage input to each of the two or more control terminals is applied to the gate of a corresponding one of the two or more path switching FET blocks so that at least one of high-frequency signal paths between the common input/output terminal and the respective separate input/output terminals is caused to be in the conducting state while the other high-frequency signal paths are caused to be in the non-conducting state, a control voltage which is an inverted version of a voltage input to each of the two or more control terminals is applied to the gate of a corresponding one of the one or more shunt FET blocks, a control voltage which has an inverted polarity and a smaller absolute value compared to a voltage input to each of the two or more control terminals, is applied to the source or drain of a corresponding one of the two or more path switching FET blocks, and a control voltage which has a non-inverted polarity and a smaller absolute value compared to a voltage input to each of the two or more control terminals, is applied to the source or drain of a corresponding one of the one or more shunt FET blocks.