Patent ID: 9419794
Filing Date: 2016-08-16
CPC Classification: G06F,G09C,H04L

Claim Text:
1. An integrated circuit comprising: a processor; a security circuit coupled to the processor, wherein the security circuit comprises an encryption circuit that is configured to generate a first key using a first local key and to encrypt the first key using a second local key to generate a second key, and wherein the encryption circuit is configured to generate the first local key and the second local key during initialization of the security circuit, wherein the security circuit is configured to provide the second key to the processor in response to a read by the processor, wherein the security circuit comprises a first software-accessible register, and wherein the security circuit is configured to write the second key to the first software-accessible register to provide the second key in response to the read by the processor, and wherein the processor is configured to generate a read operation to the first software-accessible register to receive the second key from the security circuit; and a first encryption peripheral external to the security circuit, wherein the first encryption peripheral is coupled to the security circuit and is configured to receive the second local key from the security circuit via hardware transmission from the security circuit, wherein the second local key is stored in one or more registers of the security circuit that are not software accessible, and wherein the first encryption peripheral is coupled to the processor and is configured to receive the second key from the processor, and wherein the first encryption peripheral is configured to decrypt the second key responsive to the second local key, and wherein the first encryption peripheral is configured to use the first key resulting from decrypting the second key for encryption operations, wherein the first encryption peripheral includes a second software-accessible register, and wherein the processor is configured to generate a write operation subsequent to reading the second key from the security circuit, the write operation writing the second key to the second software-accessible register, wherein the security circuit is configured to receive an instance-specific value and is configured to generate the first local key responsive to the instance specific value and at least one instance-invariant value.