Patent ID: 9471319
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A method of managing a plurality of threads on a multi-threading processing core, comprising: providing an instruction count threshold condition that determines how many countable instructions of a thread the multi-threading processing core will execute before context switching to another one of the plurality of threads; processing a first plurality of instructions for a first one of the plurality of threads on the multi-threading processing core; determining, for each of the first plurality of instructions, whether the instruction is a countable instruction such that execution of the instruction influences context switching for the multi-threading processing core, wherein at least one of the first plurality of instructions is not a countable instruction such that execution of the at least one instruction does not influence context switching for the multi-threading processing core; determining a plurality of instruction tiers, each corresponding to a respective one or more different types of instructions and each having a respective cost value; for each of the first plurality of instructions executed on the processing core for the thread, determining which one of the plurality of instruction tiers the respective instruction corresponds to, according to a type of the instruction; maintaining, for each of the plurality of instruction tiers, a respective count of the countable instructions that have been executed; and upon determining that the instruction count threshold condition is satisfied, based on the maintained counts, switching the multi-threading processing core to process a second plurality of instructions for a second one of the plurality of threads.