Patent ID: 9348750
Filing Date: 2016-05-24
CPC Classification: G06F

Claim Text:
1. A circuit for realigning data received at a receiver, the circuit comprising: a plurality of memory arrays, each memory array having a predetermined data width; a plurality of multiplexers responsive to selection signals associated with a shift value, wherein each multiplexer is coupled to select an address comprising a current address or a previous address for data to be output by a memory array of the plurality of memory arrays based upon the shift value indicating data of the previous address which is to be simultaneously output with data of the current address; an output multiplexer coupled to select an order of the outputs of the plurality of memory arrays as a single output word based upon the selected addresses, wherein the outputs of the plurality of memory arrays are provided in an order based upon the shift value; and a memory control circuit coupled to the plurality of multiplexers and the output multiplexer, the memory control circuit coupling select signals to the plurality of multiplexers and the output multiplexer to enable generating realigned data comprising the outputs of the predetermined data width from each memory array of the plurality of memory arrays.