Patent ID: 9349421
Filing Date: 2016-05-24
CPC Classification: G06F,G11C

Claim Text:
1. A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the data path interface according to a first clock signal and wherein the PDUs apply delays to the received data; align blocks; and a clock alignment logic, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal, wherein the clock alignment logic determines relative edge positions of the first clock signal and the second clock signal along a time axis, wherein the selected certain ones of the delayed data are selected as a function of the determined edge positions, wherein a cycle of the first clock signal is partitioned into predefined regions along the time axis, and wherein an amount of delay of the selected certain ones of the delayed data is a function of where a rising edge of the second clock signal falls within the predefined regions along the time axis.