Patent ID: 9466366
Filing Date: 2016-10-11
CPC Classification: G11C

Claim Text:
1. A resistive memory cell, comprising: a first bit line switch, having a first terminal receiving a bit line signal, and controlled by a bit line selecting signal to be turned on or off; a first resistor, having a first terminal coupled to a second terminal of the first bit line switch; a first word line switch, connected between a second terminal of the first resistor and a source line in series, and controlled by a word line signal to be turned on or off; a second bit line switch, having a first terminal receiving the bit line signal, and controlled by the bit line selecting signal to be turned on or off; a second resistor, having a first terminal coupled to a second terminal of the second bit line switch; and a second word line switch, connected between a second terminal of the second resistor and the source line in series, and controlled by the word line signal to be turned on or off, wherein when the resistive memory cell is programmed, resistances of the first and second resistors are simultaneously programmed to a high impedance or simultaneously programmed to a low impedance.