Patent ID: 9455234
Filing Date: 2016-09-27
CPC Classification: B23K,H01L,Y10T

Claim Text:
1. A method of joining a chip on a laminate, comprising: positioning a laminate having a top surface, a bottom surface and sides on a surface of a first plate of a fixture and directly abutting against at least two surfaces of a stepped feature; positioning a second plate of the fixture on the top surface of the laminate; mating the first plate and the second plate together; placing a chip on the laminate; and reflowing solder to connect the chip on the laminate, wherein when the first plate and the second plate are mated and the laminate is directly abutting the at least two surfaces of the stepped feature, the laminate is constrained in X, Y, and Z directions during assembly processes, wherein the stepped feature is provided on both the first plate and the second plate, and the second plate has a U-shaped stepped portion on the first plate in a plan view, and wherein a coefficient of thermal expansion (CTE) of the fixture is such that the fixture expands less than the laminate to prevent expansion of the laminate.