Patent ID: 9337350
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method of fabrication of a transistor, comprising: preparing a stack of layers provided with at least one substrate overlaid by an insulating layer and by an active layer, a first portion of the active layer being configured to form a channel for the transistor, and a second portion of the active layer and a third portion of the active layer being separated from each other and from the first portion; and preparing a source and a drain, wherein said preparing comprises: wherein the source and the drain do not extend over an upper face of the first portion of the active layer, the second portion of the active layer, and the third portion of the active layer, and wherein the source contacts at least two first side surfaces and at least two first bottom surfaces of the active layer, and the drain contacts at least two second side surfaces and at least two second bottom surfaces of the active layer.