Patent ID: 9362306
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method of fabricating a three-dimensional semiconductor device, comprising: alternatingly and repeatedly stacking interlayered insulating layers and sacrificial layers on top of each other on a substrate with a cell region and a connection region; forming a channel hole and dummy hole through the interlayered insulating layers and the sacrificial layers, the channel hole exposing a part of the cell region of the substrate, the dummy hole exposing a part of the connection region of the substrate, the channel hole and the dummy hole being spaced apart from each other; forming first and second semiconductor patterns, the first semiconductor pattern filling a lower portion of the channel hole, the second semiconductor pattern filling a lower portion of the dummy hole; forming a gate dielectric layer in the channel and dummy holes; and forming a first gate dielectric pattern in the channel hole and a second gate dielectric pattern in the dummy hole by anisotropically etching the gate dielectric layer, the first gate dielectric pattern having a spacer shape that covers a sidewall of the channel hole, the first gate dielectric pattern partially exposing a top surface of the first semiconductor pattern in the channel hole, and the second gate dielectric pattern covering a sidewall of the dummy hole and a whole top surface of the second semiconductor pattern in the dummy hole.