Patent ID: 9275986
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A transistor, comprising: a stack of at least one semiconductor layer and a plurality of metal layers, at least one gate region between at least one drain region and at least one source region, wherein a ratio between a width of the gate region and a length of the gate region exceeds 300, wherein the at least one drain region and the at least one source region are formed in the at least one semiconductor layer, and wherein a plurality of interconnected drain contact regions and a plurality of interconnected source contact regions are formed in the plurality of metal layers, wherein the at least one drain region is connected to a drain contact pad via an array of vertically stacked drain contact regions, wherein a first drain contact region is formed in a first metal layer and wherein a second drain contact region is formed in a second metal layer, and wherein the at least one source region is connected to a source contact pad via an array of vertically stacked source metal regions, wherein a first source metal region is formed in the first metal layer and wherein a second source metal region is formed in the second metal layer.