Patent ID: 9336872
Filing Date: 2016-05-10
CPC Classification: G06F,G09C,G11C,H01L,H04L

Claim Text:
1. A storage element comprising: a first column of restive elements; a second column of restive elements, the second column having a same number of resistive elements as the first column of restive elements; a bridge top coupled to a top restive element of the first column and a top restive element of the second column, the bridge top configured to receive a first bias voltage from a read bias component; a bridge bottom coupled to a bottom restive element of the first column and a bottom restive element of the second column, the bridge bottom configured to receive a second bias voltage from the read bias component; a first out path coupled to the first column; a second out path coupled to the second column; a first drive path and a second drive path associated with the first column of restive elements, the first drive path configured to receive a first drive voltage from a write driver and the second drive path configured to receive a second drive voltage from the write driver; and a third drive path and a fourth drive path associated with the second column of restive elements, the third drive path configured to receive a third drive voltage from a write driver and the fourth drive path configured to receive a fourth drive voltage from the write driver, wherein the first, second, third, and fourth drive voltages configure a state of the resistive elements of first column of resistive elements and the resistive elements of the second column on restive elements to associate a first output voltage with the first out path and a second output voltage with the second out path when the bridge top and the bridge bottom are biased.