Patent ID: 9466671
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region; a fin gate extending to overlap an upper surface and a lateral surface of the active pillar; and a gate insulating layer interposed between the active pillar and the fin gate, wherein the first region of the active pillar is formed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillar, wherein the second region includes Si, wherein the first region includes SiC, AlN, GaN, ZnS, ZnO, ZnSe, CdS, BR or InN, and wherein a stress for improving a current mobility is applied to the first region by a difference of the lattice constants between the first region and the second region.