Patent ID: 9349708
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A chip stacked package structure, wherein the chip stacked package structure comprises: a first chip; and a second chip, stacked with the first chip, wherein the second chip comprises: a package layer, wherein the package layer comprises at least two dies and an attaching part configured to attach the at least two dies, wherein the attaching part is provided with multiple vias, a first part of vias in the multiple vias are disposed at a periphery of the at least two dies, and a second part of vias in the multiple vias are disposed between the at least two dies; and a first routing layer, electrically connecting the at least two dies; wherein the package layer is located between the first routing layer and the first chip, an electrically conductive material is disposed in the multiple vias, and the electrically conductive material electrically connects the first routing layer and the first chip, so that the first chip is electrically connected to at least one die of the at least two dies, and the first part of vias surrounds the at least two dies and an area located between the at least two dies, and the second part of vias is located within the area.