Patent ID: 9373376
Filing Date: 2016-06-21
CPC Classification: G11C,H03L

Claim Text:
1. A latency control circuit comprising: a first latency control section configured to receive a delay-locked termination signal, control a latency of the delay-locked termination signal according to a first divided clock signal, and generate a first preliminary signal; a second latency control section configured to receive the delay-locked termination signal, control the latency of the delay-locked termination signal according to a first divided clock bar signal, and generate a second preliminary signal; a signal combination unit configured to receive the first preliminary signal and the second preliminary signal, shift the first preliminary signal and the second preliminary signal by latency values set differently from each other, according to the first divided clock signal, and generate a first combined signal and a second combined signal; and a signal generation unit configured to generate a latency-controlled termination signal in response to the first combined signal and the second combined signal, wherein the first divided clock bar signal is an inverted first divided clock signal.