Patent ID: 9419146
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a gate electrode layer over a substrate; a gate insulating film over the gate electrode layer; an oxide semiconductor layer over the gate insulating film; an insulating layer over the oxide semiconductor layer; and a source electrode layer and a drain electrode layer over the insulating layer, wherein the oxide semiconductor layer comprises: wherein the first region is positioned between the second region and the third region, wherein a crystallinity of the first region is higher than a crystallinity of each of the second region and the third region, wherein a defect density of the first region is lower than a defect density of the second region, wherein the first region comprises a first crystal part and a second crystal part, wherein a c-axis of each of the first crystal part and the second crystal part is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer, wherein directions of an a-axis and a b-axis of the first crystal part are different from directions of an a-axis and a b-axis of the second crystal part, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, and wherein the insulating layer is in direct contact with top and side surfaces of the oxide semiconductor layer.