Patent ID: 9356040
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a memory device, comprising: forming a plurality of layers of a first semiconductor material; forming a plurality of holes through the plurality of layers; applying an etch process to the plurality of layers through the plurality of holes, to form pull-back regions in the layers adjacent and surrounding the holes; depositing a film of a second semiconductor material over the plurality of holes and into the pull-back regions; removing portions of the film of the second semiconductor material from the plurality of holes while leaving elements of the second semiconductor material in the pull-back regions in contact with the first semiconductor material in the layers; and filling the plurality of holes with insulating material, wherein layers in the plurality of layers of the first semiconductor material have respective first doping concentration profiles, and the elements of the second semiconductor material in the pull-back regions have second doping concentration profiles, the second doping concentration profiles establishing a conductivity in the elements of the second semiconductor material higher than that established by the first doping concentration profiles in the corresponding layers of first semiconductor material.