Patent ID: 9318162
Filing Date: 2016-04-19
CPC Classification: G11C

Claim Text:
1. A circuit comprising: a static random access memory (SRAM) cell comprising at least a wordline coupled to a plurality of NFETs of a transistor array; a wordline driver comprising a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline, wherein overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage; a power gating voltage circuit coupled between the wordline group decode node and the power supply; a retention device coupled to the wordline the power supply, wherein: the plurality of inverters of the wordline driver each include a PFET device and an NFET device; the PFET devices are coupled to the power supply; the NFET device of a first inverter of the plurality of inverters is coupled to a wordline pull down network and its source is coupled to the wordline; a second inverter of the plurality of inverters is coupled to the wordline group decode node; and in a retention state: