Patent ID: 9524143
Filing Date: 2016-12-20
CPC Classification: G06F

Claim Text:
1. Apparatus for data processing configured to respond to a division instruction to perform a division operation, wherein the division operation is arranged to generate a result value by dividing an input numerator specified by the division instruction by an input denominator specified by the division instruction, wherein the input numerator and input denominator are binary values, the apparatus comprising: division circuitry configured to generate the result value by carrying out the division operation; power-of-two detection circuitry configured to signal a bypass condition if the input denominator has a value given by ±2 bypass circuitry configured, in response to signalling of the bypass condition, to cause the division circuitry to be bypassed and to cause the result value to be generated as the input numerator shifted by N bits, and leading zero determination circuitry configured to determine a leading zero count of the input denominator, wherein the power-of-two detection circuitry is configured to determine N from the leading zero count of the input denominator by inverting a binary representation of the leading zero count.