Patent ID: 9490017
Filing Date: 2016-11-08
CPC Classification: G11C

Claim Text:
1. A method of operating a NAND array that includes a plurality of blocks of memory cells, wherein a block of memory cells in the plurality of blocks comprises a plurality of NAND strings having channel lines between first string select switches and second string select switches, and in which the plurality of NAND strings shares a set of word lines between the first and second string select switches, comprising: applying a channel-side erase voltage to the channel lines through the first string select switches in a selected block; applying word line-side erase voltages to a selected subset of the set of word lines in the selected block to induce tunneling in memory cells coupled to the selected subset, the selected subset including more than one member of the set of word lines; applying word line-side inhibit voltages to an unselected subset of the set of word lines in the selected block to inhibit tunneling in memory cells coupled to the unselected subset, the unselected subset including more than one member of the set of word lines; applying a first bias voltage on a first boundary word line in the set of word lines, to induce first boundary conditions, between the selected subset of the set of word lines and the unselected subset of the set of word lines; and applying a second bias voltage on a second boundary word line in the set of word lines, to induce second boundary conditions, between the first boundary word line and the unselected subset of the set of word lines, wherein the first bias voltage is between the word line-side erase voltages and the second bias voltage, and the word line-side inhibit voltages are higher than the second bias voltage.