Patent ID: 9304924
Filing Date: 2016-04-05
CPC Classification: G06F,G11C

Claim Text:
1. A hardware processing element in a processor network, the hardware processing element comprising: at least one receiver configured to receive: a plurality of memory request messages from a plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location; and a plurality of response messages to the memory requests from the plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location; at least one transmitter configured to transmit the memory requests and memory responses to the plurality of memory nodes; and a controller coupled to the receiver and the transmitter and configured to enforce ordering such that memory requests and memory responses designating the same memory location and the same source node/destination node pair are transmitted by the transmitter in the same order received by the receiver, wherein the hardware processing element is coupled to the memory nodes via a plurality of channels, wherein an earlier received ordered memory message is positioned in a first of the channels, wherein a later received ordered memory message is positioned in a second of the channels, and wherein order is enforced by cross-posting a copy of the earlier received message in the second channel in front of the later received message.