Patent ID: 9310776
Filing Date: 2016-04-12
CPC Classification: G04F,H03M

Claim Text:
1. A circuit comprising: a comparator array comprising a first comparator configured to receive an input voltage and output a first polarity signal indicating a polarity of the input voltage along with a first ready signal indicating the first polarity signal is ready in accordance with a timing of a clock signal, and a second comparator configured to receive a first reference voltage and output a second polarity signal indicating a polarity of the first reference voltage along with a second ready signal indicating the second polarity signal is ready in accordance with the timing of the clock signal; a time-to-digital converter configured to receive the first ready signal and the second ready signal and output a digital signal indicating a relative timing between the first ready signal and the second ready signal; and an output encoder configured to receive the first polarity signal and the digital signal and output an output data representing an analog-to-digital conversion of the input voltage.