Patent ID: 9231649
Filing Date: 2016-01-05
CPC Classification: G01S,H03L,H04B,H04J,H04L

Claim Text:
1. A delay locked loop (DLL), comprising: a local signal generation unit configured to generate an early and late delayed signal pair B(t+τ+Δ/2) and B(t+τ−Δ/2), early and late delayed signals, respectively, based on phase delay τ and a delay value difference Δ, with respect to a signal pulse train of a TMBOC (Time-Multiplexed Binarly Offset Carrier) (6,1,4/33)-modulated received signal B(t); early and late autocorrelation units configured to generate 12 early partial correlation functions {P an early sub-correlation function generation unit configured to generate an early sub-correlation function R an early main correlation function combination unit configured to generate an early main correlation function R a late main correlation function combination unit configured to generate a late main correlation function R a numerical control oscillator (NCO) configured to determine a phase delay τ of a delayed signal for the received signal based on a discrimination output based on values of the early and late main correlation functions, and to output the determined phase delay τ to the local signal generation unit; wherein the elimination operation is an operation satisfying algebraic relations in which |A|+|B|−|A −B|=0 in response to real numbers A and B being AB≦0 and |A|+|B|−|A−B|>0 in response to the real numbers A and B being AB>0.