Patent ID: 9396079
Filing Date: 2016-07-19
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor memory device, comprising: a memory cell array including a normal region for storing a plurality of data, an error information region for storing a plurality of error information data corresponding to the plurality of data, respectively, and a redundancy region for replacing the normal region; a write operation unit suitable for storing first bits of an input data as one of the plurality of data on the memory cell array and storing second bits of the input data as a corresponding one of the plurality of error information data on the error information region; an error detection unit suitable for detecting an error on the plurality of data in response to the plurality of error information data, and storing an error location information, which indicates a storage region of a data having an error in the normal region, based on an error detection result; and a repair operation unit suitable for replacing the storage region which is indicated by the error location information, by the redundancy region during a repair operation period.