Patent ID: 9436049
Filing Date: 2016-09-06
CPC Classification: G02F

Claim Text:
1. A flat display panel, comprising: a substrate including a display area and a non-display area surrounding the display area, the display area comprising a plurality of common lines each coupled to a corresponding one of a plurality of rows of pixels; a gate in panel (GIP) gate driver formed in the non-display area of the substrate; a conductive sealing region formed in the non-display area, the conductive sealing region surrounding the gate driver, the conductive sealing region including conductive sealant supplying a common line voltage throughout an entirety of the conductive sealing region; and a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply the common line voltage to said corresponding one of the rows of pixels, the common line voltage supplied to the plurality of common pads through the conductive sealant surrounding each common pad, the conductive sealant electrically connecting the plurality of common pads directly to each other, wherein the plurality of common pads are disposed proximate to a first side of the gate driver, and the display area is disposed proximate to a second side of the gate driver opposite the first side.