Patent ID: 9324687
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A wafer-level package device comprising: a segmented semiconductor wafer section configured to function as a base layer; an integrated circuit chip device coupled to the segmented semiconductor wafer section; a passive device disposed proximate to the integrated circuit chip device and coupled to the segmented semiconductor wafer section; at least one pillar electrically coupled to the integrated circuit chip device and at least one pillar electrically coupled to the passive device; an encapsulation layer covering at least a portion of the segmented semiconductor wafer section, the integrated circuit chip device, and the passive device; a redistribution layer structure coupled to the at least one pillar; and at least one solder bump coupled to the redistribution layer structure and disposed on a surface of the encapsulation layer distal from the segmented semiconductor wafer section.