Patent ID: 9425778
Filing Date: 2016-08-23
CPC Classification: G06F,G11C,H03K,H03L

Claim Text:
1. A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation, comprising; receiving a first stream of data bits input to the data interface circuit; initially establishing, using a first calibration method, an optimal sampling point for sampling the data bits input to the data interface circuit; receiving a second stream of data bits input to the data interface circuit during normal system operation; from time to time during normal system operation, and without disturbing normal system operation, performing a second calibration method different from the first, the second calibration method comprising: establishing at least one reference data path for sampling transition edges of the second stream of data bits input to the data interface during normal system operation; using the at least one reference data path, sampling a plurality of fringe timing points associated with transition edges of the second stream of data bits input to the data interface circuit; wherein the sampling the fringe timing points associated with the transition edge of a particular data bit comprises sampling: a) a plurality of interfringe timing points; and b) an intrafringe timing point; comparing a first fringe timing measurement made during a first performance of the second calibration method, with a second fringe timing measurement made during a second performance of the second calibration method to determine a drift amount for transition edges of the second stream of data bits input to the data interface; comparing the drift amount with a drift correction threshold value; and if the drift amount is greater than the drift correction threshold value, shifting the first optimal timing point in time by the drift amount to revise the first optimal sampling point.