Patent ID: 9449853
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device comprising an electron trap layer between a first semiconductor and a gate electrode, the method comprising the steps of: forming the electron trap layer by sputtering hafnium oxide, wherein the electron trap layer is formed so that the electron trap layer includes crystallized hafnium oxide; forming an electrode so as to be electrically connected to the first semiconductor; forming a second semiconductor; and forming a third semiconductor, wherein the first semiconductor is between the second semiconductor and the third semiconductor, wherein the third semiconductor is between the first semiconductor and the electron trap layer, wherein the sputtering of the hafnium oxide is performed so that the following condition is satisfied: where T is a substrate temperature in degrees centigrade and P is a proportion of oxygen in an atmosphere in percent, and wherein 0≦P≦100.