Patent ID: 9520879
Filing Date: 2016-12-13
CPC Classification: H03K

Claim Text:
1. A gate driver integrated circuit for driving an external n-type MOSFET (NMOS) transistor having a gate, a drain and a source, the drain being coupled through a load to a power supply, the gate driver integrated circuit comprising: a gate driver output configured to drive the gate of the external NMOS transistor; a first comparator operable to receive the drain voltage of the external NMOS transistor and compare it to a reference voltage representative of a short circuit condition between the drain and the power supply, the first comparator being configured to output a first value if the drain voltage is greater than the reference voltage and to output a second value if the drain voltage is less than or equal to the reference voltage; control circuitry configured to receive the output of the first comparator and to pull the voltage of the gate driver output low if the comparator output is of the first value; adaptive masking circuitry operable, upon an application of an “on” signal to the gate driver output, to mask the output of the first comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low, the adaptive masking circuitry being operable to detect a Miller plateau in the gate voltage of the external NMOS transistor, wherein the adaptive masking circuitry is operable to stop masking the output of the first comparator after the end of said Miller plateau.