Patent ID: 9378979
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming an etch-target layer and a first mask layer on a substrate; forming a second mask pattern on the first mask layer, the second mask pattern including a second line portion, a second pad portion, and a second connecting portion between the second line portion and the second pad portion; forming a photoresist pattern on the second pad portion; forming a first spacer to cover a sidewall of the second mask pattern; removing the second line portion and the second connecting portion using the photoresist pattern as an etch mask; etching the first mask layer to form a first mask pattern including a first line portion, a first connecting portion, and a first preliminary pad portion, the first line portion, the first connecting portion, and the first preliminary pad portion having shapes corresponding to those of portions of the first spacer covering the second line portion, the second connecting portion, and the second pad portion, respectively, in plan view; partially removing end portions of the first line portion and the first preliminary pad portion to form a pair of first pad portions spaced apart from each other; forming a second spacer to cover a sidewall of the first mask pattern; removing the first line portion and the first connecting portion; and etching the etch-target layer using the first pad portion and the second spacer as an etch mask, wherein a width of the first spacer is substantially equivalent to a width of the second spacer.