Patent ID: 9258501
Filing Date: 2016-02-09
CPC Classification: H04N

Claim Text:
1. An endoscopic system comprising: a host device; and an endoscope including: wherein said host device comprises an analog-to-digital (A/D) converter connected to the output wire, wherein said means for controlling the plurality of pixels of said CMOS image sensor includes an internal clock having a first clock speed, wherein the A/D converter of said host device includes a second clock having a second clock speed that is faster than the first clock speed, and means for reconstructing the first clock speed of the internal clock, wherein said plurality of pixels are arranged in an array comprising a plurality of rows and a plurality of columns, wherein said means for controlling the plurality of pixels comprises means for causing a first row of pixels including said first pixel to sequentially transmit a first set of said analog reset values onto associated signal lines during said first time period, and for causing said first row of pixels to transmit a first set of said analog signal values onto said associated signal lines during said second time period, wherein said means for transmitting includes means for sequentially transmitting the first set of said analog reset values from said associated signal lines to said output pad during the first time period, and for sequentially transmitting the first set of said analog signal values from said associated signal lines to said output pad during the second time period, wherein said CMOS image sensor further comprises means for transmitting a first synchronization signal onto said output pad prior to said first time period, and a second synchronization signal onto said output pad between said first and second time periods, and wherein said means for reconstructing the first clock speed comprises means for utilizing the first and second synchronization signals and said first set of said analog reset values to determine the first clock speed of the internal clock.