Patent ID: 9385778
Filing Date: 2016-07-05
CPC Classification: H04B

Claim Text:
1. A vector processor, comprising: a plurality of code generators, wherein each code generator is configured to generate a different code corresponding to a different code hypothesis; a plurality of delay elements coupled in series, wherein the delay elements are configured to shift a code by different time delays to generate a plurality of time-shifted codes, each time-shifted code corresponding to a different time hypothesis; and a plurality of despread blocks configured to receive first samples and second samples of a signal; wherein, in a time-searching mode, the plurality of despread blocks is configured to despread at least a portion of the first samples with each one of the time-shifted codes, and, in a code-searching mode, the plurality of despread blocks is configured to despread at least a portion of the second samples with each one of the different codes generated by the code generators.