Patent ID: 9503115
Filing Date: 2016-11-22
CPC Classification: G06F,H03M

Claim Text:
1. A circuit for implementing a time-interleaved analog-to-digital converter circuit, the circuit comprising: a sampling clock generator configured to receive a reference clock signal having a first frequency, the sampling clock generator having a first stage sampling clock generator configured to generate a first plurality of clock signals based upon the reference clock signal and having a second frequency, and a second stage sampling clock generator configured to generate, for each clock signal of the first plurality of clock signals, a second plurality of clock signals having a third frequency; a first stage having a plurality of switches configured to receive an analog input signal, wherein each switch of the plurality of switches is controlled by a corresponding clock signal of the first plurality of clock signals; and a second stage having a plurality of analog-to-digital converter banks, each analog-to-digital converter bank having a plurality of analog-to-digital converters and configured to receive the analog input signal by way of a corresponding switch of the plurality of switches; and wherein each analog-to-digital converter bank of the plurality of analog-to-digital converter banks is configured to receive a plurality of clock phases of a corresponding clock signal of the second plurality of clock signals.