Patent ID: 9461127
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A vertical transistor comprising a semiconductor substrate having a first electrode on its bottom surface; a first layer of a first conductivity type above the bottom surface of the substrate, the first layer having a first dopant concentration; a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface; a trench having a vertical sidewall adjoining the second layer; a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface; a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate; a conductive gate overlying the channel for creating a lateral conductive path in the channel when the gate is biased above a threshold voltage, a vertical field plate facing the vertical sidewall of the second layer and insulated from the sidewall; a second region of the first conductivity type surrounding and abutting the well region and extending to the trench vertical sidewall, the second region having a dopant concentration higher than the second dopant concentration for reducing on-resistance; and a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a current flows between the channel and the substrate.