Patent ID: 9230052
Filing Date: 2016-01-05
CPC Classification: G03F,G06F

Claim Text:
1. A method of generating a simulation model according to a sample conductive feature, the method comprising: receiving a geometry configuration of the sample conductive feature and a layout design of the sample conductive feature; generating a circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature; and converting, by a hardware processor, the circuit-level simulation model of the sample conductive feature into a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and into a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design, wherein at least one of the first set of predetermined criteria or the second set of predetermined criteria comprises a ratio of a first length of the sample conductive feature along a first direction and a second length of the sample conductive feature along a second direction.