Patent ID: 9496052
Filing Date: 2016-11-15
CPC Classification: G11C

Claim Text:
1. An integrated circuit, comprising: first and second memory systems, wherein each memory system includes a memory module having an associated first repair register for receiving compressed memory repair data, and wherein the first repair registers are connected in series as a chain; a store for storing compressed memory repair data for the first and second memory modules; and a processor, operably coupled to the store, for fetching the compressed memory repair data from the store and shifting the fetched compressed memory repair data through the chain for reception by the first repair registers, wherein each memory system includes a second repair register and a decoder, wherein each of the respective decoders is operably coupled between the respective second repair register and the respective first repair register of the memory systems, and wherein each memory system shifts compressed memory repair data for its memory module from the first repair register thereof through the decoder to the second repair register thereof for storage therein as decompressed memory repair data.