Patent ID: 9465610
Filing Date: 2016-10-11
CPC Classification: G06F

Claim Text:
1. A semiconductor device, comprising: a plurality of hardware threads that each issues an independent instruction flow; an execution unit that executes an arithmetic instruction belonging to the instruction flow issued by any one of the plurality of hardware threads; and a scheduler that includes a plurality of first setting registers provided in correspondence with a plurality of partitions and defining a correspondence relationship between the hardware threads and the partitions, and generates a thread select signal on the basis of a partition schedule defining a rate of execution times of the respective partitions, and a thread schedule defining a rate of execution times of the respective hardware threads within the execution time assigned to each of the partitions, wherein the scheduler outputs the thread select signal designating a hardware thread indicated by a first occupation control signal as the hardware thread selected, and wherein the thread select signal is output during the execution time assigned to the partition which is indicated by the first occupation control signal, according to the first occupation control signal output by the execution unit when the arithmetic instruction executed in the execution unit is the first occupation start instruction for occupying the execution time assigned to any one of the partitions.