Patent ID: 9250322
Filing Date: 2016-02-02
CPC Classification: G01S

Claim Text:
1. A signal processor for performing an input signal transform of a signal, the signal processor comprising: a signal demodulator for demodulating said input signal by a first chirp signal having a first chirp rate to obtain a reduced bandwidth signal; an all-pass quadratic phase filter for filtering the demodulated reduced bandwidth signal to introduce a delay proportional to a frequency of said demodulated reduced bandwidth signal, wherein a constant of proportionality is the reciprocal of the first chirp rate; and a signal modulator for modulating said filtered signal from the all-pass quadratic phase filter by a second chirp signal having a second chirp rate to obtain an increased bandwidth chirped signal, the second chirp rate chosen to provide an output representing a time domain spectrum of said input signal, wherein each of said first chirp signal and said second chirp signal is a complex signal representing a linear frequency modulated chirp.