Patent ID: 9484305
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A semiconductor die comprising: a semiconductor substrate; first and second elongated doped regions, said first region serving as a source of a first transistor, said second region serving as a drain of the first transistor and a source of a second transistor; a plurality of straight elongated gate structures including a first gate structure disposed between the first and second regions and serving as a gate of the first transistor and a second gate structure disposed adjacent to the second region and serving as a gate of the second transistor, the second gate structure being parallel with the first gate structure; a first set of evenly-spaced electrical contact pads disposed on the first region, the first set of electrical contact pads including contact pads having a side dimension d a second set of evenly-spaced electrical contact pads disposed on the second region, the second set of contact pads including contact pads having the side dimension d