Patent ID: 9502094
Filing Date: 2016-11-22
CPC Classification: G11C,H01L

Claim Text:
1. A method for driving a memory element comprising a logic circuit configured to hold different potentials in a first node and a second node; a first memory circuit comprising a first transistor and a first capacitor; and a second memory circuit comprising a second transistor and a second capacitor, wherein the first transistor and the second transistor each include indium in a semiconductor layer in which a channel is formed, wherein one of a source and a drain of the first transistor is connected to the first node, wherein the other of the source and the drain of the first transistor and one electrode of the first capacitor are connected to a third node, wherein one of a source and a drain of the second transistor is connected to the second node, wherein the other of the source and the drain of the second transistor and one electrode of the second capacitor are connected to a fourth node, wherein a gate of the first transistor and a gate of the second transistor are connected to a first wiring, and wherein the other electrode of the first capacitor and the other electrode of the second capacitor are connected to a second wiring, the method for driving the memory element comprising the steps of: