Patent ID: 9401196
Filing Date: 2016-07-26
CPC Classification: G11C,H01L

Claim Text:
1. A dual mode memory apparatus, comprising: an array of ferroelectric random access memory (FRAM) storage cells, each FRAM cell consisting of two half-cells (2T/2C); a switching matrix coupled to each FRAM storage cell to switch a bit line associated with each half-cell for write access to the FRAM cell and read access from the FRAM cell; and dual mode state control logic coupled to the switching matrix to control switches associated with the switching matrix to enable full cell read access and both full cell and half-cell write access and to sequence the switches according to a first sequence to perform read operations of read/write (“R/W”) data and to sequence the switches according to a second sequence to perform read operations of imprinted read-only (“RO”) data.