Patent ID: 9401478
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a transistor, the method comprising: forming a base film for supporting a catalyst for electroless plating; forming a resist layer having an opening portion onto the base film, the opening portion having first and second openings corresponding to a source electrode and a drain electrode, respectively; causing the base film within the opening portion to support the catalyst for electroless plating and performing a first electroless plating to form electrodes respectively in the first and second openings; removing the resist layer; after the removing the resist layer, performing a second electroless plating on a surface of each of the electrodes formed by the first electroless plating, thereby forming a source electrode and a drain electrode; and forming a semiconductor layer in contact with a surface of the source electrode and a surface of the drain electrode, the surfaces facing each other, wherein an energy level difference between a work function of a metal material which is used for the second electroless plating and an energy level of a molecular orbital which is used for electron transfer in a formation material of the semiconductor layer is less than an energy level difference between a work function of a metal material which is used for the first electroless plating and the energy level of the molecular orbital.