Patent ID: 9324844
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method for fabricating a vertical JFET, the method comprising: providing a gallium nitride (GaN) substrate; forming an n-type GaN epitaxial layer coupled to the GaN substrate; forming a p-type GaN epitaxial layer coupled to the n-type GaN epitaxial layer, wherein the p-type GaN epitaxial layer is characterized by a p-type dopant concentration; removing at least a portion of the p-type GaN epitaxial layer to expose a portion of the n-type GaN epitaxial layer; forming an n-type GaN channel region coupled to the n-type GaN epitaxial layer and at least a portion of the p-type GaN epitaxial layer; forming an n-type GaN epitaxial structure coupled to the n-type GaN channel region; forming a first metallic structure electrically coupled to the GaN substrate; forming a second metallic structure electrically coupled to the p-type GaN epitaxial layer; and forming a third metallic structure electrically coupled to the n-type GaN epitaxial structure.