Patent ID: 9330926
Filing Date: 2016-05-03
CPC Classification: H01J,H01L

Claim Text:
1. A method of etching features into at least one conductive layer, at least one dielectric layer, and into a silicon substrate through a patterned mask, comprising: a) loading a wafer into a process chamber, wherein the patterned mask, the at least one conductive layer and the at least one dielectric layer are disposed over the silicon substrate; b) etching at least one conductive layer through the patterned mask, comprising c) etching at least one dielectric layer through the patterned mask, comprising: d) etching the silicon substrate through the patterned mask, the at least one patterned conductive layer, and the at least one patterned dielectric layer, comprising: e) unloading the wafer from the process chamber, wherein a temperature of a chuck supporting the silicon substrate is maintained in a range between −10° C. and +10° C. during the etching of the at least one conductive layer and the etching of the silicon substrate.