Patent ID: 9374098
Filing Date: 2016-06-21
CPC Classification: G06F,H03L,H03M,H04L

Claim Text:
1. A transmitter, comprising: a plurality of multiplexers each configured to combine a pseudo random bit sequence (PRBS) with at least one input stream according to a data control clock; at least one storage device coupled to an output of each of the plurality of multiplexers and configured to latch data according to the data control clock; an output multiplexer coupled to each of the at least one storage device and configured to select between storage paths according to a data serializer clock; and a PRBS checker configured to compare a PRBS pattern on an output of the output multiplexer with a predicted PRBS pattern; and a phase rotator configured to adjust the data serializer clock based upon the comparison of the PRBS checker to reduce latency of the transmitter, wherein the PRBS checker is further configured to assess timing between the data control clock and the data serializer clock.