Patent ID: 9368438
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A semiconductor die package, comprising: a semiconductor die, the semiconductor die having a topmost surface and having a contact pad on a bottommost surface; a molding compound at least partially encapsulating the semiconductor die, the molding compound having a topmost surface and a bottommost surface, the topmost surface of the molding compound being coplanar with the topmost surface of the semiconductor die; a through package via (TPV) formed in the molding compound the TPV having a bottommost end that is co-planar with the bottommost surface of the molding compound and having a topmost end that is co-planar with the topmost surface of the molding compound, wherein the TPV has a substantially uniform diameter from the topmost end of the TPV to the bottommost end of the TPV and includes a first conductive layer and a second conductive layer, and wherein the first conductive layer contacts a surface of the molding compound at a first side, contacts the surface of the molding compound at a second side, and is planar across a top surface defined by the first and second side; and a redistribution structure, wherein the redistribution structure includes a redistribution layer (RDL), wherein the TPV is physically connected to the RDL in a first plane, the first plane being parallel to the bottommost surface of the semiconductor die and wherein the semiconductor die is also physically connected to the RDL in the first plane and wherein both the TPV and the semiconductor die are electrically connected to the RDL and wherein the RDL enables fan-out of the semiconductor die.