Patent ID: 9268321
Filing Date: 2016-02-23
CPC Classification: G01R,G04F,G05B,H03M

Claim Text:
1. An apparatus comprising: an input port configured to receive an analog signal that varies as a function of time and to generate an ordered sequence of digital values therefrom; a symbol generator that generates an ordered sequence of symbols from said ordered sequence of digital values, said symbol generator generating one symbol corresponding to each of said digital values, wherein said digital values are characterized by a number of possible digital value states and said symbols are characterized by a number of possible symbol states, said number of possible symbol states being less than said number of possible digital value states; and an FSM characterized by an input word, and a plurality of FSM states, said FSM changing from a current one of said plurality of FSM states to another one of said plurality of FSM states that is determined by said input word and said current one of said plurality of FSM states in response to a cycle signal being received; a controller that causes said FSM to search for a pattern in said ordered sequence of symbols, said controller loading said input word with a plurality of said symbols, generating said cycle signal, and coupling said cycle signal to said FSM.