Patent ID: 9515182
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate including a first active region, a second active region and a field region, the field region being disposed between the first active region and the second active region, the field region directly contacting both the first active region and the second active region; an interlayer dielectric layer disposed on or above the substrate and including a trench, the interlayer dielectric layer extending from the first active region to the second active region; a gate dielectric layer disposed in the trench, and formed along sidewalls and a bottom surface of the trench; a first metal gate electrode disposed on or above the first active region, and disposed on a first sidewall and a bottom surface of the gate dielectric layer; and a second metal gate electrode disposed on or above the second active region, and disposed on a second sidewall and the bottom surface of the gate dielectric layer, wherein a contact surface between the first metal gate electrode and the second metal gate electrode is closer to the first active region than to the second active region, and a top surface of the first metal gate electrode, a top surface of the second metal gate electrode and a top surface of the interlayer dielectric layer are coplanar with each other.