Patent ID: 9424179
Filing Date: 2016-08-23
CPC Classification: G06F,G11C,H03M

Claim Text:
1. A data processing system, the system comprising: a memory device operable to maintain a data set; a data decoder circuit operable to apply one or more iterations of a data decoding algorithm to the data set accessed from the memory device to yield a decoded output, and to provide an iteration count indicating a number of iterations that the data decoding algorithm was applied to the data set; a memory access circuit operable to calculate a frequency of access corresponding to the data set; and a recycle control circuit including a comparator circuit operable to compare the frequency of access with an access frequency threshold, and the recycle control circuit modifies an iteration threshold upon determining the frequency of access exceeds the access frequency threshold; wherein the comparator circuit is operable to compare the iteration count to the modified iteration threshold; and wherein the recycle control circuit recycles read data corresponding to the data set upon determining the iteration count exceeds the modified iteration threshold.