Patent ID: 9443053
Filing Date: 2016-09-13
CPC Classification: G06F

Claim Text:
1. A method of generating macrocells of a semiconductor device according to an integrated circuit design including a hybrid tree mesh clock distribution network, the method comprising: generating with a computing device and storing on a non-transitory computer-readable medium, a collection of macrocells instantiated in the integrated circuit design, wherein instance names of the macrocells include placement information for placing the macrocells in a layout of the integrated circuit design, and further wherein each of the macrocells includes one or more corresponding base cells; determining target drive strengths of clock signals for multiple sequential components on the semiconductor device; determining groups of standard-size clock-driving elements, wherein each of the standard-size clock-driving elements corresponds to one of the base cells and each of the groups has a drive strength equal to one of the target drive strengths; combining the clock-driving elements into the groups; extracting with the computing device, from each of the instance names of the macrocells on the non-transitory computer-readable medium, the corresponding placement information; and distributing the clock signals having the target drive strengths on the semiconductor device with the groups of clock-driving elements as the groups form the hybrid tree mesh clock distribution network of the semiconductor device.