Patent ID: 9230876
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A stack type semiconductor package comprising: a lower semiconductor package comprising a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and comprises a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package comprising an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate; a plurality of first upper lands which are formed on a top surface of the upper package substrate to be insulated from one another by a first solder resist layer, and which the upper semiconductor chip is connected; a plurality of second upper lands and a plurality of third upper lands which are formed on the bottom surface of the upper package substrate, the second upper lands are insulated from the third upper lands by a second solder resist layer, and which the inter-package connection unit and the interconnection unit are respectively connected, wherein a maximum height of the inter-package connection unit measured in a first direction is substantially greater than a maximum height of the interconnection unit measured in the first direction, wherein the first direction is perpendicular to the top surface of the lower package substrate, and wherein the third upper lands are not electrically connected to the first upper lands and the second upper lands, and the second upper lands and the third upper lands have different exposure sizes.