Patent ID: 9436609
Filing Date: 2016-09-06
CPC Classification: G06F,G11C

Claim Text:
1. An apparatus comprising a memory device, the apparatus comprising: a plurality of memory arrays including at least a first memory array and a second memory array; an address translator configured to receive at least a block portion of logical addresses originating from a processor, wherein the block portion corresponds to an address range for selecting blocks of memory, wherein the address translator is configured to modify the received block portion of the logical addresses to generate first modified addresses for the first memory array and second modified addresses for the second memory array for a contiguous logical addresses space; wherein blocks of memory from the first memory array and the second memory array are paired for simultaneous access even when the blocks have disparate physical addresses, wherein pairing blocks from the first memory array and the second memory array is performed by: wherein accesses to pages from paired blocks are interleaved; and a plurality of cache registers including at least a first cache register and a second cache register, wherein the first cache register is disposed in a first signal path between a bus and the first memory array, wherein the second cache register is disposed in a second signal path between the bus and the second memory array, wherein the first cache register is configured to provide first data originally retrieved from the first memory array to a data bus while the second cache register is retrieving second data from the second memory array.