Patent ID: 9299456
Filing Date: 2016-03-29
CPC Classification: G06F,G11C

Claim Text:
1. A computer implemented method for matrix and compression-based error detection, the method comprising: summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row, each of the first plurality of summing modules being coupled to the respective row of the matrix; and summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix, each of the second plurality of summing modules being coupled to the respective column of the matrix; and determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.