Patent ID: 9385135
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method for fabricating a nonvolatile memory device, the method comprising: alternately forming a plurality of interlayer dielectric layers and a plurality of sacrificial layers over a substrate; defining a hole through the interlayer dielectric layers and the sacrificial layers to expose the substrate; forming a semiconductor layer in the hole; defining trenches on both sides of the hole to a depth that passes through the plurality of sacrificial layers; removing the sacrificial layers that are exposed due to the defining of the trenches to create spaces between the interlayer dielectric layers; forming floating gate electrodes, comprising a metal-semiconductor compound, from portions of a side surface of the semiconductor layer that have been exposed due to the removal of the sacrificial layers; and forming a charge blocking layer and a control gate electrode in each of the spaces, wherein the floating gate electrodes are protruded beyond side surfaces of the interlayer dielectric layers toward a vertical channel layer to be formed in the hole.