Patent ID: 9461811
Filing Date: 2016-10-04
CPC Classification: H03L,H04L

Claim Text:
1. A clock and data recovery circuit comprising: a phase detector comparing an input data signal with a frequency dividing signal and generating a phase indication signal to indicate a phase difference between the input data signal and the frequency dividing signal, wherein the phase detector is operated at a first frequency; a phase interpolator receiving a first clock signal, a second clock signal, and a control signal and performing phase interpolation on the first and the second clock signals according to the control signal, so as to generate a phase interpolation signal, wherein the phase interpolator is operated at a second frequency, and the second frequency is greater than the first frequency; a finite state machine coupled to the phase detector and the phase interpolator, the finite state machine generating the control signal based on the phase indication signal with the first frequency and the phase interpolation signal with the second frequency; and a divisor-controllable frequency divider coupled to the phase detector and the phase interpolator, the divisor-controllable frequency divider dividing the second frequency of the phase interpolation signal by a divisor, so as to generate the frequency dividing signal with the first frequency, wherein the divisor is set according to a ratio of the first frequency and the second frequency, wherein when the first frequency of the input data signal is changed, the divisor is adjusted according to the ratio of the changed first frequency and the unchanged second frequency.