Patent ID: 9251305
Filing Date: 2016-02-02
CPC Classification: G06F

Claim Text:
1. A method for evaluating structured cells on a target device, the method comprising: identifying logic functions implementable by a candidate structured cell on the target device by connecting one or more components in the candidate structured cell together to generate a circuit, determining whether the circuit satisfies a set of wiring rules, determining output values for given input values for the circuit, and deriving a truth table that describes one or more logic functions implemented by the circuit from the determination, wherein the candidate structured cell comprises a plurality of gates configurable to be coupled together and the logic functions are implemented by connecting a subset of the plurality of gates together; generating a cell library with a subset of the logic functions implementable by the structured cell; implementing a system on the target device using the subset of logic functions in the cell library; and evaluating the system on the target device, wherein at least one of the identifying, generating, implementing, and evaluating is performed using a processor.