Patent ID: 9300292
Filing Date: 2016-03-29
CPC Classification: H01L,H03K

Claim Text:
1. A semiconductor device comprising: a circuit comprising: wherein a first terminal of the switch is electrically connected to an input terminal of the circuit and a second terminal of the switch is electrically connected to an input node of the first logic circuit, wherein an output node of the first logic circuit is electrically connected to an output terminal of the circuit and an input node of the second logic circuit, wherein an output node of the second logic circuit is electrically connected to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the input terminal of the first logic circuit, wherein a first clock signal is supplied to the switch, wherein a second clock signal is supplied to a gate of the first transistor, wherein the first clock signal comprises a first potential and a second potential lower than the first potential, wherein the second clock signal comprises a third potential and a fourth potential lower than the third potential, wherein the third potential is higher than the first potential, and wherein the fourth potential is higher than the second potential.