Patent ID: 9362402
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a first gate structure and a second gate structure on the semiconductor substrate; forming an offset spacer material layer on the first gate structure, the second gate structure, and the semiconductor substrate; performing a stability doping process onto the offset spacer material layer; performing an etch back process onto the offset spacer material layer to form offset spacers on both sides of each of the first gate structure and the second gate structure, wherein: the offset spacers are doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers by a stability doping process; forming a mask layer on the second gate structure, the offset spacers of the second gate structure, and surface portions of the semiconductor substrate adjacent to the second gate structure; forming first trenches in the semiconductor substrate on both sides of the first gate structure; forming first stress layers in the first trenches; forming second trenches in the semiconductor substrate on both sides of the second gate structure having the mask layer thereon; and forming second stress layers in the second trenches.