Patent ID: 9437319
Filing Date: 2016-09-06
CPC Classification: G11C

Claim Text:
1. A method for reducing bit line interference when programming a non-volatile memory device, the method comprising: providing the non-volatile memory device comprising a set of cells, each cell of the set of cells associated with a bit line; shooting a first shot of programming voltage across each cell of the set of cells; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based on at least the threshold voltage for each cell; and shooting one or more subsequent shots of the programming voltage until the threshold voltage for each cell of the set of cells is greater than a verify voltage, wherein for each shot of the one or more subsequent shots, a fast bit line bias is applied to the bit line associated with each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.