Patent ID: 9263252
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first gate structure; a second gate structure; an interlayer dielectric (ILD) layer over a substrate for electrically insulating the first gate structure from the second gate structure; a protective layer on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, wherein a top surface of the protective layer is level with a top surface of the first gate structure and a top surface of the second gate structure, a thickness of the protective layer is about 20% to about 100% of a thickness of the ILD layer, and the protective layer comprises silicon carbon nitride (SiCN); and a contact etch stop layer (CESL) between the substrate and the ILD layer, wherein the protective layer contacts a sidewall of the CESL.