Patent ID: 9443933
Filing Date: 2016-09-13
CPC Classification: G06F,H01L

Claim Text:
1. A pair of transistors on a substrate having a buried interface which delimits the active region thickness of the channel of said transistors, said transistors having each: a transistor channel length L a transistor channel width W a transistor channel surface S, said transistor channel surface S being greater than or equal to 0.5 μm wherein each transistor of said transistor pair is made of several sub-transistors, wherein each sub-transistor of a transistor has a sub-transistor channel length L wherein the sub-transistor channel width W wherein each sub-transistor of a transistor of said transistor pair is spaced apart from at least one adjoining sub-transistor of the other transistor of said transistor pair by a distance D less than half the transistor channel width W