Patent ID: 9306048
Filing Date: 2016-04-05
CPC Classification: H01L,H03K

Claim Text:
1. An insulated gate turn-off thyristor formed as a die comprising: a first semiconductor layer of a first conductivity type; a first electrode in electrical contact with the first semiconductor layer; a second semiconductor layer of a second conductivity type over the first semiconductor layer; a third semiconductor layer of the first conductivity type over the second semiconductor layer; a matrix of cells comprising a plurality of insulated gate electrodes within trenches formed at least within the third semiconductor layer; a fourth semiconductor layer of the second conductivity type over the third semiconductor layer, wherein there is no semiconductor material of the first conductivity type overlying the fourth semiconductor layer, the fourth semiconductor layer being formed in first areas between at least some of the gate electrodes, wherein a vertical structure of NPN and PNP transistors is formed, and conduction between the first semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the gate electrodes; and a second electrode in electrical contact with the fourth semiconductor layer, wherein a majority of the gate electrodes are first gate electrodes that extend only within the third semiconductor layer, and wherein a minority of the gate electrodes are second gate electrodes that extend through the third semiconductor layer and into the second semiconductor layer.