Patent ID: 9432008
Filing Date: 2016-08-30
CPC Classification: H03K

Claim Text:
1. A delay circuit comprising: an input node; an output node; a first transistor of a first conductivity type, the first transistor having a control node coupled to the input node, a first main current node coupled to a first supply voltage node, and a second main current node coupled to the output node through a third transistor; a second transistor of a second conductivity type, the second transistor having a control node coupled to the input node, a first main current node coupled to a second supply voltage node, and a second main current node coupled to the output node through a fourth transistor; the third transistor having the first conductivity type and having a control node, wherein the first main current node of the first transistor is coupled to the first supply voltage node via the third transistor; the fourth transistor having the second conductivity type and having a control node, wherein the first main current node of the second transistor is coupled to the second supply voltage node via the fourth transistor; and a biasing circuit having a first differential control voltage output coupled to a further control node of the first transistor and a second differential control voltage output coupled to a further control node of the second transistor.