Patent ID: 9306549
Filing Date: 2016-04-05
CPC Classification: G11C,H03K

Claim Text:
1. A negative voltage level shifter, comprising: a first cross-coupled pair of devices, the first cross-coupled pair of devices including NMOS devices; a second cross-coupled pair of devices coupled to the first cross-coupled pair of devices, the second cross-coupled pair of devices including an NMOS device and a PMOS device; wherein the first cross-coupled pair of devices is operable to cause a first predetermined voltage to be applied to a gate of the PMOS device of the second cross-coupled pair of devices responsive a voltage indicative of a predetermined logical value being applied to a logic input of the negative voltage level shifter; and wherein the second cross-coupled pair of devices is operable to cause a negative voltage to be output on a first output of the negative voltage level shifter responsive to application of the first predetermined voltage to the gate of the PMOS device of the second cross-coupled pair of devices.