Patent ID: 9367462
Filing Date: 2016-06-14
CPC Classification: G06F,Y02D

Claim Text:
1. A multi-core processor adapted to share processor resources, comprising: a plurality of processor cores, including first, second, third, and fourth processor cores, configured in a three-dimensional arrangement on a single integrated circuit that includes a plurality of layers, the first, second, third, and fourth processor cores being located on respective first, second, third, and fourth layers of the plurality of layers; a plurality of shared register files, including first, second, third, and fourth shared registers files configured in another three-dimensional arrangement on the single integrated circuit, the shared register files selectively coupled to the plurality of processor cores that are located on the first, the second, the third, and the fourth layers, wherein: a crossbar switch configured to selectively couple any one of the plurality of processor cores to any one of the plurality of shared register files.