Patent ID: 9385068
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method of forming an interconnect structure, the method comprising: forming a first dielectric layer overlying a first conductive layer; etching a trench opening in the first dielectric layer; depositing a sacrificial material layer in the trench opening; forming a second conductive layer overlying the sacrificial material layer; forming an etch stop layer over the second conductive layer; etching away portions of the etch stop layer and the second conductive layer to provide a second conductive portion over the first conductive layer, and an etch stop that overlies the second conductive portion; forming a second dielectric layer overlying the etch stop layer and the sacrificial material layer; forming a via to the sacrificial material layer; and performing an etch to remove the sacrificial material layer through the via and leave a resultant air gap between the first conductive layer and the second conductive layer decreasing the effective dielectric constant between the first and second conductive layers, and decreasing the RC time constant of the interconnect structure.