Patent ID: 9490335
Filing Date: 2016-11-08
CPC Classification: H01L,Y10S

Claim Text:
1. A method for forming semiconductor devices, comprising: doping a surface of a substrate in exposed areas where extra gate (EG) devices are to be formed to form a highly doped region; forming a stack of alternating layers on the substrate over single gate (SG) regions and the EG regions; patterning the stack to form nanosheet structures; forming a dummy gate structure over and between the nanosheet structures; forming an interlevel dielectric layer over the dummy gate structure and the nanosheet structures; removing dummy gate structures to form a dummy gate trench; blocking the SG regions; removing top sheets from the nanosheet structures along the dummy gate trench; releasing at least one bottommost sheet including a semiconductor layer to form a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the at least one bottom most sheet; and forming a gate structure in and over the dummy gate trench wherein the at least one bottommost sheet forms a device channel for the EG device.