Patent ID: 9350324
Filing Date: 2016-05-24
CPC Classification: H03K

Claim Text:
1. A retention flip-flop, comprising: a master latch comprising a first cross-coupled transistor structure and configured to receive and to retain input data in response to a rising or falling edge of a first buffered clock signal and further configured to provide intermediate output data based on the input data; a slave latch comprising a second cross-coupled transistor structure and configured to receive and to retain the intermediate output data from the master latch in response to a falling or rising edge of a second buffered clock signal; a power switch coupled to one of the master latch or the slave latch but not the other of the master latch or slave latch, and configured to reduce power consumption of the one of the master latch or the slave latch, in response to a power off signal; and pull-down circuitry coupled to the other of the master latch or slave latch but not the one of the master latch or slave latch, and configured to pull down the first or second buffered clock signal to a low logic state, which enables the master latch or the slave latch to retain a stored data state, in response to the same power off signal as provided to the one of the master latch or slave latch.