Patent ID: 9431522
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: patterning a semiconductor substrate to form an active pattern; forming oxidation reducing spacers on upper sidewalls of the active pattern; forming device isolation patterns spaced apart from bottom surfaces of the oxidation reducing spacers, the device isolation patterns exposing portions of lower sidewalls of the active pattern; forming a dummy gate pattern crossing over the active pattern and the oxidation reducing spacers, the dummy gate pattern being in direct contact with the active pattern between the device isolation pattern and the oxidation reducing spacers; forming protecting spacers on both sidewalls of the dummy gate pattern, the protecting spacers comprising a material having an etch selectivity with respect to the oxidation reducing spacers; removing the dummy gate pattern to form a gate region exposing lower sidewalls of the active pattern between the protecting spacers; oxidizing the lower sidewalls of the active pattern exposed by the gate region to form a local insulation pattern in the active pattern; and forming a gate electrode in the gate region.