Patent ID: 9479183
Filing Date: 2016-10-25
CPC Classification: G11C,H03L,H04L

Claim Text:
1. A memory storage device, comprising: a connection interface unit, configured to couple to a host system; a rewritable non-volatile memory module comprising a plurality of physical erasing units; and a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the connection interface unit comprises a clock and data recovery circuit module, wherein the clock and data recovery circuit module comprises a data frequency detection circuit and a clock control circuit, wherein the data frequency detection circuit comprises: a sampling circuit module, comprising a plurality of sampling circuits and configured to sample a data signal according to a plurality of reference clocks and output a sampling result; a first logic circuit module, coupled to the sampling circuits and configured to perform a first logic operation according to the sampling result and output a first logic result; a delay circuit module, coupled to the first logic circuit module and configured to delay the first logic result and output the delayed first logic result; a second logic circuit module, coupled to the delay circuit module and configured to perform a second logic operation according to the first logic result and the delayed first logic result and output a second logic result; and a frequency adjustment circuit, coupled to the second logic circuit module and configured to output a first frequency adjustment signal according to the second logic result, wherein the clock control circuit is coupled to the data frequency detection circuit and configured to perform a phase lock according to the first frequency adjustment signal and a frequency of the data signal.