Patent ID: 9317289
Filing Date: 2016-04-19
CPC Classification: G06F,H04L

Claim Text:
1. A method executed by a network processor implementing a pipeline for processing a data packet, where the pipeline includes a plurality of logical blocks, where each of the plurality of logical blocks is configured to process a stage of the pipeline, where the data packet includes a descriptor and a data, and where the network processor is coupled to a resource for storing the data, the method to reduce latency and enable non-blocking processing of the data packet by forwarding a unique identification of a write request from a first logical block in the plurality of logical blocks to a second logical block in the plurality of logical blocks that is subsequent to the first logical block, the write request to modify the data in the resource, the method comprising the steps of: receiving the descriptor of the data packet for processing at the first logical block in the pipeline executed by the network processor; generating the write request and the unique identification of the write request at the first logical block; transmitting the write request from the first logical block to the resource; transmitting the unique identification from the first logical block toward the second logical block before an acknowledgment of the write request is returned by the resource; receiving the unique identification at the second logical block; monitoring for the acknowledgement of the write request from the resource at the second logical block; processing the descriptor in response to receiving the acknowledgment of the write request; and transmitting the descriptor upstream in the pipeline for reprocessing at the first logical block in response to not receiving the acknowledgement after an amount of time has elapsed.