Patent ID: 9466566
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A memory device, comprising: a substrate; a first conductive element; a first conductive line over the substrate and coupled to the first conductive element, the first conductive line orthogonal to the first conductive element; second and third conductive elements orthogonal to the first conductive element; a first memory cell between the second and first conductive elements on a sidewall beside the first conductive element; a second memory cell between the third and first conductive elements on the sidewall beside the first conductive element, wherein the first memory cell is over the second memory cell, and the sidewall extends from the first memory cell to the second memory cell; and a second conductive line parallel to the first conductive line, and a fourth conductive element orthogonal to and coupled to the second conductive line through a conductive pad.