Patent ID: 9378692
Filing Date: 2016-06-28
CPC Classification: G09G,G11C

Claim Text:
1. A gate driving circuit comprising shift registers at a plurality of stages, wherein the shift register at each stage including a pull-up driving unit, a pull-up unit, a reset unit and a pull-down unit, said shift register further including: a supplementary unit; wherein, said pull-up unit is connected to an output terminal of the shift register at a present stage and is used for making a clock signal at a first clock terminal an output signal at the output terminal when being turned on; said supplementary unit is connected to the output terminal of the shift register at the present stage, and is used for making a clock signal at a second clock terminal the output signal at the output terminal when being turned on; said pull-down unit is connected to the output terminal of the shift register at the present stage, and is used for making a low level at a low voltage signal terminal the output signal at the output terminal when being turned on, wherein a first voltage corresponding to a high level of the clock signal at the first clock terminal is higher than a second voltage corresponding to a high level of the clock signal at the second clock terminal, such that the output signal at the output terminal of the shift register at the present stage lumps from the first voltage to the second voltage and then to the low level at the low voltage signal terminal.