Patent ID: 9508428
Filing Date: 2016-11-29
CPC Classification: G11C,H01L

Claim Text:
1. A method of fabricating a vertical type semiconductor device, the method comprising: forming pillar structures, each of the pillar structures in which a conductive layer and a first insulating layer are stacked, on a common source region; forming a gate insulating layer and a gate electrode material on the common source region including the pillar structures; removing the gate electrode material to a predetermined height to insulate gate electrode materials to at least one direction; forming a second insulating layer on the common source region including the gate electrode materials to bury between the pillar structures, planarizing the second insulating layer to expose a surface of the first insulating layer, and removing the first insulating layer; and burying a data storage material in a space from which the first insulating layer is removed.