Patent ID: 9330223
Filing Date: 2016-05-03
CPC Classification: G06F,G06N

Claim Text:
1. A method implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to: obtain a simulation of a metal layer and a via; and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function; detecting at risk structures of a semiconductor device during lithography based on the determined probability, wherein determining the probability that the arbitrary point (x, y) on the metal layer is covered by the via comprises: determining that the metal layer is inside the via by calculating: wherein: determining that the metal layer is outside the via by calculating: wherein: computing a probabilistic area of contact made by a ring having radius “dr” at a distance “r” from a center of the via, wherein: wherein: and wherein the mathematical approximations of the summing function is provided by discretizing equation (4), wherein the arbitrary point (x, y) is defined by an x coordinate and a y coordinate in a cartesian coordinate system, wherein P is a probability, and O wherein [r, r] is a point, Mr2πrdr is an area of the ring covered by the metal, and ε is a member of a set of (0, 1).