Patent ID: 9437502
Filing Date: 2016-09-06
CPC Classification: B82Y,H01L

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: forming a first sacrificial gate structure straddling over a portion of a first fin stack and a second sacrificial gate structure straddling over a portion of a second fin stack, wherein said first and second fin stacks comprise alternating layers of a III-V compound semiconductor material portion and a germanium material portion; forming a first source/drain structure on other portions of said first fin stack and adjacent said first sacrificial gate structure and a second source/drain structure on other portions of said second fin stack and adjacent said second sacrificial gate structure; removing said first sacrificial structure selective to said second sacrificial gate structure to provide a first gate cavity; removing each exposed III-V compound semiconductor portion of said first fin stack in said first gate cavity to provide suspended germanium nanowires that comprise a portion of each germanium material portion of said first fin stack; forming a first functional gate structure in said first gate cavity and surrounding each suspended germanium nanowire; removing said second sacrificial structure selective to said first functional gate structure to provide a second gate cavity; removing each exposed germanium material portion of said second fin stack in said second gate cavity to provide suspended III-V compound semiconductor nanowires that comprise a portion of each III-V compound semiconductor material portion of said second fin stack; and forming a second functional gate structure in said second gate cavity and surrounding each suspended III-V compound semiconductor nanowire.