Patent ID: 9449678
Filing Date: 2016-09-20
CPC Classification: G11C,H01L,Y10S

Claim Text:
1. A semiconductor integrated circuit device provided with a plurality of lead layers over a semiconductor substrate, comprising: a plurality of first memory cells arranged along a first direction; a plurality of second memory cells arranged along the first direction; a first bit line and a second bit line, each commonly connected to the plurality of first memory cells; a third bit line and a fourth bit line, each commonly connected to the plurality of second memory cells; a plurality of word lines extending in a second direction, different from the first direction, each of the plurality of word lines being connected to one of the plurality of first memory cells and one of the plurality of second memory cells, respectively; first, second and third P-well regions provided on a main surface of the semiconductor substrate; a first N-well region provided on the main surface of the semiconductor substrate and arranged between the first and second P-well regions; a second N-well region provided on the main surface of the semiconductor substrate and arranged between the second and third P-well regions; a first voltage supply lead formed at a first level of the plurality of lead layers; a first supply path physically contacting a first portion of the first voltage supply lead opposite to the semiconductor substrate and configured to supply a first voltage to the first P-well region from the first voltage supply lead; a second supply path physically contacting a second portion of the first voltage supply lead, which is different from the first portion, opposite to the semiconductor substrate and configured to supply the first voltage to the second P-well region from the first voltage supply lead; a third supply path connecting to a third portion of the first voltage supply lead, which is different from the first and the second portions, opposite to the semiconductor substrate and configured to supply the first voltage to the third P-well region from the first voltage supply lead; a second voltage supply lead formed at the first level of the plurality of lead layers; a fourth supply path physically contacting a fourth portion of the second voltage supply lead opposite to the semiconductor substrate and supplying a second voltage to the first N-well region from the second voltage supply lead; and a fifth supply path physically contacting a fifth portion of the second voltage supply lead, which is different from the fourth portion, opposite to the semiconductor substrate and supplying the second voltage to the second N-well region from the second voltage supply lead, wherein the first, the second and the third portions are provided to be aligned linearly along the second direction in plan view, wherein the fourth and the fifth portions are provided to be aligned linearly along the second direction in plan view, wherein the plurality of word lines are formed at the first level of the plurality of lead layers, wherein the first, the second, the third and the fourth bit lines are formed at a second level of the plurality of lead layers which is located at a higher level of the plurality of lead layers than the first level, wherein each of the plurality of first memory cells includes: first and second P-channel transistors provided on the first N-well region; first and second N-channel transistors provided on the first P-well region; and third and fourth N-channel transistors provided on the second P-well region, wherein the first N-channel transistor and the first P-channel transistor configure a first inverter, the third N-channel transistor and the second P-channel transistor configure a second inverter with an input of the first inverter coupled to an output of the second inverter and with an output of the first inverter coupled to an input of the second inverter, and wherein the second N-channel transistor electrically connects the first bit line with the output of the first inverter, and the fourth N-channel transistor electrically connects the second bit line with the output of the second inverter, wherein a gate of the fourth N-channel transistor and a gate of the second N-channel transistor are both coupled to a corresponding word line, and wherein each of the plurality of second memory cells includes: third and fourth P-channel transistors provided on the second N-well region; fifth and sixth N-channel transistors provided on the second P-well region; and seventh and eighth N-channel transistors provided on the third P-well region, wherein the fifth N-channel transistor and the third P-channel transistor configure a third inverter, the seventh N-channel transistor and the fourth P-channel transistor configure a fourth inverter with an input of the third inverter coupled to an output of the fourth inverter and with an output of the third inverter coupled to an input of the fourth inverter, and wherein the sixth N-channel transistor electrically connects the third bit line with the output of the third inverter, and the eighth N-channel transistor electrically connects the fourth bit line with the output of the fourth inverter, wherein a gate of the eighth N-channel transistor and a gate of the sixth transistor are both coupled to a corresponding word line.