Patent ID: 9368468
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. An integrated circuit assembly comprising: an insulating layer of a semiconductor-on-insulator die having a first surface and a second surface, the first surface of the insulating layer being less than 10 microns below an upper plane of the integrated circuit assembly, wherein the insulating layer is a buried insulator of the semiconductor-on-insulator die; an active layer of the semiconductor-on-insulator die contacting the first surface of the insulating layer; a via hole through the insulating layer and into the active layer; an electrically conductive material disposed within the via hole and physically contacting the active layer; a metal bond pad formed on the second surface of the insulating layer; a printed circuit board electrically connected to the metal bond pad; wherein the insulating layer, active layer, metal bond pad and printed circuit board are located below the upper plane.