Patent ID: 9286069
Filing Date: 2016-03-15
CPC Classification: G06F

Claim Text:
1. Apparatus for processing data comprising: a register bank configured to store input operands and output operands of data processing operations performed under control of program instructions, said register bank having one or more write ports; processing pipeline circuitry having a plurality of pipeline stages, said processing pipeline circuitry coupled to said register bank via at least said one or more write ports and configured to perform a data processing operation under control of a program instruction and a processing clock signal over a plurality of clock cycles of said processing clock signal to generate one or more output operands; and issue control circuitry configured to issue of said program instruction during a starting clock cycle into said processing pipeline circuitry to commence said data processing operation; wherein said issue control circuitry is configured to select said starting clock cycle such that, at a first predetermined number of clock cycles following said starting clock cycle, at least a minimum number of said one or more write ports will be available to permit said one or more output operands to be written to said register bank; and said processing pipeline circuitry includes bypass circuitry configured: to detect, after said program instruction has been issued into said processing pipeline circuitry, a predetermined state generated by partial completion of said processing operation and indicative of permitted early generation of said one or more output operands; and if (i) said predetermined state is detected, and (ii) said one or more previously issued program instructions indicate that at least said minimum number of said one or more write ports will be available to permit said one or more output operands to be written to said register bank at a second predetermined number of clock cycles following said starting clock cycle, said second predetermined number being fewer than said first predetermined number, then to bypass one or more of said pipeline stages such that said one or more output operands are written to said register bank during a clock cycle following said starting clock cycle by said second predetermined number.