Patent ID: 9330942
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a wiring substrate including an upper surface, an upper conductive pad formed on said upper surface, a lower surface opposite to said upper surface, a lower conductive pad formed on said lower surface, and a testing conductive pad formed on said lower surface, said upper conductive pad to be electrically connected with a conductive pad of another semiconductor device; a semiconductor chip mounted over said upper surface of said wiring substrate; and a solder ball connected with said lower conductive pad, wherein said lower conductive pad is electrically connected with said semiconductor chip; wherein said testing conductive pad is electrically connected with said upper conductive pad; wherein said upper conductive pad is arranged closer to a peripheral portion of said wiring substrate than said semiconductor chip; wherein said testing conductive pad is arranged closer to said peripheral portion of said wiring substrate than said lower conductive pad; and wherein said testing conductive pad is exposed for contacting a probe.