Patent ID: 9455301
Filing Date: 2016-09-27
CPC Classification: G06F,G11C,H01L

Claim Text:
1. A method for operating a non-volatile memory, comprising: determining a first word line within a memory array; determining a first global bit line within the memory array, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line; determining a dummy word line within the memory array, the dummy word line comprises the word line closest to the first global bit line; determining a dummy word line voltage; and performing a memory operation on the memory array, the memory operation includes applying a selected word line voltage to the first word line and applying a selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the dummy word line voltage to the dummy word line while the adjustable resistance local bit line is set into the conducting state, the adjustable resistance local bit line comprises undoped polysilicon.