Patent ID: 9348694
Filing Date: 2016-05-24
CPC Classification: G06F,G11C

Claim Text:
1. A method for managing bad columns of a NAND flash memory array of a NAND flash memory unit, the method comprises: receiving or generating bad columns information indicative of the bad columns of the NAND flash memory array on a column to column basis; receiving an input data unit to be written to the NAND flash memory array; wherein the input data unit comprises bad column mapped data bits that are mapped to flash memory cells that belong to the bad columns of the NAND flash memory array; sending the input data unit to the NAND flash memory unit and instructing the NAND flash memory unit to write the input data unit to a first portion of the NAND flash memory array to provide a programmed data unit; sending the bad column mapped data bits to the NAND flash memory unit; and instructing the NAND flash memory unit to write the bad column mapped data bits to a second portion of the NAND flash memory array to provide programmed bad column mapped data bits; and wherein the first and second portions of the NAND flash memory array belong to a same physical page of the NAND flash memory array.