Patent ID: 9431409
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A three dimensional memory device, comprising: a substrate; a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate; at least one charge storage region located adjacent to the semiconductor channel; a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; an etch stop layer located between the substrate and the plurality of control gate electrodes; a first insulating layer located between the etch stop layer and the substrate, or between the etch stop layer and the plurality of control gate electrodes; a trench extending through the plurality of control gate electrodes and extending vertically to a top surface of the etch stop layer, the top surface of the etch stop layer being a topmost surface or a recessed surface of the etch stop layer; and a material portion located in the trench and having a bottommost surface that contacts the top surface of the etch stop layer and continuously extending through the plurality of control gate electrodes and above a horizontal plane including a topmost surface of the plurality of control gate electrodes, wherein the semiconductor channel extends through the etch stop layer and the first insulating layer.