Patent ID: 9355970
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A method for forming a chip package, comprising: providing a semiconductor substrate having a first surface and a second surface opposite thereto, providing a conducting pad on the first surface of the semiconductor substrate; providing a dielectric layer overlying the first surface of the semiconductor substrate, wherein the dielectric layer comprises an opening exposing the conducting pad; forming a first side recess on at least a first side of the semiconductor substrate, wherein the first side recess extends from the first surface toward the second surface; forming an upper recess on at least a first side of the dielectric layer outside the conducting pad, wherein sidewalls of the upper recess and the first side recess are non-coplanar with each other; providing a conducting layer on the first surface, wherein the conducting layer is electrically connected to the conducting pad and extends to the upper recess and the first side recess.