Patent ID: 9305863
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device including a substrate, and first and second wiring layers formed on the substrate, comprising: a first wiring formed in the first wiring layer; an interlayer insulation film formed between the first wiring layer and the second wiring layer; a second wiring formed in the second wiring layer; a via formed through the interlayer insulation film and connecting the first wiring to the second wiring; and a dummy pattern region in which first dummy wirings formed in the first wiring layer, second dummy wirings formed in the second wiring layer, and dummy vias formed through the interlayer insulation film and connecting the first dummy wirings to the second dummy wirings are disposed, wherein: the first and second wirings constitute a functionable circuit, the dummy pattern region includes a first dummy via region and a second dummy via region, the first dummy via region is located closer to the first and second wirings than the second dummy via region, a number of the dummy vias per area in the first dummy via region is higher than a number of the dummy vias per area in the second dummy via region and in a planar view, a center of an overlap region of one of the first dummy wirings and one of the second dummy wirings coincides with a center of one of the dummy vias.