Patent ID: 9379707
Filing Date: 2016-06-28
CPC Classification: H03K

Claim Text:
1. A decoupling circuit comprising: a first inverter that is coupled between a first power supply and a second power supply having a voltage lower than that of the first power supply to be supplied with a power and that has a first input terminal receiving an enable signal, a second inverter that is coupled between the first power supply and the second power supply and that has a second input terminal receiving an inverted signal of the enable signal, wherein the first inverter includes: a first transistor that is coupled between an output end of the first inverter and the first power supply; second transistors that are coupled in series between the output end of the first inverter and the second power supply and having a conduction type different from that of the first transistor; and wherein control terminals of the first transistor and the second transistors are coupled to the first input terminal, and wherein the second inverter includes: third transistors that are coupled between an output end of the second inverter and the first power supply and having a same conduction type as that of the first transistor; and a fourth transistor that is coupled between the output end of the second inverter and the second power supply and having a conduction type different from that of the first transistor, wherein control terminals of the third transistors and the fourth transistor are coupled to the second input terminal, and wherein a total of gate areas of the first transistor and the fourth transistor is smaller than a total of gate areas of the second transistors and the third transistors.