Patent ID: 9520297
Filing Date: 2016-12-13
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: sequentially forming a hard mask layer and a first sacrificial layer on a substrate; forming a first mandrel on the first sacrificial layer; forming a first spacer on both sidewalls of the first mandrel; removing the first mandrel; forming a second mandrel by etching the first sacrificial layer using the first spacer as an etch mask; forming a second spacer on both sidewalls of the second mandrel; removing the second mandrel; forming a hard mask pattern by patterning the hard mask layer using the second spacer as an etch mask, the hard mask pattern including first to ninth fin-type mask patterns extending to be parallel with each other in a first direction and sequentially spaced apart from each other in a second direction perpendicular to the first direction; removing the third, fifth and seventh fin-type mask patterns; forming first to sixth active patterns by etching the substrate using the hard mask pattern as an etch mask; and forming a first gate electrode extending in the second direction to intersect the first to fourth active patterns and a second gate electrode extending in the second direction to intersect the third to sixth active patterns and spaced apart from the first gate electrode in the first direction without intersecting the first and second active patterns.