Patent ID: 9281070
Filing Date: 2016-03-08
CPC Classification: G11C,H01L

Claim Text:
1. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a ground selection transistor, a plurality of nonvolatile memory cells and a dummy memory cell, the ground selection transistor being connected to a source line, and the plurality of memory cells stacked on a direction perpendicular to a substrate, the method comprising: generating an erase voltage that rises from a first level, the erase voltage being supplied to a channel of the first memory cell string; supplying a first voltage to a ground selection line connected to the ground selection transistor and a second voltage to a dummy word line connected to the dummy memory cell; then floating the ground selection line when a level of the erase voltage reaches to a second level higher than the first level; and floating the dummy word line when a level of the erase voltage reaches to a third level higher than the second level.