Patent ID: 9356530
Filing Date: 2016-05-31
CPC Classification: H02M,Y02B

Claim Text:
1. A DC-DC converter, comprising: a coil connected to a first node, to which a pulse signal is supplied, at a first end thereof and to an output terminal at a second end thereof; a capacitor that is connected between the second end of the coil and a first fixed potential; a voltage dividing circuit that divides a voltage at the output terminal and outputs a resulting divided voltage; an error amplifier that receives the divided voltage and a reference voltage, outputs a comparison result signal, which is responsive to a result of comparison between the divided voltage and the reference voltage, to a second node; a filter circuit that is connected to the second node at a first end thereof and to the first fixed potential at a second end thereof, compensates for a phase of the comparison result signal output from the error amplifier; a switching controlling circuit that controls a duty cycle of the pulse signal supplied to the first node so as to bring the voltage at the output terminal closer to a target value, based on the comparison result signal; a mode comparator that receives the comparison result signal and a threshold, outputs a mode signal that prescribes an active mode in which the switching controlling circuit performs an operation of outputting the pulse signal, or the mode signal that prescribes an inactive mode in which the switching controlling circuit stops the operation of outputting the pulse signal, based on the result of comparison between the comparison result signal and the threshold, the mode comparator having a hysteresis characteristic; and a lower limit value setting circuit that sets a lower limit value for the comparison result signal supplied to the second node in accordance with the mode signal and performs control to prevent the comparison result signal from being lower than the lower limit value, and wherein in the lower limit value setting circuit, the lower limit value is switched to a first lower limit value, if the mode signal prescribes the active mode, on the other hand, the lower limit value is switched to a second lower limit value, which is higher than the first lower limit value, if the mode signal prescribes the inactive mode.