Patent ID: 9229854
Filing Date: 2016-01-05
CPC Classification: G06F

Claim Text:
1. An integrated circuit, comprising: a memory controller to control the performance of memory transactions directed to multiple arrays of flash memory; and interface circuitry sufficient to exchange information with a host and with the multiple arrays of flash memory; wherein the memory controller includes logic to, via the interface circuitry, receive one or more requests from the host relating to a transaction operand in the multiple arrays of flash memory, the one or more requests each specifying an address for each of the multiple arrays of flash memory, and to control satisfaction of the one or more requests by the multiple arrays of flash memory; and wherein the memory controller is configured to preserve page addressing specified by each of the one or more requests relative to any erase unit (EU) position within flash memory, such that any address translation performed by the memory controller for any one of the multiple arrays of flash memory is limited to translating EU location within the one or more arrays of flash memory.