Patent ID: 9401343
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. A method of processing a semiconductor wafer, the method comprising: forming a plurality of semiconductor dies in the semiconductor wafer, each semiconductor die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the semiconductor dies being separated by a scribe line; forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric; forming ancillary wiring over the edge region of each semiconductor die in the interlayer dielectric, the ancillary wiring in electrical isolation from the interconnect wiring; forming a passivation on the interlayer dielectric; forming a plurality of bond pads over the interconnect wiring of each semiconductor die, the bond pads of each semiconductor die being in electrical connection with the interconnect wiring of that semiconductor die; and forming a plurality of additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each semiconductor die being in electrical connection with the interconnect wiring of that semiconductor die, wherein the electrical connection is made through openings in the passivation over the active region.