Patent ID: 9507602
Filing Date: 2016-11-29
CPC Classification: G06F

Claim Text:
1. A computer-implemented method, comprising: requesting, by a first processor thread of a computer processor, access to exception tracking logic, the exception tracking logic being shared across a plurality of processor threads, wherein only a single processor thread of the plurality of processor threads is configured to access the exception tracking logic at a time; receiving, by the first processor thread, access to the exception tracking logic; preventing a second processor thread's access to the exception tracking logic while the first processor thread has access to the exception tracking logic; executing, by the first processor thread, a process in slow mode, wherein the executing the process in the slow mode comprises: based on detecting an exception during the slow mode, storing, by the first processor thread, exception information about the exception in the exception tracking logic; copying the exception information from the exception tracking logic to a set of external registers outside the exception tracking logic; releasing the exception tracking logic to allow access to the exception tracking logic by the other processor threads of the plurality of processor threads; and processing the exception, after the copying the exception information, based on the exception information stored in the set of external registers, wherein the copying the exception information and the processing the exception are performed by firmware.