Patent ID: 9401334
Filing Date: 2016-07-26
CPC Classification: H01L

Claim Text:
1. An integrated circuit for preventing unauthorized use of the integrated circuit in radiation-hardened environments, the integrated circuit comprising: a silicon-on-insulator (SOI) structure comprising a silicon substrate, a buried oxide layer on the silicon substrate, and an active silicon layer on the buried oxide layer; a radiation insensitive sub-circuit formed on the active layer, and including a partially depleted transistor; and a radiation sensitive sub-circuit formed on the active layer, and including a fully depleted transistor, to prevent operation of the radiation insensitive sub-circuit under specified radiation conditions; and wherein: each of the partially depleted transistor and the fully depleted transistor includes a channel region formed in the active silicon layer, and the channel regions of the partially depleted transistor and the fully depleted transistor have substantially the same thickness and different doping concentrations.