Patent ID: 9461633
Filing Date: 2016-10-04
CPC Classification: H03K,H03M

Claim Text:
1. A latch circuit having a first mode of operation in which the latch circuit functions as a static latch circuit, and having a second mode of operation in which the latch circuit functions as a dynamic latch circuit; the latch circuit having inputs for receiving a latch circuit clock input and a data input and having an output for producing a latch circuit output, the latch circuit comprising: a forward data path transmission circuit connected to receive the latch circuit clock input and the data input, the forward data path transmission circuit producing a data output, the forward data path transmission circuit having a transparent state activated by the clock input during which the data input is produced as the data output; a storage circuit connected to receive the data output, the storage circuit having a forward path and a feedback path, the storage circuit having a clock input and producing the latch circuit output; wherein during the first mode of operation the feedback path is active, and based on the clock input of the storage circuit, the storage circuit maintains a value output by the forward data path transmission circuit as part of the data output, such that the latch circuit functions as a static latch circuit; and during the second mode of operation, the feedback path is inactive, and the latch circuit output is the data output after passing through the forward path of the storage circuit, such that the latch circuit functions as a dynamic latch circuit.