Patent ID: 9257437
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: forming a bit line structure on a substrate, the bit line structure including a polysilicon layer pattern doped with impurities and a metal layer pattern on the polysilicon layer pattern; forming a first insulating layer including a nitride on a sidewall of the bit line structure by a plasma treatment process; forming a second insulating layer including a nitride on the first insulating layer, wherein the first and second insulating layer are merged to each other to define a single insulating layer; etching the single insulating layer anisotropically to form a first spacer surrounding and contacting the sidewall of the bit line structure, the first spacer having a constant thickness at least on sidewalls of the polysilicon layer pattern and the metal layer pattern; and forming a capacitor contact structure on the substrate, the capacitor contact structure together with the first spacer defining an air gap therebetween.