Patent ID: 9391082
Filing Date: 2016-07-12
CPC Classification: G11C,H01L

Claim Text:
1. A method of forming a memory array, comprising: forming a plurality of control gates; forming a plurality of first dielectrics, wherein the control gates and the first dielectrics alternate so that one of the plurality of first dielectrics is interposed between successively adjacent ones of the plurality of control gates; forming a plurality of blocking dielectrics so that a blocking dielectric is adjacent to each of the plurality of control gates; forming a plurality of charge-storage structures so that a charge-storage structure is adjacent to each of the plurality of blocking dielectrics; forming a plurality of tunnel dielectrics so that a tunnel dielectric is adjacent to each of the plurality of charge-storage structures; forming a substantially vertical pillar adjacent to the plurality of tunnel dielectrics; wherein each memory cell of a portion of a series-coupled string of memory cells comprises one of the control gates, one of the blocking dielectrics, one of the charge-storage structures, and one of the tunnel dielectrics; wherein one of the plurality of first dielectrics is further interposed between successively adjacent ones of the plurality of plurality of blocking dielectrics, between successively adjacent ones of the plurality of charge-storage structures, and between successively adjacent ones of the plurality of tunnel dielectrics; and wherein a memory cell of the series-coupled string where the pillar has a first size has a greater thickness than a memory cell of the series-coupled string where the pillar has a second size larger than the first size.