Patent ID: 9269690
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor chip having conductive pads; a package structure defining a rectangular boundary and having a bottom surface and comprising; only two interior polygonal pads exposed at the bottom surface of the package structure, each of the interior polygonal pads being physically and electrically separated from each other at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure; and only four edge polygonal pads exposed at the bottom surface of the package structure, each of the edge polygonal pads being located at an edge of the rectangular boundary, the edge polygonal pads including one edge polygonal pad in the vicinity of each corner of the rectangular boundary; wherein each of the interior polygonal pads has a first side that is parallel to a facing side of the edge polygonal pad that is nearest to the first side and a second side that is parallel to a facing side of the edge polygonal pad that is nearest to the second side, wherein the first side and the second side of each of the interior polygonal pads are not parallel to the rectangular boundary of the package structure; and wherein the interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure; wherein each of the interior polygonal pads and the edge polygonal pads is electrically connected to a different one of the conductive pads of the semiconductor chip.