Patent ID: 9496833
Filing Date: 2016-11-15
CPC Classification: H03F

Claim Text:
1. An amplifier comprising: a plurality of channels comprising: a timing control circuit configured to operate the first channel in the autozero phase during a first time interval and to operate two or more other channels in at least one of the non-inverting chop phase or the inverting chop phase during the first time interval, wherein the timing control circuit is further configured to operate the second channel in the autozero phase during a second time interval and to operate two or more other channels in at least one of the non-inverting chop phase or the inverting chop phase during the second time interval, and wherein the timing control circuit is further configured to operate the third channel in the autozero phase during a third time interval and to operate two or more other channels in at least one of the non-inverting chop phase or the inverting chop phase during the third time interval, wherein the first time interval, the second time interval, and the third time interval are staggered in time with respect to one another.