Patent ID: 9419106
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a non-planar transistor fin on a substrate; forming a non-planar transistor gate over the non-planar transistor fin; conformally depositing a dielectric material layer over the non-planar transistor gate and the non-planar transistor fin; and forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent sidewalls of the non-planar transistor gate; and removing the dielectric material layer adjacent the non-planar transistor fin; wherein forming the non-planar transistor gate spacers and removing the dielectric material layer adjacent the non-planar transistor fin occur simultaneously; wherein forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent sidewalls of the non-planar transistor gate, and removing the dielectric material layer adjacent the non-planar transistor fin comprises: