Patent ID: 9396789
Filing Date: 2016-07-19
CPC Classification: G06F,G11C,Y02D

Claim Text:
1. A memory control device including a delay locked loop circuit, the memory control device comprising: a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory; a first register to store a first DLL value output by the delay locked loop circuit; a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits; and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value, wherein the delay controller calculates the second setting value at n times, where n is a natural number equal to or greater than 1, using the following equation, the A the B the A the B