Patent ID: 9373363
Filing Date: 2016-06-21
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor device comprising: first to n-th (n is an integer of 2 or more) nonvolatile semiconductor memories; (n+1)-th to 2n-th nonvolatile semiconductor memories; first to n-th resistive elements; a controller configured to control the first to 2n-th nonvolatile semiconductor memories; first to n-th signal lines respectively connecting the controller and the first to n-th resistive elements; (n+1)-th to 2n-th signal lines respectively connecting the first to n-th resistive elements and the first to n-th nonvolatile semiconductor memories; (2n+1)-th to 3n-th signal lines divided from the (n+1)-th to 2n-th signal lines, and respectively connected with the (n+1)-th to 2n-th nonvolatile semiconductor memories; and a substrate, wherein the substrate includes a front surface layer including a wiring pattern formed on a front surface of the substrate, and on which the first to n-th nonvolatile semiconductor memories, the first to n-th resistive elements, and the controller are mounted, a rear surface layer including a wiring pattern formed on a rear surface of the substrate, and on which the (n+1)-th to 2n-th nonvolatile semiconductor memories are mounted, and a connector configured to be connected with an external device, and the first to n-th nonvolatile semiconductor memories and the (n+1)-th to 2n-th nonvolatile semiconductor memories are symmetrically disposed with respect to the substrate.