Patent ID: 9431108
Filing Date: 2016-08-30
CPC Classification: G11C,H01L

Claim Text:
1. An integrated structure comprising: a substrate; a first MOS transistor of an SRAM elementary cell overlying the substrate and comprising a first controllable gate region separated from the substrate by a first gate dielectric; a second MOS transistor of the SRAM elementary cell neighboring the first MOS transistor and comprising a second controllable gate region separated the substrate by the first gate dielectric; and a common conductive region being part of the SRAM elementary cell and overlying the first and second gate regions and separated therefrom by a second gate dielectric, the common conductive region comprising a continuous element located over a portion of the first and second controllable gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric, the branch located between the first and second controllable gate regions and spaced from both the first and second controllable gate regions, wherein the first controllable gate region laterally extends beyond the continuous element of the common conductive region and comprising a first contact pad for coupling to a first metal track portion disposed over the first controllable gate region, and wherein the second controllable gate region laterally extends beyond the continuous element of the common conductive region and comprising a second contact pad for coupling to a second metal track portion disposed over the second controllable gate region.