Patent ID: 9444465
Filing Date: 2016-09-13
CPC Classification: H03K,H03L

Claim Text:
1. A frequency divider including: (a) a master counter; (b) an auxiliary counter coupled to the master counter; (c) a source for a settable master counter value; (d) a source for a settable auxiliary counter value; (e) a source for a variable offset number; (f) combining circuitry having a first mode of operation in which the variable offset set number, the settable master counter value, and the settable auxiliary counter value are combined to generate an actual master counter value and to generate an actual auxiliary counter value in a first range of values, and having a second mode of operation in which the variable offset set number and the settable auxiliary counter value are combined to generate an actual auxiliary counter value in a second range of values and in which the settable master counter value is passed unchanged as the actual master counter value; and (g) coupling circuitry for providing the actual master counter value to the master counter and the actual auxiliary counter value to the auxiliary counter; wherein phase noise of the frequency divider is lower in the second mode of operation than in the first mode of operation.