Patent ID: 9502112
Filing Date: 2016-11-22
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device comprising a plurality of memory cells arranged like a matrix, each of the memory cells being configured to be capable of holding two bits of information and including a first cell configured to be capable of holding one bit of information, a second cell adjacent, in a column direction, to the first cell and configured to be capable of holding another bit of information, and a logic operation cell coupled to the first cell and the second cell, the semiconductor memory device further comprising: a bit line pair extending in the column direction and coupled to both the first and the second cell; a first and a second word line extending in a row direction and coupled to the first and the second cell, respectively; a match line extending in the row direction and coupled to the logic operation cell; a search line pair extending in the column direction and coupled to the logic operation cell; the logic operation cell driving the match line based on comparison results between information held in the first and the second cell and search data transferred by the search line pair; and a search line driver provided correspondingly to the search line pair to drive the search line pair, wherein, in a state with the search line pair precharged to a third voltage between a first voltage and a second voltage, the search line driver drives, according to the search data, one and the other search line included in the search line pair to the first and the second voltage, respectively.