Patent ID: 9391137
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A power semiconductor device comprising: a substrate; a trench structure situated in the substrate and comprising first trenches and dummy trenches formed adjacent to the first trenches; a first well region of a second conductivity type situated between the first trenches; a base region of a first conductivity type situated on the first well region; a source region of the second conductivity type and a first contact region of the first conductivity type situated in the base region; gate insulating layers situated in the first trenches and the dummy trenches; gate electrodes situated on the gate insulating layers; a field stop layer situated below the base region; a collector layer and a drain electrode situated below the field stop layer; and a dummy cell region situated between the first trenches and the dummy trenches, wherein the dummy cell region has no channel region.