Patent ID: 9396783
Filing Date: 2016-07-19
CPC Classification: G06F,G11C

Claim Text:
1. A memory device configured to emulate dynamic random access memory (DRAM) comprising: a memory array including a plurality of memory cells organized into rows and columns, at least one row of memory cells comprising a plurality of pages that store bursts of data during burst write operations, each burst of data including sequential data units that are written to a page; a mask register coupled to said memory array and configured to generate write masks for said burst write operations; and a control circuit operable to: initiate a burst write operation that writes a burst of data to said memory array, said burst write operation spanning multiple clock cycles; and after receiving one or more data units of said burst of data by said memory array, allow a subsequent burst write or read command to begin before completion of said burst write operation in progress.