Patent ID: 9293102
Filing Date: 2016-03-22
CPC Classification: G02F,G06F,G09F,G09G,H01L

Claim Text:
1. A display, comprising: rows and columns of pixels, each pixel having at least one transistor with a gate; a plurality of gate lines each of which is connected to the gates of the transistors in the pixels of a respective one of the rows; a plurality of data lines running perpendicular to the gate lines; a plurality of gate line extensions each of which runs parallel to the data lines and each of which is connected to a respective one of the gate lines, wherein each gate line extension runs under a respective one of the data lines and is separated from that gate line by a layer of dielectric, wherein the plurality of gate line extensions are all of equal length; a layer of liquid crystal material; electrodes coupled to the transistors, wherein the transistors apply voltages to the electrodes that create electric fields in the layer of liquid crystal material; and vias that connect the gate lines extensions to the gate lines.