Patent ID: 9356032
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate; a first element isolation film which is formed in the substrate and is located adjacent to a first element formation region of the substrate; a floating gate insulating film formed over the substrate located in the first element formation region; a floating gate electrode formed over the floating gate insulating film; a control gate electrode formed over the floating gate electrode via a first insulating film; a selection gate insulating film which is formed over the substrate located in the first element formation region and is located adjacent to the floating gate insulating film; a selection gate electrode which is continuously formed over the selection gate insulating film and the first element isolation film and whose side surface is in contact with a first side surface of the floating gate electrode through a second insulating film; and an erase gate electrode that is in contact with a second side surface of the floating gate electrode through a third insulating film, wherein a first upper surface, which is an upper surface of a region overlapping with the selection gate electrode in the first element isolation film, is located lower than an upper surface of the substrate.