Patent ID: 9362391
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A silicon carbide semiconductor device comprising an MOSFET that includes: a well region formed in an upper surface portion of a silicon carbide semiconductor layer; a source region formed in an upper surface portion of said well region; a source electrode formed on said source region; a gate oxide film formed on said well region and said source region; and a gate electrode formed on said gate oxide film, wherein an impurity concentration at an upper surface portion of said source region is 1×10 wherein a peak of the impurity concentration in said source region is 1×10 wherein the peak of the impurity concentration in said source region is in a location of the source region different from the surface portion of the source region at a depth deeper than an interface between said source region and a bottom surface of said source electrode.