Patent ID: 9275959
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A semiconductor package comprising: a substrate including an insulation layer; a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines extending between the first internal ground line and sidewalls of the substrate, the first extended ground lines including end portions that are exposed at the sidewalls of the substrate; a second ground line including a second internal ground line disposed along the edges of the substrate and a plurality of second extended ground lines extending between the second internal ground line and the sidewalls of the substrate, the plurality of second extended ground lines including end portions that are exposed at the sidewalls of the substrate, and being spaced apart from each other along the edges of the substrate by the insulation layer; a chip on the substrate; a molding member disposed on the substrate to cover the chip; and an electromagnetic interference (EMI) shielding layer covering the molding member and extending along the sidewalls of the substrate, the EMI shielding layer contacting the end portions of the plurality of first extended ground lines, and alternately contacting the end portions of the plurality of second extended ground lines and exposed portions of the sidewalls of the insulation layer along a circumference of the substrate.