Patent ID: 9466252
Filing Date: 2016-10-11
CPC Classification: G09G,G11C

Claim Text:
1. A liquid crystal display device, comprising: a pixel array comprising a plurality of pixels arranged in rows and columns; a timing controller outputting a clock signal; a gate driver receiving the clock signal, comprising: a first shift register coupled to a first row of the pixel array; and a second shift register coupled to a second row of the pixel array, wherein when it is determined that the first row is to be skipped, the first shift register outputs a first voltage level to the first row with the clock signal, and when it is determined that the second row is to be scanned, the second shift register outputs a second voltage level to the second row with the clock signal, wherein the first voltage level is between the second voltage level and a third voltage level which maintains a previously written display data of the pixel array; wherein at least one of the pixels comprises a pixel transistor, and the first voltage level is set to not turn on the pixel transistor but have enough of a high voltage to maintain the propagation of the first shift register operation of the gate driver.