Patent ID: 9459317
Filing Date: 2016-10-04
CPC Classification: G01R

Claim Text:
1. A mixed mode integrated circuit being adapted for electromagnetic compatibility testing, the mixed mode integrated circuit comprising: an analogue sub-circuitry; a digital sub-circuitry; a clock network comprising a clock input and being arranged to provide a first clock signal and a second clock signal in response to a clock signal received at the clock input; an integrated test clock signal generator being arranged to generate a first test clock signal and to generate a second test clock signal in response to an input test clock signal having a controllable frequency, the first test clock signal and the second test clock signal having a controllable frequency that relates to the controllable frequency of the input test clock signal; a first controllable clock multiplexer coupled to the first clock signal and to the first test clock signal and being arranged to provide either the first clock signal or the first test clock signal to the analogue sub-circuitry; and a second controllable clock multiplexer coupled to the second clock signal and to the second test clock signal and being arranged to provide either the second clock signal or the second test clock signal to the digital sub-circuitry.