Patent ID: 9368393
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method of mitigating line-edge roughness in a semiconductor device, the method comprising: providing a substrate with a plurality of layers formed on the substrate, wherein the plurality of layers comprise: an organic antireflective coating/silicon oxynitride (oARC/SiON) film stack, a high density plasma oxide (HDP) film and a tetraethyl orthosilicate (TEOS) film; providing a patterned photoresist layer over the plurality of layers formed over the substrate, wherein the patterned photoresist layer is in contact with the oARC/SiON film stack; and etching the plurality of layers formed on the substrate, using the patterned photoresist layer as an etching mask to form at least one trench in the plurality of layers, wherein a bottom electrode in contact with the semiconductor device has a temperature approximately in a range of 10-15 degrees Celsius during at least the oARC/SiON film etching.