Patent ID: 9373611
Filing Date: 2016-06-21
CPC Classification: H01L,H03K

Claim Text:
1. A semiconductor integrated circuit device which includes a standard logic cell, wherein the standard logic cell comprising: a plurality of circuit elements which are formed on a semiconductor substrate; first and second power wirings which are formed in a first wiring layer which is an upper layer of the semiconductor substrate, which are separated from each other in a cell height direction and extend in a cell width direction which is perpendicular to the cell height direction in a planar view, and which supply a first reference voltage to at least one of the plurality of circuit elements, wherein the first reference voltage is one of power voltage and ground voltage; a third power wiring which is formed in the first wiring layer, which extends in the cell width direction between the first and second power wirings in the planar view, and which supplies a second reference voltage which is different from the first reference voltage to at least one of the plurality of circuit elements, wherein the second reference voltage is the other of the power voltage and the ground voltage; a plurality of first signal wirings formed in the first wiring layer, which are separated from the first, second, and third power wirings in the planar view, and each of which is electrically connected to at least one of the plurality of circuit elements; and a plurality of second signal wirings formed in a second wiring layer which is a next wiring layer just above the first wiring layer, each of which extends in the cell width direction in the planar view, and each of which is electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings, wherein: at least one of the plurality of second signal wirings extends in the cell width direction between the first and third power wirings in the planar view, has a linear shape having a longer length along the cell width direction than along the cell height direction, and is separated from other ones of the plurality of second signal wirings, the standard logic cell further includes a first auxiliary wiring which is formed in the second wiring layer, and the first auxiliary wiring extends in the cell height direction in the planar view, and connects two second signal wirings from among the plurality of second signal wirings.