Patent ID: 9230946
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A semiconductor integrated circuit device comprising: (a) an organic multilayer wiring board having a chip mounting surface and an external land arrangement surface; (b) a first semiconductor chip mounted over the chip mounting surface and having an analog circuit area and a first digital circuit area; (c) a second semiconductor chip mounted over the chip mounting surface and having a second digital circuit area; and (d) a plurality of bonding wires which interconnect between a plurality of terminals provided over respective surfaces of the first and second semiconductor chips, wherein the thickness of the first semiconductor chip is thinner than the thickness of the second semiconductor chip, wherein a semiconductor substrate of the first semiconductor chip is a P-type single crystal semiconductor silicon substrate, comprising a non-epitaxial substrate type bulk CMOS structure, wherein the organic multilayer wiring board includes: (a1) a front surface wiring layer provided on the front surface side; (a2) a back surface wiring layer provided on the back surface side; (a3) a front surface-side internal wiring layer provided between the front surface wiring layer and the back surface wiring layer; (a4) a back surface-side internal wiring layer placed between the front surface wiring layer and the back surface wiring layer and provided on the side closer to the back surface wiring layer than the front surface-side internal wiring layer; (a5) a first analog circuit-internal layer reference voltage plane which is below the first semiconductor chip and provided in one of the front surface-side internal wiring layer and the back surface-side internal wiring layer; and (a6) a first digital circuit-internal layer reference voltage plane which is below the first semiconductor chip and which is provided in the one of the front surface-side internal wiring layer and the back surface-side internal wiring layer and plane-geometrically separated from the first analog circuit-internal layer reference voltage plane.