Patent ID: 9304731
Filing Date: 2016-04-05
CPC Classification: G06F,G09G,H04L,H04N

Claim Text:
1. A method, comprising: determining, by a processor circuit, a target display data transmission rate for one or more displays; generating, by a digital differential analyzer (DDA) communicatively coupled to the processor circuit, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate; transmitting the one or more display data packets based on the actual display data transmission rate; accumulating a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets, the display data packets comprising a display data packet stream, the display data packet stream comprising one or more display data transmission lanes; receiving one or more display data source streams; and processing the one or more display data source streams to form the display data packet stream, each of the one or more display data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data source streams.