Patent ID: 9488692
Filing Date: 2016-11-08
CPC Classification: G01R

Claim Text:
1. An integrated circuit comprising: a plurality of functional circuit blocks each coupled to receive a respective one of one or more clock signals, wherein each of the plurality of functional circuit blocks includes logic circuitry intended to perform a function of the integrated circuit; a first plurality of clock-gating circuits, wherein each of the plurality of functional circuit blocks includes a subset comprising two or more clock-gating circuits each coupled to receive the respective one of the clock signals for that functional circuit block, and wherein each of the first plurality of clock-gating circuits is a leaf level clock-gating circuit of a corresponding clock tree; and a second plurality of clock-gating circuits implemented as branch level clock-gating circuits, wherein each of the second plurality of clock-gating circuits is coupled to distribute the respective one of the clock signals for that functional circuit block to the subset comprising two or more clock-gating circuits implemented in that functional circuit block; wherein, during a scan test and within each of the plurality of functional circuit blocks, a first clock-gating circuit is configured to provide a first delay to its respectively received clock signal and a second clock-gating circuit is configured to provide a second delay different from the first to its respectively received clock signal.