Patent ID: 9244850
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. A method for reducing instruction cache duplication for frequently fetched instructions, a caching system having a first instruction cache and a second instruction cache, the caching system coupled to a computer instruction fetch unit, the method comprising: receiving, by the caching system from the computer instruction fetch unit, an instruction address; based on the received instruction address resulting in a cache miss in both the first instruction cache and the second instruction cache: based on the received instruction address resulting in a cache miss in the second instruction cache and resulting in a cache hit in the first instruction cache: based on the received instruction address resulting in a cache hit in the second instruction cache, retrieving, by the caching system, the instruction associated with the received instruction address from the second instruction cache; and returning, by the caching system, the retrieved instruction to the instruction fetch unit.