Patent ID: 9530486
Filing Date: 2016-12-27
CPC Classification: G11C

Claim Text:
1. An article of manufacture comprising a memory array comprising: first and second bit lines; at least one cell coupled to the first and second bit lines, wherein a bit value stored in the cell is detectable by sensing a voltage difference developed between the first and second bit lines during a read operation; a first signal-development circuit coupled to the first bit line to accelerate draining the first bit line of charge during the read operation if a first bit value is stored in the cell; and a second signal-development circuit coupled to the second bit line to accelerate draining the second bit line of charge during the read operation if a second bit value, different from the first value, is stored in the cell, wherein each signal-development circuit comprises: a p-type device comprising a gate coupled to the corresponding bit line and a source coupled to a voltage supply; and an n-type device comprising a gate coupled to the drain of the p-type device, a source coupled to a ground, and a drain coupled to the corresponding bit line.