Patent ID: 9298668
Filing Date: 2016-03-29
CPC Classification: G06F,H04B,H04L,Y02D

Claim Text:
1. A bit error rate reduction buffer comprising: a data recovery circuit including differential bit pair inputs and differential bit pair outputs; a cyclic redundancy check (CRC) circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator; and a serializer including differential bit pair inputs and differential bit pair outputs; the differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit; and the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer; the differential bit pair inputs of the data recovery circuit to be driven by a first high speed serial (HSS) link; the different bit pair outputs of the serializer to drive a second HSS link; and the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit.