Patent ID: 9274171
Filing Date: 2016-03-01
CPC Classification: G01R

Claim Text:
1. An integrated circuit structure comprising: a plurality of combined latch structures, wherein each of the combined latch structures comprises a first input configured to receive data on a first scan path comprising an original latch and a second input configured to receive data on a second scan path comprising a redundant latch; and a plurality of combined logic structures, wherein each of the combined logic structures comprises a first input configured to receive data on the first scan path comprising an original logic structure and a second input configured to receive data on the second scan path comprising a redundant logic structure, wherein each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure, wherein the each of the combined latch structures is configured to provide an output indicative of whether at least one of the original latch and the redundant latch is not defective in response to a test scan of the combined latch structures, and wherein each of the combined logic structures is configured to provide an output indicative of whether at least one of the original logic structure and the redundant logic structure is not defective in response to a logic test which is performed only if all of the combined latch structures pass the test scan.