Patent ID: 9489326
Filing Date: 2016-11-08
CPC Classification: G06F,G11C,H03K

Claim Text:
1. An integrated circuit device, comprising: a first integrated circuit (IC) portion having a memory array configured to store data units at respective storage locations, and burst access circuitry configured to sequentially access, through a single burst access, N related storage locations within the memory array, wherein N>1, the N related storage locations within the memory array comprise related addressed that are addressable based on a single base address, wherein the burst access circuitry is configured to sequentially access the N related storage locations and transfer the respective data unit at the respective storage location to a second IC portion responsive to the single base address in the single burst access; and the second IC portion comprising a plurality of burst access registers coupled to the burst access circuitry, each burst access register having register locations to store at least N data units of the N related storage locations, and coupled to a corresponding port, of a plurality of ports of the second IC, by a single data unit access path, wherein a data bandwidth between the first IC portion and the second IC portion is greater than a sum of maximum data bandwidths of the plurality of ports, and wherein a first data transfer between one of the plurality of burst access registers and the first IC portion is according to the single burst access the respective ones of the data units corresponding to the N related storage locations within the memory array and a second data transfer between the one burst access register and at least one of the plurality of ports of the second IC portion is according to non-burst access of the respective one of the at least N data units stored in the one burst access register.