Patent ID: 9310435
Filing Date: 2016-04-12
CPC Classification: G01R

Claim Text:
1. A scan flip-flop, comprising: a data input terminal coupled to a data signal; a scan input terminal coupled to a scan input signal; an internal circuit comprising a first internal input terminal, capable of latching an internal signal received via the first internal input terminal in response to a clock; a first transistor comprising a first gate, a first source and a first drain; and a plurality of second transistors, each of the plurality of second transistors comprising a second gate, a second source and a second drain; and a third transistor comprising a third gate, a third source and a third drain, the third source and the third drain being coupled between the first internal input terminal and the data input terminal, and the third gate being coupled to a second enabling signal; wherein the second sources and the second drains of the plurality of second transistors, and the first source and the first drain, are serially coupled between a first voltage and the first internal input terminal, the first gate is coupled to the scan input terminal, and the second gates of the plurality of second transistors are commonly coupled to a first enabling signal, and wherein the second enabling signal and the first enabling signal are of opposite phases.