Patent ID: 9239704
Filing Date: 2016-01-19
CPC Classification: G06F,H03M

Claim Text:
1. A low-density parity check min-sum decoder including a variable node processing unit comprising: N+1 inputs, a first bank of N+1 two-input adders, each having an associated output, at least one of the N+1 inputs going to more than two of the adders of the first bank, a second bank of N two-input adders, the first bank and the second bank having no adders in common, at least one of the adders of the first bank providing its associated output to more than one adder of the second bank, the banks of adders disposed in series, a sign module for outputting a sign value produced from one of the inputs and an output from one of the adders of the second bank, and N+1 outputs, where one of the outputs is the sign value.