Patent ID: 9280455
Filing Date: 2016-03-08
CPC Classification: G06F,G11C

Claim Text:
1. A memory control device, comprising: a write control unit configured to control writing of write-data to a collection of memory cells by designating write targets in units of memory blocks, where each memory block includes a plurality of the memory cells, and to: a write driver unit configured to write the write-data by driving bit lines of the memory cells based on the write control unit's designations of the write targets; a verifying unit configured to read read-data from the memory cells and to indicate, on a cell-by-cell basis, whether or not the read-data matches the write-data; and a retry inhibiting unit configured to inhibit the write-retry process, on a cell-by-cell basis, for those of the memory cells in which the read-data matches the write-data.