Patent ID: 9366725
Filing Date: 2016-06-14
CPC Classification: G01R,H03K

Claim Text:
1. A two-input multiplexer circuit, comprising: a first CMOS inverter having an input terminal for receiving a select signal and an output terminal for generating an inverted select signal; a second CMOS inverter having an input terminal for receiving a first input signal and an output terminal for generating an inverted first input signal; a transmission gate having a first input terminal for receiving the select signal, a second input terminal connected to the output terminal of the second CMOS inverter for receiving the inverted first input signal, a third input terminal connected to the output terminal of the first CMOS inverter for receiving the inverted select signal, and an output terminal for outputting the inverted first input signal; a tri-state inverter having a first input terminal for receiving a second input signal, a second input terminal connected to the output terminal of the first CMOS inverter for receiving the inverted select signal, a third input terminal for receiving the select signal, and an output terminal for generating an inverted second input signal; and a third CMOS inverter, having an input terminal connected to the output terminals of the transmission gate and the tri-state inverter for receiving at least one of the inverted first and second input signals, respectively, and an output terminal for outputting at least one of the first and second input signals.