Patent ID: 9443585
Filing Date: 2016-09-13
CPC Classification: G11C

Claim Text:
1. A resistance change memory comprising: a first memory cell including a resistance change element; a word line coupled to the first memory cell; a first bit line coupled to the first memory cell; a sense amplifier which reads data from the first memory cell, the sense amplifier including a first inverter, a second inverter, and a first transistor, the first transistor being electrically coupled between each of output terminals of the first and second inverters and a first voltage source, and the first transistor having one of a conduction state and a cutoff state according to a first signal supplied to a gate of the first transistor; a second transistor electrically coupled between the first bit line and the sense amplifier, the second transistor having one of the conduction state and the cutoff state according to a second signal supplied to a gate of the second transistor; a third transistor electrically coupled between the second transistor and the sense amplifier, the third transistor having one of the conduction state and the cutoff state according to a third signal supplied to a gate of the third transistor; a fourth transistor electrically coupled between the word line and the first memory cell, the fourth transistor having one of the conduction state and the cutoff state according to a fourth signal supplied to the word line; and a fifth transistor, wherein when one of the second transistor and the fourth transistor has the cutoff state, the first transistor and the third transistor have the cutoff state, and wherein the fifth transistor has the cutoff state in which a read current of the first memory cell is interrupted.