Patent ID: 9418899
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a silicon (Si) fin; forming a n-type field effect transistor (nFET) replacement metal gate (RMG) trench and a p-type FET (pFET) RMG trench, each over and perpendicular to the Si fin, the nFET and pFET RMG trenches being laterally separated; forming a first titanium (Ti) layer in the nFET and pFET RMG trenches; implanting nitrogen gas (N annealing the N stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting aluminum (Al) or carbon (C) in the second Ti layer vertically at a 0° implant angle; annealing the Al or C implanted second Ti layer to form titanium aluminide (TiAl) or titanium carbide (TiC) at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or tungsten (W).