Patent ID: 9330224
Filing Date: 2016-05-03
CPC Classification: G06F,Y02P

Claim Text:
1. A method for manipulating a circuit design comprising: receiving a plurality of dummy cell modification parameters; selecting, by a computer processor and based on the plurality of dummy cell modification parameters, a dummy cell insertion region on the circuit design; generating, in the dummy cell insertion region, a plurality of dummy cells; selecting a first dummy cell from the plurality of dummy cells; determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell; removing, by the computer processor in response to determining the illegal overlap and from the plurality of dummy cells, the first dummy cell; inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the plurality of dummy cells to obtain a modified circuit design; and presenting the modified circuit design to manufacture a semiconductor wafer, wherein device degradation is reduced during manufacturing of the semiconductor wafer.