Patent ID: 9525069
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method for fabricating a FinFET device, the method comprising: forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and to form a semiconductor layer gap in between the fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate region; and fabricating a high-k dielectric metal gate structure overlaying the plurality of fin structures in the gate region.