Patent ID: 9256504
Filing Date: 2016-02-09
CPC Classification: G01R,G06F

Claim Text:
1. A semiconductor integrated circuit, comprising: a state machine configured to generate a next state based on a current state and an external input, and to output a state signal indicating the current state; a test circuit configured to perform a test of the state machine in a test mode; a monitoring circuit configured to monitor, in a normal operation mode, whether or not a state of the state machine is a first state based on the state signal; and a detection circuit configured to detect, in the test mode, a transition request signal requesting a transition of the state of the state machine from the first state to a second state, wherein when the monitoring circuit decides that the state of the state machine is the first state in the normal operation mode, a mode transfers from the normal operation mode to the test mode, the test circuit performs the test of the state machine, and the state machine continues to output information indicating the first state by the state signal regardless of the state of the state machine in the test mode, and when the detection circuit detects the transition request signal in the test mode, the mode transfers from the test mode to the normal operation mode, the test circuit stops the test of the state machine.