Patent ID: 9269792
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming at least one sacrificial gate structure over a portion of at least one semiconductor fin formed on a substrate, the at least one sacrificial gate structure comprising a sacrificial gate material and at least one hard mask atop the sacrificial gate material; forming an interlevel dielectric (ILD) layer over the at least one sacrificial gate structure, the at least one semiconductor fin and the substrate; recessing the ILD layer to expose the at least one hard mask and a top portion of the sacrificial gate material; forming a first gate spacer on sidewalls of the at least one hard mask and the top portion of the sacrificial gate material; removing a remaining portion of the ILD layer to expose a remaining portion of the sacrificial gate material; and forming a second gate spacer on sidewalls of the remaining portion of the sacrificial gate material.