Patent ID: 9292651
Filing Date: 2016-03-22
CPC Classification: G06F

Claim Text:
1. A method of physical design of an integrated circuit (IC) using an electronic design automation (EDA) tool, wherein the EDA tool includes a processor and a memory coupled to the processor, wherein a circuit design of the IC is stored in the memory, the method comprising: analyzing the circuit design stored in the memory with the processor to identify elements of the circuit design that have excess positive timing slack; creating a timing slack partition, using the processor, and placing the identified elements in the timing slack partition such that the identified elements are separated from other elements of the circuit design, wherein the timing slack partition is a hard partition having physical boundaries and is placed and routed independent of the rest of the circuit design; modifying parameters of characteristics of the identified elements to reduce their excess timing slack; and saving circuit design with the timing slack partition and modified parameters in the memory as a revised circuit design.