Patent ID: 9324818
Filing Date: 2016-04-26
CPC Classification: B82Y,H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate formed of a first crystalline semiconductor material; forming a plurality of shallow trench isolation (STI) regions in the semiconductor substrate; forming a plurality of semiconductor fins interposed between a pair of adjacent STI regions and extending in a first lateral direction, each of the semiconductor fins comprising a second crystalline semiconductor material lattice mismatched to the first crystalline semiconductor material, each semiconductor fin being separated from an adjacent fin by one of the STI regions; providing at least one nanostructure formed of a third crystalline semiconductor material on the second crystalline semiconductor material of each semiconductor fin, the at least one nanostructure extending in the first lateral direction; providing a sacrificial gate on the at least one nanostructure; providing on the at least one nanostructure a source region and a drain region separated in the first lateral direction from the source region by the sacrificial gate; removing the sacrificial gate and further removing the second crystalline semiconductor material, thereby suspending the at least one nanostructure being anchored by the source and drain region; and providing a final gate stack surrounding the at least one nanostructure after removing the second crystalline semiconductor material.