Patent ID: 9385032
Filing Date: 2016-07-05
CPC Classification: G06F,G11C,H01L,Y02D

Claim Text:
1. A memory device comprising: a memory core; input circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer; at least one memory circuit that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output, wherein the memory device stores and processes the DBI bit on an internal data bus as a regular data bit; and a data buffering circuit coupled to the memory core, the data buffering circuit including a write buffer comprising a data register positioned between the input circuitry and the DBI logic and storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the DBI logic when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the DBI logic.