Patent ID: 9443723
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A method of producing an integrated circuit comprising: forming an insulating layer overlying a substrate, wherein the insulating layer comprises a first composition, wherein the first composition comprises silicon oxide and a porogen; forming a via in the insulating layer; removing the porogen from the first composition to form a second composition comprising a pore, wherein the second composition has a dielectric constant lower than that of the first composition; determining an insulating layer mechanical property desired range, wherein the second composition has a mechanical property outside of the insulating layer mechanical property desired range; altering the second composition to form a third composition, wherein the third composition has the mechanical property within the insulating layer mechanical property desired range; and forming a contact within the via, wherein the contact is formed before altering the second composition to form the third composition.