Patent ID: 9293459
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a plurality of semiconductor fins located on a region of a substrate; at least one gate structure overlying a channel portion of each of the plurality of semiconductor fins; an epitaxial source region located on a first side of the at least one gate structure, the epitaxial source region merging the plurality of semiconductor fins on the first side; an epitaxial drain region located on a second side of the at least one gate structure opposite the first side, the epitaxial drain region merging the plurality of semiconductor fins on the second side; a first isolation structure located at a first end of each of the at least one gate structure, the epitaxial source region and the epitaxial drain region, wherein the first isolation structure has a sidewall abutting the first end of each of the at least one gate structure, the epitaxial source region and the epitaxial drain region; and a second isolation structure located at a second end of each of the at least one gate structure, the epitaxial source region and the epitaxial drain region opposite the first end, wherein the second isolation structure has a sidewall abutting the second end of each of the at least one gate structure, the epitaxial source region and the epitaxial drain region, wherein each of the first isolation structure and the second isolation structure has a topmost surface coplanar with a topmost surface of the at least one gate structure.