Patent ID: 9417946
Filing Date: 2016-08-16
CPC Classification: G06F

Claim Text:
1. A system in a multi-central processing unit (CPU) system, comprising: a first CPU; at least one second CPU, wherein the at least one second CPU is configured to operate in delayed lockstep configuration with the first CPU; a delay unit configured to expose at least one output signal from the first CPU to a delay; a comparator configured to detect an error by comparing the at least one output signal from the first CPU delayed by the delay unit with at least one output signal from the at least one second CPU; and an error blocking unit coupled to the delay unit and the comparator, wherein the error blocking unit receives the at least one output signal delayed by the delay unit and an error signal from the comparator having a state indicative of whether an error was detected by the comparator in the processing of the at least one output signal in the first CPU, and wherein the error blocking unit is configured to block or modify a propagation of the at least one output signal from the first CPU if the error signal indicates an error.