Patent ID: 9460816
Filing Date: 2016-10-04
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array divided into a first memory region and a second memory region, each of the first and second memory regions including a plurality of pages each page including a plurality of memory cells connected to a word line; and an error correction code (ECC) circuit configured to correct single-bit errors of the first memory region using parity bits, wherein the first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region, wherein each of the first failed page of the first memory region and the second failed page of the second memory region is replaced by a corresponding pass page in the second memory region; and wherein each of the first and second memory regions includes the same number of pages.