Patent ID: 9323692
Filing Date: 2016-04-26
CPC Classification: G06F

Claim Text:
1. A system for managing memory translations, comprising: a processor, coupled with a memory, and configured to perform the actions of: responsive to a current context with a particular process currently in control of the processor requesting access to a shared address space, setting a process identifier field in a virtual address to be looked up in a translation lookaside buffer to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space; and responsive to comparing the virtual address for the current context to a particular entry of at least one entry within the translation lookaside buffer comprising the at least one entry stored for a previous translation of a previous virtual address, only indicating a match between the process identifier field and a translation process identifier field within the particular entry of the translation lookaside buffer if the translation process identifier field is also set to the clamped value.