Patent ID: 9406770
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: providing a substrate including a transistor area and a resistor area; forming active gate structures on the substrate in the transistor area; forming dummy gate structures on the substrate in the resistor area; forming a lower interlayer insulating layer on the substrate to cover side walls of the active gate structures and the dummy gate structures; forming a resistor structure comprising a buffer insulating pattern, a resistor element, and an etch-retard pattern stacked sequentially on the dummy gate structures and the lower interlayer insulating layer in the resistor area; forming an intermediate interlayer insulating layer on the lower interlayer insulating layer to cover the resistor structure; forming resistor contact structures configured to pass through the intermediate interlayer insulating layer and the etch-retard pattern, and to contact the resistor element; and forming an upper interlayer insulating layer on the intermediate interlayer insulating layer and the resistor contact structures.