Patent ID: 9293216
Filing Date: 2016-03-22
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor device comprising: a semiconductor memory in which data erasure is performed in units of blocks; a block management memory that stores, corresponding to each of the blocks, an erasure count data piece representing a data erasure count performed in the block; a read address generation circuit that generates a read address signal in response to a search start instruction and provides the read address signal to the block management memory to successively read the erasure count data pieces from the block management memory; and a minimum erasure count search circuit that searches for a block corresponding to an erasure count data piece representing a minimum erasure count from among the erasure count data pieces read from the block management memory, the minimum erasure count search circuit including: a first latch that outputs, when the erasure count data piece read from the block management memory represents an erasure count smaller than a minimum erasure count data piece, the erasure count data piece as the minimum erasure count data piece; and a second latch that outputs, when the erasure count data piece read from the block management memory represents an erasure count smaller than the minimum erasure count data piece, an address indicated by the read address signal as a minimum erasure count address.