Patent ID: 9503124
Filing Date: 2016-11-22
CPC Classification: H03M

Claim Text:
1. A method of decoding a low-density parity-check code (LDPC) by a processor in an apparatus for performing the same, comprising: an initialization process of initializing a plurality of check nodes and a plurality of variable nodes by initializing check-variable messages and variable-check messages, both of which are for calculating the check nodes and the variable nodes, a check node update process of updating the check nodes using the variable-check messages, a variable node update process of updating the variable nodes using initial values of the variable-check messages and the check-variable messages, a tentative decoding process of performing tentative decoding using the initial values of the variable-check messages and the check-variable messages, and a parity check process of determining whether a decoding stop condition is satisfied using results of the tentative decoding and a parity check matrix which represents the connectivity between the plurality of check nodes and the plurality of variable nodes, wherein: the method further comprises detecting at least one inactive variable nodes using the results of the tentative decoding and a threshold value among the variable nodes between the initialization process and the check node update process; the variable node update process is performed only on active variable nodes except for the inactive variable node; and the check node update process is performed only using the active variable nodes; and the method is implemented as a computer readable code in a data storage device.