Patent ID: 9529042
Filing Date: 2016-12-27
CPC Classification: G01R,G05B

Claim Text:
1. A device for estimating an error point in a logic diagram including arithmetic elements that perform arithmetic operations and a signal line connecting said arithmetic elements, the device comprising: a logic diagram storage that stores said logic diagram; a test table storage that stores a test table as a correspondence table of an input value and an output value to each test, for determining whether said logic diagram is correct or incorrect; a signal line correctness/incorrectness determining unit that determines for said each test whether each signal line in said logic diagram is correct or incorrect based on a signal line status value of said each signal line and said test table, said signal line status value being acquired for said each test by conducting said each test in said test table on said logic diagram; a signal line correctness/incorrectness result summarizing unit that calculates a correctness/incorrectness result summarized value of said each signal line based on a result of determination about the correctness or incorrectness of said each signal line given by said signal line correctness/incorrectness determining unit; an error signal line estimating unit that estimates an error in said each signal line based on said correctness/incorrectness result summarized value of said each signal line calculated by said signal line correctness/incorrectness result summarizing unit; and a display that displays said each signal line in said logic diagram in a display style responsive to said error in said each signal line estimated by said error signal line estimating unit; wherein said signal line correctness/incorrectness determining unit includes a signal line tracking unit that tracks said signal line from an output side toward an input side of said logic diagram based on said signal line status value of said each signal line, said output value in said test table, and a tracking rule determined for each type of said arithmetic elements in said logic diagram, wherein said signal line correctness/incorrectness determining unit determines whether said each signal line in said logic diagram is correct or incorrect based on a result of tracking by said signal line tracking unit.