Patent ID: 9298237
Filing Date: 2016-03-29
CPC Classification: G06F,Y02D

Claim Text:
1. A method performed by a circuit for scaling voltage, the method comprising: receiving an instruction to scale a system supply voltage to a target supply voltage; placing a processor into a sleep mode, where the sleep mode halts a clock of the processor; receiving, at a first input of a logic gate, an indication that the processor is in the sleep mode; receiving, at a second input of the logic gate, an output of a register that is configured to be in a first state upon receipt of the instruction to scale the system supply voltage to the target supply voltage; setting an output of the logic gate to a first value in response to receiving the indication that the processor is in the sleep mode and receiving the output of the register in the first state; based on setting the output of the logic gate to the first value, providing a signal to a voltage regulator to scale the system supply voltage to the target supply voltage; scaling the system supply voltage to the target supply voltage using the voltage regulator upon providing the signal to the voltage regulator; and in response to the scaling, waking up the processor from the sleep mode with an interrupt signal, where the interrupt signal is sent by the voltage regulator when the system supply voltage has reached the target supply voltage.