Patent ID: 9473081
Filing Date: 2016-10-18
CPC Classification: H03F,H03G

Claim Text:
1. A circuit comprising: a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage; and a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage, wherein a first gain of the first power amplifier stage decreases when the time-varying power supply voltage is in a first low voltage range, and wherein a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range, and wherein the output of the first power amplifier stage is coupled to the output of the second power amplifier stage in a shunt configuration.