Patent ID: 9299675
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a semiconductor die having opposing first and second main surfaces, wherein the second main surface includes a plurality of pads for communication with internal circuitry of the semiconductor die; at least one stud bump formed on one of the pads on the second main surface of the semiconductor die; at least one die conductive member electrically coupled to the at least one stud bump; at least one grid array conductive member electrically coupled to the at least one die conductive member; an encapsulation material encapsulating the semiconductor die, the at least one stud bump, and the at least one die conductive member, wherein at least a portion of the at least one grid array conductive member is exposed through the encapsulation material; and a solder ball electrically coupled to the at least one grid array conductive member.