Patent ID: 9520166
Filing Date: 2016-12-13
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: a memory cell array including, a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively, such that a first potential difference is applied to a selected variable resistance element disposed at the intersection of the selected first line and the selected second line, the control circuit including a detection circuit configured to, during the setting operation, detect a transition of a resistance state of the selected variable resistance element using a reference voltage, and the control circuit being configured to, before the setting operation, execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line during the read operation.