Patent ID: 9337259
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a wafer including a plurality of regions comprising at least a first semiconductor layer overlying a buried oxide layer overlying a second semiconductor layer, separated by at least one shallow trench isolation extending through the first semiconductor layer, through the buried oxide layer, and partially into the second semiconductor layer and containing a first dielectric, wherein the first dielectric is partially removed so as to create a divot at a side of the shallow trench isolation; a gate structure formed directly over the first semiconductor layer such that the divot extends into the first dielectric of the at least one shallow trench isolation so as to expose sidewalls of the first semiconductor layer, the buried oxide layer, and the second semiconductor layer; a second dielectric deposited uniformly over the semiconductor device, including the divot; a hole etched adjacent and parallel to the gate structure into the second dielectric, wherein the hole is not fully landed and extends at least partially into the at least one shallow trench isolation so as to re-expose at least a portion of the divot; an insulating material that fills the hole and extends into the divot, from the top of the second semiconductor layer extending down to the first dielectric material, wherein the insulating material has physical properties that allow it to be etched selective to the second dielectric in the hole, and wherein the insulating material completely fills the exposed portion of the divot to the first semiconductor layer; and a metal material filling the rest of the hole.