Patent ID: 9412458
Filing Date: 2016-08-09
CPC Classification: G11C

Claim Text:
1. A method for carrying out an erase operation in a semiconductor memory device that includes: a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to one terminal of the first memory string and one terminal of the second memory string; a plurality of word lines connected to the plurality of memory strings; and a controller configured to control the erase operation of the memory block, the method comprising: applying, by the controller, a first erase voltage to the plurality of word lines; selecting, by the controller, the first memory string; applying, by the controller, an erase verify voltage to the plurality of word lines and reading data of the first memory string; when the first memory string passes the erase verify, selecting, by the controller, the second memory string without first discharging the plurality of word lines; and when the first memory string fails the erase verify, discharging, by the controller, the plurality of word lines and repeating, by the controller, the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a first number.