Patent ID: 9337312
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a TFT, comprising a step of forming a pattern of source/drain electrode, a pattern of doped semiconductor layer, and a pattern of semiconductor layer, wherein the step of forming the pattern of source/drain electrode, the pattern of doped semiconductor layer, and the pattern of semiconductor layer comprises: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially, the first patterned photoresist layer covering a region of the pattern of source/drain electrode and a channel region; performing first etching so as to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer; performing second etching so as to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer, thereby forming the pattern of semiconductor layer; performing ashing treatment on the photoresist layer so as to remove the photoresist layer on the channel region; hard-baking the photoresist layer after the ashing treatment; performing third etching so as to remove the source/drain electrode film on a region that is not covered by the photoresist layer after the ashing treatment, thereby forming the pattern of source/drain electrode; and performing fourth etching so as to remove the doped semiconductor film on the region that is not covered by the photoresist layer after the ashing treatment, thereby forming the pattern of doped semiconductor layer.