Patent ID: 9508797
Filing Date: 2016-11-29
CPC Classification: H01L

Claim Text:
1. A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged as an array with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer; a plurality of gate strip electrodes formed on the nitride semiconductor layer in active regions between adjacent source island electrodes and drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump, ball or post connection formed thereon; each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump, ball or post connection formed thereon; the low resistance gate interconnect being connected to a plurality of gate pads; and wherein, in defective active regions, individual gate strip electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.