Patent ID: 9431095
Filing Date: 2016-08-30
CPC Classification: G11C

Claim Text:
1. A memory circuit, comprising: an input stage comprising N input ports and N output ports, wherein N is an integer greater than one; an N:1 port multiplexer coupled to the N output ports of the input stage and configured to time division multiplex the N output ports to one multiplexed port; a random access memory matrix coupled to the multiplexed port; and a 1:N port multiplexer coupled to the random access memory matrix and comprising N output ports, wherein the 1:N port multiplexer is configured to de-multiplex signals from the random access memory matrix into the N output ports of the 1:N port multiplexer; and wherein the input stage comprises: address decoder circuitry coupled to the N input ports of the input stage; wherein the address decoder circuitry is configured to decode a portion of an address for each of the N input ports of the input stage and generate an enable signal for each of the N output ports of the input stage.