Patent ID: 9251741
Filing Date: 2016-02-02
CPC Classification: G09G

Claim Text:
1. A display device comprising: a display area in which a plurality of pixels, a plurality of gate signal lines, and a plurality of source signal lines divided into N groups are arranged in a matrix, N being a natural number, each of the plurality of pixels including a transistor and a display element being sandwiched between a pixel electrode and a common electrode and having memory properties; a scan line driver circuit configured to control a timing of selecting any one of the plurality of gate signal lines; and a signal line driver circuit configured to control, in a period during which the scan line driver circuit selects any one of the plurality of gate signal lines, a timing of outputting a first signal to the source signal lines in the second to N-th groups and concurrently outputting a second signal simultaneously to all of the source signal lines in the first group, and then outputting the second signal simultaneously to the source signal lines in each of the second to N-th groups, sequentially group by group, wherein a first terminal of the transistor is electrically connected to any one of the plurality of source signal lines, wherein a second terminal of the transistor is electrically connected to the pixel electrode, and wherein a gate of the transistor is electrically connected to any one of the plurality of gate signal lines.