Patent ID: 9379197
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A recess array device, comprising: a semiconductor substrate; at least an active area in a main surface of the semiconductor substrate; a trench isolation surrounding the active area in the main surface of the semiconductor substrate; at least one gate trench extending into the semiconductor substrate, wherein the gate trench includes a first sidewall, a second sidewall facing the first sidewall, and a bottom surface extending between the first sidewall and the second sidewall; a bump portion of the semiconductor substrate protruding from a bottom surface of the gate trench, wherein the bump portion has two opposite sidewalls and a top portion extending between the two opposite sidewalls, wherein the bottom surface includes surface of the top portion and surfaces of the two opposite sidewalls; a gate oxide layer on the first sidewall, the second sidewall, and the bottom surface of the gate trench, wherein the gate oxide layer has a first thickness on the first and second sidewalls, a second thickness on the two opposite sidewalls of the bump portion, and a third thickness on the top portion of the bump portion, wherein the first thickness is greater than the second thickness, and the second thickness is greater than the third thickness; and a recess gate disposed within the gate trench.