Patent ID: 9461598
Filing Date: 2016-10-04
CPC Classification: H03F

Claim Text:
1. A power amplifier, comprising: a clamping circuit configured to provide a clamped voltage from a power supply at a supply voltage rejection node; a biasing circuit comprising a differential buffer circuit having a first input coupled to receive a first voltage derived from the clamped voltage and a second input coupled to receive a second voltage derived from the clamped voltage, said differential buffer circuit having an output generating a bias voltage; and an amplifier pair having a first plurality of inputs coupled to the clamped voltage at the clamping circuit, an output for providing an amplified signal, and a second plurality of inputs; and wherein the bias voltage generated at the output of the differential buffer circuit is coupled to the second plurality of inputs of the amplifier pair to adjust input bias voltages of the amplifier pair such that the output of the amplifier pair varies proportionally to a change of the power supply.