Patent ID: 9304573
Filing Date: 2016-04-05
CPC Classification: G06F,Y02D

Claim Text:
1. An apparatus comprising: a plurality of processors; a power control circuit coupled to the plurality of processors, wherein the power control unit is programmable with data describing a plurality of operating points for the plurality of processors, and wherein the data further includes an indication for each respective operating point of the plurality of operating points indicating a limit to a first number of active processors in the plurality of processors at the respective operating point, wherein exceeding the limit of active processors at the respective operating point would exceed a capability of a power management unit that provides power to the plurality of processors when the active processors are consuming a maximum amount of power, and wherein the power control circuit is configured to detect that a second number of processors to be active exceeds the limit for a selected operating point and to override the selected operating point with a second operating point responsive to the detecting.