Patent ID: 9443613
Filing Date: 2016-09-13
CPC Classification: G11C

Claim Text:
1. An apparatus comprising: a processor; a memory that stores code executable by the processor, the code comprising: code that identifies an unreserved amount of a main memory; code that requests a portion of the main memory based on the unreserved amount; code that determines whether an allocated portion of the main memory includes non-contiguous memory addresses; code that identifies an address space based on the allocated portion of the main memory, the allocated portion comprising a plurality of blocks of memory addresses; code that performs, at least three times, a memory test procedure on the address space using a block pattern, wherein a first block pattern is used the first time, a second block pattern is used the second time, and a third block pattern is used the third time; and code that determines the presence of a memory fault based on results of the memory test procedures.