Patent ID: 9368213
Filing Date: 2016-06-14
CPC Classification: G11C,H01L

Claim Text:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array including a first block and a second block, the first block including a first memory string, the first memory string including a first selection transistor and a plurality of first memory cells connected in series, the second block including a second memory string, the second memory string including a second selection transistor and a plurality of second memory cells connected in series; a plurality of first transfer transistors connected to gates of the plurality of first memory cells and a gate of the first selection transistor; a plurality of second transfer transistors connected to gates of the plurality of second memory cells and a gate of the second selection transistor; a third transfer transistor having a first end connected to an end of one of the first transfer transistors and the gate of the first selection transistor; a fourth transfer transistor having a first end connected to an end of one of the second transfer transistors and the gate of the second selection transistor; and a first block decoder configured to output a first selection signal to gates of the first and second transfer transistors and a first non-selection signal to gates of the third and fourth transfer transistors, a first output of the first block decoder being connected to the gates of the first and second transfer transistors and a second output of the first block decoder being connected to the gates of the third and fourth transfer transistors.