Patent ID: 9420695
Filing Date: 2016-08-16
CPC Classification: H01L,H05K

Claim Text:
1. A semiconductor package structure comprising: a first dielectric layer having a first surface and a second surface opposite the first surface; a second dielectric layer having a first surface and a second surface opposite the first surface, the second surface of the first dielectric layer being attached to the first surface of the second dielectric layer; a component within the second dielectric layer comprising at least two electrical contacts, the electrical contacts being adjacent to the second surface of the first dielectric layer; a first patterned conductive layer within the first dielectric layer and adjacent to the first surface of the first dielectric layer; at least two first conductive vias penetrating the first dielectric layer and electrically connecting the electrical contacts with the first patterned conductive layer; a second conductive via formed in the first dielectric layer, the second conductive via having a top surface and a bottom surface, the second conductive via tapering from the top surface to the bottom surface so that a width of the top surface is greater than a width of the bottom surface; and a third conductive via formed in the second dielectric layer, the third conductive via having a top surface and a bottom surface, the third conductive via tapering from the bottom surface to the top surface so that a width of the top surface is less than a width of the bottom surface, the top surface of the third conductive via being joined to the bottom surface of the second conductive via, wherein a height of the third conductive via is greater than a height of the second conductive via.