Patent ID: 9407296
Filing Date: 2016-08-02
CPC Classification: H03G,H04B

Claim Text:
1. A current buffer used in a receiver arrangement comprising: a direct path mode that includes a plurality of first set of transistors and a plurality of first set of current sources that are turned on while all remaining transistors and current sources are turned off, during the direct path mode a current signal at an input node directly appears at an output node; and a mirror path mode that includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on; wherein the current signal at the input node goes through a current mirror pair and appears at the output node with a gain that is controlled by slicing one of the transistors of the current mirror pair and a second current source allowing more than one gain in the mirror path mode.