Patent ID: 9274169
Filing Date: 2016-03-01
CPC Classification: G01R,G06F

Claim Text:
1. A system to asynchronously debug a core logic, the core logic comprising a central processing unit, a bus, and a functional clock, the system comprising: an intelligence unit comprising a test program executed by a joint test action group-compliant (JTAG compliant) debugger, the JTAG compliant debugger to operate with a JTAG-compliant test access port (TAP) controller using a test clock, the test program to be run on the core logic through a JTAG interface in real time; a read interface to read from a register, a memory location, or an input/output (I/O) port of the core logic through a side channel; a write interface to write to the register, the memory location, or the I/O port of the core logic through the side channel; and a priority arbiter to arbitrate between access to the bus of the core logic by either the intelligence unit or circuitry within the core logic; wherein a predetermined number of idle states is sent to the core logic by the test program using the JTAG interface in between succeeding write operations to or read operations from the register, the memory location, or the I/O port of the core logic, wherein the succeeding write operations to or read operations from are taking place through the side channel.