Patent ID: 9299712
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor wafer to form a memory area and a logic area, the memory area comprising nonvolatile memory devices comprising floating gate transistors, the logic area comprising field effect transistors, the method comprising: separating the semiconductor wafer into memory and logic areas; forming a first gate dielectric region over the memory area; forming a second gate dielectric region over the logic area; depositing and patterning a conducting material, wherein the conducting material forms a gate electrode over the logic areas and a floating gate electrode over the memory areas; doping to form source regions, drain regions, and channel regions; and forming a metallization region over the floating gate electrode, wherein the metallization region capacitively couples a control gate node to the floating gate electrode of the floating gate transistors, wherein forming the metallization region comprises forming a first metal feature and a second metal feature embedded in an insulating dielectric region, wherein the first metal feature is electrically coupled to the floating gate electrode and the second metal feature is electrically coupled to the control gate node, wherein the floating gate electrode and the first metal feature form a portion of a floating gate and the second metal feature forms a portion of a control gate of one of the floating gate transistors, wherein the control gate and floating gate form an interlocking finger structure.