Patent ID: 9379210
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A method of fabricating a transistor, the method comprising: (a) forming a plurality of dummy gate structures adjacent to a plurality of electrical contact regions for source and/or drain regions, each dummy gate structure comprising a dielectric spacer separating one of the contact regions and a dummy gate abutting the spacer; (b) forming a sacrificial pre-metal dielectric over the plurality of dummy gate structures and adjacent electrical contact regions; (c) removing the dummy gates while substantially preserving the spacers and the sacrificial pre-metal dielectric positioned over the electrical contact regions; (d) forming replacement gates where the dummy gates were located; (e) removing the sacrificial pre-metal dielectric, wherein after removing the sacrificial pre-metal dielectric, a plurality of replacement gate structures and the adjacent electrical contact regions are exposed, each of the replacement gate structures comprising a replacement gate and an associated dielectric spacer; (f) forming a contact etch stop layer over the plurality of replacement gate structures and adjacent electrical contact regions; (g) forming a replacement pre-metal dielectric over the contact etch stop layer; and (h) selectively etching through the replacement pre-metal dielectric and contact etch stop layer to expose the electrical contact regions without exposing the replacement gates.