Patent ID: 9264380
Filing Date: 2016-02-16
CPC Classification: G06F,H04L

Claim Text:
1. A processor, comprising: a plurality of processor cores; a data switch interconnect, coupled with a data cache of each of the plurality of processor cores, to move information among the plurality of processor cores, without being directly coupled to an instruction cache of at least one of the plurality of processor cores; a messaging network configured to move information between the plurality of processor cores and a plurality of communication ports, the messaging network being directly coupled with the instruction cache of the at least one of the plurality of processor cores without being directly coupled to the data cache of each of the plurality of processor cores; and a level 2 cache coupled to the data switch interconnect to share dirty cache lines across the plurality of processor cores, wherein cache coherence for the level 2 cache is maintained using a Modified, Own, Shared, Invalid (MOSI) protocol.