Patent ID: 9368481
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A semiconductor package comprising: a first semiconductor chip including: a first substrate having a first surface and a second surface that are opposite to each other; a plurality of first through electrodes penetrating the first substrate and being spaced apart from each other; a plurality of first front-side bumps disposed on the first surface of the first substrate and connected to first odd-numbered through electrodes among the first through electrodes; a plurality of first backside bumps disposed on the second surface of the first substrate and connected to first even-numbered through electrodes among the first through electrodes; and a second semiconductor chip including: a second substrate having a first surface and a second surface that are opposite to each other; a plurality of second through electrodes penetrating the second substrate and being spaced apart from each other; a plurality of second front-side bumps disposed on the first surface of the second substrate and connected to second odd-numbered through electrodes among the second through electrodes; and a plurality of second backside bumps disposed on the second surface of the second substrate and connected to second even-numbered through electrodes among the second through electrodes, wherein the first and second semiconductor chips are combined with each other so that the first surface of the first substrate faces the second surface of the second substrate.