Patent ID: 9379217
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A device comprising: a semiconductor substrate; isolation regions at a surface of the semiconductor substrate; a plurality of semiconductor strips comprising a first, a second, and a third semiconductor strip between the isolation regions and parallel to each other, wherein the second semiconductor strip is between the first and the third semiconductor strips; a first semiconductor fin over and joined to the second semiconductor strip; a gate dielectric on sidewalls of the first semiconductor fin, wherein the gate dielectric is directly on the first and the third semiconductor strips and the gate dielectric bottom surface is substantially level with a top surface of the isolation regions as the gate dielectric crosses over the first and third semiconductor strips; a gate electrode over the gate dielectric, wherein the gate dielectric and the gate electrode form portions of a Fin Field-Effect Transistor (FinFET); and a source/drain region aligned with and extending continuously over the first, the second, and the third semiconductor strips.