Patent ID: 9524962
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device comprising the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein: forming said transistor comprises forming a dummy gate above a substrate, removing said dummy gate and forming a metal gate in place of said dummy gate above said substrate; and forming said e-fuse comprises forming a metal-containing layer above said isolation region, forming a semiconductor layer on said metal-containing layer during the process of forming said dummy gate, the semiconductor layer being made of the same material as said dummy gate, forming a hard mask layer above and in contact with an upper surface of said semiconductor layer, forming an interlayer dielectric material above said hard mask layer, and forming contact openings extending through at least said hard mask layer and said semiconductor layer so as to thereby expose portions of said metal-containing layer, wherein said contact openings are formed through at least said hard mask layer and said semiconductor layer during the process of removing said dummy gate.