Patent ID: 9322852
Filing Date: 2016-04-26
CPC Classification: G01R,H02M,H03K

Claim Text:
1. An inverter comprising: a phase switch having an insulated gate; a complementary transistor pair adapted to receive a supply voltage and a PWM signal to alternately charge and discharge the insulated gate; a comparator comparing a voltage at the insulated gate with a reference voltage representing a gate drive fault to generate a first logic signal; a latch sampling the first logic signal when the PWM signal has a value corresponding to charging the insulated gate; a logic circuit inhibiting charging of the insulated gate when the latched logic signal indicates the gate drive fault; and a second comparator for comparing a voltage across the phase switch to a second reference voltage indicative of an On state of the phase switch, wherein the latch is triggered by the second comparator when the on state is detected.