Patent ID: 9443951
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a plurality of fin-defining mask structures over a semiconductor material layer comprising a first semiconductor material; forming a disposable gate structure and a gate spacer over a middle portion of each of said plurality of fin-defining mask structures; recessing portions of said semiconductor material layer that are not covered by said disposable gate structure or by said gate spacer; forming a first stress-generating semiconductor portion and a second stress-generating semiconductor portion on said recessed portions of said semiconductor material layer, each of said first stress-generating semiconductor portion and said second stress-generating semiconductor portion comprises a second semiconductor material that is different from said first semiconductor material; removing said disposable gate structure to form a gate cavity; and forming a plurality of semiconductor fins within said gate cavity, after removing said disposable gate structure, by etching portions of said semiconductor material layer that are not covered by said plurality of fin-defining mask structures, said gate spacer, said first stress-generating semiconductor portion and said second stress-generating semiconductor portion.