Patent ID: 9455032
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A semiconductor integrated circuit device comprising: a cell array including a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells located at interconnections of the word lines and the bit lines, wherein each memory cell includes an OTS (ovonic threshold switch) and a calcogenide material; a mode setting unit configured to set a leakage current sensing mode by applying a first voltage to the cell array, and sets a read mode by applying a second voltage to the cell array; a reference current generation unit configured to provide a reference current to an output node while in the read mode; a leakage current generation unit including a capacitor loop, and configured to generate a leakage current according to a charge amount stored in the capacitor loop and transfer the leakage current to the output node while in the leakage current sensing mode; a leakage current compensation unit configured to reflect a ratio of a voltage in the read mode to a component of the first voltage to the leakage current applied to the output node while in the read mode; and a determination circuit unit configured to compare a voltage corresponding to a comparison result between a current of the cell array and a current of the output node with a reference voltage and determine a set state or a reset state of the cell array.