Patent ID: 9431425
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: providing a structure comprising a plurality of semiconductor mandrel structures containing a nitride-containing hard mask cap and extending upward from a semiconductor substrate, wherein a first oxide isolation structure is located between each semiconductor mandrel structure and on exposed portions of said semiconductor substrate; forming a silicon germanium alloy fin on opposing sidewalls of each semiconductor mandrel structure in a pFET device region of said semiconductor substrate, wherein each silicon germanium alloy fin has a bottommost surface that directly contacts a topmost surface of one of said first oxide isolation structures; removing each nitride-containing hard mask cap and each semiconductor mandrel structure adjoining each silicon germanium alloy fin; and forming a second oxide isolation structure between each first oxide isolation structure, said second oxide isolation structure having a topmost surface coplanar with a topmost surface of each first oxide isolation structure and a bottommost surface that is deeper than a bottommost surface of each first oxide isolation structure.