Patent ID: 9261946
Filing Date: 2016-02-16
CPC Classification: G06F,Y02D

Claim Text:
1. A cache memory system comprising: a cache memory storing a plurality of data segments, wherein the data segments are compressed from a multi-block including contiguous data blocks originating from a higher level of memory; a tag, memory array coupled to the cache memory, wherein the tag memory array stores a plurality of tag addresses with each tag address corresponding to a multi-block originating from the higher level of memory; and a back pointer array coupled to the cache memory and the tag memory array, wherein the back pointer array stores a plurality of back pointer entries with each back pointer entry corresponding to a data segment in the cache memory and each back pointer entry identifying a multi-block associated with a tag address in the tag memory array and a data block of the multi-block compressed to form the data segment; wherein the data segments are stored non-contiguously in the cache memory.