Patent ID: 9449976
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A semiconductor device structure, comprising: a first-conductivity-type semiconductor substrate; a first-conductivity-type metal oxide semiconductor (MOS) region comprising: a first-conductivity-type MOS transistor; a second-conductivity-type well surrounding the first-conductivity-type MOS transistor; a first-conductivity-type deep well surrounding the second-conductivity-type well; and a second-conductivity-type deep well surrounding the first-conductivity-type deep well; a second-conductivity-type MOS region comprising: a second-conductivity-type MOS transistor; a first-conductivity-type well surrounding the second-conductivity-type MOS transistor, the first-conductivity-type well being electrically isolated from the second-conductivity-type well; and a second-conductivity-type deep well surrounding the first-conductivity-type well, and the second-conductivity-type deep well in the second-conductivity-type MOS region being separated from the second-conductivity-type deep well in the first-conductivity-type MOS region; and an isolated region separating the first-conductivity-type MOS region and the second-conductivity-type MOS region.