Patent ID: 9496267
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor, comprising: demarcating a first space portion by means of a plurality of first line patterns extending in a first direction, and a plurality of second line patterns extending over the plurality of first line patterns in a second direction which intersects the first direction; depositing a first silicon film, containing an impurity having a first concentration, to a thickness that does not fill the first space portion; depositing a second silicon film, containing an impurity having a second concentration, to a thickness that fills the first space portion and fills between the second line patterns; forming a silicon filler body by etching back the first and second silicon films in such a way as to make them lower than an upper surface of the second line pattern; forming masking films on each of the sidewalls of the second line patterns in such a way that a portion of the silicon filler body is exposed; selectively removing the silicon filler body, using the masking film as a mask, to form a first groove; filling the first groove with an isolating and insulating film; removing the masking film, a portion of the isolating and insulating film, and portions of the second line patterns in such a way that the upper surfaces of the silicon filler body that has been divided by the isolating and insulating film are exposed; and forming a second groove in the silicon filler body, and then employing heat treatment to bring the impurity concentration in the divided silicon filler body to a third concentration; and in that the first concentration is higher than the third concentration, and the second concentration is lower than the third concentration.