Patent ID: 9496269
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A static random access memory (SRAM) comprising a plurality of SRAM unit cells, each of the plurality of SRAM unit cells being defined by a cell boundary and comprising: first, second, third and fourth fin structures extending in a first direction and arranged in a second direction crossing the first direction; a first fin field effect transistor (Fin FET) formed by a first gate electrode and the first fin structure; a second Fin FET formed by a second gate electrode and the first fin structure; a third Fin FET formed by the second gate electrode and the third fin structure; a fourth Fin FET formed by a third gate electrode and the second fin structure; a fifth Fin FET formed by a fourth gate electrode and the second fin structure; a sixth Fin FET formed by the fourth gate electrode and the fourth fin structure; a first dummy fin structure located adjacent the second Fin FET, and connected by a first source/drain epitaxial layer to the first fin structure; and a second dummy fin structure located adjacent to the fifth Fin FET, and connected by a second S/D epitaxial layer to the second fin structure.