Patent ID: 9477258
Filing Date: 2016-10-25
CPC Classification: G06F

Claim Text:
1. A clock tree in a circuit, comprising: a first sub clock tree, disposed in a first function module of the circuit to transfer a first delayed clock to different components in the first function module; a second sub clock tree, disposed in a second function module of the circuit to transfer a second delayed clock to different components in the second function module; at least one first channel power-mode-aware buffer connected in series between the first sub clock tree and a system clock to delay the system clock for a first delay time to serve as the first delayed clock for providing to the first sub clock tree; at least one second channel power-mode-aware buffer connected in series between the second sub clock tree and the system clock to delay the system clock for a second delay time to serve as the second delayed clock for providing to the second sub clock tree; and a power-mode control circuit, coupled to the at least one first channel power-mode-aware buffer, the at least one second channel power-mode-aware buffer, the first function module and the second function module, the power-mode control circuit determining power modes of the first function module and the second function module through at least two first power information, and the power-mode control circuit providing at least two second power information to the at least one first channel power-mode-aware buffer and the at least one second channel power-mode-aware buffer to determine the first delay time and the second delay time.