Patent ID: 9229046
Filing Date: 2016-01-05
CPC Classification: G01R,G06F,H03K

Claim Text:
1. A semiconductor device comprising: a first flip-flop; a second flip-flop which is provided in a subsequent stage of the first flip-flop; and a malfunction pre-detecting circuit provided on a route branching off from a route to a data input terminal of the second flip-flop, the malfunction pre-detecting circuit comprising: a delay element to delay input data that is input in parallel to the data input terminal of the second flip-flop; a third flip-flop that receives output of the delay element; and a comparator that compares output of the second flip-flop and output of the third flip-flop, wherein first test data and second test data are input to the malfunction pre-detecting circuit in an operation test mode for testing operation of the malfunction pre-detecting circuit and the second test data is input to the delay element, wherein the comparator compares the first test data and output of the third flip-flop in the operation test mode, and wherein the malfunction pre-detecting circuit further comprises: