Patent ID: 9306545
Filing Date: 2016-04-05
CPC Classification: H03K

Claim Text:
1. A master-slave flip-flop circuit for generating an output signal in response to an input signal and a clock signal, the master-slave flip-flop circuit comprising: a master latch configured to capture a master signal dependent on the input signal during a first phase of the clock signal and to retain the master signal during a second phase of the clock signal; a slave latch configured to capture a slave signal dependent on the master signal during the second phase of the clock signal and to retain the slave signal during the first phase of the clock signal, wherein the output signal is dependent on the slave signal; and clock generating circuitry configured to: at least one clocked component controlled by the gated clock signal; and at least one clocked component controlled by the inverted clock signal, wherein the clock generating circuitry is further configured to generate the gated clock signal with a value dependent on the clock signal when the gating control signal has a first value, and to generate the gated clock signal with a fixed value independent of the clock signal when the gating control signal has a second value, and wherein the gating control signal is dependent on the input signal or a signal at a signal node of the master latch, and is independent of the slave signal and the output signal.