Patent ID: 9269583
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A fabricating method of a memory device, the fabricating method comprising: providing a substrate comprising a first portion and a second portion; forming a plurality of semiconductor fin structures on the substrate of the first portion, wherein each of the semiconductor fin structures extends in a first direction and comprises a first doped region and a body region on which the first doped region is disposed, and a trench is formed between two adjacent semiconductor fin structures; forming a second doped region in the substrate under the body regions of the semiconductor fin structures and the trench, wherein the second doped region extends into the substrate of the second portion; forming a plurality of word lines on the substrate, wherein each of the word lines extends in a second direction and covers a portion of a sidewall and a portion of a top of each of the semiconductor fin structures, and the second direction is different from the first direction; forming a charge storage layer between the semiconductor fin structures and the word lines; forming a plurality of first contacts on the second portion of the substrate, wherein the first contacts are arranged in the first direction and each of the first contacts is electrically connected with the second doped region; and forming a plurality of second contacts on the first portion of the substrate, wherein each of the second contacts is electrically connected with the corresponding first doped region.