Patent ID: 9257345
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A method for manufacturing an anti-fuse array of a semiconductor device comprising: forming an active region in a first-type semiconductor substrate by a device isolation region; forming a second-type first impurity implantation region in a lower portion of the active region; depositing a gate insulation film and a gate electrode over the active region; forming a spacer film over a sidewall of the gate electrode; forming second-type second and third impurity implantation regions, using the gate electrode and the spacer film as a mask, in the active region and along a sidewall of the device isolation region; and forming a first metal contact over the second impurity implantation region, wherein an upper portion of the active region includes a first-type channel region separated from the semiconductor substrate by the first, second, and third impurity implantation regions.