Patent ID: 9305883
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A finFET including a gate and a source/drain (S/D) region formed on a substrate, the gate formed over at least two fins, said at least two fins extending into said S/D region, the finFET further comprising: facing sidewalls of said at least two fins within said S/D region, first epitaxial material formed on a first of said facing sidewalls, and second epitaxial material formed on a second of said facing sidewalls, wherein each of said first epitaxial material and said second epitaxial material include a faceted upper surface sloping from the associated sidewall toward said substrate; a dielectric material disposed on said substrate between said facing sidewalls such that said dielectric material covers a lower portion of both said upper surfaces; and a bar conductively connected to an upper portion of both said upper surfaces.