Patent ID: 9330992
Filing Date: 2016-05-03
CPC Classification: H01L,H05K

Claim Text:
1. A semiconductor device, comprising: a semiconductor chip having a front surface with a plurality of electrode pads formed thereover, and a back surface opposite to the front surface; and a wiring substrate including a chip mounting surface over which the semiconductor chip is mounted, a lower mounting surface opposite to the chip mounting surface, a plurality of bonding pads mounted over the chip mounting surface and electrically coupled to the electrode pads of the semiconductor chip, a plurality of ball lands associated with the lower mounting surface, and a plurality of wiring layers electrically coupling the bonding pads to the ball lands, wherein the wiring substrate comprises: a first wiring layer including a plurality of first via wirings electrically coupled to the bonding pads, a first conductive plane provided around the first via wirings and spaced apart from the first via wirings, and a first insulating layer covering the first via wirings and the first conductive plane; a second wiring layer including a plurality of second-layer wirings electrically coupled to the first via wirings, a plurality of second via wirings electrically coupled to the second-layer wirings, a second conductive plane provided around the second-layer wirings and the second via wirings and spaced apart from the second-layer wirings and the second via wirings, and a second insulating layer covering the second-layer wirings, the second via wirings, and the second conductive plane, the second wiring layer being positioned closer to the lower mounting surface than the first wiring layer; a third wiring layer including a plurality of first through hole lands electrically coupled to the second via wirings, a third conductive plane provided around the first through hole lands and spaced apart from the first through hole lands, and a third insulating layer covering the first through hole lands and the third conductive plane, the third wiring layer being positioned closer to the lower mounting surface than the second wiring layer; and a core insulating layer including a first surface with the third wiring layer formed thereat, a second surface opposite to the first surface, a plurality of through holes extending between the first and second surfaces, and a plurality of through hole wirings covering respective inner walls of the through holes and formed integrally with the first through hole lands, wherein the second-layer wirings are sandwiched between the first conductive plane of the first wiring layer and the third conductive plane of the third wiring layer in a side view, wherein the first conductive plane of the first wiring layer is provided with a plurality of first openings, the first openings being located to be superimposed over the first through hole lands of the third wiring layer in a thickness direction, each first opening having an area thereof larger than a plane area of a corresponding one of the first through hole lands, and each first opening being entirely filled with the first insulating layer, wherein the second conductive plane of the second wiring layer is provided with a plurality of second openings, the second openings being located to be superimposed over the first openings of the first wiring layer in the thickness direction, each second opening having an area thereof larger than the plane area of a corresponding one of the first through hole lands, and wherein each of the second via wirings is formed within the corresponding first and second openings in a planar view.