Patent ID: 9412703
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A chip package structure, comprising: a main substrate having a first circuit layer including a plurality of pads; a carrier substrate having a second circuit layer and a third circuit layer, wherein the second circuit layer and third circuit layer are respectively located on two opposite surfaces of the carrier substrate, the second circuit layer has a plurality of contacts and a ground layer, and the carrier substrate is disposed over the main substrate; at least one chip disposed on the carrier substrate and electrically connected to the carrier substrate; a molding compound disposed over the carrier substrate, at least encapsulating the chip and a portion of the carrier substrate; a shielding layer disposed directly on the molding compound, wherein the shielding layer conformally covers a top surface and sidewalls of the molding compound and covers an upper sidewall portion of the carrier substrate, wherein the shielding layer is directly coupled with the third circuit layer through physical contact; and a plurality of first connection structures and a plurality of second connection structures located between the plurality of pads of the first circuit layer and the plurality of contacts of the second circuit layer, wherein the at least one chip and the carrier substrate are electrically connected to the main substrate through the plurality of first connection structures, and the shielding layer is electrically connected to and indirectly coupled with the second circuit layer of the carrier substrate through the plurality of second connection structures.