Patent ID: 9378326
Filing Date: 2016-06-28
CPC Classification: G06F

Claim Text:
1. A processing system to identify a region of a design block of an integrated circuit for redesign, the system comprising: a processor configured to divide the design block into grids, each of the grids including a respective number of logic elements, filter each of the grids based on a specified criticality criteria, the filtering including determining a total number (A) of the logic elements in each grid and a number (B) of the total number (A) of the logic elements in each grid that meet the specified criticality criteria, compute a power efficiency score (PES) for each of the total number (A) of the logic elements in each grid as: where CDS_assignment_score being based on a minimum and maximum cell drive strength (CDS) for each of the logic elements of each of the grids, VT_assignment_score being based on a threshold voltage (VT) used for the logic element, slack_achievement_score being based on slack as compared with a target slack, and slew_achievement_score being based on slew as compared with a target slew, and identify the region as a set of two or more of the grids based on a result of the filtering; and a display device configured to display the result of the filtering.