Patent ID: 9250289
Filing Date: 2016-02-02
CPC Classification: G01R,H01L,H05K,Y10T

Claim Text:
1. A method for electrical testing of a 3-D integrated circuit chip stack comprising at least a first integrated circuit chip and a second integrated circuit chip, wherein the first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing, the method comprising: placing an integrated circuit chip holder on an integrated circuit chip carrier, wherein the integrated circuit chip carrier is operable for electrically connecting the 3-D chip stack with an electronic testing system; making a first temporary electrical connection between the first integrated circuit chip and the integrated circuit chip carrier and a first temporary mechanical connection between the first integrated circuit chip and the integrated circuit chip carrier, wherein the integrated circuit chip holder is operable for making the first temporary electrical connection and the first temporary mechanical connection; making a second temporary electrical connection between the second integrated circuit chip and the first integrated circuit chip and a second temporary mechanical connection between the second integrated circuit chip and the first integrated circuit chip, wherein the integrated circuit chip holder is operable for making the second temporary electrical connection and the second temporary mechanical connection; and performing electrical testing of the 3-D integrated circuit chip stack using the electrical testing system; wherein the first temporary electrical connection and the first temporary mechanical connection are made between first solder bumps attached to a bottom surface of the first integrated circuit chip and contact pads on a top surface of the integrated circuit chip carrier; and the second temporary electrical connection and the second temporary mechanical connection are made between second solder bumps attached to a bottom surface of the second integrated circuit chip and contact pads on a top surface of the first integrated circuit chip; and wherein the first temporary electrical connection and the first temporary mechanical connection are made by applying a first vacuum via one or more first holes in sidewalls of the integrated circuit chip holder, wherein inner sides of the sidewalls follow edges of the first integrated circuit chip and edges of the second integrated circuit chip, wherein distances from the inner sides of the sidewalls to the edges of the first integrated chip and to the second integrated chip are less than a minimum of distances between any two second solder bumps attached adjacent to each other and distances between any two first solder bumps attached adjacent to each other, wherein the sidewalls have one or more first holes, wherein the first holes have first inner openings on the inner sides of the sidewalls abreast a first gap between the bottom surface of the first integrated circuit chip and the top surface of the integrated circuit chip carrier, wherein a height of the first gap is determined by a height of the first solder bumps, wherein a height of the first inner openings is smaller than the height of the first gap, wherein a bottom surface of the integrated chip holder is parallel to the top surface of the integrated circuit chip carrier, wherein the bottom surface of the integrated chip holder is in a first temporary rigid mechanical contact with the top surface of the integrated circuit chip carrier.