Patent ID: 9521346
Filing Date: 2016-12-13
CPC Classification: G01J,H01L,H04N

Claim Text:
1. A readout integrated circuit, comprising: a memory for each of a plurality of pixels, wherein the memory maintains an initial bias voltage for each pixel during an initial integration frame time and during a sample and hold readout processing time, and wherein the sample and hold readout processing time is utilized to write a subsequent bias voltage for each pixel for a subsequent integration frame time to allow a first one of the pixels to have a different bias voltage than a second one of the pixels inside each integration frame time; an address selector to synchronize a subsequent bias voltage for each of the pixels; a reference voltage recover switch to subtract the initial bias voltage from an output voltage of the integrated circuit, and to result an integrator voltage for a sample and hold block; and a pulse-width control circuit to prevent crosstalk of the subsequent bias voltage between the first and second pixels while a pixel clock selects adjacent columns.