Patent ID: 9362276
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate including a plurality of active regions configured in parallel and an isolation region between adjacent active regions; forming isolation structures in the isolation regions; providing a plurality of dummy gate structures on the isolation structures and the active regions that are in the semiconductor substrate, wherein each dummy gate structure includes a dummy gate electrode layer and a sidewall spacer on a sidewall surface of the dummy gate electrode layer; forming a stress layer in the semiconductor substrate between two adjacent dummy gate structures; forming a first dielectric layer on the semiconductor substrate, the stress layers, and the sidewall spacers of the plurality of dummy gate structures, wherein the first dielectric layer exposes the dummy gate electrode layers of the plurality of dummy gate structures; removing the dummy gate electrode layers to form first openings in the first dielectric layer; forming gate structures in the first openings, wherein the gate structures include a plurality of functional gate structures and at least one non-functional gate structure; removing the at least one non-functional gate structure to form at least one second opening in the first dielectric layer; forming at least one third opening in the semiconductor substrate at a bottom of the at least one second opening; and forming a second dielectric layer to fill up the at least one second opening and the at least one third opening.