Patent ID: 9438409
Filing Date: 2016-09-06
CPC Classification: H04L

Claim Text:
1. An apparatus for clock data recovery (CDR), comprising: a data slicer operable to generate data samples derived from a transmitted signal; an error slicer operable to generate error samples derived from the transmitted signal; a CDR circuit operable to generate a common sampling clock phase for both the data slicer and the error slicer from output of the data samples and the error samples; and a decision adapt circuit operable to set a decision threshold of the error slicer, wherein for each main-cursor data sample of the data samples the decision adapt circuit is operable to adjust the decision threshold based on a sum of at least one term, each of the at least one term being a product of a scalar and one of a pre-cursor data sample or a post-cursor data sample.