Patent ID: 9472267
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A static random access memory comprising a plurality of cells, wherein each of the plurality of cells comprises: a first inverter and a second inverter, wherein an output terminal of the first inverter is connected to an input terminal of the second inverter, and an input terminal of the first inverter is connected to an output terminal of the second inverter; a first n-type metal-oxide-semiconductor (NMOS) transistor configured to control a write signal of the static random access memory, wherein the first NMOS transistor is connected to the input terminal of the first inverter, the output terminal of the second inverter, a write word line, and a write bit line; and a second NMOS transistor configured to control a read signal of the static random access memory, wherein the second NMOS transistor is connected to the output terminal of the first inverter, the input terminal of the second inverter, a read word line, and an internal line, wherein the internal line is connected to a read bit line via a fifth NMOS transistor, wherein a gate of the fifth NMOS transistor is connected to the internal line, and a drain of the fifth NMOS transistor is connected to the read bit line, and wherein gates of a plurality of fifth NMOS transistors of the plurality of cells are commonly connected to the internal line.