Patent ID: 9251886
Filing Date: 2016-02-02
CPC Classification: G11C

Claim Text:
1. A semiconductor storage device, comprising: a first and a second memory region, each of the first and second memory region including a plurality of memory cell array units; a first memory cell array unit in the first memory region having a plurality of first sense amplifiers, a plurality of first bit line pairs extending both sides of the first sense amplifiers, and a plurality of first memory cells connected to the first bit line pairs; a second memory cell array unit in the second memory region having a plurality of second sense amplifiers, a plurality of second bit line pairs extending both sides of the second sense amplifiers, and a plurality of second memory cells connected to the second bit line pairs; a first power supply line arranged to surround the first and second memory region; a second power supply line extending in a word-line direction and being connected to the first power supply line; wherein one of the first bit line pairs and one of the second bit line pairs are alternately provided in the word-line direction between the first and second sense amplifiers, wherein first word lines connected to the first memory cells and the second memory cells between the first and second sense amplifiers are in an inactivate state, and wherein the second power supply line is formed between the first and second sense amplifiers so as to overlap the first and second memory cells between the first and second sense amplifiers in plane view.