Patent ID: 9431908
Filing Date: 2016-08-30
CPC Classification: G01R,H02M,Y02B

Claim Text:
1. A zero current detector comprising: a bias current source; a current mirror comprising: an input terminal coupled to the bias current source, a first output terminal, and a second output terminal; a first transistor coupled to the first output terminal and grounded via a first resistor; a second transistor coupled to the second output terminal and a detection node via a second resistor; a first comparator comprising a non-inverting input terminal coupled to the second output terminal and an inverting input terminal coupled to the first output terminal; a voltage controlling unit configured to control a voltage of the non-inverting input terminal, so that the voltage is in a predetermined range; and when the voltage of the non-inverting input terminal is larger than a voltage of the inverting input terminal, the first comparator outputs an indication signal to denote that the detection node generates a zero current; wherein the voltage controlling unit comprises a first NMOS transistor and a second comparator; a drain of the first NMOS transistor is coupled to the second output terminal, a source of the first NMOS transistor is grounded; the second comparator comprises a non-inverting input terminal, an inverting input terminal, and a second comparison output terminal, the non-inverting input terminal of the second comparator is coupled to the output terminal, the inverting input terminal of the second comparator is coupled to a reference voltage, and the second comparison output terminal is coupled to a gate of the NMOS transistor.