Patent ID: 9472578
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A display substrate, comprising a base substrate, gate lines and data lines formed on the base substrate, and at least one pixel unit defined by the gate lines and the date lines, each pixel unit comprising a thin film transistor and a pixel electrode, wherein, in each pixel unit, a drain electrode of the thin film transistor is electrically connected with the pixel electrode by at least part of an edge region of at least one side of the drain electrode, wherein a passivation layer is formed over the drain electrode, a via for exposing the at least part of the edge region of the at least one side of the drain electrode is formed in the passivation layer, and the pixel electrode is electrically connected with the drain electrode through the via, and wherein the via has a ring shape when viewed in a direction vertical to a display plane of the display substrate, or has a planar shape which is formed by a plurality of holes arranged in an array, when viewed in a direction vertical to a display plane of the display substrate.