Patent ID: 9257522
Filing Date: 2016-02-09
CPC Classification: G11C,H01L

Claim Text:
1. A memory cell to store one or more bits of data, comprising: a capacitor comprising first and second capacitor plates which are separated from one another by a dielectric, wherein the first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and wherein the second capacitor plate is a polysilicon or metal layer arranged over the doped region; a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions, wherein a width of the gate electrode differs from a width of the second capacitor plate; and an interconnect structure disposed over the semiconductor substrate and coupling the gate electrode of the transistor to the second capacitor plate; wherein an upper surface of the second capacitor plate is co-planar with an upper surface of the gate electrode.