Patent ID: 9362134
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A chip package comprising: a semiconductor chip having a first surface and a second surface that is opposite to the first surface, at least one conductive pad, and a first opening, wherein the conductive pad is adjacent to the first surface, and the first opening extends from the second surface to the first surface to expose the conductive pad; an insulating layer disposed on the second surface and extending to a sidewall and a bottom portion of the first opening to expose the conductive pad, wherein the insulating layer on the bottom portion of the first opening has an underfoot structure; a redistribution layer disposed on the insulating layer and electrically connected to the exposed conductive pad through the first opening; and a passivation layer covering the redistribution layer and partially located into the first opening, wherein the passivation layer has at least one second opening to expose the redistribution layer on the second surface.