Patent ID: 9354823
Filing Date: 2016-05-31
CPC Classification: G06F

Claim Text:
1. A memory subsystem, comprising: a memory device comprising a plurality of independently accessible memory partitions; and a control unit coupled to the memory device and configured to read and write data to the memory device in response to receiving memory transactions via a memory interface; wherein the control unit is configured to perform memory transactions that include a memory write burst command having a first frame that specifies a starting address in the memory device, and further having a plurality of subsequent frames for conveying a data payload; and wherein the control unit is configured to generate a number of memory write operations to the memory in response to receiving the memory write burst command, wherein the memory write operations write the data payload from each subsequent frame to a different memory partition, beginning with a partition specified in the memory write burst command, wherein the data payload is written to the different memory partitions at the starting address.