Patent ID: 9524787
Filing Date: 2016-12-20
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a plurality of memory cells that are stacked above a substrate; a plurality of word lines that are electrically connected to gates of the memory cells; a source line that is electrically connected to one end of the memory cells; and a controller configured to execute a read operation that includes a first operation carried out over first and second time periods and a second operation carried out over third and fourth time periods, a first voltage being applied to a selected word line during the first and second time periods of the first operation, a second voltage that is higher than the first voltage being applied to the selected word line during the third and fourth time periods of the second operation, a third voltage being applied to the source line during the first and third time periods, a fourth voltage that is lower than the third voltage being applied to the source line during the second time period, and a fifth voltage that is lower than the third voltage being applied to the source line during the fourth time period.