Patent ID: 9230995
Filing Date: 2016-01-05
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: a substrate, a plurality of gate lines and a plurality of data lines, crossing each other and formed on the substrate, respectively; a plurality of pixel units, disposed on the substrate and defined by the plurality of gate lines and the plurality of data lines crossing each other, each of the plurality of pixel units comprising a thin film transistor and a pixel electrode, wherein the thin film transistor comprises a source electrode, a drain electrode, an active layer, a gate insulating layer and a gate electrode, and the source electrode and the drain electrode are provided on the substrate opposing to each other with a channel of the thin film transistor provided therebetween, the active layer is provided above the substrate on which the source electrode and the drain electrode are formed the gate insulating layer and the gate electrode are sequentially provided above the active layer, and the pixel electrode is positioned in a region outside the thin film transistor within the pixel unit, and is extended to a position above the drain electrode to be partly lapped over and directly connected to the drain electrode, wherein an area of the active layer is larger than that of the gate insulating layer, wherein the pixel electrode only laps over and directly connects to a part of the drain electrode adjacent to the pixel electrode, one part of the active layer positioned above the drain electrode is directly lapped over and connected to the drain electrode and the other part thereof is connected to the drain electrode via the pixel electrode.