Patent ID: 9496169
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, the method comprising: forming a plurality of conductive features within a first dielectric layer over a substrate; forming a first etch stop layer over the plurality of conductive features; forming a first opening through the first etch stop layer to at least partially expose a first top surface of a first one of the plurality of conductive features and to expose a second top surface of a second one of the plurality of conductive features; removing a portion of the first dielectric layer between the first one of the conductive features and the second one of the conductive features to form a second opening; lining the second opening with a second etch stop layer, wherein the second etch stop layer extends over the first etch stop layer; and depositing a dielectric material into the second opening, wherein the depositing the dielectric material further comprises forming an air gap within the second opening.