Patent ID: 9459956
Filing Date: 2016-10-04
CPC Classification: G06F,H03M

Claim Text:
1. A low density parity check decoder comprising: a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages; a check node processor operable to generate check node to variable node message vectors and to calculate checksums based on the variable node to check node messages; a convergence detector and bit map generator operable to detect convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks, wherein the convergence detector and bit map generator comprises a plurality of barrel shifters; wherein the convergence detector and bit map generator comprises a shift memory, a first set of multiplexors, and a plurality of subtractor circuits operable to configure the plurality of barrel shifters; and an output selector circuit operable to receive the at least one bit map from the convergence detector and bit map generator, to receive hard decisions from a cyclic shifter, and to select between outputting the hard decisions and the at least one bit map.