Patent ID: 9525076
Filing Date: 2016-12-20
CPC Classification: B82Y,G11C,H01L,Y10S

Claim Text:
1. A graphene memory comprising: a conductive semiconductor substrate; a source and a drain spaced apart from each other on a surface of the conductive semiconductor substrate; a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain when viewed from a plan view, the graphene layer being flat; a conductive layer directly on the graphene layer, the conductive layer facing the conductive semiconductor substrate with the graphene layer therebetween; and a gate electrode above the conductive layer, wherein a Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges, wherein the gate electrode covers the graphene layer and overlaps a portion of the conductive semiconductor substrate exposed by a periphery of the graphene layer when viewed from the plan view, wherein the graphene layer includes one of at least one hole and at least one slit passing through the graphene layer, and wherein the conductive layer includes one of polysilicon, aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr).