Patent ID: 9520176
Filing Date: 2016-12-13
CPC Classification: G11C

Claim Text:
1. A semiconductor apparatus comprising: a plurality of first pads including a first power supply pad and a first data input/output pad, the plurality of first pads aligned to a first line elongated in a first direction; a plurality of second pads including a second power supply pad and a second data input/output pad, the plurality of second pads aligned to a second line elongated in the first direction; first and second memory cell arrays arranged between the plurality of first pads and the plurality of second pads in a second direction crossing the first direction; a first main amplifier arranged between the first memory cell array and the plurality of first pads; a second main amplifier arranged between the second memory cell array and the plurality of second pads; a first data input/output circuit coupled between the first data input/output pad and the first main amplifier; a second data input/output circuit coupled between the second data input/output pad and the second main amplifier; a first signal line coupled between the first main amplifier and the first data input/output circuit; a second signal line coupled between the second main amplifier and the second data input/output circuit; a primary power supply line arranged between the first and second main amplifiers; wherein the first signal line extends along the second direction from an edge of the primary power supply line, and is sandwiched between a pair of shielding power supply lines that extend in the second direction along opposing surfaces of the first signal line; wherein a width of the primary power supply line is wider than a width of the first signal line; and wherein the shielding power supply lines are about the same width as the first signal line.