Patent ID: 9491015
Filing Date: 2016-11-08
CPC Classification: H04B,H04L

Claim Text:
1. A receiver for a three-wire digital interface, comprising: first, second and third input terminals; first, second, third, fourth, fifth and sixth output terminals; first, second and third junction nodes; a first resistive element coupled between the first input terminal and the first junction node; a second resistive element coupled between the second input terminal and the second junction node; a third resistive element coupled between the third input terminal and the third junction node; a network comprising first, second and third network terminals coupled to, respectively, the first, second and third junction nodes the network having substantially the same impedance between all pairs of the first, second and third network terminals; a first comparator having a non-inverting input coupled to the first input terminal, an inverting input coupled to the second junction node, and an output coupled to the first output terminal; a second comparator having a non-inverting input coupled to the first input terminal, an inverting input coupled to the third junction node, and an output coupled to the second output terminal; a third comparator having a non-inverting input coupled to the second input terminal, an inverting input coupled to the third junction node, and an output coupled to the third output terminal; a fourth comparator having a non-inverting input coupled to the second input terminal, an inverting input coupled to the first junction node, and an output coupled to the fourth output terminal; a fifth comparator having a non-inverting input coupled to the third input terminal, an inverting input coupled to the first junction node, and an output coupled to the fifth output terminal; and a sixth comparator having a non-inverting input coupled to the third input terminal, an inverting input coupled to the second junction node, and an output coupled to the sixth output terminal.