Patent ID: 9384797
Filing Date: 2016-07-05
CPC Classification: G06F,G11C

Claim Text:
1. A memory control method for a system including a memory having a plurality of ports, a plurality of devices, and a port connector that controls connections between the plurality of devices and a plurality of port, the method comprising: assigning, based on a table for enregistering an allocated device that executes a first process of a plurality of processes jointly operated in a pipeline manner in a first application, the first process of the plurality of processes jointly operated in the pipeline manner in the first application to the allocated device registered to execute the first process; notifying the port connector of identification information of a port of the plurality of ports of the memory used by the plurality of processes jointly operated in the pipeline manner in the first application; enregistering the identification information of the port into the table; allocating to the port a storage area used by the plurality of processes jointly operated in the pipeline manner in the first application; and enregistering an address of the allocated storage area into the table.