Patent ID: 9501991
Filing Date: 2016-11-22
CPC Classification: G09G,H01L

Claim Text:
1. A scan driving circuit for oxide semiconductor thin film transistors, comprising: a plurality of GOA units which are cascade connected, and N is set to be a positive integer and the Nth GOA unit comprises a pull-up control part, a pull-up part, a transfer part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up control part comprises an eleventh transistor, and a gate of the eleventh transistor is electrically coupled to a driving output end of a N−2th GOA unit which is the two former stage of the Nth GOA unit, and a drain is electrically coupled to an output end of the N−2th GOA unit which is the two former stage of the Nth GOA unit, and a source is electrically coupled to a first node; the first pull-down part comprises a forty-first transistor, and a gate of the forty-first transistor is electrically coupled to an output end of a N+2th GOA unit which is the two latter stage of the Nth GOA unit, and a drain is electrically coupled to the first node, and a source is electrically coupled to a second negative voltage level or an output end; the pull-down holding circuit part comprises a fifty-first transistor, and both a gate and a drain of the fifty-first transistor are electrically coupled to a constant high voltage level, and a source is electrically coupled to a fourth node; a fifty-second transistor, and a gate of the fifty-second transistor is electrically coupled to the first node, and a drain is electrically coupled to the fourth node, and a source is electrically coupled to a first negative voltage level; a fifty-third transistor, and a gate of the fifty-third transistor is electrically coupled to the fourth node, and a drain is electrically coupled to the constant high voltage level, and a source is electrically coupled to a second node; a fifty-fourth transistor, and a gate of the fifty-fourth transistor is electrically coupled to the first node, and a drain is electrically coupled to the second node, and a source is electrically coupled to a third node; a seventy-third transistor, and a gate of the seventy-third transistor is electrically coupled to the fourth node, and a drain is electrically coupled to the constant high voltage level, and a source is electrically coupled to the third node; a seventy-fourth transistor, and a gate of the seventy-fourth transistor is electrically coupled to the first node, and a drain is electrically coupled to the third node, and a source is electrically coupled to a constant low voltage level; a forty-second transistor, and a gate of the forty-second transistor is electrically coupled to the second node, and a drain is electrically coupled to the first node, and a source is electrically coupled to the second negative voltage level; a thirty-second transistor, and a gate of the thirty-second transistor is electrically coupled to the second node, and a drain is electrically coupled to the output end, and a source is electrically coupled to the first negative voltage level; the fifty-first transistor, the fifty-second transistor, the fifty-third transistor, the fifty-fourth transistor construct a main inverter, and the main inverter is employed to control the thirty-second transistor and the forty-second transistor; the seventy-third transistor and the seventy-fourth transistor construct an auxiliary inverter, and the auxiliary inverter is employed to provide a low voltage level to the main inverter in a functioning period, and a high voltage level to the main inverter in a non-functioning period; a relation of the first negative voltage level, the second negative voltage level and the constant low voltage level is: the constant low voltage level<the second negative voltage level<the first negative voltage level.