Patent ID: 9472295
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A nonvolatile semiconductor memory device comprising: a memory cell array which comprises: a memory string having a plurality of memory cells connected in series therein, each of the memory cells being configured capable of having formed therein a first threshold voltage distribution, a second threshold voltage distribution, a third threshold voltage distribution and a fourth threshold voltage distribution that are respectively assigned to data of four values to be stored in each of the memory cells and that have values ascending in an order of the first, second, third and fourth threshold voltage distributions; a first select transistor connected to one end of the memory string; a second select transistor connected to the other end of the memory string; a bit line connected to the memory string via the first select transistor; a source line connected to the memory string via the second select transistor; and a word line connected to a control gate electrode of each of the memory cells; and a control circuit configured to apply a reading voltage to the control gate electrode of a selected memory cell in the memory string to determine whether the selected memory cell is conductive or not, and thereby execute data reading of the selected memory cell, the control circuit being configured capable of,