Patent ID: 9390980
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A method of at least partially making a semiconductor device, the method comprising: providing a first sub-assembly including a substrate layer, a Germanium-containing layer formed on at least a portion of a top surface of the substrate layer, a III-V material nanowire layer located on a portion of a top surface of the Germanium-containing layer, a Silicon-Germanium (SiGe) nanowire layer located on a portion of the top surface of the Germanium-containing layer; refining the first sub-assembly into a second sub-assembly by removing the Germanium-containing layer so that: (i) the III-V material nanowire layer is at least partially suspended above the substrate layer, and (ii) the SiGe nanowire layer is at least partially suspended above the substrate layer; electrically connecting the III-V material nanowire layer to a first set of source/drain components so that the III-V material nanowire layer acts as a gate for an n-type field effect transistor (nFET); and electrically connecting the SiGe nanowire layer to a second set of source/drain components so that the SiGe nanowire layer acts as a gate for a p-type field effect transistor (pFET).