Patent ID: 9361960
Filing Date: 2016-06-07
CPC Classification: G11C

Claim Text:
1. A method of operating a memory module, comprising: providing a storage array having a plurality of memory banks and a first set of memory segments, wherein each of the plurality of memory banks includes a second set of memory segments; in a first mode of operation, using the first set of memory segments as an additional memory bank; and in a second mode of operation, accessing a memory segment in the first set of memory segments in parallel with a corresponding one of the plurality of memory banks; wherein in the first mode of operation, each accessible memory bank of the memory module has a first number of memory segments accessible in parallel, and in the second mode of operation, each accessible memory bank of the memory module has a second number of memory segments accessible in parallel, wherein the second number is greater than the first number, and the first number of memory segments is an integer multiple of 8 and the second number of memory segments is an integer multiple of 9; and wherein a total number of memory segments accessible in the first mode of operation is the same as a total number of memory segments accessible in the second mode of operation.