Patent ID: 9449883
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device, comprising the steps of: forming a first gate electrode portion in a first region on a main surface of a semiconductor substrate by stacking a first metal film having a predetermined work function on a first dielectric film having a predetermined dielectric constant; forming a second gate electrode portion in a second region on said main surface of said semiconductor substrate by stacking a second metal film having a predetermined work function on a second dielectric film having a predetermined dielectric constant; forming a first protective film including a first silicon nitride film to cover a side surface of said first gate electrode portion and a side surface of said second gate electrode portion, wherein the first silicon nitride film on the side surface of the first gate electrode portion is a first offset spacer, and the first protective film is in direct contact with both of the side and upper surfaces of the first gate electrode and the side and upper surfaces of the second gate electrode; forming a first extension implantation region in said first region by injecting an impurity of a first conduction type by using said first offset spacer as a mask; cleaning said semiconductor substrate after forming said first extension implantation region, wherein an upper surface and the side surface of the first gate electrode portion and an upper surface and the side surface of the second gate electrode portion are covered with the first protective film during said cleaning; forming a second protective film on a surface of said first protective film by stacking a silicon oxide film on the first silicon nitride film and a second silicon nitride film on the silicon oxide film, wherein a stack of at least the first silicon nitride film, the silicon oxide film, and the second silicon nitride film on a side surface of the second gate electrode portion is a second offset spacer, and each of the silicon oxide film and the silicon nitride film of the second protective film is formed to cover a whole side surface of each of the first gate electrode portion and the second gate electrode portion; forming a second extension implantation region in said second region by injecting an impurity of a second conduction type by using said second offset spacer as a mask; cleaning said semiconductor substrate after forming said second extension implantation region, wherein the upper surface and the side surface of the first gate electrode portion and the upper surface and the side surface of the second gate electrode portion are covered with at least a portion of the first protective film during said cleaning; forming a first sidewall spacer on the side surface of said first gate electrode portion with said first protective film and said second protective film disposed therebetween, wherein the first sidewall spacer is formed with the first protective film between the semiconductor substrate and the first sidewall spacer, and forming a second sidewall spacer on the side surface of said second gate electrode portion with said first protective film and said second protective film disposed therebetween, wherein the second sidewall spacer is formed with the first protective film between the semiconductor substrate and the second sidewall spacer; forming a first source/drain implantation region in said first region by injecting the impurity of the first conduction type using said first sidewall spacer as a mask; forming a second source/drain implantation region in said second region by injecting the impurity of the second conduction type using said second sidewall spacer as a mask; forming a first extension region, a second extension region, a first source/drain region, and a second source/drain region, respectively, by performing predetermined heat treatment to thermally diffuse said impurities in said first extension implantation region, said second extension implantation region, said first source/drain implantation region, and said second source/drain implantation region; and forming an oxide layer as said first protective film in addition to said first silicon nitride film by oxidizing a surface of each of said first gate electrode portion and second gate electrode portion after forming said first gate electrode portion and second gate electrode portion and before forming said first silicon nitride film, wherein the oxide layer remains without being removed at least until the steps of forming the first extension implantation region, the second extension implantation region, the first source/drain implantation region, and the second source/drain implantation region are completed.