Patent ID: 9494873
Filing Date: 2016-11-15
CPC Classification: G03F

Claim Text:
1. An asymmetry compensation method used in a lithography overlay process, comprising: providing a first substrate, wherein a circuit layout, a first mask layer, and a second mask layer are disposed on the first substrate, the first mask layer and the second mask layer are stacked sequentially on the circuit layout, wherein the first mask layer has an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout, the second mask layer has an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout, the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter based on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.