Patent ID: 9391268
Filing Date: 2016-07-12
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor storage device comprising: a plurality of first select transistors, the first select transistor disposed above a lower electrode, and the first select transistor extended in a first direction; a plurality of memory cell arrays disposed in the first direction, the memory cell array including one or more memory cells connected in series in a normal direction of the lower electrode; and a selector that selects one of the plurality of memory cell arrays along the first direction; wherein an end of the memory cell array in the normal direction is electrically connected with the first select transistor, and another end of the memory cell array is electrically connected with the selector, wherein a plurality of the first select transistor is disposed along a second direction that is perpendicular to the first direction in a plane of the lower electrode, and wherein a channel of each of the first select transistor is electrically connected with each of the memory cell arrays adjacent to each other along the first direction.