Patent ID: 9437673
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. An integrated circuit, comprising: a substrate of a first conductivity type semiconductor; a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate; a driver circuit including a first doped region of a second conductivity type semiconductor disposed in the semiconductor layer; an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end; at least one guard structure formed in the semiconductor layer and under the interconnect structure, wherein the at least one guard structure is electrically floating; and a well region of the first conductivity type semiconductor formed in a top portion of the semiconductor layer and under the interconnect structure, wherein the well region is disposed between the driver circuit and the at least one guard structure and wherein the well region is doped heavier than the semiconductor layer.