Patent ID: 9309109
Filing Date: 2016-04-12
CPC Classification: B81B,B81C

Claim Text:
1. A method for forming an integrated semiconductor device, comprising: providing a first wafer, the first wafer comprising a first substrate having a microelectromechanical system (MEMS) device layer; providing a second wafer, the second wafer comprising a second substrate having at least one active device, and at least one interconnect layer over the second substrate, the at least one interconnect layer comprising an interlayer dielectric (ILD) and at least one conductive structure embedded inside the ILD; bonding the first wafer over the second wafer so that the MEMS device layer is connected with the at least one interconnect layer; forming at least one conductive plug through the first substrate and the MEMS device layer and inside the at least one interconnect layer, the at least one conductive plug comprising a metal and contacting the at least one conductive structure; etching the second substrate and the at least one interconnect layer to form a cavity extending from a surface of the second substrate to the MEMS device layer; and etching the first substrate and the MEMS device layer to form a MEMS device interfacing with the cavity extending from a surface of the second substrate to the MEMS device layer.