Patent ID: 9460776
Filing Date: 2016-10-04
CPC Classification: G11C

Claim Text:
1. An SRAM array, comprising: SRAM lines comprising a plurality of wordlines and a plurality of bitlines; a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines; and voltage boost circuitry operatively coupled with the cells, the voltage boost circuitry comprising a boost capacitor configured to provide an amount of voltage boost that is based on an address of a cell to be accessed, where the boost capacitor is coupled and decoupled to at least one SRAM line of the SRAM lines through a transistor, where the voltage boost circuitry is configured to provide voltage boost by (i) charging an SRAM line to a pre-boosted voltage while the transistor is disabled to decouple the boost capacitor from the SRAM line; and (ii) after the charging to the pre-boosted voltage, enabling the transistor to couple the boost capacitor to the SRAM line and applying a boost command signal to a boost command terminal of the boost capacitor.