Patent ID: 9524165
Filing Date: 2016-12-20
CPC Classification: G06F

Claim Text:
1. A computer implemented method for register comparison for operand store compare (OSC) prediction, the method comprising: for each instruction in an instruction group of a processor pipeline: masking a set of lowest order bits of the displacement of each instruction, wherein a number of the set of lowest order bits that are masked is four; determining that a first instruction of the instruction group does not have a base register value; based on determining that the first instruction does not have a base register value, setting the base register value of the first instruction equal to a default value, wherein the default value is zero; determining that a second instruction of the instruction group does not have an index register value; based on determining that the second instruction does not have an index register value, setting the index register value of the instruction equal to a default value, wherein the default value is zero; comparing the base register value, the index register value, and the displacement of each instruction in the instruction group to the base register value the index register value, and the displacement of each other instruction in the instruction group; based on the comparison, determining that a first load instruction of the instruction group has a probable OSC conflict with a first store instruction of the instruction group; delaying the first load instruction based on the probable OSC conflict with the first store instruction; determining that a prediction override instruction is located between a second load instruction and a second store instruction of the instruction group; turning off OSC prediction for the second load instruction and the second store instruction; comparing the base register value, the index register value, and the displacement of each instruction in the instruction group to a base register value, an index register value, and a displacement of each other instruction in another instruction group; based on the comparison to instructions of the another instruction group, determining that a third load instruction of the instruction group has a probable OSC conflict with a store instruction of the another instruction group; and delaying the third load instruction based on the probable OSC conflict with the store instruction of the another instruction group.