Patent ID: 9389999
Filing Date: 2016-07-12
CPC Classification: G06F,G11C

Claim Text:
1. A system configured to emulate an electrically erasable programmable read only memory, the system comprising a non-volatile memory, wherein the non-volatile memory is configurable into a first region and a second region, wherein the first region is configured to store a first class of data and the second region is configured to store a second, different class of data, wherein the first region and the second region of the non-volatile memory are arranged on one single semiconductor chip and share a same bit line and a common well of the one single semiconductor chip, the system further configured to provide a first voltage to a word line of the second region, and a second voltage different from the first voltage both to the common well of the first and the second region and to a word line of the first region to erase a cell of the second region and inhibit erasure of a cell of the first region.