Patent ID: 9443925
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A structure comprising: a semiconductor substrate; a first source/drain material disposed in the semiconductor substrate; a first dielectric liner disposed between the first source/drain material and the semiconductor substrate, the first dielectric liner having a bottom portion disposed along a bottom of the first source/drain material and having a sidewall portion disposed along a sidewall of the first source/drain material; a top surface of the first source/drain material, a top surface of the sidewall portion of the first dielectric liner, and a topmost surface of the semiconductor substrate being co-planar; a semiconductor layer over the top surface of the first source/drain material and the top surface of the semiconductor substrate; and a gate structure over the semiconductor layer, wherein a first portion of the semiconductor layer and at least a portion of the first source/drain material form a first source/drain, and a second portion of the semiconductor layer forms a channel.