Patent ID: 9367348
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A processing unit for a data processing system including a shared memory system, the processing unit comprising: a processor core; a cache memory coupled to the processor core, wherein the cache memory includes: a cache array; wherein the cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory, forms based on the load mask or store mask a working set of ways in the congruence class containing one or more cache lines within the transaction footprint and updates a replacement order of the cache lines in the congruence class, wherein the update to the replacement order promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set.