Patent ID: 9250538
Filing Date: 2016-02-02
CPC Classification: G03F

Claim Text:
1. A computer-implemented method comprising: receiving, by way of a processor, an input data stream of an integrated circuit (IC) design layout; correcting, by the processor, identified outliers in the IC design layout by way of an iterative repair loop comprising steps of: performing, by the processor, a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value, the smart enhancement step comprising an inverse lithography technology (ILT) process; cross-linking, by the processor, a base optical rule check (ORC) process with the OPC step; and performing, by the processor, pattern classification during the one or more iterations of the OPC step, wherein the pattern classification is based on a pattern matching database or one or more compensation tables.