Patent ID: 9229851
Filing Date: 2016-01-05
CPC Classification: G06F,G11C

Claim Text:
1. A memory controller configured to control a flash memory including memory cells, the memory controller comprising: a memory configured to include an access number storing section configured to store a number of read accesses for encoded data stored in a memory cell in association with one of logical addresses provided from a host apparatus; and a processor configured to include: an address translator configured to translate the logical addresses to physical addresses of the flash memory; a storage state checking section configured to, at an interval which is determined by a number of read accesses, check the number of errors in decoding processing of data read from the memory cell; and a refresh processing section configured to perform refresh processing to restore the encoded data stored in the memory cell, when the number of errors checked by the storage state checking section, is larger than a predetermined number, wherein the predetermined number of read accesses is set to have a small enough interval with respect to a difference between a number of accesses at which a sign of read disturb occurs and a number of accesses at which error correction is disabled.