Patent ID: 9530371
Filing Date: 2016-12-27
CPC Classification: G09G,G11C

Claim Text:
1. A GOA circuit for tablet display, which comprises cascaded plurality of GOA units, charges to the nth-stage horizontal scan line in the display region according to the nth-stage GOA control unit, the nth-stage GOA unit comprises a pull-up part, a key pull-down part, a pull-down holding part, a pull-up control part, a transfer part and a boast capacitor; the pull-up part, the key pull-down part, the pull-down holding part and the boast capacitor are respectively connected with the gate signal and the nth-stage horizontal scan line, the pull-up control part and the transfer part are respectively connected with the gate signal point; wherein, the transfer part comprises: a first thin film transistor, the gate thereof being connected with the gate signal point, the drain and the source being respectively input the nth-stage clock signal and being output the turn-on signal; wherein, the pull-up control part comprises: a second thin film transistor, the gate thereof being input the turn-on signal from the (n−2)th stage GOA unit, the drain and the source being respectively connected with the (n−2)th stage horizontal scan line and the gate signal point; a third thin film transistor, the gate thereof being connected with the (n−1)th stage horizontal scan line, the drain and the source being respectively connected with the (n−1)th stage horizontal scan line and the gate signal point; wherein, the pull-down holding part comprises: a fourth thin film transistor, the gate thereof being connected with the first circuit point, the drain and the source being respectively connected with the nth horizontal scan line and being input the first direct current low voltage; a fifth thin film transistor, the gate thereof being connected with the second circuit point, the drain and the source being respectively connected with the nth horizontal scan line and being input the first direct current low voltage; a sixth thin film transistor, the gate thereof being connected with the first circuit point, the drain and the source being respectively connected with the (n−1)th stage horizontal scan line and the gate signal point; a seventh thin film transistor, the gate thereof being connected with the second circuit point, the drain and the source being respectively connected with the (n−1)th stage horizontal scan line and the gate signal point; an eighth thin film transistor, the gate thereof being connected with the gate signal point, the drain and the source being respectively connected with the first circuit point and being input the first direct current low voltage; a ninth thin film transistor, the gate thereof being connected with the gate signal point, the drain and the source being respectively connected with the second circuit point and being input the first direct current low voltage; a tenth thin film transistor, the gate thereof being input a first clock signal, the drain and the source being respectively input a first clock signal and being connected with the first circuit point; an eleventh thin film transistor, the gate thereof being input a second clock signal, the drain and the source being respectively input the first clock signal and being connected with the first circuit point; a twelfth thin film transistor, the gate thereof being input the second clock signal, the drain and the source being respectively input the second clock signal and being connected with the second point; a thirteenth thin film transistor, the gate thereof being input the first clock signal, the drain and the source being respectively input the second clock signal and being connected with the second circuit point; during operation, the frequencies of the first clock signal and the second clock signal being lower than the nth stage clock signal, the first circuit point and the second circuit point being alternately charged by the first clock signal and the second clock signal and being at high voltage; wherein, the pull-up part comprises: a fourteenth thin film transistor, the gate thereof being connected with the gate signal point, the drain and the source being respectively input the nth stage clock signal and being connected with the nth stage horizontal scan line; wherein, the key pull-down part comprises: a fifteenth thin film transistor, the gate thereof being connected with the (n+2)th stage scan line, the drain and the source being respectively connected with the nth stage horizontal scan line and being input the direct current low voltage; a sixteenth thin film transistor, the gate thereof being connected with the (n+2)th stage horizontal scan line, the drain and the source being respectively connected with the gate signal point and being input the direct current low voltage; wherein, the duty ratio of the nth stage clock signal is less than 50%.