Patent ID: 9240940
Filing Date: 2016-01-19
CPC Classification: H04L

Claim Text:
1. A method for evaluating the performance of large scale computer systems, the method comprising: receiving topology data at a large scale distributed memory computer system, wherein the topology data describes the connections between a plurality of switches, each switch connected to a plurality of nodes, and the topology data lists each node of the plurality of nodes that is associated with each switch of the plurality of switches; performing a data transfer test for each of a pair of switches based on the received topology data for each pair of switches in the plurality of switches, wherein each of the pair of switches includes a first switch and a second switch that connect to each other via direct links, the first and the second switch grouped as a pair when preparing to perform the data transfer test, and each switch is included in only one of the pair of switches at a time; transferring data between a plurality of nodes associated with a first switch in a pair of switches and a plurality of nodes associated with a second switch in the pair of switches; determining a respective overall test result value reflecting overall performance of a respective pair of switches for a plurality of component tests, wherein the component tests reflect performance of links between switches and performance nodes connected to the switches during the transfer of data; determining that the pair of switches meets minimum performance standards by comparing the overall test result value against an acceptable test value; and reporting the respective pair of switches as underperforming in accordance with a determination that the overall test result value does not meet the minimum performance standards.