Patent ID: 9235377
Filing Date: 2016-01-12
CPC Classification: G06F

Claim Text:
1. A device comprising: one or more sensors, each having a bandwidth associated therewith; one or more processors; a memory coupled to the one or more sensors and the one or more processors and having a first portion, a second portion, and a third portion, the first, second, and third portions being contiguous, the third portion being a first-in-first-out (FIFO) having one or more FIFO portions, the first portion allocated to store instructions for execution by a processor of the one or more processors, the second portion allocated to store data generated by the processor, and the third portion allocated to store data from the one or more sensors wherein the sizes of the first, second and third portions of the memory are based on the bandwidth of the one or more sensors; and control logic coupled to the memory and operable to dynamically allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors.