Patent ID: 9478284
Filing Date: 2016-10-25
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device, comprising: a lower electrode in a flat plate shape and an upper electrode in the flat plate shape; a plurality of first select transistors arranged between the lower electrode and the upper electrode, extending in a first direction, and provided along a second direction different from the first direction; a plurality of wires connected to the lower electrode via the plurality of first select transistors and each paired with a corresponding one of the plurality of first select transistors; a plurality of second select transistors arranged between the plurality of wires and the upper electrode, extending in the second direction, and provided along the first direction; and a plurality of memory chains having one or more memory cells connected in series in a normal direction to the lower electrode and the upper electrode, each memory chain provided along the first direction and the second direction, wherein the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor.