Patent ID: 9306597
Filing Date: 2016-04-05
CPC Classification: H03M

Claim Text:
1. A system comprising: a first interface to access a first data sample having “n” bits ordered from a most significant bit to a least significant bit and to access a second data sample having “n” bits ordered from a most significant bit to a least significant bit, wherein the second data sample is the next data sample after the first data sample in an ordered sequence of data samples; first logic to determine the highest-order bit, if any, that is different between the first data sample and the second data sample; second logic to determine a tap point that is a specific bit of the “n” bits, wherein the tap point is one of a number of permitted starting points for an overlay of “m” bits, wherein the tap point corresponds to a bit whose order is at least as high as the highest-order bit that is different between the first and second data samples, wherein the tap points are positioned such that all “n” bits fall within at least one overlay; third logic to access a portion of the second data sample comprising “m” contiguous bits, wherein the portion starts at the tap point and includes bits towards the least significant bit, wherein the portion is an overlay for the second data sample, wherein the third logic is operable to form a compressed word for the second data sample that comprises the portion of the second data sample in association with a code that indicates the tap point; and a second interface to output the compressed word for the second data sample.