Patent ID: 9379244
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate having a first region and a second region; a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate; and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate, wherein the first and third buffer patterns comprise a first semiconductor layer including germanium (Ge), the first channel pattern comprises a second semiconductor layer including germanium (Ge), and the second channel pattern comprises a third semiconductor layer including germanium (Ge), and wherein a germanium (Ge) concentration of the first semiconductor layer is less than germanium (Ge) concentrations of the second and third semiconductor layers.