Patent ID: 9343120
Filing Date: 2016-05-17
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a first register; and a second register comprising a first flip-flop circuit and a second flip-flop circuit, wherein the first register is electrically connected to the first flip-flop circuit, wherein the first flip-flop circuit is electrically connected to the second flip-flop circuit, wherein each of the first flip-flop circuit and the second flip-flop circuit comprises a first transistor and a capacitor, wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor, wherein each of the first flip-flop circuit and the second flip-flop circuit comprises a first three-state buffer, wherein an output of the first three-state buffer is electrically connected to a second terminal of the first transistor, wherein each of the first flip-flop circuit and the second flip-flop circuit comprises a second transistor and a second three-state buffer, wherein the second transistor comprises a channel formation region comprising an oxide semiconductor, wherein a first terminal of the second transistor is electrically connected to an input of the first three-state buffer, wherein a second terminal of the second transistor is electrically connected to an output of the second three-state buffer, and wherein an input of the second three-state buffer is electrically connected to the first terminal of the capacitor.