Patent ID: 9455022
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A semiconductor integrated circuit device comprising: a memory cell including: a holding circuit which has a plurality of MOSFETs and a pair of input/output nodes and operates with a first voltage as an operating voltage; and a pair of transfer MOSFETs which are coupled to the input/output nodes respectively and whose gates receive a selection signal; and a voltage generation circuit for generating a second voltage which is higher than the first voltage in terms of an absolute value, wherein in response to a unique ID generation instruction, the second voltage is applied to the gates of the transfer MOSFETs, a third voltage is supplied to the input/output nodes via the transfer MOSFETs, and then the second voltage applied to the gates of the transfer MOSFETs is lowered to a voltage that is lower than the first voltage in terms of an absolute value.