Patent ID: 9229057
Filing Date: 2016-01-05
CPC Classification: G01R

Claim Text:
1. A semiconductor test system comprising: a user device configured to operate a reference device in accordance with an interface signal of the reference device based on a timing signal having a variable operating frequency; a pattern synthesis apparatus configured to measure an interval between adjacent ones of edges of the timing signal transmitted from the user device, and to extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data; and a test device configured to receive the test pattern data, reconstruct the timing signal based on-the measured interval, generate a test driving signal such that a logic value of a response signal is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT, wherein the pattern synthesis apparatus includes