Patent ID: 9520554
Filing Date: 2016-12-13
CPC Classification: G11C,H01L

Claim Text:
1. A memory comprising: an array of memory cells; first and second voltage control word lines arranged outside of the array of memory cells, wherein the first and second voltage control word lines are adjacent to one another; and a plurality of clamp elements, each clamp element of the plurality of clamp elements including a wall self-heating type cell structure having a rectangular shape with at least one dimension oriented non-orthogonally relative to at least one of a respective bit line and a respective one of the first and second voltage control word lines and configured to control a voltage of a respective bit line, wherein the wall self-heating type cell structure includes a cap, a chalcogenic material, and a switch, and wherein the chalcogenic material is both self-heating and a phase change material, and wherein alternating ones of the plurality of clamp elements are arranged on alternating ones of the first and second voltage control word lines.