Patent ID: 9406560
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method of forming a wiring structure for an integrated circuit device, the method comprising: forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines such that first portions of the one or more copper lines are covered and second portions of the copper lines are not covered so as to define exposed regions, the masking selected regions comprising depositing a nitrogen-doped silicon carbide layer over the ILD layer and one or more copper lines, and patterning and removing portions of the nitrogen-doped silicon carbide layer; selectively plating metal cap regions over the exposed regions of the one or more copper lines such that the metal cap regions are not initially plated over the covered portions of the one or more copper lines; and following the plating of the metal cap regions over the exposed regions of the one or more copper lines, forming a conformal insulator layer over the metal cap regions and remaining portions of the nitrogen-doped silicon carbide layer.