Patent ID: 9385117
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, comprising the steps: providing a substrate comprising silicon semiconductor material; forming a gate of an NMOS transistor over the substrate; forming a gate of a PMOS transistor over the substrate; forming an n-type collector of an NPN heterojunction bipolar transistor (NHBT) in the substrate; forming source/drain cavities in the substrate adjacent to the gate of the PMOS transistor; forming a base cavity in the NHBT; forming p-type SiGe stressors in the source/drain cavities by an epitaxial process; forming a p-type SiGe base in the base cavity by an epitaxial process; forming n-type raised source and drain (NRSD) layers on n-type source and drain regions adjacent to the gate of the NMOS transistor by an epitaxial process; and forming an n-type silicon emitter on the p-type SiGe base by an epitaxial process.