Patent ID: 9236457
Filing Date: 2016-01-12
CPC Classification: G02F,H01L

Claim Text:
1. A method for manufacturing a thin film transistor (TFT) array substrate, which comprises a plurality of pixel units, for each pixel unit the method comprising: forming a gate metal layer on a base substrate and forming a pattern comprising a gate electrode and a gate line by patterning the gate metal layer; forming a gate insulator on the base substrate; sequentially depositing a semiconductor layer and an ohmic contact layer on the base substrate formed with the gate insulator and patterning the semiconductor layer and the ohmic contact layer, wherein the material of the semiconductor layer is zinc oxide, and the material of the ohmic contact layer is Ga depositing a source-drain metal thin film on the base substrate and forming a pattern comprising a data line, a source electrode, a drain electrode and a thin film transistor channel region by patterning the source-drain metal thin film, wherein the source electrode and the drain electrode are disposed adjoining the semiconductor layer with the interposed ohmic contact layer; forming a passivation layer on the base substrate and forming a passivation layer pattern; and depositing a transparent conductive thin film on the base substrate and forming a pixel electrode pattern by patterning the transparent conductive thin film, wherein the pixel electrode is disposed in the pixel unit defined by the gate line and the data line and is connected with the drain electrode.