Patent ID: 9251914
Filing Date: 2016-02-02
CPC Classification: G11C

Claim Text:
1. A test control circuit comprising: an address sequencer that generates a first address for selecting a cell in a predetermined order; a register that stores a second address of a cell that is determined to be a fail by a verify determination; a selector that selects the first address generated by the address sequencer or the second address stored in the register based on whether or not one or more predetermined number of addresses have been stored in the register; and a verify determination circuit that performs a verify determination of a cell which is indicated by the address selected by the selector; wherein the verify determination circuit performs a first verify determination of a cell which is indicated by the first address generated by the address sequencer and performs a second verify determination of one or more cells which are indicated by the one or more predetermined number of addresses after a predetermined voltage has been applied to a plurality of cells of an erase unit where there is a cell determined to be a fail in the first verify determination in a state in which the one or more predetermined number of addresses have been stored in a register, and wherein the selector selects the first address generated by the address sequencer after the second verify determination has been finished.