Patent ID: 9502438
Filing Date: 2016-11-22
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: gate lines; first data lines; second data lines; and N×M pixel units defined by the gate lines intersecting with the first data lines and the second data lines, where N is a total number of rows of the pixel units, and M is a total number of columns of the pixel units; the first data lines are configured to drive odd numbered pixel units in a same column of the pixel units, the second data lines are configured to drive even numbered pixel units in the same column of the pixel units; and a repairing line for each column of the pixel units is provided in a region at which at least one row of the pixel units are located; wherein projections of two ends of the repairing line on the substrate respectively overlap with regions at which the first data line and the second data line of the same column of pixel units are located, and the repairing line is isolated from the first data line and the second data line, and wherein the pixel units each comprise a pixel electrode; and the repairing line and the pixel electrode are formed simultaneously and located in a same layer of the array substrate.