Patent ID: 9397640
Filing Date: 2016-07-19
CPC Classification: G11C,H03K

Claim Text:
1. A latch circuit comprising: first to fourth storage nodes; and first to fourth pairs of transistors, each of which comprises a PMOS transistor and an NMOS transistor coupled in series with each other through a corresponding node among the first to fourth storage nodes, wherein the PMOS transistor is coupled to one of the storage nodes included in a previous one of the pairs of transistors at a gate of the PMOS transistor, wherein the NMOS transistor is coupled to one of the storage nodes included in a next one of the pairs of transistors at a gate of the NMOS transistor, wherein the PMOS transistors of the first to fourth pairs of transistors are formed in a first active region, wherein the NMOS transistors of the first to fourth pairs of transistors are formed in a second active region, separated from the first active region, wherein the PMOS transistors of the first to fourth pairs of transistors are sequentially arranged at each corner of a rectangle formed in the first active region that is a single region, and wherein the NMOS transistors of the first to fourth pairs of transistors are sequentially arranged at each corner of a rectangle formed in the second active region that is a single region.