Patent ID: 9401722
Filing Date: 2016-07-26
CPC Classification: H03L

Claim Text:
1. A phase-locked loop (PLL), comprising: a frequency detector circuit for estimating a frequency of a reference frequency signal by counting a number of cycles of the reference frequency signal over a fixed period of time; a phase detector for generating up and down command signals in response to phase differences between the reference frequency signal and a frequency signal related to a base PLL output frequency signal; a circuit for producing control signals in dependence upon the frequency detected by said frequency detector; a charge-pump DAC for generating a charge-pump output current, said charge-pump DAC being connected to receive said up and down command signals and control signals from said circuit; an integrator for integrating said charge-pump output current, said integrator including a plurality of capacitors switchably selected by said control signals from said circuit for producing control signals to adjust an integrating capacitance value; and a voltage controlled oscillator (VCO) for producing the base PLL output frequency signal in response to said integrated charge-pump output current; wherein the frequency detector circuit includes an oscillator configured to produce a clock signal having a fixed frequency, a first counter coupled to the clock signal configured to count for a fixed number of cycles of the clock signal to form a fixed time period, and a second counter coupled to the reference frequency signal configured to count a number of cycles of the reference frequency signal during the fixed time period, such that an output of the second counter is proportional to the frequency of the reference frequency signal.