Patent ID: 9443596
Filing Date: 2016-09-13
CPC Classification: G11C

Claim Text:
1. A non-volatile memory device, comprising: a memory cell array having a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor; and a voltage generator to generate a program voltage, a first pass voltage, and a second pass voltage, wherein when programming one of the outermost memory cells of the plurality of memory cells a first boost channel voltage is generated based on the first pass voltage applied to word lines of ones of the memory cells other than the one of the outermost memory cells and when programming one of the memory cells of the plurality of memory cells other than the outermost memory cells of the plurality of memory cells a second boost channel voltage is generated based on the second pass voltage applied to word lines of ones of the memory cells other than the one of the memory cells of the plurality of memory cells being programmed; wherein a level of the first boost channel voltage is lower than a level of the second boost channel voltage; and wherein a level of the first pass voltage is lower than a level of the second pass voltage.