Patent ID: 9373514
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method for manufacturing an electronic device, comprising: providing a substrate comprising a plurality of fin-type projections separated by an isolation dielectric material and laterally coextending in a first direction through a memory cell region and select gate regions abutting said memory cell region, said plurality of fin-type projections configured to include lower semiconducting sections and upper masking layer sections; removing a portion of said dielectric isolation material in said memory cell region to expose said lower semiconducting sections in said memory cell region, such that said dielectric isolation material in said memory cell region has a lower thickness than a thickness of said lower semiconducting sections of said plurality of fin-type projections, and said dielectric isolation material in said select gate regions has a greater thickness than said thickness of said lower semiconducting sections of said plurality of fin-type projections; removing said upper masking sections; forming a plurality of gate layers on said substrate, such that gate layers formed in said select gate regions are at least partially disposed on sidewalls of said dielectric isolation material in said select gate regions; and processing said plurality of gate layers to define a plurality of gate features coextending in a second direction transverse to said first direction.