Patent ID: 9431252
Filing Date: 2016-08-30
CPC Classification: H01L,Y10S

Claim Text:
1. A method of forming an integrated circuit, the method comprising: forming a first masking layer over a gate stack, a first source/drain region, and a second source/drain region, the first source/drain region and the second source/drain region being on opposing sides of the gate stack; modifying an etch rate of a portion of the first masking layer such that an etch rate of the first masking layer over the first source/drain region is different than an etch rate of the first masking layer over the second source/drain region; removing the first masking layer over the first source/drain region, the removing forming a first exposed source/drain region; doping the first exposed source/drain region with first dopants; removing the first masking layer; forming a second masking layer over the gate stack, the first source/drain region, and the second source/drain region; modifying an etch rate of a portion of the second masking layer such that an etch rate of the second masking layer over the first source/drain region is different than an etch rate of the second masking layer over the second source/drain region; removing the second masking layer over the second source/drain region, the removing forming a second exposed source/drain region; and doping the second exposed source/drain region with second dopants.