Patent ID: 9396992
Filing Date: 2016-07-19
CPC Classification: H01J,H01L

Claim Text:
1. An integrated circuit device manufacturing process, comprising: forming a dielectric matrix layer over a substrate; forming trenches in the dielectric matrix layer; cleaning the trenches in a first chamber using a plasma comprising ions configured to reduce copper oxide; lining the trenches with a diffusion barrier layer; in a second chamber, forming a copper seed layer over the diffusion barrier layer, the copper seed layer having an overhang proximate openings of the trenches; and in the first chamber, reducing the overhang by: producing a plasma comprising positively charged ions and negatively charged ions, the positively and negatively charged ions including halogen ions; filtering the plasma to selectively exclude ions of the positively charged ions; and bombarding the copper seed layer with ions of the filtered plasma.