Patent ID: 9502378
Filing Date: 2016-11-22
CPC Classification: H01L,H05K

Claim Text:
1. A method of manufacturing a semiconductor package, the method comprising: providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer; mounting semiconductor chips on the plurality of unit substrate regions; and forming conductive wires electrically connecting connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips, wherein the connection pads are electrically connected to the blind vias, and wherein forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the plurality of unit substrate regions.