Patent ID: 9514799
Filing Date: 2016-12-06
CPC Classification: G06F,G11C

Claim Text:
1. A memory scheduling method, comprising: consecutively writing, by a memory controller, a first group of first row strobe commands (ACTs) into a first memory, wherein the first group of first ACTs comprises multiple first ACTs and wherein a periodic interval exists between adjacent first ACTs being written by the memory controller into the first memory; writing, by the memory controller, operation commands that correspond to the first group of first ACTs into the first memory after consecutively writing the first group of first ACTs into the first memory, wherein a periodic interval exists between adjacent operation commands being written by the memory controller into the first memory; writing, by the memory controller, second ACTs into a second memory during periodic intervals between adjacent first ACTs being written into the first memory and/or during periodic intervals between adjacent operation commands that correspond to the first group of first ACTs being written into the first memory; and writing, by the memory controller, operation commands that correspond to the second ACTs into the second memory, wherein the first memory and the second memory are configured with dual Ranks.