Patent ID: 9335929
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. A flash memory package comprising: a flash memory controller coupled to a first data bus, a second data bus, a switching signal line and multiple chip enable signal lines; multiple first flash memory chips; multiple second flash memory chips; a first switch coupled to the first data bus and any one of the multiple first flash memory chips; and a second switch coupled to the second data bus and any one of the multiple second flash memory chips, wherein the switching signal line is coupled to the first switch and the second switch; each of the multiple chip enable signal lines is coupled respectively to one of the multiple first flash memory chips and one of the multiple second flash memory chips; and the flash memory controller is configured to set a particular first flash memory chip of the multiple first flash memory chips and a particular second flash memory chip of the multiple second flash memory chips in accessible status based on the switching signal line and a particular chip enable signal line of the multiple chip enable signal lines.