Patent ID: 9524902
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising: forming a dielectric layer over a substrate; forming a hard mask (HM) layer over the dielectric layer; forming, via a first removal process, a line-like opening in the HM layer, the line-like opening having ends and a first width; forming, via a second removal process subsequent to the first removal process, two line-end openings in the HM layer that each connect with the previously-formed line-like opening at the respective ends of the line-like opening, each of the two line-end openings having a second width greater than the first width; etching the dielectric layer through the line-like opening and the line-end openings to form a dielectric trench and expose a set of conductive features, each of the two line-end openings being aligned with a respective conductive feature in the set of conductive features; and forming a conductive line in the dielectric trench.