Patent ID: 9245759
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a dual work function semiconductor device, the method comprising: providing a substrate comprising a first predetermined area for forming a transistor of a first conduction type and a second predetermined area for forming a transistor of a second conduction type, the first conduction type being different from the second conduction type; forming a dielectric layer on the substrate, the dielectric layer extending to cover at least a part of the first area and extending to cover at least a part of the second area; forming a first metal layer/stack on the dielectric layer in the first predetermined area, wherein the first metal layer/stack comprises a first work function-shifting element, wherein the first metal layer/stack is one of TiN/Mg/TiN, Mg/TiN, TiN/La/TiN, La, La forming a second metal layer/stack directly on the first metal layer/stack in the first predetermined area and on the dielectric layer in the second predetermined area, wherein the second metal layer/stack comprises a second work function-shifting element; annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer; removing the first metal layer/stack and the second metal layer/stack; and forming a third metal layer/stack in the first predetermined area and the second predetermined area.