Patent ID: 9478550
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising: individual of the rows comprising an access line interconnecting transistors in that row, the access lines comprising a gate of individual of the transistors, the individual transistors comprising a channel region, a gate dielectric being between the channel region and the gate of the individual transistors; individual of the columns comprising a data/sense line interconnecting transistors in that column; and a plurality of conductive lines, individual of the conductive lines extending longitudinally parallel and laterally between immediately adjacent of the data/sense lines, the individual conductive lines comprising four straight sides forming a four-major-sided polygon in a vertical cross-section, immediately adjacent of the straight sides joining in a single of four corner regions in the vertical cross-section, one of the four single corner regions being the sole elevationally outermost corner region of the respective individual conductive line in the vertical cross-section, another of the four single corner regions being opposite the one corner region in the vertical cross-section and being the sole elevationally innermost corner region of the respective individual conductive line in the vertical cross-section.