Patent ID: 9465612
Filing Date: 2016-10-11
CPC Classification: G06F,H04N

Claim Text:
1. A method comprising: decoding a single instruction into a decoded single instruction with a decoder of a processor core; and executing, in an execution unit of the processor core, the decoded single instruction that includes a source operand and a destination operand each having a same plurality of packed data elements and no other elements to calculate for each packed data element position of the source operand, other than a first packed data element position, a value of that packed data element minus a packed data element that is of immediate lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.