Patent ID: 9311999
Filing Date: 2016-04-12
CPC Classification: G11C

Claim Text:
1. A memory sense amplifier comprising: a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time; a second input configured to receive a reference signal; modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of the different memory states of the memory element at the different moments in time, wherein the modification circuitry comprises a plurality of transistors individually coupled with one of the first and the second inputs; supply circuitry configured to provide different bias signals to the transistors, the different bias signals corresponding to the different memory states of the memory element to be verified at the different moments in time; and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory states of the memory element at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory element at the different moments in time.