Patent ID: 9437449
Filing Date: 2016-09-06
CPC Classification: H01J,H01L

Claim Text:
1. A method of forming an integrated circuit, comprising the steps: forming a sacrificial silicon nitride feature on said integrated circuit; forming a surface layer of oxidized silicon on an exposed surface of said sacrificial silicon nitride feature; placing said integrated circuit in a two-step oxidized layer etch tool, so that a substrate of said integrated circuit is on a substrate base of said two-step oxidized layer etch tool, said substrate base being at a temperature less than 40° C.; generating a plasma in said two-step oxidized layer etch tool using a fluorine-containing gas, ammonia and an inert gas so as to produce fluorine radicals which adsorb onto said surface layer of oxidized silicon and react with said surface layer of oxidized silicon while said substrate is on said substrate base; raising said substrate off said substrate base proximate to a heated element of said two-step oxidized layer etch tool so that by-products of a reaction between said fluorine radicals and said surface layer of oxidized silicon are removed, said heated element being at a temperature above 90° C.; subsequently lowering said substrate onto said substrate base; and generating a plasma in said two-step oxidized layer etch tool using fluorine-containing reagents which are substantially free of ammonia so as to produce fluorine radicals which react with silicon in said sacrificial silicon nitride feature so as to remove at least a portion of said sacrificial silicon nitride feature, so that said integrated circuit is not exposed to an ambient containing more than 1 torr of oxygen between said step of raising said substrate off said substrate base and the instant step.