Patent ID: 9312193
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A semiconductor package structure, comprising: a substrate; a solder region; one or more dies bonded on the substrate through the solder region; and two or more stress relief structures, each stress relief structure of the stress relief structures being formed on or bonded onto a surface of the substrate and being disposed adjacent to at least one die of the one or more dies, wherein a first stress relief structure of the two or more stress relief structures has a different shape from a second stress relief structure of the two or more stress relief structures, wherein wherein the two or more stress relief structures individually comprise a material selected from the group consisting of a thermally conductive material, metal, tungsten, aluminum, aluminum alloy, polysilicon, silicide, tantalum, refractory metal, copper, copper alloy, gold, gold alloy, TaN, titanium, TiN, nickel, and combinations thereof.