Patent ID: 9431086
Filing Date: 2016-08-30
CPC Classification: G11C

Claim Text:
1. A memory circuit, comprising: a memory array having a plurality of memory blocks; a plurality of word lines disposed to correspond to the memory blocks; and a memory controller, outputting an access instruction and an access address to address the word lines for accessing the memory array, or outputting a refresh instruction and a refresh address to address the word lines for refreshing the memory array, wherein the memory controller performs a refresh operation on each of the memory blocks corresponding to each of the word lines at predetermined intervals; wherein the memory controller counts the number of times the access instructions have been output and determines whether the number equals a predetermined value or not; and wherein according to the determination result, the memory controller selects an address adjacent to the access address as the refresh address for the next refresh operation; a counting unit, counting the number of times the access instructions have been output, wherein the counting unit outputs a refresh flag and resets the number of times the access instructions have been output when the number of times the access instructions have been output equals the predetermined value; an instruction decoder coupled to the counting unit, receiving an instruction input, determining whether the instruction input is the access instruction or the refresh instruction, and outputting the access instruction or the refresh instruction; wherein if the instruction input is the access instruction, the instruction decoder informs the counting unit accumulating the number of times the access instructions have been output; a refresh address control unit coupled to the counting unit, receiving an access address, the refresh flag and the refresh instruction, and outputting the refresh address; and an address decoder and selector coupled to the refresh address control unit, receiving the access address, the refresh instruction and the refresh address, and addressing the word lines of the memory array according to the access address or the refresh address, wherein when the address decoder and selector does not receive the refresh instruction, the address decoder and selector decodes the access address to address the word lines of the memory array, and wherein when the address decoder and selector receive the refresh instruction, the address decoder and selector stop decoding the access address and address the word lines of the memory array according to the refresh address.