Patent ID: 9349455
Filing Date: 2016-05-24
CPC Classification: G11C,H01L

Claim Text:
1. A nonvolatile memory device, comprising: a memory cell array including a plurality of cell strings arranged in a first direction and a second direction, the plurality of cell strings being divided into a plurality of groups including a first group and a second group, each of the plurality of cell strings including a selection transistor and a plurality of nonvolatile memory cells connected in series and stacked on or above a substrate in a third direction that is perpendicular to both the first direction and the second direction and perpendicular to the substrate; a word line extending in the first direction, and connected to each of the plurality of cell strings; a selection line extending in the first direction and connected to the selection transistor of each cell string of the first group; a first pass transistor connected to one end of the word line; a second pass transistor connected to one end of the selection line; a third pass transistor connected to the other end of the selection line; and a decoder configured to drive the word line with a word line voltage via only one end of the word line, and to drive the selection line with a selection line voltage via both the one end and the other end of the selection line, wherein the word line voltage is driven through the first pass transistor, and the selection line voltage is driven through the second pass transistor and the third pass transistor.