Patent ID: 9330226
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. A method, executed by at least one processor of a computer, comprising: clustering two or more neighboring substrate contacts; combining the two or more neighboring substrate contacts into one equivalent substrate contact by calculating a position for the equivalent substrate contact; modeling electrical impedance between a first substrate contact and a second substrate contact in the presence of the equivalent substrate contact based on one of a horizontal impedance model and an L-shaped impedance model, wherein the first substrate contact, the second substrate contact and the two or more neighboring substrate contacts are substrate contacts in a layout design and/or particular areas of the layout design, and wherein the horizontal impedance model models electrical impedance for the first substrate contact and the second substrate contact in the presence of the equivalent substrate contact positioned on a line that passes through the first substrate contact and the second substrate contact, and wherein the L-shaped impedance model models electrical impedance for the first substrate contact and the second substrate contact in the presence of the equivalent substrate contact positioned on a line that passes through one of the first substrate contact and the second substrate contact and is perpendicular to a line passing through the first substrate contact and the second substrate contact; performing circuit simulation on a circuit associated with the layout design, wherein the circuit includes a parasitic element having the electrical impedance; and fabricating an integrated circuit based upon the layout design.