Patent ID: 9368221
Filing Date: 2016-06-14
CPC Classification: G11C,H03K

Claim Text:
1. A device for use with non-volatile memory, the device comprising: a first transistor of a first channel type coupled between first and second nodes, including a control gate supplied with a first control signal having a first phase; a second transistor of a second channel type different from the first channel type including a first terminal coupled to the first node, a second terminal coupled to a third node, a back gate connected to the first terminal thereof, and a control gate supplied with a second control signal having a second phase substantially opposite to the first phase; a third transistor of the second channel type including a first terminal coupled to the second node, a second terminal coupled to the third node, a back gate connected to the first terminal thereof, and a control gate supplied with the second control signal; and a protection circuit coupled between the first and second node so that the protection circuit, the second transistor and the third transistor are connected in series, the protection circuit being supplied with the first control signal.