Patent ID: 9230612
Filing Date: 2016-01-05
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising: a plurality of word lines extending in a first direction in or on a substrate; a plurality of bit lines crossing over the plurality of word lines; a plurality of bit line node contacts, each of the plurality of bit line node contacts connecting a corresponding bit line to the substrate, and each of the plurality of bit line node contacts having a width substantially equal to a width of the corresponding bit line; a plurality of storage node contacts between the plurality of bit lines and connected to the substrate, a distance between a first sidewall of a first of the plurality of storage node contacts and a corresponding first bit line adjacent to the first sidewall is substantially equal to a distance between a second sidewall of the first storage node contact and a second bit line adjacent to the second sidewall; and a plurality of storage node pads, each of the plurality of storage node pads being between the substrate and a corresponding storage node contact, each of the plurality of storage node pads having a width greater than a width of the corresponding storage node contact, and a sidewall of each of the plurality of storage node pads being aligned with a sidewall of the corresponding storage node contact.