Patent ID: 9250292
Filing Date: 2016-02-02
CPC Classification: G01R

Claim Text:
1. A testing system for testing semiconductor package stacking chips, comprising: a testing socket for loading a chip-under-test; a testing arm installed over the testing socket, for moving in the vertical direction; and a testing mechanism for moving to an upper position over the testing socket and leaving the upper position, the testing mechanism comprising a probe testing device, the probe testing device having a testing chip inside and a plurality of testing probes electrically connected to the testing chip, the plurality of testing probes extending toward the testing socket for contacting the chip-under-test loaded on the testing socket; wherein when the testing mechanism moves to the upper position between the testing socket and the testing arm, the testing arm moves downward in the vertical direction and presses down the testing mechanism thereby coercing the plurality of testing probes in the testing mechanism to closely abut against the chip-under-test, so that the testing chip inside the testing mechanism is electrically connected to the chip-under-test for forming a test loop; and wherein the testing mechanism is physically unattached to and independent from the testing arm, such that the moving of the testing mechanism to the upper position or leaving the upper position is independent from the moving of the testing arm in the vertical direction.