Patent ID: 9461131
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, comprising the steps: forming a trench pattern on a silicon substrate of the integrated circuit; etching a trench into the silicon substrate to a depth between 0.6 um and 6 um; removing the trench pattern; performing a plasma soft etch; growing a sacrificial oxide in dilute oxygen ambient at a temperature in the range of 1050° C. to 1250° C. to a thickness in the range of 10 nm to 50 nm; removing the sacrificial oxide by etching in dilute HF; growing a high quality trench oxide at a temperature in the range of 1050° C. to 1250° C. in an ambient of nitrogen, oxygen, and trans 1,2 dichloroethylene (TLC); annealing the high quality trench oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.; and depositing polysilicon to fill the trench.