Patent ID: 9437609
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A vertical channel-type 3D semiconductor memory device, comprising: a substrate; a multi-layer film formed by depositing alternating layers of at least one insulating layer and at least one electrode material layer on the substrate; a plurality of through-holes, which define respective channel regions, formed by etching the multi-layer film to the substrate; a plurality of gate stacks, each formed by depositing a barrier layer, a storage layer, and a tunnel layer in sequence on an inner wall of a respective one of the plurality of through-holes; a plurality of hollow channels, each formed by depositing and incompletely filling a channel material on a surface of the tunnel layer of a respective one of the plurality of gate stacks; a plurality of drains, each formed in a contact hole region for bit-line connection in a top portion of a respective one of the plurality of hollow channels; and a plurality of sources, each formed in a contact region between a respective one of the plurality of through-holes and the substrate in a bottom portion of a respective one of the plurality of hollow channels.