Patent ID: 9269634
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A method for forming a semiconductor device, comprising: forming an N-field effect transistor (NFET) gate region and a P-field effect transistor (PFET) gate region, wherein each gate region comprises a metal base layer and a dummy gate structure formed on the metal base layer, wherein the dummy gate structure of the NFET gate region comprises an N-type polysilicon (N-poly) material, wherein the dummy gate structure of the PFET gate region comprises a P-type polysilicon (P-poly) material, and wherein sidewall spacers are formed on sidewalls of the dummy gate structures of the NFET gate region and the PFET gate region; depositing a silicon nitride (SiN) liner over the NFET and PFET gate regions; depositing a dielectric layer over the SiN liner; etching the dielectric layer and the SiN liner to expose the dummy gate structure of the NFET region and the dummy gate structure of the PFET region; removing the dummy gate structure of the NFET gate region selective to the dummy gate structure of the PFET gate region, thereby forming an NFET gate hole which exposes the metal base layer of the NFET gate region; and filling the NFET gate hole with SiN material.