Patent ID: 9385090
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate comprising a plurality of wiring layers including at least one grounding wire, a plurality of pad electrodes on a surface thereof, and cut side surfaces; one or more semiconductor chips provided on the substrate; external connection terminals provided on an external surface of the substrate; a sealing resin layer on an upper surface of the substrate on which the semiconductor chips are provided, the sealing resin layer encapsulating the semiconductor chips and adjacent areas of the substrate; and a conductive shield layer covering the sealing resin layer and the cut side surfaces of the substrate, wherein portions of the wiring layers have cut planes which are exposed at one side of the cut side surfaces of the substrate including a cut plane of the grounding wire, which is electrically connected to the shield layer, and an area of the cut plane of the grounding wire is larger than an area of a cross section of the grounding wire parallel to the cut plane at a location of the grounding wire inward of the one of the cut side surfaces of the substrate, wherein the grounding wire includes a main wire that is formed of a first metal material, and a protective metal film that is formed of a second metal material having higher resistance to oxidation than the first metal material, the second metal material contacting at least a portion of the main wire, and wherein at the cut plane of the grounding wire, a cut plane of the main wire is covered with the protective metal film.