Patent ID: 9377660
Filing Date: 2016-06-28
CPC Classification: G02F,G09G

Claim Text:
1. A display device comprising: a pixel comprising: wherein on/off of the first transistor and on/off of the second transistor are controlled by a signal input to a scan line, wherein the first capacitor serves to hold a voltage between a potential of the first wiring and a common potential supplied by a Cs line, wherein the second capacitor serves to hold a voltage between a potential of the second wiring and the common potential, wherein one of a source and a drain of the first transistor is in contact with the first wiring, wherein the first pixel electrode is in contact with the first wiring, wherein one of a source and a drain of the second transistor is in contact with the second wiring, wherein the second pixel electrode is in contact with the second wiring, wherein one of a source and a drain of the third transistor is in contact with the second wiring, wherein the other of the source and the drain of the third transistor is in contact with the third wiring, wherein the first wiring is not overlapped with the second pixel electrode and the second wiring and the third wiring are not overlapped with the first pixel electrode, and wherein a ratio of a channel width to a channel length of the second transistor is larger than a ratio of a channel width to a channel length of the third transistor.