Patent ID: 9489259
Filing Date: 2016-11-08
CPC Classification: G06F,H03M,H04L

Claim Text:
1. A low density parity check (LDPC) encoder, comprising: first memory configured to store an LDPC codeword having a length of second memory configured to be initialized to 0; and a processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM), wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 2160, a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 3240, and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10800, wherein the sequence has a number of rows equal to a sum of a value obtained by dividing the length of the systematic part by a circulant permutation matrix (CPM) size corresponding to the PCM, and a value obtained by dividing the length of the first parity part by the CPM size, and wherein the sequence is represented by the following Sequence Table: