Patent ID: 9496511
Filing Date: 2016-11-15
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate having a thin film transistor, comprising: a substrate; source and drain electrodes on the substrate and spaced apart from each other; an organic semiconductor layer on the source electrode and the drain electrode; a gate insulating layer on the organic semiconductor layer, the gate insulating layer having substantially the same size as the organic semiconductor layer, the small organic semiconductor layer and the gate insulating layer including a first drain contact hole exposing a portion of the drain electrode; a gate electrode on the gate insulating layer; an auxiliary drain electrode contacting the portion of the drain electrode through the first drain contact hole; a passivation layer over the surface of the substrate including the gate electrode and the auxiliary drain electrode, the passivation layer including a second drain contact hole exposing the auxiliary drain electrode; and a pixel electrode on the passivation layer and contacting the auxiliary drain electrode through the second drain contact hole.