Patent ID: 9263517
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. An extra-thin semiconductor-on-insulator (ETSOI) layer comprising: a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; a plurality of recesses located within the distinct SOI regions; and an oxide cap over each of the plurality of recesses, wherein the at least three different thicknesses include: a first thickness of approximately 60-100 angstroms, a second thickness of approximately 25-60 angstroms, and a third thickness of approximately 5-25 angstroms, wherein the plurality of STIs are located over a portion of a buried insulator layer, and the plurality of distinct SOI regions are located over a distinct portion of the buried insulator layer than the plurality of STIs, and wherein each of the plurality of distinct SOI regions is located in a same lateral layer overlying the buried insulator layer, wherein one of the plurality of recesses has a distinct profile than a distinct recess in the plurality of recesses.