Patent ID: 9524991
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. An array substrate, comprising: a base substrate, and a thin film transistor and a storing capacitor provided on the base substrate, wherein the thin film transistor comprises a gate, a source, a drain and a gate insulation layer provided between the source and drain and the gate; the storing capacitor comprises a first plate, a second plate and a dielectric layer provided between the first plate and the second plate, wherein, both of the first plate and the second plate are formed of metal material; and the dielectric layer is formed of the same material as the gate insulation layer; and the array substrate further comprises: a buffer layer provided above the source and the drain, the buffer layer partially covers the source and is provided with a source via hole, and the buffer layer also partially covers the drain and is provided with a drain via hole; and an active layer provided above the buffer layer, and the active layer is connected to the source through the source via hole and connected to the drain through the drain via hole.