Patent ID: 9391202
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor layer extending in a first direction, the semiconductor layer including a pair of source/drain regions and a channel region extending between the pair of source/drain regions; a gate extending in a second direction on the semiconductor layer to cover the channel region; a gate dielectric layer interposed between the channel region and the gate; an insulating capping layer covering a top surface of the gate; a corner insulating spacer having a first surface and a second surface, the first surface extending in the second direction along a side wall of the gate, the first surface covering from a side portion of the gate dielectric layer to at least a portion of the side wall of the gate, and the second surface covering a portion of the semiconductor layer; and an outer portion insulating spacer covering the side wall of the gate above the corner insulating spacer, the outer portion insulating spacer having a smaller dielectric constant than the corner insulating spacer, wherein each of the pair of source/drain regions includes a deep source/drain region and a source/drain extension region extending from the deep source/drain region, and the outer portion insulating spacer has a vertical surface contacting a sidewall of the insulating capping layer, and a horizontal surface contacting a top surface of the source/drain extension region.