Patent ID: 9519481
Filing Date: 2016-12-13
CPC Classification: G06F,H05K

Claim Text:
1. A method comprising: generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces; generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph; running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results; and generating a second assembly pattern file, for use with a second ISA/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph; wherein: the generation of the first assembly pattern file uses a first application binary interface data set, specific to the first ISA/microarchitecture set, so that the assembly pattern file can run on the first ISA/microarchitecture set; and the generation of the second assembly pattern file uses a second application binary interface data set, specific to the second ISA/microarchitecture set, so that the assembly pattern file can run on the second ISA/microarchitecture set.