Patent ID: 9349635
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, the method comprising: providing a substrate, wherein the substrate comprises an electrical contact disposed therein; forming a first dielectric layer over the substrate and the electrical contact; patterning a recess through the first dielectric layer and into the substrate; patterning a metal-containing layer over the first dielectric layer to form a patterned metal-containing layer, wherein the recess is patterned through the first dielectric layer and into the substrate prior to patterning the metal-containing layer over the first dielectric layer, wherein at least a first portion of the patterned metal-containing layer is disposed over the first dielectric layer, wherein a second portion of the metal-containing layer has a landing surface generally disposed along a common plane with a contact surface of the electrical contact, and wherein the patterned metal-containing layer is absent in regions of the first dielectric layer over the electrical contact; forming a second dielectric layer over the patterned metal-containing layer; etching a first via in the first dielectric layer and the second dielectric layer over the electrical contact and a second via in the second dielectric layer over the patterned metal-containing layer, wherein the electrical contact defines a bottom of the first via and the patterned metal-containing layer defines a bottom of the second via; filling the first via and the second via with an electrically-conductive material to form a first interconnect in electrical communication with the electrical contact and a second interconnect in electrical communication with the patterned metal-containing layer.