Patent ID: 9412454
Filing Date: 2016-08-09
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device comprising: a plurality of semiconductor members arranged along a first direction and a second direction, the second direction crossing the first direction, and the plurality of semiconductor members extending in a third direction crossing a plane including the first direction and the second direction; a plurality of electrode members extending in a direction crossing the third direction; a charge accumulation member provided between the semiconductor member and the electrode member, and the charge accumulation member being capable of accumulating charge; a memory unit configured to retain information, the information indicating a memory cell belongs to a first group or a second group, the memory cell being formed at each crossing portion of the semiconductor member and the electrode member via the charge accumulation member; and a control unit configured to perform a first step and a second step when reducing the charge accumulated in the charge accumulation member,