Patent ID: 9298423
Filing Date: 2016-03-29
CPC Classification: G06F

Claim Text:
1. A method for testing a property of a sequence of at least k n-state symbols with n an integer greater than 1 and k an integer greater than 2, each n-state symbol being represented by a signal, comprising: a processor selecting a first n-state inverter from a plurality of n-state inverters and implementing the first n-state inverter in a shift register of p n-state shift register elements with feedback with p an integer greater than 1 and at least one n-state switching function; the processor generating n-state symbols in the sequence by a sequence generator that is defined by a first configuration that includes the n-state feedback shift register of p n-state shift register elements, the first n-state inverter and the at least one n-state switching function, wherein each generated n-state symbol corresponds with a content of the shift register of p n-state symbols, wherein the processor generates a first n-valued symbol and stores a corresponding first content of the shift register of p n-state symbols in a memory; the processor generating a k the processor comparing the k