Patent ID: 9355971
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A fuse structure formed in a semiconductor device and connected in series with an input-output pad of the semiconductor device, the semiconductor device being fabricated using a fabrication process including N metal layers from a bottommost metal layer being the first metal layer to a topmost metal layer being the Nth metal layer, the fuse structure comprising: a thin film resistive element formed on and insulated from a semiconductor body, the thin film resistive element having a first end and a second end, the second end being electrically connected to a circuit of the semiconductor device; one or more metal pads formed using one or more metal layers from the first metal layer to the (N-2)th metal layer, a first metal pad formed in the first metal layer being connected through contacts to the first end of the thin film resistive element, each metal pad being connected to an adjacent metal pad using vias, the vias and the one or more metal pads being stacked in a vertical direction above the contacts and the first end of the thin film resistive element, the one or more metal pads being formed of a material having a melting point much lower than the melting point of the thin film resistive element; a metal fuse element having a first end connected through vias to the input-output pad and a second end connected through vias to the metal pad formed in the (N-2)th metal layer, the input-output pad being formed using the topmost metal layer and the metal fuse element being formed using the (N-1)th metal layer, wherein the vias, the one or more metal pads and the contacts form the fuse link of the fuse structure, the fuse structure protects the input-output pad of the semiconductor device from an electrical overstress event by breaking of the fuse link in response to an electrical overstress event.