Patent ID: 9329210
Filing Date: 2016-05-03
CPC Classification: G01R,G05F,H03K

Claim Text:
1. An integrated circuit, comprising: a first reference voltage generator for generating a first reference voltage signal; a voltage regulator for generating a first supply voltage signal; a reset controller connected to the first reference voltage generator for stabilizing the first reference voltage signal in a first predetermined time period, and generating a power down signal after the first predetermined time period; and a first voltage monitoring circuit connected to the first reference voltage generator, the voltage regulator, and the reset controller, for receiving the first reference voltage signal, the first supply voltage signal, and the power down signal, respectively, and generating a first voltage monitor signal at a first logic state when a voltage level of the first supply voltage signal exceeds a voltage level of the first reference voltage signal during the first predetermined time period and at second logic state after the first predetermined time period, whereby the integrated circuit is configured in a safe state after the first predetermined time period.