Patent ID: 9413525
Filing Date: 2016-08-09
CPC Classification: H03L,H04B,H04L

Claim Text:
1. A semiconductor device having a serdes (serializer/deserializer) that mutually convert serial data and parallel data, comprising: one or more pairs of transmitter circuits and receiver circuits; and a PLL (phase locked loop) which is connected with one or more of the transmitter circuits and one or more of the receiver circuits, and includes an SSC (spread spectrum clocking) controller, and outputs an SSC clock signal, wherein each of the transmitter circuits receives the SSC clock signal subjected to the spread-spectrum frequency modulation from the PLL, and conducts parallel/serial conversion on the basis of the SSC clock signal, to thereby output the serial data that has been subjected to the spread-spectrum frequency modulation, wherein each of the receiver circuits, comprising: a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal; a frequency tracking loop that conducts a tracking control to reduce a frequency deviation between a frequency of the input data and a frequency of the extracted clock signal on the basis of a result of integrating a detection result of the phase detector together; and a phase interpolator that receives the SSC clock signal subjected to spread-spectrum frequency modulation from the PLL, adjusts a phase of the SSC clock signal on the basis of a detection result of the frequency deviation in the frequency tracking loop, and supplies the SSC clock signal to the phase detector as the extracted clock signal, wherein the frequency tracking loop receives frequency modulation information corresponding to the SSC clock signal subjected to the spread-spectrum frequency modulation from the PLL, corrects the frequency deviation on the basis of the frequency modulation information, and reduces the frequency modulation of the clock signal.