Patent ID: 9293083
Filing Date: 2016-03-22
CPC Classification: G09G

Claim Text:
1. A pixel circuit comprising: a first pixel sub-circuit and a second pixel sub-circuit, as well as an initialization module and a data voltage writing module connected to the first pixel sub-circuit and the second pixel sub-circuit, wherein the initialization module is connected to a reset signal terminal and a low potential terminal, and is configured to initialize the first pixel sub-circuit and the second pixel sub-circuit under a control of a reset signal inputted from the reset signal terminal; the data voltage writing module is connected to a data signal line and a gate signal terminal, and is configured to firstly write a first data voltage to the first pixel sub-circuit and the second pixel sub-circuit under a control of a signal inputted from the gate signal terminal and to compensate for a driving module of the second pixel sub-circuit, and then to write a second data voltage to the first pixel sub-circuit and compensate for a driving module of the first pixel sub-circuit; wherein the first pixel sub-circuit comprises a first driving module and a first threshold compensation module, the first threshold compensation module is connected to the first driving module and is configured to perform threshold voltage compensation on the first driving module; the first threshold compensation module comprises a first storage capacitor and a fourth transistor, and the first driving module comprises a fifth transistor, wherein one terminal of the first storage capacitor is connected to a high voltage level signal line, and the other terminal thereof is connected to a source of the fourth transistor; a gate of the fourth transistor is connected to a gate signal terminal, a drain of the fourth transistor is connected to a drain of the fifth transistor, and the source of the fourth transistor is connected to a gate of the fifth transistor; the gate of the fifth transistor is connected to the initialization module, and a source of the fifth transistor is connected to the data voltage writing module; the second pixel sub-circuit comprises a second driving module and a second threshold compensation module; the second threshold compensation module is connected to the second driving module, and is configured to perform threshold voltage compensation on the second driving module; wherein the second threshold compensation module comprises a second storage capacitor and a second transistor, and the second driving module comprises a sixth transistor; one terminal of the second storage capacitor is connected to the high voltage level signal line, and the other terminal thereof is connected to a source of the second transistor; a gate of the second transistor is connected to a switching control signal line, and a drain of the second transistor is connected to the initialization module; a gate of the sixth transistor is connected to the source of the second transistor, and a source of the sixth transistor is connected to the data voltage writing module.