Patent ID: 9257454
Filing Date: 2016-02-09
CPC Classification: G02F,H01L

Claim Text:
1. A thin film transistor array substrate comprising: a thin film transistor formed on a substrate; a common wiring formed on said substrate; a first interlayer insulating film formed on said thin film transistor and said common wiring; a second interlayer insulating film formed on said first interlayer insulating film; a common electrode formed on said second interlayer insulating film; a third interlayer insulating film formed on said common electrode; and a pixel electrode formed on said third interlayer insulating film, wherein said pixel electrode is connected to a drain electrode of said thin film transistor via a first aperture formed on said second interlayer insulating film, a second aperture that includes a bottom portion of said first aperture and is formed on said common electrode, and a third aperture that is included in the bottom portion of said first aperture and is formed on said first interlayer insulating film and said third interlayer insulating film, said common electrode is connected indirectly to said common wiring via a fourth aperture formed on said second interlayer insulating film, and a fifth aperture that is included in a bottom portion of said fourth aperture and is formed on a first interlayer insulating film, at least a part of said common electrode is exposed from said third interlayer insulating film on an inclined plane of an inner wall of said fourth aperture so as to be formed on said inner wall of said fourth aperture, said common electrode and said common wiring are connected via a contact electrode that is connected between a portion of said common electrode formed on the inner wall of said fourth aperture and said common wiring exposed on said fifth aperture, and is made of a conductive film on the same layer as said pixel electrode.