Patent ID: 9372800
Filing Date: 2016-06-21
CPC Classification: G06F

Claim Text:
1. A method of providing memory coherence between multiple chip devices of a multi-chip system, the method comprising: maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies of a data block, the data block stored in a memory associated with one of the multiple chip devices, the one or more copies of the data block residing in one or more chip devices of the multi-chip system; receiving, by the first chip device, a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices; and in response to the message received, executing, by the first chip device, a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received; wherein the data block is stored in a memory attached to the first chip device and the message is indicative of a state, maintained at the second chip device, of a copy of the data block residing in the second chip device.