Patent ID: 9495285
Filing Date: 2016-11-15
CPC Classification: G06F,G11C

Claim Text:
1. A timing device comprising: a timing device circuit for generating at least one timing signal: a static random access memory (SRAM) coupled to the timing device circuit; a read only memory (ROM) having a first timing device configuration stored therein; a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration; and selection logic having an output coupled to the SRAM and having a first input coupled to the ROM and a second input coupled to the OTP NVM, the selection logic operable to receive input indicating whether the SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.