Patent ID: 9355733
Filing Date: 2016-05-31
CPC Classification: G11C

Claim Text:
1. A method of operating a memory system including a nonvolatile memory device having a plurality of multi-level cells and a memory controller controlling a read operation on the nonvolatile memory device, the method comprising: performing a first sensing operation to sense whether each of the multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected word line; supplying a pre-charge voltage only to bit lines corresponding to multi-level cells that have been sensed as assuming the off-cell state in response to the first read voltage; and performing a second sensing operation with the supplied pre-charge voltage to sense whether each of the multi-level cells that have been sensed as assuming the off-cell state assumes an on-cell state or an off-cell state in response to a second read voltage applied to the selected word line.