Patent ID: 9312994
Filing Date: 2016-04-12
CPC Classification: H04L

Claim Text:
1. A downlink physical layer processing system, comprising: a transport block segmentation processor configured to receive a transport block and to generate segmented blocks from the transport block; an encoder configured to encode the segmented blocks to form encoded blocks; a mapping processor configured to map the encoded blocks to symbols corresponding to resource elements to generate mapped symbols for transmission over a transmission medium; and a transmission signal generator configured to process the mapped symbols to generate transmission signals for transmission over the transmission medium; wherein the mapping processor is configured to map the encoded blocks to the symbols in response to a control signal generated by the transmission signal generator; wherein the transmission symbols comprise orthogonal frequency division multiplexing symbols; and wherein the mapping processor receives encoded code blocks at a rate that is based on processing of transmission time intervals by the encoder and generates symbols from the encoded code blocks at a rate that is based on a rate at which symbols are processed by the transmission symbol generator to generate the transmission symbols.