Patent ID: 9507898
Filing Date: 2016-11-29
CPC Classification: G06F

Claim Text:
1. A method of data processing, comprising: prior to a simulation of an integrated circuit design using a simulation model running on a computer: the computer identifying a storage element for storing a logic value in the simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its logic value forced, wherein the storage element has an associated clock signal providing a timing reference for updates to the logic value held in the storage element; in response to identifying the storage element, recording in a database an indication of the storage element and an identification of the associated clock signal including a clock edge and a period of the associated clock signal, the associated clock signal period being a number of simulation cycles; and during simulation of the integrated circuit design using the simulation model running on the computer: in response to receiving an input indicating the logic value of the storage element is to be forced, determining by reference to the database, an active edge of the associated clock signal, and determining whether or not forcing of the logic value is mistimed with reference to the active edge of the associated clock signal; and in response to a determination that the forcing of the logic value as indicated by the input is mistimed with reference to the active edge of the associated clock signal, automatically modifying the timing of forcing of the logic value of the storage element for a number of simulation cycles with respect to the active edge of the associated clock signal so that forcing of the logic value is not mistimed, and outputting an indication that forcing of the logic value is mistimed.