Patent ID: 9293577
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A transistor comprising: a source region including a first impurity region of a first impurity type implanted into a well region, also of the first impurity type, implanted on a substrate and a third impurity region of an opposite second impurity type abutting the first impurity region, and a fourth impurity region of the second impurity type surrounding the first impurity region and the third impurity region, the fourth impurity region having a lower doping concentration than the third impurity region; a drain region including a second impurity region of the first impurity type implanted into the substrate, the drain region further including a fifth impurity region of the first impurity type surrounding the second impurity region, the fifth impurity region having a lower doping concentration than the second impurity region; an intrinsic diode between the fourth impurity region and the drain region, the intrinsic diode formed by the fourth impurity region of the second impurity type and the well region of the first impurity type; and a gate including an oxide layer formed over the substrate and a conductive material formed over the oxide layer, the oxide layer comprising a first side and a second side, the first side formed over a portion of the first impurity region and the second side formed over a portion of the second impurity region, the first side having a thickness such that a turn-on voltage of the transistor is less than a forward bias turn-on voltage of the intrinsic diode; wherein: a thickness of the first side of the oxide layer is greater than zero and less than 70 Å.