Patent ID: 9374110
Filing Date: 2016-06-21
CPC Classification: H03M,H04L

Claim Text:
1. A multi-mode decoder implementation method, comprising: storing to-be-decoded data according to a predetermined method; performing an interleaving processing on the stored to be decoded data to obtain an interleaving address; and based on the interleaving address, using a Radix-4 algorithm architecture, multiplexing a set of maximum a posterior (MAP) decoding units in different standards, and using a parallel processing method to perform a MAP iterative decoding processing on the to-be-decoded data in accordance with standard types; wherein, said storing to-be-decoded data according to a predetermined method comprises: in the LTE standard, respectively storing input to-be-decoded data into four groups of RAMs with a depth of 1536 in accordance with processing units (PUs) where the to-be-decoded data are located; wherein each group of RAMs with the depth of 1536 is composed of two RAMs with the depth of 768, which respectively store to-be-decoded data of each PU according to even and odd addresses of each group; in the UMTS standard and the TD-SCDMA standard, for the input to-be-decoded data, according to the even and odd addresses of each group, in accordance with a length of code block, using a storing method that a group of RAMs with the depth of 1536 is filled up and then a next group of RAMs with the depth of 1536 is filled, wherein each group of RAMs with the depth of 1536 is composed of two RAMs with the depth of 768, and one RAM with the depth of 768 corresponds to data with the odd address, and the other RAM with the depth of 768 corresponds to data with the even address; and in the WiMAX standard, storing 600 bit pairs corresponding to A/B of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536, storing 600 bit pairs corresponding to Y of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536, and storing 600 bit pairs corresponding to W of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536.