Patent ID: 9292425
Filing Date: 2016-03-22
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; a read circuit configured to read data from selected memory cells in the memory cell array; a write circuit configured to write data into selected memory cells in the memory cell array; an operation unit configured to perform an operation on read data obtained by the read circuit according to operation assignment information applied through an address line when entering a modified read mode; and a control circuit configured to manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit into the selected memory cells in the modified read mode, wherein during the modified read mode, a second input address identifying an operator and indicating an address storing a second operand is received after a first input address indicating an address storing a first operand to be applied to the operation unit, wherein the second input address comprises a first part that identifies the operator and a second other part that indicates the address storing the second operand, and the second part is a column offset with respect to the first input address.