Patent ID: 9502650
Filing Date: 2016-11-22
CPC Classification: G11C,H01L

Claim Text:
1. An apparatus comprising: a memory cell comprising: a semiconductor-oxide-based, non-silicon selector switch in direct contact with the memory cell; a sealing layer in contact with both the memory cell and the semiconductor-oxide-based, non-silicon selector switch; a plurality of dielectric layers that partially surround the memory cell, the semiconductor-oxide-based, non-silicon selector switch, and the sealing layer, wherein the plurality of dielectric layers are in direct contact with at least the memory cell and the sealing layer, and wherein the sealing layer separates adjacent dielectric layers of the plurality of dielectric layers; a word line conductive plug located on the sealing layer and configured to allow electrical access between the semiconductor-oxide-based, non-silicon selector switch and a word line; a bit line conductive plug located on the memory cell and configured to allow electrical access between the memory cell and a bit line; a first diffusion barrier layer at least partially surrounding the word line conductive plug; and a second diffusion barrier at least partially surrounding the bit line conductive plug.