Patent ID: 9385697
Filing Date: 2016-07-05
CPC Classification: H03F,H03K,H04B

Claim Text:
1. A spurious signal rejection (SSR) direct digital synthesizer (DDS) comprising: a) a first DDS circuit comprising: b) a second DDS circuit comprising: c) a tracking logic module having a first input and a second input and an output, the first input of the tracking logic module coupled to the second output of the first modulo-M counter, the second input of the tracking logic module coupled to the second output of the modulo-Y counter, the output of the tracking logic module being 1 if the second output of the modulo-M counter is 1 and the second output of the modulo-Y counter is a zero, and the output of the tracking logic module otherwise being a zero if the second output of the modulo-M counter is a zero and the second output of the modulo-Y counter is 1.