Patent ID: 9430348
Filing Date: 2016-08-30
CPC Classification: G06F

Claim Text:
1. A scalable test platform comprising: one or more PCIe-based event fabrics; one or more CPU subsystems coupled to the one or more PCIe-based event fabrics and configured to execute an automated test process; one or more instrument subsystems externally coupled to the one or more PCIe-based event fabrics and configured to interface one or more devices under test, obtain captured test data from the one or more devices under test and store the captured test data within at least one memory subsystem of at least one of the one or more instrument subsystems, wherein the one or more instrument subsystems is one or more instrument cards, wherein the one or more instrument cards include a first set of one or more direct memory access engines configured to write the captured test data directly to a remote memory system accessible by one or more CPU subsystems coupled to the one or more PCIe-based event fabrics for processing by the one or more CPU subsystems, and based upon a size of the captured test data, at least one of the one or more instrument subsystems is further configured to allow a second set of one or more direct memory access engines within one or more digital signal processing subsystems externally coupled to the one or more PCIe-based event fabrics to obtain the captured test data stored within at least one of the one or more instrument subsystems via a PCIe interface, process the captured test data obtained from within at least one of the one or more instrument subsystems to generate a result set, store the result set, and write the result set directly to the remote memory system accessible by one or more CPU subsystems coupled to the one or more PCIe-based event fabrics; and wherein the one or more PCIe-based event fabrics include one or more PCIe switches, the one or more PCIe switches configured to interface the one or more CPU subsystems with the one or more instrument cards, wherein the one or more instrument cards is separate from each of the one or more PCIe switches.