Patent ID: 9268486
Filing Date: 2016-02-23
CPC Classification: G06F,G11C

Claim Text:
1. An information processor comprising: an information processing sub-system; and a plurality of memory sub-systems performing data communication with the information processing sub-system, wherein: the information processing sub-system has an information processing circuit for processing a graph according to graph processing instructions, the memory sub-system has a first memory, a second memory having reading and writing latencies longer than those of the first memory, and a memory controller for controlling data transfer between the first memory and the second memory, in graph data to be subjected to the processing of the graph, to each of the vertices of the graph, an ID for uniquely specifying each of the vertices is assigned, and in the case that the ID assigned to one of the vertices is known, it is possible to specify where the IDs of other vertices relating to the vertex are located in an address space, and the graph data is stored in two or more different memory sub-systems and has a plurality of data blocks, at least one pair of relating vertices of the graph meets the following condition: the memory sub-system storing one vertex of a pair is different from the memory sub-system storing the other vertex of a pair, the data block is all or part of data corresponding to an address identified by analyzing the ID of the one vertex using the memory controller, and at least the ID of the one vertex is recorded therein, the memory controller has a function of storing the graph data to be processed into the second memory, a preloading function of transferring the plurality of data blocks from the second memory to the first memory, and a function of generating additional information which is necessary for another memory controller of a different memory sub-system to take over the preloading function from the said memory controller, and by using the preloading function, the memory controller: autonomously analyzes the ID of at least one vertex included in one data block A of the data blocks, calculates the address of at least one data block B to be required next by the information processing circuit, and transfers the data block B from the second memory to the first memory, then analyzes the ID of at least one vertex included in the data block A or block B transferred previously from the second memory to the first memory or included in a data block C different from the data blocks A and B, calculates the address of at least one data block D to be required next by the information processing circuit, and transfers the data block D from the second memory to the first memory, and then similarly transfers a plurality of data blocks from the second memory to the first memory.