Patent ID: 9350328
Filing Date: 2016-05-24
CPC Classification: H03K

Claim Text:
1. A ring oscillator circuit comprising a plurality of stages operably coupled output-to-input in a ring configuration; at least one of the stages of the ring oscillator circuit comprises a frequency tuning stage, the at least one frequency tuning stage comprising an inverting logic gate and a delay component; the delay component comprising: a first capacitive component comprising a first terminal operably coupled to an output of the inverting logic gate and a second terminal operably coupled to a first reference voltage at least when the ring oscillator is disabled, the first reference voltage comprising one of a high reference voltage and a low reference voltage; and at least one further capacitive component comprising a first terminal operably coupled to the output of the inverting logic gate and a second terminal selectively couplable to the first reference voltage and a second reference voltage, the second reference voltage comprising the other of the high reference voltage and the low reference voltage; wherein the second terminal of the at least one further capacitive component is arranged to be operably coupled to the first reference voltage when the ring oscillator is enabled, and operably coupled to the second reference voltage when the ring oscillator is disabled.