Patent ID: 9406860
Filing Date: 2016-08-02
CPC Classification: G01K,H01L

Claim Text:
1. A wafer level package structure for temperature sensing elements, comprising: a wafer cover which is formed of an infrared penetrable material, the wafer cover having a plurality of package walls, and the plurality of package walls forming a plurality of first grooves and a plurality of second grooves in the wafer cover; and a substrate comprising a plurality of chip areas, a plurality of soldering areas, and a plurality of pin areas, a plurality of temperature sensing chips being respectively disposed in the plurality of chip areas corresponding to the plurality of first grooves, each of the plurality of package walls being soldered with a corresponding one of the plurality of soldering areas, the substrate and the plurality of first grooves forming a plurality of vacuum sealed spaces respectively in the plurality of chip areas, and the plurality of pin areas being cut to form a plurality of packaging devices of temperature sensing elements and corresponding to the plurality of second grooves.