Patent ID: 9324440
Filing Date: 2016-04-26
CPC Classification: G11C,H01L

Claim Text:
1. A method for operating a nonvolatile memory device including a plurality of strings arranged in rows and columns on a substrate, each string including at least one ground select transistor, a plurality of memory cells and at least one string select transistor sequentially stacked on the substrate, the method comprising: erasing memory cells of the plurality of strings; performing an erasure verification by a unit of each row with respect to the memory cells of the plurality of strings; and erasing first memory cells of an erasure failed row and inhibiting erasure of second memory cells of an erasure passed row, such that a first voltage of a first ground select line connected to a first ground select transistor of the erasure failed row increases differently during an erase operation from a second voltage of a second ground select line connected to a second ground select transistor of the erasure passed row.