Patent ID: 9367247
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A device, comprising: a hybrid controller configured to manage data transfers between a host processor and a secondary memory, the secondary memory configured to serve as a cache for a primary memory, the primary memory including a memory space corresponding to host logical block addresses (LBAs), the hybrid controller configured to: receive incoming memory access requests from the host processor, the memory access requests including a range of host LBAs; route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, comprising: map the range of host LBAs directly into clusters of the secondary memory; transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of secondary memory; route the outgoing memory access requests from the incoming queues into a set of outgoing queues; and access the secondary memory using the outgoing memory access requests.