Patent ID: 9508438
Filing Date: 2016-11-29
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; a peripheral circuit unit configured to perform a program operation with respect to a memory cell selected from the plurality of memory cells, wherein first to third program voltage applying operations and first to third verifying operations are alternatively performed; and a control logic configured to control the peripheral circuit unit to perform the first to third program voltage applying operations and the first to third verifying operations and to increase a second program voltage applied during the second program voltage applying operation more than a first program voltage applied during the first program applying operation by a first step voltage and a third program voltage applied during the third program voltage applying operation more than the second program voltage by a second step voltage, wherein a first verifying voltage used in the first verifying operation has a voltage value at or around a half (½) point of a threshold voltage distribution width of the memory cells after the first program voltage applying operation is performed.