Patent ID: 9519482
Filing Date: 2016-12-13
CPC Classification: G06F

Claim Text:
1. A processor coupled to a memory system, the processor comprising: a fetch stage that causes a sequence of instructions to be fetched from the memory system, wherein the sequence of instructions includes a first instruction and a second instruction; a decode stage that first decodes the first instruction and then decodes the second instruction, wherein the decode stage can decode skip instructions; a register file read stage coupled to the decode stage, wherein the register file read stage includes a plurality of flag bits and a plurality of predicate bits; and an execute stage that can carry out an instruction operation of an instruction, wherein the second instruction defines an instruction operation to be performed when the second instruction is executed by the processor, wherein if the first instruction is a skip instruction and if a predicate condition is satisfied then the instruction operation of the second instruction is not carried out by the execute stage even though the second instruction was decoded by the decode stage, wherein the predicate condition for the skip instruction is specified by values of the predicate bits, and wherein the predicate condition is a specified function of values of at least one of the plurality of flag bits.