Patent ID: 9472423
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. During fabrication of a semiconductor device on a crystal substrate, the semiconductor device having source and drain regions, with a channel between the source and drain regions and a gate conductor positioned above the channel, a method for suppressing the formation of leakage-promoting defects in a crystal lattice due to dopant implantation in the lattice, comprising: providing impurity atoms within the substrate, more deeply than the source and drain regions within the lattice, the impurity atoms being selected to impose a compressive stress on the crystal lattice, at least some of the impurity atoms being directly below at least part of the gate conductor; implanting dopant atoms into the lattice; and after implanting the dopant atoms into the lattice, annealing the lattice to thereby cause compressive stress exerted by the impurity atoms on the lattice, including those of the impurity atoms directly below at least part of the gate conductor, to emit interstitial defect atoms from a region containing the impurity atoms.