Patent ID: 9310430
Filing Date: 2016-04-12
CPC Classification: G01R

Claim Text:
1. A semiconductor integrated circuit comprising: a decoding circuit configured to decode one or more test source signals and generate a plurality of test decoding signals; a transmission circuit configured to transmit the plurality of test decoding signals as a plurality of test mode group signals in response to a test enable signal, such that when the test decoding signals different from each other are sequentially activated, the transmission circuit outputs a corresponding newly-activated test mode group signal while maintaining an activation state of a previously-activated test mode group signal; and a test mode signal output circuit configured to output a plurality of test mode signals corresponding to a plurality of test mode groups, respectively, in response to the plurality of test mode group signals and one or more test mode select signals, wherein test modes belonging to different test mode groups are concurrently entered due to the corresponding newly-activated test mode group signal being output and the activation state of the previously-activated test mode group signal being maintained, and any test modes belonging to a same test mode group are selectively reset.