Patent ID: 9378967
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a stacked microelectronic unit, comprising: aligning saw lanes of a first wafer with saw lanes of a second wafer such that a first saw lane of the first wafer is positioned above a corresponding first saw lane of the second wafer and long dimensions of the first saw lanes extend in a first direction, the first and second wafers comprising first and second microelectronic elements, respectively, wherein a first trace electrically coupled with a contact of the first microelectronic element extends in a second direction parallel to a major surface of the first wafer towards the first saw lane of the first wafer, and a second trace electrically coupled with a contact of the second microelectronic element extends in the second direction towards the first saw lane of the second wafer, and the first trace is offset in the first direction from the second trace closest to the first trace in the first direction; forming a notch including at least partially cutting through the aligned first saw lanes of the first and second wafers in the first direction, wherein the first and second traces are exposed at a wall of the notch; and forming a first lead of electrically conductive material on the wall of the notch in contact with the first trace but not in contact with the second trace, and forming a second lead of electrically conductive material extending on the wall of the notch in contact with the second trace but not in contact with the first trace; and severing the first and second wafers to form a stacked microelectronic including the first and second microelectronic elements and the first and second leads, each lead electrically coupled with a respective contact of the first or the second microelectronic element through the first trace or the second trace, respectively.