Patent ID: 9354891
Filing Date: 2016-05-31
CPC Classification: G06F

Claim Text:
1. A processor, comprising: an instruction issue unit configured to issue vector program instructions for execution, where each vector program instruction operates on one or more vectors, each vector including a plurality of data elements, wherein each vector program instruction operates on one of a plurality of possible element sizes, wherein the plurality of possible element sizes includes a maximum element size; and a functional unit configured to receive a single instance of a given vector program instruction that operates on the maximum element size, and to concurrently operate on a plurality of data elements of the given vector program instruction having the maximum element size; wherein the functional unit is further configured to concurrently receive a plurality of vector program instructions that each operate on an element size that is less than the maximum element size, and to concurrently operate on data elements of two or more of the plurality of vector program instructions that operate on less than the maximum element size, such that the plurality of vector program instructions share execution resources of the functional unit that would be underutilized by execution of a single vector program instruction that operates on less than the maximum element size; and wherein a maximum number of data elements per vector on which the functional unit is configured to concurrently operate is independent of a number of vector program instructions the functional unit is configured to concurrently execute.