Patent ID: 9525027
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. A method comprising: obtaining a structure comprising a plurality of parallel silicon fins adjoining an electrically insulating layer and a dummy gate extending across a plurality of the silicon fins, the fins defining a channel region having a first conductivity type beneath the dummy gate, a source region on a first side of the dummy gate, and a drain region on a second side of the dummy gate; diffusing germanium into the channel region of the structure to form a germanium gradient within the channel region having an increasing germanium content in the direction of the drain region; removing the drain region; removing a portion of the electrically insulating layer beneath the drain region; epitaxially growing a silicon region on the second side of the dummy gate and from the fins within the channel region subsequent to forming the germanium gradient; doping the silicon region such that the silicon region has a second conductivity type opposite to the first conductivity type; replacing the dummy gate with a gate structure operatively associated with the channel region; and forming electrical connections to the gate structure and the silicon region.