Patent ID: 9406472
Filing Date: 2016-08-02
CPC Classification: B81B,B81C,H01H,H01L,Y10S,Y10T

Claim Text:
1. A method comprising forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process, wherein the reverse damascene process comprises forming a resist on an insulator layer, which is patterned to form an opening with edges of the resist overlapping an underlying silicon layer used to form one of the at least one MEMS cavity, and planarizing the insulator layer with the underlying silicon layer, and further comprising: forming and patterning an electrode layer over the underlying silicon layer; forming and patterning an insulator layer over the electrode layer, wherein the patterning includes forming a via to expose a portion of the electrode layer; forming and patterning an upper electrode on the insulator layer, a portion of the upper electrode being in contact with the electrode through the via; forming an insulator layer over the upper electrode layer; and forming a via in the insulator layer to expose the underlying silicon layer.