Patent ID: 9305936
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a nonvolatile semiconductor memory device including a semiconductor substrate; a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of the semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate; and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively, wherein each of the first to n-th NAND strings includes memory cells connected in series, each of the memory cells includes a charge storage layer and a control gate electrode, the charge storage layers of the memory cells are separated from one another, and the upper insulating layer includes an oxide or a nitride of an element selected from a group of Al, Hf, Ta, Ti, and W, the method comprising: forming a sidewall mask layer on a sidewall of a hard mask layer as the upper insulating layer; forming the stacked layer structure by anisotropic etching using the hard mask layer and the sidewall mask layer as a mask; forming a charge storage material on a surface of the stacked layer structure in the third direction; removing the sidewall mask layer after forming the charge storage material; forming a control gate material on the surface of the stacked layer structure in the third direction after removing the sidewall mask layer; forming a gate mask layer on the stacked layer structure and the control gate material; forming the control gate electrode of each of the memory cells by patterning the control gate material using the gate mask layer as a mask; and separating the charge storage layers of the memory cells from one another by patterning the charge storage material using the hard mask layer as a mask in an area which is not covered with the gate mask layer, while the control gate material is patterned.