Patent ID: 9442866
Filing Date: 2016-09-13
CPC Classification: G06F

Claim Text:
1. A memory apparatus, comprising: a memory array comprising a plurality of memory array channels; a memory controller configured to receive a memory request and comprising: a memory port for coupling to said memory array, said memory port comprising a plurality of physical memory channels configured to couple to said memory array and to access said memory array with relatively low latency or relatively high latency and with relatively high throughput or relatively low throughput; and circuitry to adjust between low latency and low throughput or high latency and high throughput in transferring information through the memory port to said memory array channels of said memory array, wherein said circuitry is capable of determining a number of said plurality of memory array channels through which to distribute said information to service said memory request with low latency and low throughput or high latency and high throughput, said determining being based, at least in part, on a type of said memory request; wherein said circuitry is capable of increasing said number of memory array channels through which to distribute the memory request to reduce latency or decreasing said number of memory array channels through which to distribute the memory request to increase throughput; and wherein said circuitry comprises circuitry for distributing requests of a length less than a threshold value to a greater number of said memory array channels.