Patent ID: 9461145
Filing Date: 2016-10-04
CPC Classification: G03F,H01L

Claim Text:
1. A method comprising: forming a shallow trench isolation (STI) region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width, wherein the dummy and gate electrodes are formed by: depositing polysilicon over the STI region and the silicon substrate; performing optical proximity correction (OPC) to a gate electrode cut mask, expanding a width of the dummy electrode from a width of the gate electrode to a width greater than or equal to the STI top width; overlaying the OPC corrected gate electrode cut mask on the polysilicon; and etching the polysilicon through the OPC corrected gate electrode cut mask.