Patent ID: 9349832
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of forming a transistor, the method comprising: forming a dummy gate on a substrate with spacers on both sides of the dummy gate; forming a source and a drain in the substrate, the source and the drain positioned under the spacers; forming an interlayer dielectric on top of the substrate, the spacers, and the dummy gate; planarizing the interlayer dielectric along with part of the spacers and the dummy gate; removing the dummy gate, thereby leaving an opening; depositing a sacrificial layer on top of the substrate in a bottom of the opening, the sacrificial layer comprising at least one of silicon germanium and germanium; removing the sacrificial layer from the substrate in the bottom of the opening, thereby growing an interfacial oxide layer on the substrate in the opening; and depositing a high-κ dielectric layer on top of the interfacial oxide layer.