Patent ID: 9513832
Filing Date: 2016-12-06
CPC Classification: G06F

Claim Text:
1. A system comprising: a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions comprising: receiving, at an accelerator device, a table of contents (TOC) generated by a compiler, the TOC including an address of global data in a host memory space; copying the global data from the address in the host memory space to an address in the device memory space, the address in the host memory space obtained from the received TOC; updating the received TOC to indicate that the global data is stored at the address in the device memory space; executing a kernel that accesses the global data from the address in the device memory space, the address in the device memory space obtained from the updated TOC; and based on the executing of the kernel completing, copying the global data from the address in the device memory space to the address in the host memory space.