Patent ID: 9466664
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a biaxially-strained semiconductor layer disposed on a substrate having an insulator formed therein; forming an array of mandrels adjacent to the biaxially-strained semiconductor layer; coating the mandrels with a conformal spacer layer; removing first portions of the conformal spacer layer to expose upper surfaces of the mandrels while retaining second portions of the conformal spacer layer adjacent to sidewalls of the mandrels; covering the mandrels and second portions with a first hard mask; patterning the first hard mask to expose upper surfaces of the second portions of the conformal spacer layer; patterning the conformal spacer layer to form openings between the mandrels and remaining first hard mask; and etching through the openings to expose strips of the biaxially-strained semiconductor layer.