Patent ID: 9472470
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a fin on a semiconductor substrate; forming a shallow trench isolation layer directly on top of the substrate adjacent to the fin; forming a dummy gate directly on top of the shallow trench isolation layer, the dummy gate oriented perpendicular to and directly covering a first portion of the fin; forming dummy gate spacers on opposite sidewalls of the dummy gate, and forming fin spacers on opposite sidewalls of a second portion of the fin; forming a dielectric layer directly on top of the shallow trench isolation layer and in contact with the fin spacers, a top surface of the dielectric layer is at or below a top surface of the fin; recessing the second portion of the fin between the fin spacers down to or below a top surface of the shallow trench isolation layer to form a first opening; removing the fin spacers selective to the dielectric layer to expand the first opening and to form a second opening between adjacent portions of the dielectric layer; and forming an unmerged source drain region in the second opening by epitaxially growing a semiconductor material from an exposed surface of a remaining portion of the fin at or near a bottom of the second opening, wherein lateral growth of the semiconductor material is constrained by the dielectric layer.