Patent ID: 9299658
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming an active region in a substrate; forming a gate stack and a grounded dummy feature over the active region; forming a first electrical contact on the gate stack and a second electrical contact electrically connected to the grounded dummy feature; depositing and patterning a plurality of metal layers separated by intermetal dielectric layers, each of the patterned metal layers having a first metal pattern and a second metal pattern electrically connected to the first contact and the second contact, respectively; depositing a passivation layer over a topmost layer of the patterned metal layers; forming a metal pad layer having a first metal pad electrically connected to the is first electrical contact, and a second metal pad electrically connected to the second metal pad by a plasma etching process; forming a metal fuse between two metal features, wherein the first of two metal features is directly connected to the first electrical contact and the second of two metal features is directly connected to the second electrical contact; and the two metal features are the first metal pad and the second metal pad, or the first metal pattern and the second metal pattern in one of the plurality of patterned metal layers; and breaking the metal fuse.