Patent ID: 9436212
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. A data bus part with a data bus Interface comprising: a downstream data bus input for receiving data from a higher-order data bus part; a clock generator for generating an internal clock signal for the data bus part; an upstream data bus input for receiving data from a lower-order data bus part; a synchronization unit for synchronizing the clock generator with the clock signal of the higher-order data bus part, wherein the synchronization unit is configured to detect transitions in the downstream data stream received at the downstream data input to regulate the frequency of the internal clock signal depending on the detected transitions, and to set a defined first phase position of the internal clock signal in relation to the detected transitions, wherein the data bus interface is bidirectional and further comprises a phase position correction unit for detecting transitions in the upstream data stream provided for the reception via the upstream data bus input and for delaying this upstream data stream depending on the detected transitions, wherein the phase position correction unit is configured in such a way that a defined second phase position of the internal clock signal, which is synchronized to the transitions of the received downstream data stream, in relation to the transitions of the delayed upstream data stream is set.