Patent ID: 9454998
Filing Date: 2016-09-27
CPC Classification: G11C

Claim Text:
1. A semiconductor device, comprising: a first bank; a second bank spaced apart from the first bank in a first direction; a third bank spaced apart from the first bank in a second direction perpendicular to the first direction; a fourth bank spaced apart from the second bank in the second direction and spaced apart from the third bank in the first direction; column control regions extending in the second direction between the first bank and the second bank and between the third bank and the fourth bank, and suitable for controlling column operations of the first to fourth banks; at least one power supply/ground voltage line extending in the second direction on a side of the first to fourth banks adjacent to the column control regions; and at least one power supply/ground voltage pads formed adjacent to and coupled with the at least one power supply/ground voltage line between the first bank and the third bank and between the second bank and the fourth bank, and suitable for receiving an external power supply voltage and a ground voltage, wherein each of the first to fourth banks comprises a core region including a normal mat and a dummy mat disposed on an edge of the normal mat that extends in the second direction and is adjacent to the column control region in the first direction, and wherein the at least one power supply/ground voltage line disposed on the dummy mat and a power line disposed on the normal mat are formed in a same layer.