Patent ID: 9484267
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, the method comprising: forming a first layer comprising a first semiconductor material on a substrate, forming a second layer comprising a second semiconductor material on the first layer, forming a third layer comprising the first semiconductor material on the second layer, removing portions of the first layer, the second layer, and the third layer to form a stack of nanowires, forming a first sacrificial gate stack and a second sacrificial gate stack over the stack of nanowires, patterning a first mask over the first sacrificial gate stack and a first portion of the stack of nanowires, removing exposed portions of the second layer, depositing an insulator material over an exposed second portion of the stack of nanowires, removing the first mask and the first sacrificial gate stack to expose a first channel region of a portion of the stack of nanowires, and performing an annealing process.