Patent ID: 9412716
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a unit substrate formed with first and second connection pads over a first surface thereof; a first ground connection pad formed over the first surface of the unit substrate and electrically coupled with the first connection pad; a semiconductor chip attached onto the first surface of the unit substrate, the semiconductor chip having a first bonding pad electrically coupled with the first connection pad and a second bonding pad electrically coupled with the second connection pad; a mold part for covering the first surface of the unit substrate including the semiconductor chip; a first conductive wire having a first end electrically coupled with the first ground connection pad and an electrically opened second end; a second conductive wire formed in an inside of the mold part and electrically coupling the first connection pad and the first bonding pad; and a third conductive wire formed in the inside of the mold part and electrically coupling the second connection pad and the second bonding pad, wherein at least two first ground connection pads are formed over the first surface of the unit substrate, the two or more first ground connection pads are electrically coupled to one first connection pad.