Patent ID: 9317253
Filing Date: 2016-04-19
CPC Classification: G06F,H03M

Claim Text:
1. A shift register, comprising: a plurality of M processing stages coupled in series, each processing stage configured to implement N taps of the shift register, wherein N>1, each coefficient of a feedback polynomial implemented by the shift register corresponding to respective one of the taps of the shift register; N single tap circuits coupled in series, a first of the N single tap circuits in the series coupled to an output of a last of the series of processing stages, and the N single tap circuits configured to implement the last N taps of the shift register; and a feedback control circuit configured to provide for one or more of the plurality of M processing stages, a respective 1-bit feedback signal as a function of polynomial coefficients implemented by the processing stage and data values input to one or more of the N single tap circuits.