Patent ID: 9286181
Filing Date: 2016-03-15
CPC Classification: G06F,G11C

Claim Text:
1. An integrated circuit structure configured for testing integrated circuit memory using a description file of Joint Test Action Group (JTAG) capture-shift test data registers, the structure comprising: a plurality of components and a plurality of electrical pathways having connections therebetween, wherein an architectural arrangement of the plurality of components, the plurality of electrical pathways, and the connections match a architectural arrangement of components of an integrated circuit controlled by a first data file; the architectural arrangement of the plurality of components, the plurality of electrical pathways, and the connections comprising: a reference memory structure that includes at least one first integrated circuit memory that has been tested; the reference memory structure further including a first input, a second input, a third input, a first output, and a second output; the first input of the reference memory structure being in electrical contact with a first electrical pathway that is in electrical contact with a first test data register; the second input of the reference memory structure being in electrical contact with a second electrical pathway that is in electrical contact with a second test data register; the third input of the reference memory structure being in electrical contact with a third electrical pathway; the first test data register being in electrical contact with the third electrical pathway and a first built in self test structure using a fourth electrical pathway; the first built in self test structure being in electrical contact with at least one first integrated circuit memory to be tested using a fifth electrical pathway; the second test data register being in electrical contact with the third electrical pathway and the first built in self test structure using a sixth electrical pathway; wherein the first output and the second output carry signals that are interpreted during testing of the at least one first memory; and wherein a description file of Joint Test Action Group (JTAG) capture-shift test data registers is configured to interpret a test result of the first memory.