Patent ID: 9449690
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A method of programming a memory system, the method comprising: selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed; applying a first bias voltage to a first wordline adjacent to a source side of the selected wordline; applying the first bias voltage to a second wordline adjacent to a drain side of the selected wordline; applying a second bias voltage to a third wordline adjacent to a drain side of the second wordline; applying a third bias voltage to a fourth wordline adjacent to a source side of the first wordline, wherein the third bias voltage is different than the second bias voltage; and selectively applying a pass voltage to remaining wordlines that do not have one of the first bias voltage, the second bias voltage, the third bias voltage, or the program voltage applied, the pass voltage being at a selected voltage level.