Patent ID: 9437528
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method for manufacturing dual-side exposed semiconductor packages with ultra-thin dies, the method comprising the steps of: preparing a plurality of dies, each of the plurality of dies having a source electrode and a gate electrode on a top surface of said each of the plurality of dies; providing a lead frame including a plurality of die paddles, said each of the plurality of dies being flipped and the top surface of said each of the plurality of flipped dies being attached to a respective die paddle of the plurality of die paddles; depositing a respective molding compound of a plurality of molding compounds on each of the plurality of flipped dies; grinding at top surfaces of the plurality of molding compounds so as to thin the plurality of molding compounds and to expose back surfaces of the plurality of flipped dies, and then grinding at top surfaces of the plurality of thinned molding compounds and the exposed back surfaces of the plurality of flipped dies so as to further thin the plurality of thinned molding compounds and the plurality of flipped dies; depositing a mask layer covering the lead frame and the plurality of further thinned molding compounds; depositing a respective back metal layer of a plurality of back metal layers on an exposed back surface of each of the plurality of further thinned flipped dies; removing the mask layer; attaching a respective metal clip of a plurality of metal clips to each of the plurality of back metal layers; depositing a molding compound layer covering the lead frame and surrounding the plurality of further thinned flipped dies so as to form a processed lead frame, top surfaces of the plurality of metal clips being exposed and a bottom surface of the lead frame being exposed; and singulating the dual-side exposed semiconductor packages from the processed lead frame.