Patent ID: 9450016
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a flat panel detector, the method comprising: forming a first transparent conductive film and patterning the first transparent conductive film to form a bottom electrode; forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer of a thin film transistor; forming a first passivation layer and patterning the first passivation layer to form a first passivation layer via hole at a location corresponding to a source of the thin film transistor; forming a second transparent conductive film and patterning the second transparent conductive film to form a second electrode at a location corresponding to the bottom electrode; forming a second passivation layer and patterning the second passivation layer to form a second passivation layer via hole at a location corresponding to the first passivation layer via hole over the source of the thin film transistor; forming a third transparent conductive film and patterning the third transparent conductive film to form an upper electrode at a location corresponding to the bottom electrode, wherein the upper electrode is connected with the source of the thin film transistor through the first passivation layer via hole and the second passivation layer via hole.