Patent ID: 9269420
Filing Date: 2016-02-23
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a cell array including a DRAM cell connected to one of a pair of bit lines; a bit line sense amplifier coupled to the pair of bit lines and discharging a low-level bit line of the pair of bit lines toward a ground level during an initial period of sensing operation, clamping the low-level bit line to a boosted sense ground voltage in response to a control signal, and pulling up a high-level bit line of the pair of bit lines toward a core supply voltage level; and a sense amplifier control logic generating the control signal having a pulse interval, wherein the low-level bit line is discharged toward the ground level for the pulse interval and after the pulse interval ends, the low-level bit line is clamped to the boosted sense ground voltage.