Patent ID: 9502360
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first substrate having a first side and a second side; a first die mounted on the first side of the first substrate; a molding compound formed on, and limited to, the first side of the first substrate; a stress compensation layer formed on, and limited to, the second side of the first substrate, wherein the stress compensation layer is configured to counter a stress applied to the first substrate by the molding compound, with a first stress exerted to the first substrate by the stress compensation layer being substantially equal to a second stress exerted to the first substrate by the molding compound, wherein the stress compensation layer has a through-opening extending to the first substrate, and wherein a thickness of the stress compensation layer is about: wherein CTE Molding is the coefficient of thermal expansion of the molding compound, E Molding is the Young's Modulus of the molding compound, THK Molding is a thickness of the molding compound CTE Compensation is the coefficient of thermal expansion of the stress compensation layer and E Compensation is the Young's Modulus of the stress compensation layer; and a second substrate electrically coupled to the first substrate on the first side.