Patent ID: 9320173
Filing Date: 2016-04-19
CPC Classification: H01L,H05K

Claim Text:
1. A semiconductor device comprising: a base plate having a first major plane and a second major plane opposite to each other, and having a plurality of fins held upright on the first major plane and a bulge portion formed on the first major plane to encircle the plurality of fins; an insulation layer formed on the second major plane of the base plate; a circuit pattern fixed to the insulation layer; a semiconductor element connected to the circuit pattern; and a sealing resin sealing the insulation layer, the circuit pattern, and the semiconductor element, wherein the bulge portion formed on the first major plane continuously encircles the plurality of fins, the base plate has a widthwise margin on an outer peripheral edge of the first major plane of the base plate, the bulge portion is formed on the widthwise margin and divides the widthwise margin into an outer widthwise margin arranged outside of the bulge portion and an inner widthwise margin arranged inside of the bulge portion, and the sealing resin covers an outer peripheral side face of the bulge portion and the outer widthwise margin.