Patent ID: 9425141
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. An integrated circuit, comprising: a first layer on a first level, the first layer comprising a set of first lines, the lines of the set of first lines each having a length measured in a first direction and a width measured in a second direction different from the first direction, wherein the length of each line of the set of first lines is greater than the width of each line of the set of first lines; a second layer on a second level different from the first level, the second layer comprising a set of second lines, the lines of the set of second lines each having a length measured in the second direction and a width measured in the first direction, wherein the length of each line of the set of second lines is greater than the width of each line of the set of second lines; a first coupling configured to electrically connect at least one line of the set of first lines with at least one line of the set of second lines, the first coupling having a length measured in the first direction and a width measured in the second direction, wherein the set of second lines has a pitch measured between the lines of the set of second lines in the first direction, and the length of the first coupling is greater than or equal to the pitch, and wherein at least one line of the set of first lines is a source power rail, and the first coupling is in direct contact with the source power rail; and a second coupling configured to electrically connect at least one other line of the set of first lines with the at least one line of the set of second lines, the second coupling having a length measured in the first direction and a width measured in the second direction, wherein the length of the second coupling is greater than the width of the second coupling, wherein at least one line of the set of first lines is a drain power rail, and the second coupling is in direct contact with the drain power rail.