Patent ID: 9412718
Filing Date: 2016-08-09
CPC Classification: G06F,H01L

Claim Text:
1. A method for operating a computer processor comprising a first processor chip and a second processor chip connected in a stacked configuration; wherein the first processor chip comprises a first processor, wherein the second processor chip comprises a second processor, wherein the first and second processors are vertically aligned and connected through vertical connections, the method comprising: configuring the vertically aligned first and second processors to operate as a single logical processor; generating, by a control system, different sets of configuration parameters to operate the single logical processor in different power operating modes; generating, by the control system, a first control signal to selectively input a first set of the configuration parameters to the single logical processor; utilizing, by the single logical processor, the first set of the configuration parameters to operate the single logical processor in a first power operating mode wherein the first processor is turned on and the second processor is turned off; generating, by the control system, a second control signal to selectively input a second set of the configuration parameters to the single logical processor; and utilizing, by the single logical processor, the second set of the configuration parameters to operate the single logical processor in a second power operating mode wherein both the first processor and the second processor are turned on; wherein in the second power operating mode, both the first processor and the second processor operate at less than full power so that a total power of the single logical processor in the second power operating mode is substantially the same as a total power of the single logical processor in the first power operating mode when only the first processor is turned on and operating at full power.