Patent ID: 9502448
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method for fabricating an array substrate, including steps: S1: sequentially forming a bottom gate, a first gate insulating layer, an active layer and a second gate insulating layer on a base substrate, wherein a gate line is formed at the same time as forming the bottom gate; S2: forming a top gate on the second gate insulating layer; S3: sequentially forming a gate isolation layer, a source electrode, a drain electrode and a pixel electrode on the top gate; wherein the method further includes step S2′ before step S2, and step S2′ includes: forming a nickel layer at an area on the active layer where the source electrode is to be formed and/or an area on the active layer where the drain electrode is to be formed, and then performing a heat treatment on the active layer at a temperature in the range of 500° C.-570° C. for 2 hours in an atmosphere of H2.