Patent ID: 9349734
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device structure, comprising: providing a first semiconductor device with a first gate structure over a first active region formed in a semiconductor substrate, said first gate structure comprising a first gate electrode material and a first gate dielectric material; providing a second semiconductor device with a second gate structure over a second active region formed in said semiconductor substrate, said second gate structure comprising a second gate electrode material and a second gate dielectric material; forming a pattern masking layer over said semiconductor structure that exposes said first semiconductor device and covers said second semiconductor device; with the pattern masking layer in position, performing a selective anisotropic etch process to said first semiconductor device to recess said first gate electrode material, thereby leaving a recessed first gate electrode material, and to form a cavity structure in said first active region, said cavity structure being in alignment with said first gate structure; with the pattern masking layer in position, performing a deposition process to deposit a strain-inducing material in said cavity structure; removing the pattern masking layer; forming a first silicide portion on and in contact with said first gate dielectric material by siliciding all of said recessed first gate electrode material; and forming a second silicide portion on and in contact with a portion of said second gate electrode material.