Patent ID: 9484439
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: providing a III-V material stack on a surface of a bulk semiconductor substrate, said III-V material stack comprising from bottom to top, a first III-V compound semiconductor buffer layer, a second III-V compound semiconductor buffer layer, and a III-V compound semiconductor channel layer; patterning said III-V material stack to provide at least one pre-fin structure located between and directly contacting a pair of pre-pad structures; suspending a remaining portion of said III-V compound semiconductor channel layer within said at least one pre-fin structure using each pre-pad structure as an anchoring element; forming a first dielectric material surrounding said at least one pre-fin structure and said pair of pre-pad structures, wherein a portion of said first dielectric material fills a gap located between said remaining portion of said III-V compound semiconductor channel layer that is suspended within said pre-fin structure and an underlying remaining portion of said first III-V compound semiconductor buffer layer; performing a fin cutting process to provide openings separating remaining portions of said at least one pre-fin structure and remaining portions of said pair of pre-pad structures; and forming a second dielectric material within each opening, said second dielectric material having a topmost surface that is located beneath a bottommost surface of said remaining portion of said III-V compound semiconductor channel layer of said remaining portions of said at least one pre-fin structure.