Patent ID: 9476933
Filing Date: 2016-10-25
CPC Classification: G01R,H01L

Claim Text:
1. A test method, comprising: coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test, and coupling a source terminal of the power transistor device under test to a ground potential; coupling a current monitor to the drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal of the power transistor device under test, and for each of the test conditions, applying a voltage pulse to the gate terminal of the power transistor device from the gate pulse generator, the gate pulse rising only after the drain pulse falls below a predetermined threshold for each of the first set of test conditions; for each of the first set of test conditions, measuring the drain current of the power transistor device under test with the drain current monitor; for a second set of test conditions, activating the drain pulse generator and applying a voltage pulse to the drain terminal of the power transistor device under test, and applying a voltage pulse to the gate terminal of the power transistor device under test as the drain pulse falls for each of the second set of test conditions, the drain pulse generator and the gate pulse generator both being active for a portion of the second set of test conditions so that there is some overlap between the voltage pulse applied to the drain terminal and the voltage pulse applied to the gate terminal; and for each of the second set of test conditions, measuring the drain current into the power transistor device under test with the drain current monitor.