Patent ID: 9281393
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate; an epitaxy layer, formed on the substrate, the epitaxy layer having a first conductivity type; a plurality of deep wells, formed in the epitaxy layer, wherein the deep wells have a second conductivity type; a plurality of trench gate MOSFET units, each of the trench gate MOSFET units formed in the top portion of the epitaxy layer between two adjacent deep wells, wherein the top of the epitaxy layer serves as a body region of the trench gate MOSFET unit, and wherein the substrate serves as a drain region of the trench gate MOSFET unit; and a source metal layer, wherein the source metal layer contacts top surfaces of the body region and the plurality of deep wells; wherein each of the plurality of trench gate MOSFET units comprises a source region and a shallow trench gate that are both formed in the body region, and wherein the depth of the shallow trench gate is smaller than half of the distance between the two adjacent deep wells.