Patent ID: 9330586
Filing Date: 2016-05-03
CPC Classification: G09G

Claim Text:
1. A display apparatus, comprising: a plurality of pixels arranged in association with a plurality of gate lines and a plurality of data lines crossing the gate lines; a data driver configured to drive the data lines; a gate driving unit configured to drive the gate lines in synchronization with a gate control signal; and a timing controller configured to control the data driver and the gate driving unit in response to an image signal and an input control signal, wherein the timing controller is configured to output the gate control signal comprising a plurality of pulses respectively corresponding to the gate lines, and an enable time of each pulse of the plurality of pulses is set according to a position of a corresponding gate line of the gate lines, wherein: the gate control signal is a gate pulse signal comprising the pulses respectively corresponding to the gate lines, and a charge sharing time of the gate pulse signal is set according to the position of the corresponding gate line of the gate lines; the gate lines are grouped into K groups (where K is a natural number greater than 2), the timing controller is configured to output the gate pulse signal having charge sharing times respectively corresponding to the K groups, and the charge sharing time of the gate control signal is set according to a driving order of the group which includes the corresponding gate line; and the charge sharing times of the gate pulse signals for each group increase as each of the groups of the gate lines is consecutively driven in the driving order from 1 to K.