Patent ID: 9419000
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, comprising: forming first and second bit line structures that extend in a first direction on a substrate, the first and second bit line structures spaced apart from each other by a first groove in a second direction that is perpendicular to the first direction; forming multilayer spacers on first and second opposing sidewalls of the first bit line structure and on first and second opposing sidewalls of the second bit line structure; forming a sacrificial layer in the first groove; patterning the sacrificial layer to form a plurality of second grooves that are spaced apart from each other in the first direction and the second direction; etching portions of an outermost spacer of at least some of the multilayer spacers that are exposed in the second grooves; forming first supplementary spacers in at least some of the second grooves; and removing the sacrificial layer to form a plurality of third grooves that are spaced apart from each other in the first direction and the second direction.