Patent ID: 9396998
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: an upper layer chip having a first face and a second face opposite to the first face; a first resin layer provided on the first face of the upper layer chip; a first interconnect layer provided in the first resin layer, the first interconnect layer being electrically connected to the upper layer chip; a second resin layer provided on a surface side of the first resin layer, the second resin layer extending into a region outside the upper layer chip, and the region being outside of a side face of the upper layer chip; a second interconnect layer provided in the second resin layer, the second interconnect layer being connected to the first interconnect layer and extending into the region outside the upper layer chip; a lower layer chip mounted on the surface side of the first resin layer and connected to the first interconnect layer; and a first sealing resin covering the upper layer chip, wherein a side surface of the first resin layer is substantially aligned with and is substantially coplanar with a side surface of the upper layer chip in a direction crossing the first face and the second face.