Patent ID: 9437556
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate; a wiring structure formed over the semiconductor substrate and including a plurality of wiring layers; and a sealring formed along the periphery of the semiconductor substrate in the wiring structure, wherein the sealring has a structure in which sealring wirings respectively formed in the wiring layers are laminated, the sealring wirings including a first sealring wiring formed in an uppermost layer of the plurality of wiring layers and a second sealring wiring formed in a wiring layer located one layer lower than the uppermost wiring layer, wherein a pad is formed in the uppermost wiring layer, wherein the position of a side surface on the inner peripheral side of the first sealring wiring is located more outside than the position of a side surface on the inner peripheral side of the second sealring wiring, wherein a width of the first sealring wiring is smaller than a width of the second sealring wiring, wherein a thickness of the first sealring wiring is larger than a thickness of the second sealring wiring, and the thickness of the first sealring wiring is the same as a thickness of the pad, and wherein a distance between the first sealring wiring and the pad in the uppermost wiring layer is larger than a distance between the second sealring wiring and another wiring in the wiring layer located one layer lower than the uppermost wiring layer.