Patent ID: 9417847
Filing Date: 2016-08-16
CPC Classification: G06F

Claim Text:
1. A computer-implemented method for generating a hardware multiplier circuit, the computer comprising a processor and a memory device, the method comprising: selecting, by the processor, a Karatsuba multiplier scheme from among a plurality of multiplier schemes in response to an iteration parameter being greater than zero, wherein said plurality of multiplier schemes includes the Karatsuba multiplier scheme and a non-Karatsuba multiplier scheme; generating, by the processor, a first circuit configured to (i) multiply a plurality of coefficients of two polynomials to generate a plurality of partial products based on a plurality of parameters of said Karatsuba multiplier scheme, and (ii) combine said partial products to generate an intermediate product, wherein each polynomial comprises n components, and wherein a number of said partial products generated is less than 2n; generating, by the processor, a second circuit configured to perform a polynomial modulo operation on said intermediate product to generate a final product of said polynomials based on said parameters and a modulo polynomial, wherein said final product of said polynomials resides in a finite field, and wherein said second circuit is connected to said first circuit; and reducing, by the processor, a depth of a plurality of logic gates through said first circuit and said second circuit to generate a reduced depth combinational logic circuit, wherein said hardware multiplier circuit comprises said reduced depth combinational logic circuit.