Patent ID: 9292297
Filing Date: 2016-03-22
CPC Classification: G06F

Claim Text:
1. A processor, comprising: an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand, the first operand to specify a first storage location to store an accumulated value, the second operand to specify a second storage location to store a first value and a second value, the third operand to specify a third storage location to store a third value; and an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of the third value to the accumulated value based on the fourth operand, wherein the fourth operand to store a value indicating the at least a portion of the third value to be added to the accumulated value.