Patent ID: 9443605
Filing Date: 2016-09-13
CPC Classification: G11C

Claim Text:
1. A non-volatile storage device, comprising: a plurality of word lines; a plurality of bit lines; a plurality of NAND strings in a three dimensional memory array, each of the NAND strings comprising a drain side select transistor coupled to a bit line of the plurality of bit lines, each of the NAND strings being associated with a group of the plurality of word lines; and managing circuitry in communication with the plurality of word lines, the plurality of bit lines, and the drain side select transistors of the plurality of NAND strings, wherein the managing circuitry is configured to generate an unselect voltage that has a magnitude that depends on temperature and location of a selected word line along an unselected NAND string, wherein the managing circuitry is configured to apply the unselect voltage to a control gate of the drain side select transistor of the unselected NAND string while a programming voltage is applied to the selected word line, while a boosting voltage is applied to unselected word lines associated with the unselected NAND string, and while a voltage is applied to a bit line associated with the unselected NAND string.