Patent ID: 9411924
Filing Date: 2016-08-09
CPC Classification: G03F,G06F

Claim Text:
1. A method for pattern density optimization, comprising: forming an integrated chip (IC) design comprising a graphical representation of a layout used to fabricate an integrated chip, using a computation element; performing an initial data preparation process on the IC design, using a data preparation element, to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design; identifying one or more low-pattern-density areas of the modified IC design having a pattern density that results in a processing failure after performing the initial data preparation process using a local density checking element, wherein respective low-pattern-density areas comprise a subset of the IC modified design; adjusting the pattern density of the modified IC design within the one or more low-pattern-density areas by adding one or more dummy shapes within the one or more low-pattern-density areas using a dummy shape insertion element, wherein the one or more dummy shapes are separated from the modified shapes by a non-zero space; and performing a second data preparation process on the modified IC design that modifies shapes of the one or more dummy shapes within the one or more low-pattern-density areas using the data preparation element.