Patent ID: 9318574
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a sacrificial gate stack over a surface of a substrate; providing a plurality of hard mask structures on a topmost surface of said sacrificial gate stack, wherein an anchoring element is disposed over segments of each hard mask structure; patterning said sacrificial gate stack into a plurality of sacrificial gate structures utilizing said plurality of hard mask structures and said anchoring element as an etch mask; removing each hard mask structure to expose a sacrificial gate cap portion of each sacrificial gate structure, wherein end segments of each sacrificial gate cap portion are connected to a sacrificial gate cap anchoring portion; forming a dielectric spacer comprising a first dielectric material on sidewalls of each of said sacrificial gate structures and sidewalls of said sacrificial gate cap anchoring portion; forming a planarization dielectric layer laterally surrounding each of said sacrificial gate structures, wherein said planarization dielectric layer has a topmost surface that is coplanar with a topmost surface of each of said sacrificial gate structures; and removing each sacrificial gate cap anchoring portion to form a spacer cavity.