Patent ID: 9465595
Filing Date: 2016-10-11
CPC Classification: G06F

Claim Text:
1. A computing apparatus that computes a performance value of a program for a case where the program is executed by a processor, the program including a specific code which is executed multiple times by the processor and which includes an access instruction for instructing the processor to access a memory area, the computer apparatus comprising: a first determining unit that determines, in a case where the specific code has become a computing target for a performance value, whether or not a cache memory accessible by the processor is in an available state for use at a time of execution of the access instruction in a simulation of an operation in which the processor executes the program, in accordance with a direction of the access instruction; a generating unit that generates, in a case where the first determining unit has determined that the cache memory is not in the available state for use, a computational code for computing the performance value of the specific code for a case where the processor executes the specific code, based on performance values of individual instructions within the specific code for a case where the cache memory is not used, without depending on an attribute of the memory area; and an execution unit that executes the generated computational code in a case where the specific code has become a new computing target for a performance value.