Patent ID: 9417685
Filing Date: 2016-08-16
CPC Classification: G06F,G11C,Y02B,Y02D

Claim Text:
1. An apparatus, comprising: an array of memory cells; a controller, wherein the controller is configured to perform an access operation on the array of memory cells; a clock generator for generating a clock signal; and a wrap-around counter for counting pulses of the clock signal; wherein the controller is further configured to determine whether a value of the wrap-around counter matches a counter value assigned to the apparatus and to pause the access operation at a designated point until the value of the wrap-around counter matches the assigned counter value of the apparatus; and wherein the controller is further configured to cause the clock generator to temporarily stop generating the clock signal in response to the value of the wrap-around counter matching the assigned counter value of the apparatus while the access operation is paused.