Patent ID: 9460794
Filing Date: 2016-10-04
CPC Classification: G11C

Claim Text:
1. A nonvolatile semiconductor memory device, comprising: a first memory string including a first memory cell; a second memory string including a second memory cell; a first bit line electrically connected to one end of the first memory string; a second bit line electrically connected to one end of the second memory string; a word line electrically connected to gates of the first memory cell and the second memory cell; and a control circuit configured to perform a writing operation, the writing operation including a first operation, a second operation, and a third operation, the control circuit being configured to apply a first voltage to the first bit line in the first operation, the control circuit being configured to apply a second voltage to the second bit line in the first operation, a voltage of the first bit line is changed to a third voltage in the second operation after the first operation, the control circuit being configured to apply a fourth voltage to the second bit line in the second operation, the third voltage being higher than the fourth voltage, the third voltage being higher than the first voltage, the fourth voltage being higher than the second voltage, the control circuit being configured to apply a program voltage to the word line in the third operation after the second operation.