Patent ID: 9373414
Filing Date: 2016-06-21
CPC Classification: G09G,G11C

Claim Text:
1. A shift register unit, comprising: a third thin film transistor for controlling a level at a pull-up node under a control of a first control signal; a first thin film transistor for outputting a first clock signal to a signal output terminal under a control of a level at the pull-up node; a control unit for controlling a level at a pull-down node; a second level output unit for outputting a second level signal to the signal output terminal under a control of the level at the pull-down node; a tenth thin film transistor having a drain and gate both connected to the pull-down node, a source connected to a first low voltage signal input terminal, for inputting a first level signal to the pull-down node under a control of the level at the pull-down node; and an eleventh thin film transistor for inputting the first level signal to the pull-down node under a control of a level at the signal output terminal; wherein the second level output unit comprise an eighth thin film transistor having a drain connected to the signal output terminal, a source connected to a second low voltage signal input terminal to receive a second level signal, and a gate connected to the pull-down mode, wherein the first level signal and the second level signal are low level signals, the first level signal is less than the second level signal, and an absolute value of a difference between the first level signal and the second level signal is larger than an absolute value of a depletion threshold voltage of the eighth thin film transistor.