Patent ID: 9431257
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. An integrated circuit for an embedded flash memory device, said integrated circuit comprising: a semiconductor substrate including a memory region and a logic region adjacent to the memory region; a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9; a flash memory cell device arranged over the memory region, wherein the flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates, and wherein a top surface of the first memory cell gate is recessed below a top surface of the metal gate; and a silicide contact pad arranged on the first memory cell gate, wherein the silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate, and the metal gate.