Patent ID: 9503068
Filing Date: 2016-11-22
CPC Classification: G01R,H03K

Claim Text:
1. An integrated circuit comprising: a delay line circuit supplied by a first power supply voltage during use, wherein an input to the delay line circuit receives a first pulse during use and wherein a plurality of taps on the delay line circuit provide delayed pulses at different times relative to the input pulse; a plurality of flops, each flop of the plurality of flops coupled to a respective one of the plurality of taps and having an input on which a second pulse is received during use, wherein the plurality of flops are supplied by a second power supply voltage that does not depend on the first power supply voltage; and a circuit coupled to the outputs of the plurality of flops and configured to compare a pattern of the outputs to at least one predetermined pattern that indicates a voltage droop on the second power supply voltage, and wherein the circuit is configured to output a signal indicating detection of the predetermined pattern.