Patent ID: 9305481
Filing Date: 2016-04-05
CPC Classification: G02F,G09G,H01L

Claim Text:
1. A display device comprising: a driver circuit including a logic circuit, the logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor; a signal line electrically connected to each of the first transistor and the second transistor; a pixel portion including a pixel whose display state is configured to be controlled by input of a signal including image data from the driver circuit through the signal line; a reference voltage line; a gate signal line; and a third transistor which is a depletion type transistor and includes a gate, a source, and a drain, and is configured to discharge electric charges from the signal line to the reference voltage line, wherein one of the source and the drain of the third transistor is electrically connected to the reference voltage line, wherein the other of the source and the drain of the third transistor is electrically connected to the signal line, wherein the gate of the third transistor is electrically connected to the gate signal line, and wherein the first to third transistors each include an oxide semiconductor layer having a channel formation region.