Patent ID: 9287197
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A method of forming a device comprising: providing a substrate with top and bottom surfaces; forming a through silicon via (TSV) in the substrate through the top surface; lining the TSV and the top surface of the substrate with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer, wherein the insulation stack lines without filling the TSV, wherein the polish stop layer lines the first insulation layer and the second insulation layer lines the polish stop layer; forming a conductive layer on the substrate, the conductive layer filling the TSV over the insulation stack comprising the first insulation layer, the polish stop layer and the second insulation layer; and planarizing the substrate to form a top portion of a TSV contact in the TSV, the planarizing removes excess conductive material of the conductive layer and the second insulation layer over the top surface of the substrate, the planarizing stops on the polish stop layer of the insulation stack over the top surface of the substrate, the planarizing leaves the polish stop layer remaining over the top surface of the substrate and a top surface of the conductive material in the TSV is planar with a top surface of the polish stop layer over the top surface of the substrate, forming the top portion of the TSV contact.