Patent ID: 9379147
Filing Date: 2016-06-28
CPC Classification: G02F,H01L

Claim Text:
1. A manufacturing method of a thin-film transistor array substrate, wherein, the method comprises steps of: providing a substrate; successively depositing a first transparent conductive layer and a first metallic layer on the substrate by sputtering, and using a first multi-tone adjustment mask to pattern the first transparent conductive layer and the first metallic layer to form a gate electrode and a common electrode, wherein the gate electrode includes the first transparent conductive layer and the second metallic layer and the common electrode is formed through the first transparent conductive layer; depositing a gate-insulating layer and a semiconductor layer and using a first mask to pattern the semiconductor layer to retain a part of the semiconductor layer that is on a top of the gate electrode; depositing a second transparent conductive layer and a second metallic layer on the substrate, using a second multi-tone adjustment mask to pattern the second transparent conductive layer and the second metallic layer so as to form a source electrode and a drain electrode, which both include the second transparent conductive layer and the second metallic layer, on the semiconductor layer, and to form a pixel electrode, which is formed through the second transparent conductive layer, on the gate-insulating layer that the common electrode corresponds to, wherein a mixture of nitric acid, phosphoric acid and acetic acid is used to perform wet etching on the second metallic layer, and oxalic acid is used to perform wet etching on the second transparent conductive layer, wherein the second transparent conductive layer is indium tin oxide; and depositing a planarization layer on the pixel electrode and the source electrode, the drain electrode and the semiconductor layer which constitute a thin-film transistor, wherein the planarization layer is formed by a transparent insulation material.