Patent ID: 9418969
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A packaged semiconductor device, comprising: an integrated circuit die disposed in a molding compound; a plurality of through-vias disposed in the molding compound; a first redistribution layer (RDL) disposed over a first side of the plurality of through-vias, the integrated circuit die, and the molding compound; a second RDL disposed over a second side of the plurality of through-vias, the integrated circuit die, and the molding compound; a plurality of contact pads disposed over the second RDL, wherein an insulating material of the second RDL includes a recess adjacent a perimeter of at least one of the plurality of contact pads; and wherein the insulating material of the second RDL includes a plurality of the recesses, each of the plurality of recesses extending from a top surface of the insulating material of the second RDL, and wherein each of the plurality of recesses is disposed adjacent a perimeter of one of the plurality of contact pads; wherein a portion of the plurality of recesses comprises at least one recess disposed between two adjacent contact pads of the plurality of contact pads.