Patent ID: 9466730
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches in the epitaxial layer of the active region; a plurality of second trenches in the epitaxial layer of the termination region, wherein distances between adjacent trenches of the first and the second trenches increase from the active region to the termination region, wherein distances between the adjacent first trenches in the active region increase from the active region to the termination region, and distances between the adjacent second trenches in the termination region increase from the active region to the termination region; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer over opposite sides of a first column which is farthest away from the termination region; a source region formed between the floating gates; an inter-layer dielectric layer covering the gate dielectric layer and the floating gates; and a contact plug formed on the source region through the inter-layer dielectric layer.