Patent ID: 9252049
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a dielectric material layer on a semiconductor substrate; patterning the dielectric material layer to form a plurality of vias therein; forming a first metal layer on the dielectric material layer, wherein the first metal layer fills the plurality of vias; planarizing the first metal layer so that the top thereof is substantially co-planar with the top of the dielectric material layer to form a plurality of first metal features; and annealing the plurality of first metal features to form a discontinuous stop layer on top of each of the plurality of first metal features, the stop layer covering and being substantially aligned with each of the plurality of first metal features and not extending substantially over the dielectric material between the plurality of first metal features, wherein the plurality of first metal features comprises a first conductive material and a second conductive material, the second conductive material being smaller in concentration than the first conductive material, and wherein the annealing the plurality of first metal features comprises segregating the second conductive material to the top of each of the plurality of the first metal features to form the discontinuous stop layer.