Patent ID: 9431964
Filing Date: 2016-08-30
CPC Classification: H03F

Claim Text:
1. An operational amplifier comprising a first input pair, a second input pair, a switch and a first current mirror, wherein the first input pair comprises a different type of MOS transistor from the second input pair; the switch is configured to determine which one of the first input pair or the second input pair is functioning, wherein the switch is further connected to the first input pair and the first current mirror, and the input pair functioning is configured to output voltage; and the first current mirror is further connected to the second input pair, and is configured to copy a current passing through the switch to the second input pair, such that the operational amplifier has a substantially constant transconductance no matter which of the first input pair and the second input pair is functioning, wherein the first input pair comprises a first MOS transistor and a second MOS transistor, the second input pair comprises a third MOS transistor and a fourth MOS transistor, the switch comprises a fifth MOS, and the operational amplifier further comprises a second current mirror, a third current mirror and a load unit; wherein any two of a first node of the first MOS transistor, a first node of the second MOS transistor, a first current source and a first node of the fifth MOS transistor are connected; a second node of the first MOS transistor is connected to a second node of the fourth MOS transistor and is also configured to receive a positive input, a third node of the first transistor is connected to both a second port of the third current mirror and a first port of the load unit; a second node of the second MOS transistor is connected to a second node of the third MOS transistor and is also configured to receive a negative input, a third node of the second transistor is connected to both a second port of the second current mirror and a second node of the load unit and is also configured to output voltage; first nodes of both the third and fourth MOS transistors are connected to a first port of the first current mirror, a third node of the third MOS transistor is connected to a first port of the third current mirror, a third node of the fourth MOS transistor is connected to a first port of the second current mirror; a second node of the fifth MOS transistor is connected to a voltage source, a third node of the fifth MOS transistor is connected to a second port of the first current mirror, wherein the third current mirror comprises a sixth MOS transistor and a seventh MOS transistor, first nodes of both the sixth and the seventh MOS transistors are connected to a first power source, both second and third nodes of the sixth MOS transistor are connected to both a second node of the seventh MOS transistor and the third node of the third MOS transistor, and the first port of the third current mirror comprises the third node of the sixth MOS transistor, and the second port of the third current mirror comprises a third node of the seventh MOS transistor; the second current mirror comprises an eighth MOS transistor and a ninth MOS transistor, first nodes of both the eighth and the ninth MOS transistors are connected to the first power source, both second and third nodes of the ninth MOS transistor are connected to a second node of the eighth MOS transistor and the third node of the fourth MOS transistor, and the first port of the second current mirror comprises the third node of the ninth MOS transistor, and the second port of the second current mirror comprises a third node of the eighth MOS transistor; and the first current mirror comprises a tenth MOS transistor and an eleventh MOS transistor, first nodes of both the tenth and the eleventh MOS transistors are connected to the second power source, both second and third nodes of the tenth MOS transistor are connected to both a second node of the eleventh MOS transistor and the third node of the fifth MOS transistor, and the first port of the first current mirror comprises a third node of the eleventh MOS transistor, and the second port of the first current mirror comprises the third node of the tenth MOS transistor.