Patent ID: 9529963
Filing Date: 2016-12-27
CPC Classification: G01R

Claim Text:
1. A method of testing a design under test (DUT) using a verification test bench, the method comprising: obtaining a computer-readable source code of the DUT and a computer-readable source code of the verification test bench; separating the computer-readable source code of the verification test bench into reactive components and analytic components, the reactive components for sending test traffic to the DUT and for receiving test traffic from the DUT, the analytic components for verifying the test traffic between the reactive components and the DUT; compiling, at a computer processor, the reactive components and the computer-readable source code of the DUT into a first computer-executable test bench; compiling, at the computer processor, the analytic components into a second computer-executable test bench; running the first computer-executable test bench on a simulator program of the computer processor to generate test traffic between the reactive components and the DUT; separately running the second computer-executable test bench on the simulator program of the computer processor to verify the test traffic; and outputting an indication of whether the second computer-executable test bench verified the test traffic as a successful simulation of the DUT or as a failed simulation of the DUT.