Patent ID: 9391200
Filing Date: 2016-07-12
CPC Classification: G06N,G10L,H01L

Claim Text:
1. A method for forming fins of a finFET, the method comprising: forming one or more spacer layers over a fin including a semiconductor fin having a first height; forming a planarized layer over the one or more spacer layers, the planarized layer being etch selective relating to the spacer layers; recessing the planarized layer to a level between a bottom of the semiconductor fin and a top of the semiconductor fin; etching the one or more spacer layers in a region adjacent the fin to expose at least a portion of the fin above a second height that is less than the first height, said etching of the one or more spacer layers being self-limited at the second height by the level of the recessed planarized layer; removing the recessed planarized layer; and etching the exposed portion of the fin to remove a portion of the semiconductor fin to a height determined, at least in part, by a top surface of the previously etched at least one of the one or more spacer layers at the second height.