Patent ID: 9531570
Filing Date: 2016-12-27
CPC Classification: H04L

Claim Text:
1. A system for predictive decision feedback equalization, the system comprising: a first sampler-multiplexer block and a second sampler-multiplexer block, each of the first sampler-multiplexer block and the second sampler-multiplexer block comprising: a clock generator, the clock generator being a phase-locked loop comprising a ring oscillator, the clock generator having: the first clock output of the clock generator being connected to the common clock input of the first and second samplers of the first sampler-multiplexer block, wherein the first sampler comprises: a first terminal of the first resistor being connected to a first power supply line, a second terminal of the first resistor being connected to a drain of the first transistor, and to the output of the first sampler, a first terminal of the second resistor being connected to the first power supply line, and a second terminal of the second resistor being connected to a drain of the second transistor, and to the output of the first sampler, wherein the multiplexer-latch comprises: wherein the multiplexer-latch does not include a capacitor connected from a gate of the first transistor of the first differential pair of the multiplexer-latch to a drain of the second transistor of the first differential pair of the multiplexer-latch.