Patent ID: 9293560
Filing Date: 2016-03-22
CPC Classification: B82Y,H01L,Y10S

Claim Text:
1. A method of fabricating a vertical nanowire transistor having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the method comprising: growing a plurality of crystalline semiconductor layers epitaxially from the substrate, the plurality including at least: a group IV or group III-V source semiconductor layer; a group IV or group III-V drain semiconductor layer; and a group IV or group III-V channel semiconductor layer disposed between source and drain semiconductor layers, wherein the epitaxial growing further comprises modifying growth conditions to vary the semiconductor composition across a thickness of the channel semiconductor layer; etching through at least the channel semiconductor layer to form a sidewall through the channel semiconductor layer; and forming a gate dielectric layer and a gate electrode on the channel semiconductor layer sidewall.