Patent ID: 9407425
Filing Date: 2016-08-02
CPC Classification: H04L

Claim Text:
1. A circuit for compensating phase imbalance, comprising: a first multiplier and a second multiplier respectively configured to output an in-phase branch signal and a quadrature branch signal related to a power signal; a phase compensator connected to the first multiplier, an adder connected to the phase compensator and the second multiplier, and a third multiplier connected to the adder, wherein the phase compensator is configured to generate a compensated in-phase branch signal using a phase compensation value, the adder is configured to generate an addition result by adding the compensated in-phase branch signal with the quadrature branch signal, and the third multiplier is configured to generate a compensated quadrature branch signal by multiplying the addition result with a factor, and output the compensated quadrature branch signal; an in-phase path digital-to-analog converter, an in-phase path low pass filter, an in-phase mixer, and an in-phase path local oscillator connected in sequence with the first multiplier and configured to output a mixed in-phase signal based on the in-phase branch signal, a quadrature path digital-to-analog converter, a quadrature low pass filter, a quadrature mixer, and a quadrature local oscillator connected in sequence with the third multiplier and configured to output a mixed quadrature branch signal based on the compensated quadrature branch signal, a summator connected to both the in-phase mixer and the quadrature mixer, a transmitter programmable gain amplifier connected to the summator, and a transmitter power amplifier connected to the programmable gain amplifier, wherein the transmitter power amplifier is configured to generate an output signal based on the mixed in-phase branch signal and the mixed quadrature branch signal; a power detector connected to the transmitter power amplifier and configured to detect a power of the output signal; a digital phase calibrator connected to the power detector and the phase compensator, and configured to instruct the phase compensator to iteratively use a plurality of phase compensation values, and obtain an optimal phase compensation value with a minimum difference among the plurality of phase compensation values; wherein the transmitter power amplifier is further configured to output an output signal corresponding to the optimal phase compensation.