Patent ID: 9436787
Filing Date: 2016-09-06
CPC Classification: G03F,G06F,H01L,Y02P

Claim Text:
1. An integrated circuit (IC) method comprising: receiving an IC design layout having main features; generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks, wherein the isolation distance is greater than or equal to a minimum isolation distance determined by a process window; calculating main pattern density PD calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density; choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR; generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and forming a tape-out data of the modified IC design layout for IC fabrication.