Patent ID: 9466624
Filing Date: 2016-10-11
CPC Classification: G02F,H01L

Claim Text:
1. A fabrication method of an array substrate, comprising: forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer on a base substrate, wherein the gate metal layer comprises at least a gate electrode and a metal pad; wherein the forming the gate insulating layer, the active layer and the source-drain metal layer on the base substrate comprises: forming a gate insulating film, an active layer film, and a source-drain metal film on the base substrate; and forming the gate insulating layer, the active layer and the source-drain metal layer by a single patterning process, wherein in a via hole is formed during the single pattern process, with the via hole penetrating the source-drain metal layer, the active layer and the gate insulating layer and reaching the metal pad.