Patent ID: 9245972
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device, comprising: providing a substrate having a first gate and a second gate respectively formed in a first region and a second region; forming an underlayer on the substrate to cover the first gate in the first region and the second gate in the second region; forming a patterned mask with a predetermined thickness on the underlayer in the first region; and removing the underlayer corresponding to the second gate in the second region by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate, a top surface of the underlayer remained in the first region has substantially equal height for forming a flat plane, and the top surface of the underlayer remained in the first region is lower than a top surface of the first gate.