Patent ID: 9425291
Filing Date: 2016-08-23
CPC Classification: B82Y,H01L

Claim Text:
1. A method of forming a semiconductor structure, said method comprising: providing a plurality of trench dielectric material portions located on a surface of a semiconductor substrate portion, wherein each trench dielectric material portion is separated from one another by an aspect ratio trapping trench; forming a semiconductor pillar structure within each aspect ratio trapping trench, wherein each semiconductor pillar structure includes alternating layers of a sacrificial III-V compound semiconductor material and a semiconductor channel material; recessing each trench dielectric material portion to expose each layer of said semiconductor channel material; forming a plurality of sacrificial gate structures on portions of each semiconductor pillar structure, wherein a dielectric spacer is present on each sidewall of each sacrificial gate structure; removing exposed portions of each semiconductor pillar structure not covered by said sacrificial gate structure and said dielectric spacer to provide a plurality of semiconductor nanosheet structures including a remaining portion of said alternating layers of sacrificial III-V compound semiconductor material and semiconductor channel material; removing each sacrificial gate structure; and suspending each remaining portion of each semiconductor channel material of each semiconductor nanosheet structure.