Patent ID: 9336903
Filing Date: 2016-05-10
CPC Classification: G11C

Claim Text:
1. A semiconductor apparatus comprising: an input buffer configured to receive and buffer data inputted through a node which is electrically coupled with a data input/output pad; a data input control unit configured to receive and transfer an output of the input buffer to a data input/output line in response to a write clock; a test loop control unit configured to receive a signal of the data input/output line and test latch data, output one of the signal of the data input/output line and the test latch data in response to a test mode signal; a data output control unit configured to receive and output an output of the test loop control unit in response to a read clock; an output inversion select unit configured to receive and output an output signal of the data output control unit by inverting or non-inverting it; and an output buffer configured to receive and buffer an output signal of the output inversion select unit and output a resultant signal to the node to which the data input/output pad and the input buffer are electrically coupled, wherein the data inputted by the input buffer is transferred to the output buffer through the data input control unit, the test loop control unit, the data output control unit and the output inversion select unit when the test loop control unit outputs the signal of the data input/output line.