Patent ID: 9261750
Filing Date: 2016-02-16
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: a display region; and a frame region surrounding the display region; the display region comprising a plurality of data lines, a plurality of scan lines and a plurality of scan connection lines, the plurality of data lines and the plurality of scan lines intersecting each other to divide the display region into a plurality of pixel regions, wherein the plurality of scan lines are electrically connected to the plurality of scan connection lines in a one-to-one correspondence in the display region; the array substrate has a top-gate configuration, the display region further comprises a bridge connection line, the scan lines are electrically connected to the scan connection lines by way of the bridge connection line; and the bridge connection line is disposed in the same layer as the data lines, the scan connection lines are disposed in the same layer as the scan lines, the bridge connection line is electrically connected to the scan lines by way of a first via hole, the bridge connection line is electrically connected to the scan connection lines by way of a second via hole.