Patent ID: 9443875
Filing Date: 2016-09-13
CPC Classification: H01L

Claim Text:
1. A manufacturing method of an array substrate, comprising steps of: forming, on a substrate, patterns including active regions of a first thin film transistor and a second thin film transistor by a patterning process; forming, on the substrate subjected to the above step, a gate insulation layer; forming, on the substrate subjected to the above steps, patterns including gates of the first thin film transistor and the second thin film transistor by a patterning process; forming, on the substrate subjected to the above steps, an isolation layer; forming, on the substrate subjected to the above steps, second contacting vias, which are used for electrically connecting sources and drains of the first thin film transistor and the second thin film transistor to the respective active regions, and a first contacting via, which is used for electrically connecting the gate of the second thin film transistor to the source of the first thin film transistor and is provided above the gate of the second thin film transistor; and on the substrate subjected to the above steps, forming patterns of corresponding sources and drains on the second contacting vias above the active regions of the first thin film transistor and the second thin film transistor by a patterning process, and forming, above the first contacting via above the gate of the second thin film transistor, a connection line for connecting the gate of the second thin film transistor to the source of the first thin film transistor at the same time.