Patent ID: 9419094
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: forming a base insulation layer on a substrate; exposing a portion of the substrate; forming a group III-V material layer on the exposed portion of the substrate, the group III-V material layer having a portion that protrudes above the base insulation layer; forming a barrier layer, on the group III-V material layer, the barrier layer covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer; forming a gate insulation film on the barrier layer; forming a gate electrode on the gate insulation film; and forming source and drain electrodes spaced apart from the gate electrode on the group III-V material layer, wherein the overall composition of the group III-V material layer is uniform; wherein the protruding portion of the group III-V material layer is substantially defect-free; and wherein the source and drain electrodes are formed to physically contact the barrier layer and the gate insulation film.