Patent ID: 9502421
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method, comprising: providing a substrate having a surface capable of sustaining epitaxial growth of a III-V semiconductor; applying a <100> silicon layer to the substrate; removing portions of the <100> silicon layer and revealing the surface of the substrate in a first region and producing a second region comprising <100> silicon; epitaxially growing a III-V semiconductor on the surface of the substrate in the first region; fabricating a HEMT structure in the first region; fabricating a CMOS device in the second region; depositing a dielectric layer over the first region and the second region; removing portions of the dielectric layer positioned over the first region and the second region and producing through holes exposing contact regions of the first region and the second region; depositing an electrically conductive material in the through holes; depositing an electrically conductive material onto the dielectric layer and the electrically conductive material in the through holes; and removing portions of the substrate under the first region and exposing the III-V semiconductor.