Patent ID: 9348402
Filing Date: 2016-05-24
CPC Classification: G06F,Y02D

Claim Text:
1. A multi-mode critical path for a central processing unit (CPU), comprising: an initial storage cell; a final storage cell, wherein both the initial storage cell and the final storage cell are configured to be clocked by a high speed clock during a high performance mode for the CPU and to be clocked by a low speed clock during a low performance mode for the CPU, and wherein a frequency for the high speed clock is greater than a frequency for the low speed clock; a plurality of first logic gates configured to form a first signal path between the initial storage cell and the final storage cell, wherein the plurality of first logic gates are configured to be operational during the high performance mode and to be non-operational during the low power mode, the plurality of first logic gates comprising devices configured to have at least one of a first channel length and a first threshold voltage; and a plurality of second logic gates configured to form a second signal path between the initial storage cell and the final storage cell, wherein the plurality of second logic gates are configured to receive power during the low power mode and to not receive power during the high performance mode, the plurality of second logic gates comprising devices configured to have at least one of a second channel length and a second threshold voltage, wherein the second channel length is longer than the first channel length and the first threshold voltage is lower than the second threshold voltage.