Patent ID: 9478307
Filing Date: 2016-10-25
CPC Classification: G11C

Claim Text:
1. A memory device comprising: a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, wherein the storage section is provided with a plurality of memory elements which are able to be written one time only and where information is held by changing resistance values in a non-written state and a written state, wherein the plurality of memory elements in the storage section are connected with each other in series, and all or some of the plurality of memory elements are configured such that it is possible to control conductivity or non-conductivity in a non-written state, wherein the plurality of memory elements which are connected with each other in series in the storage section are each formed with a transistor structure, and each of the memory elements is formed such that on resistances in a non-written state are resistance values which are different from each other due to gate lengths, densities of each of the semiconductor layers, and gate oxide film thicknesses being different from each other.