Patent ID: 9287266
Filing Date: 2016-03-15
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device comprising a first memory comprising: a first transistor, a second transistor, and a third transistor electrically connected to each other in series in order; and a fourth transistor, a fifth transistor, and a sixth transistor electrically connected to each other in series in order, wherein one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor are electrically connected to a high power supply potential line, wherein one of the source and the drain of the third transistor and one of the source and the drain of the sixth transistor are electrically connected to a low power supply potential line, wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to a first terminal, wherein a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to a second terminal, wherein the second terminal is electrically connected between the second transistor and the third transistor, wherein a gate of the second transistor and a gate of the third transistor are electrically connected to a third terminal, wherein the third terminal is electrically connected between the fifth transistor and the sixth transistor, wherein each of the second transistor and the fifth transistor is a p-channel transistor, and wherein each of the first transistor, the third transistor, the fourth transistor, and the sixth transistor is a transistor comprising an oxide semiconductor layer.