Patent ID: 9400753
Filing Date: 2016-07-26
CPC Classification: G06F,Y02D

Claim Text:
1. A control system comprising: a processing device configured to process data; a main storage device configured to store therein a plurality of pieces of the data; a cache memory configured to store therein a part of the plurality of pieces of the data stored in the main storage device; and a power supply unit configured to supply power, wherein the cache memory comprises a set-associative cache memory, the cache memory includes a memory area having the data stored therein, the memory area includes a first memory area allocated to a first way and a second memory area allocated to a second way, the first memory area capable of storing data necessitating being written back to the main storage device, the second memory area capable of storing data necessitating being written back to the main storage device, supplying of the power from the power supply unit to the cache memory is performed for each of the first memory area and the second memory area, and the control system further comprises a swapping unit configured to swap data stored in a predetermined entry of the first memory area with data stored in a predetermined entry of the second memory area when the data stored in the predetermined entry of the second memory area is data not necessitating being written back to the main storage device and the data stored in the predetermined entry of the first memory area becomes data necessitating being written back to the main storage device from the data not necessitating being written back to the main storage device.