Patent ID: 9362892
Filing Date: 2016-06-07
CPC Classification: G09G,G11C,H03K

Claim Text:
1. A scanning signal line drive circuit driving a plurality of scanning signal lines, the scanning signal line drive circuit comprising: a shift register including a plurality of bistable circuits which are cascade-connected to one another and sequentially making output signals of the plurality of bistable circuits active based on a clock signal which is supplied from the outside and periodically repeats an on level and an off level, wherein each of the bistable circuits comprises: outputting the output signal which is active based on the clock signal, the first driving unit has a first-node-turn-off switching element having a control terminal connected to the second node, a conduction terminal connected to the first node, and another conduction terminal to which off-level potential is supplied, the output unit has an output-node-turn-off switching element having a control terminal connected to the second node, a conduction terminal connected to an output node for outputting the output signal, and another conduction terminal to which off-level potential is supplied, the first driving unit and the second driving unit maintain the potential of the first node and the potential of the second node at off level, respectively, in a predetermined period of two horizontal scanning periods or longer in each vertical scanning period, supply of the clock signal to the plurality of bistable circuits stops in the predetermined period, the first driving unit in a bistable circuit in a final stage further comprises a first end switching element having a control terminal to which an end signal whose potential becomes an on level to make the output signal of the bistable circuit in the final stage in the shift register the first node and another conduction terminal to which off-level potential is supplied, and the second driving unit in each bistable circuit comprises a second end switching element having a control terminal to which the end signal is supplied, a conduction terminal connected to the second node, and another conduction terminal to which off-level potential is supplied.