Patent ID: 9343127
Filing Date: 2016-05-17
CPC Classification: G06F,G11C

Claim Text:
1. A memory controller for accessing a memory device, the memory device including a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address, the memory device being capable of having an adaptable number of open rows, the memory controller comprising: an arbiter for receiving and scheduling a memory access request from a requestor, the memory access request including a logical address, the arbiter being configured to determine the adaptable number of open rows for the memory access request; a memory mapper coupled to the arbiter for translating the logical address into a physical address including a row address and a column address; and a command generator coupled to the memory mapper and the arbiter for generating a sequence of commands corresponding to the memory access request and for sending the sequence of commands to the memory device, one command of the sequence of commands including a row mode indicator specifying the adaptable number of open rows; wherein the arbiter is configured to monitor a memory access pattern of the requestor to determine the adaptable number of open rows by monitoring a ratio of row misses to row hits, and to determine the adaptable number of open rows to be more than one row when the ratio of row misses to row hits exceeds a threshold.