Patent ID: 9378799
Filing Date: 2016-06-28
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a first control circuit configured to produce a hit signal in response to an internal refresh command being issued; a second control circuit configured to produce a control signal in response to the hit signal being produced, the control signal changing between first and second levels in response to temperature information indicative of a temperature of the semiconductor device; a memory cell array including a plurality of memory cells; an output buffer coupled to the memory cell array and configured to output data read from the memory cells; a calibration circuit coupled to the output buffer and configured to perform, when activated, a calibration operation on the output buffer to adjust an impedance of the output buffer; a refresh circuit coupled to the memory cell array and configured to perform a refresh operation on the memory cells of the memory cell array in response to the internal refresh command; and a third control circuit configured to issue the internal refresh command when the control signal takes the first level and to activate the calibration circuit in response to the hit signal when the control signal takes the second level.