Patent ID: 9337239
Filing Date: 2016-05-10
CPC Classification: G11C,H01L

Claim Text:
1. An electronic device comprising a semiconductor memory unit, the semiconductor memory unit comprising: a first cell array including a plurality of first-type memory cells disposed at a first level; a first peripheral circuit configured to control the first cell array and disposed at the first level; a second cell array including a plurality of second-type memory cells disposed at a second level, wherein the first-type memory cells are different from the second-type memory cells; and a second peripheral circuit configured to control the second cell array and disposed at the first level, wherein the second level is higher than the first level, the second cell array overlaps with the second peripheral circuit and the first cell array, the plurality of first-type memory cells includes a portion of a semiconductor substrate as their components while the plurality of second-type memory cells do not include a portion of the semiconductor substrate, the first peripheral circuit includes a first peripheral circuit transistor which includes a portion of the semiconductor substrate, the second peripheral circuit includes a second peripheral circuit transistor which includes a portion of the semiconductor substrate, and the first cell array includes a cell transistor and a selection transistor each including a portion of the semiconductor substrate.