Patent ID: 9230684
Filing Date: 2016-01-05
CPC Classification: G06F,G11C

Claim Text:
1. A memory controller controlling a NAND memory having D bits/cell where D is an integer of two or more, comprising: a code encoder which generates a code word having correction capability oft symbols by performing an error correction coding process based on an information data which is to be written in the NAND memory where t is an integer of two or more; a write control unit which controls writing of the code word to the NAND memory; a read control unit which controls reading of the code word from the NAND memory; a code decoder which decodes the code word read from the NAND memory; and a memory interface which performs writing to the NAND memory and reading from the NAND memory, wherein the write control unit writes, in adjacent word lines in a block of the NAND memory, code data to the NAND memory into 2×D different pages for each word line, the data being formed from 2×D/t or more code words, one code word among the 2×D/t or more code words being written to t or less pages among the 2×D pages, the 2×D pages being included in B blocks of the NAND memory, where B is an integer of one or more, wherein N is code length of the code word and greater than t, and B is smaller than N/t, and wherein said code data in the 2×D different pages forms a basis for error correction of the information data.