Patent ID: 9355740
Filing Date: 2016-05-31
CPC Classification: G11C

Claim Text:
1. A semiconductor nonvolatile memory device comprising: a plurality of transistors arranged in rows and columns to form a matrix, each transistor including a source region and a drain region separately disposed in a semiconductor region, and a gate disposed on the semiconductor region in a channel region between the source region and the drain region, the transistors in the same row being connected in series to form a transistor string having a first terminal and a second terminal; a plurality of first wiring lines each corresponding to one of the columns, and being connected to the gates of the transistors of the corresponding column; a common first electrode connected to each semiconductor region in which each transistor is disposed; and a write circuit that selects one of the first wiring lines and one of the transistor strings, and applies a first voltage to the first electrode, a first write voltage to the selected first wiring line, a second voltage to the other first wiring lines, and a second write voltage to the first terminal and the second terminal of the selected transistor string in a write operation, the first voltage being between the first write voltage and the second write voltage, and the second write voltage being between the first voltage and the second voltage, wherein when the transistors are n-channel transistors, the first write voltage, the first voltage, the second write voltage, and the second voltage meet the following relationship: the first write voltage<the first voltage<the second write voltage<the second voltage, and when the transistors are p-channel transistors, the first write voltage, the first voltage, the second write voltage, and the second voltage meet the following relationship: the first write voltage>the first voltage>the second write voltage>the second voltage.