Patent ID: 9460804
Filing Date: 2016-10-04
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device comprising: a memory cell array in which memory cells is provided in a matrix; word lines connected to the memory cells; bit lines connected to the memory cells; a control circuit configured to control potentials of the word lines and potentials of bit lines, a constant voltage generation circuit, wherein data in an n number of memory cells among the memory cells is simultaneously read from memory cell array; an h (2<h<n) number of memory cells among the n number of memory cells is used as flag cells, data of the flag cells is determined by a majority decision for the read data from the h number of memory cells, and in a read result of a k (k<n) number of memory cells among the read n number of memory cells, the read data from the k number of memory cells is converted based on data of the flag cells determined by a majority decision.