Patent ID: 9436611
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. A processor capable of storing trace data, comprising: a core adapted to execute programs; and a cache memory electrically connected to the core and comprising a core way and a trace way, wherein the core way is adapted to store data that is required when the core executes the programs, and wherein the trace way is adapted to store data that is generated during debugging operations of the core, wherein each of the core way and the trace way comprises a data memory, a tag memory and a write back address memory, wherein the data memory of the core way is adapted to store the data that is required when the core executes the programs, wherein the data memory of the trace way is adapted to store the data that is generated during the debugging operations of the core, wherein the tag memory stores a plurality of states of row and a plurality of tags, and selects one of the plurality of states of row and one of the plurality of tags according to an address outputted by the core, wherein the write back address memory is adapted to store a plurality of row addresses, wherein the cache memory further comprises: a data/trace cache control register adapted to store a predetermined trace address and a plurality of cache way control bits, wherein each of the plurality of cache way control bits corresponds to a respective one of the data memories and comprises two state values; a line index calculator generating a trace address, a trace data and a trace enabling bit according to the plurality of cache way control bits, a valid trace bit and the data that is generated during the debugging operations of the core; a cache controller generating a core data, a core enabling bit and a cache way cleaning bit according to the address outputted by the core and the data that is required when the core executes the programs, wherein the address comprises a set index and an address tag; a plurality of data/trace configuration units, each corresponding to a respective one of the plurality of cache way control bits, wherein each of the plurality of data/trace configuration units controls the core data to be written into the data memory according to one of the two state values of the cache way control bit, the set index and the core enabling bit, or controls the trace data to be written into the data memory according to another one of the two state values of the cache way control bit, the trace address and the trace enabling bit; a plurality of comparators, each comparing the address tag with the tag outputted by the tag memory and generating a tag hit bit; a plurality of trace protection units, each generating a locking bit and a hit bit according to a corresponding one of the plurality of cache way control bits, the plurality of states of row outputted by the tag memory and the tag hit bit; and a plurality of trace dump units, each generating a write-back address according to a corresponding one of the plurality of cache way control bits, the plurality of row addresses, the plurality of states of row and the predetermined trace address.