Patent ID: 9515086
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a stack including gate electrodes and insulating layers alternately and repeatedly stacked on a substrate; a channel structure connected to the substrate and extending through the stack; for each gate electrode: wherein the tunnel insulating layer comprises a first tunnel insulating layer between the charge storing layer and the channel structure, a high-k dielectric layer between the charge storing layer and the first tunnel insulating layer, and a second tunnel insulating layer between the first tunnel insulating layer and the high-k dielectric layer, the first tunnel insulating layer comprises a silicon oxide layer, and the second tunnel insulating layer comprises a silicon nitride layer or a silicon oxynitride layer, wherein, at each gate electrode, the blocking insulating layer extends between the gate electrode and its corresponding insulating layers.