Patent ID: 9379123
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor memory device, comprising: forming patterns that are adjacent one another on a semiconductor substrate; forming a trench in the semiconductor substrate between the patterns; forming a sacrificial pattern in the trench that defines an air gap and that covers lower sidewalls of the patterns; forming a blocking insulating layer and a gate electrode on the patterns and the sacrificial pattern; and removing the sacrificial pattern through the air gap to form an expanded air gap exposing a bottom surface of the blocking insulating layer between the patterns, wherein forming the sacrificial pattern comprises: forming a first sacrificial layer in the trench to expose sidewalls of the patterns; forming a porous insulating layer with pores on the patterns, the porous insulating layer extending on a top surface of the first sacrificial layer; removing the first sacrificial layer through the pores of the porous insulating layer to form the air gap below the porous insulating layer; forming a second sacrificial layer on the porous insulating layer to fill a gap between the patterns; and recessing the porous insulating layer and the second sacrificial layer to expose sidewalls of the patterns.