Patent ID: 9275689
Filing Date: 2016-03-01
CPC Classification: G11C,H01L,H05K

Claim Text:
1. A semiconductor device comprising: first to n-th (n is an integer equal to or greater than 2) DDR a multi-layer wiring board having a plurality of first address lines formed of a first wiring layer of the multi-layer wiring board and a plurality of second address lines formed of a second wiring layer of the multi-layer wiring board, the first wiring layer being at a different level from the second wiring layer, in each of the first and the second wiring layer, each of the first and the second address lines has a first end and a second end; and capacitors each of which is coupled to the second end of each of the first and the second address lines, wherein the first address terminals of each of the first to n-th DDR wherein the second address terminals of each of the first to n-th DDR