Patent ID: 9378318
Filing Date: 2016-06-28
CPC Classification: G01R,G03F,G06F,G21K

Claim Text:
1. A method of masking scan channels in a semiconductor chip, comprising storing, in a first memory of a first mask logic, a first channel mask enable decode for a first mask that masks a first scan channel of a circuit under test; storing, in a second memory of a first mask logic, a second channel mask enable decode for a second mask that masks a second scan channel of the circuit under test; receiving at least three channel mask enable signals, a first channel mask enable signal on a first channel mask enable pin, a second channel mask enable signal on a second channel mask enable pin, and a third channel mask enable signal on a third channel mask enable pin, wherein the first, second, and third channel mask enable signals produce a channel mask enable encode; comparing with a first comparator the first channel mask enable decode to the channel mask enable encode; comparing with a second comparator the second channel mask enable decode to the channel mask enable encode; masking the first scan channel with the first mask when the first channel mask enable decode matches the channel mask enable encode; and masking the second scan channel with the second mask when the second channel mask enable decode matches the channel mask enable encode.