Patent ID: 9263292
Filing Date: 2016-02-16
CPC Classification: B81C,H01L

Claim Text:
1. A method for planarizing topographies on a surface of a semiconductor substrate including at least one cavity or channel ranging from several microns to several mils in depth, said method comprising: providing a planarizing material atop said surface including filling said at least one cavity or channel with said planarizing material to produce a planarized surface, said planarizing material a single polymer material; forming a continuous hard mask coating over the planarized surface of the filled cavity or channel; patterning a feature over said filled at least one cavity or channel using the hard mask structure; etching away the planarizing single polymer fill material from said cavity or channel according to said patterned feature to produce an overhang structure including an opening atop said cavity or channel, said overhang structure including overhang portions extending over opposite sides of said cavity or channel; and, depositing a material on a lower surface of said cavity or channel through said opening, wherein said step of filling said at least one cavity or channel with said planarizing material includes implementing a screening technique.