Patent ID: 9343180
Filing Date: 2016-05-17
CPC Classification: G06F,G11C,Y02B,Y02D

Claim Text:
1. An apparatus, comprising: a plurality of stacked memory dies including a first memory die and a second memory die; a memory vault formed from stacked memory arrays of the plurality of stacked memory dies, the stacked memory arrays including a first memory array in the first memory die and a second memory array in the second memory die, wherein the plurality of stacked memory dies are selected such that addresses associated with contiguous areas of defective memory cells in the first memory die used to form the memory vault do not overlap with addresses associated with another contiguous areas of defective memory cells in the second memory die used to form the memory vault; and a spare memory array included in the memory vault, wherein the memory vault is configured such that at least one first contiguous area of operational memory cells on the spare memory array is located at a starting memory address including at least one of a bank address, a row address, or a column address in common with a second contiguous area of operational memory cells on at least one of the first and second memory dies, wherein the apparatus further comprising a repair decode assessment module to estimate a latency associated with translating a requested memory address to a repair address; and a decision module to cause the requested memory address to be passed to a memory address decoder associated with the memory vault if the latency estimated by the repair decode assessment module is greater than a selected amount.