Patent ID: 9373549
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device comprising: forming first and second sacrificial contact plugs on a substrate; forming a gate structure in a region between the first and second sacrificial contact plugs and over the substrate wherein forming the gate structure includes: forming a first ILD layer over the first and second sacrificial contact plugs; patterning the first ILD layer, thereby removing the first ILD layer in the region between the first and second sacrificial contact plugs; and depositing a high-k dielectric material and a metal material to thereby form the gate structure; selectively removing the first and second sacrificial contact plugs to define first and second source and drain regions; epitaxially growing first and second source and drain features in the first and second source and drain regions; and forming first and second contact features over the first and second source and drain features, the first and second contact features being in electrical contact with the first and second source and drain features.