Patent ID: 9397103
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A dynamic memory structure, comprising: a substrate; a first strip semiconductor material disposed on said substrate and extending along a first direction; a second strip semiconductor material disposed on said substrate and extending along said first direction; a gate standing astride said first strip semiconductor material, extending along a second direction and dividing said first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region and dividing said second strip semiconductor material into a second source terminal, a second drain terminal, and a second channel region, wherein said first drain terminal and said second drain terminal form into an integrated drain terminal, wherein the gate further comprises a first curved surface over said first strip semiconductor material and a second curved surface over said second strip semiconductor material; a first dielectric layer partially sandwiched between said gate and said first strip semiconductor material and partially sandwiched between said gate and said second strip semiconductor material; and a first capacitor unit disposed on said substrate and comprising said first source terminal serving as a first bottom electrode, a second dielectric layer partially covering said first source terminal to serve as a first capacitor dielectric layer and a capacitor metal layer partially covering said second dielectric layer to serve as a top electrode.