Patent ID: 9299393
Filing Date: 2016-03-29
CPC Classification: G11C,H01L

Claim Text:
1. A memory device comprising: a first cell array comprising first memory cells; a second cell array comprising second memory cells; first word lines electrically connected to only the first cell array between the first cell array and the second cell array; second word lines electrically connected to only the second cell array between the first cell array and the second cell array; a word line driver circuit electrically connected to the first word lines and to the second word lines; first bit lines electrically connected to only the first cell array between the first cell array and the second cell array; second bit lines electrically connected to only the second cell array between the first cell array and the second cell array; a first bit line driver circuit electrically connected to the first bit lines, the first bit line driver circuit comprising a first bit line reading circuit; and a second bit line driver circuit electrically connected to the second bit lines, the second bit line driver circuit comprising a second bit line reading circuit, wherein the first cell array and the second cell array overlap with the first bit line reading circuit and the second bit line reading circuit, respectively, and wherein any one of the first bit line reading circuit, and the second bit line reading circuit includes a transistor comprising a channel formation region in polycrystalline silicon, single crystal silicon, polycrystalline germanium, or single crystal germanium.