Patent ID: 9324699
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a wiring member having a first surface and a second surface opposite the first surface, a plurality of wirings being formed in the wiring member, a plurality of external terminals being arranged on the second surface; a memory chip having a first main surface on which a plurality of first electrodes are formed; and a logic chip for controlling the memory chip having a second main surface on which a plurality of second electrodes and a plurality of third electrodes are formed, wherein the memory chip is mounted over the first surface of the wiring member such that the first main surface of the memory chip faces the first surface of the wiring member, and such that the memory chip is located over the logic chip, wherein all of the first electrodes of the memory chip are electrically connected with the second electrodes of the logic chip, respectively, and wherein the third electrodes of the logic chip are electrically connected with the external terminals via the wirings of the wiring member, respectively.