Patent ID: 9362296
Filing Date: 2016-06-07
CPC Classification: G11C,H01L

Claim Text:
1. A non-volatile memory device comprising: a semiconductor substrate; a tunnel dielectric formed on the substrate; a floating gate formed on the tunnel dielectric, wherein the floating gate comprises a hybrid floating gate structure including a lower layer and an upper metal layer; a first interfacial layer formed on the floating gate; an inter-gate dielectric stack formed on the first interfacial layer; and a control gate formed on the inter-gate dielectric stack, wherein the inter-gate dielectric stack comprises a first layer, a second layer and a third layer, the first layer being formed on the first interfacial layer and the control gate structure being formed on the third layer, the first and third layers having a higher k-value than the second layer which is sandwiched therebetween, and wherein the first interfacial layer comprises a high k-value material.