Patent ID: 9343506
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A memory array, comprising: a first series of access/sense lines extending along a first lateral direction relative to an upper surface of a substrate; a second series of access/sense lines elevationally, over the first series of access/sense lines and extending along a second lateral direction which is substantially orthogonal to the first lateral direction; and memory cells extending vertically upward relative to the upper surface and being disposed between the first and second series of access/sense lines; each memory cell being uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series; the memory cells comprising programmable material; at least some of the programmable material within each memory cell being a polygonal structure having a sidewall that extends along a third lateral direction which is different from the first and second lateral directions.