Patent ID: 9286076
Filing Date: 2016-03-15
CPC Classification: G06F

Claim Text:
1. A method for intra-instructional transaction abort handling comprising: using, by a processing circuit, an emulation routine to execute an instruction within a transaction, the instruction comprising at least one unit of operation, the transaction effectively delaying committing stores to memory until successful completion of the transaction; setting a transaction block abort (TXBA) flag based on determining that the emulation of the instruction has made updates to one or more of: an architected facility and an architected facility buffer, wherein the architected facility buffer comprises one or more rename registers that store data temporarily until instruction completion moves the data to a targeted location; and based on receiving an abort indication, terminating the emulation of the instruction prior to completing the execution of the instruction, the terminating performed after completing, by the emulation routine, any previously initiated unit of operation of the instruction, wherein the terminating of the emulation of the instruction comprises: