Patent ID: 9406590
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A chip package, comprising: a semiconductor chip with an upper surface and a lower surface, the semiconductor chip having at least one first conducting pad in contact with a sidewall of the semiconductor chip, and a first hole corresponding to the first conducting pad, the first hole extending from the upper surface to the lower surface to expose the first conducting pad; an isolation layer extending from the upper surface to the lower surface, part of the isolation layer positioned in the first hole, wherein the isolation layer has at least one opening to expose the first conducting pad; a redistributing metal layer disposed on the isolation layer and having at least one redistributing metal line corresponding to the first conducting pad, and the redistributing metal line electrically connecting to the first conducting pad through the opening; and at least one bonding pad disposed on the isolation layer and positioned at a side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the bonding pad positioned at the side and the first conducting pad that contacted with the sidewall of the semiconductor chip.