Patent ID: 9419110
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method for growing a III-V semiconductor structure on an area of a Si n Ge 1-n substrate, wherein n is from 0 to 1, comprising the steps of: (a) setting the temperature of a Si (b) exposing an area of the Si (c) setting the temperature of the Si (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the doped region; (e) setting the temperature of the Si (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas, thereby forming a III-V semiconductor structure.