Patent ID: 9383999
Filing Date: 2016-07-05
CPC Classification: G06F

Claim Text:
1. A data processing apparatus comprising: processing circuitry for processing data; an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to process said data; a status store for storing a current condition state of said processing circuitry, said current condition state being modifiable during processing of said data; wherein said program instructions include a conditional compare instruction, and said instruction decoder is responsive to said conditional compare instruction to generate control signals for controlling said processing circuitry to perform a conditional compare operation comprising: (i) if said current condition state passes a test condition, then performing a compare operation on a first operand and a second operand and setting said current condition state to a result condition state generated during said compare operation; and (ii) if said current condition state fails said test condition, then setting said current condition state to a fail condition state specified by said conditional compare instruction.