Patent ID: 9384850
Filing Date: 2016-07-05
CPC Classification: G11C

Claim Text:
1. A one-time programmable (OTP) memory cell read circuit comprising: an OTP bit memory element operable to store a data bit; a programmed-on OTP reference cell operable to generate a first reference current; a first current mirror having a first input coupled to receive the first reference current, and having a second input coupled to a current output of the OTP bit memory element and operable to sink current from the OTP bit memory element, wherein the amount of current the first current mirror sinks from the OTP bit memory element is proportional to the first reference current; a programmed-off OTP reference cell operable to generate a second reference current; a second current mirror having a first input coupled to receive the second reference current, and having a second input coupled to the current output of the OTP bit memory element and operable to sink current from the OTP bit memory element, wherein the amount of current the second current mirror sinks from the OTP bit memory element is proportional to the second reference current; and a comparator operable to compare the voltage at the current output of the OTP bit memory element to a threshold voltage, and operable to output a logical “1” if the voltage is higher than the threshold voltage, and operable to output a logical “0” if the voltage is lower than the threshold voltage.