Patent ID: 9419002
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a bit line contact; a bit line disposed on the bit line contact and electrically connected to the bit line contact; and a spacer disposed on a sidewall of the bit line contact and a sidewall of the bit line, wherein the spacer has a structure in which a first spacer with a first dielectric constant, a second spacer with a second dielectric constant, a third spacer with a third dielectric constant, and a protecting spacer with a fourth dielectric constant are stacked, the second spacer having a different dielectric constant from those of the first, third, and protecting spacers, the protecting spacer having a same dielectric constant as those of the first and third spacers, the protecting spacer capping a lower portion of the second spacer.