Patent ID: 9245073
Filing Date: 2016-01-26
CPC Classification: G06F

Claim Text:
1. A method, performed by at least one processor, comprising: receiving, by the at least one processor, a layout of a circuit; generating, by the at least one processor using the layout, a netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively; and performing, by the at least one processor, a simulation on the netlist such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads, wherein generating, by the at least one processor, the netlist comprises: defining a plurality of zones with the different PDs in the layout; and generating the netlist with the indicated PD-dependent mismatch elements in different zones, respectively, wherein generating , by the at least one processor, the netlist with the indicated PD-dependent mismatch elements in the different zones comprises: generating a post-layout netlist from the layout; and back-annotating the PD-dependent mismatch elements in the post-layout netlist with the corresponding zones to generate the netlist with the indicated PD-dependent mismatch elements.