Patent ID: 9449974
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate with a n-type transistor forming region and a p-type transistor forming region; an n-type transistor in the n-type transistor forming region of the semiconductor substrate, the n-type transistor comprising, in cross section, (a) a first gate insulating film on the semiconductor substrate, (b) a first gate electrode on the first gate insulating film, the first gate electrode including a metal material, (c) a first side wall film at opposite sides of the first gate electrode, (d) a first stress applying film at the opposite sides of the first gate electrode, at least a portion of the first side wall insulating film being between the first gate insulating film and the first stress applying film, (e) first source/drain regions in the semiconductor substrate at the both sides of the first gate electrode, and (f) first silicide regions at surfaces of the first source/drain regions and at the opposite sides of the first gate electrode, the first silicide regions being between the first source/drain regions and the first stress applying layer and are in contact with the first stress applying layer; a p-type transistor in the p-type transistor forming region of the semiconductor substrate, the p-type transistor comprising, in cross section, (a) a second gate insulating film on the semiconductor substrate, (b) a second gate electrode on the second insulating film, the second gate electrode including a metal material, (c) a second side wall film at opposite sides of the second gate electrode, (d) a second stress applying film at the opposite sides of the second gate electrode, at least a portion of the second side wall insulating film being between the second gate insulating film and the second stress applying film, (e) second source/drain regions in the semiconductor substrate at the both sides of the second gate electrode, and (f) second silicide regions at surfaces of the second source/drain regions and at the opposite sides of the second gate electrode, the second silicide regions being between the second source/drain regions and the second stress applying layer and are in contact with the second stress applying layer; in the n-type transistor forming region of the semiconductor substrate, a third stress applying film on the first stress applying film including the first gate electrode; and in the p-type transistor forming region of the semiconductor substrate, a fourth stress applying film on the second stress applying film including the second gate electrode.