Patent ID: 9412720
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a substrate; a first semiconductor chip on the substrate, wherein the first semiconductor chip comprises a controller; a second semiconductor chip on the substrate, wherein the second semiconductor chip comprises a buffer chip; a chip stack on the first and the second semiconductor chips and having at least one third semiconductor chip; an adhesion layer between the first semiconductor chip and the chip stack and between the second semiconductor chip and the chip stack; a first conductive connection, wherein the first conductive connection penetrates the adhesion layer and connects the substrate to the first semiconductor chip, wherein a portion of the first conductive connection is between the first and second semiconductor chips; and a second conductive connection, wherein the second conductive connection penetrates the adhesion layer and connects the substrate to the second semiconductor chip, wherein a portion of the second conductive connection is between the first and second semiconductor chips; and a support plate between the substrate and the chip stack, wherein the adhesion layer is directly on the first semiconductor chip, the second semiconductor chip, and the support plate; wherein the chip stack includes a plurality of third semiconductor chips, wherein the plurality of third semiconductor chips comprises a plurality of memory chips, and wherein a sidewall of the first semiconductor chip is coplanar with a sidewall of a first one of the third semiconductor chips.