Patent ID: 9406678
Filing Date: 2016-08-02
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: preparing a substrate including a PMOS region and an NMOS region; forming a high-k dielectric layer over the substrate; forming a threshold voltage modulation layer over the high-k dielectric layer of the NMOS region; forming a first work function layer over the threshold voltage modulation layer of the NMOS region and the high-k dielectric layer of the PMOS region; forming, in-situ, an oxidation suppressing layer over the first work function layer of the NMOS region without an air break after the forming of the first work function layer; forming a second work function layer over the oxidation suppressing layer and the first work function layer of the PMOS region; forming, over the PMOS region of the substrate, a first gate stack that includes the high-k dielectric layer, the first work function layer and the second work function layer; and forming, over the NMOS region of the substrate, a second gate stack which includes the high-k dielectric layer, the threshold voltage modulation layer, the first work function layer, the oxidation suppressing layer and the second work function layer, wherein the oxidation suppressing layer is formed only the second gate stack.