Patent ID: 9257988
Filing Date: 2016-02-09
CPC Classification: H03K

Claim Text:
1. An apparatus comprising: a circuit having a decoder in combination with a bit-slice mapping unit, where the circuit has as input an x-bit input word having a binary value at each x-bit position, where the x-bit input word is input into the decoder which has a z-bit source word output having binary value at each z-bit position, where the z-bit source word is input into the mapping unit which also receives y-bit selector address input from outside the circuit, where the circuit outputs an output word having a binary value at each position, being an integer and α is an integer ≧2, where n>z>x, where each position is hardwire connectable to a subset of said z-bit positions (the “Mapping Subsets”) of the z-bit source word.