Patent ID: 9378824
Filing Date: 2016-06-28
CPC Classification: G11C

Claim Text:
1. A memory system, comprising: a memory device including a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of pages, wherein each of the plurality of pages includes a plurality of memory cells, and wherein the plurality of memory cells are coupled to a plurality of word lines; and a controller suitable for grouping the plurality of word lines to N number of word line zones, where N is integer equal to or greater than 2, wherein each of the word line zones includes M number of memory cells, where M is integer equal to or greater than 2, and wherein the controller performs a bad block management operation for word line zone by word line zone, wherein the controller stores a table having bitmap information for the N number of word line zones, checks if a bad word line zone exists among the N number of word line zones using the bitmap information stored in the table, and performs the bad block management operation for the bad word line zone.