Patent ID: 9280930
Filing Date: 2016-03-08
CPC Classification: G09G

Claim Text:
1. A circuit for a flat panel display capable to display images, comprising: an image storage and/or processing block for said images to be displayed, made up of appropriate image data; a display and timing controller block controlling said display operation; an image pixel matrix containing a multitude of row and column arranged pixel elements; one or more controlled row driver blocks; one or more controlled column driver blocks; and a pixel pre-charge and display drive mechanism for displaying said pixel elements employing a back to back pre-charge operation applied in each case to pairs of row and/or column drive activated pixel element display operations of said image data, whereby said back to back pre-charge operation is signified by during every pair of pixel element display operating sequences two differently modified timing sequences within every two row and/or column drive activated sequential pixel element display operations are used at a time, replacing said pre-charge operation by an immediately following activated pixel element data display operation for every pixel element from each column during a second row oriented sequence of pixel activations thus writing image data back to back into identical pixels avoiding the pre-charge operation completely; thus functionally substituting a potentially second pre-charge operation directly by the next activated pixel element display drive operation of the same pixel according to an adjacently following period of time within a pixel driving scheme itself and thus executing said back to back pre-charge operation for each single pixel element as one and the same given entity.