Patent ID: 9367356
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A method, implemented at a computer system that includes one or more processors and a memory resource, for coordinating access to the memory resource, the method comprising: ascertaining that a high priority activity is accessing the memory resource, and that a lower priority activity concurrently requests access to the memory resource; responsive to said ascertaining, suppressing the lower priority activity by at least caching one or more memory operations of the lower priority activity in a cache memory while the high priority activity accesses the memory resource, rather than writing the one or more memory operations to the memory resource while the high priority activity accesses the memory resource; subsequent to suppressing the lower priority activity, determining that the high priority activity has stopped accessing the memory resource; based at least on determining that the high priority activity has stopped accessing the memory resource, transacting the one or more memory operations from the cache memory to the memory resource; and delaying one or more data writes by the high priority activity to the memory resource until after the one or more memory operations have been transacted from the cache memory to the memory resource.