Patent ID: 9329235
Filing Date: 2016-05-03
CPC Classification: G01R

Claim Text:
1. A method for localizing at least one scan flop associated with a fault, the method comprising: generating a first test pattern comprising first scan-in data and first control data, the first control data of the first test pattern at least identifying a first sequence of compressor outputs used to generate a first fault data, the first sequence of compressor outputs identifying a sequential combination of outputs of a test circuit for generating the first fault data; receiving first fault data, the received first fault data generated by applying the first scan-in data to scan flops in the test circuit of an integrated circuit based at least on the first control data and compressing an output of the test circuit using the first sequence of compressor outputs; responsive to determining that the first fault data indicates presence of a fault in the integrated circuit, generating a second test pattern comprising second scan-in data and second control data, the second control data of the second test pattern at least identifying a second sequence of compressor outputs used to generate a second fault data, the second sequence of compressor outputs different than the first sequence of compressor outputs; receiving second fault data, the received second fault data generated by applying the second scan-in data to the scan flops in the test circuit based at least on the second control data and compressing the output of the test circuit using the second sequence of compressor outputs; and identifying at least one scan flop associated with the fault by identifying at least one scan flop common to first scan flops and second scan flops, an incorrect output of the first scan flops resulting in the first fault data, and an incorrect output of the second scan flops resulting in the second fault data.