Patent ID: 9285997
Filing Date: 2016-03-15
CPC Classification: G06F,G11C,Y02D

Claim Text:
1. An apparatus comprising a three-dimensional (3D) memory array that includes: a plurality of tiles; a plurality of blocks, wherein individual tiles of the plurality of tiles and individual blocks of the plurality of blocks each include a plurality of tile blocks having memory elements, wherein the plurality of tile blocks include at least a first array of tile blocks and a second array of tile blocks, wherein the tile blocks are accessible for read or write according to a tile address to identify a tile of the plurality of tiles and a block address to identify a block of the plurality of blocks; and a data restructuring module to modify, based on the tile address, an order of data to be read from or written to the tile blocks in a first mode at a first point in time and in a second mode at a second point in time that is different than the first point in time, wherein in the first mode data addressed to a first tile of the second array is to be transferred subsequent to transfer of data addressed to the first tile of the first array, data addressed to a second tile of the first array is to be transferred subsequent to transfer of data addressed to the first tile of the second array, and data addressed to the second tile of the second array is to be transferred subsequent to transfer of data addressed to the second tile of the first array, wherein in the second mode only data addressed to the first array is to be transferred and a power supply to the second array is disabled.