Patent ID: 9304525
Filing Date: 2016-04-05
CPC Classification: G05F,G11C,H03K

Claim Text:
1. A semiconductor device, comprising: a) a first transmission gate coupled between a reference voltage and an adjusted reference voltage, and being off during a calibration sequence, wherein the calibration sequence comprises first and second phases; b) a digital-to-analog converter (DAC) configured to provide an adjustment voltage to be added to or subtracted from the reference voltage to produce the adjusted reference voltage; c) second and third transmission gates coupled between the reference voltage and the adjusted reference voltage, and being enabled to provide the adjusted reference voltage during the first phase and disabled during the second phase; and d) fourth and fifth transmission gates coupled between the reference voltage and the adjusted reference voltage, and being disabled during the first phase and enabled to provide the adjusted reference voltage during the second phase, wherein the adjustment voltage is received between the intervening node between the second and third transmission gates and the intervening node between the fourth and fifth transmission gates.