Patent ID: 9461159
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A method for fabricating a field effect transistor (FET) device on a common wafer with other FET devices, said method comprising: providing a plurality of semiconductor layers including a substrate, a buffer layer deposited on the substrate, a channel layer deposited on the buffer layer, a barrier layer deposited on the channel layer, an undoped etch stop layer deposited on the barrier layer, and a heavily doped cap layer deposited on the undoped etch stop layer; depositing an electron-beam lithography (EBL) photoresist layer on the semiconductor wafer; patterning the EBL photoresist layer using an electron-beam lithography process to form a wide an upper opening in the EBL photoresist layer and a narrow lower opening in the EBL photoresist layer where the upper opening is wider than the lower opening; performing a first etch in a first chemical solution through the upper and lower openings in the EBL photoresist layer and into the wafer for a predetermined period of time; and performing a second etch in a second chemical solution through the upper and lower openings in the EBL photoresist layer for a predetermined period of time to form a gate recess to a depth defined by a transition between the undoped etch stop layer and the barrier layer.