Patent ID: 9460021
Filing Date: 2016-10-04
CPC Classification: G06F,G11C,Y02D

Claim Text:
1. A system comprising: a plurality of volatile memory devices corresponding to a first memory hierarchy, the plurality of volatile memory devices disposed on a first memory module that is coupled to a memory controller by a first signal path; a nonvolatile memory device corresponding to a second memory hierarchy, the nonvolatile memory device disposed on a second memory module that is coupled to the first memory module by a second signal path, wherein a plurality of memory transactions for the nonvolatile memory device corresponding to the second memory hierarchy are transferred from the memory controller to the first memory hierarchy using the first signal path, and wherein data associated with an accumulation of the plurality of memory transactions is to be written from the first memory hierarchy to the second memory hierarchy using the second signal path, a first control signal, and a second control signal; a durability circuit to generate the first control signal in view of a detection of wear in the nonvolatile memory device based on a comparison of a number of writes to a memory location in the nonvolatile memory device to a write threshold value; and a defect circuit to generate the second control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from the memory location to a stored value.