Patent ID: 9305916
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A Silicon-On-Insulator (SOI) Electro-Static-Discharge (ESD) protection structure comprising: a shunting SOI transistor having a first source/drain connected to a first terminal, a second source/train connected to a second terminal, and a gate connected to a gate node, the gate controlling a channel in a channel region between the first and second source/drains; a buried oxide under the first and second source/drains and the channel region, the buried oxide preventing current flow from the first and second source/drains and the channel region to a substrate, wherein a parasitic substrate diode is not available for ESD protection under the shunting SOI transistor; a resistor connected between the first terminal and a filter node; a capacitor connected between the second terminal and the filter node; a n-channel pass transistor having a gate connected to the first terminal, a drain connected to the filter node, and a source connected to an inverting node; an inverter that inverts the inverting node to drive the gate node of the shunting SOI transistor; and a p-channel pass transistor having a gate connected to the first terminal, a source connected to the filter node, and a drain connected to the gate node of the shunting SOI transistor; whereby the shunting SOI transistor shunts ESD pulses without assistance from a parasitic substrate diode.