Patent ID: 9378018
Filing Date: 2016-06-28
CPC Classification: G03F,G06F,H03M,Y02D,Y02P

Claim Text:
1. A system comprising a processor and an external memory, the processor including: a first data path having a first bit width; a second data path having a second bit width greater than the first bit width; a plurality of third data paths having a combined bit width less than the second bit width; a register file including registers having the first bit width, the register file being connected to the third data paths; a wide operand storage coupled to the first data path and to the second data path, the wide operand storage storing a wide operand having a size with a number of bits greater than the first bit width; a functional unit capable of performing operations in response to instructions, coupled by the second data path to the wide operand storage, and coupled by the third data paths to the register file; wherein address information for the wide operand includes both an address of the wide operand in the external memory and an indicia of the size of the wide operand; wherein the processor executes an instruction containing instruction fields specifying (i) a control register in the register file storing a control operand, and (ii) results register in the register file, the instruction causing the functional unit to perform an operation using the control register and the wide operand, and place the results in the results register; and wherein the external memory is coupled to the processor by the first data path, the wide operand being stored in the external memory before being provided to the wide operand storage.