Patent ID: 9471423
Filing Date: 2016-10-18
CPC Classification: G06F,G11C

Claim Text:
1. A system for selectively reporting memory errors, the system having a processor and a memory system, the memory system further comprising: a memory controller configured to access data from a location within a memory array of a memory device; an error correcting code (ECC) decoder configured to identify a correctable memory error at a first address within the memory device; an error counter configured to update, based on at least the identifying, a first correctable memory error count from a first quantity to a second quantity; a threshold module configured to determine whether the second quantity exceeds a threshold; a number converter configured to convert the first correctable memory error count from the second quantity to a third quantity when the second quantity exceeds the threshold, the third quantity being lower than the second quantity, wherein the memory device is further configured to report to the memory controller the first correctable memory error count of the third quantity when the second quantity exceeds the threshold, and wherein the memory device is further configured for selecting to not report to the memory controller the first correctable memory error count of the second quantity when the second quantity does not exceed the threshold; a command decoder configured to receive, prior to the identifying, a first error count enable command at the first address, wherein the first error count enable command requests information concerning whether there is the correctable memory error at the first address; and a command counter configured to update, in response to the receiving the first error count enable command, an error count enable command count from a fourth quantity to a fifth quantity.