Patent ID: 9478468
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a substrate including a first semiconductor material portion located in an nFET device region and a second semiconductor material portion located in a pFET device region; an nFET functional gate structure located on a surface of said first semiconductor material portion, wherein a source region is located on one side of said nFET functional gate structure and a drain region is located on another side of said nFET functional gate structure; a pFET functional gate structure located on a surface of said second semiconductor material portion, wherein a source region is located on one side of said pFET functional gate structure and a drain region is located on another side of said pFET functional gate structure; nFET contact structures contacting an exposed portion of said source region and said drain region of said nFET functional gate structure, wherein each of said nFET contact structures includes a Ti liner in direct physical contact with an exposed portion of a surface of one of said source region or said drain region of said nFET functional gate structure; and pFET contact structures contacting an exposed portion of said source region and said drain region of said pFET functional gate structure, wherein each of said pFET contact structures includes a Ni—Pt semiconductor alloy in direct physical contact with an exposed portion of a surface of one of said source region or said drain region of said pFET functional gate structure.