Patent ID: 9362160
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of said structure, said structure comprising: a first portion of a trench extending through said top semiconductor layer and through a base oxide layer below said top semiconductor layer; a handle wafer situated below said base oxide layer; a second portion of said trench extending from an interface between said base oxide layer and said handle wafer into said handle wafer and having sloped sidewalls, wherein a depth of said second portion of said trench from said interface to a bottom of said trench is greater than that of said first portion of said trench from a top surface of said top semiconductor layer to said interface, wherein said first portion of said trench has a substantially constant width that is greater than a width of said second portion at said bottom of said trench; wherein said sloped sidewalls are amorphized, thereby reducing carrier mobility in said handle wafer to improve electrical signal isolation between said adjacent devices situated in said top semiconductor layer.