Patent ID: 9405309
Filing Date: 2016-08-02
CPC Classification: G05F

Claim Text:
1. A method comprising: operating a low-dropout (LDO) regulator system in one of a voltage regulation mode or a power balancing mode, the method of operating the LDO regulator system comprising: delivering, by a transistor connected to a power source of a LDO linear regulator and a load of the LDO linear regulator, an amount of current needed to maintain an output of the LDO linear regulator at a constant output voltage level; generating, by a first amplifier stage, a first current proportional to a difference between a first reference voltage and a first feedback voltage, wherein the first reference voltage is across a reference resistor and the first feedback voltage is across a shunt resistor; generating, by a second amplifier stage, a second current proportional to a difference between a second reference voltage and a second feedback voltage; and in response to generating the first current and the second current, generating, by an output buffer stage connected to a combined output of the first amplifier stage and the second amplifier stage, based on an amount of current at the combined output, a control signal to control the transistor to maintain the load at the constant output voltage level.