Patent ID: 9337302
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising an integrated circuit, said integrated circuit comprising a first field-effect transistor and other electronic components, said first field-effect transistor having a drain and a source, a buried insulating layer, of UTBOX type, formed plumb with said first field-effect transistor, a ground plane made plumb with a gate and with a channel of said first field-effect transistor, said ground plane being disposed under said buried insulating layer and having a first type of doping, a first semiconducting element made under said buried insulating layer, said first semiconducting element having said first type of doping, a second semiconducting element made under said buried insulating layer and offset laterally with respect to said gate of said first field-effect transistor, said second semiconducting element being in contact with and separating said ground plane and said first semiconducting element, said second semiconducting element having a second type of doping opposite to said first type of doping, said first and second semiconducting elements being made plumb with one of said source and said drain of said first field-effect transistor, first and second bias electrodes in contact respectively with said ground plane and with said first semiconducting element, said first bias electrode having said first type of doping and being connected to a first bias voltage, said second bias electrode having said first type of doping and being connected to a second bias voltage different from said first voltage, a semiconducting well having said second type of doping and made plumb with said first ground plane and with said first and second semiconducting elements, a first isolation trench isolating said first field-effect transistor from said other electronic components of said integrated circuit, said first isolation trench extending through said buried insulating layer and into said semiconducting well, and second and third isolation trenches isolating said first field-effect transistor respectively from said first and second bias electrodes, and extending to a depth strictly less than the depth of said ground plane, wherein said ground plane and said first and second semiconducting elements are included in a field-effect transistor whose gate is formed by one of said drain and said source plumb with which said first and second semiconducting elements are formed.