Patent ID: 9318581
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A method of forming a transistor, the method comprising: providing a structure including one or more dummy gates on a top of an isolation layer and over one or more fins, a hard mask on top of the one or more dummy gates, and spacers on sides of the one or more dummy gates and the hard mask, wherein the isolation layer is on top of a substrate; forming pillars along sides of the one or more fins such that trenches separate the pillars from the sides of the one or more fins, the pillars including a first intermediate layer formed on the isolation layer and a second intermediate layer formed on the first intermediate layer; depositing an epitaxial layer in the trenches such that the epitaxial layer is laterally confined by the pillars, a top of the epitaxial layer forming a triangular shape that extends higher than the pillars; removing the pillars such that straight sidewalls of the epitaxial layer are exposed; replacing the one or more dummy gates and the hard mask with one or more replacement gates; forming a first filling material on top of the structure, such that contact openings in the first filling material are formed over a source part of the epitaxial layer on the one or more fins, a drain part of the epitaxial layer on the one or more fins, and the one or more replacement gates; and forming a metal silicide contact that wraps around the source part of the epitaxial layer and the drain part of the epitaxial layer, by forming a conductive layer on top of the structure.