Patent ID: 9230662
Filing Date: 2016-01-05
CPC Classification: G11C,H03K

Claim Text:
1. A register cell comprising: one output node; at least two power supply nodes; a first flash transistor and a second flash transistor, the first flash transistor connected between a first power supply node and the output node, the second flash transistor connected between a second power supply node and the output node; a first transistor separating the first flash transistor from the first power supply node; a second transistor separating the first flash transistor from the second power supply node; and a third transistor separating the second flash transistor from the second power supply node; wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors, the register cell is configured so that current flowing to and/or from the output node flows through at least one of the flash transistors, and the register cell is configured so that the flash transistors are programmed by controlling at least one of the first transistor, the second transistor, and the third transistor.