Patent ID: 9367456
Filing Date: 2016-06-14
CPC Classification: G06F,Y02D

Claim Text:
1. An integrated circuit comprising: a cache folded a predetermined number of times, wherein the cache comprises a plurality of arrays and a plurality of storage elements, wherein each of the plurality of arrays comprises respective ones of the plurality of storage elements, wherein the plurality of arrays are configured to store a cache line, wherein the cache line comprises a plurality of segments of data, wherein the plurality of segments of data are stored in two or more of the plurality of arrays, and wherein each of the plurality of segments of data is stored in a corresponding one of the plurality of storage elements; a first module configured to a second module configured to, based on the index, access one or more of the plurality of segments of data from the two or more of the plurality of arrays and output the one or more of the plurality of segments of data.