Patent ID: 9256505
Filing Date: 2016-02-09
CPC Classification: G06F,G11C

Claim Text:
1. A method of generating data transformations to improve ROM yield and programming time, said method comprising: configuring a bit flip register in association with a ROM and thereafter reading a binary string into said it flip register upon reset; selectively complementing data output from said ROM utilizing a content of said bit flip register and programming said content of said bit flip register into said ROM in order to reduce a programming time with respect to each ROM; tolerating a defective cell by selectively flipping a column with respect to a defective cell to improve a yield with respect to said ROM; and limiting said ROM access to a programmed part during a test run in order to tolerate a defect in an unused location utilizing a ROM built-in self test engine that generates addresses up to and including a content of an address limiting register.