Patent ID: 9412871
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A device, comprising: a buffer layer disposed over a substrate; a template layer disposed over the substrate; a channel backside passivation layer disposed over the buffer layer; a channel layer disposed over the channel backside passivation layer, wherein the channel backside passivation layer has an upper portion and a lower portion; a gate insulator layer disposed over and in contact with the channel layer and the channel backside passivation layer, the channel backside passivation layer separating the buffer layer from the gate insulator layer, and wherein the gate insulator layer is in contact with a sidewall of the upper portion; and shallow trench isolation structures (STIs) disposed on opposite sides of the channel backside passivation layer, the buffer layer, and the template layer, wherein the channel layer is disposed above a topmost surface of the STIs, the channel backside passivation layer having a topmost surface disposed above the topmost surface of the STIs and having a bottommost surface disposed below the topmost surface of the STIs, and wherein a bottommost surface of the STIs contacts the topmost surface of the substrate and the topmost surface of the STIs contacts a bottommost surface of the gate insulator layer.