Patent ID: 9361253
Filing Date: 2016-06-07
CPC Classification: G06F,G11C

Claim Text:
1. A signal control circuit, comprising: a first delay acquisition circuit configured to acquire a first delay amount for adjusting, based on a first timing for capturing, based on a reference signal, a first delayed input signal obtained by delaying an input signal by a first rise delay amount and a second delayed input signal obtained by delaying the first delayed input signal by a second rise delay amount, a timing of a rise of the input signal and a fall or a rise of the reference signal; a second delay acquisition circuit configured to acquire a second delay amount for adjusting, based on a second timing for capturing, based on the reference signal, a third delayed input signal obtained by delaying the input signal by a first fall delay amount and a fourth delayed input signal obtained by delaying the third delayed input signal by a second fall delay amount, a timing of a fall of the input signal and the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.