Patent ID: 9502314
Filing Date: 2016-11-22
CPC Classification: G11C,H01L

Claim Text:
1. A method for manufacturing a tested apparatus, the method comprising: forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer, the semiconductor wafer comprising a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns, each of the first and second semiconductor chips includes a first conductive structure and a second conductive structure that is (1) electrically isolated from the first conductive structure and (2) staggered such that a portion of the second conductive structure overlaps the first conductive structure, the portion of the second conductive structure of each of the first semiconductor chips being stacked over and electrically connected to the first conductive structure of a different one of the second semiconductor chips; contacting a probe card to at least one of the first semiconductor chips; while contacting the probe card, performing a first test operation on the at least one of the first semiconductor chips via the first conductive structure of the at least one of the first semiconductor chips; and while performing the first test operation, performing a second test operation independent of the first test operation on a corresponding one of the second semiconductor chips over which the at least one of the first semiconductor chips is stacked via the second conductive structure of the at least one of the first semiconductor chips.