Patent ID: 9230968
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A method of forming a memory array, comprising: providing a base comprising a first semiconductive material, the base having an memory array region and a peripheral region; forming a planar recessed upper surface of the array region, the upper surface of the array region being recessed relative to uppermost surfaces of the base in the peripheral region; forming a heavily-doped region within the first semiconductor material in the array region; epitaxially growing a second semiconductor material over the first semiconductor material; the second semiconductor material being in situ doped during the epitaxial growth to form a stack of doped regions over the heavily-doped region; forming first trenches through the second semiconductor material; the first trenches extending along a first direction, and penetrating entirely through the heavily-doped region; forming second trenches through the second semiconductor material, the second trenches extending along a second direction which intersects the first direction, and not penetrating entirely through the heavily-doped region; the first and second trenches together patterning the second semiconductor material into a plurality of vertically-extending pillars comprising the stacked doped regions, and patterning the heavily-doped region into a plurality of buried lines under the pillars; the buried lines electrically interconnecting pluralities of the pillars to one another; and forming data storage devices over the vertically-extending pillars and electrically coupled with top doped regions of the stacked doped regions.