Patent ID: 9350335
Filing Date: 2016-05-24
CPC Classification: H03K,H03M

Claim Text:
1. A combined multiplexer and latch circuit comprising: a first complementary signal input stage comprising a first input circuit and a second input circuit configured to receive respective components of a first complementary input signal, and to receive a first multiplexer select input signal that enables the first complementary signal input stage, the first complementary signal input stage having an output connected to an output of the combined multiplexer and latch circuit, the first complementary signal input stage having a single gate delay between an input of the first complementary signal input stage and the output of the combined multiplexer and latch circuit; a second complementary signal input stage comprising first and second input circuits configured to receive respective components of a second complementary input signal, and to receive a second multiplexer select input signal that enables the second complementary signal input stage, the second complementary signal input stage having an output connected to the output of the combined multiplexer and latch circuit, the second complementary input signal having a single gate delay between an input of the second complementary signal input stage and the output of the combined multiplexer and latch circuit; a clocked preset circuit that presets a signal at the output of the combined multiplexer and latch circuit with timing based on a first phase of an input clock; a storage circuit configured to store a value based on the output of the combined multiplexer and latch circuit with timing based on a second phase of the input clock; a preset mode during which the output of the combined multiplexer and latch circuit is preset by the clocked preset circuit, and having a latch mode during which a value output by the selected complementary signal input stage is output by the circuit and also stored in the storage circuit.