Patent ID: 9251863
Filing Date: 2016-02-02
CPC Classification: G11C,H01L

Claim Text:
1. A multi-channel semiconductor memory chip comprising: a first channel memory area configured to receive a first channel command signal through a shared bus during a first time period and receive a first data signals through a first data bus; and a second channel memory area configured to receive a second channel command signal through the shared bus after the first time period and receive a second data signals through a second data bus, wherein the first channel command signal is applied to the first channel memory area through the shared bus, and the second channel command signal is applied to the second channel memory area different from the first channel memory area in the multi-channel semiconductor memory chip through the shared bus, wherein the first a data bus is connected to a first control unit, the second data bus is connected to a second control unit, and the shared bus is commonly connected to the first control unit and the second control unit, wherein the first data bus provides the first channel memory area with a first column command and a first column address, the second data bus provides the second channel memory area with a second column command and a second column address, and the shared data bus provides both the first channel memory area and the second channel memory area with a first row command and first row addresses.