Patent ID: 9292641
Filing Date: 2016-03-22
CPC Classification: G06F

Claim Text:
1. In an electronic design automation (EDA) tool in a computer, a method for guiding circuit optimization, the method comprising: the EDA tool in the computer computing a set of aggregate slacks for a set of chains of logic paths in a circuit design, wherein each aggregate slack in the set of aggregate slacks corresponds to a chain of logic paths in the set of chains of logic paths, wherein each logic path in each chain of logic paths (1) begins at a primary input or an output of a sequential circuit element and (2) ends at a primary output or an input of a sequential circuit element, wherein each aggregate slack in the set of aggregate slacks is equal to a sum of slacks of individual logic paths in the corresponding chain of logic paths in the set of chains of logic paths; the EDA tool in the computer determining an optimization guidance based on the set of aggregate slacks, wherein the optimization guidance comprises one or more of: (1) a specification of one or more timing violations that are not to be resolved, (2) a specification of one or more timing violations that are to be resolved, (3) a specification of one or more aggregate slacks that are to be increased, (4) a specification of an order in which chains of logic paths are to be optimized, (5) a specification of an order in which logic paths are to be optimized, and (6) a specification of a termination condition for terminating a circuit optimization; and the EDA tool in the computer optimizing the circuit design based on the optimization guidance.