Patent ID: 9501418
Filing Date: 2016-11-22
CPC Classification: G06F

Claim Text:
1. A cache comprising: a journal configured for tracking data blocks stored in the cache; and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal, wherein the invalidation data area is on a separate region of the cache from the journal; wherein the journal is configured for tracking metadata for the data blocks, and wherein the metadata comprises a memory address corresponding to the data block, wherein the invalidation data area is configured for tracking metadata associated with the invalidated data blocks, and wherein the associated metadata comprises a memory address corresponding to the invalidated data block, wherein the memory address tracked in the invalidation data area is truncated compared to the memory address tracked in the journal, based on at least one of a storage size of an underlying storage device being cached and an offset determined based on a memory address of a block in the underlying storage device.