Patent ID: 9524788
Filing Date: 2016-12-20
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; a plurality of first wiring lines connected to the memory cells; a sense amplifier portion that detects data of one of the memory cells via one of the first wiring lines; and a connecting portion having a first region between the memory cell array and the sense amplifier portion, and including a plurality of transistors in the first region, one of the transistors having a first terminal electrically connected to a certain memory cell of the memory cells and a second terminal electrically connected to the sense amplifier portion, the connecting portion including: a first transistor group configured from transistors of the plurality of transistors that are aligned in a first direction, the first direction being as their channel width direction; and a second transistor group configured from transistors of the plurality of transistors that are aligned in a second direction intersecting the first direction, the second direction being as their channel width direction, and at least one of first terminals of the transistors of the second transistor group being disposed more inside of the first region than at least one of second terminals of the transistors of the second transistor group.