Patent ID: 9503105
Filing Date: 2016-11-22
CPC Classification: H03L

Claim Text:
1. A locking circuit to provide a clock output signal according to a reference clock signal, comprising: a controlled oscillator including an output to provide an oscillator output clock signal according to a control voltage signal; a feedback circuit including a first output to provide a feedback clock signal according to the oscillator output clock signal; a loop filter circuit comprising an impedance and a second output to provide the control voltage signal according to a current signal; a charge pump circuit including a third output to generate the current signal according to a control input signal; and a phase frequency detector (PFD) circuit operative in a first mode to generate the control input signal having a pulse width corresponding to a phase difference between a reference clock signal and the feedback clock signal, and operative in a second mode to generate the control input signal with a constant value; and a mode control circuit operative to place the PFD circuit in the first mode when the phase difference between the reference clock signal and the feedback clock signal is less than a predetermined value, and operative in response to the phase difference exceeding the predetermined value to place the PFD circuit in the second mode for a predetermined time.