Patent ID: 9502307
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure with improved negative bias temperature instability, the method comprising: forming an interfacial layer on a semiconductor substrate wherein the semiconductor substrate includes an nFET and a pFET; depositing a gate dielectric layer on the interfacial layer; depositing a pFET work function metal layer on the gate dielectric layer; diffusing fluorine atoms into the semiconductor structure by an anneal in a fluorine containing gas; removing the pFET work function metal layer from an area above the nFET wherein the area above the nFET includes at least the area over the nFET; depositing a layer of nFET work function metal on a remaining portion of the pFET work function metal and on an exposed portion of the gate dielectric layer; depositing a gate metal over the nFET work function metal layer; and performing an anneal in a reducing environment followed by a high temperature anneal.