Patent ID: 9373609
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A semiconductor package comprising: a first semiconductor chip having a first contact pad on a first major surface; a first bump disposed on the first contact pad; and a first solder layer disposed on sidewalls of the first bump, the first solder layer being disposed on all four sidewalls and a top surface of the first bump; a second bump disposed on a second contact pad of the first semiconductor chip, the second contact pad disposed on a second major surface opposite the first major surface; and a second solder layer disposed on sidewalls of the second bump; an encapsulant disposed around the first semiconductor chip; and a second semiconductor chip disposed in the encapsulant proximate the first semiconductor chip, wherein the second semiconductor chip comprises a third contact pad on the first major surface and a fourth contact pad on the second major surface.