Patent ID: 9245845
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: an electrode layer disposed in an active region above a semiconductor substrate; a first wiring layer disposed above the electrode layer; and a second wiring layer disposed above the first wiring layer, wherein the first wiring layer includes a plurality of first electrode wires electrically connected to element electrodes included in the electrode layer, the second wiring layer includes a plurality of second electrode wires arranged parallel to each other and electrically connected to at least one of the first electrode wires, the first wiring layer includes first regions and second regions, and in a plan view of the semiconductor substrate, the first electrode wires are each continuous in the first regions and each discontinuous in the second regions, the second electrode wires are arranged to regularly and alternately cover the first regions and the second regions, a corresponding one of the first regions and a corresponding one of the second regions being arranged in a longitudinal direction of each of the second electrode wires, and external connection terminals are not bonded over the second regions and are bonded over the second electrode wires over the first regions.