Patent ID: 9336391
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. A semiconductor device to securely initialize a state of an electronic circuit, the semiconductor device comprising: one or more architecture state registers; a memory; an intellectual property core that includes an execution logic; a first device connected to and configured to monitor the architecture state registers and the execution logic, wherein the first device is configured to verify whether a state machine, included in the execution logic, has not generated output by determining whether a trusted state of an architecture state latch is verified based, at least in part, on a result that indicates a state of the architecture state latch; and a second device connected to the memory and first device, wherein the second device controls whether the execution logic is integrated into the electronic circuit to process programming instructions; and a third device that is i) included in the intellectual property core, and ii) is configured to a) determine the state of the architecture state latch, wherein the architecture state latch is vulnerable to state manipulations, b) generate the result, and c) respond to a determination that the trusted state of the architecture state latch is not verified by sending a signal to the second device that indicates that the intellectual property core is not trusted.