Patent ID: 9344309
Filing Date: 2016-05-17
CPC Classification: H04B,H04L

Claim Text:
1. A decision circuit comprising: a first decision block, coupled to an input terminal, configured to distinguish a value of a first bit of a plurality of bits by using an amplitude of an analog signal from the input terminal as a discrimination point, the analog signal being an amplitude shift keyed signal in which a demodulation pattern of the plurality of bits is set for each one of a plurality of amplitudes; a superposition block, coupled to the input terminal, configured to acquire a signal of an absolute value of a difference of the analog signal from the input terminal in respect to an amplitude center value of the analog signal from the input terminal by superposing divided analog signals which is obtained by dividing the analog signal from the input terminal; an inversion block, coupled to an output of the superposition block and an output of the first decision block, configured to control inverting of the signal from the superposition block based on a first distinction result of the first decision block; a second decision block, coupled to an output of the inversion block, configured to distinguish a value of a second bit of the plurality of bits based on an amplitude of an output signal from the inversion block and the discrimination point; and an output buffer, coupled to an output of the second decision block and an output of the first decision block, configured to output the first distinction result and a second distinction result of the second decision block in synchronization with a clock.