Patent ID: 9435859
Filing Date: 2016-09-06
CPC Classification: G01R,H01L

Claim Text:
1. An integrated circuit interposer comprising: A. a substrate having a first side and an opposed second side; B. first functional input pads formed on the first side of the substrate; C. first functional output pads formed on the second side of the substrate and coupled to the first functional input pads; D. second functional input pads formed on the second side of the substrate; E. second functional output pads formed on the first side of the substrate and coupled to the second functional input pads; F. a test data input pad, a test clock input pad, a test mode select input pad, and a test data output pad formed on the first side of the substrate; G. a test access port controller, formed on the substrate, coupled to the test clock input pad and the test mode select input pad, and having a control output bus; and H. boundary register circuitry formed on the substrate, the boundary register circuitry including input boundary scan cells, each input boundary scan cell including a functional input coupled to a first functional input pad, a functional output coupled to a first functional output pad, a test data input coupled to the test data input pad, a test data output coupled to the test data output pad, and a control input coupled to the control output bus of the test access port controller, each input boundary scan cell including: