Patent ID: 9484944
Filing Date: 2016-11-01
CPC Classification: G01R,H03K,H03M

Claim Text:
1. A circuit comprising: a regulator comprising a pass transistor and a replica transistor, wherein the replica transistor generates a sense current; a first capacitor configured to receive the sense current in a first mode; a second capacitor configured to receive the sense current in a second mode, wherein when the first capacitor receives the sense current, the second capacitor does not receive the sense current, and when the second capacitor receives the sense current, the first capacitor does not receive the sense current; a comparator coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode and coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode; a reset circuit to discharge the first capacitor in the second mode and to discharge the second capacitor in the first mode in response to the count signal; and a counter incrementing a count of a number of occurrences of the count signal.