Patent ID: 9252754
Filing Date: 2016-02-02
CPC Classification: G01R,H03K

Claim Text:
1. A scan flip-flop which performs a normal operation latching a data input, which is externally input to the scan flip-flop via a first terminal, and a scan operation latching a scan input, which is externally input to the scan flip-flop via a second terminal, the scan flip-flop comprising: a first circuit determining an intermediate node voltage, which is a voltage at an intermediate node, based on a clock signal, one of the data input and the scan input, and data of a latch input node; a second circuit determining the data based on the clock signal, the intermediate node voltage and the data input during the normal operation and determining the data based on the clock signal and the intermediate node voltage during the scan operation; and a latch latching the data based on the clock signal and outputting the latched data via an output terminal, wherein the first circuit includes a first sourcing circuit including: