Patent ID: 9437597
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A static memory cell, comprising: a semiconductor substrate having a first region and a second region; a first fin structure extending from the semiconductor substrate in the first region; a second fin structure extending from the semiconductor substrate in the second region; an isolation layer on the semiconductor substrate exposed by the first fin structure and the second fin structure; a first gate structure disposed across a length of the first fin structure, wherein the first gate structure covers a height of the first fin structure above a top surface of the isolation layer and covers a depth of the first fin structure below the top surface of the isolation layer; and a second gate structure disposed across a length of the second fin structure, wherein the second gate structure covers a height of the first fin structure above a top surface of the isolation layer and does not cover a depth of the second fin structure below the top surface of the isolation layer.