Patent ID: 9437714
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A method comprising: obtaining a structure including a channel region comprising semiconductor material, spacers adjoining the channel region, a recess having an upper portion and a lower portion above the channel region and bounded by the spacers, a gate dielectric layer within the recess and adjoining the channel region, and a barrier layer on the gate dielectric layer, the barrier layer having an exposed inner surface comprising a work function material within the lower portion of the recess, the spacers having exposed inner surfaces adjoining the upper portion of the recess above the exposed inner surface of the barrier layer, the exposed inner surface of the barrier layer being selective to deposition of a gate metal with respect to the exposed inner surfaces of the spacers; selectively depositing the gate metal on the exposed inner surface of the barrier layer, thereby forming a gate metal layer only within the lower portion of the recess, and forming a dielectric cap over the gate metal and within the upper portion of the recess.