Patent ID: 9356093
Filing Date: 2016-05-31
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate; a first circuit which is formed on the substrate and in which a power supply potential is set to a first voltage; a second circuit in which a power supply potential is set to a second voltage lower than the first voltage and which is electrically isolated from the first circuit by an isolation region, the second circuit being formed on the substrate and positioned at an outer side of the isolation region when seen in a plan view; and a connection transistor which is formed on the substrate and is positioned between the first circuit and the second circuit, and which connects the second circuit to the first circuit, wherein the isolation region includes: an element isolation film, and a field plate electrode arrangement which overlaps the element isolation film and substantially surrounds the first circuit when seen in the plan view, wherein a source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in the plan view, wherein an insulating interlayer is formed over the element isolation film, and wherein the field plate electrode arrangement includes a first portion positioned over the connection transistor, and a second portion not positioned over the connection transistor, wherein the field plate electrode arrangement includes: a first electrode formed over the element isolation film, and a second electrode formed over the insulating interlayer, and wherein the first electrode and the second electrode are shifted from each other in the plan view.