Patent ID: 9472692
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A process of collective fabrication of electronic devices, comprising: forming a plurality of stacked assemblies respectively on adjacent locations, established in the form of a matrix, on a front face of a base wafer, each stack comprising an integrated circuit chip on top of the base wafer and a protection wafer on top of the integrated circuit chip, in such a manner that channels subsist between the stacked assemblies; forming an outer peripheral barrier on a peripheral area of the front face of the base wafer, around and at a distance from the plurality of stacked assemblies; depositing a first coating material within the channels and hardening this first coating material so as to form a first encapsulation ring, surrounding the stacked assemblies, having an annular beading protruding towards the front with respect to front faces of the protection wafers and situated in annular regions including the peripheral edges of the protection wafers, and forming, along the channels, recessed grooves with respect to the protruding annular beading, wherein the annular beading extends above the front faces of the protection wafers; placing a face of a mold in contact on the protruding annular beading; injecting a second coating material in the recessed grooves and hardening this second coating material so as to form a second encapsulation ring; and carrying out dicing operations along the locations in such a manner as to cut out the individual electronic devices formed in these locations.