Patent ID: 9367438
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A semiconductor integrated circuit comprising: a first processor which executes a first operation; a second processor which executes a second operation which is redundant with the first operation; a second buffer memory which stores a plurality of second data items output from the second processor during the second operation; a first FIFO memory which selects and stores only a predetermined number of the first data items sequentially output from the first buffer memory; a second FIFO memory which selects and stores only the predetermined number of the second data items sequentially output from the second buffer memory; a comparator which respectively compares the predetermined number of first data items output from the first FIFO memory with the predetermined number of second data items output from the second FIFO memory and outputs respective comparison results, wherein a total number of the first data items is equal to a total number of the second data items, and the predetermined number is less than the total number, a first built-in memory which stores instructions which cause the first processor to execute the first operation; and a second built-in memory which stores instructions which cause the second processor to execute the second operation, wherein the first data items output from the first processor are stored in the first built-in memory, and wherein the second data items output from the second processor are stored in the second built-in memory, wherein the first buffer memory counts a first number of the plurality of first data items which are sequentially supplied to the first buffer memory during the first operation, and wherein the second buffer memory counts a second number of the plurality of second data items which are sequentially supplied to the second buffer memory during the second operation, a control unit that is connected to the first buffer memory, the second buffer memory, the first FIFO memory, and the second FIFO memory, wherein the control unit includes a first register and a second register which can store information of the predetermined number of outputs, wherein, when the first number of the first data items counted by the first buffer memory matches information stored in the first register, the control unit supplies a first FIFO write enable signal to cause the first FIFO memory to select and store the predetermined number of first data items, and wherein, when the second number of the second data items counted by the second buffer memory matches information stored in the second register, the control unit supplies a second FIFO write enable signal to cause the second FIFO memory to select and store the predetermined number of second data items.