Patent ID: 9360918
Filing Date: 2016-06-07
CPC Classification: G06F,Y02D

Claim Text:
1. A multi-core data processor comprising: a plurality of data processor cores, each data processor core comprising a power state controller having a first input for receiving an idle signal from each of the plurality of data processor cores, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state, wherein in response to said idle signal, said power state controller causes a corresponding data processor core to enter an idle state, and in response to said release signal, said power state controller changes said current power state from said idle state to an active state in dependence on said control signal; a central power state controller coupled to each of said plurality of data processor cores for providing said control signal in response to current power states in said plurality of data processor cores, said central power state controller further including inputs coupled to said outputs of each of said plurality of data processor cores, and having an output coupled to each of said plurality of data processor cores for providing said control signal equal to a total number of idle cores; and wherein each of said plurality of data processor cores wakes up from said idle state in dependence on said control signal.