Patent ID: 9418719
Filing Date: 2016-08-16
CPC Classification: G06F,G11C

Claim Text:
1. A computing device comprising: a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0; and at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from said first section; and a decoder to activate a word line connected to a cell in said column in said second section to write said bit line voltage into said cell; and a controller to provide said decoder with an instruction set for decoding in said decoder wherein said instruction set represents compressed data associated with the operation of any one of said memory array, said at least one multiplexer, and said decoder.