Patent ID: 9324708
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A reverse conducting power semiconductor device having a wafer that includes layers of different conductivity types, which layers are arranged between an emitter electrode on an emitter side and a collector electrode on a collector side, which is arranged opposite of the emitter side, the device comprising: a drift layer of a first conductivity type, which is arranged between the emitter side and the collector side; a first layer having a first region of the first conductivity type and higher doping concentration than the drift layer and a second region of a second conductivity type, the second region is arranged adjacent to the first region, and the first layer is arranged between the drift layer and the collector electrode; a plurality of base layers of a second conductivity type, arranged between the drift layer and the emitter electrode, wherein the base layers are in direct electrical contact to the emitter electrode; a plurality of source regions of the first conductivity type, arranged at the emitter side embedded in one of the base layers and contact the emitter electrode, wherein the source regions have a higher doping concentration than the drift layer, and the emitter electrode includes a plurality of base layer contact areas, at which the emitter electrode contacts the base layers and the source regions; a plurality of gate electrodes, each of which are electrically insulated from the base layers, the source regions, and the drift layer by an insulating layer; an IGBT semiconductor cell formed within the wafer, which includes such layers or parts of such layers that lie in an orthogonal projection with respect to the emitter side of one of the base layer contact areas, to which one of the source regions is in contact, said source region and such a part of one of the base layers, at which an electrically conductive channel is formed, wherein a cluster is formed by a plurality of at least 10 IGBT cells, the IGBT cells being arranged directly adjacent to each other on the emitter side; and a well of the second conductivity type, arranged in a plane, that is parallel to the emitter side and in which plane the base layers are arranged, wherein the well has a surface area and wherein the well is arranged outside the IGBT cells and is electrically connected to the emitter electrode directly via a contact of the well to the emitter electrode at a well contact area being at most 10% of the maximum area of the well.