Patent ID: 9412848
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor device, the method comprising: providing an SOI substrate portion with a semiconductor layer, a buried insulating material layer and a bulk substrate, said buried insulating material layer being interposed between said semiconductor layer and said bulk substrate; patterning said SOI substrate portion and forming a patterned bi-layer stack from said buried insulating material layer and said semiconductor layer on said bulk substrate, said patterned bi-layer stack comprising a patterned buried insulating material layer and a patterned semiconductor layer; enclosing said patterned bi-layer stack with a further insulating material layer; and forming an electrode material on and around said further insulating material layer, wherein a gate electrode is formed by said bulk substrate and said electrode material such that said gate electrode substantially surrounds a channel portion formed by a portion of said patterned semiconductor layer.