Patent ID: 9455203
Filing Date: 2016-09-27
CPC Classification: H01L

Claim Text:
1. A method of making a semiconductor device comprising: providing a substrate having an NMOS region and a PMOS region; forming a high-k dielectric layer over the NMOS region and the PMOS region; incorporating a metal into the high-k dielectric layer over at least one of the NMOS region and the PMOS region wherein the metal is lanthanum when incorporated into the high-k dielectric over the NMOS region and the metal is aluminum when incorporated into the high-k dielectric over the PMOS region; depositing a nitride layer or a carbide layer over the NMOS and PMOS regions; depositing a silicon layer over the nitride layer or the carbide layer; patterning a gate structure of the nitride layer or the carbide layer and the silicon layer over the NMOS and PMOS regions; forming at least one spacer adjacent to the NMOS region gate structure and on the high-k dielectric layer over the NMOS region and forming at least one spacer adjacent to the PMOS region gate structure and on the high-k dielectric layer over the PMOS region so that the high-k dielectric layer extends underneath the at least one spacer adjacent to the NMOS region and extends underneath the at least one spacer adjacent to the PMOS region; applying an interlevel dielectric between the gate structure over the NMOS region and the gate structure over the PMOS region; removing the silicon layer from the gate structure over the NMOS region and the gate structure over the PMOS region to leave an opening in the gate structures; depositing a first work function setting metal in the opening over the NMOS region and depositing a second work function setting metal in the opening over the PMOS region to partially fill the openings; and depositing a gate electrode fill metal to fill the openings in the NMOS region and the PMOS region wherein the NMOS region gate electrode fill material having a bottom and sides such that the first work function setting metal being in direct contact with the bottom and sides of the NMOS region gate electrode fill material and wherein the PMOS region gate electrode fill material having a bottom and sides such that the second work function setting metal being in direct contact with the bottom and sides of the PMOS region gate electrode fill material.