Patent ID: 9312220
Filing Date: 2016-04-12
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit device, the method comprising: receiving a substrate; depositing a resist material layer over the substrate; forming a copolymer layer over the resist material layer, wherein the copolymer layer includes a first constituent polymer and a second constituent polymer; selectively removing the first constituent polymer from the copolymer layer; etching a first region of the resist material layer corresponding to the selectively removed first constituent polymer, wherein the etching leaves a second region of the resist material layer underlying the second constituent polymer unetched; depositing a dielectric material within the etched first region; etching a trench in the resist material layer and the dielectric material by removing at least a portion of each of the resist material layer and the dielectric material; forming an interconnect feature within the trench; and removing the resist material layer from the second region to form an air gap.