Patent ID: 9477599
Filing Date: 2016-10-25
CPC Classification: G06F,Y02D

Claim Text:
1. A method comprising: responsive to a store memory event: writing data to a level n cache, where n is an integer greater than zero representing the level of cache hierarchy; writing, to a level n pool, a store entry that includes an address location in main memory to which the data in the level n cache is to be written and a thread identity associated with the store entry, wherein the level n pool maintains a partial order among the store entry, a prior received store entry, and a release marker entry; when a release marker is present, ordering the store entry in the level n pool to be after a most-recent release marker; and when a level (n+1) cache is present: evicting the prior store entry from the level n pool to the level (n+1) pool, and evicting data, when present, from the level n cache associated with the evicted prior store entry, to the level (n+1) cache.