Patent ID: 9257359
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A chip stack comprising: a first semiconductor chip and a second semiconductor chip, the second semiconductor chip mounted above the first semiconductor chip, wherein the first and second semiconductor chips are substantially identical in outline and are each rectangular in plan view; a thermal interface material pad between the first and second semiconductor chips, the entire thermal interface material pad comprising four portions, wherein the first portion and the second portion are shaped as acute isosceles trapezoids and comprise nanofibers aligned substantially only perpendicularly to the parallel sides of the first portion and the second portion, the shorter parallel sides of the first portion and the second portion abutting each other; wherein the third portion and the fourth portion are shaped as isosceles right triangles and comprise nanofibers aligned substantially only perpendicularly to the hypotenuses of the third portion and the fourth portion; the right-angled vertices of the third portion and the fourth portion abutting respective ends of the shorter parallel sides of the first portion and the second portion; the longer parallel sides of the first portion and the second portion extending to cover respective long edges of the first and second semiconductor chips, and the hypotenuses of the third portion and the fourth portion extending to cover respective short edges of the first and second semiconductor chips.