Patent ID: 9419613
Filing Date: 2016-08-16
CPC Classification: H03K

Claim Text:
1. An input/output (IO) circuit comprising: a first bias circuit and a second bias circuit coupled to a node; a first capacitor and a second capacitor being cascaded, coupled to the node, the node being defined between the first capacitor and the second capacitor; and a pad coupled to the node; wherein the first bias circuit is configured to maintain a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit is configured to maintain the voltage at the node below the threshold during the receive mode, wherein the voltage at the node is dependent on a voltage at the pad during the receive mode; a reference voltage generator configured to receive a supply voltage and configured to generate a set of reference voltages that are supplied to the first bias circuit, the second bias circuit and the driver circuit, the set of reference voltages comprises one of a PMOS reference voltage, an NMOS reference voltage and a divided supply voltage, wherein the first bias circuit comprises: a first PMOS transistor coupled to a first NMOS transistor configured to be driven by the divided supply voltage and the NMOS reference voltage respectively; and a second PMOS transistor coupled to a second NMOS transistor configured to be driven by the PMOS reference voltage and the divided supply voltage respectively, wherein the first NMOS transistor and the second PMOS transistor are coupled to the node.