Patent ID: 9466601
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate including a first region and a second region; a first transistor in the first region and including a first channel region formed of an upper semiconductor layer and a lower semiconductor layer, such that the upper semiconductor layer is formed on the lower semiconductor layer and includes a first material, and the lower semiconductor layer includes a second material different from the first material, the first channel region being a fin structure contacting the substrate and protruding therefrom; a second transistor in the second region and including a second channel region formed of the upper semiconductor layer and not the lower semiconductor layer or the second material, the second channel region having a gate-all-around structure; a first gate electrode of the first transistor, the first gate electrode covering the fin structure; a first gate dielectric layer covering surfaces of the fin structure and formed between the fin structure and the first gate electrode; a second gate electrode of the second transistor, the second gate electrode formed around the second channel region, such that the second gate electrode covers the second channel region from above, below, and on both sides; and a second gate dielectric layer covering surfaces of the second channel region and formed between the second channel region and the second gate electrode, the second gate dielectric layer contacting at least a bottom surface of the second channel region.