Patent ID: 9336740
Filing Date: 2016-05-10
CPC Classification: G09G,G11C

Claim Text:
1. A shift register for use in a display driving circuit, the shift register comprising flip-flops at respective stages, the flip-flops each including: a gate side of the first CMOS circuit, a drain side of the second CMOS circuit, and the first output terminal being connected to each other, a drain side of the first CMOS circuit, a gate side of the second CMOS circuit, and the second output terminal being connected to each other, the shift register further comprising signal generation circuits each for generating an output signal for a corresponding stage with use of an output of a corresponding one of the flip-flops, the signal generation circuits each including an output transistor having a source terminal supplied with a clock signal and a drain terminal connected to an output terminal of the signal generation circuit, the shift register further comprising floating control circuits each provided between a gate terminal of the output transistor and a source-side terminal of the first or second CMOS circuit, each of the floating control circuits including (i) an input terminal connected to the first output terminal or the second output terminal and (ii) an output terminal connected to the gate terminal of the output transistor, each of the floating control circuits including an N channel type control transistor, and the control transistor having a gate terminal connected to a high-potential-side power supply having a constant potential, a source terminal connected to the first output terminal, and a drain terminal connected to the gate terminal of the output transistor.