Patent ID: 9390769
Filing Date: 2016-07-12
CPC Classification: G11C,H03K

Claim Text:
1. A multiplexed latch comprising: a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output; a first latch having a first latch clock input, and a first latch output; a second latch having a second latch clock input, and a second latch output; and a feedback loop connecting the multiplexor output to the first latch clock input and the second latch clock input, the first latch output being connected to the first data input of the multiplexor, the second latch output being connected to the second data input of the multiplexor, when the selection input of the multiplexor receives a first latch selection signal, the feedback loop forces the first latch output to remain unchanged until the first latch clock input transitions, and when the selection input of the multiplexor receives a second latch selection signal, the feedback loop forces the second latch output to remain unchanged until the second latch clock input transitions.