Patent ID: 9257379
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A coreless packaging substrate, comprising: a circuit buildup structure having at least a dielectric layer, at least a wiring layer formed on the at least a dielectric layer, and a plurality of conductive elements formed in the dielectric layer and electrically connected to the at least a wiring layer; a plurality of electrical pads embedded in a lowermost one of the at least a dielectric layer for electrically connecting part of the conductive elements, wherein the electrical pads are exposed from a surface of the lowermost one of the at least a dielectric layer; a plurality of copper bumps formed on an uppermost one of the at least a wiring layer, and each having a copper column portion and a copper wing portion integrally formed on the copper column portion, wherein the copper wing portion of each of the copper bumps is greater in diameter than the copper column portion; and a dielectric passivation layer formed on an uppermost one of the at least a dielectric layer, the uppermost one of the at least a wiring layer, and the copper bumps, with an entire top surface of the copper wing portion of each of the copper bumps exposed from the dielectric passivation layer, wherein the exposed top surface of the copper wing portion of each of the copper bumps directly contacts and is electrically connected with solder bumps of a semiconductor chip, the dielectric passivation layer is the same in width as the uppermost one of the at least a dielectric layer, and the copper bumps are free from protruding from the dielectric passivation layer.