Patent ID: 9343356
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A method of forming a metal back-end-of-the-line interconnect layer, comprising: selectively depositing a first self-assembled monolayer (SAM) contacting an underlying first inter-level dielectric (ILD) layer; selectively depositing a second self-assembled monolayer (SAM) on an underlying metal interconnect layer laterally surrounded by the first ILD layer; and removing a portion of the first SAM or the second SAM to form a metal interconnect layer area, wherein the first SAM or the second SAM is removed by using a photomask to selectively expose the first SAM or the second SAM to an ultraviolet radiation pattern that degrades a portion of the first SAM or a portion of the second SAM; selectively depositing a metal interconnect layer comprising a plurality of metal structures within the metal interconnect layer area; and depositing a second inter-level dielectric layer in areas between the plurality of metal structures.