Patent ID: 9478532
Filing Date: 2016-10-25
CPC Classification: H01L

Claim Text:
1. An electro static discharge (ESD) protection circuit comprising a signal transmission line coupled to an external input terminal, the ESD protection circuit comprising: a first power line coupled to a high voltage power supply; a second power line coupled to a low voltage power supply; a plurality of first oxide thin film transistors coupled in parallel between the first power line and the signal transmission line, the first oxide thin film transistors being diode-connected; and a plurality of second oxide thin film transistors coupled in parallel between the signal transmission line and the second power line, the second oxide thin film transistors being diode-connected, wherein a W/L of a channel of each of the first and second oxide thin film transistors is less than 1, wherein the first oxide thin film transistors and the second oxide thin film transistors each comprise a gate electrode, a first electrode, and a second electrode, wherein each of the first oxide thin film transistors is diode-connected such that the second electrode of each of the first oxide thin film transistors is coupled to the first power line, the first electrode of each of the first oxide thin film transistors is coupled to the signal transmission line at a common node, and the gate electrode of each of the first oxide thin film transistors is coupled to the first electrode of a corresponding one of the first oxide thin film transistors, and wherein each of the second oxide thin film transistors is diode-connected such that the second electrode of each of the second oxide thin film transistors is coupled to the signal transmission line at the common node, the first electrode of each of the second oxide thin film transistors is coupled to the second power line, and the gate electrode of each of the second oxide thin film transistors is coupled to the first electrode of a corresponding one of the second oxide thin film transistors.