Patent ID: 9245475
Filing Date: 2016-01-26
CPC Classification: G09G

Claim Text:
1. A demultiplexer circuit, adapted to transmit a data voltage provided by a source driver to a first to a Pth data lines of a display panel, the demultiplexer circuit comprising: a first to a Pth switch units, respectively electrically coupled to the first to the Pth data lines of the display panel and configured to collectively receive the data voltage, wherein the first to the Pth switch units are turned on in sequence to provide the data voltage to the corresponding data lines, and a period of the data voltage being provided to the first to the Pth data lines in sequence is defined as a data transmission period, wherein, each of the switch units comprises a first to a Nth transistors, the N transistors are connected with one another in series and configured to receive a plurality of control signals, wherein when the switch units are turned on, the N transistors are further configured to be turned on according to the control signals to transmit the data voltage to the corresponding data lines, and when the switch units are turned off, at least one of the N transistors is further configured to be turned off according to the corresponding control signal, wherein N is equal to P−1, and P is an integer greater than 2, and in the data transmission period, a time length of each of the control signals having a first voltage is greater than or equal to a time length of each of the control signals having a second voltage, and the first voltage is greater than the second voltage.