Patent ID: 9489896
Filing Date: 2016-11-08
CPC Classification: G09G,G11C

Claim Text:
1. A gate driving circuit comprising: a driving signal output circuit provided with a storage capacitor; a driving control circuit connected to the driving signal output circuit via a first node and a second node, and configured to sample an input signal in a first period of each scanning cycle, control the driving signal output circuit to output a first gate driving signal which is configured to turn on thin film transistors (TFTs) in a display panel in a second period of each scanning cycle, and control the driving signal output circuit to output a second gate driving signal which is configured to turn off the TFTs in the display panel by using the storage capacitor across which a voltage difference is within a predetermined range in a third period of each scanning cycle, wherein the first gate driving signal and the second gate driving signal are outputted by a gate driving signal output end; and the storage capacitor is connected between the first node and the gate driving signal output end; and a compensating circuit configured to maintain the voltage difference across the storage capacitor to be within the predetermined range in the third period of each scanning cycle, wherein the compensating circuit comprises: a first compensating transistor, a gate electrode of which is inputted with a control signal, and a first electrode of which is connected to the gate driving signal output end; and a second compensating transistor, a gate electrode of which is connected to the gate driving signal output end, a first electrode of which is connected to a second electrode of the first compensating transistor, and a second electrode of which is connected to the first node.