Patent ID: 9471733
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. A method comprising: providing a system graph of an electronic circuit comprising multiple instances of at least one primitive; identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph; dividing the tree into n subtree instances comprising at least first and second subtree instances, wherein n is predefined number of instances having an integer value 2 or greater; identifying links of the system graph as at least one of a global link or a local link, wherein the system graph comprises both global and local links, a global link forms a path from a branch of the first subtree instance to a branch of the second subtree instance, and a loop with the global link and branches of the first and second subtrees has a voltage drop of 0; and using at least one multicore computer processor, recursively partitioning the first subtree instance into i subtrees while a number of branches of each of the i subtrees is greater than a predefined partition size.