Patent ID: 9484074
Filing Date: 2016-11-01
CPC Classification: G11C

Claim Text:
1. An apparatus comprising: an array of memory cells; a read/write circuitry coupled to the memory cells and configured to amplify read data read from the array, the read/write circuitry including a current mode sense amplifier, comprising: cross-coupled transistors including first and second transistors; a load circuit coupled to the cross-coupled transistors and to a ground and configured to provide a resistance to control, at least in part, a loop gain of the current mode sense amplifier, the load circuit including a first resistor coupled to the first transistor and a second resistor coupled to the second transistor; a latch mode circuit coupled to the cross-coupled transistors and to the ground, the latch mode circuit configured to increase the loop gain of the current mode sense amplifier when activated; and wherein a state sensed by the current mode sense amplifier is latched based on the latch mode circuit being activated and the load circuit being deactivated.