Patent ID: 9337878
Filing Date: 2016-05-10
CPC Classification: H04B,H04W,Y02D

Claim Text:
1. A radio frequency (RF) receiver capable of operating in both a dual watch mode and a single watch mode, the RF receiver comprising: a low noise amplifier (LNA) that is configured to amplify a received RF signal; a first receiver path coupled to the LNA, wherein the first receiver path comprises a first mixer that is configured to downconvert an RF signal received from the LNA to a first intermediate frequency (IF) to produce a first IF signal; a second receiver path coupled to the LNA, wherein the second receiver path comprises a second mixer that is configured to downconvert an RF signal received from the LNA to a second IF to produce a second IF signal, wherein the second IF is different from the first IF, and wherein the first receiver path and second receiver path process a received RF signal in parallel; a processor coupled to each of the first receiver path and the second receiver path, wherein the processor is configured to, when operating in single watch mode: in response to determining to route amplified versions of a same RF signal to both the first receiver path and the second receiver path, route amplified versions of the same RF signal to both the first receiver path and the second receiver path and combine outputs of the first receiver path and the second receiver path; wherein the first receiver path is configured to downconvert an amplified version the RF signal to a first intermediate frequency (IF) to produce a first IF signal; wherein the second receiver path is configured to downconvert another amplified version the RF signal to a second IF to produce a second IF signal, wherein the first IF is different than the second IF; and wherein the processor is configured to translate the first IF signal to baseband to produce a first baseband signal, generate a first bit stream based on the first baseband signal, translate the second IF signal to baseband to produce a second baseband signal, generate a second bit stream based on the second baseband signal, and combine the first bit stream and the second bit stream; and wherein the processor is configured to, prior to combining the first bit stream and the second bit stream, add a delay to one or more of the first bit stream and the second bit stream.