Patent ID: 9418700
Filing Date: 2016-08-16
CPC Classification: G11B,G11C

Claim Text:
1. An apparatus, comprising: an Address Indirect Table (AIT) to store information to translate between system memory addresses and write-in place non-volatile random access memory (NVRAM) addresses, said AlT to access said non-volatile random access memory at a level of granularity that is finer than a storage block level of granularity; a free block list including a list of blocks available to be used as replacement blocks; a system memory controller to interface to a multi-level system memory, said system memory controller and said AIT being architecturally between a processor last level cache and said multi-level system memory, said write-in place NVRAM residing at a level of said multi-level system memory; an NVRAM controller comprising logic to detect a bad block within the write-in place NVRAM device, retire the bad block, select a replacement block from the free block list, wherein blocks of the free block list are not available for use by software, and replace the bad block with a replacement block by remapping an address of the bad block to the replacement block using the AIT.