Patent ID: 9525503
Filing Date: 2016-12-20
CPC Classification: H04B,H04J,H04L,H04W

Claim Text:
1. A method for reconfiguring a transceiver design using a plurality of frequency synthesizers and a plurality of carrier aggregation (CA) receiver (Rx) and transmitter (Tx) chains, the method comprising: connecting a first frequency synthesizer to a first CA Tx chain, wherein the first frequency synthesizer is configured to be used for the first CA Tx chain in one of a frequency division duplex (FDD) mode or time division duplex (TDD) mode; connecting the plurality of frequency synthesizers to the plurality of CA Rx chains, wherein a second frequency synthesizer of the plurality of frequency synthesizers is connected as a shared synthesizer to a first CA Rx chain and a second CA Tx chain, wherein the shared synthesizer is configured to be used for one of the second CA Tx chain or the first CA Rx chain when the shared synthesizer is to drive a TDD chain or is in the FDD mode, and wherein remaining frequency synthesizers are configured to be used for remaining Rx chains in one of the FDD mode or the TDD mode.