Patent ID: 9311880
Filing Date: 2016-04-12
CPC Classification: G09G,G11C

Claim Text:
1. A GOA circuit structure sharing GOA pull-down circuits to reduce TFT stress of the GOA pull-down circuits, comprising multiple twined GOA units cascaded with each other, assuming N is natural number, the N-level GOA unit charging the N-level horizontal scanning line in the displaying area, each said twined GOA unit comprising the (2N−1)-level GOA unit and the 2N-level GOA unit, the (2N−1)-level GOA unit comprising a first pull-down holding circuit and a second pull-down holding circuit respectively connected with the (2N−1)-level gate signal point and the (2N−1)-level horizontal scanning line, the 2N-level GOA unit comprising a third pull-down holding circuit and a fourth pull-down holding circuit respectively connected with the 2N-level gate signal point and the 2N-level horizontal scanning line; the (2N−1)-level gate signal point being further connected with the third pull-down holding circuit and the fourth pull-down holding circuit respectively, the 2N-level gate signal point being further connected with the first pull-down holding circuit and the second pull-down holding circuit respectively; the first pull-down holding circuit comprising: a first thin film transistor, the gate thereof inputting a second clock signal, the source and the drain thereof respectively inputting a first clock signal and being connected to a first circuit point, the first pull-down holding circuit working or not depending on the potential level of the first circuit point; the second pull-down holding circuit comprising: a second thin film transistor, the gate thereof inputting a fourth clock signal, the source and the drain thereof respectively inputting a third clock signal and being connected to a second circuit point, the second pull-down holding circuit working or not depending on the potential level of the second circuit point; the third pull-down holding circuit comprising: a third thin film transistor, the gate thereof inputting a third clock signal, the source and the drain thereof respectively inputting a second clock signal and being connected to a third circuit point, the third pull-down holding circuit working or not depending on the potential level of the third circuit point; the fourth pull-down holding circuit comprising: a fourth thin film transistor, the gate thereof inputting a first clock signal, the source and the drain thereof respectively inputting a fourth clock signal and being connected to a fourth circuit point, the fourth pull-down holding circuit working or not depending on the potential level of the fourth circuit point; the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal being provided to make the first pull-down holding circuit, the second pull-down holding circuit, the third pull-down holding circuit, and the fourth pull-down holding circuit work alternately.