Patent ID: 9432040
Filing Date: 2016-08-30
CPC Classification: H03M

Claim Text:
1. An analog-to-digital converter comprising: an upper bit conversion unit suitable for receiving an input signal, sampling upper bits from the input signal, and outputting a residual voltage remaining after the sampling the upper bits; a lower bit conversion unit suitable for receiving the residual voltage from the upper bit conversion unit, and sampling lower bits from the residual voltage; and an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits; wherein the upper bit conversion unit includes a capacitor array having a lowermost capacitor receiving the ramp signal from the lower bit conversion unit, wherein the lower bit conversion unit includes a ramp signal generator suitable for generating the ramp signal and applying the ramp signal to the lowermost capacitor, when sampling the lower bits.