Patent ID: 9239899
Filing Date: 2016-01-19
CPC Classification: G01R,G06F

Claim Text:
1. A method for transaction based verification of a design under test (DUT) by a test bench, the method comprising: configuring, by a transaction based verification computing device, the design under test with at least one configuration, the at least one configuration comprising one or more configuration values, the one or more configuration values changing during a transaction; applying, by the transaction based verification computing device, at least one input to the DUT to generate at least one output, the at least one output based on a configuration value; associating, by the transaction based verification computing device, a list of changed one or more configuration values with at least one abstract input transaction to generate at least one input transaction, the at least one abstract input transaction being generated by abstracting the at least one input; associating, by the transaction based verification computing device, a list of changed one or more configuration values with one or more abstract output transactions to generate at least one output transaction, the one or more abstract output transactions being generated by abstracting the at least one output; determining, by the transaction based verification computing device, one or more expected transactions based on the at least one input transaction using one or more transfer functions; generating, by the transaction based verification computing device, an outcome as pass/fail based on comparing the at least one output transaction with each of the one or more expected transactions, wherein the generating, by the transaction based verification computing device, identifies the outcome as the fail only when a match between the at least one output transaction and each of the one or more expected transactions cannot be identified for any of the one or more configuration values changed during the transaction.