Patent ID: 9397567
Filing Date: 2016-07-19
CPC Classification: H02M,Y02B

Claim Text:
1. An integrated circuit comprising: a load circuit; and an internal voltage regulator coupled to the load circuit at a supply voltage node, wherein the integrated circuit further includes an input configured to provide a voltage from an external voltage regulator to the supply voltage node, wherein the internal voltage regulator is configured to provide current to the load circuit responsive to determining that an output voltage provided by the external voltage regulator is below a predetermined threshold value, the internal voltage regulator including a pulse generation circuit configured to generate a number of pulses responsive to a determination that the output voltage provided by the external voltage regulator is below the predetermined threshold value, the pulse generation circuitry including a pre-driver circuit, a pull-up transistor and a pull-down transistor coupled to an output node, wherein the pulse generation circuitry is configured to, during generation of a pulse, activate the pull-up transistor N+1 times, activate the pull-down transistor N times, and tri-state the output node at an end of the pulse, wherein N is an integer value.