Patent ID: 9323678
Filing Date: 2016-04-26
CPC Classification: G06F

Claim Text:
1. A processor comprising: a plurality of cores including a first core to execute instructions, the first core including a pipeline having a reorder buffer (ROB) including a plurality of entries each associated with an instruction received in the pipeline, and a first logic to determine whether a load instruction is a critical instruction based at least in part on a miss indicator of an entry of the ROB associated with the load instruction to indicate that the load instruction missed in a core cache and a dependency counter field of the entry of the ROB that is greater than a threshold, and if so to send a memory request transaction associated with the load instruction to a system agent of the processor with a critical indicator to indicate the critical instruction; and the system agent coupled to the first core and including a distributed cache controller having a plurality of portions each associated with a corresponding portion of a distributed shared cache memory of the system agent, each of the distributed cache controller portions and the distributed shared cache memory portions associated with one of the plurality of cores, a memory controller to interface with a system memory coupled to the processor and an interconnect to couple the distributed shared cache memory and the distributed cache controller with the first core, wherein the system agent is to prioritize the memory request transaction based on the critical indicator at a plurality of points of the system agent.