Patent ID: 9479186
Filing Date: 2016-10-25
CPC Classification: H03M

Claim Text:
1. An analog to digital converter (ADC) comprising: a main ADC configured to generate a zone information signal and a digital output in response to an input signal; a reference ADC configured to receive a plurality of reference voltages from the main ADC, the plurality of reference voltages includes a first reference voltage and a second reference voltage, and the reference ADC configured to generate a reference output in response to the input signal, the first reference voltage and the second reference voltage; a subtractor configured to generate an error signal in response to the digital output and the reference output; and a logic block coupled to the main ADC, the reference ADC and the subtractor, the logic block configured to generate one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.