Patent ID: 9245755
Filing Date: 2016-01-26
CPC Classification: H01L

Claim Text:
1. A process of forming an integrated circuit, comprising the steps: providing a substrate wafer with a first doping type; implanting a first implant of a second doping type to form a deep well in the substrate wafer wherein the deep well forms a collector of a deep collector vertical bipolar transistor; implanting a second implant of the second doping type to form a first well in the substrate wafer wherein the first well contacts the deep well and electrically isolates a base region of the deep collector vertical bipolar transistor from the substrate; implanting the second implant to form a second well in the substrate wherein the second well forms a body of a MOS transistor; forming a MOS transistor gate dielectric; forming a MOS transistor gate on the MOS transistor gate dielectric; implanting a third implant of the second doping type to form source and drain diffusions self aligned to the MOS transistor gate; implanting the third implant to form an emitter of the deep collector vertical bipolar transistor; implanting a fourth implant of the first doping type to form a first base tuning diffusion within the base of the deep collector vertical bipolar transistor; and implanting the fourth implant to form a second base tuning diffusion under the gate of the MOS transistor gate and under the source and drain diffusions.