Patent ID: 9311212
Filing Date: 2016-04-12
CPC Classification: G06F

Claim Text:
1. A system comprising: a first application that, during a first clock cycle, writes a first plurality of tasks to a first memory buffer; a second memory buffer that, during a second clock cycle, receives a copy of the first plurality of tasks; a second application that, during the first clock cycle, writes a second plurality of tasks to a third memory buffer; a fourth memory buffer that, during the second clock cycle, receives a copy of the second plurality of tasks; a first comparison module that i) receives a first task from the first plurality of tasks and a second task from the second plurality of tasks and ii) selectively generates a first voting signal based on a first comparison between the first task and the second task; a second comparison module that i) receives the first task from the first plurality of tasks and the second task from the second plurality of tasks and ii) selectively generates a second voting signal based on a second comparison between the first task and the second task: and a first central processing unit (CPU) that selectively determines whether to de-assert a module health signal based on the first voting signal and the second voting signal.