Patent ID: 9367287
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A method of fused calculation of the sum of an addend and a product of two multiplication operands using a floating-point unit of a proccessor, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent, wherein the multiplication operands are in a lower precision format than the addend, with q>2p, where p is the mantissa size of the multiplication operands precision format and q is the mantissa size of the addend precision format, the method comprising the steps of: multiplying, using a p-bit multiplier, the mantissas of the multiplication operands; right-padding the 2p-bit product resulting from the multiplication with zeros to form a q-bit product mantissa; aligning, with a shifter, the mantissa of the addend and the mantissa of the product based on the exponent values of the addend and multiplication operands; and adding with an adder, the aligned mantissas of the product and the addend.