Patent ID: 9467252
Filing Date: 2016-10-11
CPC Classification: H03M,H04L

Claim Text:
1. A turbo decoder comprising: a plurality of turbo decoder engines configured to concurrently decode a received signal encoded within rows and columns of an interleaving matrix where interleaved values stayed in a same re-ordered row during interleaving; a plurality of extrinsic addressable memories operatively coupled to the turbo decoder engines and configured to store extrinsic values used by the turbo decoder engines for the decoding; an extrinsic reader operatively coupled between the extrinsic addressable memories and the turbo decoder engines and configured to read from the extrinsic addressable memories using extrinsic addresses for accessing the extrinsic addressable memories; and an extrinsic writer operatively coupled between the extrinsic addressable memories and the turbo decoder engines and configured to write to the extrinsic addressable memories using the extrinsic addresses for accessing the extrinsic addressable memories; and a deinterleaver operatively coupled to the extrinsic reader and configured to access the extrinsic addressable memories by arranging storage of the extrinsic values by the same rows of the same interleaving matrix, which same rows were previously used to encode the received signal, and each of the same rows corresponds to one turbo decoder engine of the plurality of turbo decoder engines.