Patent ID: 9336897
Filing Date: 2016-05-10
CPC Classification: G09G,G11C

Claim Text:
1. A shift register circuit comprising: an input terminal, an output terminal, and a clock terminal; a first transistor configured to supply said output terminal with a clock signal inputted to said clock terminal; second and third transistors each configured to charge said output terminal; and a driving circuit configured to drive said second transistor when a first control signal is active, said driving circuit driving said third transistor when a second control signal is active, wherein nodes connected to respective control electrodes of said first, second, and third transistors are defined as first, second, and third nodes, respectively, said shift register circuit further comprising a fourth transistor having a control electrode connected to said second node, configured to discharge said first node; and a fifth transistor having a control electrode connected to said third node, configured to discharge said first node, wherein at least one of said first and second control signals is activated for a predetermined time period before said clock signal first starts operating after power-on.