Patent ID: 9448065
Filing Date: 2016-09-20
CPC Classification: G01B,G08B,H01L

Claim Text:
1. A method for manufacturing a semiconductor device, comprising: determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip; determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip; moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes; after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes; after said stacking, determining an after-stacking position of the second semiconductor chip, using one or more third alignment marks formed on a surface of the second semiconductor chip opposite to a surface on which the one or more second alignment marks are formed; and calculating, by a control unit, a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon, based on the position of the first semiconductor chip before said stacking and the after-stacking position of the second semiconductor chip after the said stacking.