Patent ID: 9490015
Filing Date: 2016-11-08
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: a plurality of memory cells electrically coupled between a source select transistor and a drain select transistor; a peripheral circuit configured to perform a program operation on the plurality of memory cells; and a control logic unit configured to control at least one operation of the peripheral circuit so that at least two memory cells of the plurality of memory cells adjacent to the source select transistor and at least two memory cells of the plurality of memory cells adjacent to the drain select transistor are programmed to have a relatively fewer number of data bits than that of remaining memory cells of the plurality of memory cells in the program operation, wherein the at least two memory cells respectively adjacent to the source select transistor and the drain select transistor are programmed by using a combination of a single level cell (SLC) program method and a multi level cell (MLC) program method.