Patent ID: 9424034
Filing Date: 2016-08-23
CPC Classification: G06F,G11C

Claim Text:
1. A processor comprising: a plurality of N-bit registers; a decode unit to receive a multiple register memory access instruction, the multiple register memory access instruction to indicate a memory location and to indicate a register; and a memory access unit coupled with the decode unit and with the plurality of the N-bit registers, the memory access unit to perform a multiple register memory access operation in response to the multiple register memory access instruction, the multiple register memory access operation to involve a different set of N-bit data, in each of the plurality of the N-bit registers that are to comprise the indicated register, which is to be one of loaded from and stored to, different corresponding N-bit portions of an M×N-bit line of memory, that is to correspond to the indicated memory location, in which a total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation in total is to amount to at least half of the M×N-bits of the line of memory.