Patent ID: 9288087
Filing Date: 2016-03-15
CPC Classification: H04B,H04L

Claim Text:
1. A data receiver circuit comprising: an over-sampling circuit configured to over-sample an input signal in response to n clock signals each having n intervals in a clock cycle, generate n sampling signals, and output n pre-recovery signals in response to the n sampling signals and a decision feedback equalizer (DFE) adaptation control signal, n being a natural number equal to or greater than 2; a data recovery circuit configured to select one of the n pre-recovery signals, generate n data transition detection signals each indicating a corresponding interval and a number of transitions of the input signal that occur at the corresponding interval in response to the n clock signals and the n pre-recovery signals, and output a lowest data transition detection signal indicating an X a DFE adaptation control circuit configured to output the DFE adaptation control signal in response to the lowest data transition detection signal and the highest data transition detection signal, wherein the X wherein the Y