Patent ID: 9236499
Filing Date: 2016-01-12
CPC Classification: G06F,H01L

Claim Text:
1. A junction field-effect transistor comprising: a plurality of trench isolation regions surrounding a device region of a substrate; a semiconductor layer on the device region and the trench isolation regions, the semiconductor layer including a first region on the device region, a second region on the trench isolation regions, and a channel in the first region of the semiconductor layer, the first region of the semiconductor layer having a top surface, and the first region of the semiconductor layer having a greater thickness than the second region of the semiconductor layer; a first gate on the top surface of the first region of the semiconductor layer, the first gate separated from the device region by the first region of the semiconductor layer; a second gate in the device region, the second gate aligned with the first gate so that the channel is disposed between the first gate and the second gate; a source in contact with the top surface of the first region of the semiconductor layer; and a drain in contact with the top surface of the first region of the semiconductor layer, wherein the source and the drain are raised relative to the top surface of the semiconductor layer, the channel is aligned with the first gate and positioned laterally between the source and the drain, the first gate is comprised of a first semiconductor material, the source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from the first semiconductor material, and the source and the drain have an epitaxial relationship with the semiconductor layer.