Patent ID: 9235528
Filing Date: 2016-01-12
CPC Classification: G06F

Claim Text:
1. A memory device, comprising: one or more memory layers stacked on top of each other and configured to store data; and a logic layer coupled to the one or more memory layers, the logic layer comprising: an Input/Output (“I/O”) port configured to receive a write command that includes a write address and data; a memory map, configured to: maintain a memory table that associates a plurality of addresses with a plurality of memory locations in the one or more memory layers; and return an associated memory location corresponding to the write address; and a controller coupled to the I/O port and the memory map, the controller configured to: store a number of write requests to the associated memory location; remap a failed memory location to a new memory location if a remapping condition has occurred in the associated memory location; and store the data in the new memory location.