Patent ID: 9373569
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method of forming packaged semiconductor devices, comprising: providing a lead frame sheet including a plurality of joined flat no-lead lead frames each having a semiconductor die including bond pads thereon mounted on a die pad of said lead frames with bond wires between said bond pads and terminals of said lead frames, and plastic encapsulation except on a back side of said lead frame sheet to expose a back side of said die pad to provide an exposed thermal die pad and to expose a back side of said terminals; partial sawing in saw lanes beginning from said back side of the lead frame sheet through said terminals ending with saw lines having a line width terminating within said plastic encapsulation to provide exposed side walls of said terminals and exposed side walls of said plastic encapsulation; shorting together said exposed thermal die pad and said exposed back side of said terminals to form electrically interconnected metal surfaces; electroplating said interconnected metal surfaces with a solder wetable metal or metal alloy plating layer on said back sides of the lead frame sheet and the thermal die pad and on said exposed side walls of said terminals; decoupling said interconnected metal surfaces, and a second sawing in said saw lanes to finish sawing through said plastic encapsulation to provide singulation to form a plurality of said packaged semiconductor devices.