Patent ID: 9383393
Filing Date: 2016-07-05
CPC Classification: G01R,H03M

Claim Text:
1. A dual-comparator circuit, comprising: a first comparator (main comparator) including a main metal oxide semiconductor (MOS) differential pair (main MOS differential pair), and an enable input, and a main output providing a first decision output (outmain) when enabled; a second comparator (auxiliary comparator) including an auxiliary MOS differential pair, wherein said auxiliary comparator is configured to receive a differential input voltage (Vin) and generate a second decision output (outaux) at a control output and a control signal (useaux) at an auxiliary output that is coupled to said enable input of said main comparator; wherein said dual-comparator circuit is configured to provide a first operating mode [OM] when a magnitude of said Vin is less than (<) a predetermined voltage level (PVL) where said useaux activates said main comparator and said main MOS differential pair receives said Vin, and a second OM implemented when said magnitude of said Vin is greater than or equal to (≧) said PVL wherein said main MOS differential pair is protected by at least one switch from developing transient voltage input offsets (VIO), and logic circuitry having logic inputs receiving said outaux and said outmain and a logic output providing a decision result for said dual-comparator circuit from said outmain when in said first OM and from said outaux when in said second OM.