Patent ID: 9496872
Filing Date: 2016-11-15
CPC Classification: H01L,H03K

Claim Text:
1. A method for manufacturing a digital circuit comprising: forming a plurality of field effect transistor pairs; forming one or more pairs of competing paths such that, for each field effect transistor pair, the two field effect transistors are in different competing paths of a pair of competing paths; forming a first sub-circuit of the digital circuit implementing a first Boolean function and a second sub-circuit of the digital circuit implementing a second Boolean function wherein, for each pair of competing paths, one competing path is in the first sub-circuit and one competing path is in the second sub-circuit; connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal; and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.