Patent ID: 9484948
Filing Date: 2016-11-01
CPC Classification: H03K,H03L,H03M

Claim Text:
1. A clock generation circuit comprising: a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal which have been received, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal; a filter circuit configured to suppress a high frequency component, of which frequency is higher than a predetermined cutoff frequency, in the phase difference signal; an output circuit configured to modulate the phase difference signal, of which high frequency component is suppressed, in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal; and a frequency dividing circuit configured to divide a frequency of the output clock signal, which has been output, at a predetermined frequency dividing ratio, and feed the output clock signal back to the phase comparison circuit as the feedback signal.