Patent ID: 9431264
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit comprising: providing a patternable structure comprising a first hard mask layer and a first patternable layer underlying the first hard mask layer; providing mandrels over the first hard mask layer; forming sidewall spacers adjacent sidewalls of the mandrels; removing the mandrels, with the sidewall spacers remaining and defining gaps therebetween; etching the first hard mask layer through the gaps between the sidewall spacers to form a first patterned hard mask feature and a second patterned hard mask feature; selectively modifying a critical dimension thickness of the first patterned hard mask feature relative to the second patterned hard mask feature to form a biased hard mask feature, wherein a space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature; and etching the first patternable layer through exposed material in the space defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature.