Patent ID: 9229289
Filing Date: 2016-01-05
CPC Classification: G02F,H01L,H05K

Claim Text:
1. An array substrate for a display device, comprising: a plurality of paired gate lines spaced at a first distance from each other, each pair of gate lines being located at a corresponding boundary between adjacent first regions on a substrate, the substrate comprising a display area comprising a plurality of first regions, each of the first regions comprising two pixel regions adjacent to each other; a gate insulating layer on the gate lines and comprising a gate contact hole configured to expose each of the gate lines; a plurality of data lines crossing the paired gate lines, such that the first regions are located at each crossing; an auxiliary gate line parallel with the data lines and at a boundary between the adjacent two pixel regions; a thin film transistor in each of the pixel regions and connected to corresponding gate and data lines; and a common line parallel with the data lines and entirely within another boundary between two adjacent pixel regions of another first region, wherein the auxiliary gate line contacts the corresponding gate line through the gate contact hole, and wherein a number of the auxiliary gate lines is n times a number of the gate lines, where n is an integer greater than or equal to 2.