Patent ID: 9502349
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A memory device on a substrate, comprising: a multilevel stack of conductive layers, each of the layers being divided into a plurality of adjacent word lines; a plurality of pillars oriented orthogonally to the conductive layers, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the word lines; a plurality of adjacent string select lines disposed above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective string select gate of the pillar; a plurality of parallel bit line conductors disposed above the string select lines, each of the bit line conductors superposing a respective distinct subset of the pillars, each of the pillars underlying one of the bit line conductors; and a plurality of adjacent ground select lines disposed below the conductive layers, each of the ground select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a ground select line defining a respective ground select gate of the pillar, wherein the minimum pitch P