Patent ID: 9232654
Filing Date: 2016-01-05
CPC Classification: H01L,H05K,Y10T

Claim Text:
1. A high performance electrical interconnect adapted to provide an interface between terminals on first and second circuit members, the electrical interconnect comprising: a first circuitry layer comprising a first surface and a second surface with a plurality of contact pads adapted to electrically coupled with the terminals on the first circuit member; at least one dielectric layer printed on the first surface of the first circuitry layer, the dielectric layer comprising a plurality recesses, the dielectric layer comprising a compliant material located behind contact pads, the compliance of the compliant material biasing the contact pads toward the terminals on at least one of the first or second circuit members; a conductive material deposited in at least a portion of the recesses comprising circuit geometry electrically coupled with the first circuitry layer; and a second circuitry layer comprising a first surface a plurality of contact pads adapted to electrically coupled with the terminals on the second circuit member and a second surface attached to the dielectric layers, the circuit geometry electrically coupling the first circuitry layer to the second circuitry layer.