Patent ID: 9318560
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A group III-V semiconductor device comprising: at least one buffer layer situated over a substrate; at least one transition layer situated over said at least one buffer layer, said at least one transition layer and said at least one buffer layer comprising different semiconductor materials; a first strain-relieving interlayer situated over said at least one transition layer and a second strain-relieving interlayer situated over said first strain-relieving interlayer; a first group III-V semiconductor body situated over said second strain-relieving interlayer; said first and second strain-relieving interlayers comprising different semiconductor materials so as to reduce a strain in said first group semiconductor body; said first and second strain-relieving interlayers each having a thickness greater than or substantially equal to 0.01 micrometers, said second strain-relieving interlayer being thicker than said first strain-relieving interlayer.