Patent ID: 9325298
Filing Date: 2016-04-26
CPC Classification: H03K

Claim Text:
1. A receiving circuit comprising: a pair of first input transistors of a first conductivity type respectively including control terminals to which differential input signals are applied; a pair of load transistors of a second conductivity type different from that of the pair of first input transistors, the pair of load transistors respectively being connected between a first wiring to which a first voltage is supplied and first terminals of the pair of first input transistors; a pair of second input transistors of the second conductivity type respectively including control terminals to which the differential input signals are applied; a latch circuit connected between a second wiring to which a second voltage is supplied and first terminals of the pair of second input transistors; and a pair of conversion transistors of the second conductivity type respectively being connected in parallel to the pair of second input transistors, the pair of conversion transistors respectively including control terminals that are respectively connected to a pair of output nodes to which the pair of first input transistors and the pair of load transistors are connected.