Patent ID: 9436562
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. An apparatus, comprising: a first data bus and a second data bus; a first circuit coupled for communication via the first data bus; a second circuit coupled for communication via the second data bus; a plurality of storage elements coupled to the first data bus and the second data bus; an error detection system coupled to the first data bus and the second data bus; the error detection system configured to compare first data on the first data bus with corresponding second data on the second data bus; the error detection system configured to generate an error signal responsive to mismatch between the first data and the second data; first routing nodes of the first data bus to provide the first data to both the plurality of storage elements and the error detection system; second routing nodes of the second data bus to provide the second data to both the error detection system and the second circuit; the first routing nodes coupled nearer to the first circuit for a first routing pipeline coverage end of the error detection system as associated with the first data on the first data bus; and the second routing nodes coupled nearer to the second circuit for a second routing pipeline coverage end of the error detection system as associated with the second data on the second data bus.