Patent ID: 9471140
Filing Date: 2016-10-18
CPC Classification: G06F,Y02D

Claim Text:
1. A system, comprising: a volatile memory for storing and accessing information, wherein the volatile memory consumes power in a first voltage domain when storing and accessing the information; a processor for writing the information to and reading the information from the volatile memory, wherein the processor consumes power in a second voltage domain when writing the information to and reading the information from the volatile memory, and wherein the processor is arranged to store a context of the processor as context information in the volatile memory in response to an indication of a transition to a first suspend mode type; a status register for storing a valid context indication for determining whether a valid processor context of the processor has been stored in the volatile memory, wherein the status register consumes power in a third voltage domain when storing the valid context indication for determining whether a valid processor context of the processor has been stored in the volatile memory; a power manager for selectively coupling power to the first, second, and third voltage domains in response to an indication of a transition to an active mode, for decoupling power to the first, second, and third voltage domains in response to an indication of a transition to an off mode, and for coupling power to the first and third voltage domains and decoupling power to the second voltage domain in response to an indication of a transition to the first suspend mode type, and; a program loader for restoring the processor context from the volatile memory in response to determining, by reading the stored valid context indication, whether a valid processor context of the processor has been stored.