Patent ID: 9423969
Filing Date: 2016-08-23
CPC Classification: G06F,G11C

Claim Text:
1. A memory device comprising: a memory array comprising a plurality of memory cells; a counting circuit configured to generate a count output and a translated count output; a voltage generation circuit coupled to the counting circuit and configured to generate a time varying voltage in response to the count output, the time varying voltage being selectively coupleable to control gates of at least some of the memory cells; and a plurality of data caches coupled to the memory cells such that each data cache is associated with a different group of memory cells and configured to store a count, wherein each data cache is configured to detect when a memory cell of its associated group turns on in response to a particular voltage of the time varying voltage and compare the count with a translated count output associated with the count output responsible for the particular voltage, to determine a state of the memory cell.