Patent ID: 9312900
Filing Date: 2016-04-12
CPC Classification: H04B,H04J,H04L

Claim Text:
1. An electrical transceiver for synchronous Ethernet comprising: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay, a decoding unit decoding a line coding signal received from the host and an encoding unit encoding the signal received from the serial link to the line coding signal, wherein a delay difference between the transmission signal and the reception signal is calculated by Equation 1 below, where, fixed RX serdes represents a delay time of the encoding unit, fixed TX PHY represents a delay time of a transmission unit in the physical layer (PHY) transceiver, fixed TX serdes represents a delay time of the decoding unit, fixed EQ delay represents a delay time in the timing control unit, and fixed RX PHY represents a delay time of a reception unit in the physical layer (PHY) transceiver, and [n] is a value at which the delays of the transmission signal and the reception signal are the same.