Patent ID: 9460814
Filing Date: 2016-10-04
CPC Classification: G11C

Claim Text:
1. A method of determining a multi-bit upset (MBU) during soft error rate (SER) testing of a memory device under test, the method comprising: receiving an error indication based on a comparison between a generated test data pattern written to an address location on the memory device and a stored version of the generated test data pattern read from the address location on the memory device, the error indication associated with error information corresponding to the comparison between the generated test data pattern and the stored version of the generated test data pattern; determining by a processor, based on the received error indication, a count value associated with one of a predetermined number of passes that a plurality of generated test data patterns traverse between a first and a second memory address location on the memory device, wherein the determined count value identifies a timestamp; determining the MBU based on the address location, the error information, and the determined count value, wherein the determining the MBU includes identifying that a threshold number of errors have occurred in sequence or at the same time based on the determined count value; and generating at least one timing control signal that includes a plurality of pulses each having a predetermined pulse width, wherein the at least one timing control signal determines the writing of the generated test data pattern to the address location on the memory device and the reading of the stored version of the generated test data pattern from the address location on the memory device, wherein the generating of the at least one timing control signal comprises: