Patent ID: 9274797
Filing Date: 2016-03-01
CPC Classification: G06F

Claim Text:
1. A system for testing whether a computer processor is capable of executing a requested instruction set, the system comprising: a computer processor configured to: receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor; and implement the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor; wherein implementing the encoded conditional branch instruction includes updating a program counter of the computer processor with an unconditional branch address if the computer processor is capable of executing the requested instruction set; wherein the computer processor further includes an instruction set array that each bit value contained indicates whether an instruction set is executable by the computer processor; wherein the encoded conditional branch instruction is in a bit array format comprising: wherein the program counter is updated by adding the offset address when the corresponding bit value of the instruction set array is 1.