Patent ID: 9432179
Filing Date: 2016-08-30
CPC Classification: G11C,H03L,H04L

Claim Text:
1. A signaling system comprising: a DRAM integrated circuit (IC) chip to receive a data signal and a strobe signal and having circuitry to sample the data signal at times indicated by the strobe signal to generate sampled data and phase error information, the phase error information indicating phase difference between the data signal and the strobe signal, and circuitry to output the phase error information from the DRAM IC chip; a signaling link; and a memory controller IC chip coupled to the DRAM IC chip via the signaling link to output the data signal and the strobe signal to the DRAM IC chip, the memory controller IC chip having delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the DRAM IC chip and adjust the first time interval in accordance with the phase error information.