Patent ID: 9484202
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A method for depositing and patterning a spacer layer during a multiple patterning process, comprising: conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has a first group of openings defined therebetween; selectively treating a first portion of the spacer layer formed on the substrate without treating a second portion of the spacer layer, wherein the selectively treating the first portion of the spacer layer further comprises supplying a post-deposition treatment gas mixture including an inert gas to the substrate, and applying an RF bias power of between 250 Watts and about 1500 Watts without a RF source power to the post-deposition treatment gas mixture; and selectively removing the treated first portion of the spacer layer.