Patent ID: 9263276
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A method for fabricating a transistor, the method comprising: providing a silicon layer above a substrate, the silicon layer being separated from the substrate by one or more layers; forming a first layer on and in contact with the silicon layer, the first layer comprising a high dielectric constant material; forming a second layer and in contact with the first layer, the second layer comprising a metal or metal alloy; forming a third layer on the second layer, the third layer comprising silicon or polysilicon; etching the first, second, and third layers so as to form first, second, and third layers of a gate stack; depositing an encapsulation layer, the encapsulation layer including a horizontal portion in contact with the silicon layer and a vertical portion that is located on and in contact with sidewalls of the gate stack; after depositing the encapsulation layer, depositing one spacer layer above and in contact with the horizontal portion of the encapsulation layer and adjacent to and in contact with the vertical portion of the encapsulation layer, wherein depositing the one spacer layer comprises after depositing the spacer layer, etching the encapsulation layer and the one spacer layer so as to form a spacer and an L-shaped gate encapsulation layer that is disposed on the sidewalls of the gate stack, the L-shaped gate encapsulation layer comprising a vertical portion covering and in contact with the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering and in contact with a portion of the silicon layer that is adjacent to the gate stack, and the spacer being above and in contact with the horizontal portion of the L-shaped gate encapsulation layer and adjacent to and in contact with the vertical portion of the L-shaped gate encapsulation layer, the spacer extending from the vertical portion of the L-shaped gate encapsulation layer to the horizontal portion of the L-shaped gate encapsulation layer, the spacer comprising a vertical sidewall extending from a surface of the horizontal portion of the L-shaped gate encapsulation layer to a height above at least the second layer comprising the metal or metal alloy, wherein etching the encapsulation layer and the at least one spacer layer further comprises after etching the encapsulation layer and the one spacer layer, performing an extension implantation to implant ions so as to form source/drain extensions in the silicon layer, the source/drain extensions not underlying the gate stack; and after performing the extension implantation, performing a source/drain implantation and performing an anneal to implant and diffuse ions for source and drain regions in the silicon layer, wherein the extension implantation and the source/drain implantation are two separate implantations, and both the extension implantation and the source/drain implantation are performed after etching the encapsulation layer and the one spacer layer and while the spacer is present above the horizontal portion of the L-shaped gate encapsulation layer and adjacent to the vertical portion of the L-shaped gate encapsulation layer.