Patent ID: 9438025
Filing Date: 2016-09-06
CPC Classification: G01R,H02H

Claim Text:
1. A chip level integrated recovery apparatus comprising: a first circuit within a partition of an integrated circuit; a second circuit within the partition of the integrated circuit; and a partition state machine coupled to the first circuit and the second circuit and configured to monitor current leakage (IDDQ) of the first circuit while the first circuit is powered on and to power on the second circuit and power off the first circuit when the monitored first circuit current leakage exceeds a first current leakage threshold; the partition state machine comprising; a first transimpedance amplifier coupled to the first circuit to translate the first circuit current leakage when the first circuit is powered on to generate a first voltage; a second transimpedance amplifier coupled to the second circuit to translate current leakage of the second circuit when the second circuit is powered on to generate a second voltage; and a comparator coupled to the first and second transimpedance amplifiers, the comparator configured to compare the first voltage to a first reference voltage based on the first current leakage threshold when the first circuit is powered on and to compare the second voltage to a second reference voltage based on a second current leakage threshold when the second circuit is powered on.