Patent ID: 9373582
Filing Date: 2016-06-21
CPC Classification: H01L

Claim Text:
1. A method for forming a via in an integrated circuit, the method comprising: patterning a first opening in a first hardmask, the first hardmask including a titanium nitride (TiN) layer disposed on a first organic self-planarizing polymer (OPL) layer; removing an exposed portion of the first OPL layer to define a first cavity; removing an exposed portion of a second hardmask in the first cavity; removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the first cavity; depositing a second OPL layer over the first hardmask and in the first cavity; patterning an opening in the second OPL layer and second opening in a first hardmask; removing the second OPL layer to expose the first hardmask; removing an exposed portion of the first OPL layer defined by the second opening in the first hardmask to define a second cavity; removing an exposed portion of the second hardmask in the second cavity and removing a exposed portion of a first cap layer in the first cavity; removing an exposed portion of the first dielectric layer in the second cavity and an exposed portion of a second dielectric layer in the first cavity; removing an exposed portion of the first cap layer in the second cavity and an exposed portion of a second cap layer in the first cavity; removing an exposed portion of a liner layer over a first conductive material in the second cavity and an exposed portion of a liner layer over a second conductive material in the first cavity; and depositing a conductive material in the first cavity and the second cavity.