Patent ID: 9437313
Filing Date: 2016-09-06
CPC Classification: G11C

Claim Text:
1. A method of reading a non-volatile memory device comprising memory cells organized in blocks, each block comprising a plurality of pages, the memory cells being included in a cell string connected in series between at least one string selection transistor connected to a string select line and a ground selection transistor connected to a ground select line, and the cell string being connected to a page buffer via a bit line connection transistor that operates in response to a bit line connection signal, the method comprising: receiving a read instruction designating a selected page of a selected block of memory cells; applying, in response to the bit line connection signal, a precharge voltage to a bit line connected to the selected page, wherein the precharge voltage varies with the voltage level of the bit line connection signal; applying a read voltage to a word line connected to the selected page and applying a pass voltage to word lines connected to remaining non-selected pages; and reading the selected page, wherein a voltage level of the bit line connection signal is adjusted according to a distance between the word line of the selected page and a string select line connected to at least one string select transistor designating the selected block, such that the voltage level of the bit line connection signal is set high when the selected page is adjacent to the string selection line and is set low when the selected page is adjacent to the ground selection line.