Patent ID: 9411758
Filing Date: 2016-08-09
CPC Classification: G06F,Y02D

Claim Text:
1. A semiconductor device including a plurality of interface units that are connected via a bus and assigned with either one of a bus master that issues a transaction and stops issuing the transaction in response to a bus master stop request and a bus slave that receives the transaction, the semiconductor device comprising: a first module that includes a first interface unit functioning as the bus master and configured to issue a first transaction; a second module that includes a second interface unit functioning as the bus slave and a third interface unit functioning as the bus master, and configured to issue a second transaction in response to the first transaction; a third module that includes a fourth interface unit functioning as the bus slave and configured to receive the second transaction; a bus master stop request control unit that is configured to assert the bus master stop request and, in response to assertion of a bus master stop acknowledgement corresponding to the bus master stop request, to complete an assertion process of the bus master stop request; and a code addition unit that is configured to add a compulsory process request code to the first transaction, wherein the second module is configured to issue the second transaction while asserting the bus master stop acknowledgement when the second module receives the first transaction added with the compulsory process request code in a period when the bus master stop request is asserted, and the first module is configured to assert the bus master stop acknowledgement corresponding to the bus master stop request in response to reception of a response to the first transaction.