Patent ID: 9437722
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A vertical power component, comprising: a silicon substrate doped with a first conductivity type and having an upper surface and a lower surface opposite said upper surface; a first well in the lower surface of said silicon substrate doped with a second conductivity type; a second well in the upper surface of said silicon substrate doped with the second conductivity type; a first insulating porous silicon ring surrounding said first well and having a lower surface aligned with the lower surface of the silicon substrate, a depth which exceeds a thickness of the first well and an upper surface in contact with the first conductivity type silicon substrate, said first insulating porous silicon ring in contact with a junction between the first well and the silicon substrate; and a second insulating porous silicon ring surrounding said second well and having an upper surface aligned with the upper surface of the silicon substrate, a depth which exceeds a thickness of the second well and a lower surface in contact with the first conductivity type silicon substrate, said second insulating porous silicon ring in contact with a junction between the second well and the silicon substrate; and wherein the first and second porous silicon rings are not in contact with each other.