Patent ID: 9286978
Filing Date: 2016-03-15
CPC Classification: G11C

Claim Text:
1. A nonvolatile semiconductor memory device, comprising: a memory cell disposed between a first line and a second line and including a variable resistance element; and a control circuit configured to cause data of 2 bits or more to be stored in the memory cell by setting the memory cell to be included in one of resistance value distributions, and to apply a voltage to the memory cell in a write operation, the control circuit being configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value as an upper limit value of the second resistance value distribution and a second lower limit value as a lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value as an upper limit value of the first resistance value distribution and a first lower limit value as a lower limit value of the first resistance value distribution.