Patent ID: 9461149
Filing Date: 2016-10-04
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor structure comprising: forming a material stack on a substrate, the material stack comprising, from bottom to top, at least a first nanowire material layer, a second nanowire material layer and a top nanowire material layer that are separated from each other by a respective sacrificial material layer; forming a hard mask layer on the top nanowire material layer of the material stack; patterning the hard mask layer and the top nanowire material layer to provide a vertical stack of a hard mask layer portion and a top nanowire material layer portion, each of the hard mask layer portion and the top nanowire material layer portion including a fin portion connected at each end to a respective supporting portion; forming a sacrificial spacer on each sidewall of the vertical stack; removing exposed portions of a sacrificial material layer located beneath the top nanowire material layer portion that are not covered by the sacrificial spacer or the vertical stack to expose portions of the second nanowire material layer; removing portions of the second nanowire material layer that are not covered by the supporting portions of the hard mask layer portion; removing the sacrificial spacer; patterning at least a remaining portion of the sacrificial material layer, the first nanowire material layer and another sacrificial material layer overlying the first nanowire material layer to provide a sacrificial material layer portion, a first nanowire material layer portion and another sacrificial material layer portion, each of the sacrificial material layer portion, the first nanowire material layer portion and the another sacrificial material layer portion including a fin portion connected at each end to a respective supporting portion; and removing fin portions of the sacrificial martial layer portion and the another sacrificial material layer portion.