Patent ID: 9502363
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method for producing a wafer level package, the method comprising: embedding a semiconductor die in a molded panel having a frontside surface at which the semiconductor die is exposed; forming inner redistribution layers over a semiconductor die by depositing a body of dielectric material over the frontside surface of the molded panel and producing metal routing features in the body of dielectric material electrically coupled to the semiconductor die, the inner redistribution layers formed to include a routing-free dielectric block in the body of dielectric material and uninterrupted by the metal routing features; and forming an outer redistribution layer over the inner redistribution layers, the outer redistribution layer containing a metal plane patterned to include one or more outgassing openings overlying the routing-free dielectric block; wherein the routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer; wherein the routing-free dielectric block is located between the semiconductor die and the outgassing openings formed in the metal plane, as taken along an axis orthogonal to the outer redistribution layer; and wherein the routing-free dielectric block is formed to include a first boundary adjacent the outgassing openings and a second, opposing boundary adjacent a frontside of the semiconductor die.