Patent ID: 9398653
Filing Date: 2016-07-19
CPC Classification: H05B

Claim Text:
1. A LED driver, comprising: a first input port and a second input port, configured to receive an input AC voltage; an output port, configured to provide a driving voltage for the LED; a power stage, having a main power switch and a freewheel power switch; an inductor, coupled between the power stage and the output port, wherein the inductor gains energy from the input AC voltage and delivers the energy to the output port when the main power switch is ON and when the freewheel power switch is OFF, and the inductor supplies energy to the output port via the freewheel power switch when the main power switch is OFF; an output capacitor, coupled between the output port and a reference ground; an error amplifier, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive a first reference voltage, the second input terminal is configured to receive a current sense signal indicative of a current flowing through the inductor, and wherein the error amplifier generates an error amplified signal by amplifying and integrating a difference between the first reference voltage and the current sense signal; a set comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the error amplifier to receive the error amplified signal, the second input terminal is configured to receive the current sense signal, and wherein based on the error amplified signal and the current sense signal, the set comparator generates a set comparison signal at the output terminal; a first timer, configured to generate a minimum OFF time signal; a logical AND circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the set comparator to receive the set comparison signal, the second input terminal is coupled to the first timer to receive the minimum OFF time signal, and wherein based on the set comparison signal and the minimum OFF time signal, the first logical AND circuit generates a set signal at the output terminal; a reset comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive a second reference voltage, the second input terminal is configured to receive the current sense signal, wherein based on the second reference voltage and the current sense signal, the reset comparator generates a reset comparison signal at the output terminal; a second timer, configured to generate a maximum ON time signal; a logical OR circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the reset comparator to receive the reset comparison signal, the second input terminal is coupled to the second timer to receive the maximum ON time signal, wherein based on the reset comparison signal and the maximum ON time signal, the logical OR circuit generates a reset signal at the output terminal; a RS flip flop, having a set input terminal, a reset input terminal and an output terminal, wherein the set input terminal is coupled to the logical AND circuit to receive the set signal, the reset input terminal is coupled to the logical OR circuit to receive the reset signal, wherein based on the set signal and the reset signal, the RS flip flop generates a control signal at the output terminal; and a driving circuit, coupled to the RS flip flop to receive the control signal to generate a driving signal, to control the operation of the main power switch.