Patent ID: 9412460
Filing Date: 2016-08-09
CPC Classification: G11C

Claim Text:
1. An integrated circuit device, comprising: a first memory block comprising memory cells, configured to store data and to read the data in the first memory block using a first operation algorithm; a second memory block comprising memory cells, configured to store data and to read the data in the second memory block using a second operation algorithm, wherein the first and second memory blocks are distinguishable by block addresses; and controller circuitry coupled to the first and second memory blocks, and configured to execute the first operation algorithm or the second operation algorithm based on whether an operation is on a first selected cell in the first memory block or a second selected cell in the second memory block, wherein a word line pass voltage applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage applied in the second operation algorithm, and an average value of peak voltage levels of word line pass voltages applied in the first operation algorithm is lower than an average value of peak voltage levels of word line pass voltages applied in the second operation algorithm.