Patent ID: 9306572
Filing Date: 2016-04-05
CPC Classification: H03K

Claim Text:
1. An output buffer, comprising: a first transistor, a second transistor and an input signal control unit; wherein the input signal control unit controls an input signal to obtain a pull-up signal and a pull-down signal, the pull-up signal and the pull-down signal are input to input terminals of the first transistor and the second transistor, respectively, wherein input terminals of the input signal control unit comprises an input terminal of the input signal and input terminals of at least two control signals, wherein the input signal control unit further comprises at least two NAND gates; at least one control signal and the input signal are input to input terminals of the NAND gates; output terminals of the NAND gates output the pull-up signal of the input terminal of the first transistor and the pull-down signal of the input terminal of the second transistor, respectively, and the output terminals of the NAND gates are directly connected to the input terminal of the first transistor and the input terminal of the second transistor, wherein the at least two control signals are clock signals, the clock signals are designed so that time periods where the pull-up signal and the pull-down signal jump from a high level to a low level and from a low level to a high level are not overlapped to each other.