Patent ID: 9331734
Filing Date: 2016-05-03
CPC Classification: H03F,H04B

Claim Text:
1. A system on a chip (SoC) comprising: a transceiver having a transmitter and a receiver, at least one of the transmitter and receiver having a single ended mode portion having a single signal line and a differential mode portion having differential signal lines; two SoC interface pins for coupling the transceiver to an antenna via an asymmetric matching network, at least one of the two interface pins being coupled to the transmitter and to the receiver signal lines; a first tunable capacitor coupled to at least one of the signal lines and having a control input line; and a latch having an output coupled to the control input line of the tunable capacitor; in which the receiver has the single ended mode portion and the differential mode portion, and the first tunable capacitor is coupled to one differential output of a low noise amplifier of the receiver and a second tunable capacitor is coupled to another differential output of the low noise amplifier.