Patent ID: 9250898
Filing Date: 2016-02-02
CPC Classification: G06F

Claim Text:
1. A VLIW (Very Long Instruction Word) processor comprising: a first comparison operation unit; a second comparison operation unit; a first operation unit; a second operation unit; a third operation unit; and a register, wherein the first comparison operation unit receives a first comparison operation signal, a first input signal, and a second input signal, performs a comparison operation indicated by the first comparison operation signal on the first input signal and the second input signal, and outputs a result of the comparison operation, the second comparison operation unit receives a second comparison operation signal, a third input signal, and a fourth input signal, performs a comparison operation indicated by the second comparison operation signal on the third input signal and the fourth input signal, and outputs a result of the comparison operation, the first operation unit receives a first control signal, the comparison result of the first comparison operation unit, and a value already held in the register, and outputs, as a first operation result, one of the comparison result of the first comparison operation unit, an AND of the comparison result of the first comparison operation unit and the value of the register, and an OR of the comparison result of the first comparison operation unit and the value of the register, according to the first control signal, the second operation unit receives a second control signal, the comparison result of the second comparison operation unit, and a value already held in the register, and outputs, as a second operation result, one of the comparison result of the second comparison operation unit, an AND of the comparison result of the second comparison operation unit and the value of the register, and an OR of the comparison result of the second comparison operation unit and the value of the register, according to the second control signal, the third operation unit receives a third control signal, the first operation result, and the second operation result, and outputs, as an execution result, one of the first operation result, an AND of the first operation result and the second operation result, and an OR of the first operation result and the second operation result to the register according to the third control signal, and the register newly holds and outputs the execution result received from the third operation unit.