Patent ID: 9417495
Filing Date: 2016-08-16
CPC Classification: G02F,G09G

Claim Text:
1. A liquid crystal display panel, comprising: a capacitive element holding a pixel potential representing a gray-scale level and provided in each of a plurality of pixels of the liquid crystal display; a first switch element having a first terminal, and having a second terminal connected to a signal line, the first switch element being controlled to be ON during a first operation period where pixel potential is written from the signal line to the capacitive element, and controlled to be OFF during a second operation period including readout of the pixel potential from the capacitive element, inversion and amplification of the read out pixel potential, and rewriting of the inverted-amplified pixel potential to the capacitive element which are sequentially performed; a second switch element having a first terminal connected to the first terminal of the first switch element, the second switch element being controlled to be OFF during the first operation period, and controlled to be ON during a readout period where pixel potential stored in the capacitive element is read out, the readout period being one part of the second operation period; a third switch element having a first terminal connected to the first terminal of the first switch element, the third switch element being controlled to be OFF during the first operation period, and controlled to be ON during a write period where the pixel potential is written into the capacitive element, the write period being another part of the second operation period; a fourth switch element having a first terminal connected to one electrode of the capacitive element and a drive electrode of a liquid crystal element, and having a second terminal connected to the first terminal of the first switch element, the first terminal of the second switch element, and the first terminal of the third switch element; and a circuit restoring a logic level of pixel potential read out from the capacitive element through the second switch element during the readout period, and then writing a logically-inverted output of the restored logic level to the capacitive element through the third switch element during the write period, wherein the first terminal of the first switch element is connected to the one electrode of the capacitive element and the drive electrode of the liquid crystal element through the fourth switch element, and the circuit is provided between the first switch element and the fourth switch element, reads out the logic level of pixel potential from the capacitive element through the fourth switch element and the second switch element during the readout period, and writes the logically-inverted output to the capacitive element through the third switch element and the fourth switch element during the write period.