Patent ID: 9472251
Filing Date: 2016-10-18
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: a first memory cell region including: a second dummy memory cell region disposed at another side of the plurality of first normal memory cell regions; a first circuit region including a first control circuit to control an operation of the plurality of first normal memory cell regions, the first dummy memory cell region, and the second dummy memory cell region, in response to a first source signal; a second memory cell region including: a second circuit region including a second control circuit suitable for controlling operations of the plurality of second normal memory cell regions, the third dummy memory cell region, and the fourth dummy memory cell region, in response to a second source signal, wherein the first memory cell region and the second memory cell region are symmetrically disposed about a peripheral region of the semiconductor device and the first circuit region and second circuit regions are symmetrically disposed about the peripheral region of the semiconductor device, wherein a longest path in the first circuit region is same distance as a longest path in the second circuit region.