Patent ID: 9502417
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate including a first active region, a second active region and a field region, the field region between and directly contacting the first and the second active regions; an interlayer dielectric layer disposed on or above the substrate and including a trench, wherein the interlayer dielectric layer extends from the first active region to the second active region; a gate structure formed in the trench extends from the first active region to the second active region; and a spacer formed on a sidewall of the gate structure, wherein a top surface of a spacer and the top surface of the gate structure are substantially coplanar with each other, and wherein the gate structure comprises: wherein the p-type metal gate electrode and the n-type metal gate electrode contact each other at a contact surface therebetween which is closer to the first active region than to the second active region.