Patent ID: 9515648
Filing Date: 2016-12-06
CPC Classification: G06F,H03K

Claim Text:
1. A host power-on reset control circuit, comprising: a comparator electrically connected to receive a divided version of a supply voltage at a first input and a reference voltage at a second input, the comparator defined to generate a high digital state signal at a comparator output when the divided version of the supply voltage at the first input is at least as large as the reference voltage at the second input; an output node electrically connected to transmit a power-on reset control signal; pulldown circuitry electrically connected between the comparator output and the output node, the pulldown circuitry defined to maintain the output node at a reset voltage level as the supply voltage rises to a predetermined threshold level based on a digital state signal present at the comparator output, wherein the pulldown circuitry includes a first pulldown transistor electrically connected between the output node and a ground reference potential, wherein activation of the first pulldown transistor into a transmit state causes the output node to be electrically connected to the ground reference potential, wherein a gate of the first pulldown transistor is electrically connected to a second pulldown transistor and to a first terminal of a resistor and to a first terminal of a capacitor, wherein both a second terminal of the resistor is connected to the supply voltage and a second terminal of the capacitor is connected to the supply voltage such that a second divided version of the supply voltage is provided to the gate of the first pulldown transistor, wherein a gate of the second pulldown transistor is electrically connected to the comparator output, wherein activation of the second pulldown transistor into a transmit state causes the gate of the first pulldown transistor to be controlled such that the first pulldown transistor is in a non-transmit state so as to electrically isolate the output node from the ground reference potential, wherein the pulldown circuitry further includes a third pulldown transistor electrically connected between the second pulldown transistor and the ground reference potential, a gate of the third pulldown transistor electrically connected to receive a second reference voltage such that the third pulldown transistor is in a transmit state prior to activation of the second pulldown transistor into the transmit state; and pullup circuitry electrically connected between the supply voltage and the output node, the pullup circuitry defined to maintain the output node at a non-reset voltage level after the supply voltage has risen to the host operational level, wherein a low digital state signal at the comparator output causes the pulldown circuitry to electrically connect the output node to a ground reference potential, and wherein the high digital state signal at the comparator output causes the output node to be electrically isolated from the ground reference potential.