Patent ID: 9236389
Filing Date: 2016-01-12
CPC Classification: H01L

Claim Text:
1. A flash memory array comprising: a substrate comprising a plurality of active regions separated from each other by at least one shallow trench isolation (STI) region; a plurality of gate structure formed over the plurality of active regions, wherein each of the plurality of gate structures comprises a vertical stack of a gate dielectric, a floating gate and a dielectric gate cap, and a dielectric gate spacer present on each sidewall of the vertical stack; and a plurality of control gates extending through an interlevel dielectric (ILD) layer, wherein each of the plurality of control gates encloses a portion of a corresponding gate structure located at the at least one STI region and is in contact with the dielectric gate cap, the dielectric gate spacer and a portion of the at least one STI region abutting the dielectric gate spacer such that each of the plurality of control gates is electrically insulated from the floating gate by the dielectric gate cap and the dielectric gate spacer.