Patent ID: 9419593
Filing Date: 2016-08-16
CPC Classification: H03K

Claim Text:
1. A current mode logic (CML) latch comprising: an input stage including a positive input node to receive a positive side of a differential input signal, a negative input node to receive a negative side of the differential input signal, a positive output node to provide a positive side of a differential intermediate output signal, and a negative output node to provide a negative side of the differential intermediate output signal; a negative resistance stage including an input node connected to a first voltage source, a positive output node connected to the positive output node of the input stage and a negative output node connected to the negative output node of the input stage, the negative resistance stage to increase a current gain of the input stage; and a latch stage including a positive input node connected to the positive output node of the input stage, a negative input node connected to the negative output node of the input stage, a positive output node to provide a positive side of a differential output signal, and a negative output node to provide a negative side of the differential output signal.