Patent ID: 9231793
Filing Date: 2016-01-05
CPC Classification: H04L

Claim Text:
1. A decision feedback equalizer (DFE), comprising: an analog front end, having as input a digital communication signal with modulation of at least four levels, and having as output a feedforward signal; an analog summing stage, having as analog inputs the feedforward communication signal and feedback tap amplifier outputs, and having as an analog output the amplified communication signal minus the feedback tap amplifier outputs; a clocked slicer having as an analog input the analog output of the analog summing stage and having as a digital output a sequence of data decisions, wherein a width of the digital output of the clocked slicer is at least two bits corresponding with the modulation of at least four levels; a clocked digital delay chain having as input the digital output of the clocked slicer and having as output a plurality of delay taps, wherein each of a width of the clocked digital delay chain and a width of each of the plurality of delay taps equals the width of the digital output of the clocked slicer, and a plurality of feedback tap amplifiers, each having as digital input one of the plurality of delay taps, each having as analog output one of the feedback tap amplifier outputs.