Patent ID: 9349653
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a semiconductor structure, comprising: providing a substrate; forming a fin structure and an inter-layer dielectric layer on the substrate; forming a plurality of gate structures on the substrate; forming a cap layer on the gate structures; forming a hard mask on the cap layer; forming a first patterned photoresist layer on the hard mask, wherein the first patterned photoresist layer covers the gate structures; etching and patterning the hard mask to form a patterned hard mask, such that the patterned hard mask covers the gate structures; forming a second patterned photoresist layer on the patterned hard mask, wherein the second patterned photoresist layer comprises a plurality of openings corresponding to the fin structure; and etching the cap layer and the inter-layer dielectric layer to form a plurality of first trenches, wherein the first trenches expose part of the fin structure.