Patent ID: 9299666
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A stacked semiconductor device, comprising: a first semiconductor package comprising: a second semiconductor package comprising: the first semiconductor package is stacked on the first surface of the second semiconductor package, such that the first semiconductor package is electrically connected to the second semiconductor package through the solder portion; the first printed wiring board has a first solder resist formed on the second surface thereof, each of the multiple first lands having a part joined to the solder portion through a first opening formed in the first solder resist; the second printed wiring board has a second solder resist formed on the one surface thereof, the second land having a part joined to the solder portion through a second opening formed in the second solder resist; an area of each of the multiple first lands joined to the solder portion through the first opening is smaller than an area of the second land joined to the solder portion through the second opening; and a ratio of the area of each of the multiple first lands joined to the solder portion through the first opening to the area of the second land joined to the solder portion through the second opening is 0.56 or more and 0.81 or less.