Patent ID: 9257517
Filing Date: 2016-02-09
CPC Classification: H01L

Claim Text:
1. A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET), with a cell structure comprising: a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first conductivity type on said substrate; first and second base regions of a second conductivity type within said epitaxial layer, spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged in said first and second base regions, respectively, wherein said first and second base region are operable to form first and second lateral channels between said source region and said epitaxial layer; a gate structure insulated from said epitaxial layer by an insulating layer and arranged above the region between the first and second base regions and wherein the gate structure comprises first and second gate regions each forming a first and second gate, each gate region only covering the first and second lateral channel, respectively within said first and second base region, wherein the insulating layer comprises a gate oxide layer on top of which a thick oxide layer is arranged and patterned to form a pedestal between said first and second source regions and wherein the gate structure is U-shaped and surrounding said pedestal, wherein the first and second gate are formed only by first and second vertical side walls of said U-shaped gate structure and wherein the first and second vertical side walls have a thickness defined by a trench and horizontal bottom end faces having said thickness of said trench form the first and second gate, respectively and cover the first and second lateral channels, respectively.