Patent ID: 9263784
Filing Date: 2016-02-16
CPC Classification: H01P,H05K

Claim Text:
1. A package substrate, comprising: a core substrate; a first buildup layer formed on a first surface of the core substrate; and a second buildup layer formed on a second surface of the core substrate on an opposite side with respect to the first surface of the core substrate, wherein the first buildup layer comprises an uppermost insulating resin interlayer, an upper inner insulating resin interlayer, an uppermost conductive layer formed on the uppermost insulating resin interlayer and including a plurality of first pads positioned to mount a first electronic component and a plurality of second pads positioned to mount a second electronic component, an upper first conductive layer formed on the upper inner insulating resin interlayer, an upper second conductive layer formed on the upper inner insulating resin interlayer on an opposite side with respect to the upper first conductive layer, a plurality of conductive vias formed through the uppermost insulating resin interlayer such that the plurality of conductive vias is connecting the upper first conductive layer and the second pads, and a plurality of conductive skip vias formed through the uppermost insulating resin interlayer and the upper inner insulating resin interlayer such that the plurality of conductive skip vias is connecting the uppermost conductive layer and the upper second conductive layer, and the second buildup layer comprises a lowermost insulating resin interlayer, a lower inner insulating resin interlayer, a lowermost conductive layer formed on the lowermost insulating resin interlayer and including a plurality of third pads, a lower first conductive layer formed on the lower inner insulating resin interlayer, a lower second conductive layer formed on the lower inner insulating resin interlayer on an opposite side with respect to the lower first conductive layer, a plurality of conductive vias formed through the lowermost insulating resin interlayer such that the plurality of conductive vias is connecting the lower first conductive layer and the third pads, and a plurality of conductive skip vias formed through the lowermost insulating resin interlayer and the lower inner insulating resin interlayer such that the plurality of conductive skip vias is connecting the lowermost conductive layer and the lower second conductive layer.