Patent ID: 9391794
Filing Date: 2016-07-12
CPC Classification: G01R,G06F,H04L

Claim Text:
1. An apparatus comprising at least one non-transitory computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: determining multiple receive waveforms capable of being output from a channel of an electrical system in response to corresponding drive waveforms input to the channel; generating a set of test bit sequences, each test bit sequence correlated to a plurality of the receive waveforms based, at least in part, on bit sequences capable of being utilized by a driver to generate the drive waveforms; and selecting a test bit sequence from the set of test bit sequences based, at least in part, on characteristics of the receive waveforms correlated to the test bit sequences; and driving the channel of the electrical system with a test drive waveform generated by the driver in response to the selected test bit sequence, wherein the test receive waveform output from the channel in response to test drive waveform input to the channel indicates a signal integrity of the channel.