Patent ID: 9379881
Filing Date: 2016-06-28
CPC Classification: H03K,H04L

Claim Text:
1. A phase interpolator circuit comprising: an interpolator suitable for generating synthesized clocks through synthesizing two multi-phase clocks that are selected from first to N-th multi-phase clocks, wherein N is an integer greater than or equal to 3; and an interpolation code generator suitable for generating an interpolation code for controlling the interpolator in response to a shift-up request, a shift-down request, a multi-shift-up request, and a multi-shift-down request, wherein the interpolation code generator generates the interpolation code so that a (K+1)-th multi-phase clock is output as the synthesized clock when a phase of the synthesized clock should be changed from a phase between K-th and (K+1)-th multi-phase clocks to a phase between (K+1)-th and (K+2)-th multi-phase clocks in response to the multi-shift-up request, wherein K is an integer greater than or equal to 1 and less than or equal to N, in the case of K-th being N-th, (K+1)-th is first, and in the case of K-th being first, (K−1)-th is N-th.