Patent ID: 9230613
Filing Date: 2016-01-05
CPC Classification: G01R,G11C

Claim Text:
1. A power up detecting system, for outputting one of a first power up detecting signal and a second power up detecting signal as a final power up detecting signal, according to power provided by a power supplier, comprising: a power up detecting module, for detecting a voltage value of the power to simultaneously generate the first power up detecting signal and the second power up detecting signal; and a selector, coupled to the power up detecting module to receive the first power up detecting signal and the second power up detecting signal, controlled by a control signal to output the first power up detecting signal as the final power up detecting signal in a first mode and controlled by the control signal to output the second power up detecting signal as the final power up detecting signal in a second mode; wherein the first power up detecting signal has a first voltage level if the voltage value of the power is smaller than a first predetermined voltage value, and has a second voltage level if the voltage value of the power is larger than the first predetermined voltage value; wherein the second power up detecting signal has the first voltage level if the voltage value of the power is smaller than the second predetermined voltage value, and has the second voltage level if the voltage value of the power is larger than the second predetermined voltage value; where the first predetermined voltage value is higher than the second predetermined voltage value; wherein the selector comprises: a inverter, for receiving the first power up detecting signal; a first NAND gate, for receiving the second power up detecting signal and the control signal; and a second NAND gate, for receiving outputs of the inverter and the first NAND gate to generate the final power up detecting signal.