Patent ID: 9520402
Filing Date: 2016-12-13
CPC Classification: H01L

Claim Text:
1. An apparatus, comprising: a memory array having a plurality of wordlines disposed in a staircase structure in a die, wherein the plurality of wordlines includes at least a first wordline, a second wordline disposed on top of the first wordline and a third wordline disposed substantially underneath the first wordline, wherein at least the first wordline includes a semiconductor layer disposed on the third wordline, and a silicide layer disposed on the third wordline to abut a vertical edge of the semiconductor layer, and to extend the first wordline on the third wordline beyond a vertical edge of the second wordline to form a stair of the staircase structure on the third wordline, wherein the silicide layer forms an etch stop of the first wordline for a wordline contact structure to electrically connect the first wordline with the memory array in response to a deposition of the wordline contact structure on the etch stop, and to prevent a physical or electrical contact of the wordline contact structure with the third wordline of the staircase structure, wherein the etch stop further includes a spacer disposed to abut the silicide layer around an end of the first wordline, wherein a top surface of the silicide layer, sidewalls of a passivation layer that separates the first wordline from the second wordline, and a space in between the first wordline and the second wordline are free from the spacer.