Patent ID: 9411740
Filing Date: 2016-08-09
CPC Classification: G06F,G11C,H01L

Claim Text:
1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes: a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is greater than a width of the contact plug and a width of the second stack structure, and wherein the first stack structure includes a first hard mask layer which is conductive and nonmagnetic, the first hard mask layer is positioned at an uppermost part of the first stack structure.