Patent ID: 9490243
Filing Date: 2016-11-08
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising an ESD protection device for protecting an integrated circuit on the semiconductor device against ESD event received by the integrated circuit, the ESD protection device comprising a semiconductor substrate, the semiconductor substrate having a first side, the semiconductor substrate having an N-buried region extending in a lateral direction in the interior of the semiconductor substrate, a p-doped isolated portion of the semiconductor substrate being isolated from a remaining part of the semiconductor substrate by an isolation structure, the isolation structure comprising the N-buried region, an N-doped region being arranged in the p-doped isolated portion and extending from the first side towards the N-buried region, the N-doped region subdividing the isolated portion in a first portion and a second portion, a first p-doped region and a second p-doped region extending from the first side into, respectively, the first portion and the second portion, the p-dopant concentration of the first p-doped region and of the second p-doped region being higher than the p-dopant concentration of the first portion and the second portion, a first contact region and a second contact region extending from the first side, respectively, into the first p-doped region and into the second p-doped region, the first contact region and the second contact region being p-doped with a dopant concentration being higher than the p-dopant concentration of the first p-doped region and of the second p-doped region, a first electrical contact being electrically connected to the first p-doped region only via the first contact region, the first electrical contact being configured for being connected to an I/O pad of the semiconductor device, a second electrical contact being electrically connected to the second p-doped region only via the second contact region, the second electrical contact being configured for being connected to a most negative voltage available on the semiconductor device under normal operational condition or to a ground voltage, a third electrical contact being electrically connected to the remaining part of semiconductor substrate, the third electrical contact being configured for being connected to the ground voltage, wherein: the second section is configured to provide a first spacing distance between the second p-doped region and the N-doped region to provide a predefined trigger voltage of the ESD protection device in case of a positive voltage ESD event, and the first section is configured to provide a second spacing distance between the first p-doped region and the N-doped region to provide a predefined trigger voltage of the ESD protection device in case of a negative voltage ESD event.