Patent ID: 9318345
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a first strain-inducing dielectric layer above a first transistor and a second transistor of a semiconductor device; selectively removing a portion of said first strain-inducing layer from above said second transistor by covering said first transistor with a resist mask and performing a first plasma assisted etch process in a first processing chamber using a first process environment; moving said semiconductor device from said first processing chamber to a second processing chamber; removing said resist mask by performing a second plasma assisted process in said second processing chamber using a second process environment that is different from said first process environment; forming a second strain-inducing dielectric layer above said first transistor and said second transistor; selectively removing said second strain-inducing dielectric layer from above said first transistor in a third process environment by using a resist mask formed above said second transistor; and removing said resist mask in a fourth process environment that is different from said first and third process environments.