Patent ID: 9263143
Filing Date: 2016-02-16
CPC Classification: G11C,H01L

Claim Text:
1. A data erase method of a three dimensional (3D) memory device, wherein the 3D memory device comprises a plurality of word lines and a plurality of semiconductor channels, the semiconductor channels intersect with the word lines to form a plurality of memory cells, the data erase method comprises: in a first phase of an erase operation, applying a first voltage to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and applying a second voltage to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel; in a second phase of the erase operation, applying the second voltage to the first semiconductor channel and applying the first voltage to the second semiconductor channel; wherein the voltage level of the first voltage is different from that of the second voltage, and the voltage polarity of the first voltage is opposite to that of the second voltage.