Patent ID: 9287397
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate; forming spacers on sidewalls of the gate electrodes; depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers; selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes, remains after the selective etch, and wherein a portion of the gate electrodes is exposed to form an exposed portion of the gate electrodes after the selective etch of the interconnection layer; forming a dielectric layer on the semiconductor substrate, the sidewalls of the spacers, and the exposed portion of the gate electrodes; and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes, wherein the electrical contact is selectively formed on a portion of the etched interconnection layer located between adjacent laterally opposite spacers.