Patent ID: 9524358
Filing Date: 2016-12-20
CPC Classification: G06F,G09B

Claim Text:
1. A method for designing and executing an interoperability architecture for computer modeling, the method comprising: establishing tasks; formulating use cases corresponding to said tasks; based on said use cases, identifying requirements; based on said requirements, constructing an interoperability architecture characterized by both physical interoperability and functional interoperability, said interoperability architecture having a core, plural modules, and an interface between said core and said modules, each said module representing a different computer model, wherein said constructing of said interoperability architecture includes determining said modules, determining plural functionalities, and assigning each said functionality to either said core or each of at least one said module, wherein: said core contains a fixed set of shared data; said core includes at least four core components; a first said core component is a geometry component; a second said core component is a communications component; a third said core component is a sensor fusion component; a fourth said core component is a decision-making component; said fixed set of said shared data is categorized according to said geometry component, said communications component, said sensor fusion component, and said decision-making component; and effecting interoperability of said modules with respect to each other, said effecting of said interoperability including implementing a computer, wherein said interoperability includes a cyclical process having at least three phases, said at least three phases including an initiation phase, a simulation phase, and an interrogation phase, said cyclical process maintaining consistency of said shared data contained in said core, wherein: during said initiation phase, said modules have write-access, via said interface, to said shared data contained in said core, each said module being capable of adding to or deleting from or modifying said shared data contained in said core, said modules not having read-access to said shared data contained in said core; during said simulation phase, said core performs at least one calculation with respect to said shared data, said modules having neither write-access nor read-access to said shared data contained in said core; during said interrogation phase, said modules have read-access, via said interface, to said shared data contained in said core, each said module being capable of reading said shared data contained in said core, said modules not having write-access to said shared data contained in said core.