Patent ID: 9519609
Filing Date: 2016-12-13
CPC Classification: G06F,H01L,Y02D

Claim Text:
1. An apparatus comprising: a first set of single-ended transmitter circuits on a first die having input/outputs (I/Os), the first die within a semiconductor package, wherein the transmitter circuits are impedance matched and have no equalization; a first set of single-ended receiver circuits on a second die having I/Os, the second die within the semiconductor package, wherein the receiver circuits have no termination and no equalization; and a plurality of conductive lines disposed on a planar board that are each directly coupled to both the I/Os of first die and the I/Os of the second die to directly couple the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched, and wherein the I/Os of the first die and the I/Os of the second die couple to the planar board beneath the first die and second die respectively and are not pins that couple into sockets.