Patent ID: 9438207
Filing Date: 2016-09-06
CPC Classification: H01L,H03K

Claim Text:
1. A semiconductor device comprising a logic circuit capable of storing configuration data, wherein the logic circuit comprises latch circuits, an arithmetic circuit, a delay circuit, and an output timing generation circuit, wherein each of the latch circuits is capable of receiving a pulse signal from an adjacent logic circuit and outputting a first signal and a second signal, wherein a third signal obtained by a logical operation on the first signals controls power supply to the arithmetic circuit and the delay circuit, wherein the arithmetic circuit is capable of receiving the second signals and outputting a fourth signal, wherein the second signal is obtained by delaying the first signal in each of the latch circuits, wherein the delay circuit is capable of receiving the third signal and outputting a fifth signal, wherein the fifth signal is obtained by delaying the third signal so as to correspond to a delay in a critical path of the arithmetic circuit, and wherein the output timing generation circuit is capable of receiving a sixth signal obtained by a logical operation on the third signal and the fifth signal and resetting the latch circuits.