Patent ID: 9281294
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A multi-chip semiconductor device comprising: a first semiconductor chip that is plate-shaped and includes a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip; and a second semiconductor chip that is plate-shaped and includes a second connection portion in which a second semiconductor chip electrode is formed on an edge surface adjacent to a second main surface of the second semiconductor chip, wherein the first connection portion and the second connection portion are connected to each other such that the first main surface of the first semiconductor chip and the edge surface of the second semiconductor chip intersect to each other such that the edge surface of the second semiconductor chip butts against the first main surface of the first semiconductor chip; the first connection portion is formed in a recessed shape on the first main surface of the first semiconductor chip and includes a first inclined surface and a second inclined surface that are inclined with respect to the first main surface of the first semiconductor chip, and a bottom surface that is parallel to the first main surface of the first semiconductor chip, and the first semiconductor chip electrode is formed on the first inclined surface, the second inclined surface and the bottom surface of the first connection portion, the second connection portion is formed on the edge surface of the second semiconductor chip and includes a third inclined surface and a fourth inclined surface that are inclined with respect to the second main surface of the second semiconductor chip, and a bottom surface that is vertical to the second main surface of the second semiconductor chip, and the second semiconductor chip electrode is formed on the third inclined surface, the fourth inclined surface and the bottom surface of the second connection portion, and the second connection portion is fitted into and connected to the first connection portion such that the first main surface of the first semiconductor chip and the edge surface of the second semiconductor chip intersect each other.