Patent ID: 9431549
Filing Date: 2016-08-30
CPC Classification: B82Y,H01L

Claim Text:
1. A memory device comprising: a channel electrically connecting a first diffusion region and a second diffusion region of the memory device; and a gate stack adjoining at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a charge-trapping layer abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the charge-trapping layer, wherein the charge-trapping layer includes a first charge-trapping layer comprising an oxygen-rich nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a silicon-rich nitride overlying the first charge-trapping layer, and wherein the multi-layer blocking dielectric comprises a first dielectric layer abutting the charge-trapping layer comprising an oxidized portion of the second charge-trapping layer and a second dielectric layer abutting the first dielectric layer, the first dielectric layer having a dielectric constant in the range of 3.5-4.5, and the second dielectric layer comprising a silicate and having a dielectric constant higher than a dielectric constant of the first dielectric layer.