Patent ID: 9520421
Filing Date: 2016-12-13
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) substrate, comprising the following steps: (1) providing a substrate and depositing a buffer layer on the substrate; (2) depositing a thermally conductive electrical insulation film on the buffer layer and patterning the thermally conductive electrical insulation film to form a thermally conductive electrical insulation layer; (3) depositing an amorphous silicon layer on the buffer layer in such a way that the amorphous silicon layer completely covers the thermally conductive electrical insulation layer; (4) implanting boron ions in the amorphous silicon layer through ion implantation; subjecting the amorphous silicon layer to rapid thermal annealing to have the amorphous silicon crystallized into polycrystalline silicon, and then applying an etching operation to remove an electrically conductive layer precipitating on a surface of the polycrystalline silicon during crystallization to form a polycrystalline silicon layer; (5) patterning the polycrystalline silicon layer to form a polycrystalline silicon semiconductor layer; (6) coating photoresist on the polycrystalline silicon semiconductor layer and conducting exposure and development on the photoresist to form a photoresist layer on the polycrystalline silicon semiconductor layer in such a way that two end portions of the polycrystalline silicon semiconductor layer are exposed; implanting boron ions into the two end portions of the polycrystalline silicon semiconductor layer through ion implantation with the photoresist layer serving as a shielding layer so as to form source/drain contact zones; and (7) peeling off the photoresist layer and forming, in sequence, a gate insulation layer, a gate terminal, an interlayer insulation layer, and source/drain terminals on the polycrystalline silicon semiconductor layer, wherein the source/drain terminals are respectively connected to the source/drain contact zones at the two end portions of the polycrystalline silicon semiconductor layer.