Patent ID: 9425181
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A preparation method of a hybrid packaging multi-chip semiconductor device, the preparation method comprising: providing a lead frame unit, the lead frame unit comprising: attaching a first semiconductor chip onto a top surface of the first die paddle and attaching a second semiconductor chip on the third pin and on the second die paddle, wherein a first electrode and a second electrode at a front surface of the second semiconductor chip are electrically connected to the second die paddle and the third pin respectively; and attaching a first interconnecting structure on the first semiconductor chip and the second semiconductor chip, wherein the first interconnecting structure comprises a main plate having at least a first side wall bending downward at a side of the main plate; wherein the first side wall is mounted on a selected pin of the first pin and the second pin, so that a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip are electrically connected to the selected pin of the first pin and the second pin; and wherein a second electrode at the front surface of the first semiconductor chip is electrically connected to an other pin of the first pin and the second pin through a second interconnecting structure.