Patent ID: 9281291
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device comprising the steps of: (a) providing a glass substrate having an electrode; (b) providing a semiconductor chip; the semiconductor chip includes: a MISFET formed over the semiconductor substrate, the MISFET being formed in the integrated circuit formation region; a first wiring layer formed over the MISFET, the first wiring layer formed in the integrated circuit formation region; a plurality of first patterns formed over the semiconductor substrate and in the same layer as the first wiring layer, the plurality of first patterns being formed in the alignment mark formation region; a first interlayer insulating film formed over the semiconductor substrate to cover the first wiring layer and the plurality of first patterns; a second wiring layer formed over the first interlayer insulating film, the second wiring layer being formed in the integrated circuit formation region; a plurality of second patterns formed over the first interlayer insulating film and in the same layer as the second wiring layer, the plurality of second patterns being formed in the alignment mark formation region; a second interlayer insulating film formed over the semiconductor substrate to cover the second wiring layer and the plurality of second patterns; a third wiring layer formed over the second interlayer insulating film, the third wiring layer being formed in the integrated circuit formation region; an alignment mark formed over the second interlayer insulating film and in the same layer as the third wiring layer, the alignment mark being formed in the alignment mark formation region; a further insulating film formed over the semiconductor substrate to cover the third wiring and the alignment mark, the insulating film having an opening at an upper side of the third wiring layer; and a bump electrode formed over the insulating film such that the bump electrode is electrically connected to the third wiring layer via the opening, wherein the first wiring, the second wiring and the third wiring are electrically connected to the MISFET, and wherein the plurality of first patterns and the plurality of second patterns are not electrically connected to the MISFET; and (c) mounting the semiconductor chip over the glass substrate such that the bump electrode is electrically connected to the electrode of the glass substrate, wherein the connection between the bump electrode and the electrode of the glass substrate in the step (c) is performed by recognizing the alignment mark with a camera.