Patent ID: 9501436
Filing Date: 2016-11-22
CPC Classification: G06F

Claim Text:
1. An apparatus comprising a processor, a logic and a memory, wherein the processor, logic and memory are operable to configure a data structure comprising: one or more second level descriptors; and one or more first level linked lists corresponding to the one or more second level descriptors; wherein each second level descriptor comprises a data descriptor address for pointing to a corresponding first level linked list; wherein each first level linked list comprises one or more first level descriptors; wherein each first level descriptor comprises a buffer address for pointing to a corresponding data buffer; and wherein at least one first level linked list and the corresponding one or more first level descriptors are accessed by a first and second DMA channel for coordinated data transfer of the corresponding data buffer; wherein the one or more first level descriptors are shared by a plurality of DMA engines.