Patent ID: 9337201
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A memory cell comprising: a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions; the inner source/drain region having opposing laterally outer sides; a pair of data/sense lines, one of the pair of data/sense lines being electrically coupled to and against one of the outer sides of the inner source/drain region, the other of the pair of data/sense lines being electrically coupled to and against the other of the outer sides of the inner source/drain region, the data/sense lines of the pair of data/sense lines being electrically coupled to one another through the inner source/drain region, the data/sense lines of the pair of data/sense lines additionally being electrically coupled to one another by an electrically conductive interconnect, each of the pair of data/sense lines proiecting laterally into the inner source/drain region and also projecting laterally outward from the inner source/drain region; an access gate line elevationally outward of the pair of electrically coupled data/sense lines and which is operatively adjacent the channel region; and a charge storage device electrically coupled to the outer source/drain region.