Patent ID: 9331171
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a semiconductor device, at least comprising the following steps: providing a substrate, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate; forming a second dielectric layer on the first dielectric layer; performing a first etching process to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein each first trench exposes each S/D region; performing a salicide process to form a salicide layer in each first trench; and performing a second etching process to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, wherein each second trench exposes each metal gate.