Patent ID: 9501279
Filing Date: 2016-11-22
CPC Classification: G06F

Claim Text:
1. A method of executing instructions in a processing unit of the type including an execution unit including a register file and instruction decode logic including an instruction buffer, the method comprising: fetching a first plurality of instructions from an instruction stream and stored in the instruction buffer with the instruction decode logic of the processing unit; in response to at least one instruction from the instruction stream, causing the execution unit to manipulate operand data stored in the register file; in response to at least one instruction from the instruction stream, loading a second plurality of instructions into the register file of the execution unit to utilize at least a portion of the register file as a local instruction loop buffer; fetching the second plurality of instructions from the register file rather than fetching instructions stored in the instruction buffer; and causing the execution unit to execute the second plurality of instructions fetched from the register file.