Patent ID: 9362396
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate having a main surface and a back surface opposing to the main surface; a drain layer of a first conduction type formed on the back surface of said semiconductor substrate; a base layer of a second conduction type different from the first conduction type formed in said semiconductor substrate and provided over said drain layer; a recess formed in said base layer so that the bottom end of said recess is located lower than base layer; a gate insulation film formed over the inner wall of said recess; a gate electrode embedded into said recess; and a source layer of the first conduction type formed in said base layer so as to be shallower than said base layer and located next to said recess in a plan view, wherein said base layer includes, in an impurity profile in the thickness direction, three or more peaks, and wherein the impurity profile of said base layer in a thickness direction includes a first peak, a second peak being located closer to a bottom face side of said semiconductor substrate than said first peak and being higher than said first peak, and a third peak located between said first peak and said second peak.