Patent ID: 9337208
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a plurality of gate structures disposed on a substrate; an intermediate layer disposed on the gate structures and above the substrate between two adjacent gate structures, wherein the intermediate layer comprises: a first intermediate material layer disposed on a surface and sidewalls of each of the gate structures; and a second intermediate material layer disposed on the first intermediate material layer, wherein a material of the second intermediate material layer comprises silicon nitride, and a material of the first intermediate material layer comprises silicon oxide; and a dielectric layer disposed on the intermediate layer, wherein an air gap is formed between two adjacent gate structures, and the air gap comprises: a main space defined by the sidewalls of two adjacent gate structures, a surface of the substrate, and the intermediate layer; and a protruding space located on the main space, defined by the intermediate layer and the dielectric layer, and protrudes into the dielectric layer.