Patent ID: 9414262
Filing Date: 2016-08-09
CPC Classification: G06F,H04B,H04W

Claim Text:
1. An interference suppression method for use in a device having a receiver and a processor, the method comprising: receiving, by the receiver, a system clock signal having a first frequency; and converting, by the processor, the system clock signal into an optimal clock signal of a current sensitive frequency band, wherein the optimal clock signal and high-order harmonics of the optimal clock signal do not fall within a receive band of the current sensitive frequency band, wherein the optimal clock signal is selected, with reference to the current sensitive frequency band, from the system clock signal and at least one planned clock signal which is determined according to the first frequency, a frequency of the at least one planned clock signal is a second frequency, and a frequency increment of the second frequency relative to the first frequency is less than or equal to a threshold.