Patent ID: 9258000
Filing Date: 2016-02-09
CPC Classification: H03L

Claim Text:
1. A detector for detecting a locked state and an out-of-lock state of a phase locked loop (PLL), the detector comprising: an out-of-lock detector circuit configured to receive a reference signal used by the PLL and an input signal representing a PLL oscillator signal, the out-of-lock detector further configured to detect an out-of-lock state of the PLL and generate an out-of-lock signal indicating whether an out-of-lock state is detected; a lock detector circuit configured to receive the reference signal and the input signal, and further configured to detect a locked state of the PLL, and generate a lock signal indicating whether a locked state is detected; and a logic circuit configured to receive the out-of-lock signal and the lock signal and further configured to combine the out-of-lock signal and the lock signal to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state.