Patent ID: 9318554
Filing Date: 2016-04-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor layer having first and second opposing main surfaces; a first trench and a second trench, each of the first and second trenches extending from the first main surface of the semiconductor layer and having a first sidewall and a second sidewall; first columns of a first conductivity type, each first column respectively extending along the first sidewall of the first trench and the second sidewall of the second trench, and a second column of a second conductivity type is disposed between and adjacent the first columns, the second conductivity type being opposite to the first conductivity type; a first channel of the first conductivity type extending from the first sidewall of the first trench along the first main surface; a second channel of the first conductivity type extending from the second sidewall of the second trench along the first main surface; a doped region of the first conductivity type disposed between the first and second trenches and extending from the first main surface, wherein between the first and second trenches, the doped region is electrically connected to the first columns by the first and second channels; a gate feed disposed proximate the doped region and separated therefrom by a layer of oxide formed on the first main surface, the gate feed having a longitudinal axis extending in a direction parallel to the first main surface and parallel to the first and second trenches; and a first MOSFET cell at least partially formed in the semiconductor layer proximate the second sidewall of the first trench and a second MOSFET cell at least partially formed in the semiconductor layer proximate the first sidewall of the second trench, the first and second trenches being separated in a direction parallel to the first main surface and perpendicular to the longitudinal axis of the gate feed by about 45 micrometers to about 60 micrometers.