Patent ID: 9276011
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. An apparatus, comprising: a source material; a drain-side select gate (SGD); a memory stack arranged between the source material and the SGD and having alternating levels of conductor materials and dielectric materials between a level corresponding to the source material and a level corresponding to the SGD; and a channel-fill material that is continuous from the source material to at least the level corresponding to the SGD, the memory stack including a plurality of recessed charge storage structures, a substantial amount of each of the plurality of charge storage structures being formed within a level of respective ones of the conductor material and laterally away from the channel-fill material, each of the plurality of charge storage structures further being formed substantially between adjacent ones of the alternating levels of dielectric materials with each of the plurality of recessed charge storage structures being separated from a remaining portion of the conductor material on the same level by a dielectric material.