Patent ID: 9470760
Filing Date: 2016-10-18
CPC Classification: G01R

Claim Text:
1. A method of performing wafer-level testing during production of a register-programmable integrated circuit, the method comprising: generating a microcode instruction by simulating a data exchange between a simulated central electronic complex and a simulation of the register-programmable integrated circuit, wherein the microcode instruction includes at least one code element configured for execution by an initializing processor to initialize the register-programmable integrated circuit after production; transforming, using a computing device, the microcode instruction and corresponding data from an initializing processor format into tester-formatted data, wherein transforming the microcode instruction includes: applying, using a tester device coupled with the computing device, the tester-formatted data to the register-programmable integrated circuit; and verifying, after applying the tester-formatted data to the register-programmable integrated circuit, the function of the integrated circuit based on a global error indicator included in the register-programmable integrated circuit.