Patent ID: 9390985
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A method of forming a semiconductor arrangement comprising: determining a first photoresist height of a first area of a first photoresist adjacent a first dummy gate after a first photoresist etch; determining a second photoresist height of a second area of the first photoresist after the first photoresist etch; responsive to a first difference between the first photoresist height and the second photoresist height being less than a first threshold difference, performing a hard mask etch, where the hard mask etch removes a first hard mask of the first dummy gate, a portion of a first sidewall spacer above the first photoresist and a portion of a second sidewall spacer above the first photoresist, where a first spacer height of the first sidewall spacer is correlated to a mean of the first photoresist height and the second photoresist height and a second spacer height of the second sidewall spacer is correlated to the mean of the first photoresist height and the second photoresist height; removing a first dummy material of the first dummy gate from between the first sidewall spacer and the second sidewall spacer; and forming a first gate by forming a first gate electrode between the first sidewall spacer and the second sidewall spacer, where a first gate height of the first gate is correlated to at least one of the first spacer height or the second spacer height.