Patent ID: 9313016
Filing Date: 2016-04-12
CPC Classification: H03L,H04L

Claim Text:
1. A receiver circuit for capturing an input signal at a plurality of capture timings determined based on a capture clock signal, comprising: a delay circuit configured to delay the input signal changing to a first state or a second state by a set delay time, and output the delayed input signal; a latch circuit configured to capture the input signal delayed by the delay circuit at each capture timing; a data test circuit configured to test a latch signal captured by the latch circuit; and a data test result register configured so that a test result value corresponding to a test result of the data test circuit is set therein, wherein the data test circuit compares the latch signal captured by the latch circuit at each capture timing with an expected value, and outputs the result of the comparison and includes a first cross-point detection unit configured to, when it is determined based on the test result value that a period of time during which the first or second state continues is longer than a cycle of the capture timing, detect a deviation of a cross point of the input signal input as differential signals.