Patent ID: 9406361
Filing Date: 2016-08-02
CPC Classification: G11C

Claim Text:
1. A computer system comprising: a processor implemented on a silicon interposer of an integrated circuit (IC) package; a die-stacked dynamic random access memory (DSDRAM) coupled to the processor, the DSDRAM implemented on the silicon interposer of the IC package; a DRAM implemented separately from the IC package, wherein the DSDRAM and the DRAM form a main memory having a contiguous address space comprising a range of physical addresses, the physical addresses of the DSDRAM occupying a first portion of the contiguous address space and the DRAM occupying a second portion of the contiguous address space; a storage unit storing instructions of an operating system (OS) executable on the processor, wherein the OS is configured to, upon initially allocating a page to the DRAM, also allocate the page to the DSDRAM; and a memory controller having a reverse promotion table (RPT) configured to store DRAM addresses of pages stored in the DRAM; wherein each physical address of the contiguous address space is augmented with a first bit that, when set, indicates that a page is stored in the DRAM and the DSDRAM; and wherein responsive to a memory request to a page having a particular DRAM address, the OS is configured to cause a search of the RPT for the particular DRAM address responsive to determining that the first bit is not set for the particular DRAM address.