Patent ID: 9230992
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a semiconductor substrate including an nFET portion and a pFET portion separately located from the nFET portion; at least one first semiconductor fin formed on the nFET portion, the at least one first semiconductor fin having an nFET channel region interposed between a pair of nFET source/drain regions; and at least one second semiconductor fin formed on the pFET portion, the at least one second semiconductor fin having a pFET channel region interposed between a pair of pFET source/drain regions, the pFET channel region including an etched portion of the at least one second semiconductor fin, and wherein the etched portion has a first thickness that is less than a second thickness of the at least one first semiconductor fin; and an epitaxial liner formed only on the pFET channel region such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel region wherein the epitaxial liner is formed on the etched portion, the combination of the etched portion and the epitaxial liner defining a third thickness that is equal to the second thickness of the at least one first semiconductor fin.