Patent ID: 9484465
Filing Date: 2016-11-01
CPC Classification: G02F,H01L

Claim Text:
1. An array substrate, comprising: a substrate; and a first gate metal layer, a first gate insulating layer, a semiconductor layer and a source-drain electrode layer disposed in this order on the substrate from bottom to top; the array substrate further comprising: a second gate insulating layer disposed on the source-drain electrode layer; a second gate metal layer disposed on the second gate insulating layer; a first common electrode line disposed in a same layer as the first gate metal layer or disposed in a same layer as the second gate metal layer; and a second common electrode line, wherein: in condition that the first common electrode line and the first gate metal layer are in same and one layer, the second common electrode line and the second gate metal layer are in same and one layer; and in condition that the first common electrode line and the second gate metal layer are in same and one layer, the second common electrode line and the first gate metal layer are in same and one layer.