Patent ID: 9391206
Filing Date: 2016-07-12
CPC Classification: H01L

Claim Text:
1. A device comprising: first and second pillars of semiconductor material, each of the first and second pillars of semiconductor material comprising a wide upper region and a narrow lower region under the wide upper region; a first gate dielectric material formed along sidewalls of the wide upper region and the narrow lower region of the first pillar of semiconductor material; a second gate dielectric material formed along sidewalls of the wide upper region and the narrow lower region of the second pillar of semiconductor material; a first gate electrode wrapping around the wide upper region and the narrow lower region of the first pillar of semiconductor material with intervening first gate dielectric material; a second gate electrode wrapping around the wide upper region and the narrow lower region of the second pillar of semiconductor material with intervening second gate dielectric material; an insulative material between the first and second gate electrodes to isolate the first and second gate electrodes from each other; first source and drain regions within the first pillar of semiconductor material; and second source and drain regions within the second pillar of semiconductor material.