Patent ID: 9502883
Filing Date: 2016-11-22
CPC Classification: H01L,H02H

Claim Text:
1. An electrostatic discharge (ESD) protection device, comprising: a plurality of semiconductor fins extending from a substrate with a gate electrode disposed over the plurality of semiconductor fins; a source region and a drain region disposed in each of the semiconductor fins on opposite sides of the gate electrode, wherein the source region and the gate electrode are electrically coupled to one or more integrated circuit (IC) nodes having a same ground reference potential, wherein and the drain region is electrically coupled to a circuit node disposed between an I/O of the IC and core circuitry of the IC coupled to the I/O, and wherein the drain region has an uppermost surface; and a lightly doped extended drain region disposed in the semiconductor fins and spacing apart the gate electrode from the drain regions by an amount greater than a spacing between the gate electrode and the source regions, wherein the lightly doped extended drain region has an uppermost surface approximately co-planar with the uppermost surface of the drain region.