Patent ID: 9355719
Filing Date: 2016-05-31
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor device comprising: a nonvolatile memory unit that includes a plurality of memory cells; and a control circuit that allocates a physical address to a logical address input from outside to perform access to the physical address of the nonvolatile memory unit, wherein the nonvolatile memory unit includes a plurality of first signal lines, a plurality of second signal lines that intersect the plurality of first signal lines, and a plurality of memory cell groups disposed at intersections of the plurality of first signal lines and the plurality of the second signal lines, each of the plurality of memory cell groups includes first to N-th (N is an integer of 2 or greater) memory cells, and first to N-th memory cell selection lines that respectively select the first to N-th memory cells, and the control circuit writes data to a first portion that includes M (M<N) memory cells among the first to N-th memory cells according to a first write command to a first physical address, and writes data to a second portion that includes M memory cells excluding the first portion among the first to N-th memory cells according to a second write command to the first physical address generated after the first write command.