Patent ID: 9292288
Filing Date: 2016-03-22
CPC Classification: G06F

Claim Text:
1. A processing system, comprising: a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic to perform a move elimination operation by causing an element of the second data structure to reference an element of the first data structure, the move elimination logic further to track, using at least one of the third data structure and the fourth data structure, availability of elements of the first data structure.