Patent ID: 9263572
Filing Date: 2016-02-16
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first semiconductor region, which has a first conductivity type; a second semiconductor region, which has a second conductivity type and is arranged on the first semiconductor region; a third semiconductor region, which has the first conductivity type and is arranged on the second semiconductor region; a fourth semiconductor region, which has the second conductivity type and is arranged on the third semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface of the fourth semiconductor region and penetrate the fourth semiconductor region and the third semiconductor region to reach the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess, the region facing a side surface of the third semiconductor region; a first main electrode, which is electrically connected to the first semiconductor region; a second main electrode, which is electrically connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film with being separated from the control electrode on a bottom surface of the recess and is electrically connected to the second main electrode, wherein a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses, as viewed from a plan view, wherein a plurality of the recesses is formed in a lattice shape to intersect with each other, wherein pillars, which corresponds areas formed in an island shape surrounded by the recesses, are two-dimensionally arranged, as viewed from a plan view, wherein gate electrodes formed on side faces of the two adjacent pillars are connected by a bottom gate wiring, which is formed on the oxide film at a bottom surface of the recess between the two adjacent pillars, and wherein a bottom electrode separated from the control electrode and electrically connected to the first main electrode is provided on the oxide film of the bottom surface of the recess between the two adjacent bottom gate wirings.