Patent ID: 9330959
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, comprising the steps: providing a substrate comprising silicon-based single-crystal semiconductor material; forming a blocking layer comprising dielectric material over a top surface of the substrate; forming an isolation recess through the blocking layer and in the substrate; forming a buried isolation layer comprising dielectric material in the isolation recess, a top surface of the buried isolation layer being lower than the top surface of the substrate adjacent to the isolation recess; forming dielectric material on lateral surfaces of the substrate in the isolation recess above the top surface of the buried isolation layer; forming a seed trench through the buried dielectric layer which exposes the substrate; forming a single-crystal silicon-based seed layer on the substrate in the seed trench, extending above the top surface of the seed trench; forming a non-crystalline region of silicon-based semiconductor material over the top surface of the buried isolation layer and over the blocking layer, the non-crystalline region contacting the seed layer; heating the non-crystalline region by a radiant-induced recrystallization process to form a single-crystalline region over the buried isolation layer aligned with the seed layer; and recessing a top surface of the single-crystalline region.