Patent ID: 9466343
Filing Date: 2016-10-11
CPC Classification: G06F,G11C,Y02D

Claim Text:
1. A semiconductor device comprising: a command decoder configured to activate a first mode register setting signal; a mode register configured to store a mode signal; an input receiving an enable signal indicating one of a first operation mode and a second operation mode; a first circuit configured to, when the enable signal indicates the first operation mode, supply the first mode register setting signal to a latency shifter and, when the enable signal indicates the second operation mode, bypass the latency shifter and supply the first mode register setting signal to the mode register, wherein the latency shifter is configured to activate a second mode register setting signal after a predetermined from the activation of the first mode register setting signal; a second circuit configured to supply the second mode register setting signal to the mode register when the enable signal indicates the first operation mode.