Patent ID: 9449983
Filing Date: 2016-09-20
CPC Classification: H01L

Claim Text:
1. A memory block, comprising: a substrate; an array comprising at least one row of monolithic three dimensional NAND strings; a first dielectric filled trench located on a first side of the array; a second dielectric filled trench located on a second side of the array opposite to the first side of the array; a first source line located in the first dielectric filled trench; a second source line located in the second dielectric filled trench; and a plurality of drain lines located over the array; wherein: each NAND string comprises a semiconductor channel, a tunnel dielectric located adjacent to an end portion of the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region, a source side select gate electrode, a gate insulating layer, a drain side select gate electrode, and a plurality of control gate electrodes extending substantially parallel to a major surface of the substrate; the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; the source side select gate electrode, the first control gate electrode and the second control gate electrode are continuous in the array; a first portion of the gate insulating layer contacts a first side of the source side select gate electrode, a second portion of the gate insulating layer contacts a second side of the source side select gate electrode, and a third portion of the gate insulating layer contacts bottom of the source side select gate electrode; a first portion of the semiconductor channel contacts the first portion of the gate insulating layer, a second portion of the semiconductor channel contacts the second portion of the gate insulating layer, and a third portion of the semiconductor channel contacts the third portion of the gate insulating layer; the array comprises at least a 4×4 array of monolithic three dimensional NAND strings; the first portion of the semiconductor channel comprises a first semiconductor protrusion which extends perpendicular to the major surface of the substrate; the second portion of the semiconductor channel comprises a second semiconductor protrusion which extends perpendicular to the major surface of the substrate; the third portion of the semiconductor channel comprises a semiconductor portion of the substrate or a semiconductor layer extending parallel to the major surface of the substrate under the control gate electrode; the substrate comprises a single crystal silicon substrate; the end portion of the semiconductor channel, the tunnel dielectric, the charge storage region and the blocking dielectric extend through the first and through the second device levels; the end portion of the semiconductor channel comprises a semiconductor pillar or hollow cylinder which extends perpendicular to the major surface of the substrate; the first semiconductor protrusion comprises an epitaxial silicon rail having straight, inverse tapered or tapered sidewalls; the second semiconductor protrusion comprises an epitaxial silicon pillar having a cylindrical, truncated cone or inverse truncated cone shape having a smaller width than the first semiconductor protrusion; the third portion of the semiconductor channel comprises an upper portion of the semiconductor substrate which connects the first semiconductor protrusion to the second semiconductor protrusion; the plurality of drain lines extend in a bit line direction from the first dielectric filled trench to the second dielectric filled trench; the source side select gate electrode, the first control gate electrode, and the second control gate electrode extend in a word line direction which is perpendicular to the bit line direction; the array comprises first, second, third and fourth rows of NAND strings extending in the word line direction; and the semiconductor channels in the first and the third rows of NAND strings are offset from respective semiconductor channels in the second and fourth rows of NAND strings.