Patent ID: 9471487
Filing Date: 2016-10-18
CPC Classification: G06F

Claim Text:
1. An electronic device comprising: a nonvolatile memory; a volatile memory having a first region where data that does not have to be restored is stored, a second region where restoration data that should be stored even when power supply to a self device is shut off is stored, a first flag region where a first flag is set correspondingly to the second region, a third region where the restoration data to be delayed and written into the nonvolatile memory is stored, a second flag region where a second flag is set correspondingly to the third region, and a timer region for counting a time; a processor that includes: the first writing section sets the first flag in the first flag region corresponding to the second region where the restoration data is written, when the first flag is set in the first flag region, the second writing section writes the restoration data stored in the second region corresponding to the first flag region into the nonvolatile memory, and the first writing section sets the second flag in the second flag region corresponding to the third region where the restoration data is written and starts time counting in the timer region, when the time counting in the timer region continues for over a predetermined time after the second flag is set in the second flag region, the second writing section writes the restoration data stored in the third region corresponding to the second flag region into the nonvolatile memory.