Patent ID: 9503062
Filing Date: 2016-11-22
CPC Classification: H03K

Claim Text:
1. A flip-flop comprising: a first inverter configured to invert first data; first and second transistors connected to each other in series and configured to receive the inverted first data and a first clock, respectively; a first gate configured to perform a logic operation on the first data and the first clock; a third transistor configured to receive an output of the first gate, the second transistor and the third transistor being connected to a first node; and a clock generating unit configured to receive a reference clock and generate the first clock and a second clock, wherein the second clock includes first and second sub-clocks, the second sub-clock is an inversion of the first sub-clock and the clock generating unit is configured to generate the first sub-clock by performing a NAND logic operation on the reference clock and the first clock.