Patent ID: 9245621
Filing Date: 2016-01-26
CPC Classification: G11C

Claim Text:
1. A semiconductor memory device, comprising: a memory cell array including plural first lines, plural second lines intersecting said first lines, and plural memory cells provided at the intersections of said plural first lines and said plural second lines and operative to store data in accordance with different resistance states; and a write circuit operative to execute a write operation to a data-write-targeted, selected memory cell of said plural memory cells, said memory cell having a set operation for changing said resistance state from the first resistance state to the second resistance state on application of a set voltage of the first polarity, and a reset operation for changing said resistance state from the second resistance state to the first resistance state on application of a reset voltage of the second polarity opposite in polarity to the first polarity, and having the voltage-current characteristic at said first polarity and the voltage-current characteristic at said second polarity being asymmetrical, said write circuit, on execution of said write operation, executing a first operation of applying a voltage across said first and second lines connected to said selected memory cell, and a different voltage across said first and second lines connected to another memory cell, and after execution of said first operation, executing a second operation of applying a voltage, required for data write, across said first and second lines connected to said selected memory cell, and bringing at least one of said first and second lines connected to the other memory cell into the floating state, and potentials on said first and second lines connected to said selected memory cell and potentials on said first and second lines connected to the other memory cell in said first operation being different from potentials on said first and second lines connected to said selected memory cell in said second operation.