Patent ID: 9335933
Filing Date: 2016-05-10
CPC Classification: G06F,H04L

Claim Text:
1. An apparatus comprising: a data receiver to receive a data signal; a clock/strobe receiver to receive a clock/strobe signal; a data signal tap/register to capture, in response to an identified data transition in the data signal, a first and a second bit values of the data signal prior to the identified data transition; a floating data signal tap/register to capture, in response to the identified data transition in the data signal, a combination of bit values prior to the first and second bit values, wherein the first and second bit values include two bits of the data signal immediately prior to the identified data transition; and an equalization circuit to delay reception of at least one of the data signal or the clock/strobe signal at a time of the data transition based, at least in part, on the first and second bit values and the identified data transition.