Patent ID: 9437263
Filing Date: 2016-09-06
CPC Classification: G06F,G11C

Claim Text:
1. An apparatus comprising: a memory controller configured to produce first and second timing strobe signals; a first memory configured to receive the first timing strobe signal and produce a first return strobe signal in response, at least in part, to the first timing strobe signal, the first memory being further configured to provide first read data; and a second memory configured to receive the second timing strobe signal and produce a second return strobe signal in response, at least in part, to the second timing strobe signal, the second memory being further configured to provide second read data; the memory controller being further configured to capture the first read data in response, at least in part, to the first return strobe signal and the second read data in response, at least in part, to the second return strobe signal.