Patent ID: 9483069
Filing Date: 2016-11-01
CPC Classification: G05F,H03K

Claim Text:
1. A circuit for generating a bias current, comprising: a loop unit that includes a first current mirror structure constituted by a first P-channel metal oxide semiconductor (PMOS) transistor and a second PMOS transistor, a second current mirror structure constituted by a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, and a resistor unit, a first terminal of the resistor unit being connected with a source of the first NMOS transistor, a second terminal of the resistor unit being grounded, and a resistance of the resistor unit being positively related to a temperature factor, a drain of the first PMOS transistor being connected with a drain of the first NMOS transistor, a first current being output from the drain of the first PMOS transistor, a gate of the first PMOS transistor being connected with a gate of the second PMOS transistor, and sources of both the first and the second PMOS transistors being connected to a power-supply voltage, a drain of the second PMOS transistor being connected with a drain of the second NMOS transistor and a second current being output from the drain of the second PMOS transistor, a gate of the first NMOS transistor being electrically connected with the drain of the first NMOS transistor and a gate of the second NMOS transistor, and a source of the second NMOS transistor being grounded, the first and second NMOS transistors operating in a sub-threshold region, an output unit adapted to output the bias current that is proportional to the first current and proportional to the second current, and an amplifying unit that includes a first input terminal and an output terminal, wherein the first input terminal is connected with the source of the first NMOS transistor, and the output terminal is connected with the gates of both the first and the second PMOS transistors.