Patent ID: 9389867
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. A method of data processing, comprising: tracking high latency operations of a processor core in entries of a data structure associated with an execution unit of a processor core; in the execution unit, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishing execution of an instruction dependent on the high latency operation, wherein the speculatively finishing includes reporting an identifier of the entry to completion logic of the processor core and freeing a resource in an execution pipeline of the execution unit utilized by the instruction; the completion logic recording a dependence of the instruction on the high latency operation and committing an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation; and in response to unsuccessful completion of the high latency operation: