Patent ID: 9466089
Filing Date: 2016-10-11
CPC Classification: G06F,G06T,G09G,H04N

Claim Text:
1. A signal processor for combining a video frame and a graphics frame in an image remote system, comprising: a host processor for generating a plurality of graphics commands based on graphics encoded data from a network and setting a video flag to active based on video encoded data and mask encoded data from the network; a command queue for sequentially receiving and sending the graphics commands and asserting a control signal according to the graphics commands; a graphics decoding circuit for decoding the graphics encoded data according to the graphics commands and generating the graphics frame, a current surface mask and a previous surface mask; a video decoding circuit coupled to the host processor for determining whether to decode the video encoded data and the mask encoded data according to the video flag to generate the video frame and a video mask; a composition engine for transferring at least one of the graphics frame, the video frame and a content of one of two display buffers to the other display buffer according to the video mask and the two surface masks when the control signal is asserted or when the video flag is active; and the two display buffers for forming a reconstructed image according to at least one of the graphics frame, the video frame and the content of the one of two display buffers to be outputted to a display device; wherein the host processor sets the video flag to active by respectively setting a first register of the composition engine, a second register and a third register of the video decoding circuit to a first preset value, a second preset value and a third preset value through its address bus.