Patent ID: 9514838
Filing Date: 2016-12-06
CPC Classification: G06F,G11C,Y02D

Claim Text:
1. An apparatus, comprising: a switch; non-volatile memory control circuitry coupled to the switch and including a plurality of channel control circuits, wherein each of the plurality of channel control circuits is configured to be coupled to a number of logical units (LUNs), wherein each of the number of LUNs includes a plurality of blocks; volatile memory coupled to the switch; and memory management circuitry coupled to the switch and including local memory, wherein the memory management circuitry is configured to: store logical to physical address translations in a logical block address (LBA) table in the volatile memory; retrieve a first physical address corresponding to a logical address for a particular block of the plurality of blocks from the block table prior to information being read from the particular block during a wear leveling operation on the particular block; retrieve a second physical address corresponding to the logical address from the LBA table after the information is written to a different one of the plurality of blocks during the wear leveling operation; and update the LBA table with a third physical address corresponding to the different one of the plurality of blocks to which the information is written during the wear leveling operation at least partially in response to the second physical address being equal to the first physical address.