Patent ID: 9257978
Filing Date: 2016-02-09
CPC Classification: G09G,H03K

Claim Text:
1. A multiplex driving circuit receiving m master signals and n slave signals, the multiplex driving circuit comprising m driving modules for generating m×n gate driving signals, wherein each driving module comprises: a voltage boost stage for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage; and n driving stages for respectively receiving the n slave signals and receiving the first high voltage signal, wherein in response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals; wherein a time duration of the high logic level of each master signal is equal to a cycle period of each slave signal, a duty cycle of each slave signal is equal to 1/n, and a phase difference between every two adjacent slave signals is equal to 360/n degrees.