Patent ID: 9466356
Filing Date: 2016-10-11
CPC Classification: G11C

Claim Text:
1. An integrated circuit comprising a solid state memory, the memory comprising: an array of solid-state memory cells arranged in rows and columns, each row of the memory cells connected to a word line, each column of the memory cells connected to a bit line, each memory cell comprising: a first pass transistor having a source/drain path connected between the first storage node and a first bit line associated with a column of memory cells containing the memory cell, and having a gate connected to a word line associated with a row of memory cells containing the memory cell; a power supply conductor extending over the array and connected to the array power supply node of each of a first plurality of memory cells; a first ground conductor extending over the array and connected to the first array ground node of each of the first plurality of memory cells, the first ground conductor also connected to a first array ground node of each of a second column of memory cells adjacent in the array to the first plurality of memory cells; a second ground conductor extending over the array and connected to the second array ground node of each of the first plurality of memory cells; and peripheral circuitry, coupled to the word lines and bit lines, for selecting one or more cells in the array for read and write access during normal memory operation.