Patent ID: 9362953
Filing Date: 2016-06-07
CPC Classification: G06F,H03M

Claim Text:
1. A circuitry SK for an error correction of at least 1-bit, 2-bit, and 3-bit errors of bits in an n-digit binary word v′=v′ 1 , . . . , v′ n which resulted from bit errors from an n-digit codeword v=v 1 , . . . , v n of a binary BCH code C over the Galois field GF(2 m ), wherein m≧4, wherein the binary BCH code C comprises a code distance of at least d≧7, wherein the BCH code C comprises an H matrix H, so that m first rows of the H matrix form a submatrix H 1 , m second rows of the H matrix form a second submatrix H 3 and further m rows of the H matrix form a third submatrix H 5 with wherein applies, α is an element of the Galois field GF (2 m ) in its vector representation as an m-component binary column vector and the respective exponent j of α j is to be interpreted modulo 2 m −1, with i=1, . . . n, and n≦2 m −1 applies, comprising: a syndrome generator Synd configured to determine an error syndrome s, wherein m first components of s form an m-component subsyndrome s apply, wherein the operation · is the operation of the multiplication in the Galois field GF(2 m ), a plurality of subcircuits wherein for each bit v wherein v is the OR-operation, wherein wherein the operation + is the addition of the corresponding elements in the Galois field GF(2 m ) which, in the vector representation, corresponds to the component-wise XOR-combination of the corresponding m-component binary vectors, and the intermediate values Zw wherein for determining the intermediate values Zw a combinational circuit Vkn configured to combine bits that are subject to possible error correction v′