Patent ID: 9379110
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming on a structure comprising a pad layer covering a surface of an nFET region, a pFET region, and a shallow trench isolation (STI) region a plurality of nFET region sacrificial mandrels on the surface of the pad layer in the nFET region and a plurality of pFET region sacrificial mandrels on the surface of the pad layer in the pFET region, wherein the nFET region contains an unstrained semiconductor material and the pFET region comprises a strained semiconductor material; depositing a conformal spacer material film on the surface of the plurality of nFET region sacrificial mandrels, plurality of pFET region sacrificial mandrels, and exposed pad layer; etching to selectively remove conformal spacer material, exposed pad layer, strained semiconductor material, and unstrained semiconductor material layer; and removing remaining conformal spacer material film, the plurality of nFET and pFET sacrificial mandrels, and remaining pad layer to result in a complimentary structure, wherein the complimentary structure comprises the nFET region comprising a solid region of unstrained semiconductor material, and the pFET region comprising a plurality of parallel strained semiconductor material stripes separated by gaps.