Patent ID: 9442734
Filing Date: 2016-09-13
CPC Classification: G06F

Claim Text:
1. A processor comprising: an issue circuit coupled to receive a vector memory operation to be executed in the processor, wherein the vector memory operation is generated from a vector instruction to be executed by the processor, and wherein the vector instruction is defined to operate on vector operands, wherein each vector operand comprises a plurality of vector elements, wherein the vector instruction is defined to perform a same operation on the plurality of vector elements in parallel, and wherein the issue circuit is configured to issue the vector memory operation responsive to dependencies on source operands resolving for the vector memory operation; and a completion time determination circuit coupled to receive the source operands of the vector memory operation in response to issuance of the vector memory operation, wherein the completion time determination circuit is configured to determine, responsive to the source operands, a time at which the vector memory operation will complete, wherein the time of completion of a given vector memory operation varies dependent on a location in memory of each element of the plurality of vector elements; wherein the issue circuit is coupled to the completion time determination circuit to receive an indication of the time, wherein the issue circuit is configured to schedule one or more operations that are dependent on the vector memory operation responsive to the indication of the time determined by the completion time determination circuit.