Patent ID: 9373275
Filing Date: 2016-06-21
CPC Classification: G09G,H03K

Claim Text:
1. A level shifter, applied in a driving circuit of a display, for converting an input voltage signal with low voltage level into an output voltage signal with high voltage level, the level shifter comprising: a first stage of level shifting unit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are N-type MOSFETs; the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type MOSFETs; the first transistor, the third transistor, the fifth transistor, and the seventh transistor are coupled in series between a ground terminal and an operational voltage; the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are coupled in series between the ground terminal and the operational voltage; gates of the first transistor and the second transistor are coupled to the input voltage signal; gates of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor are coupled to a half operational voltage which is half of the operational voltage; a gate of the seventh transistor is coupled to a first node between the sixth transistor and the eighth transistor; a gate of the eighth transistor is coupled to a second node between the fifth transistor and the seventh transistor; a second stage of level shifting unit comprising a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein the second stage of level shifting unit is coupled to the first stage of level shifting unit; the ninth transistor and the tenth transistor are N-type MOSFETs; the eleventh transistor and the twelfth transistor are P-type MOSFETs; the ninth transistor and the eleventh transistor are coupled in series between the half operational voltage and the operational voltage; the tenth transistor and the twelfth transistor are coupled in series between the half operational voltage and the operational voltage; a gate of the ninth transistor is coupled to a first output terminal between the tenth transistor and the twelfth transistor; a gate of the tenth transistor is coupled to a second output terminal between the ninth transistor and the eleventh transistor; a gate of the eleventh transistor is coupled to the first node; a gate of the twelfth transistor is coupled to the second node; the second stage of level shifting unit outputs the output voltage signal via the first output terminal and the second output terminal; and another second stage of level shifting unit comprising a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, wherein the another second stage of level shifting unit is coupled to the first stage of level shifting unit; the thirteenth transistor and the fourteenth transistor are N-type MOSFETs; the fifteenth transistor and the sixteenth transistor are P-type MOSFETs; the thirteenth transistor and the fifteenth transistor are coupled in series between the ground terminal and the half operational voltage; the fourteenth transistor and the sixteenth transistor are coupled in series between the ground terminal and the half operational voltage; a gate of the thirteenth transistor is coupled between the first transistor and the third transistor; a gate of the fourteenth transistor is coupled between the second transistor and the fourth transistor; a gate of the fifteenth transistor is coupled to a third output terminal between the fourteenth transistor and the sixteenth transistor; a gate of the sixteenth transistor is coupled to a fourth output terminal between the thirteenth transistor and the fifteenth transistor; a gate of the twelfth transistor is coupled to the second node; the another second stage of level shifting unit outputs another output voltage signal via the third output terminal and the fourth output terminal.