Patent ID: 9502270
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A package for a semiconductor device, comprising: an integrated circuit die mounting region; a molding material disposed around the integrated circuit die mounting region; an insulating layer over the integrated circuit die mounting region and the molding material, the insulating layer having a bottom surface and a top surface, the bottom surface adjacent to the integrated circuit die mounting region and the molding material; an interconnect structure disposed in the insulating layer, the interconnect structure configured to provide electrical connections extending between the top and bottom surface of the insulating layer; and a protection pattern disposed in a perimeter region of the package, the perimeter region being adjacent to the interconnect structure, wherein the protection pattern comprises conductive features separate from the interconnect structure, wherein the conductive features are electrically isolated from the interconnect structure, and wherein a topmost surface of the conductive features is below the top surface of the insulating layer.