Patent ID: 9472466
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: forming an NMOS transistor structure and a PMOS transistor structure with an isolation layer therebetween, the isolation layer disposed in a semiconductor substrate, each transistor structure including source/drain regions in the semiconductor substrate and a gate electrode; forming a tensile stress layer on the NMOS transistor structure; forming a compressive stress layer on the PMOS transistor structure; and providing a buffer layer under the compressive stress layer after forming the tensile stress layer, the buffer layer confined to an undersurface of the compressive stress layer, wherein a portion of the compressive stress layer overlaps a portion of the tensile stress layer above the isolation layer, the tensile stress layer directly contacting the isolation layer, and a bottom surface of the tensile stress layer on the isolation layer and a bottom surface of the compressive stress layer on the isolation layer are located at different vertical levels.