Patent ID: 9275726
Filing Date: 2016-03-01
CPC Classification: G11C

Claim Text:
1. A static memory cell comprising: a data latch circuit configured to store a bit data, the data latch circuit comprising a first inverter and a second inverter coupled to each other, the first inverter and the second inverter respectively receiving a first voltage and a second voltage as power voltages; and a voltage provider coupled to the data latch circuit to provide the first voltage and the second voltage to the data latch circuit, wherein when the bit data is written into the data latch circuit, the voltage provider adjusts a voltage value of the first voltage or a voltage value of the second voltage according to the bit data, wherein the voltage provider comprises: a first tri-state inverter, an output end of the first tri-state inverter being coupled to an input end of the first tri-state inverter, such that the output end of the first tri-state inverter being coupled to a first output end, and the first output end providing the first voltage to the first inverter; and a second tri-state inverter, an output end of the second tri-state inverter being coupled to an input end of the second tri-state inverter, such that the output end of the second tri-state inverter being coupled to a second output end, and the second output end providing the second voltage to the second inverter, wherein when the bit data is written into the data latch circuit, one of the first tri-state inverter and the second tri-state inverter is enabled according to the bit data.