Patent ID: 9483428
Filing Date: 2016-11-01
CPC Classification: G06F

Claim Text:
1. A storage apparatus, comprising an interleaved bus, N memory groups, and K direct-connect bus groups, wherein K is less than or equal to N, and N and K are both integers; wherein the interleaved bus comprises M master interfaces and S slave interfaces, wherein each master interface among the M master interfaces is configured to receive continuous-addresses access operations, M is less than or equal to S, and M and S are both integers; each memory group among the N memory groups comprises S memories respectively connected to the S slave interfaces, wherein addresses of the S memories in each of the memory groups are continuous, a difference between addresses of two storage units of any one memory among the S memories in each of the memory groups is an integral multiple of S, and the interleaved bus is configured to decode the continuous-addresses access operations, and send the continuous-addresses access operations to at least one memory group among the N memory groups; and each direct-connect bus group among the K direct-connect bus groups is connected to at least one memory group among the N memory groups, wherein one end of each direct-connect bus in each of the direct-connect bus groups is used to receive discrete-addresses access operations, the other end of each direct-connect bus is connected to a respective corresponding memory in the at least one memory group, memory groups connected to different direct-connect bus groups are different, and each direct-connect bus group among the K direct-connect bus groups is configured to send the discrete-addresses access operations to at least one memory group among the N memory groups.