Patent ID: 9424910
Filing Date: 2016-08-23
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising a first memory module and a second memory module, each provided with a power supply voltage and a ground voltage, wherein the first memory module includes: a plurality of first word lines extending in parallel in a first direction; a plurality of first bit lines extending in parallel in a second direction crossing the first direction; and a plurality of first SRAM memory cells coupled to the first word lines and the first bit lines, wherein the second memory module includes: a plurality of second word lines extending in parallel in a third direction; a plurality of second bit lines extending in parallel in a fourth direction crossing the third direction; and a plurality of second SRAM memory cells coupled to the second word lines and the second bit lines, wherein the first memory module further includes: a plurality of first memory cell power supply lines extending in parallel in the second direction to supply power to the first SRAM memory cells; and a first write assist circuit for converging a voltage level of the first memory cell power supply line corresponding to a first SRAM memory cell to be written in the write operation to a first level between the power supply voltage and the ground voltage, wherein the second memory module further includes: a plurality of second memory cell power supply lines extending in parallel in the fourth direction to supply power to the second SRAM memory cells; and a second write assist circuit for converging a voltage level of the second memory cell power supply line corresponding to a second SRAM memory cell to be written in the write operation to a second level between the power supply voltage and the ground voltage, and wherein the number of the first word lines is greater than the number of the second word lines.