Patent ID: 9390814
Filing Date: 2016-07-12
CPC Classification: G01R,G11C

Claim Text:
1. A circuit to detect faults in one or more arrays of data storage elements, the circuit comprising: a resistor network comprising two or more resistors; a switching network for selectively coupling a respective portion of the resistor network to a first array of data storage elements, and the switching network is further operable to couple the respective portion of the resistor network to a second array of data storage elements; a current monitoring module connected to the resistor network, wherein the current monitoring module is operable to monitor current flow through the respective portion of the resistor network during performance of a respective operation on the first array of data storage elements, wherein the respective operations is a host-initiated memory read operation, host-initiated write operation, or data erase operation; and a control module coupled to the switching network and the current monitoring module;