Patent ID: 9299790
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A silicon carbide semiconductor device having a plane layout including a central portion and an outer edge portion that surrounds said central portion and that constitutes an outer edge, the silicon carbide semiconductor device comprising: a silicon carbide film having a first main surface and a second main surface opposite to said first main surface in a thickness direction, said silicon carbide film having a first range that constitutes said first main surface and a second range that constitutes said second main surface, said first and second ranges having an interface separated from said first and second main surfaces between said first and second ranges, said first range including a first breakdown voltage holding layer and an outer edge embedded region, said first breakdown voltage holding layer constituting said first main surface and having a first conductivity type, said outer edge embedded region being provided partially at said interface in said outer edge portion and having said second conductivity type, said second range including a second breakdown voltage holding layer that constitutes said interface and that has said first conductivity type, said first and second breakdown voltage holding layers constituting a breakdown voltage holding region in which said outer edge embedded region is embedded, said second range being provided with a semiconductor element for controlling current from one of said second main surface and said interface to the other, said first range having a central section and an outer edge section, said central section facing said semiconductor element in said central portion in the thickness direction, said outer edge section facing said semiconductor element in said outer edge portion in the thickness direction, said outer edge section including a portion that has an impurity concentration different from an impurity concentration of said central section by having at least a portion of said outer edge embedded region at said interface, the impurity contributing to said second conductivity type; a first electrode facing said first main surface in each of said central portion and said outer edge portion; and a second electrode in contact with said second main surface in each of said central portion and said outer edge portion.