Patent ID: 9324385
Filing Date: 2016-04-26
CPC Classification: G11C

Claim Text:
1. A semiconductor device comprising: an initialization information signal generator configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data; a domain crossing unit including a plurality of pipe latches configured to receive the first initialization information in response to the first clock and output the first initialization information as second initialization information by outputting the second initialization information in response to a second clock; and a pulse generation unit including a plurality of flip-flops configured to operate in response to the second clock and adjust a toggling point in time of a control pulse in response to the second initialization information wherein the first clock is a clock obtained by delaying an external system clock by an internal setting operation, and the second clock is an internal clock set to have an edge synchronized with the external system clock, wherein the initialization information signal generator is configured to perform a plurality of operations on the address signal in synchronization with the first clock and generate the first initialization information.