Patent ID: 9312285
Filing Date: 2016-04-12
CPC Classification: G02F,H01L

Claim Text:
1. A thin film transistor array panel comprising: a substrate; a gate line disposed on the substrate; a signal line disposed adjacent to an end part of the gate line; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; an insulating layer covering the thin film transistor; a first electrode disposed on the insulating layer; a passivation layer disposed on the first electrode; and a second electrode disposed on the passivation layer and connected to the thin film transistor, wherein the passivation layer is between the second electrode and the substrate, wherein the first electrode overlaps the second electrode, wherein the first electrode overlaps the gate line and the data line, and is connected to the signal line at an edge portion of the thin film transistor array panel, wherein the signal line is disposed at a same layer as the gate line, and wherein the second electrode is disposed at a different layer than the signal line.