Patent ID: 9490020
Filing Date: 2016-11-08
CPC Classification: G11C

Claim Text:
1. A non-volatile memory circuit, comprising: a string of a plurality of serially connected non-volatile programmable threshold transistors formed on a common channel structure; and driver circuitry connectable to the channel structure and connectable to a corresponding control gate of each of the programmable threshold transistors of the string, wherein, in response to an erase command selecting one or more, but less than all, of the programmable threshold transistors of the string to be erased, the driver circuitry applies to the common channel structure a voltage that ramps up to an erase level and, for each of one or more programmable threshold transistors of the string not selected to be erased, applies an erase inhibit voltage to a control gate thereof that, after a corresponding delay, ramps up with the voltage applied to the channel structure, and wherein for each of the programmable threshold transistors of the string not selected to be erased, a duration of the delay is dependent upon a location of the corresponding programmable threshold transistors not selected to be erased within the string.