Patent ID: 9355726
Filing Date: 2016-05-31
CPC Classification: G11C

Claim Text:
1. An EPROM cell array comprising: a cell array including multiple unit cells, each of which consists of a p-channel MOSFET having a P+ drain, a P+ source, a channel region between the P+ drain and P+ source, and a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns; multiple first selection lines each coupled with P+ drains of unit cells, which are disposed on the same row among the multiple unit cells; and multiple second selection lines each coupled with P+ sources of unit cells, which are disposed on the same column among the unit cells, wherein a selected unit cell is programmed by applying a program voltage and a ground voltage to a first selection line and a second selection line to be coupled with the selected unit cell, respectively, or by applying a program voltage and a ground voltage to the second selection line and the first selection line to be coupled with the selected unit cell, respectively.