Patent ID: 9281310
Filing Date: 2016-03-08
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: forming an NMOS region and a PMOS region in a substrate; forming a gate dielectric layer over the substrate; forming a first work function layer that contains aluminum over the gate dielectric layer; forming a reaction preventing layer consisting of polysilicon over the first work function layer; selectively removing the reaction preventing layer and the first work function layer from the NMOS region; forming a threshold voltage modulation layer that contains lanthanum over the remaining reaction preventing layer of the PMOS region and the gate dielectric layer of the NMOS region; forming a second work function layer over the threshold voltage modulation layer; and annealing, thereby forming a first dipole-interface by diffusion of the aluminum into the gate dielectric layer of the PMOS region and a second dipole-interface by diffusion of the lanthanum into the gate dielectric layer of the NMOS region, respectively, wherein the remaining reaction preventing layer is formed between the first work function layer and the threshold voltage modulation layer over the PMOS region.