Patent ID: 9244648
Filing Date: 2016-01-26
CPC Classification: G06F,G06T,G09G,H04N

Claim Text:
1. A video image synchronous transmission and display method in a multi-processor video processing system, wherein the system includes multiple processors which are connected via a PCIE bus, each processor comprises one or more display units and one or more decoding units, each display unit respectively comprises a corresponding group of memory area, each group of memory area comprises two buffers, a read information packet and a write information packet, the read information packet contains a read flag, the write information packet contains a write flag; each decoding unit corresponds to one or more display units; the read information packet corresponding to the display unit is read-only for the decoding unit, and the write information packet corresponding to the display unit can be read and written by the decoding unit; the method includes the following steps: the decoding unit generating a frame of uncompressed image and respectively performing the following steps on each display unit corresponding to the decoding unit: if the read and write flags corresponding to the display unit are equal, sending the image belonging to the display unit to an idle buffer indicated by the write flag by calling the PCIE bus or using local transmission inside the processor, and negating the write flag, otherwise waiting until the read flag is equal with the write flag; each display unit querying for corresponding read and write flags according to a display refresh frequency, if the read flag is not equal with the write flag, using the buffer indicated by the read flag as a storage area for source data to be displayed next time, and setting the read flag to the same value with the write flag.