Patent ID: 9412600
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method, comprising: providing a semiconductor structure comprising a logic transistor region, a ferroelectric transistor region and an input/output transistor region; forming a first protection layer over said semiconductor structure, said first protection layer covering said logic transistor region and said input/output transistor region, at least a portion of said ferroelectric transistor region not being covered by said first protection layer; after forming said first protection layer, forming a recess in said ferroelectric transistor region by performing an etch process adapted to remove a semiconductor material of said ferroelectric transistor region; after said etch process, performing an oxidation process adapted to oxidize said semiconductor material of said ferroelectric transistor region and performing a wet etch adapted to remove an oxide formed in said oxidation process; and depositing a ferroelectric transistor dielectric over said semiconductor structure, wherein a portion of said ferroelectric transistor dielectric is deposited in said recess, removing said ferroelectric transistor dielectric and said first protection layer from said logic transistor region and said input/output transistor region, forming an input/output transistor dielectric over said input/output transistor region, and forming a logic transistor dielectric over at least said logic transistor region.