Patent ID: 9336894
Filing Date: 2016-05-10
CPC Classification: G11C

Claim Text:
1. A memory device including nonvolatile memory cells, each of which comprises: an active pattern including first to fourth regions successively arranged in one direction; a first gate structure crossing the active pattern on the second region and including a first gate electrode and a first insulating layer; and a second gate structure crossing the active pattern on the fourth region and including a second gate electrode and a second insulating layer, wherein the nonvolatile memory cell is configured such that: a first voltage is applied to the second gate electrode when the second insulating layer is in a first state such that a current that passes through the second region becomes a first current, the first voltage is applied to the second gate electrode when the second insulating layer is in a second state such that a current that passes through the second region becomes a second current, the first voltage is applied to the second gate electrode when the second insulating layer is in a third state such that a current that passes through the second region becomes a third current, the second current and the third current are higher than the first current, and the second current is different from the third current.