Patent ID: 9230687
Filing Date: 2016-01-05
CPC Classification: G06F,G11C

Claim Text:
1. A method for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system comprising: responsive to detecting a fail when reading from memory, determining if incorrect data is in the data or the ECC component of the data; responsive to the incorrect data being detected in the data or the ECC component of the data, checking for a predefined actionable threshold being reached, responsive to said predefined actionable threshold not being reached, performing a predetermined Reliability, Availability, and Serviceability (RAS) action; responsive to said predefined actionable threshold being reached and identifying the incorrect data being detected in the ECC component of the data, performing an analysis process to identify faulty ECC logic; and responsive to a fail being detected in the ECC logic, halting mainline traffic to prevent collisions, and replacing the identified ECC failed logic with a spare block of logic.