Patent ID: 9466572
Filing Date: 2016-10-11
CPC Classification: B81B,H01L

Claim Text:
1. A method of fabricating an integrated circuit including a non-volatile memory cell comprised of a floating-gate transistor at which carriers can be trapped to define a stored data state, and from which trapped carriers release upon exposure to energy of an ultraviolet wavelength, the method comprising the steps of: forming a conductive element near a surface of a semiconducting body, the conductive element disposed around a memory cell region; forming portions of the non-volatile memory cell region within the memory cell region; disposing an insulating layer over the conductive element; forming contact openings through the insulating layer to expose locations of the conductive element, the contact openings having a width ranging from about one-half of the ultraviolet wavelength to about two times the ultraviolet wavelength, and wherein adjacent ones of the contact openings are spaced apart from one another by a distance ranging from about one-half of the ultraviolet wavelength to about two times the ultraviolet wavelength; filling the contact openings with an opaque conductive material; performing a chemical-mechanical polishing; and after the step of performing a chemical-mechanical polishing, forming a roof structure of an opaque material to overlie the memory cell region.