Patent ID: 9367464
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A semiconductor chip comprising: a cache comprising a tag array and a data array; a request queue to store a plurality of cache requests to access the cache; a data request queue to store a data request to access the data array of the cache; a dataless request queue to store a dataless request to access the tag array of the cache; allocation logic circuitry to determine a cache request is to be serviced from the request queue when both of the data request queue and the dataless request queue have a slot for a next request; classification logic circuitry to receive the cache request from the allocation logic circuitry and determine whether the cache request is a data request or a dataless request, and place said cache request in said data request queue if said cache request is a data request and place said cache request in said dataless request queue if said cache request is a dataless request; and servicing logic to issue data requests from the data request queue to the data array and dataless requests from the dataless request queue to the tag array.