Patent ID: 9424914
Filing Date: 2016-08-23
CPC Classification: G11C

Claim Text:
1. A resistive memory cell, comprising: a first transistor having a first terminal, a second terminal and a control terminal, the first terminal and the second terminal of the first transistor being respectively coupled to a first bit line and a reference voltage, and the control terminal of the first transistor receiving a word line signal; a second transistor having a first terminal, a second terminal and a control terminal, the first terminal and the second terminal of the second transistor being respectively coupled to a second bit line and the reference voltage, and the control terminal of the second transistor receiving the word line signal; a first resistor serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage; and a second resistor serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage, wherein when the resistive memory cell is selected for reading, the first and the second transistors are turned on according to the word line signal, and impedance states of the first resistor and the second resistor are provided through the first bit line and the second bit line respectively, wherein the impedance states of the first resistor and the second resistor indicate a storing data stored by the resistive memory cell.