Patent ID: 9330964
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor structure, comprising: providing a substrate; forming a to-be-etched layer made of a porous low-K dielectric material including boron nitride on one surface of the substrate; forming a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) directly on the to-be-etched layer; etching the first hard mask layer to have same patterns corresponding to positions of subsequently formed a plurality of openings; forming the plurality of openings through an entire thickness of the to-be-etched layer using the first hard mask layer as an etching; etching and cleaning a bottom surface of the openings along with side surfaces of both the to-be-etched layer and the first hard mask layer in the openings by a wet chemical cleaning process, to level the side surfaces of both the to-be-etched layer and the first hard mask layer with each other in the openings, wherein an etching rate of a solution of the wet chemical cleaning process to the first hard mask layer and an etching rate of the solution of the wet chemical cleaning process to the to-be-etched layer is identical; and after the wet chemical cleaning process, forming a conductive structure in each of the openings.