Patent ID: 9460798
Filing Date: 2016-10-04
CPC Classification: G11C,H01L

Claim Text:
1. A non-volatile memory on a semiconductor substrate, comprising: bit lines, first memory cells of a first type each including a single floating-gate transistor, the floating-gate transistor of each of the first memory cells including a drain region electrically coupled to a first bit line of the bit lines, second memory cells of the first type each including a single floating-gate transistor, the floating-gate transistor of each of the second memory cells including a drain region electrically coupled to a second bit line of the bit lines, and memory cells of a second type each including: the floating gate of the first floating-gate transistor is electrically coupled to the floating gate of the second floating-gate transistor, and the second floating-gate transistor comprises a tunnel dielectric layer and a permanently conductive region extending on an opposite side of the tunnel dielectric layer with respect to the floating gate of the second floating-gate transistor.