Patent ID: 9400652
Filing Date: 2016-07-26
CPC Classification: G06F

Claim Text:
1. A processor system vector address translation apparatus comprising: an instruction register receiving, in a processor from a program memory coupled to the processor, a first vector instruction that is identified to specify a vector register file indexing (RFI) operation, the first received vector RFI instruction encoded to identify a first memory address and control information that includes a specification for a sequence of memory addresses; a vector update unit enabled to generate on a vector update unit output a sequence of memory addresses following the first memory address based on the specification for the sequence of memory addresses, wherein a plurality of vector RFI instructions are subsequently received sequentially from the instruction register for which the processor vector update unit generates, for each subsequently received vector RFI instruction, a subsequent memory address in the sequence of memory addresses; a processor multiplexer enabled to select the first memory address for the first received vector RFI instruction from a first input of the processor multiplexer coupled to the instruction register and enabled to select the sequence of memory addresses for the plurality of subsequently received vector RFI instructions from a second input of the processor multiplexer coupled to the vector update unit output, an output of the processor multiplexer producing a sequence of vector addresses beginning with the first memory address; and a data memory device coupled to the processor for read operations by a k-bit read address port coupled to the output of the processor multiplexer, a load translation parameter port, and a read data port, the data memory device having an internal translation parameter storage element previously loaded by the processor with a first translation parameter, the data memory device comprising: