Patent ID: 9343404
Filing Date: 2016-05-17
CPC Classification: G11C,H01L

Claim Text:
1. An anti-fuse for a semiconductor device, the anti-fuse comprising: a plurality of active pillars arranged in a zigzag pattern when viewed in a plan view and including first to fourth active pillars, the first to fourth active pillars including respective junctions at their upper portions, the second active pillar being diagonally contiguous to the first active pillar; a first selection line disposed at a lower portion of a space between the first active pillar and the second active pillar; a second selection line disposed at a lower portion of a space between the second active pillar and the third active pillar and at a lower portion of a space between the second active pillar and the fourth active pillar; a first signal line commonly coupled to the junctions of the first active pillar and the fourth active pillar; a second signal line coupled to the junction of the second active pillar; a third signal line coupled to the junction of the third active pillar; and a trap layer electrically coupling the first to fourth active pillars by trapping minority carriers according to individual voltages applied to the first to third signal lines, the first selection line, and the second selection line, wherein the trap layer is disposed between each of the first and second selection lines and corresponding ones of the first and fourth active pillars, and the trap layer is disposed on first and second sidewalls of the first active pillar, first and second sidewalls of the second active pillar, and a surface of a substrate between the first active pillar and the second active pillar.