Patent ID: 9425192
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. An integrated circuit comprising: a power supply voltage path on which an adjustable power supply voltage is provided; a ground power supply path; a plurality of power supply decoupling capacitors distributed in a plurality of parallel clusters on the integrated circuit, wherein the plurality of parallel clusters of capacitor cells are coupled between the power supply voltage path and the ground power supply path; a first power source that is coupled to a power supply voltage path and the ground power supply path and that outputs a first voltage; a second power source that is coupled to the power supply voltage path and the ground power supply path and that outputs a second voltage that is lower than the first voltage; a first region of memory cells; a first multiplexer that receives the first and second voltages and that selectively outputs the first voltage to the first region of memory cells in response to determining that the first region of memory cells is to be placed in a fast mode; a second region of memory cells; and a second multiplexer that receives the first and second voltages and that selectively outputs the second voltage to the second region of memory cells in response to determining that the second region of memory cells is to be placed in a slow mode.