Patent ID: 9269796
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a thin film transistor, characterized in that the method comprises the following steps: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate sequentially; coating a photoresist on the etching barrier layer evenly and placing the same mask over the photoresist, etching through a same mask, the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate, retaining the metal oxide layer, a first part of the gate insulating layer, the gate metal layer and the etching barrier layer in a gate region, and a second part of the metal oxide layer, the gate insulating layer and the gate metal layer in a source region and a drain region for forming contact vias; and exposing a first part of the metal oxide layer in the source region and the drain region; metallizing the exposed first part of the metal oxide layer in the source region and the drain region to form a part of a source and a drain, and then depositing a passivation layer; etching the passivation layer, the gate metal layer and the gate insulating layer in the source region and the drain region for forming the contact vias, exposing a second part of the metal oxide layer in the source region and the drain region for forming the contact vias, thereby forming a source contact via and a drain contact via; metallizing the exposed second part of the metal oxide layer in the source region and the drain region to connect them respectively with the formed part of the source and the drain for forming a complete source and drain; filling a conductive material into the source contact via and the drain contact via.