Patent ID: 9472419
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method of fabricating doped FET and an undoped FET in a replacement metal gate process, the method comprising: forming first and second openings in a dielectric layer overlying first and second FET regions of a substrate thereby forming first and second openings overlying the first and second FET regions; forming a high-k layer at the bottom of both the first and second openings; forming a doping layer over the high-k layer in both the first and second openings; forming a multi-layer mask layer on the doping layer in both the first and second openings; in the second opening, removing the multi-layer mask layer and the doping layer to expose the high-k layer in the second opening; in the first opening, thinning the multi-layered mask over the high-k in the first opening to formed a thinned mask layer in the first opening; annealing the substrate to form a doped high-k in the first opening while the high-k of the second opening remains undoped; removing the thinned mask layer to expose the doped high-k in the first opening; after removing the thinned mask layer, forming a first work function metal stack in the first opening of the first FET region; forming a second work function metal stack in the second opening of the second FET region; and filling the first and second openings with a fill material.