Patent ID: 9425057
Filing Date: 2016-08-23
CPC Classification: C23C,H01L

Claim Text:
1. A method for manufacturing a semiconductor device having a 3-dimensional structure, the method comprising: stacking a plurality of insulation layers and a plurality of sacrificial layers alternately one another on a substrate; forming a through hole passing through the insulation layers and the sacrificial layers; forming a pattern filling the through hole; forming an opening passing through the insulation layers and the sacrificial layers; and supplying an etchant through the opening to remove the sacrificial layers, wherein the stacking of the insulation layers is performed by supplying at least one first gas selected from the group comprising SiH the stacking of the sacrificial layers is performed by supplying dichlorosilane (SiCl the etchant comprises one of an HF solution and a buffered oxide etch (BOE) solution, the silicon carbon oxide (SiCO) of the insulation layers and the silicon oxide of the sacrificial layers have etch selectivity with respect to the etchant, and the silicon oxide of the sacrificial layers has an etch rate greater by about 5 times to about 300 times than that of the silicon carbon oxide (SiCO) of the insulation layers.