Patent ID: 9507662
Filing Date: 2016-11-29
CPC Classification: G06F,G11C,H03M,H04L

Claim Text:
1. A memory device comprising: a memory array having a plurality of bits associated with an error correction code (ECC) word and configured to set the plurality of bits to a predefined state in response to reading the plurality of bits from the memory array, the plurality of bits associated with the ECC word including stored data bits, stored parity bits, and at least one stored inversion bit; a parity calculation component configured to generate calculated parity bits determined based at least in part on the stored data bits and the stored inversion bit; a parity/difference generation component configured to generate parity/difference information based at least in part on a comparison of the stored parity bits and the calculated parity bits; and an error correction component configured to identify and correct errors associated with particular bits of the stored data bits, the stored parity bits, or the at least one stored inversion bit.