Patent ID: 9362864
Filing Date: 2016-06-07
CPC Classification: H03B

Claim Text:
1. An apparatus comprising: a monitoring device configured to monitor a duty cycle of a clock output signal of a crystal oscillator circuit during oscillation buildup upon power-up of the crystal oscillator circuit, the duty cycle being output from a buffer with a ratio of a first p-type metal-oxide-semiconductor (PMOS) transistor to a second PMOS transistor that is different from a ratio of a first n-type metal-oxide-semiconductor (NMOS) transistor to a second NMOS transistor to condition the duty cycle to have an initial value that does not meet a duty cycle threshold value at the power-up, and a value of the duty cycle being adjusted from the initial value during the oscillation buildup; a detecting device configured to detect whether the duty cycle of the clock output signal of the crystal oscillator circuit meets the duty cycle threshold value; and an assertion device configured to assert a control signal based on detecting the duty cycle meets the duty cycle threshold value, the asserted control signal configured to dynamically adjust a transconductance of the crystal oscillator circuit.