Patent ID: 9465537
Filing Date: 2016-10-11
CPC Classification: G06F,G11C

Claim Text:
1. A memory system comprising: a nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of word lines, each of the word lines including a plurality of memory cells, the plurality of memory cells having a storage capacity for one or more pages; and a controller configured to: cyclically execute patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to one or more but not all of the word lines in each of the blocks; change a word line as an execution target of the patrol read each time a patrol read cycle is started; wherein the patrol read includes error correction that is performed using an error-correcting code added to the data; and wherein when number of errors in the read data exceeds a predetermined threshold, the controller moves data in a block including the read data to another block.