Patent ID: 9269432
Filing Date: 2016-02-23
CPC Classification: G11C

Claim Text:
1. A memory system comprising: a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states; access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states; a controller configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second of the signals to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic; wherein the memory cells individually comprise a memory element intermediate a plurality of electrodes, the memory element having a plurality of different electrical resistances corresponding to the different memory states of the individual memory cell; and wherein the first memory state of the one memory cell is a low resistance state wherein the memory element of the one memory cell comprises at least one electrically conductive structure electrically coupled with the electrodes of the one memory cell, and the application of the second signal to the one memory cell removes the electrical coupling of the at least one electrical conductive structure and at least one of the electrodes of the one memory cell.