Patent ID: 9508396
Filing Date: 2016-11-29
CPC Classification: G11C,H01L

Claim Text:
1. An array structure of a single-poly nonvolatile memory, the array structure comprising: a first word line; a second word line; a first source line; a second source line, wherein the second source line and the first source line are different; a first erase line; a first bit line; a first memory cell comprising a first PMOS transistor, a second PMOS transistor and a first NMOS transistor, wherein a source terminal of the first PMOS transistor is connected to the first source line, a gate terminal of the first PMOS transistor is connected to the first word line, a drain terminal of the first PMOS transistor is connected to a source terminal of the second PMOS transistor, a drain terminal of the second PMOS transistor is connected to the first bit line, a gate terminal of the second PMOS transistor is connected to a gate terminal of the first NMOS transistor, and a drain terminal and a source terminal of the first NMOS transistor are connected to the first erase line; and a second memory cell comprising a third PMOS transistor, a fourth PMOS transistor and a second NMOS transistor, wherein a source terminal of the third PMOS transistor is connected to the second source line, a gate terminal of the third PMOS transistor is connected to the second word line, a drain terminal of the third PMOS transistor is connected to a source terminal of the fourth PMOS transistor, a drain terminal of the fourth PMOS transistor is connected to the first bit line, a gate terminal of the fourth PMOS transistor is connected to a gate terminal of the second NMOS transistor, and a drain terminal and a source terminal of the second NMOS transistor are connected to the first erase line, wherein the gate terminal of the second PMOS transistor and the gate terminal of the first NMOS transistor are connected to a first floating gate, and the gate terminal of the fourth PMOS transistor and the gate terminal of the second NMOS transistor are connected to a second floating gate.