Patent ID: 9323942
Filing Date: 2016-04-26
CPC Classification: G01R,G06F

Claim Text:
1. A processor comprising: storage; a debug unit to receive a policy from a debug aggregator, the policy based on a value of a first fuse, the policy having a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse; a test access port to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode; wherein the policy is also based on the value of an unlock signal, the unlock signal indicating the use of an authenticated debugger, the policy also having a locked mode corresponding to a locked value of the unlock signal, the test access port also to prevent access to the storage using the debug command in the locked mode; wherein the debug mode also corresponds to an unlocked value of the unlock signal.