Patent ID: 9348240
Filing Date: 2016-05-24
CPC Classification: G03F

Claim Text:
1. A method for aligning a mask with a wafer for exposing the wafer with a mask pattern in the mask, comprising: dividing the wafer into a plurality of regions including a first region and a second region different from the first region, each region containing a plurality of chip areas; obtaining alignment offset values for the first region; determining a first alignment compensation equation for the first region based on the alignment offset values for the first region, wherein: the first alignment compensation equation is represented as: A1[Tx, Ty, Ex, Ey, Rx, Ry], A1 represents an alignment compensation for the first region, (Tx, Ty) represents a compensation from a lateral shift caused by a wafer warpage of the wafer along X-axis and Y-axis, (Ex, Ey) represents a compensation from pattern image amplification changes caused by the wafer warpage of the wafer in Z-axis, and (Rx, Rv) represents a compensation from a rotation caused by the wafer warpage of the wafer, Tx is X-axis lateral shift compensation, Ty is Y-axis lateral shift compensation, k1 and k2 are coefficients, the compensation equation for lateral shift is: Tx=k1, and Ty=k2, the chip area has an X-coordinate ‘x’, and a Y-axis coordinate ‘y’, Ex is X-axis distance shift compensation, Ey is Y-axis distance shift compensation, k3 and k4 are coefficients, the compensation equation for distance shift is: Ex=k3*x, and Ey=k4*y, the chip area has an X-coordinate ‘x’, and a Y-axis coordinate ‘y’, Rx is X-axis rotation compensation, Ry is Y-axis rotation compensation, k5 and k6 are coefficients, the compensation equation for lateral shift is: Rx=k5*y, and Ry=k6*x, and the one or more of k1, k2, k3, k4, k5, and k6 are determined, based on an average or weighted average of corresponding alignment offsets measured from chip areas selected from the plurality of chip areas in the first region; obtaining alignment offset values for the second region; determining a second alignment compensation equation for the second region based on the alignment offset values for the second region; determining whether a chip area to be exposed is in the first region or the second region; when the chip area is in the first region, using the first alignment compensation equation to adjust alignment of the wafer; and when the chip area is in the second region, using the second alignment compensation equation to adjust the alignment of the wafer.