Patent ID: 9502416
Filing Date: 2016-11-22
CPC Classification: G11C,H01L

Claim Text:
1. A semiconductor device, comprising: a substrate including a first, a second, a third, a fourth areas; a first, a second, a third, a fourth gate stacks on the first through fourth areas of the substrate, respectively, wherein the first gate stack includes a first high-dielectric constant (k) layer on the substrate, a first TiN layer on the first high-k layer to contact the first high-k layer and has a first thickness, and a first gate metal on the first TiN layer, wherein the second gate stack includes a second high-k layer on the substrate, a second TiN layer on the second high-k layer to contact the second high-k layer and has a second thickness, and a second gate metal on the second TiN layer, wherein the third gate stack includes a third high-k layer on the substrate, a third TiN layer on the third high-k layer to contact the third high-k layer and has a third thickness, and a third gate metal on the third TiN layer, and wherein the fourth gate stack includes a fourth high-k layer on the substrate, a fourth TiN layer on the fourth high-k layer to contact the fourth high-k layer and has a fourth thickness, and a fourth gate metal on the fourth TiN layer, wherein the first through fourth thicknesses are different.