Patent ID: 9384995
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A memory device, comprising: a channel comprising a first end and a second end, the first end of the channel being coupled to a bit line and the second end of the channel being coupled to a source; a select gate formed at the second end of the channel to selectively control conduction between the bit line and the channel, the select gate comprising a layer of tungsten salicide; at least one non-volatile memory cell formed along a length of the channel between the select gate and the first end of the channel; and at least one word line coupled to the at least one non-volatile memory cell; wherein a distance between the select gate and the at least one word line measures less than 50 nanometers: and wherein the layer of tungsten salicide comprises an etch stop without a recess or floating gate that would otherwise occur with an aluminum oxide etch stop.