Patent ID: 9240354
Filing Date: 2016-01-19
CPC Classification: H01L

Claim Text:
1. A semiconductor memory device, comprising: a semiconductor-on-insulator (SOI) substrate including an active semiconductor layer formed on a buried insulator layer; a semiconductor device formed on the SOI substrate, the semiconductor device including a channel region formed between a source region and a drain region; at least one storage element formed adjacent the channel region; at least one isolation region disposed between the channel region and the at least one storage element; impurities disposed within the active semiconductor layer of the channel region; and a diffusion barrier layer formed in the active semiconductor layer, the diffusion barrier layer disposed between the impurities and an upper surface of the channel region to increase a voltage threshold at a leakage region shared by the buried insulator layer, the channel region, and the at least one isolation region; and a gate formed directly over the channel region containing the impurities and above the diffusion barrier layer such that the impurities are contained in the channel region without extending beyond the channel region.