Patent ID: 9419126
Filing Date: 2016-08-16
CPC Classification: H01L

Claim Text:
1. A method for fabricating an integrated circuit comprising: providing a semiconductor substrate including a shallow trench isolation structure disposed therein and a gate electrode structure overlying semiconductor material of the semiconductor substrate; forming a first sidewall spacer adjacent to the gate electrode structure, wherein a first surface of the shallow trench isolation structure is exposed and spaced from the first sidewall spacer by a region of the semiconductor material; epitaxially growing a crystalline material over the region of the semiconductor material between the first sidewall spacer and the shallow trench isolation structure to form a self-aligned dummy structure, wherein the dummy structure is not embedded in the region of semiconductor material, and wherein the shallow trench isolation structure remains free of the dummy material after epitaxially growing the crystalline material over the region of the semiconductor material between the first sidewall spacer and the shallow trench isolation structure, forming an oxide mask layer in a self-aligned manner on the exposed first surface of the shallow trench isolation structure after epitaxially growing the crystalline material over the region of the semiconductor material between the first sidewall spacer and the shallow trench isolation structure, wherein the region of the semiconductor material disposed between the first sidewall spacer and the shallow trench isolation structure is free from the isolation structure mask, and wherein the isolation structure mask is only disposed on the shallow trench isolation structure; etching a recess in the region of the semiconductor material disposed between the first sidewall spacer and the shallow trench isolation structure with the isolation structure mask in place; and epitaxially growing a semiconductor material within the recess after masking the first surface of the shallow trench isolation structure with the isolation structure mask to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure; wherein the isolation structure mask is formed with a mask surface of the isolation structure mask raised in relation to the epitaxially-grown semiconductor region disposed in the semiconductor substrate.