Patent ID: 9401210
Filing Date: 2016-07-26
CPC Classification: G11C,H01L

Claim Text:
1. A nonvolatile memory device comprising: a memory cell array including a plurality of memory blocks each having a plurality of strings formed in a direction perpendicular to a substrate and connected between bit lines and a common source line; an address decoder adapted to select one of the plurality of memory blocks based upon an address; an input/output circuit adapted to store data to be programmed at memory cells connected to a selected one of word lines of a selected memory block, of the plurality of memory blocks, for a program operation and store data read from the memory cells connected to the selected word line for a verification operation; a common source line driver adapted to set the common source line with a preset voltage, and, selectively drain charge from and supply charge to the common source line using a voltage level of the common source line as a feedback signal; and control logic adapted to control the address decoder, the input/output circuit, and the common source line driver for the program operation and the verification operation; wherein the common source line driver stepwise decreases a voltage level of the common source line during a common source line recovery period.