Patent ID: 9231538
Filing Date: 2016-01-05
CPC Classification: H03F

Claim Text:
1. An energy efficient, low distortion amplification apparatus comprising: a differential amplifier having a pair of differential inputs, a pair of outputs, and a bias current control input; a digital delay having an n-bit word input and an m-bit word output; a digital-to-analog converter (DAC) having an input coupled to the output of the digital delay and a pair of differential outputs coupled to the pair of differential inputs of the differential amplifier; and a bias current controller having an input coupled to the digital delay and having an output coupled to the bias current control input of the differential amplifier; wherein the digital delay includes a First-In-First-Out (FIFO) buffer; wherein the input of the bias current controller is coupled to the n-bit word input of the digital delay; and wherein the output of the bias current controller is a digital signal having a width w of at least one bit.