Patent ID: 9431405
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method for fabricating a flash memory device, comprising: providing a semiconductor substrate; forming a first polysilicon layer on a surface of the semiconductor substrate; forming a hard mask layer on the first polysilicon layer; forming a plurality of first openings to expose the first polysilicon layer in the hard mask layer and first polysilicon silicon layer by etching the hard mask layer and the first polysilicon, forming a plurality of grooves in the semiconductor substrate by etching the semiconductor substrate along the first openings; forming liner oxide layers by oxidizing the first polysilicon layer exposed by the first openings; forming shallow trench isolation structures covering the liner oxide layers by filling the first openings and the grooves with an isolation material; forming second openings by removing the hard mask layer and a non-oxidized first polysilicon layer; forming a tunnel oxide layer on the surface of the semiconductor substrate at a bottom of each of the second openings; and forming a floating gate on each of the tunnel oxide layers.