Patent ID: 9385049
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A process for manufacturing an integrated device, comprising: forming a STI insulation structure in a semiconductor body that extends above a depressed first portion of the semiconductor body and laterally delimits second portions of the semiconductor body projecting from the first portion, said STI insulation structure having a sidewall with the second portions of the semiconductor body that is disposed at a first angle with respect to a plane defined by a top surface of the second portions that is less than ninety degrees; forming low-voltage CMOS components in the second portions; forming an aperture in the STI insulation structure to expose a region of the depressed first portion of the semiconductor body, said aperture having a sidewall that is disposed at a second angle with respect to the plane defined by the top surface of the second portions that is less than the first angle, wherein the first angle is between eighty and ninety degrees, and the second angle is between twenty and seventy degrees; and forming a power component in said region of the depressed first portion of the semiconductor body exposed by the aperture; wherein forming the power component comprises: