Patent ID: 9368502
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method for fabricating a memory cell transistor, the method comprising: forming a trench capacitor within a substrate; forming a non-planar transistor including a transistor gate assembly and a transistor channel, the transistor gate assembly having multiple gate surfaces coupled to the transistor channel, the transistor channel of the non-planar transistor is positioned, at least partially, on a different plane than source/drain regions of the non-planar transistor; forming a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor by ion implantation followed by dopant activation through an annealing process, a portion of the self-aligned silicide interconnect forming one of the source/drain regions; depositing a dielectric layer over and in contact with the self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor; and forming a transistor passivation layer above and in contact with the transistor gate assembly, the transistor passivation layer entirely filling a trench defined by the dielectric layer.