Patent ID: 9484246
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A semiconductor structure comprising: a deep trench isolation structure embedded within a semiconductor-on-insulator (SOI) substrate and laterally surrounding a vertical stack including, from bottom to top, an upper portion of a semiconductor material layer, a buried conductive portion comprising a doped semiconductor material, and a portion of a buried insulator layer; a top semiconductor portion overlying said portion of said buried insulator layer; a shallow trench isolation layer laterally surrounding said top semiconductor portion; a via dielectric layer located on a topmost surface of said shallow trench isolation layer and a topmost surface of said top semiconductor portion; and a pair of contact via structures laterally spaced from each other by a portion of said via dielectric layer and extending below a topmost surface of said buried conductive portion, wherein a topmost source of each contact structure of said pair of contact structures is coplanar with a topmost surface of said via dielectric layer.