Patent ID: 9286251
Filing Date: 2016-03-15
CPC Classification: G06F,H04B,H04L

Claim Text:
1. A transceiver comprising: a memory comprising a plurality of bytes, X, wherein X is a number, wherein the memory can be shared between an interleaver function associated with a transmit latency path and a deinterleaver function associated with a receive latency path, wherein the sharing comprises using a first portion of the memory for the interleaver function and simultaneously using a second portion of the memory, different than the first portion, for the deinterleaver function, and the first and second portions are configurable such that one or more bytes of the memory can be used by the interleaver function at one particular time and the same one or more bytes of the memory can be used by the deinterleaver function at a second time, different than the first time, and wherein the transceiver is operable to transmit a message or receive a message, wherein the message comprises information that is used to determine a maximum number of bytes, Y, of the memory, for the interleaver function and information is used to determine a maximum number of bytes, Z, of the memory, for the deinterleaver function, wherein Y and Z are positive numbers and wherein Y+Z is less than or equal to X.