Patent ID: 9361980
Filing Date: 2016-06-07
CPC Classification: G11C

Claim Text:
1. A resistive random access memory (RRAM) array, comprising: a word line voltage source configured to produce a first voltage and a second voltage, wherein in a first operation loop the first voltage is lower than the second voltage; a first RRAM connected to a first word line and the word line voltage source; a second RRAM connected to a second word line and the word line voltage source, wherein a first electrical resistance between the first word line and the word line voltage source is lower than a second electrical resistance between the second word line and the word line voltage source, the word line voltage source is configured to provide the first voltage for resetting the first RRAM, the word line voltage source is configured to provide the second voltage for resetting the second RRAM; and a verifier configured to determine whether the first and second RRAM were successfully reset, the word line voltage source being configured to provide, in a second operation loop, first and second voltages that are higher than the respective first and second voltages provided in the first operation loop, the word line voltage source providing the higher first and second voltages based on a determination by the verifier that the first and second RRAM were not successfully reset.