Patent ID: 9349729
Filing Date: 2016-05-24
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate having a first region and a second region; forming a first dummy gate on a surface of the semiconductor substrate in the first region and a device layer on the surface of the semiconductor substrate in the second region; forming a dielectric layer on the first dummy gate and the device layer and with a top surface leveling the top surfaces of the first dummy gate and the device layer on the semiconductor substrate; removing the first dummy gate to form a first trench; forming a first metal layer on the first trench to fill the first trench and on the surface of the dielectric layer and the surface of the device layer; and performing a first planarization process on the first metal layer using a first polishing slurry having a first protective agent to form a first gate electrode in the first trench and a protective layer on the device layer preventing the device layer being damaged during the first planarization process.