Patent ID: 9305859
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. An integrated circuit die comprising: a semiconductor substrate; a stack of dielectric layers formed on a surface of said semiconductor substrate, said stack including a contact layer, at least one interlayer dielectric layer, and a passivation layer, said contact layer adjoining said semiconductor substrate, a principal surface of said die having an exposed surface of said passivation layer, said at least one interlayer dielectric layer being sandwiched between said contact layer and said passivation layer; a stack of metal layers, each of said metal layers being at an interface between two of said dielectric layers, a first metal layer being located at an upper surface of said contact layer, a top metal layer being located at a lower surface of said passivation layer; a plurality of thermal vias, each of said thermal vias being filled with metal, said thermal vias being grouped in two-dimensional arrays, said thermal vias including a first array of thermal vias contacting said surface of said semiconductor substrate, terminating at said surface of said semiconductor substrate, and extending from said semiconductor substrate through said contact layer to said first metal layer, and a second array of thermal vias extending from said top metal layer through one of said at least one interlayer dielectric layers adjoining said passivation layer; an under bump metal (UBM) layer located at said principal surface of said die and contacting the top metal layer; and a first metal bump attached to said UBM layer, a thermal path being formed from said semiconductor substrate through said thermal vias and said metal layers to said first metal bump, an area of contact between said first array of thermal vias and said surface of said semiconductor substrate being horizontally offset from a location of said first metal bump, said first array of thermal vias contacting said surface of said semiconductor substrate over an area that is not directly beneath the first metal bump, each of said metal layers extending both directly above said area of contact between said first array of thermal vias and said surface of said semiconductor substrate and directly below said first metal bump.