Patent ID: 9287890
Filing Date: 2016-03-15
CPC Classification: H03M,H04N

Claim Text:
1. An analog-to-digital (AD) converter comprising: a reference signal generation section configured to generate a reference signal that increases or decreases with a passage of time; a comparator configured to compare an analog signal with the reference signal and generate a comparison signal at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signal; a clock generation section configured to generate a plurality of clock signals having different phases from each other; a latch section having a plurality of latch units corresponding to the plurality of clock signals, each of the plurality of latch units being configured to latch one corresponding clock signal of the plurality of clock signals; a capacitor to which a first voltage is applied; a latch control signal line to which a second voltage less than the first voltage is applied and which is connected to the plurality of latch units; a first switch configured to control an electrical connection between the capacitor and the latch control signal line based on a control signal; and a selection circuit configured to output the control signal for electrically connecting the capacitor to the latch control signal line, only when the comparison signal has been generated, wherein a third voltage less than the first voltage and greater than the second voltage is applied as a power supply voltage to the plurality of latch units, when the capacitor is electrically connected to the latch control signal line, a potential of the latch control signal line becomes greater than or equal to the third voltage, only when the electrical connection between the capacitor and the latch control signal line is disconnected, the first voltage is applied to the capacitor and the second voltage is applied to the latch control signal line, and when the potential of the latch control signal line becomes greater than or equal to the third voltage, the plurality of latch units latch the plurality of clock signals.