Patent ID: 9437303
Filing Date: 2016-09-06
CPC Classification: G11C

Claim Text:
1. A programming method of a memory array, wherein the memory array comprises a target memory cell electrically connected to a first word line, two periphery memory cells electrically connected to the first word line and adjacent to the target memory cell, and a plurality of non-target memory cells, a first transistor, and a second transistor connected in series with the target memory cell, and the programming method comprises: performing a first programming operation on the target memory cell, wherein the step of performing the first programming operation on the target memory cell comprises: verifying the target memory cell and the two periphery memory cells through at least one verification operation to obtain a first verification result after the first programming operation is performed on the target memory cell; and determining whether to perform a second programming operation or a third programming operation on the target memory cell according to the first verification result, wherein the step of performing the second programming operation or the third programming operation on the target memory cell comprises: