Patent ID: 9335949
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. A computing device comprising: a memory containing a machine readable medium comprising machine executable code having stored thereon instructions for performing a method of deferring invalidation of inodes; a processor coupled to the memory, the processor configured to execute the machine executable code to cause the processor to: store inode head data comprising a plurality of inodes associated with a corresponding plurality of storage objects in a storage volume designated for removal; mark each storage volume designated for removal to indicate that the corresponding plurality of storage objects are not accessible and that an inode invalidation walk-through is to be performed on the storage volume; send an indication that the invalidation walk-through will be performed on the storage volume designated for removal after the marking has been completed; perform the inode invalidation walk-through, wherein the inode invalidation walk-through comprises removing the plurality of inodes associated with the plurality of storage objects; receive an access request for at least one of the plurality of storage objects in the volume to be removed, the access request comprising a volume identifier for a storage volume; and provide an indication that the storage volume has been removed when the volume identifier corresponds to the storage volume designated for removal.