Patent ID: 9529954
Filing Date: 2016-12-27
CPC Classification: G06F,H01L

Claim Text:
1. A collection of standard logic cells, implementing a plurality of logic functions, wherein each standard cell comprises at least: two elongated supply rails, each formed in a first metal (M0) layer, each supply rail having a width at least twice a minimum permitted width for M0 features, each supply rail extending horizontally across the entire width of the standard cell; at least three elongated gate stripes, each formed in a gate (PC) layer, and each extending vertically between at least two of said supply rails, adjacent gate stripes spaced at a minimum contacted poly pitch (CPP); positioned vertically between said supply rails, at least two, first-exposure M0 tracks, each of said first-exposure M0 tracks having the minimum permitted width and extending horizontally across the cell, said first-exposure M0 tracks patterned, in part, by portion(s) of a first-exposure M0 mask (M0_color1) and, in part, by portion(s) of a first-exposure M0 cut mask (M0CUT1); positioned vertically between said supply rails, at least two, second-exposure M0 tracks, each of said second-exposure M0 tracks having the minimum permitted width and extending horizontally across the cell, said second-exposure M0 tracks patterned, in part, by portion(s) of a second-exposure M0 mask (M0_color2) and, in part, by portion(s) of a second-exposure M0 cut mask (M0CUT2); and, additional patterned features, in NW (N-well), TS (trench silicide), RX (active), CA (contact to active), GO (gate open), V0 (via to interconnect), and M1 (first-level interconnect) layers, configured to realize a logical function or behavior of the standard cell; wherein within in the cell: