Patent ID: 9379255
Filing Date: 2016-06-28
CPC Classification: H01L

Claim Text:
1. A non-volatile memory cell comprising: a semiconductor substrate of a first conductivity type having a top surface; a first region of a second conductivity type in said substrate along the top surface; a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region; a channel region between the first region and the second region; a word line gate positioned over a first portion of the channel region, immediately adjacent to the first region, said word line gate spaced apart from the channel region by a first insulating layer; a floating gate positioned over another portion of the channel region, said floating gate having a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface; said floating gate having a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall, wherein said upper surface having a non-planar contour from said first side wall to said second side wall; a coupling gate positioned over the upper surface of the floating gate and insulated therefrom by a third insulating layer, said coupling gate having a lower surface that has a contour that follows the contour of said upper surface of said floating gate; and an erase gate positioned adjacent to the second side wall of the floating gate; said erase gate positioned over the second region and insulated therefrom; wherein said upper surface of said floating gate has a single step like non-planar contour such that the second side wall is taller than said first side wall.