Patent ID: 9252222
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A method of fabricating a transistor, the method comprising: providing a substrate including a semiconductor layer; forming a gate insulating layer and a gate electrode at a position corresponding to a core of the semiconductor layer; forming an interlayer insulating layer covering the gate electrode and exposing both sides of the semiconductor layer; forming an electrode layer extending along the substrate and contacting the both sides of the semiconductor layer; forming a conductive layer covering the electrode layer; forming a first electrode and a second electrode spaced from the first electrode by patterning the electrode layer; and forming a conductive line on the first electrode by removing the conductive layer on the second electrode, wherein the first electrode contacts one side of the semiconductor layer and the second electrode contacts the other side of the semiconductor layer; and the semiconductor layer, the first electrode, and the second electrode have a coplanar level surface.