Patent ID: 9385039
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A 3D chip comprising a plurality of silicon substrates having through-silicon via (TSV) in which a through hole by a method of forming a through-silicon via (TSV) includes blocking a lower end of the through hole of at least one silicon substrate, placing solid solder above the through hole of the at least one silicon substrate for subsequently filling in the through hole, evacuating a space that includes both the internal space and an external space of the through hole, melting the placed solid solder to block an upper end of the through hole of the silicon substrate by the molten solder, and changing an evacuated state back to a previous state to cause a pressure difference between the external space and the internal space of the through hole so that the molten solder is guided to the internal space of the through hole and the internal space of the through hole is filled with the molten solder; wherein the plurality of silicon substrates are joined by an additional method, the additional method comprising: providing a plurality of solder bumps on the at least one silicon substrate; providing a second silicon substrate on the plurality of solder bumps; and melting the solder bumps by generating a specific temperature higher than a melting temperature of the solder bumps.