Patent ID: 9455717
Filing Date: 2016-09-27
CPC Classification: H03K

Claim Text:
1. A digital counter comprising: at least a first counting module and a second counting module, said counting modules being serially coupled and forming a counting module chain; each counting module comprising at least a first digital storage cell and a second digital storage cell, each counting module providing module counting information of at least two bits; said counting modules being operative, during counting, to respectively change only one bit of said module counting information between two successive counting state; wherein the counting modules are coupled such that the start of counting of the second counting module is enabled by the first counting module when said first counting module has passed through all counting states of said first counting module; wherein the digital storage cells of the first counting module comprise level-triggered latches and wherein the digital storage cells of the first counting module are triggered by clock signals that are inverted with respect to each other; and wherein the digital storage cells of higher order counting modules comprise edge-triggered flip-flops.