Patent ID: 9389864
Filing Date: 2016-07-12
CPC Classification: G06F

Claim Text:
1. A data processing device comprising an external memory that stores an instruction and data necessary for execution of the instruction and a plurality of processor units, each of the plurality of processor units comprising: cache memory that temporarily stores the instruction and the data; an instruction execution unit that reads the instruction and the data from the external memory via the cache memory and executes the instruction; an initiation detecting unit that detects an entering of a thread implemented by processing of the instruction execution unit into an exclusive control section, which is specified in advance to become a bottleneck; a termination detecting unit that detects an exiting of the thread out of the exclusive control section; and the exclusive control section in-execution flag that is set by an output of the initiation detecting unit and is reset by an output of the termination detecting unit, wherein the data processing device uses the value of the exclusive control section in-execution flag for controlling the cache memory.