Patent ID: 9431306
Filing Date: 2016-08-30
CPC Classification: H01L

Claim Text:
1. A method, comprising: forming a plurality of fin-formation trenches in a semiconductor substrate so as to define a fin comprised of a lower portion and an upper portion, wherein said lower portion of said fin has tapered sidewalls; forming a first layer of insulating material in said fin-formation trenches so as to cover substantially all of said tapered sidewalls of said lower portion of said fin; forming a sidewall spacer on opposite sides of said upper portion of said fin above an upper surface of said first layer of insulating material; removing said first layer of insulating material so as to expose said tapered sidewalls of said lower portion of said fin; with said sidewall spacers in position, performing a fin-trimming etching process to remove at least a portion of said lower portion of said fin and to increase a depth of said fin-formation trenches so as to thereby define a plurality of increased-size trenches; forming a first oxidation-blocking layer of insulating material in said increased-size trenches such that a section of said lower portion of said fin is exposed between an upper surface of said first oxidation-blocking layer of insulating material and a bottom surface of said sidewall spacers; forming a second layer of insulating material above said first oxidation-blocking layer of insulating material and on and in contact with said exposed portion of said fin; and performing a thermal anneal process wherein, after said thermal anneal process, at least a part of the portion of said fin that is in contact with said second layer of insulating material and positioned above said first oxidation-blocking layer of insulating material is converted into an oxide fin isolation region positioned under said upper portion of said fin.