Patent ID: 9418008
Filing Date: 2016-08-16
CPC Classification: G06F,G11C

Claim Text:
1. An electronic device comprising a semiconductor memory unit, wherein the semiconductor memory unit comprises: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction intersecting the first direction; and a plurality of variable resistance patterns positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a direction that is perpendicular to the first and second directions, wherein each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns extends outside a region in which a corresponding first line and a corresponding second line overlap with each other, wherein each of the variable resistance patterns overlaps with each of the intersections of the first lines and the second lines so that there is a one-to-one correspondence between the variable resistance patterns and the intersections of the first lines and the second lines, and wherein, in a direction of a major axis of each of the variable resistance patterns, two adjacent variable resistance patterns are spaced apart from each other.