Patent ID: 9331199
Filing Date: 2016-05-03
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: first and second active regions spaced apart from each other in a first direction with an isolation layer interposed therebetween; a first normal gate on the first active region, the first normal gate extending in a second direction crossing the first direction; a first dummy gate comprising a first portion overlapping a first end of the isolation layer and a second portion overlapping the first active region and being spaced apart from the first normal gate in the first direction; a second dummy gate comprising a first portion overlapping a second end of the isolation layer and a second portion overlapping the second active region; a first normal source/drain contact on a first source/drain region between the first normal gate and the first dummy gate; and a dummy contact on the isolation layer and between the first and second dummy gates, the dummy contact not overlapping the first and second dummy gates and including a metallic material that applies stress to the first active region disposed under the first normal gate.