Patent ID: 9420694
Filing Date: 2016-08-16
CPC Classification: H01L,H05K,Y10T

Claim Text:
1. A method of manufacturing an electronic product with decreased warpage, the method comprising: manufacturing at least one wiring pattern layer; manufacturing at least one insulating material layer; forming groove holes to the at least one insulating material layer; connecting at least one embedded component to the at least one wiring pattern layer; stacking the at least one wiring pattern layer having the at least one embedded component and the at least one insulating material layer having the groove holes on top of each other to form a stacked substrate such that the insulating material layer and the embedded component are on the same side of the wiring pattern layer; curing the stacked substrate together with heat and pressure treatment in order to achieve the electronic product with decreased warpage, wherein the groove holes are formed to the at least one insulating material layer prior to curing of the stacked substrate; and wherein the groove holes are configured to cut the longitudinal forces caused by reinforcing fibers within the insulating material layer.