Patent ID: 9308619
Filing Date: 2016-04-12
CPC Classification: B24B,H01L

Claim Text:
1. A method of simultaneous double-side polishing of at least one wafer composed of semiconductor material, the method comprising: disposing each wafer in a respective suitably dimensioned cutout in a carrier plate having a front side and a rear side, wherein each wafer can be configured to rotate within each suitability dimensioned cutout and wherein each suitably dimensioned cutout in the carrier plate is surrounded by at least one segmented cutout at a distance A from the dimensioned cutout; and polishing the at least one wafer between an upper polishing plate covered with a first polishing pad and a lower polishing plate covered with a second polishing pad while supplying a polishing agent, wherein the polishing agent is supplied on a front side and a rear side of the semiconductor wafer in a pressurized manner, through openings present in the upper and the lower polishing pad and through openings present in the upper and in the lower polishing plate; wherein each polishing pad has an inner circular region and an outer edge region formed by a ring-shape area where the quantity of the polishing agent emerging from the openings into a working gap per unit time in the inner circular region of each polishing pad is different from a quantity that emerges in the same time from the openings situated in the outer ring-shaped region.