Patent ID: 9437715
Filing Date: 2016-09-06
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a non-volatile memory, comprising: providing a substrate, wherein a tunneling dielectric layer and a first conductive pattern are formed on the substrate in order, and a plurality of isolation structures are formed in the first conductive pattern, the tunneling dielectric layer, and the substrate; forming a first photoresist layer on the substrate, wherein the first photoresist layer exposes a portion of the first conductive pattern and a portion of the isolation structures; removing a portion of the first conductive pattern by using the first photoresist layer as a mask to form a first opening between the isolation structures and the first conductive pattern, wherein the first opening exposes the substrate; removing the first photoresist layer; forming an insulating layer on the substrate, wherein the insulating layer completely fills the first opening and covers the first conductive pattern and the isolation structures; forming a second photoresist layer on a portion of the insulating layer, wherein the second photoresist layer shields a portion of the first conductive pattern; by using the first photoresist layer as a mask, removing a portion of the insulating layer and a portion of the isolation structures located in a periphery of the first conductive pattern, wherein the insulating layer and the isolation structures remaining on the substrate form a patterned insulating layer, the patterned insulating layer has a second opening, and the second opening exposes a top portion and a sidewall of the first conductive pattern; removing the second photoresist layer; forming an inter-gate dielectric layer on the first conductive pattern, wherein the insulating layer remaining on the substrate is disposed between the inter-gate dielectric layer and the substrate; forming a second conductive pattern on the inter-gate dielectric layer, wherein the second conductive pattern completely fills the second opening and thus the insulating layer remaining on the substrate is disposed on a sidewall of the second conductive pattern, the second conductive pattern forms a control gate, the first conductive pattern forms a floating gate, and the control gate covers and surrounds the floating gate; and removing a portion of the insulating layer remaining on the substrate to form an insulator pattern at two sides of a bottom portion of the floating gate and under a portion of the control gate on two sides of the floating gate.