Patent ID: 9490025
Filing Date: 2016-11-08
CPC Classification: G11C

Claim Text:
1. A method of programming a memory device, the method comprising: biasing unselected data lines of a plurality of data lines to a first program inhibit voltage and biasing selected data lines of the plurality of data lines to a program enable voltage, wherein each data line of the plurality of data lines is connected to a respective string of series connected memory cells of a plurality of strings of series connected memory cells, wherein the selected data lines are coupled to memory cells selected for programming and the unselected data lines are not coupled to memory cells selected for programming; applying a plurality of first programming pulses to the memory cells selected for programming while biasing the unselected data lines to the first program inhibit voltage; biasing the unselected data lines to a second program inhibit voltage that is greater than the first program inhibit voltage and biasing selected data lines of the plurality of data lines to the program enable voltage when the plurality of first programming pulses reaches a certain number; and applying a plurality of second programming pulses to memory cells selected for programming while biasing the unselected data lines to the second program inhibit voltage.