Patent ID: 9362265
Filing Date: 2016-06-07
CPC Classification: H01L

Claim Text:
1. A protection device for a mixed-signal integrated circuit, the protection device comprising: a semiconductor substrate; a first n-type well in the semiconductor substrate; a first p-type well in the semiconductor substrate adjacent the first n-type well; a first n-type active region disposed along a boundary of the first n-type well and the first p-type well; a second n-type active region in the first p-type well; a first p-type active region in the first n-type well; a gate structure over the first n-type well, wherein the first p-type active region is disposed on a first side of the gate structure, and wherein the first n-type active region is disposed on a second side of the gate structure opposite the first side; a second p-type well in the semiconductor substrate, wherein the first n-type well is positioned between the first p-type well and the second p-type well; and an n-type isolation layer beneath the first p-type well, the first n-type well, and the second p-type well.