Patent ID: 9287283
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A non-volatile memory device comprising: a channel formed over a substrate and including a pillar portion and first and second protrusion portions, wherein the pillar portion extends in a first direction perpendicular to the substrate, and wherein each of the first and the second protrusion portions protrudes from a first side surface of the pillar portion in a second direction parallel to the substrate, wherein the first and the second protrusion portions are located at different levels in the first direction and are spaced apart from each other; first and second multi-layered structures each of which includes a charge blocking layer, a charge trap/storage layer, and a tunnel insulation layer, wherein the first multi-layered structure surrounds a top surface, a bottom surface, and an outer side surface of the first protrusion portion, wherein the second multi-layered structure surrounds a top surface, a bottom surface, and an outer side surface of the second protrusion portion, and wherein the first and the second multi-layered structures are located at different levels in the first direction and spaced apart from each other by an interlayer dielectric layer which is interposed between the first multi-layered structure and the second multi-layered structure; a first gate electrode being in contact with an outer side surface of the first multi-layered structure; and a second gate electrode being in contact with an outer side surface of the second multi-layered structure, wherein the first and the second multi-layered structures are not connected to each other.