Patent ID: 9252031
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a lower heat-transfer layer disposed on the lower semiconductor chip; an interposer provided on the lower package, the interposer comprising an interposer substrate, a first heat-transfer opening defined by a recessed bottom surface of the interposer substrate, a second heat-transfer opening defined by a recessed top surface of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad; and an upper package provided on the interposer, the upper package comprising an upper package substrate, an upper package heat-transfer pad disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate, wherein the lower heat-transfer layer is provided in the first heat-transfer opening to be in contact with the upper interposer heat-transfer pad exposed to the first heat-transfer opening, and the upper heat-transfer layer is provided in the third heat-transfer opening to contact the upper package heat-transfer pad.