Patent ID: 9502533
Filing Date: 2016-11-22
CPC Classification: H01L

Claim Text:
1. A method, comprising: receiving a semiconductor substrate with an active region disposed in the semiconductor substrate; forming a shallow trench isolation (STI) structure that laterally surrounds the active region; recessing an upper surface of the active region bounded by the STI structure to below an upper surface of the STI structure, wherein the recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed; epitaxially growing a semiconductor layer which is in direct contact with the recessed surface of the active region and the inner sidewalls of the STI structure and which exhibits an absence of germanium; forming a gate dielectric over the epitaxially-grown semiconductor layer; and forming a conductive gate electrode over the gate dielectric.