Patent ID: 9255000
Filing Date: 2016-02-09
CPC Classification: B81B,B81C

Claim Text:
1. A method of fabricating a semiconductor device, comprising: forming a first dielectric layer above a substrate, the first dielectric layer including a fixed dielectric portion and a proof mass portion; forming a source region and a drain region in the substrate; forming a routing layer above the first dielectric layer; forming a second dielectric layer above the routing layer; forming a bond layer above the second dielectric layer, a portion of the bond layer supported by the proof mass portion; forming a gate electrode in the proof mass portion; bonding a silicon layer to the bond layer, the silicon layer including a first silicon portion and a second silicon portion; releasing the proof mass portion; and releasing the second silicon portion, such that a proof mass of the semiconductor device includes the proof mass portion and the second silicon portion, the proof mass movable with respect to the fixed dielectric portion and the first silicon portion, the gate electrode movable with the proof mass portion relative to the source region and the drain region, the second silicon portion movable with the proof mass portion, and the first silicon portion fixed with respect to the fixed dielectric portion.