Patent ID: 9355694
Filing Date: 2016-05-31
CPC Classification: G11C

Claim Text:
1. A memory circuit comprising: a supply node; one or more memory bitcells coupled to the supply node, the one or more memory bitcells to receive a write word line (WWL) signal to selectively activate a write operation for the memory cells; and an assist circuit coupled between a main supply rail and the supply node, the main supply rail to receive a main supply voltage and the assist circuit to selectively provide a first voltage to the supply node during at least a portion of the write operation, the first voltage being lower than the main supply voltage, wherein the assist circuit is to provide the first voltage to the supply node during a first time period of the write operation and is to provide a second voltage to the supply node during a second time period of the write operation, the second voltage being greater than the first voltage and the second time period occurring later in time than the first time period.