Patent ID: 9384092
Filing Date: 2016-07-05
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor memory device comprising a dynamic random access memory (DRAM) and including: a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic; a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array; a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array; a first sense amplifier accessing the first data stored in the first sub-memory cell array during the read operation using a first data access approach; and a second sense amplifier accessing the second data stored in the second sub-memory cell array during the read operation using a second data access approach different from the first data access approach; wherein each of the first and second peripheral circuits to control a timing of AC parameter corresponding to the first and second sub-memory cell array by controlling core voltages applied to the first and second sub-memory cell arrays and the corresponding first and second sense amplifiers.