Patent ID: 9524007
Filing Date: 2016-12-20
CPC Classification: G01R,G06F

Claim Text:
1. A power management integrated circuit comprising: a finite state machine having a first terminal to receive a digital command signal, a second terminal to receive a clock signal, and a third terminal to receive a first reset signal to reset the finite state machine into a predetermined operational state; a plurality of diagnostic registers configured to receive the first reset signal and a second reset signal and to store a signal state of the digital command signal or a clock state of the clock signal, or both in response to the first reset signal, the diagnostic registers are configured to maintain the signal state or the clock state, or both after powering down of the power management integrated circuit in response to the first reset signal, wherein the plurality of diagnostics registers are not cleared in response to the first reset signal, and wherein the plurality of diagnostics registers are cleared in response to the second reset signal generated when battery power is removed from the power management integrated circuit; and a halt detector having an input to receive the clock signal and having an output to provide a halt detection signal to at least one diagnostic register to store the clock state in response to detection of a halt of the clock signal.