Patent ID: 9508648
Filing Date: 2016-11-29
CPC Classification: H01L,Y10T

Claim Text:
1. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, has a first interlayer filler layer containing a resin (A) and an inorganic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrates, and has a second interlayer filler layer coma a resin (a) and an inorganic filler (b) is formed between the semiconductor substrate laminate and the organic substrate, wherein the semiconductor substrate laminate is mounted on an organic substrate, said first interlayer filler layer is obtained from a composition containing from 50 to 400 parts by weight of an inorganic filler (B), from 0.1 to 60 parts by weight of a curing agent (C) and from 0.1 to 10 parts by weight of a flux (D) per 100 parts by weight of a resin (A), the resin (A) is a plurality of epoxy resins differing in the structural units in combination, and the inorganic filler (B) has an average particle size of at least 0.1 μm and at most 10 μm, a maximum particle size of at most 10 μm, and a thermal conductivity of at least 2 W/(m·K).