Patent ID: 9466672
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method of making a semiconductor stack, the method comprising: disposing a first semiconductor layer directly on a silicon substrate, the first semiconductor layer comprising a first atomic % (at. %) of a semiconductor element, having a thickness in a range from 1 to 5 microns and being 90 to 100% relaxed; disposing a tensile strained interlayer on the first semiconductor layer, the tensile strained interlayer comprising a second at. % of the semiconductor element and having a thickness in a range from 20 to 50 nanometers, the second at. % being at least 25 at. % smaller than the first at. %; disposing a second semiconductor layer on the tensile strained interlayer, the second semiconductor layer comprising a third at. % of the semiconductor element and having a thickness in a range from 1 to 5 microns and being 90 to 100% relaxed, and the third at. % being at least 25 at. % larger than the second at. %; and wherein the first semiconductor layer, the tensile strained interlayer, and the second semiconductor layer comprise silicon germanium (SiGe), and the semiconductor element is germanium (Ge).