Patent ID: 9343563
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A HEMT device, comprising: a substrate; a multilayer stack on the substrate, wherein the multilayer stack comprises plurality of thin film layers; a first merged area positioned on a first portion of the multilayer stack; a second merged area positioned on a second portion of the multilayer stack, wherein the first merged area and the second merged area are formed from annealing an ultra-thin barrier layer and a SAG S-D thin film layer on the ultra-thin barrier layer; a treated area on the multilayer stack positioned between the first merged area and the second merged area, wherein the treated area comprises a fluorine-treated ultra-thin barrier layer; a source on the first merged area; a drain on the second merged area; a dielectric coating over the treated area such that the dielectric coating is positioned between the source and the drain; a gate electrode positioned on the dielectric coating such that the dielectric coating is positioned between the gate electrode and the treated area; a silicon based passivation layer positioned around the gate electrode; and a field plate electrode positioned on the silicon based passivation layer.