Patent ID: 9406399
Filing Date: 2016-08-02
CPC Classification: G09G,G11C

Claim Text:
1. A bidirectional shift register circuit comprising: four clock signal lines supplying four-phase clock pulses respectively; a plurality of cascade-connected register circuits including a top dummy register circuit, a bottom dummy register circuit, and main register circuits providing between the top dummy register circuit and the bottom dummy register circuit; and a common signal line supplying a common signal to the plurality of cascade-connected register circuits respectively, wherein each of the plurality of cascade-connected register circuits has wherein the bottom dummy register circuit has a second node reset circuit which sets the second node to the low level when the common signal is input into the bottom dummy register circuit, and wherein the top dummy register circuit has a second node reset circuit which sets the second node to the low level when the common signal is input into the top dummy register circuit.