Patent ID: 9523738
Filing Date: 2016-12-20
CPC Classification: G01R,G06F,H04L

Claim Text:
1. An integrated circuit comprising: (a) a test clock lead capable of receiving a test clock signal; (b) a test mode select counter lead capable of carrying bidirectional serial data signals and receiving a test mode select signal; (c) first circuitry having inputs coupled to the test clock lead and to the test mode select counter lead, and having a CE clock output lead for carrying CE clock signals; (d) counter circuitry having a CE clock input connected to the CE clock output lead, the counter circuitry counting edges of the CE clock signals, a first count output corresponding to a first count of the CE clock signals, a second count output corresponding to a second count of the CE clock signals, a third count output corresponding to a third count of the CE clock signals, a fourth count output corresponding to a fourth count of the CE clock signals, the counter circuitry having a reset output coupled to the fourth count output; and (e) gating circuitry having inputs connected to the first and second count outputs and having a technology specific function output lead carrying an output based on the first and second count outputs.