Patent ID: 9495131
Filing Date: 2016-11-15
CPC Classification: G06F

Claim Text:
1. A method for adding a plurality of first floating point (FP) numbers in a parallel computing system, the system comprising a plurality of computing nodes, a computing node including at least one processor and at least one memory device, and a collective logic device, the method comprising: receiving, at the front-end logic device, a plurality of the first floating point numbers in parallel from the computing nodes or network links; converting, by said front-end device, the first floating point numbers to a plurality of integer numbers, said front-end logic device further for comparing exponents of each of the first floating point numbers to determine a maximum exponent; adding, using an ALU comprising a plurality of levels with combining blocks, the integer numbers in parallel and generating a summation of all of the plurality of integer numbers in one pass; and converting, at a back-end logic device, the summation to a second floating point number by performing shifting according to the maximum exponent; and providing, by one or more arbiter devices, configuration bits to front-end logic device for configuring said front-end logic device with a number of FP shifters used for said converting said first FP numbers to said integer numbers, and for configuring said ALI to perform an addition of the integer numbers, at least one arbiter device performing a method including: