Patent ID: 9472554
Filing Date: 2016-10-18
CPC Classification: H01L

Claim Text:
1. A method of fabricating an integrated circuit having a FinFET, wherein the method comprises: providing a substrate comprising fins, wherein the fins comprise semiconductor material; forming a first metal oxide layer over sidewall surfaces of the fins, wherein the first metal oxide layer comprises a first metal oxide; recessing the first metal oxide layer to a depth below a top surface of the fins to form a recessed first metal oxide layer, wherein the top surface and sidewall surfaces of the fins at a top portion thereof are free from the first metal oxide layer; depositing a dielectric material different from the first metal oxide over the first metal oxide layer and between the fins to form a dielectric layer, wherein the dielectric layer is recessed below the top surface of the fins to a depth above the recessed first metal oxide layer; forming a gate electrode structure over the top surface and sidewall surfaces of the fins at the top portion thereof and over the dielectric layer, wherein the recessed first metal oxide layer is recessed beneath the gate electrode structure; and forming source and drain regions between which a current can flow through a channel under the influence of a bias applied to the gate electrode structure.