Patent ID: 9311095
Filing Date: 2016-04-12
CPC Classification: G06F

Claim Text:
1. A computer system for optimizing instructions to be executed, the system comprising: a processor, the processor comprising an instruction fetcher, an instruction decoder and an execution unit, the processor configured to perform a method comprising: fetching two instructions for execution; determining that the two instructions to be executed are candidates for optimization to a single optimized internal instruction, the two instructions comprising a first instruction identifying a first operand as a target operand and a second instruction identifying, the first operand as a source operand, the first instruction preceding the second instruction in program order; determining that the first operand is specified as a last-use operand that is not used after execution of the second instruction; creating the single optimized internal instruction based on the two instructions, wherein the single optimized internal instruction does not specify the first operand; and executing the single optimized internal instruction instead of the two instructions.