Patent ID: 9324793
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method of patterning a structure, said method comprising: forming a vertical stack, from bottom to top, comprising at least a gate dielectric layer, a metallic material layer, an organic planarization layer (OPL), and a photoresist layer on a planar top surface and a recessed horizontal surface that are provided on, or over, a substrate; lithographically patterning said photoresist layer; etching said OPL and said metallic material layer employing at least one anisotropic etch that employs said patterned photoresist layer as an etch mask; etching physically exposed portions of said gate dielectric layer; and simultaneously removing a residual portion of said OPL and a vertical portion of said metallic material layer over said recessed horizontal surface employing an ashing process, said ashing process employing a combination of Cl