Patent ID: 9424198
Filing Date: 2016-08-23
CPC Classification: G06F

Claim Text:
1. A processor comprising: at least one execution unit; a near memory; and memory management logic to manage the near memory and a far memory as a unified exclusive memory space divided into a plurality of locations, wherein the plurality of locations is arranged in a plurality of sets and a plurality of ways, wherein the plurality of ways includes ways numbered from 1 to W, wherein the near memory includes locations associated with all of the plurality of sets and a first portion of the plurality of ways, wherein the first portion of the plurality of ways includes ways 1 to N, wherein the far memory is external to the processor and includes locations associated with all of the plurality of sets and a second portion of the plurality of ways, wherein the second portion of the plurality of ways includes ways (N+1) to W, wherein N and W are integer numbers, wherein N is less than W and N is greater than 1, and wherein, for each set of the plurality of sets, a way having a lowest way address of the plurality of ways stores metadata including tags associated with all remaining ways.