Patent ID: 9405649
Filing Date: 2016-08-02
CPC Classification: G06F

Claim Text:
1. A debugging circuit connecting to a device to be debugged, the debugging circuit comprising: a platform controller hub comprising a first group of data pins and a second group of data pins; a central processing unit comprising a first group of data pins and a second group of data pins; a controller outputting a control signal; a debugging interface comprising a plurality of input terminals; and a switch unit comprising a plurality of logic control pins receiving the control signal from the controller, a first group of input terminals, a second group of input terminals, and a plurality of output terminals coupled to the plurality of input terminals of the debugging interface; wherein the first group of input terminals of the switch unit are correspondingly coupled to the first and second groups of data pins of the platform controller hub, for receiving a first data signal from the platform controller hub; the second group of input terminals of the switch unit are correspondingly coupled to the first and second groups of data pins of the central processing unit, for receiving a second data signal from the central processing unit; the output terminals of the switch unit selectively output the first data signal or the second data signal to the device to be debugged through the debugging interface, according to the control signal received by the logic control pins of the switch unit from the controller.