Patent ID: 9444451
Filing Date: 2016-09-13
CPC Classification: H03K

Claim Text:
1. A switch circuit for routing one of a positive voltage and a negative voltage from and input terminal to an output terminal, the switch circuit comprising: a first NMOS transistor including a drain connected to the input terminal, a source connected to a first node, and a gate connected to a control terminal; a second NMOS transistor including a drain connected to the first node, a source connected to a second node, and a gate connected to the control terminal; a first PMOS transistor including a source connected to the input terminal, a drain connected to the first node; a second PMOS transistor including a source connected to the first node, a drain connected to the second node, and a gate connected to the control terminal via the inverter; a third NMOS transistor including a source connected to a ground voltage, a drain connected to the first node, and a gate connected to the control terminal via the inverter; and a level shift circuit that includes an input terminal connected to the control terminal, an output terminal connected to a gate of the first PMOS transistor, and a power supply terminal connected to the input terminal, wherein the first PMOS transistor includes a back gate connected to the input terminal of the switch circuit.