Patent ID: 9515122
Filing Date: 2016-12-06
CPC Classification: G06F,G11C,H01L

Claim Text:
1. A method for fabricating an electronic device including a semiconductor memory, comprising: forming a first interlayer dielectric layer over a substrate, and to cover, at least first and second areas of the substrate; forming a first contact plug over the substrate to pass through the first interlayer dielectric layer of the second area; forming an anti-peeling layer over the first interlayer dielectric layer including the first contact plug to cover the first contact plug; after forming the anti-peeling layer covering the first contact plug, forming a second contact plug over the substrate to pass through the anti-peeling layer and the first interlayer dielectric layer in the first area; and subsequently forming a variable resistance pattern over the second contact plug and above the anti-peeling layer, wherein the anti-peeling layer includes a stacked structure of a passivation layer and an adhesive layer.