Patent ID: 9274793
Filing Date: 2016-03-01
CPC Classification: G06F,Y02D

Claim Text:
1. A system for executing instructions using a plurality of memory fragments for a processor, comprising: a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions; a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein resources of each partitionable engine are operable to be partitioned to instantiate a virtual core with partitioned resources of other partitionable engines, wherein communication between resources of each of said plurality of partitionable engines is supported by a global interconnection structure, and wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode; and a plurality memory fragments coupled to the partitionable engines for providing data storage, wherein the global interconnection structure links each of the plurality of memory fragments to each of the plurality of partitionable engines.