Patent ID: 9484422
Filing Date: 2016-11-01
CPC Classification: H01L

Claim Text:
1. A high-voltage metal-oxide-semiconductor (HVMOS) transistor, comprising: a substrate; a gate dielectric layer, disposed on the substrate, the gate dielectric layer comprising a protruded portion and a recessed portion, and the protruded portion being disposed at two sides of the recessed portioned and comprising a thickness greater than a thickness of the recessed portion; a first doped region embedded in the substrate, wherein a border between the protruded portion and the recessed portion is vertically aligned with a side edge of the first doped region; a gate electrode, disposed on the gate dielectric layer; a spacer, disposed on a side wall of the gate electrode and contacted with the first doped region; and a source and drain region, embedded in the substrate at two sides of the gate electrode.