Patent ID: 9496020
Filing Date: 2016-11-15
CPC Classification: G11C,H01L

Claim Text:
1. In an integrated circuit having at least one logic circuit operating within a MOSFET logic circuit range and a plurality of memory cells arranged in an array interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each memory cell in the array connected a complementary bit line pair and a word line, each memory cell comprising: a pair of cross-coupled thyristors, each thyristor having first and second semiconductor regions intermediate an anode and a cathode, a first intermediate region of one thyristor connected to the second intermediate region of the other thyristor and a second intermediate region of the one thyristor connected to the first intermediate region of the other thyristor, each thyristor having an anode connected to a first supply voltage and a cathode connected to a second supply voltage; and a pair of select transistors, each select transistor connected between one of the complementary bit line pair, and a first intermediate region of one thyristor and a second intermediate region of the other thyristor, each select transistor having a control terminal connected to the word line; wherein the memory cell has regions electrically biased so that voltage swings on the complementary bit line pair and the word line, operating within a magnitude of the MOSFET logic circuit range, are sufficient to read and write the memory cell.