Patent ID: 9311075
Filing Date: 2016-04-12
CPC Classification: G06F

Claim Text:
1. A basic input/output system (BIOS) updating apparatus suitable for an electronic apparatus which has a BIOS memory and a chipset, comprising: a first interface circuit; a volatile memory coupled to the first interface circuit, when an extended storage is connected to the first interface circuit, the chipset is in a disable mode, and a first BIOS in the extended storage is stored in the volatile memory by the first interface circuit; a second interface circuit connected to the BIOS memory, wherein the BIOS memory has a second BIOS, wherein the first BIOS and the second BIOS are independent BIOSes; and a first switcher including three selection terminals, a first selection terminal coupled to the volatile memory, a second selection terminal coupled to the second interface circuit, and a common terminal coupled to the chipset, respectively; wherein the BIOS memory and the extended storage are independent storages, and when the first BIOS is stored in the volatile memory, the volatile memory is coupled to the chipset by the first switcher; when the first BIOS is not stored in the volatile memory, the second interface circuit is coupled to the chipset by the first switcher.