Patent ID: 9501712
Filing Date: 2016-11-22
CPC Classification: G06K,G06T,H04N

Claim Text:
1. A device for edge detection and quality enhancement in an image having pixels, the device comprising a mixed signal hardware comprising a plurality of identical and locally interconnected elementary processing cells, wherein each elementary processing cell comprises: a plurality of pixel capacitors, wherein each pixel capacitor has a voltage value for analogically representing a corresponding pixel of the image; at least two MOS transistors for interconnecting each pixel capacitor to other pixel capacitors in its immediate vicinity, which represent adjoining pixels corresponding to the lower row and right column, the MOS transistors comprising a gate terminal; voltage comparators with digital output for comparing the voltage value representing a pixel with the voltage value representing its neighbouring pixels taking as inputs the voltage value of the pixel under study and the voltage value of one of the adjoining pixels; at least two OR digital gates for combining the output of each voltage comparator with a global filtering signal, which is active by logic level ‘0’, wherein the outputs of the OR digital gates are connected with the gate terminal of the MOS-transistors; and a third OR digital gate which has as inputs the outputs of the voltage comparators and which additionally has an output representing a binary image which has logic value ‘1’ for the pixels which are edges in the original image and which has logic value ‘0’ for other pixels.