Patent ID: 9367656
Filing Date: 2016-06-14
CPC Classification: G06F

Claim Text:
1. A computer-implemented method of synchronizing a hardware functional verification system having a plurality of emulation chips, including a root emulation chip and a plurality of branch emulation chips, and having an interconnect mesh connecting each emulation chip to at least one other emulation chip, wherein the root emulation chip and the plurality of branch emulation chips are each programmed with a portion of a hardware circuit design, the method comprising: defining a distribution tree covering the root emulation chip and the plurality of branch emulation chips, wherein the distribution tree comprises a plurality of branch interconnections of the interconnect mesh, wherein each branch interconnection connects either two branch emulation chips or a branch emulation chip and the root emulation chip, wherein the distribution tree is configured to carry a start stepping message away from the root emulation chip, and wherein each branch emulation chip is configured to receive the start stepping message from only one of either the root emulation chip or a branch emulation chip; calculating, for each branch emulation chip, a distance in time between the branch emulation chip and the root emulation chip; transmitting the start stepping message to the distribution tree from the root emulation chip; delaying, for each of the plurality of branch emulation chip a start of emulation stepping for a number of clock cycles, the number of clock cycles for each of a selected one of the plurality of branch emulation chips being a difference between (i) a number selected to be greater than or equal to a maximum distance in time, the maximum distance in time being a number of clock cycles from the root emulation chip to a lowest branch of the plurality of branch emulation chips, and (ii) a distance in time, the distance in time being a number of clock cycles from the root emulation chip to the selected one of the plurality of branch emulation chips and the root emulation chip; and delaying, for the root emulation chip, the start of emulation stepping for a predetermined number, the predetermined number of clock cycles being a number selected to be greater than or equal to the maximum distance in time, so that emulation starts synchronously in the root emulation chip and each branch emulation chip.