Patent ID: 9256536
Filing Date: 2016-02-09
CPC Classification: G06F

Claim Text:
1. A method of providing data of a memory address, comprising: determining whether the data is present in a first cache or a second cache of a cache memory system; reading the data from the first cache or the second cache in response to the data being determined to be present in the first cache or the second cache, respectively; in response to the cache memory system being operated in a first mode, using the first cache and the second cache independently; in response to the cache memory system being operated in a second mode, sharing the first cache and the second cache; and in response to the cache memory system alternating from the first mode to the second mode, maintaining a number of tag bits to be consistant and increasing a number of set index bits by one, wherein bits representing the memory address comprise at least one bit overlapping between the tag bits and the set index bits, and tag data is a fixed size.