Patent ID: 9319186
Filing Date: 2016-04-19
CPC Classification: H04L

Claim Text:
1. An integrated circuit with on-die instrumentation for obtaining bit error data for an eye-opening diagram, the integrated circuit comprising: a voltage multiplexer for selecting a reference voltage from a high reference voltage and a low reference voltage; a clock multiplexer for selecting a clock signal from an even clock signal and an odd clock signal; a first sense amplifier circuit for slicing an input data signal using a first slicing voltage at times indicated by said clock signal to generate a speculative-high error signal, wherein said first slicing voltage comprises said reference voltage increased by a speculative voltage; and a second sense amplifier circuit that slices the input data signal using a second slicing voltage at times indicated by said clock signal to generate a speculative-low error signal, wherein said second slicing voltage comprises said reference voltage reduced by the speculative voltage.