Patent ID: 9396787
Filing Date: 2016-07-19
CPC Classification: G06F,G11C,H01L

Claim Text:
1. A memory device comprising: a memory stack including one or more coupled memory elements; and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip; wherein the memory controller is to obtain thermal values of the one or more thermal sensors, the logic chip to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic chip; and wherein a refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.