Patent ID: 9350529
Filing Date: 2016-05-24
CPC Classification: H04L

Claim Text:
1. A system comprising: a driver circuit configured to receive a source data and output a first voltage at a first node; a transmission line having a characteristic impedance configured to couple the first node to a second node; a three-point three-level slicer circuit configured to receive a second voltage at the second node and output a first ternary signal, a second ternary signal, and a third ternary signal in accordance with a first reference voltage, a second reference voltage, a first clock, a second clock, and a third clock; and a CDR (clock-data recovery) circuit configured to receive a reference clock, the first ternary signal, the second ternary signal, and the third ternary signal and output a recovered data, the first reference voltage, the second reference voltage, the first clock, the second clock, and the third clock.