Patent ID: 9343567
Filing Date: 2016-05-17
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a substrate; a gate positioned on the substrate; a drain region and a source region formed at two respective sides of the gate in the substrate, the drain region further comprising a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region, the first conductivity type and the second conductivity type being complementary to each other; a first well region formed under the first doped region, the first well region comprising the first conductivity type; a second well region formed under the second doped region, the second well region comprising the first conductivity type; and a third well region formed under the third doped region, the third well region comprising the first conductivity type, wherein a concentration of the second well region is different from a concentration of the third well region.