Patent ID: 9276088
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A method comprising: forming first and second pluralities of silicon fins on an upper surface of a substrate layer, separated by a space, wherein each pair of adjacent silicon fins is separated by a trench along the upper surface of the substrate layer; forming an oxide layer on the upper surface of the substrate layer and filling in a portion of each trench along the upper surface of the substrate layer; forming first and second deep isolation trenches into the oxide layer and into the substrate layer adjacent to the first and second pluralities of silicon fins; forming a graded voltage junction by implanting one or more concentration levels of a dopant into the substrate layer below each of the first and second pluralities of silicon fins; forming a gate structure on an upper surface of the oxide layer, positioned at the space between the first and second pluralities of silicon fins; implanting a dopant into and under the first and second pluralities of silicon fins, forming source and drain regions, respectively; and forming an epitaxial layer onto the first and second pluralities of silicon fins to form merged source and drain fins, respectively.