Patent ID: 9385044
Filing Date: 2016-07-05
CPC Classification: H01L

Claim Text:
1. A method of forming an integrated circuit, comprising the steps: providing a substrate comprising semiconductor material; forming a gate dielectric layer over said substrate; forming sacrificial gates over said gate dielectric layer; forming a chemical mechanical polish (CMP) stop layer over said sacrificial gates; forming a dielectric fill layer over said CMP stop layer, said dielectric fill layer filling spaces between said sacrificial gates; performing a first oxide CMP process which removes dielectric material from said dielectric fill layer, planarizes a top surface of said dielectric fill layer and exposes said CMP stop layer over said sacrificial gates without removing material from said sacrificial gates; performing a selective plasma etch process which removes said CMP stop layer and so as to expose said sacrificial gates, wherein said selective plasma etch process removes material from said CMP stop layer at least twice as quickly as material from said dielectric fill layer; removing said sacrificial gates to form gate cavities; performing a second oxide CMP process which lowers a top surface of said dielectric fill layer without removing material from said sacrificial gates, after said step of performing said selective plasma etch process which removes said CMP stop layer and prior to said step of removing said sacrificial gates; and forming replacement metal gates in said gate cavities.