Patent ID: 9460763
Filing Date: 2016-10-04
CPC Classification: G06F,G11C

Claim Text:
1. A memory access device, comprising: multiple CPUs using a memory as main memories; other functional blocks using the memory as a data buffer; a CPU interface circuit to control memory access requests from the multiple CPUs; and, a memory controller coupled to the CPU interface circuit, wherein: the CPU interface circuit holds the memory access requests from the multiple CPUs, notifies the memory controller of the memory access requests, and on receiving an Allowed signal for the memory access requests, sends the information to the memory controller, and on not receiving the Allowed signal for the memory access requests, holds awaiting the memory access requests from the multiple CPUs; and the memory controller receives the memory access request signals, specifies a CPU whose memory access requests are allowed from access arbitration, and sends the Allowed signal to the CPU interface circuit and executes the multiple CPU memory access requests in one bus cycle, wherein in response to a data flow transfer of the other functional blocks being performed, the memory controller holds the multiple CPU memory access requests, and after completion of the data flow transfer performs the multiple CPU memory access requests in one transfer cycle.