Patent ID: 9324726
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate; (b) forming, in a first region of a first main surface of the semiconductor substrate, a first insulation film at the first main surface of the semiconductor substrate, and forming, in a second region of the first main surface of the semiconductor substrate, a second insulation film at the same layer as the first insulation film at the first main surface of the semiconductor substrate; (c) forming a first conductive film over the first insulation film, and forming a second conductive film at the same layer as the first conductive film over the second insulation film; (d) patterning the first conductive film, thereby forming a first gate electrode formed of the first conductive film, forming a first gate insulation film formed of the first insulation film between the first gate electrode and the semiconductor substrate, and leaving the second conductive film; (e) forming a third insulation film having a charge accumulation part in the inside thereof at the first main surface of the semiconductor substrate, and the surface of the first gate electrode in the first region; (f) forming a third conductive film over the third insulation film; (g) etching back the third conductive film, and thereby leaving the third conductive film over the sidewall of the first gate electrode via the third insulation film, and forming a second gate electrode; (h) removing the third insulation film at a portion thereof not covered with the second gate electrode, and leaving the third insulation film between the second gate electrode and the semiconductor substrate, and, between the first gate electrode and the second gate electrode; (i) removing the second conductive film; (j) after the step (h) and the step (i), forming a first semiconductor region of a first conductivity type in the first main surface of the semiconductor substrate in the second region; (k) forming a fourth insulation film over the first semiconductor region; (l) forming a fourth conductive film over the fourth insulation film; and (m) patterning the fourth conductive film, and thereby forming a third gate electrode formed of the fourth conductive film, and forming a second gate insulation film formed of the fourth insulation film between the third gate electrode and the first semiconductor region.