Patent ID: 9337109
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. An integrated circuit device comprising: a first transistor including a first strained channel region, the first strained channel region disposed between first source/drain regions, the first source/drain regions formed from a first III-V semiconductor material; and a second transistor including a second strained channel region, the first strained channel region and the second strained channel region being subjected to opposite strains, the second strained channel region disposed between second source/drain regions, the second source/drain regions formed from a second III-V semiconductor material, the first III-V semiconductor material and the second III-V semiconductor material being a same material with different stoichiometric ratios, wherein the first strained channel region and the second strained channel region comprises a same III-V semiconductor material having a same stoichiometric ratio, and wherein the first transistor and the second transistor are each an n-type field effect transistor (FET).