Patent ID: 9366932
Filing Date: 2016-06-14
CPC Classification: G02F

Claim Text:
1. A TFT-LCD array substrate manufacturing method comprising the steps of: a) forming a gate electrode, a gate electrode insulator layer, an active layer comprising an amorphous silicon layer and an ohmic contact layer, a source electrode and a drain electrode on top of the active layer, a passivation layer, and a passivation layer via on top of the drain electrode sequentially on a glass substrate; b) depositing an ITO film on the glass substrate processed by the step a), coating a photo resist on the ITO film; c) exposing the photo resist on the ITO film using an ITO mask and UV ray so that, in a TFT area, the photo resist coated in the passivation layer via and its vicinity is not exposed, and the photo resist coated in the other part is fully exposed and, in a pixel area, the photo resist coated on a desired ITO electrode is not exposed, and the photo resist coated on gaps to be formed among the ITO electrode is partially exposed, where the ITO mask is one of a single slit mask (SSM), a gray tone mask, and a half tone mask; d) developing and removing the photo resist in the TFT area outside the passivation layer via and a part of the photo resist in the pixel area where gaps are to be formed so as to reveal the ITO film outside the passivation layer via in the TFT area; e) removing a remaining photo resist in the pixel area where gaps are to be formed from the step d) using a fourth dry etch, so that the ITO film on the gaps to be formed is revealed; f) removing the ITO film revealed by the steps d) and e) using a third wet etch so that the gaps are no more than 1.9 μm; and g) peeling the photo resist not yet removed, and forming an ITO electrode that is connected to the passivation layer via.