Patent ID: 9319041
Filing Date: 2016-04-19
CPC Classification: H03K

Claim Text:
1. A squelch detector, comprising: a first differential pair circuit receiving a first input signal and a second input signal, and generating a first current and a second current to a first node and a second node, respectively; a second differential pair circuit receiving the first input signal and the second input signal, and generating a third current and a fourth current to a third node and a fourth node, respectively; a reference differential pair circuit receiving a first reference voltage and a second reference voltage, and generating a first reference current and a second reference current to a fifth node and a sixth node, respectively; a first current mirror, wherein a current input terminal of the first current mirror is connected with the fifth node for receiving the first reference current, a first current mirroring terminal of the first current mirror is connected with the first node, and a second current mirroring terminal of the first current mirror is connected with the fourth node; a second current mirror, wherein a current input terminal of the second current mirror is connected with the sixth node for receiving the second reference current, a first current mirroring terminal of the second current mirror is connected with the second node, and a second current mirroring terminal of the second current mirror is connected with the third node; a first current-to-voltage converter connected with the first node and the second node, and generating a first output signal and a second output signal according to a current change of the first node and the second node; a second current-to-voltage converter connected with the third node and the fourth node, and generating a third output signal and a fourth output signal according to a current change of the third node and the third node; and a judging circuit receiving the first output signal, the second output signal, the third output signal and the fourth output signal, and generating a detected signal to indicate whether the first input signal and the second input signal are valid.