Patent ID: 9324857
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a p-type semiconductor layer; n-type column regions arranged in a mutually spaced-apart relationship along a predetermined direction parallel to a front surface of the semiconductor layer, each of the n-type column regions formed of thermal donors exhibiting an n-type property; a p-type column region of the semiconductor layer interposed between the n-type column regions adjoining to each other, the n-type column regions configured to form a super-junction structure in the semiconductor layer in cooperation with the p-type column region; a channel region of an n-type or p-type selectively formed in a front surface portion of the semiconductor layer to make up a portion of the front surface of the semiconductor layer; a source region selectively formed in a front surface portion of the channel region to make up a portion of the front surface of the semiconductor layer, a conductivity type of the source region being opposite to that of the channel region; a gate insulator film formed on the front surface of the semiconductor layer; and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film, wherein H