Patent ID: 9520187
Filing Date: 2016-12-13
CPC Classification: G06F,G11C,H01L

Claim Text:
1. An electronic device comprising a semiconductor memory, the semiconductor memory including: a mat region configured to include a plurality of memory cells coupled with first wires; and a switching region configured to control coupling between the first wires and an external region in transfer of data stored in the memory cells, wherein the mat region comprises: first active regions formed in a substrate, extended in a second direction, and arranged in a first direction crossing the second direction; a first gate extended in the first direction across the first active regions; stack structures respectively disposed over the first active regions on a first side of the first gate, each stack structure including a first lower contact, a variable resistance element, and a first upper contact; and wire contacts disposed over every first active regions on a second side of the first gate, and fourth wires, wherein the first wires are coupled with one of the stack structures and the wire contacts and extended in the second direction, and the fourth wires coupled with the other of the stack structures and the wire contacts and extended in the second direction.