Patent ID: 9257155
Filing Date: 2016-02-09
CPC Classification: G11C

Claim Text:
1. A memory device comprising: a voltage generation circuit coupled to a first bit line of a plurality of bit lines, wherein the voltage generation circuit comprises a plurality of transistors coupled in parallel to the first bit line, wherein each of the plurality of transistors is coupled to first control circuitry and a respective voltage source, wherein the first control circuitry controls each of the plurality of transistors to switch between an on state and an off state, wherein the on state causes a respective transistor to electrically connect its respective voltage source to the first bit line, and wherein the off state causes a respective transistor to electrically disconnect its respective voltage source from the first bit line; a coupling circuit coupled to the first bit line and a second bit line of the plurality of bit lines; and a selection circuit coupled to the first bit line and the second bit line.