Patent ID: 9491151
Filing Date: 2016-11-08
CPC Classification: G06F,G09C,G11C,H02M,H03K,H04L,Y02B

Claim Text:
1. A charge pump circuit, comprising: a plurality of delay units coupled in series, wherein the delay units respectively generate a plurality clock signals by delaying an output clock signal in sequence; a latch circuit, coupled to the delay units, receiving a final stage clock signal of the clock signals generated by the delay units and receiving a latch enable signal, wherein the latch circuit decides whether to latch the final stage clock signal or not to generate the output clock signal according to the latch enable signal; and a plurality of charge pump units are coupled in series, wherein a first stage of the charge pump unit receives an input voltage, and the charge pump units operate a voltage pumping operation on the input voltage to generate an output voltage according to the clock signals and the output clock signal.