Patent ID: 9417284
Filing Date: 2016-08-16
CPC Classification: G01R

Claim Text:
1. An integrated circuit die comprising: (a) a bottom surface including bottom parallel test input signal contact points, bottom parallel test output signal contact points, a test clock in signal contact point, a test mode select in signal contact point, a test reset in signal contact point, a bottom test data in signal contact point, and a bottom test data out signal contact point; (b) a top surface including top parallel test output signal contact points, top parallel test input signal contact points, a test clock out signal contact point, a test mode select out signal contact point, a test reset out signal contact point, a top test data out signal contact point, a top test data in signal contact point, and an UP signal contact point; (c) TAP lock circuitry having a test clock input coupled with the test clock in signal contact point, a test mode select input coupled with the test mode select in signal contact point, a test reset input coupled with the test reset in signal contact point, a test clock output, and a test mode select output; (d) test circuitry having a clock input coupled to the test clock output, a mode select input coupled to the test mode select output, a test reset input coupled to the test reset in signal contact point, and an input coupled to the bottom test data in signal contact point, and having control outputs; (e) scan circuitry having an input coupled to the bottom test data in signal contact point, an output coupled to the bottom and top test data out signal contact points, and having control inputs coupled with the control outputs of the test circuitry; and (f) UP control circuitry having control inputs coupled with the control outputs of the test circuitry, an input coupled with the test reset in signal contact point, and an output coupled with the UP signal contact point.