Patent ID: 9437252
Filing Date: 2016-09-06
CPC Classification: G11C

Claim Text:
1. A semiconductor memory apparatus comprising: a plurality of stack bank structures, the plurality of stack bank structures being spaced apart from each other at a predetermined interval and including a plurality of sub-banks; a plurality of control blocks, wherein each control block configured to control all column-related signals of the plurality of sub-banks constituting each stack bank structure; and a plurality of global input/output lines arranged between the stack bank structures, wherein each of the plurality of control blocks includes an address control block and an Input/Output control block, the address control block is arranged between the plurality of sub banks constituted in each of the plurality of stack bank structures, the Input/Output control block is arranged at one side of each of the plurality of stack bank structures, and the address control block includes a main decoder and a predecoder.