Patent ID: 9261558
Filing Date: 2016-02-16
CPC Classification: G01R

Claim Text:
1. An interposer comprising: A. a test access port having a test data input lead, a test data output lead, a test clock lead, a test mode select lead, and test control leads; B. functional circuitry leads including an address bus, a data bus, and control signal leads; C. monitor trigger circuitry having inputs coupled to the address bus, the data bus, and the control signal leads, the test data input lead, and the test control leads, and having an output coupled to the test data output lead, a clock output, a start output, and an enable output; and D. monitor circuitry having inputs coupled to the functional circuitry leads, inputs coupled to the clock output, the start output, the enable output, an input coupled to the test data input lead, an input coupled to the test control leads, and an output coupled to the test data output lead.