Patent ID: 9306062
Filing Date: 2016-04-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a semiconductor substrate; a body layer disposed in the semiconductor substrate; a plurality of cell regions, each comprising a source region arranged around a surface layer part of the body layer; first trenches arranged in a grid pattern and having a constant width, for separating the plurality of cell regions from each other; a second trench disposed at an outermost circumference of the plurality of cell regions; a gate insulating film for covering inner walls of the first trenches and an inner wall of the second trench; a gate electrode that fills the first trenches and the second trench covered by the gate insulating film; a cell circumferential region disposed to surround an outer side of the second trench; an interlayer insulating film disposed on the plurality of cell regions, the first trenches, and the second trench; a gate contact hole disposed in the interlayer insulating film at an intersection of the first trenches arranged in the grid pattern, the gate contact hole not being provided on the second trench; and a gate wiring connected to the gate electrode via the gate contact hole.