Patent ID: 9436634
Filing Date: 2016-09-06
CPC Classification: G06F

Claim Text:
1. A system, comprising: means for exchanging data words via one or more predetermined storage locations to at least convey queue pointer update information between a host bus adapter and a host bus coupled mass storage device; means for conveying mass storage device auxiliary control information between the host bus adapter and the mass storage device via the exchanged data words, at the same rate and latency employed to the convey the queue pointer update information, and without requiring additional data exchanges or storage locations beyond those already employed to convey the queue pointer update information; and wherein each of the data words comprise a first number of bits that is a native data unit width of a host processing element, the queue pointer update information requires at most a second number of bits that is less than the first number of bits, and the auxiliary control information requires a third number of bits that is no more than the difference of the first number of bits less the second number of bits.