Patent ID: 9383409
Filing Date: 2016-07-05
CPC Classification: G01R

Claim Text:
1. A method for implementing a scan chain to test a semiconductor, the method comprising: obtaining an initial structure of the scan chain; determining, according to function modules of the semiconductor corresponding to scan registers on the scan chain, at least one scan register pair with backward dependency; adjusting the initial structure of the scan chain such that the at least one scan register pair with backward dependency becomes a scan register pair with forward dependency; and determining a key subset of a fan-out scan register in the at least one scan register pair with backward dependency, wherein a fan-in scan register in the at least one scan register pair with backward dependency belongs to the key subset of the fan-out scan register, wherein logic values of all fan-in scan registers in the key subset and a logic value of an output of a function module connected to the fan-out scan register are the same, no matter which logic values are taken by fan-in scan registers outside the key subset.