Patent ID: 9324832
Filing Date: 2016-04-26
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: forming an isolation layer pattern on a substrate to define an active fin protruding from the isolation layer pattern; sequentially forming a dummy gate layer structure and a mask layer on the active fin and the isolation layer pattern; patterning the mask layer to form a plurality of masks, each of the masks extending in a first direction; forming spacers on opposed sidewalls of each mask; forming a dummy gate mask between the spacers; patterning the dummy gate layer structure using the dummy gate mask as an etching mask to form a plurality of dummy gate structures, each of the dummy gate structures extending in the first direction; and replacing the dummy gate structure with a gate structure, wherein patterning the mask layer to form the plurality of masks includes: designing a plurality of initial mask layouts, each extending in the first direction; providing an offset bias in a second direction that is substantially perpendicular to the first direction for specific regions of respective ones of at least some of the initial mask layouts using a marker to design a plurality of final mask layouts, each having a width in the second direction that varies along the first direction; and patterning the mask layer according to the final mask layouts to form the plurality of masks, each of the plurality of masks having a width in the second direction that varies along the first direction.