Patent ID: 9274860
Filing Date: 2016-03-01
CPC Classification: G06F

Claim Text:
1. A data storage device, comprising: a nonvolatile memory; and a controller to control the nonvolatile memory, wherein the controller of the data storage device includes: the DMA is to manage data exchange between the first processor and the second processor through the bus using the first memory and the second memory when an inter-process communication (IPC) operation is performed, wherein the first memory includes a first transmission region to store a first data to be transmitted to the second memory and a first reception region to store a second data received from the second memory, and the second memory includes a second transmission region to store the second data to be transmitted to the first memory and a second reception region to store the first data received from the first memory, and the DMA includes a buffer to temporarily store data received from at least one of the first transmission region and the second transmission region, wherein the IPC operation including: a first writing operation during which the first processor stores the first data in the first transmission region from the first register of the first processor, and a second writing operation during which the second processor stores the second data in the second transmission region from the second register of the second processor.