Patent ID: 9449687
Filing Date: 2016-09-20
CPC Classification: G11C

Claim Text:
1. A sense circuit, comprising: sample and hold circuitry operably coupled to a data sense line and configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal being applied to a resistance variable memory cell, the evaluation signal including a second signal corresponding to the second response voltage potential, a first signal corresponding to the first response voltage potential, and a third signal corresponding to the third response voltage potential, wherein the third signal causes the resistance variable memory cell to transition from a first data state to a second data state; and a switched capacitor amplifier operably coupled to the sample and hold circuitry and configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential.