Patent ID: 9412655
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A method comprising: forming a plurality of sacrificial lines embedded in a first dielectric layer formed above a substrate; forming a hard mask layer above said first dielectric layer and said plurality of sacrificial lines; forming a line merge opening and a line cut opening in said hard mask layer; removing portions of said first dielectric layer exposed by said line merge opening to define a line merge recess; removing a portion of a selected sacrificial line exposed by said line cut opening to define a line cut recess between first and second segments of said selected sacrificial line; forming a second dielectric layer in said line cut recess; removing said hard mask; and replacing said plurality of sacrificial lines with a conductive material to define at least one line having third and fourth segments in locations previously occupied by said first and second segments, respectively, of said selected sacrificial line and to define a line-merging conductive structure in said line merge recess.