Patent ID: 9293360
Filing Date: 2016-03-22
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor memory device, the method comprising: forming a tunnel insulating layer and a first conductive layer configured as a floating gate in an active region of a semiconductor substrate, and forming a trench in an isolation region of the semiconductor substrate; filling the trench with a sacrificial layer having a top surface higher than a surface of the semiconductor substrate; forming a first oxide layer along an entire surface of a resultant structure filled with the sacrificial layer; forming an air gap in the isolation region by generating plasma and removing the sacrificial layer while maintaining the first oxide layer, wherein the sacrificial layer passes through the first oxide layer; transforming a portion of the first oxide layer into a first nitride layer; forming a second nitride layer and a second oxide layer over the first oxide layer; and forming a second conductive layer configured as a control gate on the second oxide layer.