Patent ID: 9239755
Filing Date: 2016-01-19
CPC Classification: G06F,G11C

Claim Text:
1. A semiconductor device comprising: a parity-bit generator configured to generate a parity bit signal according to a parity-bit selection signal; a selector configured to select one of the parity bit signal and a data mask signal in response to a selection signal, and to output the selected signal through a transfer path between the selector and a channel, wherein the data mask signal is transmitted through the transfer path in a write operation; and a decoder configured to receive the data mask signal from the channel and decode the data mask signal during the write operation when the selection signal has a first logic value, wherein the selector selects the parity bit signal received from the parity-bit generator and outputs the selected parity bit signal to the transfer path, during a read operation when the selection signal has a second logic value.