Patent ID: 9378561
Filing Date: 2016-06-28
CPC Classification: G06T,H04N

Claim Text:
1. An apparatus comprising: a decoder circuit configured to generate a first intermediate signal having a plurality of coefficients of a target layer and a plurality of coefficients of a base layer, in response to an input bitstream; a memory circuit configured to (i) store said first intermediate signal and (ii) present (a) a second intermediate signal comprising said plurality of coefficients of said target layer and (b) a third intermediate signal comprising said plurality of coefficients of said base layer; and a processing circuit configured to (i) read said second intermediate signal and said third intermediate signal from said memory circuit, (ii) switch a plurality of times between said coefficients of said target layer and said coefficients of said base layer while reading a frame from said memory circuit, (iii) transform said coefficients of said base layer into base layer information, (iv) buffer said base layer information, wherein said base layer information buffered at any time comprises at most a subset of macroblock rows of said frame and (v) generate an output signal comprising a plurality of target layer samples in response to said second intermediate signal and said base layer information as buffered.