Patent ID: 9293219
Filing Date: 2016-03-22
CPC Classification: G11C

Claim Text:
1. A non-volatile memory circuit comprising: a plurality of storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal only during data reading; and wherein cathodes of respective zener zap devices of the plurality of storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plurality of storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage only during data writing, wherein the switch section is switched ON only during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector; and wherein the detector comprises a negative feedback circuit that restricts a voltage on the input terminal so as to lie within a predetermined amplitude.