Patent ID: 9397194
Filing Date: 2016-07-19
CPC Classification: G02F,G09G,H01L

Claim Text:
1. A method for manufacturing a semiconductor device, comprising steps of: forming a gate electrode over an insulating surface; forming a gate insulating layer over the gate electrode by sputtering; forming a first semiconductor layer over the gate insulating layer by sputtering without exposure to air after forming the gate insulating layer; forming a second semiconductor layer over the first semiconductor layer by sputtering; and patterning the second semiconductor layer to form a source region and a drain region over the first semiconductor layer, wherein the first semiconductor layer is an oxide semiconductor layer, and wherein the source region and the drain region are oxide semiconductor layers containing indium, gallium, and zinc, and have a lower oxygen concentration than the first semiconductor layer, and wherein the source region and the drain region include a crystal grain with a size of 1 nm to 10 nm.