Patent ID: 9252095
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a package substrate including at least one non-metallized hole; at least one lower conductive pattern on a bottom surface of the package substrate; at least one semiconductor chip mounted on the package substrate in a flip-chip bonding manner; and a mold layer on the package substrate, the mold layer including, a lower mold portion including a first mold side surface and connected to the upper mold portion through the at least one non-metallized hole to cover at least a portion of the bottom surface of the package substrate and expose at least a portion of the lower conductive pattern, and the lower mold portion including a mold bottom surface defining a lower mold hole exposing the at least one portion of the lower conductive pattern; and at least one lower solder ball on the lower conductive pattern, the at least one lower solder ball being in direct contact with the first mold side surface.