Patent ID: 9515050
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. An electronic apparatus comprising: a first semiconductor component including a second semiconductor component including a through electrode configured to go through the first multilayer wiring structure, the first insulation member, the adhesion layer, the second multilayer wiring structure, and the second insulation member; wherein the first multilayer wiring structure is formed on the one surface of the first insulation member, wherein the one surface of the first insulation member is substantially flush with the first electrode pad forming surface, wherein a length between the first electrode pad forming surface and the first back surface is equivalent to a film-thickness of the first insulation member, wherein the through electrode includes a through hole and a through electrode body provided in the through hole, wherein the through hole is formed to go through the first multilayer wiring structure, the first insulation member, the adhesion layer, the second multilayer wiring structure, the second insulation member, the first patterned wiring, and the second patterned wiring, wherein the through electrode body includes a plating continuously formed on an inner surface of the through hole, and a resin filled in the through hole, wherein the plating is directly connected to the first patterned wiring and the second patterned wiring exposed in the inner surface of the through hole, wherein the through electrode includes at one end a first external connection pad and at the other end a second external connection pad, wherein the first external connection pad is provided on a plane of the first multilayer wiring structure, the first external connection pad provided on the through electrode body and the resin, wherein the second external connection pad is provided on a plane of the second insulation member, the second external connection pad provided on the through electrode body and the resin, wherein the plane of the first multilayer wiring structure is covered by a first solder resist layer, wherein the first solder resist layer includes a first opening from which the first external connection pad is exposed to the outside of the electronic apparatus, wherein the plane of the second insulation member is covered by a second solder resist layer, wherein the second solder resist layer includes a second opening from which the second external connection pad is exposed to the outside of the electronic apparatus, wherein the first opening is formed on a first end of the through hole and the second opening is formed on a second end of the through hole, wherein the first external connection pad closes the first opening and is connected to the through electrode body on the one end of the through electrode, wherein the second external connection pad closes the second opening and is connected to the through electrode body on the other end of the through electrode, wherein the first electronic part and the second electronic part are electrically connected to each other by way of the direct connection between the plating and the first and second patterned wirings.