Patent ID: 9299615
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A method of forming a multiple threshold voltage (V T ) device structure, the method comprising the steps of: forming an alternating series of channel layers and barrier layers as a stack on a side of a buried oxide (BOX) opposite a substrate, wherein the stack comprises at least one first channel layer present over at least one first barrier layer, and at least one second channel layer present below the at least one first barrier layer, wherein the at least one first channel layer comprises a first III-V material and the at least one second channel layer comprises a second III-V material, and wherein the first III-V material has a different electron affinity from the second III-V material; defining at least one first active area and at least one second active area in the stack; selectively removing the at least one first channel layer and the at least one first barrier layer from the at least one second active area, such that the at least one first channel layer is a top-most layer in the stack in the at least one first active area, and the at least one second channel layer is a top-most layer in the stack in the at least one second active area, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area; and forming at least one first gate on the at least one first channel layer in the at least one first active area, and at least one second gate on the at least one second channel layer in the at least one second active area, wherein the at least one first channel layer serves as a channel of a first field effect transistor (FET) in the at least one first active area, and the at least one second channel layer serves as a channel of a second FET in the at least one second active area, and wherein the first FET has a different V