Patent ID: 9253276
Filing Date: 2016-02-02
CPC Classification: H04L

Claim Text:
1. A protocol bridge comprising: a processor; memory connected to the processor; a plurality of PHYs, at least two of the plurality of PHYs configured to connect to at least two separate data storage devices, and at least one of the plurality of PHYs configured to connect to at least one initiator device; and computer executable program code configured to execute on the processor, wherein: the computer executable program code configures the processor to: cache data from two or more data storage devices in the memory; receive a first IO request from a first initiator in data communication with the processor through one of the plurality of PHYs; retrieve data identified by the first IO request from a first data storage device connected to one or more of the plurality of PHYs; write the data identified by the first IO request to the memory; send the data identified by the first IO request to the first initiator; receive a second IO request from a second initiator in data communication with the processor, wherein the second IO request identifies the same data identified by the first IO request; retrieve the data identified by the second IO request from the memory; and send the data identified by the second IO request to the second initiator; wherein the computer executable program code further configures the processor to: