Patent ID: 9425294
Filing Date: 2016-08-23
CPC Classification: H01L

Claim Text:
1. A manufacturing method of a display array substrate, comprising: providing a substrate having a display area and a peripheral area; depositing a first metal layer on the substrate; coating a photo-resist layer on a portion of the first metal layer located in the peripheral area; anodizing the first metal layer to form a first metal oxide layer by utilizing the photo-resist layer as a mask, wherein the first metal oxide layer in the display area forms a gate insulator and the first metal oxide layer in the peripheral area forms a first insulation layer; removing the photo-resist layer to expose the first metal layer in the peripheral area; forming a channel layer on the gate insulator; and depositing a second metal layer in a pattern to form a source electrode and a drain electrode in the display area, and form a pad electrode in the peripheral area.