Patent ID: 9515024
Filing Date: 2016-12-06
CPC Classification: H01L

Claim Text:
1. A manufacturing method comprising: (1) obtaining a structure comprising: a planar insulating layer having a first planar surface and a second planar surface opposite to the first planar surface; a first semiconductor layer having a planar surface contacting the first planar surface of the planar insulating layer; and a second semiconductor layer having a planar surface contacting the second planar surface of the planar insulating layer; (2) forming one or more through vias each of which passes through the first and second semiconductor layers and the planar insulating layer; and (3) forming a conductor in each through via, the conductor providing a conductive path in the through via between the first and second semiconductor layers; wherein each through via comprises: a respective first via portion passing through the first semiconductor layer and formed in operation (2) by removing part of the first semiconductor layer from a side opposite to the second semiconductor layer; and a respective second via portion passing through the second semiconductor layer and formed in operation (2) by removing part of the second semiconductor layer from a side opposite to the first semiconductor layer; wherein in each through via, the conductor comprises a first conductor portion present in the respective first via portion but not in the respective second via portion, and comprises a second conductor portion present in the respective second via portion but not in the respective first via portion; wherein the method further comprises thinning the second semiconductor layer before forming any second via portion but after forming each first via portion and each first conductor portion.