Patent ID: 9397205
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A semiconductor device, comprising: a substrate having a first conductivity type; a first doped well having a second conductivity type and disposed in the substrate; a second doped well having the first conductivity type and disposed in the substrate adjacent to a first side of the first doped well; a buffer region having the second conductivity type and disposed in the first doped well adjacent to a second and opposite side of the first doped well; a gate structure disposed above the first side of the first doped well and extending along a first horizontal direction; a first contact region having the first conductivity type and disposed in the buffer region toward the second side of the first doped well; a second contact region having the second conductivity type and disposed in the buffer region adjacent to the first contact region; and a doped region having the second conductivity type and disposed in the buffer region under the first contact region.