Patent ID: 9355915
Filing Date: 2016-05-31
CPC Classification: B82Y,H01L

Claim Text:
1. A method for integrated circuit (IC) manufacturing, the method comprising: providing a substrate having a metal-oxide-semiconductor (MOS) region, wherein the MOS region includes first gate, source, and drain regions for a first device, and second gate, source, and drain regions for a second device, and wherein the first gate region has a first length, and the second gate region has a second length that is different from the first length; forming a first fin in the first gate region; forming a second fin in the second gate region; forming a first semiconductor layer stack over the first fin; forming a second semiconductor layer stack over the second fin; and performing a thermal oxidation process to the first and second semiconductor layer stacks, thereby forming first and second nanowire sets in the first and second gate regions respectively, wherein the first and second nanowire sets are wrapped by respective semiconductor oxide layers, wherein the first nanowire set has a first diameter, and wherein the second nanowire set has a second diameter that is different from the first diameter.