Patent ID: 9478310
Filing Date: 2016-10-25
CPC Classification: G09G,G11C

Claim Text:
1. A shift register unit comprising an input module, a pulling-up module, a first control module, a second control module, a first reset module and a pulling-down module; wherein the input module is configured to control a level at a pulling-up control node according to a signal inputted from a first signal terminal; the pulling-up module is configured to control an output terminal to output a third level signal according to a signal inputted from a first clock signal terminal and the level at the pulling-up control node; the first control module is configured to control a level at a pulling-down control node according to a signal inputted from a third clock signal terminal and the level at the pulling-up control node; the second control module is configured to control the level at the pulling-down control node according to the signal inputted from the first clock signal terminal; the first reset module is configured to reset the level at the pulling-up control node according to the level at the pulling-down control node; and the pulling-down module is configured to control the output terminal to output a first level signal according to a signal inputted from a second signal terminal, wherein the first control module comprises a fifth TFT and a sixth TFT; the fifth TFT has a first electrode and a second electrode connected to the third clock signal terminal and a third electrode connected to the pulling-down control node, the sixth TFT has a first electrode connected to the pulling-down control node, a second electrode connected to the pulling-up control node, and a third electrode connected to a first voltage terminal; the second control module comprises a ninth TFT having a first electrode connected to the pulling-down control node, a second electrode connected to the first clock signal terminal, and a third electrode connected to the first voltage terminal; the signal inputted from the first clock signal terminal and the signal inputted from the third clock signal terminal have a duty ratio of ¼, and there is a time delay equal to half of a clock signal therebetween.