Patent ID: 9484945
Filing Date: 2016-11-01
CPC Classification: H03M

Claim Text:
1. A metastability-correcting asynchronous Successive-Approximation Register (SAR) Analog-to-Digital Converter (ADC) comprising: an analog input for receiving an analog signal for conversion to a digital value that represents the analog signal; a sample-and-hold circuit for sampling the analog signal to generate a sampled signal; a Successive-Approximation Register (SAR) for storing and adjusting a digital test value; a Digital-to-Analog Converter (DAC) that receives a sequence of the digital test value from the SAR and generates a DAC voltage represented by the digital test value; a comparator that compares the DAC voltage to the sampled signal to generate a compare result; a valid detector that generates a valid signal when the compare result has reached a valid logic state, the valid detector withholding generation of the valid signal when the comparator has a metastable event and the compare result is metastable and has not yet reached the valid logic state; a bit-conversion-counter that generates a valid count by counting a number of valid signals generated during each system clock period; an end of conversion signal generated by the bit-conversion-counter when the valid count equals a number of bits to be converted; a raw data register in the SAR that captures the compare result from the comparator when the valid signal is generated, wherein the compare result is captured as successive raw data bits for each successive valid signal generated; and a data corrector that generates corrected data from the raw data and the valid count, the data corrector outputting raw data from the raw data register for bits captured by valid signals, and concatenating with forced data values for bits not receiving a valid signal; wherein when the end of conversion signal has been generated when a next system clock period starts, raw data from the raw data register is output as the digital value representing the analog signal; wherein when the end of conversion signal has not been generated when the next system clock period starts, corrected data from the data corrector is output as the digital value representing the analog signal.