Patent ID: 9262318
Filing Date: 2016-02-16
CPC Classification: G06F

Claim Text:
1. A system, comprising: a processor having an address space, wherein the address space includes (i) a first portion allocated to data and (ii) a second portion allocated to code, wherein the processor is configured to generate a request to retrieve information corresponding to an address in the address space; a memory controller module comprising a flash memory module configured to, in response to receiving the flash memory read request, provide the information corresponding to the address to the memory controller module, wherein the second portion of the address space allocated to code includes a first range of addresses corresponding to a main memory and a second range of addresses corresponding to the flash memory module, wherein the first range of addresses and the second range of addresses are different and non-overlapping, and wherein the processor is configured to execute code stored in the flash memory module by accessing the second range of addresses.