Patent ID: 9525060
Filing Date: 2016-12-20
CPC Classification: H01L

Claim Text:
1. An integrated circuit, comprising: a semiconductor substrate; an isolated device disposed in and on the substrate; a lower buried layer disposed in the substrate under the isolated device, the lower buried layer having a conductivity type opposite from a conductivity type of the substrate; a deep trench isolation structure surrounding the isolated device; an upper buried layer disposed in the substrate under the isolated device and over the lower buried layer, the upper buried layer having the same conductivity type as the substrate; and a deep well disposed in the substrate around the isolated device, the deep well extending to and making electrical contact with the lower buried layer, the deep well having the same conductivity type as the lower buried layer, such that: a lateral separation between the deep trench isolation structure and the upper buried layer along a first side of the isolated device is at least one micron wider than a lateral separation between the deep trench isolation structure and the upper buried layer along a second side of the isolated device; the contact between the deep well and the lower buried layer is increased by at least a micron along the first side of the isolated device compared to the contact between the deep well and the lower buried layer along the second side of the isolated device; and a lateral width of the increased contact is less than one half a perimeter of the isolated device.