Patent ID: 9438227
Filing Date: 2016-09-06
CPC Classification: H01L,H03K

Claim Text:
1. A power semiconductor structure, comprising: a trench lined with a gate dielectric comprising three layers, comprising an inner layer, an outer layer, and a middle layer formed between the inner layer and the outer layer; a gate electrode formed within the trench and adjacent to the inner layer; a lightly doped channel of a first conductivity type located next to a first side of the trench and adjacent to the outer layer, wherein the lightly doped channel is doped no more than a first defined doping level; a lightly doped drift region of the first conductivity type located below a second side of the trench, below the channel, and adjacent to the outer layer, wherein the lightly doped drift region is doped no more than a second defined doping level; a cathode region of the first connectivity type located above and adjacent to the channel, and adjacent to the outer layer; a heavily doped region of a second connectivity type located above and adjacent to the cathode region and adjacent to the outer layer, wherein the heavily doped region is doped no less than a third defined doping level; another heavily doped region of the first connectivity type located above and adjacent to the cathode region and adjacent to the heavily doped region of the second connectivity type, wherein the other heavily doped region is doped no less than a fourth defined doping level; and a cathode electrode short connecting the other heavily doped region of the first conductivity type and the heavily doped region of the second conductivity type, wherein the cathode region is connected to the cathode electrode via the other heavily doped region of the first conductivity type.