Patent ID: 9330769
Filing Date: 2016-05-03
CPC Classification: G11C

Claim Text:
1. An operating method of a nonvolatile memory device including at least first through fourth strings on a substrate, each string including a plurality of memory cells and at least one select transistor sequentially stacked on the substrate in a direction perpendicular to the substrate, the operating method comprising: erasing first memory cells of a first portion of the first through fourth strings and preventing erasures of second memory cells of a second portion of the first through fourth strings, select transistors of the first and second strings being connected to a first select line, select transistors of the third and fourth strings being connected to a second select line, select transistors of the first and third strings being connected to a first bit line, and select transistors of the second and fourth strings being connected to a second bit line, wherein each string further includes at least one second select transistor connected between the plurality of memory cells and the substrate, second select transistors of the first and second strings are connected to a third select line, select transistors of the third and fourth strings are connected to a fourth select line, and the erasing includes,