Patent ID: 9368601
Filing Date: 2016-06-14
CPC Classification: H01L

Claim Text:
1. A method for fabricating a semiconductor device, comprising: etching a layered semiconductor material, the layered semiconductor material comprising polysilicon layers above a metal line, the etching etches through the polysilicon layers and down to the metal line, forming polysilicon structures from the polysilicon layers and exposing regions of the metal line, each of the polysilicon structures is a body of a vertical channel transistor; oxidizing the regions of the metal line to provide metal oxide regions; after the oxidizing, depositing a gate insulator material followed by depositing a control gate material; etching through the control gate material and the gate insulator material and down to the metal oxide regions, the etching through forms control gates of the vertical channel transistors from the control gate material, and the etching through forms gate insulators between the polysilicon structures and the control gates from the gate insulator material; etching away the metal oxide regions, the etching away forms voids directly under the control gates; and depositing an insulation material, a portion of the insulation material fills the voids.