Patent ID: 9502336
Filing Date: 2016-11-22
CPC Classification: H01L,H05K

Claim Text:
1. A package assembly comprising: a coreless substrate comprising a first side, a second side opposite to the first side, and a plurality of build-up layers between the first side and the second side; two or more passive device pads disposed on the first side of the coreless substrate, wherein each of the two or more passive device pads has a first surface and a second surface, and, for each of the two or more passive device pads, the second surface is disposed between the first surface and the coreless substrate; an electrical routing feature disposed on the second side of the coreless substrate; a first solder resist layer disposed on the first side of the coreless substrate, wherein the first solder resist layer has a first surface and a second surface, the second surface of the first solder resist layer is disposed between the first surface of the first solder resist layer and the coreless substrate, the two or more passive device pads are disposed within corresponding openings in the first solder resist layer, and the first surfaces of the two or more passive device pads are recessed from the first surface of the first solder resist layer; and an electrical path defined in the plurality of build-up layers to route an electrical power between the two or more passive device pads and the electrical routing feature; wherein the electrical path includes a conductive element disposed on or within the build-up layers and adjacent to the first solder resist layer, the two or more passive device pads being conductively coupled to the conductive element.