Patent ID: 9412684
Filing Date: 2016-08-09
CPC Classification: H01L

Claim Text:
1. A semiconductor package comprising: a lead frame having a first die pad, a first source lead and a first gate lead separated but near the first die pad, wherein the first source lead has a V groove disposed on a top surface of the first source lead, and wherein two sidewalls of the V groove of the first source lead are terminated substantially on a same plane coplanar to the top surface of the first source lead; a first semiconductor chip having a source electrode and a gate electrode on a top surface of the first semiconductor chip and a drain electrode on a bottom surface of the first semiconductor chip, wherein the first semiconductor chip is disposed on the first die pad, and wherein the drain electrode of the first semiconductor chip is electrically attached to a top surface of the first die pad through a conductive adhesive; a first metal plate with a first bent extension, wherein a bottom face of the first metal plate is electrically attached to the source electrode of the first semiconductor chip, wherein the first bent extension is terminated in the V groove of the first source lead, and wherein the first bent extension is in contact with at least one of the V groove sidewalls of the first source lead; a first bond wire electrically connecting the gate electrode of the first semiconductor chip to the first gate lead of the lead frame; and a molding plastic encapsulating the first semiconductor chip, the first metal plate, the first bond wire and the lead frame with a bottom face of the lead frame exposed on a bottom surface of the molding plastic.