Patent ID: 9334576
Filing Date: 2016-05-10
CPC Classification: C25D,H01L,H05K

Claim Text:
1. A wiring substrate comprising: an insulating layer; a wiring layer formed on the insulating layer; a first metal layer formed on the wiring layer; a solder resist layer that wraps around the wiring layer and the first metal layer, and is provided with an open portion that exposes a part of an upper surface of the first metal layer; a second metal layer formed on the upper surface of the first metal layer that is exposed within the open portion; and a third metal layer foamed on the second metal layer, wherein the solder resist layer covers an outer peripheral portion of the upper surface of the first metal layer to expose the part of the upper surface of the first metal layer within the open portion, and wherein an upper surface of the second metal layer is flush with an upper surface of the solder resist layer or projects from the upper surface of the solder resist layer.