Patent ID: 9455267
Filing Date: 2016-09-27
CPC Classification: G11C,H01L

Claim Text:
1. A monolithic three dimensional NAND memory device, comprising: a plurality of control gate electrodes extending in a first direction substantially parallel to a major surface of a substrate in at least one active region, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; an interlevel insulating layer located between the first control gate electrode and the second control gate electrode; a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the major surface of the substrate, such that at least one first portion of each of the plurality of semiconductor channels is located in the first device level, and at least one second portion of each of the plurality of semiconductor channels is located in the second device level; at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels; at least one first slit trench extending substantially perpendicular to the major surface of the substrate; a drain electrode that contacts the first wing portion of the semiconductor channel from above; and a source electrode that contacts the connecting portion of the semiconductor channel from above; wherein: each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region; the semiconductor channel has J-shaped pipe shape; a wing portion of the J-shaped pipe shape semiconductor channel extends substantially perpendicular to the major surface of the substrate and a connecting portion of the J-shaped pipe shape semiconductor channel which connects to the wing portion extends substantially parallel to the major surface of the substrate; the source electrode is located in the first slit trench and has a profile complementary to the nonlinear side wall of the plurality of control gate electrodes; a length of the source electrode extends substantially parallel to the plurality of control gate electrodes and a height of the source electrode extends substantially perpendicular to the major surface of the substrate; a dielectric material is located in the first slit trench to insulate the source electrode from the plurality of control gate electrodes; the drain electrode is electrically connected to a bit line which is located above the semiconductor channel; and the bit line extends substantially perpendicular to the source electrode and substantially parallel to the major surface of the substrate.