Patent ID: 9484272
Filing Date: 2016-11-01
CPC Classification: B82Y,H01L

Claim Text:
1. A method of fabricating a semiconductor device, the method comprising: forming a three-dimensional semiconductor structure on an epitaxial seed layer disposed above a semiconductor substrate, the epitaxial seed layer comprising a semiconductor material different from the three-dimensional semiconductor structure; etching the three-dimensional semiconductor structure to provide a three-dimensional channel region and to expose portions of the epitaxial seed layer on either side of the three-dimensional channel region; forming source and drain regions on either side of the three-dimensional channel region and on the epitaxial seed layer; insulating the three-dimensional channel region and the source and drain regions from the semiconductor substrate by forming an insulating structure comprising one or more isolation pedestals, the insulating structure continuous with the semiconductor substrate; and, subsequently, removing a portion of the epitaxial seed layer; forming a gate electrode stack at least partially surrounding the three-dimensional channel region; and forming a pair of conducting contacts, one contact at least partially surrounding the source region, and another contact at least partially surrounding the drain region, wherein removing the portion of the epitaxial seed layer comprises removing a portion between the source and drain regions and the semiconductor substrate, and wherein the one contact surrounds the source region and the other contact surrounds the drain region.