Patent ID: 9330764
Filing Date: 2016-05-03
CPC Classification: G11C,H01L

Claim Text:
1. A device comprising: a substrate; an array of memory cells on the substrate, including a row/column line; the row/column line including a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate, the semiconductor strip including a semiconductor channel body insulated from the substrate by a layer of dielectric, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, the extension coupled to memory cells in the array; a select line in a second patterned layer crossing the semiconductor channel body; a row/column line select signal generator which produces a select signal, connected to the select line; and a row/column line voltage generator which produces a row/column line voltage, connected to the contact region.