Patent ID: 9312873
Filing Date: 2016-04-12
CPC Classification: G04F,H03M,H04N

Claim Text:
1. An analog-to-digital converter comprising: a sampler to hold a sampled signal obtained by sampling an input signal for each specific time; an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal; a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal level of the sampled signal; a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal; and a second counter to perform a count operation in synchronism with a second clock signal having a higher frequency than the first clock signal after the generation of the prediction signal and to increase or decrease a count value in accordance with the comparison signal.