Patent ID: 9337329
Filing Date: 2016-05-10
CPC Classification: H01L

Claim Text:
1. A method for manufacturing a trenched semiconductor power device comprising a plurality of trenched gates which are insulated by a gate insulation layer and surrounded by a source region, which in turn is encompassed in a body region above a drain region, which in turn is disposed on a bottom portion of a semiconductor substrate, the method comprising: forming each of said trenched gates with a spacer cap on top of the trenched gate and having vertical cap edges substantially aligned with gate sidewalls of the trenched gates, and forming the source region surrounding the trenched gates; opening a source-body contact trench substantially in a middle portion between two of the trenched gates; forming a low resistance metal layer for covering a top surface of the source region wherein the low resistance layer further covers trench sidewalls of the source-body contact trench; filling said source body contact trench with a source contact metal layer for directly contacting the low-resistance metal layer; and wherein the step of forming the source region further comprises a step of forming the source region as a metal silicide source aligned substantially with one edge of the spacer cap on top of the trenched gate.