Patent ID: 9286829
Filing Date: 2016-03-15
CPC Classification: G09G

Claim Text:
1. A display device, comprising: a display panel including a display area, in which pixels are arranged, and a non-display area; a driving circuit on the non-display area of the display panel, the driving circuit being configured to drive the pixels and including a memory cell, the memory cell receiving a first control signal and a second control signal; and a delay circuit on the non-display area of the display panel, the delay circuit being connected to the memory cell of the driving circuit and being configured to delay at least one of the first and second control signals to the memory cell of the driving circuit to provide the first and second control signal to the driving circuit at the same time, wherein programming and erasing of the memory cell is controlled by combinations of the first and second control signals, wherein each of the pixels includes a transistor containing a gate electrode on a substrate, a gate dielectric layer, a semiconductor pattern, and source/drain electrodes, wherein the delay circuit includes a resistor pattern and a capacitor, wherein the resistor pattern includes a lower resistor pattern, a resistor pattern dielectric layer on the lower resistor pattern, and an upper resistor pattern on the resistor pattern dielectric layer, and wherein the capacitor includes a lower electrode, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer.