Patent ID: 9496277
Filing Date: 2016-11-15
CPC Classification: H01L

Claim Text:
1. A vertical-type non-volatile memory device, comprising: a substrate; insulation interlayer patterns and control gate patterns alternately and repeatedly stacked on the substrate to form a multi-layered structure; semiconductor patterns on the substrate and extending through the insulation interlayer patterns and the control gate patterns in a vertical direction relative to the substrate; a tunnel oxide layer contacting at least a portion of a sidewall of the semiconductor patterns; a charge-trapping layer on the tunnel oxide layer; a blocking dielectric layer on the charge-trapping layer and conformally formed along inner sidewalls, upper surfaces and lower surfaces of the control gate patterns, the blocking dielectric layer extending in an extending direction of the control gate patterns; and a metal silicide pattern on each of the control gate patterns or on each of the semiconductor patterns.