Patent ID: 9426891
Filing Date: 2016-08-23
CPC Classification: H01L,H05K

Claim Text:
1. A semiconductor device substrate, comprising: a first dielectric layer comprising a body portion and a wall portion protruded from a first surface of the body portion, the wall portion having an end; a second dielectric layer having a first surface and an opposing second surface, the first surface of the second dielectric layer being adjacent to the first surface of the body portion, the second dielectric layer surrounding the wall portion, the end of the wall portion extending beyond the second surface of the second dielectric layer; an electronic component comprising a first electrical contact and a second electrical contact, at least a part of the electronic component being surrounded by the wall portion; a first patterned conductive layer embedded in the second surface of the second dielectric layer; and a second patterned conductive layer disposed on the second surface of the second dielectric layer and an exposed surface of the first patterned conductive layer, wherein the second patterned conductive layer is aligned with the first electrical contact, the second electrical contact and the end of the wall portion.