Patent ID: 9252142
Filing Date: 2016-02-02
CPC Classification: H01L

Claim Text:
1. A gate-last technique for forming an integrated circuit including a resistance element, the technique comprising: providing a semiconductor substrate including a shallow trench isolation structure disposed therein; patterning a dummy gate electrode structure overlying semiconductor material of the semiconductor substrate and a resistor structure overlying the shallow trench isolation structure, wherein the dummy gate electrode structure and the resistor structure comprise a dummy layer overlying a metal capping layer and a gate dielectric layer underlying the metal capping layer; forming an interlayer dielectric layer overlying the semiconductor substrate and the shallow trench isolation structure, between the dummy gate electrode structure and the resistor structure; concurrently patterning end terminal recesses for the resistance element through the dummy layer of the resistor structure and removing the dummy layer of the dummy gate electrode structure to form a gate electrode recess, wherein concurrently patterning the end terminal recesses and removing the dummy layer of the dummy gate electrode structure comprises masking a first region of the resistor structure with a first mask, wherein entire second regions of the resistor structure on either side of the first region remain unmasked and wherein portions of the interlayer dielectric layer adjacent to the second regions also remain unmasked; and depositing metal gate material in the end terminal recesses and the gate electrode recess to form end terminals for the resistance element and a gate electrode, respectively.