Patent ID: 9368189
Filing Date: 2016-06-14
CPC Classification: G11C,H03K

Claim Text:
1. A semiconductor device comprising: an output circuit having a plurality of unit buffer circuits, wherein an impedance of each unit buffer circuit of the plurality of unit buffer circuits is adjustable; a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits; and an impedance adjustment unit configured to adjust the impedance of each of the unit buffer circuits of the plurality of unit buffer circuits, wherein the impedance adjustment unit comprises a first power line, a replica circuit, and a load current generation circuit, and wherein the replica circuit and the load current generation circuit are coupled in common to the first power line, the replica circuit has a replica impedance that is substantially equal to the impedance of the output circuit, and the load current generation circuit changes current flowing therethrough in accordance with a number of the activated one or more unit buffer circuits of the plurality of unit buffer circuits, and wherein the load current generation circuit comprises a comparator having an output that is used to selectively change the current flowing through the load current generation circuit.