Patent ID: 9269786
Filing Date: 2016-02-23
CPC Classification: H01L

Claim Text:
1. An integrated semiconductor structure comprising: a field effect transistor (FET) having a metal gate adjacent to an interlayer dielectric (ILD) on top of a source and drain, the metal gate surrounded by a gate work function metal, the gate work function metal surrounded by a gate dielectric and the gate dielectric abutting to a sidewall spacer, an oxygen blocking layer above a planarized top surface of the metal gate and spanning across the gate dielectric, the ILD, the entire source and the entire drain, wherein the work function metal and the metal gate each have a top and wherein the gate dielectric further comprising a recess to a level below the top of the work function metal and below the top of the metal gate, the oxygen blocking layer fills the entire recess, and wherein the gate dielectric and the oxygen blocking layer comprise different materials, and a dielectric layer directly over the oxygen blocking layer, the gate dielectric and the ILD, the dielectric layer only in direct contact with the oxygen blocking layer.