Patent ID: 9305326
Filing Date: 2016-04-05
CPC Classification: G06T

Claim Text:
1. An apparatus for tile elimination in rendering, comprising: a front portion pipeline module, a tile-elimination module, a back portion pipeline module, all connected in a pipeline manner; the tile-elimination module further comprising: a tile engine, connected to the front portion pipeline module and to generate a list of arrays indicating the processing elements to be rendered on a tile basis; a signature value computation unit, connected to the front portion pipeline and the tile engine for computing each of a plurality of signature values corresponding to each of a plurality of signature types from the front portion pipeline module; a signature value repository, connected to the signature value computation unit for storing the signature values computed by the signature value computation unit; and a tile comparison unit, connected to the tile engine and the signature value repository for comparing signature values of a tile of the current frame and the same tile of a previous frame, and for accessing signature values of tiles stored in the signature value repository; the tile comparison unit also responsible for determining whether to eliminate the rendering of the tile in the current frame; the tile comparison unit being connected to the back portion pipeline and responsible for determining whether to proceed to render the tile or to copy the tile in the previous frame the back portion pipeline and eliminate the rendering of the tile.