Patent ID: 9519746
Filing Date: 2016-12-13
CPC Classification: G06F

Claim Text:
1. A computer implemented method for correcting early mode slack fails in an electronic circuit, comprising: generating a logical description of an electronic circuit having a first path from first circuit to a second circuit; compiling, by a processor, the logical description into a technology specific representation of the electronic circuit; determining, by a processor, that a second path in the technology specific representation of the electronic circuit corresponding with the first path has a first early mode slack fail at the second circuit, wherein an early mode slack fail results when an output of the first circuit coupled to an input of the second circuit has an early mode slack below a first threshold value; identifying, in response to the determining, a complex logic gate located in the second path and having an output coupled to the input of the second circuit, that can be decomposed into two or more logic gates; and decomposing, by a processor, the complex logic gate into a two or more logic gates to address the early mode slack fail, wherein an electrical signal propagating in the second path to the second circuit though the decomposed complex logic gate traverses at least one logic stage more than an electrical signal propagating in the second path to the second logic circuit though the complex logic gate.