Patent ID: 9355739
Filing Date: 2016-05-31
CPC Classification: G11C

Claim Text:
1. A bitline circuit controlling a charge trap comprises a MOSFET memory array coupled to a bitline and a source-line, wherein said bitline is mode-dependent pull-down circuit changes its circuit strength causing a greater current flow through said MOSFET memory array when coupled from said source-line to said bitline, activating said mode-dependent pull-down circuit when in Programming mode and limiting said current when in Read mode, said mode-dependent pull-down circuit comprising: a P-type MOS (PMOS) device having a source and drain coupled to a bitline high voltage (VBLH) and further connected to the bitline, and a first N-type MOS (NMOS) having said source and drain coupled to GROUND (GND), said drain connecting to said bitline, and a second NMOS having said source and drain coupled to GND and said drain further connected to said bitline, respectively, discharging said bitline to a first condition by turning on said first NMOS when in said Programming mode, and discharging to a second condition by turning on said second NMOS when in said Read mode, wherein said first NMOS device has a size greater than that of said second NMOS device.