Patent ID: 9336003
Filing Date: 2016-05-10
CPC Classification: G06F

Claim Text:
1. A processor comprising: a decode unit configured to decode instructions and generate a plurality of instruction operations; a plurality of reservation stations, each of the plurality of reservation stations coupled to a respective execution unit and configured to store instruction operations for issuance to the respective execution unit, wherein the plurality of reservation stations are configured to schedule the instruction operations for issuance responsive to availability of operands for the instruction operations; and a dispatch unit coupled to the decode unit, wherein the dispatch unit includes a plurality of dispatch buffers, each of the plurality of dispatch buffers coupled to two or more of the plurality of reservation stations, wherein each dispatch buffer of the plurality of dispatch buffers is configured to store instruction operations to be dispatched to the two or more of the plurality of reservation stations coupled to that dispatch buffer, wherein the dispatch unit is configured to allocate instruction operations to the plurality of dispatch buffers responsive to a relative fullness of the plurality of dispatch buffers with respect to each other, wherein at least a first instruction operation of the plurality of instruction operations is allocated to a least full dispatch buffer of the plurality of dispatch buffers, and wherein each dispatch buffer is configured to dispatch instruction operations to the two or more of the plurality of reservation stations responsive to a relative fullness of the two or more of the plurality of reservation stations with respect to each other, wherein at least a second instruction operation is dispatched to a least full reservation station of the two or more reservation stations.