Patent ID: 9484326
Filing Date: 2016-11-01
CPC Classification: G06F,G11C,H01L

Claim Text:
1. A semiconductor device comprising: a dice stack including a first die, a second die and a third die stacked in order, wherein each of the first, the second and the third dice includes: wherein the first through silicon via of the first die is electrically coupled to the second through silicon via of the second die, the second through silicon via of the first die is electrically coupled to the first through silicon via of the second die, the first through silicon via of the third die is electrically coupled to the second through silicon via of the second die, and the second through silicon via of the third die is electrically coupled to the first through silicon via of the second die, and wherein the first through silicon via and the second through silicon via interleave between the first die and the second die of the dice stack.