Patent ID: 9255966
Filing Date: 2016-02-09
CPC Classification: G01R,H04L

Claim Text:
1. A receiver circuit comprising: a clock data recovery circuit; a jitter generator configured to generate jitter having first characteristics which include a first frequency and a first amplitude of the jitter; a test pattern generator configured to generate a test pattern to which the jitter is added and to supply the test pattern to the clock data recovery circuit; a comparator configured to compare a value outputted from the clock data recovery circuit on the basis of the test pattern with an expected value and to output a comparison result; a jitter extractor configured to extract jitter from a clock recovered by the clock data recovery circuit; and a jitter characteristic detector configured to detect a second frequency and a second amplitude of the extracted jitter and to evaluate the second frequency and the second amplitude with the first frequency and the first amplitude of the jitter set by the jitter generator as expected values, wherein the jitter generator generates the jitter based on a first digital code which represents a first combination of the first frequency and the first amplitude of the jitter.