Patent ID: 9530505
Filing Date: 2016-12-27
CPC Classification: G11C

Claim Text:
1. An EEPROM memory cell gate control signal generating circuit, comprising: a high-voltage row decoding circuit and a plurality of word selection circuits; the high-voltage row decoding circuit comprises a first-part row decoding circuit composed of a first PMOS transistor and a second PMOS transistor, and a second-part row decoding circuit composed of a first NMOS transistor and a second NMOS transistor; the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor to output a first total wordline voltage, the gate of the first PMOS transistor is connected to a first control signal, the gate of the second PMOS transistor is connected to a second control signal, the source of the first PMOS transistor is connected to a third control signal, and the source of the second PMOS transistor is connected to a fourth control signal; the first total wordline voltage outputted by the first-part row decoding circuit is made to be one of an erasing positive voltage and levitation under the control of the first control signal, the second control signal, the third control signal and the fourth control signal; the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor to output a second total wordline voltage, the gate of the first NMOS transistor is connected to a fifth control signal, the gate of the second NMOS transistor is connected to a sixth control signal, the source of the first NMOS transistor is connected to a seventh control signal, and the source of the second NMOS transistor is connected to an eighth control signal; the second total wordline voltage outputted by the second-part row decoding circuit is made to be one of an erasing negative voltage and levitation under the control of the fifth control signal, the sixth control signal, the seventh control signal and the eighth control signal; the second total wordline voltage being levitated when the first total wordline voltage is the erasing positive voltage, the first total wordline voltage being levitated when the second total wordline voltage is the erasing negative voltage; a wordline of each memory cell of EEPROM is connected to one of the word selection circuits, which are the same in structure, with each of the word selection circuits including a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; the drain of the third PMOS transistor, the drain of the third NMOS transistor and the drain of the fourth NMOS transistor are connected together to output a wordline voltage, which is inputted into a wordline of the corresponding memory cell; the source of the third PMOS transistor is connected to the first total wordline voltage, the source of the third NMOS transistor is connected to the second total wordline voltage, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fifth NMOS transistor is grounded; and the gate of the third PMOS transistor is connected to a ninth control signal, the gate of the third NMOS transistor is connected to a tenth control signal, the gate of the fourth NMOS transistor is connected to a working voltage, and the gate of the fifth NMOS transistor is connected to an eleventh control signal; the wordline voltage is made to output one of the erasing negative voltage, erasing positive voltage and ground under the control of the ninth control signal, the tenth control signal and the eleventh control signal.