Patent ID: 9276058
Filing Date: 2016-03-01
CPC Classification: H01L

Claim Text:
1. A method of manufacturing a semiconductor device, the method comprising: forming a first mold layer on a substrate, the substrate including conductive regions; forming a plurality of first supporting layer patterns on the first mold layer, the first supporting layer patterns extending in a first direction and being spaced apart from each other by a first width; forming a second mold layer covering the first supporting layer patterns on the first mold layer; forming a plurality of second supporting layer patterns on the second mold layer, the second supporting layer patterns extending in a second direction perpendicular to the first direction and being spaced apart from each other by a second width; forming a third mold layer covering the second supporting layer patterns on the second mold layer; partially etching the third mold layer, the second mold layer and the first mold layer to form a plurality of openings, the openings exposing the conductive region; and forming lower electrodes on inner walls of the openings, the lower electrodes being in contact with the conductive region.