Patent ID: 9384318
Filing Date: 2016-07-05
CPC Classification: G03F,G06F

Claim Text:
1. A method of fabricating a semiconductor device, comprising: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio; determining an area of a hole of the patterning layer or an area of a vertical integration access feature of the patterning layer, wherein the estimating a penetration ratio is based on determining whether to select a predefined penetration ratio or to initiate a calculation of the penetration ratio, and the determining of whether to select a predefined penetration ratio or to initiate a calculation of the penetration ratio is based on the area of a hole or area of a vertical integration access feature; and fabricating the semiconductor device with the circuit design corrected by the compensation metric.