Patent ID: 9317451
Filing Date: 2016-04-19
CPC Classification: G06F,G09C,H04L

Claim Text:
1. A nonvolatile semiconductor storage device comprising: an encrypting circuit to execute an operation of a predetermined encrypting system, a memory cell array preliminarily storing complementary data to be used in the operation, a page buffer comprising a first region for storing the data being read out from the memory cell array, and a second region used at the time of execution of the operation, a register to store the data from the first region, and supplying the stored data into the second region, an inspection circuit to judge presence or absence of error in the data when storing the data into the register, and store the data into the register when the data is judged to be free from error, a control circuit to control reading out of the data from the memory cell array into the first region, and reading out of the data from the first region into the second region, and an address control circuit to designate an address of the page buffer or the memory cell array, based on a signal supplied from the control circuit, wherein the control circuit controls the address control circuit, and supplies the data from the first region into the second region, and when the inspection circuit detects an error in the data, it is notified to the address control circuit, and the address control circuit receives the notice, and designates other address in which data of same contents as the data in the page buffer is stored, and thereby the inspection circuit judges presence or absence of error in the data in the other address.