Patent ID: 9367497
Filing Date: 2016-06-14
CPC Classification: G06F,Y02D

Claim Text:
1. A method for dynamically reconfiguring a hierarchical relationship between one or more cores of a multi-core microprocessor comprising a system bus connected to a chipset, a plurality of cores, and sideband communication wires that are distinct from the system bus, the sideband communication wires facilitating non-system-bus inter-core communications, wherein at least some of the cores are operable to be reconfigurably designated as a master core, the method comprising: determining an initial hierarchical configuration of the cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core; and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from the at least one core initially so designated, and assigns a master designation to a core not initially so designated; wherein each core is configured to conditionally drive an output on a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.