Patent ID: 9287160
Filing Date: 2016-03-15
CPC Classification: H01L

Claim Text:
1. A method of fabricating a semiconductor device, comprising: patterning a substrate to form a plurality of first trenches defining a plurality of line patterns; forming a plurality of device isolation patterns in the plurality of first trenches, each of the plurality of device isolation patterns including a first device isolation pattern and a second device isolation pattern; patterning the plurality of line patterns and the plurality of device isolation patterns so as to form a plurality of second trenches extending across the plurality of first trenches and so as to define a plurality of active portions; forming a plurality of gate patterns in the plurality of second trenches, each of the plurality of gate patterns including a gate insulating layer, a gate line and a gate capping pattern; recessing at least one of the first device isolation pattern and the gate insulating layer so as to expose upper side surfaces of the plurality of active portions; forming a metal layer covering the exposed upper side surfaces of the plurality of active portions; and reacting the metal layer with the substrate to form a plurality of ohmic patterns on the plurality of active portions.