Patent ID: 9419642
Filing Date: 2016-08-16
CPC Classification: H03M

Claim Text:
1. A delta-sigma modulator having a dual quantizer architecture for processing an analog input signal and generating a digital output signal representing the analog input signal at a digital output, the delta-sigma modulator comprising: a loop filter for processing an error between the analog input signal to the delta-sigma modulator and a feedback signal from a feedback digital-to-analog converter (DAC); a first analog-to-digital converter (ADC) for digitizing an output of the loop filter of the delta-sigma modulator at a first sampling rate; and a second ADC for digitizing the analog input signal to the delta-sigma modulator at a second sampling rate different from the first sampling rate; wherein a quantization noise of the second ADC is cancelled at the digital output of the delta-sigma modulator.