Patent ID: 9299568
Filing Date: 2016-03-29
CPC Classification: H01L

Claim Text:
1. A method of fabricating a nonvolatile trapped-charge memory device, comprising: forming a channel region in a substrate, the channel region electrically connecting a source region and a drain region in the substrate, wherein the channel region comprises polysilicon; forming a tunneling layer on the substrate over the channel region, wherein forming the tunneling layer comprises oxidizing the substrate to form an oxide film and nitridizing the oxide film; forming a multi-layer charge trapping layer comprising an oxygen-rich first layer on the tunneling layer and an oxygen-lean second layer over the first layer; and forming a blocking layer on the multi-layer charge trapping layer, wherein forming the multi-layer charge trapping layer further comprises forming an anti-tunneling layer comprising an oxide separating the first layer from the second layer.