Patent ID: 9488998
Filing Date: 2016-11-08
CPC Classification: G05F,G06F,Y02D

Claim Text:
1. An integrated circuit device comprising: first and second processor cores configured to perform a respective first and second set of functional processing; a core-specific process state monitor associated with the first processor core; a core-specific process state monitor associated with the second processor core; a core-specific aging monitor associated with the first processor core; a core-specific aging monitor associated with the second processor core; a power management unit; a clock generation unit; a control system configured to individually control operating points of the first and second processor cores and workload in response to feedback from the core-specific process state monitors and from the core-specific aging monitors; wherein the control system comprises a workload scheduler configured to control the distribution of workload amongst the first and second processor cores based on a relative performance amongst the first and second processor cores as indicated by the feedback from at least one of the core-specific process state monitors and the core-specific aging monitors, wherein controlling the distribution of workload amongst the first and second processor cores comprises controlling how the execution of instructions by the first and second processors is distributed amongst the first and second processor cores.