Patent ID: 9239801
Filing Date: 2016-01-19
CPC Classification: G06F

Claim Text:
1. A processing system, comprising: a lower stack bound register for at least one of: a 32-bit user mode, a 64-bit user mode, or a supervisor mode, for storing a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register for at least one of: the 32-bit user mode, the 64-bit user mode, or the supervisor mode, for storing a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address; wherein the processing system is to operate in at least one of: the 32-bit user mode, the 64-bit user mode, or the supervisor mode.