Patent ID: 9312032
Filing Date: 2016-04-12
CPC Classification: G11C

Claim Text:
1. A semiconductor memory apparatus comprising: a main memory area comprising a plurality of banks; one or more redundancy memory areas; a plurality of global data lines configured to exchange data of respective banks with the outside; a main page buffer coupled to the main memory area; redundancy page buffers coupled to respective redundancy memory areas; and a controller configured to control a redundancy program mode in which, as a program command, an access address, and data are provided, the data is inputted to the main page buffer, and the data of the main page buffer is transferred to a corresponding redundancy page buffer when the main memory area is repaired, wherein one or more of the global data lines comprise a common global data line which is commonly shared by the redundancy memory areas and the main memory area; and wherein the controller sets the main page buffer in a program-inhibited state, after the data of the main page buffer is transferred to the corresponding redundancy page buffer.