Patent ID: 9330011
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. A method performed by a microprocessor to prevent execution of a shellcode, the microprocessor having an instruction cache and a hardware state machine, the method comprising: detecting, by the hardware state machine, a no operation (NOP) slide by counting a continuous sequence of NOP instructions within an unmodified stream of instructions fetched from the instruction cache, wherein an unmodified stream of instructions is one in which no additional instructions are inserted into the stream from a time in which the instructions are fetched to a time in which the hardware state machine counts the continuous sequence of NOP instructions; and responding to detecting the NOP slide by suspending execution of the stream of instructions, including any non-NOP instruction immediately following the NOP slide; wherein when the NOP slide leads to a shellcode, the suspension of execution of the stream of instructions prevents execution of the shellcode.