Patent ID: 9466573
Filing Date: 2016-10-11
CPC Classification: H01L

Claim Text:
1. A method of manufacturing an integrated circuit, the method comprising: providing a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer; forming a protective layer on the second semiconductor substrate; forming a plurality of shallow trench isolations through the protective layer and the second semiconductor substrate; forming a plurality of via holes through the shallow trench isolations and the insulating layer, the via holes extending into a portion of the first semiconductor substrate; selectively removing a portion of the first semiconductor substrate disposed between the via holes to form a continuous cavity area; filling the via holes with a dielectric material and performing a chemical mechanical polishing process to remove excess of the dielectric material to form a plurality of isolation plugs dividing the continuous cavity area into a plurality of separate cavities; removing a portion of the shallow trench isolations and a portion of the isolation plugs higher than the second semiconductor substrate and the protective layer; and forming a transistor within a portion of the second semiconductor substrate disposed between two adjacent shallow trench isolations.