Patent ID: 9304403
Filing Date: 2016-04-05
CPC Classification: G03F

Claim Text:
1. A method, comprising: providing an integrated circuit (IC) substrate having a first alignment mark, a second alignment mark, and a first circuit pattern defined in a first pattern layer and a third alignment mark, a fourth alignment mark, and a second circuit pattern defined in a second pattern layer; illuminating the first and second alignment marks, through a photomask, with a first light to determine a first layer alignment error including a first alignment error in relation to the first alignment mark and a second alignment error in relation to the second alignment mark, wherein the first alignment error has more weight than the second alignment error; illuminating the third and fourth alignment marks, through the photomask, with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to fourth alignment mark, wherein the third alignment error has more weight than the fourth alignment error; determining a collective alignment error including the first layer alignment error in relation to the first circuit pattern and the second layer alignment error in relation to the second circuit pattern; and adjusting alignment between the IC substrate and the photomask to minimize the collective alignment error.