Patent ID: 9397069
Filing Date: 2016-07-19
CPC Classification: H01L

Claim Text:
1. A semiconductor package, comprising: a semiconductor die surrounded by an encapsulating material within a substrate; a plurality of first capture pads aligned with an actual position of the semiconductor die; a plurality of second capture pads in which each of the plurality of second capture is partially disposed over a corresponding first capture pad of the plurality of first capture pads, the plurality of second capture pads being aligned with an outline of the semiconductor package; a plurality of overlap areas defined by a plurality of footprints common to corresponding footprints of the plurality of first capture pads and the plurality of second capture pads; and a plurality of conductive vias extending between, and coupled to, the plurality of first capture pads and the plurality of second capture pads, the plurality of conductive vias comprising modified sizes or shapes that are substantially equal to sizes or shapes of the plurality of overlap areas, the modified sizes or shapes of the plurality of conductive vias accounting for a misalignment between the semiconductor die and the outline of the semiconductor package.