Patent ID: 9442512
Filing Date: 2016-09-13
CPC Classification: G06F,Y02D

Claim Text:
1. A method of interface clock frequency switching control in a computer system, the method comprising: determining, by a controller, a first clock delay adjustment of a clock signal on a clock line of an interface of the computer system operated at a first clock frequency; changing the clock signal on the clock line from the first clock frequency to a second clock frequency; determining, by the controller, a second clock delay adjustment of the clock signal on the clock line of the interface operated at the second clock frequency; computing, by the controller, an insertion delay between the clock signal and a data signal of the interface based on the first clock delay adjustment, the first clock frequency, the second clock delay adjustment, and the second clock frequency; periodically updating the second clock delay adjustment and the insertion delay while operating the clock signal at the second clock frequency and prior to changing the clock signal from the second clock frequency to a third clock frequency; computing, by the controller, a third clock delay adjustment of the clock signal to operate the clock line of the interface at the third clock frequency based on the insertion delay and a relative difference between the third clock frequency and the second clock frequency; and adjusting the clock signal based on the third clock delay adjustment to align timing of the clock signal with the data signal at the third clock frequency.