Patent ID: 9329994
Filing Date: 2016-05-03
CPC Classification: G06F

Claim Text:
1. A memory system comprising: a first memory that includes a plurality of first blocks to which data is written from the outside, erasing being performed for each first block; a second memory that stores a first table in which a plurality of first correspondences between a logical address and a physical address of a writing position of the data is described; a third memory that has a higher processing speed than the second memory and stores a second table in which second correspondences are described, the second correspondences being parts of the first correspondences; and a memory controller that preferentially uses the second table over the first table to acquire a physical address of an access destination when accessing the first memory in response to a request from the outside, wherein the memory controller determines whether data in a second block is first data to be copied, using the first table, not the second table, the second block is a written block among the plurality of first blocks, the memory controller copies the first data from the second block to a third block to copy all data in a first state in the second block to the third block, and the third block is a writable block among the plurality of first blocks, and the memory controller sets all data in the second block to a second state.