Patent ID: 9231106
Filing Date: 2016-01-05
CPC Classification: H01L

Claim Text:
1. A semiconductor device comprising: a first semiconductor fin extending above a substrate; a first source region on the first semiconductor fin, the first source region having a first width; a first drain region on the first semiconductor fin, the first drain region having a second width, the second width being different than the first width; a first channel region in the first semiconductor fin interposed between the first source region and the first drain region, the first channel region being doped with impurities of a first conductivity type; a first active gate on a top surface and sidewalls of the first channel region in the first semiconductor fin, the first active gate being interposed between the first source region and the first drain region; a first dummy gate on the top surface and sidewalls of the first semiconductor fin, the first dummy gate being on a first end of the first semiconductor fin adjacent the first source region; and a second dummy gate on the top surface and sidewalls of the first semiconductor fin, the second dummy gate being on a second end of the first semiconductor fin adjacent the first drain region, the second end of the first semiconductor fin being opposite the first end.